	.file	"76526.c"
	.intel_syntax noprefix
	.text
	.globl	__VERIFIER_nondet_bool
	.type	__VERIFIER_nondet_bool, @function
__VERIFIER_nondet_bool:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	call	__VERIFIER_nondet_int@PLT
	test	eax, eax
	setne	al
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.globl	t13_l1
	.bss
	.type	t13_l1, @object
	.size	t13_l1, 1
t13_l1:
	.zero	1
	.globl	_x_t13_l1
	.type	_x_t13_l1, @object
	.size	_x_t13_l1, 1
_x_t13_l1:
	.zero	1
	.globl	t13_l0
	.type	t13_l0, @object
	.size	t13_l0, 1
t13_l0:
	.zero	1
	.globl	_x_t13_l0
	.type	_x_t13_l0, @object
	.size	_x_t13_l0, 1
_x_t13_l0:
	.zero	1
	.globl	t13_evt1
	.type	t13_evt1, @object
	.size	t13_evt1, 1
t13_evt1:
	.zero	1
	.globl	_x_t13_evt1
	.type	_x_t13_evt1, @object
	.size	_x_t13_evt1, 1
_x_t13_evt1:
	.zero	1
	.globl	t13_evt0
	.type	t13_evt0, @object
	.size	t13_evt0, 1
t13_evt0:
	.zero	1
	.globl	_x_t13_evt0
	.type	_x_t13_evt0, @object
	.size	_x_t13_evt0, 1
_x_t13_evt0:
	.zero	1
	.globl	t13_x
	.align 4
	.type	t13_x, @object
	.size	t13_x, 4
t13_x:
	.zero	4
	.globl	_x_t13_x
	.align 4
	.type	_x_t13_x, @object
	.size	_x_t13_x, 4
_x_t13_x:
	.zero	4
	.globl	t12_l1
	.type	t12_l1, @object
	.size	t12_l1, 1
t12_l1:
	.zero	1
	.globl	_x_t12_l1
	.type	_x_t12_l1, @object
	.size	_x_t12_l1, 1
_x_t12_l1:
	.zero	1
	.globl	t12_l0
	.type	t12_l0, @object
	.size	t12_l0, 1
t12_l0:
	.zero	1
	.globl	_x_t12_l0
	.type	_x_t12_l0, @object
	.size	_x_t12_l0, 1
_x_t12_l0:
	.zero	1
	.globl	t12_evt1
	.type	t12_evt1, @object
	.size	t12_evt1, 1
t12_evt1:
	.zero	1
	.globl	_x_t12_evt1
	.type	_x_t12_evt1, @object
	.size	_x_t12_evt1, 1
_x_t12_evt1:
	.zero	1
	.globl	t12_evt0
	.type	t12_evt0, @object
	.size	t12_evt0, 1
t12_evt0:
	.zero	1
	.globl	_x_t12_evt0
	.type	_x_t12_evt0, @object
	.size	_x_t12_evt0, 1
_x_t12_evt0:
	.zero	1
	.globl	t12_x
	.align 4
	.type	t12_x, @object
	.size	t12_x, 4
t12_x:
	.zero	4
	.globl	_x_t12_x
	.align 4
	.type	_x_t12_x, @object
	.size	_x_t12_x, 4
_x_t12_x:
	.zero	4
	.globl	t11_l1
	.type	t11_l1, @object
	.size	t11_l1, 1
t11_l1:
	.zero	1
	.globl	_x_t11_l1
	.type	_x_t11_l1, @object
	.size	_x_t11_l1, 1
_x_t11_l1:
	.zero	1
	.globl	t11_l0
	.type	t11_l0, @object
	.size	t11_l0, 1
t11_l0:
	.zero	1
	.globl	_x_t11_l0
	.type	_x_t11_l0, @object
	.size	_x_t11_l0, 1
_x_t11_l0:
	.zero	1
	.globl	t11_evt1
	.type	t11_evt1, @object
	.size	t11_evt1, 1
t11_evt1:
	.zero	1
	.globl	_x_t11_evt1
	.type	_x_t11_evt1, @object
	.size	_x_t11_evt1, 1
_x_t11_evt1:
	.zero	1
	.globl	t11_evt0
	.type	t11_evt0, @object
	.size	t11_evt0, 1
t11_evt0:
	.zero	1
	.globl	_x_t11_evt0
	.type	_x_t11_evt0, @object
	.size	_x_t11_evt0, 1
_x_t11_evt0:
	.zero	1
	.globl	t11_x
	.align 4
	.type	t11_x, @object
	.size	t11_x, 4
t11_x:
	.zero	4
	.globl	_x_t11_x
	.align 4
	.type	_x_t11_x, @object
	.size	_x_t11_x, 4
_x_t11_x:
	.zero	4
	.globl	t10_evt1
	.type	t10_evt1, @object
	.size	t10_evt1, 1
t10_evt1:
	.zero	1
	.globl	_x_t10_evt1
	.type	_x_t10_evt1, @object
	.size	_x_t10_evt1, 1
_x_t10_evt1:
	.zero	1
	.globl	t10_evt0
	.type	t10_evt0, @object
	.size	t10_evt0, 1
t10_evt0:
	.zero	1
	.globl	_x_t10_evt0
	.type	_x_t10_evt0, @object
	.size	_x_t10_evt0, 1
_x_t10_evt0:
	.zero	1
	.globl	t10_x
	.align 4
	.type	t10_x, @object
	.size	t10_x, 4
t10_x:
	.zero	4
	.globl	_x_t10_x
	.align 4
	.type	_x_t10_x, @object
	.size	_x_t10_x, 4
_x_t10_x:
	.zero	4
	.globl	t9_l1
	.type	t9_l1, @object
	.size	t9_l1, 1
t9_l1:
	.zero	1
	.globl	_x_t9_l1
	.type	_x_t9_l1, @object
	.size	_x_t9_l1, 1
_x_t9_l1:
	.zero	1
	.globl	t9_l0
	.type	t9_l0, @object
	.size	t9_l0, 1
t9_l0:
	.zero	1
	.globl	_x_t9_l0
	.type	_x_t9_l0, @object
	.size	_x_t9_l0, 1
_x_t9_l0:
	.zero	1
	.globl	t9_evt1
	.type	t9_evt1, @object
	.size	t9_evt1, 1
t9_evt1:
	.zero	1
	.globl	_x_t9_evt1
	.type	_x_t9_evt1, @object
	.size	_x_t9_evt1, 1
_x_t9_evt1:
	.zero	1
	.globl	t9_evt0
	.type	t9_evt0, @object
	.size	t9_evt0, 1
t9_evt0:
	.zero	1
	.globl	_x_t9_evt0
	.type	_x_t9_evt0, @object
	.size	_x_t9_evt0, 1
_x_t9_evt0:
	.zero	1
	.globl	t3_x
	.align 4
	.type	t3_x, @object
	.size	t3_x, 4
t3_x:
	.zero	4
	.globl	_x_t3_x
	.align 4
	.type	_x_t3_x, @object
	.size	_x_t3_x, 4
_x_t3_x:
	.zero	4
	.globl	t2_evt1
	.type	t2_evt1, @object
	.size	t2_evt1, 1
t2_evt1:
	.zero	1
	.globl	_x_t2_evt1
	.type	_x_t2_evt1, @object
	.size	_x_t2_evt1, 1
_x_t2_evt1:
	.zero	1
	.globl	controller_l1
	.type	controller_l1, @object
	.size	controller_l1, 1
controller_l1:
	.zero	1
	.globl	_x_controller_l1
	.type	_x_controller_l1, @object
	.size	_x_controller_l1, 1
_x_controller_l1:
	.zero	1
	.globl	t2_l0
	.type	t2_l0, @object
	.size	t2_l0, 1
t2_l0:
	.zero	1
	.globl	_x_t2_l0
	.type	_x_t2_l0, @object
	.size	_x_t2_l0, 1
_x_t2_l0:
	.zero	1
	.globl	t2_evt0
	.type	t2_evt0, @object
	.size	t2_evt0, 1
t2_evt0:
	.zero	1
	.globl	_x_t2_evt0
	.type	_x_t2_evt0, @object
	.size	_x_t2_evt0, 1
_x_t2_evt0:
	.zero	1
	.globl	t1_l1
	.type	t1_l1, @object
	.size	t1_l1, 1
t1_l1:
	.zero	1
	.globl	_x_t1_l1
	.type	_x_t1_l1, @object
	.size	_x_t1_l1, 1
_x_t1_l1:
	.zero	1
	.globl	controller_l0
	.type	controller_l0, @object
	.size	controller_l0, 1
controller_l0:
	.zero	1
	.globl	_x_controller_l0
	.type	_x_controller_l0, @object
	.size	_x_controller_l0, 1
_x_controller_l0:
	.zero	1
	.globl	t2_x
	.align 4
	.type	t2_x, @object
	.size	t2_x, 4
t2_x:
	.zero	4
	.globl	_x_t2_x
	.align 4
	.type	_x_t2_x, @object
	.size	_x_t2_x, 4
_x_t2_x:
	.zero	4
	.globl	t1_evt1
	.type	t1_evt1, @object
	.size	t1_evt1, 1
t1_evt1:
	.zero	1
	.globl	_x_t1_evt1
	.type	_x_t1_evt1, @object
	.size	_x_t1_evt1, 1
_x_t1_evt1:
	.zero	1
	.globl	controller_evt0
	.type	controller_evt0, @object
	.size	controller_evt0, 1
controller_evt0:
	.zero	1
	.globl	_x_controller_evt0
	.type	_x_controller_evt0, @object
	.size	_x_controller_evt0, 1
_x_controller_evt0:
	.zero	1
	.globl	t1_l0
	.type	t1_l0, @object
	.size	t1_l0, 1
t1_l0:
	.zero	1
	.globl	_x_t1_l0
	.type	_x_t1_l0, @object
	.size	_x_t1_l0, 1
_x_t1_l0:
	.zero	1
	.globl	t1_x
	.align 4
	.type	t1_x, @object
	.size	t1_x, 4
t1_x:
	.zero	4
	.globl	_x_t1_x
	.align 4
	.type	_x_t1_x, @object
	.size	_x_t1_x, 4
_x_t1_x:
	.zero	4
	.globl	t2_l1
	.type	t2_l1, @object
	.size	t2_l1, 1
t2_l1:
	.zero	1
	.globl	_x_t2_l1
	.type	_x_t2_l1, @object
	.size	_x_t2_l1, 1
_x_t2_l1:
	.zero	1
	.globl	t3_evt0
	.type	t3_evt0, @object
	.size	t3_evt0, 1
t3_evt0:
	.zero	1
	.globl	_x_t3_evt0
	.type	_x_t3_evt0, @object
	.size	_x_t3_evt0, 1
_x_t3_evt0:
	.zero	1
	.globl	delta
	.align 4
	.type	delta, @object
	.size	delta, 4
delta:
	.zero	4
	.globl	_x_delta
	.align 4
	.type	_x_delta, @object
	.size	_x_delta, 4
_x_delta:
	.zero	4
	.globl	t0_evt0
	.type	t0_evt0, @object
	.size	t0_evt0, 1
t0_evt0:
	.zero	1
	.globl	_x_t0_evt0
	.type	_x_t0_evt0, @object
	.size	_x_t0_evt0, 1
_x_t0_evt0:
	.zero	1
	.globl	gate_l0
	.type	gate_l0, @object
	.size	gate_l0, 1
gate_l0:
	.zero	1
	.globl	_x_gate_l0
	.type	_x_gate_l0, @object
	.size	_x_gate_l0, 1
_x_gate_l0:
	.zero	1
	.globl	t5_l0
	.type	t5_l0, @object
	.size	t5_l0, 1
t5_l0:
	.zero	1
	.globl	_x_t5_l0
	.type	_x_t5_l0, @object
	.size	_x_t5_l0, 1
_x_t5_l0:
	.zero	1
	.globl	t0_evt1
	.type	t0_evt1, @object
	.size	t0_evt1, 1
t0_evt1:
	.zero	1
	.globl	_x_t0_evt1
	.type	_x_t0_evt1, @object
	.size	_x_t0_evt1, 1
_x_t0_evt1:
	.zero	1
	.globl	gate_l1
	.type	gate_l1, @object
	.size	gate_l1, 1
gate_l1:
	.zero	1
	.globl	_x_gate_l1
	.type	_x_gate_l1, @object
	.size	_x_gate_l1, 1
_x_gate_l1:
	.zero	1
	.globl	t5_l1
	.type	t5_l1, @object
	.size	t5_l1, 1
t5_l1:
	.zero	1
	.globl	_x_t5_l1
	.type	_x_t5_l1, @object
	.size	_x_t5_l1, 1
_x_t5_l1:
	.zero	1
	.globl	t6_evt0
	.type	t6_evt0, @object
	.size	t6_evt0, 1
t6_evt0:
	.zero	1
	.globl	_x_t6_evt0
	.type	_x_t6_evt0, @object
	.size	_x_t6_evt0, 1
_x_t6_evt0:
	.zero	1
	.globl	gate_y
	.align 4
	.type	gate_y, @object
	.size	gate_y, 4
gate_y:
	.zero	4
	.globl	_x_gate_y
	.align 4
	.type	_x_gate_y, @object
	.size	_x_gate_y, 4
_x_gate_y:
	.zero	4
	.globl	t4_evt1
	.type	t4_evt1, @object
	.size	t4_evt1, 1
t4_evt1:
	.zero	1
	.globl	_x_t4_evt1
	.type	_x_t4_evt1, @object
	.size	_x_t4_evt1, 1
_x_t4_evt1:
	.zero	1
	.globl	t5_x
	.align 4
	.type	t5_x, @object
	.size	t5_x, 4
t5_x:
	.zero	4
	.globl	_x_t5_x
	.align 4
	.type	_x_t5_x, @object
	.size	_x_t5_x, 4
_x_t5_x:
	.zero	4
	.globl	t4_l1
	.type	t4_l1, @object
	.size	t4_l1, 1
t4_l1:
	.zero	1
	.globl	_x_t4_l1
	.type	_x_t4_l1, @object
	.size	_x_t4_l1, 1
_x_t4_l1:
	.zero	1
	.globl	t5_evt0
	.type	t5_evt0, @object
	.size	t5_evt0, 1
t5_evt0:
	.zero	1
	.globl	_x_t5_evt0
	.type	_x_t5_evt0, @object
	.size	_x_t5_evt0, 1
_x_t5_evt0:
	.zero	1
	.globl	t0_l0
	.type	t0_l0, @object
	.size	t0_l0, 1
t0_l0:
	.zero	1
	.globl	_x_t0_l0
	.type	_x_t0_l0, @object
	.size	_x_t0_l0, 1
_x_t0_l0:
	.zero	1
	.globl	t0_l1
	.type	t0_l1, @object
	.size	t0_l1, 1
t0_l1:
	.zero	1
	.globl	_x_t0_l1
	.type	_x_t0_l1, @object
	.size	_x_t0_l1, 1
_x_t0_l1:
	.zero	1
	.globl	t1_evt0
	.type	t1_evt0, @object
	.size	t1_evt0, 1
t1_evt0:
	.zero	1
	.globl	_x_t1_evt0
	.type	_x_t1_evt0, @object
	.size	_x_t1_evt0, 1
_x_t1_evt0:
	.zero	1
	.globl	t10_l0
	.type	t10_l0, @object
	.size	t10_l0, 1
t10_l0:
	.zero	1
	.globl	_x_t10_l0
	.type	_x_t10_l0, @object
	.size	_x_t10_l0, 1
_x_t10_l0:
	.zero	1
	.globl	controller_evt1
	.type	controller_evt1, @object
	.size	controller_evt1, 1
controller_evt1:
	.zero	1
	.globl	_x_controller_evt1
	.type	_x_controller_evt1, @object
	.size	_x_controller_evt1, 1
_x_controller_evt1:
	.zero	1
	.globl	t8_l0
	.type	t8_l0, @object
	.size	t8_l0, 1
t8_l0:
	.zero	1
	.globl	_x_t8_l0
	.type	_x_t8_l0, @object
	.size	_x_t8_l0, 1
_x_t8_l0:
	.zero	1
	.globl	gate_evt1
	.type	gate_evt1, @object
	.size	gate_evt1, 1
gate_evt1:
	.zero	1
	.globl	_x_gate_evt1
	.type	_x_gate_evt1, @object
	.size	_x_gate_evt1, 1
_x_gate_evt1:
	.zero	1
	.globl	t5_evt1
	.type	t5_evt1, @object
	.size	t5_evt1, 1
t5_evt1:
	.zero	1
	.globl	_x_t5_evt1
	.type	_x_t5_evt1, @object
	.size	_x_t5_evt1, 1
_x_t5_evt1:
	.zero	1
	.globl	t6_x
	.align 4
	.type	t6_x, @object
	.size	t6_x, 4
t6_x:
	.zero	4
	.globl	_x_t6_x
	.align 4
	.type	_x_t6_x, @object
	.size	_x_t6_x, 4
_x_t6_x:
	.zero	4
	.globl	controller_z
	.align 4
	.type	controller_z, @object
	.size	controller_z, 4
controller_z:
	.zero	4
	.globl	_x_controller_z
	.align 4
	.type	_x_controller_z, @object
	.size	_x_controller_z, 4
_x_controller_z:
	.zero	4
	.globl	t6_l0
	.type	t6_l0, @object
	.size	t6_l0, 1
t6_l0:
	.zero	1
	.globl	_x_t6_l0
	.type	_x_t6_l0, @object
	.size	_x_t6_l0, 1
_x_t6_l0:
	.zero	1
	.globl	t10_l1
	.type	t10_l1, @object
	.size	t10_l1, 1
t10_l1:
	.zero	1
	.globl	_x_t10_l1
	.type	_x_t10_l1, @object
	.size	_x_t10_l1, 1
_x_t10_l1:
	.zero	1
	.globl	controller_evt2
	.type	controller_evt2, @object
	.size	controller_evt2, 1
controller_evt2:
	.zero	1
	.globl	_x_controller_evt2
	.type	_x_controller_evt2, @object
	.size	_x_controller_evt2, 1
_x_controller_evt2:
	.zero	1
	.globl	t8_l1
	.type	t8_l1, @object
	.size	t8_l1, 1
t8_l1:
	.zero	1
	.globl	_x_t8_l1
	.type	_x_t8_l1, @object
	.size	_x_t8_l1, 1
_x_t8_l1:
	.zero	1
	.globl	gate_evt0
	.type	gate_evt0, @object
	.size	gate_evt0, 1
gate_evt0:
	.zero	1
	.globl	_x_gate_evt0
	.type	_x_gate_evt0, @object
	.size	_x_gate_evt0, 1
_x_gate_evt0:
	.zero	1
	.globl	t0_x
	.align 4
	.type	t0_x, @object
	.size	t0_x, 4
t0_x:
	.zero	4
	.globl	_x_t0_x
	.align 4
	.type	_x_t0_x, @object
	.size	_x_t0_x, 4
_x_t0_x:
	.zero	4
	.globl	controller_cnt
	.align 4
	.type	controller_cnt, @object
	.size	controller_cnt, 4
controller_cnt:
	.zero	4
	.globl	_x_controller_cnt
	.align 4
	.type	_x_controller_cnt, @object
	.size	_x_controller_cnt, 4
_x_controller_cnt:
	.zero	4
	.globl	t6_l1
	.type	t6_l1, @object
	.size	t6_l1, 1
t6_l1:
	.zero	1
	.globl	_x_t6_l1
	.type	_x_t6_l1, @object
	.size	_x_t6_l1, 1
_x_t6_l1:
	.zero	1
	.globl	t7_evt0
	.type	t7_evt0, @object
	.size	t7_evt0, 1
t7_evt0:
	.zero	1
	.globl	_x_t7_evt0
	.type	_x_t7_evt0, @object
	.size	_x_t7_evt0, 1
_x_t7_evt0:
	.zero	1
	.globl	t3_evt1
	.type	t3_evt1, @object
	.size	t3_evt1, 1
t3_evt1:
	.zero	1
	.globl	_x_t3_evt1
	.type	_x_t3_evt1, @object
	.size	_x_t3_evt1, 1
_x_t3_evt1:
	.zero	1
	.globl	t4_x
	.align 4
	.type	t4_x, @object
	.size	t4_x, 4
t4_x:
	.zero	4
	.globl	_x_t4_x
	.align 4
	.type	_x_t4_x, @object
	.size	_x_t4_x, 4
_x_t4_x:
	.zero	4
	.globl	_diverge_delta
	.align 4
	.type	_diverge_delta, @object
	.size	_diverge_delta, 4
_diverge_delta:
	.zero	4
	.globl	_x__diverge_delta
	.align 4
	.type	_x__diverge_delta, @object
	.size	_x__diverge_delta, 4
_x__diverge_delta:
	.zero	4
	.globl	t3_l0
	.type	t3_l0, @object
	.size	t3_l0, 1
t3_l0:
	.zero	1
	.globl	_x_t3_l0
	.type	_x_t3_l0, @object
	.size	_x_t3_l0, 1
_x_t3_l0:
	.zero	1
	.globl	t3_l1
	.type	t3_l1, @object
	.size	t3_l1, 1
t3_l1:
	.zero	1
	.globl	_x_t3_l1
	.type	_x_t3_l1, @object
	.size	_x_t3_l1, 1
_x_t3_l1:
	.zero	1
	.globl	t4_evt0
	.type	t4_evt0, @object
	.size	t4_evt0, 1
t4_evt0:
	.zero	1
	.globl	_x_t4_evt0
	.type	_x_t4_evt0, @object
	.size	_x_t4_evt0, 1
_x_t4_evt0:
	.zero	1
	.globl	t4_l0
	.type	t4_l0, @object
	.size	t4_l0, 1
t4_l0:
	.zero	1
	.globl	_x_t4_l0
	.type	_x_t4_l0, @object
	.size	_x_t4_l0, 1
_x_t4_l0:
	.zero	1
	.globl	t6_evt1
	.type	t6_evt1, @object
	.size	t6_evt1, 1
t6_evt1:
	.zero	1
	.globl	_x_t6_evt1
	.type	_x_t6_evt1, @object
	.size	_x_t6_evt1, 1
_x_t6_evt1:
	.zero	1
	.globl	t7_x
	.align 4
	.type	t7_x, @object
	.size	t7_x, 4
t7_x:
	.zero	4
	.globl	_x_t7_x
	.align 4
	.type	_x_t7_x, @object
	.size	_x_t7_x, 4
_x_t7_x:
	.zero	4
	.globl	t7_evt1
	.type	t7_evt1, @object
	.size	t7_evt1, 1
t7_evt1:
	.zero	1
	.globl	_x_t7_evt1
	.type	_x_t7_evt1, @object
	.size	_x_t7_evt1, 1
_x_t7_evt1:
	.zero	1
	.globl	t8_x
	.align 4
	.type	t8_x, @object
	.size	t8_x, 4
t8_x:
	.zero	4
	.globl	_x_t8_x
	.align 4
	.type	_x_t8_x, @object
	.size	_x_t8_x, 4
_x_t8_x:
	.zero	4
	.globl	t7_l0
	.type	t7_l0, @object
	.size	t7_l0, 1
t7_l0:
	.zero	1
	.globl	_x_t7_l0
	.type	_x_t7_l0, @object
	.size	_x_t7_l0, 1
_x_t7_l0:
	.zero	1
	.globl	t7_l1
	.type	t7_l1, @object
	.size	t7_l1, 1
t7_l1:
	.zero	1
	.globl	_x_t7_l1
	.type	_x_t7_l1, @object
	.size	_x_t7_l1, 1
_x_t7_l1:
	.zero	1
	.globl	t8_evt0
	.type	t8_evt0, @object
	.size	t8_evt0, 1
t8_evt0:
	.zero	1
	.globl	_x_t8_evt0
	.type	_x_t8_evt0, @object
	.size	_x_t8_evt0, 1
_x_t8_evt0:
	.zero	1
	.globl	t8_evt1
	.type	t8_evt1, @object
	.size	t8_evt1, 1
t8_evt1:
	.zero	1
	.globl	_x_t8_evt1
	.type	_x_t8_evt1, @object
	.size	_x_t8_evt1, 1
_x_t8_evt1:
	.zero	1
	.globl	t9_x
	.align 4
	.type	t9_x, @object
	.size	t9_x, 4
t9_x:
	.zero	4
	.globl	_x_t9_x
	.align 4
	.type	_x_t9_x, @object
	.size	_x_t9_x, 4
_x_t9_x:
	.zero	4
	.text
	.globl	main
	.type	main, @function
main:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t13_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t13_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t13_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t13_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t13_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t12_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t12_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t12_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t12_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t12_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t11_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t11_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t11_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t11_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t11_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t10_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t10_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t10_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t9_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t9_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t9_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t9_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t3_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t2_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR controller_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t2_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t2_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t1_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR controller_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t2_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t1_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR controller_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t1_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t1_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t2_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t3_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t0_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR gate_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t5_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t0_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR gate_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t5_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t6_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR gate_y[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t4_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t5_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t4_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t5_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t0_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t0_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t1_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t10_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR controller_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t8_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR gate_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t5_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t6_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR controller_z[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t6_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t10_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR controller_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t8_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR gate_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t0_x[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR controller_cnt[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t6_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t7_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t3_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t4_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _diverge_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t3_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t3_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t4_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t4_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t6_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t7_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t7_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t8_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t7_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t7_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t8_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t8_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t9_x[rip], eax
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t13_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	jne	.L6
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	je	.L7
.L6:
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	je	.L7
.L8:
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	je	.L9
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	je	.L7
.L9:
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	je	.L4
.L7:
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L10
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L11
.L10:
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	je	.L12
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L11
.L12:
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L13
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	je	.L11
.L13:
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L4
.L11:
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	jne	.L14
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	je	.L15
.L14:
	movss	xmm1, DWORD PTR t13_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L15:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t12_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	jne	.L18
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	je	.L19
.L18:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	je	.L20
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	je	.L19
.L20:
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	je	.L21
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	je	.L19
.L21:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	je	.L4
.L19:
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L22
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L23
.L22:
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L24
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L23
.L24:
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L25
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L23
.L25:
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L4
.L23:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	jne	.L26
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	je	.L27
.L26:
	movss	xmm1, DWORD PTR t12_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L27:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t11_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	jne	.L30
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	je	.L31
.L30:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	je	.L32
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	je	.L31
.L32:
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	je	.L33
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	je	.L31
.L33:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	je	.L4
.L31:
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L34
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L35
.L34:
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L36
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L35
.L36:
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L37
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L35
.L37:
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L4
.L35:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	jne	.L38
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	je	.L39
.L38:
	movss	xmm1, DWORD PTR t11_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L39:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t10_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	jne	.L42
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	je	.L43
.L42:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	je	.L44
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	je	.L43
.L44:
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	je	.L45
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	je	.L43
.L45:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	je	.L4
.L43:
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L46
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L47
.L46:
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L48
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L47
.L48:
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L49
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L47
.L49:
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L4
.L47:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	jne	.L50
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	je	.L51
.L50:
	movss	xmm1, DWORD PTR t10_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L51:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t9_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	jne	.L54
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	je	.L55
.L54:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	je	.L56
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	je	.L55
.L56:
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	je	.L57
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	je	.L55
.L57:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	je	.L4
.L55:
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L58
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L59
.L58:
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L60
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L59
.L60:
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L59
.L61:
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L4
.L59:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	jne	.L62
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	je	.L63
.L62:
	movss	xmm1, DWORD PTR t9_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L63:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t8_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	jne	.L66
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	je	.L67
.L66:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	je	.L68
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	je	.L67
.L68:
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	je	.L69
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	je	.L67
.L69:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	je	.L4
.L67:
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L70
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L71
.L70:
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L72
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L71
.L72:
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L73
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L71
.L73:
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L4
.L71:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	jne	.L74
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	je	.L75
.L74:
	movss	xmm1, DWORD PTR t8_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L75:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t7_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	jne	.L78
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	je	.L79
.L78:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	je	.L80
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	je	.L79
.L80:
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	je	.L79
.L81:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	je	.L4
.L79:
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L82
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L83
.L82:
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L84
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L83
.L84:
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L85
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L83
.L85:
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L4
.L83:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	jne	.L86
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	je	.L87
.L86:
	movss	xmm1, DWORD PTR t7_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L87:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t6_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	jne	.L90
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	je	.L91
.L90:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	je	.L92
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	je	.L91
.L92:
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	je	.L93
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	je	.L91
.L93:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	je	.L4
.L91:
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L94
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L95
.L94:
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L96
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L95
.L96:
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L97
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L95
.L97:
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L4
.L95:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	jne	.L98
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	je	.L99
.L98:
	movss	xmm1, DWORD PTR t6_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L99:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t5_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	jne	.L102
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	je	.L103
.L102:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	je	.L104
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	je	.L103
.L104:
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	je	.L105
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	je	.L103
.L105:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	je	.L4
.L103:
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L106
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L107
.L106:
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L108
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L107
.L108:
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L109
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L107
.L109:
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L4
.L107:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	jne	.L110
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	je	.L111
.L110:
	movss	xmm1, DWORD PTR t5_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L111:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t4_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	jne	.L114
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	je	.L115
.L114:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	je	.L116
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	je	.L115
.L116:
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	je	.L117
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	je	.L115
.L117:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	je	.L4
.L115:
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L118
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L119
.L118:
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L120
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L119
.L120:
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L121
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L119
.L121:
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L4
.L119:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	jne	.L122
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	je	.L123
.L122:
	movss	xmm1, DWORD PTR t4_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L123:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t3_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	jne	.L126
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	je	.L127
.L126:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	je	.L128
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	je	.L127
.L128:
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	je	.L129
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	je	.L127
.L129:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	je	.L4
.L127:
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L130
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L131
.L130:
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L132
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L131
.L132:
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L133
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L131
.L133:
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L4
.L131:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	jne	.L134
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	je	.L135
.L134:
	movss	xmm1, DWORD PTR t3_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L135:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	jne	.L138
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	je	.L139
.L138:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	je	.L140
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	je	.L139
.L140:
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	je	.L141
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	je	.L139
.L141:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	je	.L4
.L139:
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L142
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L143
.L142:
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L144
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L143
.L144:
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L145
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L143
.L145:
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L4
.L143:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	jne	.L146
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	je	.L147
.L146:
	movss	xmm1, DWORD PTR t2_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L147:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	jne	.L150
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L151
.L150:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	je	.L152
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L151
.L152:
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L153
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	je	.L151
.L153:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L4
.L151:
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L154
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L155
.L154:
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L156
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L155
.L156:
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L157
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L155
.L157:
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L4
.L155:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	jne	.L158
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L159
.L158:
	movss	xmm1, DWORD PTR t1_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L159:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	jne	.L162
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L163
.L162:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	je	.L164
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L163
.L164:
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L165
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	je	.L163
.L165:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L4
.L163:
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L166
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L167
.L166:
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L168
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L167
.L168:
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L169
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L167
.L169:
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L4
.L167:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	jne	.L170
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L171
.L170:
	movss	xmm1, DWORD PTR t0_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L171:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR controller_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L174
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L175
.L174:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L176
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L175
.L176:
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L177
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L175
.L177:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L4
.L175:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L178
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L178
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L179
.L178:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L180
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L180
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L179
.L180:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L179
.L181:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L182
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L182
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L179
.L182:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L4
.L179:
	mov	eax, DWORD PTR controller_cnt[rip]
	test	eax, eax
	je	.L183
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 1
	je	.L183
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 2
	je	.L183
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 3
	je	.L183
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 4
	je	.L183
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 5
	je	.L183
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 6
	je	.L183
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 7
	je	.L183
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 8
	je	.L183
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 9
	je	.L183
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 10
	je	.L183
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 11
	je	.L183
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 12
	je	.L183
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 13
	je	.L183
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 14
	je	.L183
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 15
	jne	.L4
.L183:
	movss	xmm1, DWORD PTR controller_z[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L184
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L185
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L4
.L185:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L184
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L4
.L184:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR gate_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	jne	.L187
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L188
.L187:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L189
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L188
.L189:
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L190
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L188
.L190:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L4
.L188:
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L191
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L192
.L191:
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L192
.L193:
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L194
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L192
.L194:
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L4
.L192:
	movss	xmm1, DWORD PTR gate_y[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L195
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L195
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L4
.L195:
	movss	xmm1, DWORD PTR gate_y[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	jnb	.L196
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L196
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	jne	.L4
.L196:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm0, DWORD PTR delta[rip]
	movss	xmm1, DWORD PTR _diverge_delta[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	mov	eax, 1
	jmp	.L199
.L4:
	mov	eax, 0
.L199:
	mov	DWORD PTR -4[rbp], eax
	jmp	.L200
.L756:
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t13_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t13_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t13_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t13_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t13_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t12_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t12_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t12_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t12_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t12_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t11_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t11_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t11_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t11_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t11_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t10_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t10_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t10_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t9_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t9_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t9_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t9_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t3_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t2_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_controller_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t2_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t2_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t1_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_controller_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t2_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t1_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_controller_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t1_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t1_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t2_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t3_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t0_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_gate_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t5_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t0_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_gate_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t5_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t6_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_gate_y[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t4_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t5_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t4_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t5_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t0_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t0_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t1_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t10_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_controller_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t8_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_gate_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t5_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t6_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_controller_z[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t6_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t10_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_controller_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t8_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_gate_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t0_x[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_controller_cnt[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t6_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t7_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t3_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t4_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x__diverge_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t3_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t3_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t4_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t4_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t6_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t7_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t7_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t8_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t7_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t7_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t8_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t8_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t9_x[rip], eax
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	jne	.L201
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	je	.L202
.L201:
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	je	.L203
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	je	.L202
.L203:
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	je	.L204
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	je	.L202
.L204:
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	je	.L205
.L202:
	movzx	eax, BYTE PTR _x_t13_evt0[rip]
	test	al, al
	jne	.L206
	movzx	eax, BYTE PTR _x_t13_evt1[rip]
	test	al, al
	je	.L207
.L206:
	movzx	eax, BYTE PTR _x_t13_evt0[rip]
	test	al, al
	je	.L208
	movzx	eax, BYTE PTR _x_t13_evt1[rip]
	test	al, al
	je	.L207
.L208:
	movzx	eax, BYTE PTR _x_t13_evt1[rip]
	test	al, al
	je	.L209
	movzx	eax, BYTE PTR _x_t13_evt0[rip]
	test	al, al
	je	.L207
.L209:
	movzx	eax, BYTE PTR _x_t13_evt0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t13_evt1[rip]
	test	al, al
	je	.L205
.L207:
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	jne	.L210
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	je	.L211
.L210:
	movss	xmm1, DWORD PTR _x_t13_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L205
.L211:
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L213
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L213
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t13_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t13_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L213
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L214
.L213:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L205
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L214
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L205
.L214:
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	je	.L217
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	jne	.L217
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	je	.L217
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	jne	.L217
	movss	xmm0, DWORD PTR _x_t13_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L217
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L218
.L217:
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	jne	.L218
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	jne	.L218
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L218
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L218
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	jne	.L205
.L218:
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	je	.L220
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	jne	.L220
	movss	xmm1, DWORD PTR t13_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L220
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	je	.L220
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L220
	movss	xmm0, DWORD PTR t13_x[rip]
	movss	xmm1, DWORD PTR _x_t13_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L220
	ucomiss	xmm0, xmm1
	je	.L221
.L220:
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	je	.L221
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	jne	.L221
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L221
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L221
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	jne	.L205
.L221:
	movss	xmm0, DWORD PTR t13_x[rip]
	movss	xmm1, DWORD PTR _x_t13_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L223
	ucomiss	xmm0, xmm1
	jne	.L223
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	je	.L223
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	je	.L223
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	je	.L223
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	jne	.L225
.L223:
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	je	.L225
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	jne	.L225
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L225
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L225
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	jne	.L205
.L225:
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	jne	.L226
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	jne	.L226
	movss	xmm1, DWORD PTR t13_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L226
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L226
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L226
	movss	xmm0, DWORD PTR t13_x[rip]
	movss	xmm1, DWORD PTR _x_t13_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L226
	ucomiss	xmm0, xmm1
	je	.L228
.L226:
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	je	.L228
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	je	.L228
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L228
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L228
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	jne	.L205
.L228:
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	jne	.L230
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	je	.L231
.L230:
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	je	.L232
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	je	.L231
.L232:
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	je	.L233
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	je	.L231
.L233:
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	je	.L205
.L231:
	movzx	eax, BYTE PTR _x_t12_evt0[rip]
	test	al, al
	jne	.L234
	movzx	eax, BYTE PTR _x_t12_evt1[rip]
	test	al, al
	je	.L235
.L234:
	movzx	eax, BYTE PTR _x_t12_evt0[rip]
	test	al, al
	je	.L236
	movzx	eax, BYTE PTR _x_t12_evt1[rip]
	test	al, al
	je	.L235
.L236:
	movzx	eax, BYTE PTR _x_t12_evt1[rip]
	test	al, al
	je	.L237
	movzx	eax, BYTE PTR _x_t12_evt0[rip]
	test	al, al
	je	.L235
.L237:
	movzx	eax, BYTE PTR _x_t12_evt0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t12_evt1[rip]
	test	al, al
	je	.L205
.L235:
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	jne	.L238
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	je	.L239
.L238:
	movss	xmm1, DWORD PTR _x_t12_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L205
.L239:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L241
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t12_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t12_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L241
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L242
.L241:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L205
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L242
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L205
.L242:
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	jne	.L245
	movss	xmm0, DWORD PTR _x_t12_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L246
.L245:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	jne	.L246
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L246
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L246
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	jne	.L205
.L246:
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	je	.L248
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	jne	.L248
	movss	xmm1, DWORD PTR t12_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L248
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L248
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L248
	movss	xmm0, DWORD PTR t12_x[rip]
	movss	xmm1, DWORD PTR _x_t12_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L248
	ucomiss	xmm0, xmm1
	je	.L249
.L248:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	je	.L249
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	jne	.L249
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L249
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L249
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	jne	.L205
.L249:
	movss	xmm0, DWORD PTR t12_x[rip]
	movss	xmm1, DWORD PTR _x_t12_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L251
	ucomiss	xmm0, xmm1
	jne	.L251
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	je	.L251
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	je	.L251
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L251
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	jne	.L253
.L251:
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	jne	.L253
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L253
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L253
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	jne	.L205
.L253:
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	jne	.L254
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	jne	.L254
	movss	xmm1, DWORD PTR t12_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L254
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L254
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L254
	movss	xmm0, DWORD PTR t12_x[rip]
	movss	xmm1, DWORD PTR _x_t12_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L254
	ucomiss	xmm0, xmm1
	je	.L256
.L254:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	je	.L256
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	je	.L256
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L256
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L256
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	jne	.L205
.L256:
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	jne	.L258
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	je	.L259
.L258:
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	je	.L260
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	je	.L259
.L260:
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	je	.L261
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	je	.L259
.L261:
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	je	.L205
.L259:
	movzx	eax, BYTE PTR _x_t11_evt0[rip]
	test	al, al
	jne	.L262
	movzx	eax, BYTE PTR _x_t11_evt1[rip]
	test	al, al
	je	.L263
.L262:
	movzx	eax, BYTE PTR _x_t11_evt0[rip]
	test	al, al
	je	.L264
	movzx	eax, BYTE PTR _x_t11_evt1[rip]
	test	al, al
	je	.L263
.L264:
	movzx	eax, BYTE PTR _x_t11_evt1[rip]
	test	al, al
	je	.L265
	movzx	eax, BYTE PTR _x_t11_evt0[rip]
	test	al, al
	je	.L263
.L265:
	movzx	eax, BYTE PTR _x_t11_evt0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t11_evt1[rip]
	test	al, al
	je	.L205
.L263:
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	jne	.L266
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	je	.L267
.L266:
	movss	xmm1, DWORD PTR _x_t11_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L205
.L267:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L269
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L269
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t11_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t11_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L269
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L270
.L269:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L205
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L270
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L205
.L270:
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	je	.L273
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	jne	.L273
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L273
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	jne	.L273
	movss	xmm0, DWORD PTR _x_t11_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L273
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L274
.L273:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	jne	.L274
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	jne	.L274
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L274
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L274
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	jne	.L205
.L274:
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	je	.L276
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	jne	.L276
	movss	xmm1, DWORD PTR t11_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L276
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L276
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L276
	movss	xmm0, DWORD PTR t11_x[rip]
	movss	xmm1, DWORD PTR _x_t11_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L276
	ucomiss	xmm0, xmm1
	je	.L277
.L276:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	je	.L277
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	jne	.L277
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L277
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L277
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	jne	.L205
.L277:
	movss	xmm0, DWORD PTR t11_x[rip]
	movss	xmm1, DWORD PTR _x_t11_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L279
	ucomiss	xmm0, xmm1
	jne	.L279
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	je	.L279
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	je	.L279
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L279
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	jne	.L281
.L279:
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	je	.L281
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	jne	.L281
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L281
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L281
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	jne	.L205
.L281:
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	jne	.L282
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	jne	.L282
	movss	xmm1, DWORD PTR t11_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L282
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L282
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L282
	movss	xmm0, DWORD PTR t11_x[rip]
	movss	xmm1, DWORD PTR _x_t11_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L282
	ucomiss	xmm0, xmm1
	je	.L284
.L282:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	je	.L284
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	je	.L284
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L284
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L284
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	jne	.L205
.L284:
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	jne	.L286
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	je	.L287
.L286:
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	je	.L288
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	je	.L287
.L288:
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	je	.L289
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	je	.L287
.L289:
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	je	.L205
.L287:
	movzx	eax, BYTE PTR _x_t10_evt0[rip]
	test	al, al
	jne	.L290
	movzx	eax, BYTE PTR _x_t10_evt1[rip]
	test	al, al
	je	.L291
.L290:
	movzx	eax, BYTE PTR _x_t10_evt0[rip]
	test	al, al
	je	.L292
	movzx	eax, BYTE PTR _x_t10_evt1[rip]
	test	al, al
	je	.L291
.L292:
	movzx	eax, BYTE PTR _x_t10_evt1[rip]
	test	al, al
	je	.L293
	movzx	eax, BYTE PTR _x_t10_evt0[rip]
	test	al, al
	je	.L291
.L293:
	movzx	eax, BYTE PTR _x_t10_evt0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t10_evt1[rip]
	test	al, al
	je	.L205
.L291:
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	jne	.L294
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	je	.L295
.L294:
	movss	xmm1, DWORD PTR _x_t10_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L205
.L295:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L297
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L297
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t10_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t10_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L297
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L298
.L297:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L205
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L298
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L205
.L298:
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	jne	.L301
	movss	xmm0, DWORD PTR _x_t10_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L301
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L302
.L301:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	jne	.L302
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	jne	.L302
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L302
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L302
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	jne	.L205
.L302:
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	je	.L304
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	jne	.L304
	movss	xmm1, DWORD PTR t10_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L304
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L304
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L304
	movss	xmm0, DWORD PTR t10_x[rip]
	movss	xmm1, DWORD PTR _x_t10_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L304
	ucomiss	xmm0, xmm1
	je	.L305
.L304:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	je	.L305
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	jne	.L305
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L305
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L305
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	jne	.L205
.L305:
	movss	xmm0, DWORD PTR t10_x[rip]
	movss	xmm1, DWORD PTR _x_t10_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L307
	ucomiss	xmm0, xmm1
	jne	.L307
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	je	.L307
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	je	.L307
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L307
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	jne	.L309
.L307:
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	je	.L309
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	jne	.L309
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L309
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L309
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	jne	.L205
.L309:
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	jne	.L310
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	jne	.L310
	movss	xmm1, DWORD PTR t10_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L310
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L310
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L310
	movss	xmm0, DWORD PTR t10_x[rip]
	movss	xmm1, DWORD PTR _x_t10_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L310
	ucomiss	xmm0, xmm1
	je	.L312
.L310:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	je	.L312
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	je	.L312
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L312
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L312
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	jne	.L205
.L312:
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	jne	.L314
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	je	.L315
.L314:
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	je	.L316
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	je	.L315
.L316:
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	je	.L317
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	je	.L315
.L317:
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	je	.L205
.L315:
	movzx	eax, BYTE PTR _x_t9_evt0[rip]
	test	al, al
	jne	.L318
	movzx	eax, BYTE PTR _x_t9_evt1[rip]
	test	al, al
	je	.L319
.L318:
	movzx	eax, BYTE PTR _x_t9_evt0[rip]
	test	al, al
	je	.L320
	movzx	eax, BYTE PTR _x_t9_evt1[rip]
	test	al, al
	je	.L319
.L320:
	movzx	eax, BYTE PTR _x_t9_evt1[rip]
	test	al, al
	je	.L321
	movzx	eax, BYTE PTR _x_t9_evt0[rip]
	test	al, al
	je	.L319
.L321:
	movzx	eax, BYTE PTR _x_t9_evt0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t9_evt1[rip]
	test	al, al
	je	.L205
.L319:
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	jne	.L322
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	je	.L323
.L322:
	movss	xmm1, DWORD PTR _x_t9_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L205
.L323:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L325
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L325
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t9_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t9_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L325
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L326
.L325:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L205
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L326
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L205
.L326:
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	je	.L329
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	jne	.L329
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L329
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	jne	.L329
	movss	xmm0, DWORD PTR _x_t9_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L329
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L330
.L329:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	jne	.L330
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	jne	.L330
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L330
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L330
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	jne	.L205
.L330:
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	je	.L332
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	jne	.L332
	movss	xmm1, DWORD PTR t9_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L332
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L332
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L332
	movss	xmm0, DWORD PTR t9_x[rip]
	movss	xmm1, DWORD PTR _x_t9_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L332
	ucomiss	xmm0, xmm1
	je	.L333
.L332:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	je	.L333
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	jne	.L333
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L333
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L333
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	jne	.L205
.L333:
	movss	xmm0, DWORD PTR t9_x[rip]
	movss	xmm1, DWORD PTR _x_t9_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L335
	ucomiss	xmm0, xmm1
	jne	.L335
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	je	.L335
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	je	.L335
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L335
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	jne	.L337
.L335:
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	je	.L337
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	jne	.L337
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L337
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L337
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	jne	.L205
.L337:
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	jne	.L338
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	jne	.L338
	movss	xmm1, DWORD PTR t9_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L338
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L338
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L338
	movss	xmm0, DWORD PTR t9_x[rip]
	movss	xmm1, DWORD PTR _x_t9_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L338
	ucomiss	xmm0, xmm1
	je	.L340
.L338:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	je	.L340
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	je	.L340
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L340
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L340
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	jne	.L205
.L340:
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	jne	.L342
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	je	.L343
.L342:
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	je	.L344
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	je	.L343
.L344:
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	je	.L345
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	je	.L343
.L345:
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	je	.L205
.L343:
	movzx	eax, BYTE PTR _x_t8_evt0[rip]
	test	al, al
	jne	.L346
	movzx	eax, BYTE PTR _x_t8_evt1[rip]
	test	al, al
	je	.L347
.L346:
	movzx	eax, BYTE PTR _x_t8_evt0[rip]
	test	al, al
	je	.L348
	movzx	eax, BYTE PTR _x_t8_evt1[rip]
	test	al, al
	je	.L347
.L348:
	movzx	eax, BYTE PTR _x_t8_evt1[rip]
	test	al, al
	je	.L349
	movzx	eax, BYTE PTR _x_t8_evt0[rip]
	test	al, al
	je	.L347
.L349:
	movzx	eax, BYTE PTR _x_t8_evt0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t8_evt1[rip]
	test	al, al
	je	.L205
.L347:
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	jne	.L350
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	je	.L351
.L350:
	movss	xmm1, DWORD PTR _x_t8_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L205
.L351:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L353
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L353
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t8_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t8_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L353
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L354
.L353:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L205
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L354
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L205
.L354:
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	je	.L357
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	jne	.L357
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L357
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	jne	.L357
	movss	xmm0, DWORD PTR _x_t8_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L357
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L358
.L357:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	jne	.L358
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	jne	.L358
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L358
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L358
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	jne	.L205
.L358:
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	je	.L360
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	jne	.L360
	movss	xmm1, DWORD PTR t8_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L360
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L360
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L360
	movss	xmm0, DWORD PTR t8_x[rip]
	movss	xmm1, DWORD PTR _x_t8_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L360
	ucomiss	xmm0, xmm1
	je	.L361
.L360:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	je	.L361
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	jne	.L361
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L361
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L361
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	jne	.L205
.L361:
	movss	xmm0, DWORD PTR t8_x[rip]
	movss	xmm1, DWORD PTR _x_t8_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L363
	ucomiss	xmm0, xmm1
	jne	.L363
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	je	.L363
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	je	.L363
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L363
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	jne	.L365
.L363:
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	je	.L365
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	jne	.L365
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L365
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L365
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	jne	.L205
.L365:
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	jne	.L366
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	jne	.L366
	movss	xmm1, DWORD PTR t8_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L366
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L366
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L366
	movss	xmm0, DWORD PTR t8_x[rip]
	movss	xmm1, DWORD PTR _x_t8_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L366
	ucomiss	xmm0, xmm1
	je	.L368
.L366:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	je	.L368
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	je	.L368
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L368
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L368
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	jne	.L205
.L368:
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	jne	.L370
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	je	.L371
.L370:
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	je	.L372
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	je	.L371
.L372:
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	je	.L373
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	je	.L371
.L373:
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	je	.L205
.L371:
	movzx	eax, BYTE PTR _x_t7_evt0[rip]
	test	al, al
	jne	.L374
	movzx	eax, BYTE PTR _x_t7_evt1[rip]
	test	al, al
	je	.L375
.L374:
	movzx	eax, BYTE PTR _x_t7_evt0[rip]
	test	al, al
	je	.L376
	movzx	eax, BYTE PTR _x_t7_evt1[rip]
	test	al, al
	je	.L375
.L376:
	movzx	eax, BYTE PTR _x_t7_evt1[rip]
	test	al, al
	je	.L377
	movzx	eax, BYTE PTR _x_t7_evt0[rip]
	test	al, al
	je	.L375
.L377:
	movzx	eax, BYTE PTR _x_t7_evt0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t7_evt1[rip]
	test	al, al
	je	.L205
.L375:
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	jne	.L378
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	je	.L379
.L378:
	movss	xmm1, DWORD PTR _x_t7_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L205
.L379:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L381
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L381
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t7_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t7_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L381
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L382
.L381:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L205
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L382
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L205
.L382:
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	je	.L385
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	jne	.L385
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L385
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	jne	.L385
	movss	xmm0, DWORD PTR _x_t7_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L385
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L386
.L385:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	jne	.L386
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	jne	.L386
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L386
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L386
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	jne	.L205
.L386:
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	je	.L388
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	jne	.L388
	movss	xmm1, DWORD PTR t7_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L388
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L388
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L388
	movss	xmm0, DWORD PTR t7_x[rip]
	movss	xmm1, DWORD PTR _x_t7_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L388
	ucomiss	xmm0, xmm1
	je	.L389
.L388:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	je	.L389
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	jne	.L389
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L389
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L389
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	jne	.L205
.L389:
	movss	xmm0, DWORD PTR t7_x[rip]
	movss	xmm1, DWORD PTR _x_t7_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L391
	ucomiss	xmm0, xmm1
	jne	.L391
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	je	.L391
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	je	.L391
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L391
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	jne	.L393
.L391:
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	je	.L393
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	jne	.L393
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L393
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L393
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	jne	.L205
.L393:
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	jne	.L394
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	jne	.L394
	movss	xmm1, DWORD PTR t7_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L394
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L394
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L394
	movss	xmm0, DWORD PTR t7_x[rip]
	movss	xmm1, DWORD PTR _x_t7_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L394
	ucomiss	xmm0, xmm1
	je	.L396
.L394:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	je	.L396
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	je	.L396
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L396
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L396
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	jne	.L205
.L396:
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	jne	.L398
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	je	.L399
.L398:
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	je	.L400
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	je	.L399
.L400:
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	je	.L401
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	je	.L399
.L401:
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	je	.L205
.L399:
	movzx	eax, BYTE PTR _x_t6_evt0[rip]
	test	al, al
	jne	.L402
	movzx	eax, BYTE PTR _x_t6_evt1[rip]
	test	al, al
	je	.L403
.L402:
	movzx	eax, BYTE PTR _x_t6_evt0[rip]
	test	al, al
	je	.L404
	movzx	eax, BYTE PTR _x_t6_evt1[rip]
	test	al, al
	je	.L403
.L404:
	movzx	eax, BYTE PTR _x_t6_evt1[rip]
	test	al, al
	je	.L405
	movzx	eax, BYTE PTR _x_t6_evt0[rip]
	test	al, al
	je	.L403
.L405:
	movzx	eax, BYTE PTR _x_t6_evt0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t6_evt1[rip]
	test	al, al
	je	.L205
.L403:
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	jne	.L406
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	je	.L407
.L406:
	movss	xmm1, DWORD PTR _x_t6_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L205
.L407:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L409
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L409
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t6_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t6_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L409
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L410
.L409:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L205
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L410
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L205
.L410:
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	je	.L413
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	jne	.L413
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L413
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	jne	.L413
	movss	xmm0, DWORD PTR _x_t6_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L413
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L414
.L413:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	jne	.L414
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	jne	.L414
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L414
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L414
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	jne	.L205
.L414:
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	je	.L416
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	jne	.L416
	movss	xmm1, DWORD PTR t6_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L416
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L416
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L416
	movss	xmm0, DWORD PTR t6_x[rip]
	movss	xmm1, DWORD PTR _x_t6_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L416
	ucomiss	xmm0, xmm1
	je	.L417
.L416:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	je	.L417
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	jne	.L417
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L417
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L417
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	jne	.L205
.L417:
	movss	xmm0, DWORD PTR t6_x[rip]
	movss	xmm1, DWORD PTR _x_t6_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L419
	ucomiss	xmm0, xmm1
	jne	.L419
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	je	.L419
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	je	.L419
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L419
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	jne	.L421
.L419:
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	je	.L421
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	jne	.L421
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L421
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L421
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	jne	.L205
.L421:
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	jne	.L422
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	jne	.L422
	movss	xmm1, DWORD PTR t6_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L422
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L422
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L422
	movss	xmm0, DWORD PTR t6_x[rip]
	movss	xmm1, DWORD PTR _x_t6_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L422
	ucomiss	xmm0, xmm1
	je	.L424
.L422:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	je	.L424
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	je	.L424
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L424
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L424
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	jne	.L205
.L424:
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	jne	.L426
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	je	.L427
.L426:
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	je	.L428
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	je	.L427
.L428:
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	je	.L429
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	je	.L427
.L429:
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	je	.L205
.L427:
	movzx	eax, BYTE PTR _x_t5_evt0[rip]
	test	al, al
	jne	.L430
	movzx	eax, BYTE PTR _x_t5_evt1[rip]
	test	al, al
	je	.L431
.L430:
	movzx	eax, BYTE PTR _x_t5_evt0[rip]
	test	al, al
	je	.L432
	movzx	eax, BYTE PTR _x_t5_evt1[rip]
	test	al, al
	je	.L431
.L432:
	movzx	eax, BYTE PTR _x_t5_evt1[rip]
	test	al, al
	je	.L433
	movzx	eax, BYTE PTR _x_t5_evt0[rip]
	test	al, al
	je	.L431
.L433:
	movzx	eax, BYTE PTR _x_t5_evt0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t5_evt1[rip]
	test	al, al
	je	.L205
.L431:
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	jne	.L434
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	je	.L435
.L434:
	movss	xmm1, DWORD PTR _x_t5_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L205
.L435:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L437
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L437
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t5_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t5_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L437
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L438
.L437:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L205
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L438
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L205
.L438:
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	je	.L441
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	jne	.L441
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L441
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	jne	.L441
	movss	xmm0, DWORD PTR _x_t5_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L441
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L442
.L441:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	jne	.L442
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	jne	.L442
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L442
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L442
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	jne	.L205
.L442:
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	je	.L444
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	jne	.L444
	movss	xmm1, DWORD PTR t5_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L444
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L444
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L444
	movss	xmm0, DWORD PTR t5_x[rip]
	movss	xmm1, DWORD PTR _x_t5_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L444
	ucomiss	xmm0, xmm1
	je	.L445
.L444:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	je	.L445
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	jne	.L445
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L445
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L445
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	jne	.L205
.L445:
	movss	xmm0, DWORD PTR t5_x[rip]
	movss	xmm1, DWORD PTR _x_t5_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L447
	ucomiss	xmm0, xmm1
	jne	.L447
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	je	.L447
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	je	.L447
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L447
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	jne	.L449
.L447:
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	je	.L449
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	jne	.L449
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L449
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L449
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	jne	.L205
.L449:
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	jne	.L450
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	jne	.L450
	movss	xmm1, DWORD PTR t5_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L450
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L450
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L450
	movss	xmm0, DWORD PTR t5_x[rip]
	movss	xmm1, DWORD PTR _x_t5_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L450
	ucomiss	xmm0, xmm1
	je	.L452
.L450:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	je	.L452
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	je	.L452
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L452
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L452
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	jne	.L205
.L452:
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	jne	.L454
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	je	.L455
.L454:
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	je	.L456
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	je	.L455
.L456:
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	je	.L457
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	je	.L455
.L457:
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	je	.L205
.L455:
	movzx	eax, BYTE PTR _x_t4_evt0[rip]
	test	al, al
	jne	.L458
	movzx	eax, BYTE PTR _x_t4_evt1[rip]
	test	al, al
	je	.L459
.L458:
	movzx	eax, BYTE PTR _x_t4_evt0[rip]
	test	al, al
	je	.L460
	movzx	eax, BYTE PTR _x_t4_evt1[rip]
	test	al, al
	je	.L459
.L460:
	movzx	eax, BYTE PTR _x_t4_evt1[rip]
	test	al, al
	je	.L461
	movzx	eax, BYTE PTR _x_t4_evt0[rip]
	test	al, al
	je	.L459
.L461:
	movzx	eax, BYTE PTR _x_t4_evt0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t4_evt1[rip]
	test	al, al
	je	.L205
.L459:
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	jne	.L462
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	je	.L463
.L462:
	movss	xmm1, DWORD PTR _x_t4_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L205
.L463:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L465
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L465
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t4_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t4_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L465
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L466
.L465:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L205
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L466
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L205
.L466:
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	je	.L469
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	jne	.L469
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L469
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	jne	.L469
	movss	xmm0, DWORD PTR _x_t4_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L469
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L470
.L469:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	jne	.L470
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	jne	.L470
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L470
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L470
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	jne	.L205
.L470:
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	je	.L472
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	jne	.L472
	movss	xmm1, DWORD PTR t4_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L472
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L472
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L472
	movss	xmm0, DWORD PTR t4_x[rip]
	movss	xmm1, DWORD PTR _x_t4_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L472
	ucomiss	xmm0, xmm1
	je	.L473
.L472:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	je	.L473
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	jne	.L473
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L473
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L473
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	jne	.L205
.L473:
	movss	xmm0, DWORD PTR t4_x[rip]
	movss	xmm1, DWORD PTR _x_t4_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L475
	ucomiss	xmm0, xmm1
	jne	.L475
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	je	.L475
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	je	.L475
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L475
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	jne	.L477
.L475:
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	je	.L477
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	jne	.L477
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L477
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L477
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	jne	.L205
.L477:
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	jne	.L478
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	jne	.L478
	movss	xmm1, DWORD PTR t4_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L478
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L478
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L478
	movss	xmm0, DWORD PTR t4_x[rip]
	movss	xmm1, DWORD PTR _x_t4_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L478
	ucomiss	xmm0, xmm1
	je	.L480
.L478:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	je	.L480
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	je	.L480
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L480
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L480
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	jne	.L205
.L480:
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	jne	.L482
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	je	.L483
.L482:
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	je	.L484
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	je	.L483
.L484:
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	je	.L485
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	je	.L483
.L485:
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	je	.L205
.L483:
	movzx	eax, BYTE PTR _x_t3_evt0[rip]
	test	al, al
	jne	.L486
	movzx	eax, BYTE PTR _x_t3_evt1[rip]
	test	al, al
	je	.L487
.L486:
	movzx	eax, BYTE PTR _x_t3_evt0[rip]
	test	al, al
	je	.L488
	movzx	eax, BYTE PTR _x_t3_evt1[rip]
	test	al, al
	je	.L487
.L488:
	movzx	eax, BYTE PTR _x_t3_evt1[rip]
	test	al, al
	je	.L489
	movzx	eax, BYTE PTR _x_t3_evt0[rip]
	test	al, al
	je	.L487
.L489:
	movzx	eax, BYTE PTR _x_t3_evt0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t3_evt1[rip]
	test	al, al
	je	.L205
.L487:
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	jne	.L490
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	je	.L491
.L490:
	movss	xmm1, DWORD PTR _x_t3_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L205
.L491:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L493
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L493
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t3_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t3_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L493
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L494
.L493:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L205
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L494
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L205
.L494:
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	je	.L497
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	jne	.L497
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L497
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	jne	.L497
	movss	xmm0, DWORD PTR _x_t3_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L497
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L498
.L497:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	jne	.L498
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	jne	.L498
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L498
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L498
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	jne	.L205
.L498:
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	je	.L500
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	jne	.L500
	movss	xmm1, DWORD PTR t3_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L500
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L500
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L500
	movss	xmm0, DWORD PTR t3_x[rip]
	movss	xmm1, DWORD PTR _x_t3_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L500
	ucomiss	xmm0, xmm1
	je	.L501
.L500:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	je	.L501
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	jne	.L501
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L501
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L501
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	jne	.L205
.L501:
	movss	xmm0, DWORD PTR t3_x[rip]
	movss	xmm1, DWORD PTR _x_t3_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L503
	ucomiss	xmm0, xmm1
	jne	.L503
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	je	.L503
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	je	.L503
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L503
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	jne	.L505
.L503:
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	je	.L505
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	jne	.L505
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L505
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L505
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	jne	.L205
.L505:
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	jne	.L506
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	jne	.L506
	movss	xmm1, DWORD PTR t3_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L506
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L506
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L506
	movss	xmm0, DWORD PTR t3_x[rip]
	movss	xmm1, DWORD PTR _x_t3_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L506
	ucomiss	xmm0, xmm1
	je	.L508
.L506:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	je	.L508
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	je	.L508
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L508
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L508
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	jne	.L205
.L508:
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	jne	.L510
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	je	.L511
.L510:
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	je	.L512
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	je	.L511
.L512:
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	je	.L513
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	je	.L511
.L513:
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	je	.L205
.L511:
	movzx	eax, BYTE PTR _x_t2_evt0[rip]
	test	al, al
	jne	.L514
	movzx	eax, BYTE PTR _x_t2_evt1[rip]
	test	al, al
	je	.L515
.L514:
	movzx	eax, BYTE PTR _x_t2_evt0[rip]
	test	al, al
	je	.L516
	movzx	eax, BYTE PTR _x_t2_evt1[rip]
	test	al, al
	je	.L515
.L516:
	movzx	eax, BYTE PTR _x_t2_evt1[rip]
	test	al, al
	je	.L517
	movzx	eax, BYTE PTR _x_t2_evt0[rip]
	test	al, al
	je	.L515
.L517:
	movzx	eax, BYTE PTR _x_t2_evt0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t2_evt1[rip]
	test	al, al
	je	.L205
.L515:
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	jne	.L518
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	je	.L519
.L518:
	movss	xmm1, DWORD PTR _x_t2_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L205
.L519:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L521
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L521
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t2_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t2_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L521
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L522
.L521:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L205
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L522
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L205
.L522:
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	je	.L525
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	jne	.L525
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L525
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	jne	.L525
	movss	xmm0, DWORD PTR _x_t2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L525
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L526
.L525:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	jne	.L526
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	jne	.L526
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L526
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L526
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	jne	.L205
.L526:
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	je	.L528
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	jne	.L528
	movss	xmm1, DWORD PTR t2_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L528
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L528
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L528
	movss	xmm0, DWORD PTR t2_x[rip]
	movss	xmm1, DWORD PTR _x_t2_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L528
	ucomiss	xmm0, xmm1
	je	.L529
.L528:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	je	.L529
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	jne	.L529
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L529
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L529
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	jne	.L205
.L529:
	movss	xmm0, DWORD PTR t2_x[rip]
	movss	xmm1, DWORD PTR _x_t2_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L531
	ucomiss	xmm0, xmm1
	jne	.L531
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	je	.L531
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	je	.L531
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L531
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	jne	.L533
.L531:
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	je	.L533
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	jne	.L533
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L533
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L533
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	jne	.L205
.L533:
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	jne	.L534
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	jne	.L534
	movss	xmm1, DWORD PTR t2_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L534
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L534
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L534
	movss	xmm0, DWORD PTR t2_x[rip]
	movss	xmm1, DWORD PTR _x_t2_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L534
	ucomiss	xmm0, xmm1
	je	.L536
.L534:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	je	.L536
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	je	.L536
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L536
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L536
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	jne	.L205
.L536:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	jne	.L538
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L539
.L538:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	je	.L540
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L539
.L540:
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L541
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	je	.L539
.L541:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L205
.L539:
	movzx	eax, BYTE PTR _x_t1_evt0[rip]
	test	al, al
	jne	.L542
	movzx	eax, BYTE PTR _x_t1_evt1[rip]
	test	al, al
	je	.L543
.L542:
	movzx	eax, BYTE PTR _x_t1_evt0[rip]
	test	al, al
	je	.L544
	movzx	eax, BYTE PTR _x_t1_evt1[rip]
	test	al, al
	je	.L543
.L544:
	movzx	eax, BYTE PTR _x_t1_evt1[rip]
	test	al, al
	je	.L545
	movzx	eax, BYTE PTR _x_t1_evt0[rip]
	test	al, al
	je	.L543
.L545:
	movzx	eax, BYTE PTR _x_t1_evt0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t1_evt1[rip]
	test	al, al
	je	.L205
.L543:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	jne	.L546
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L547
.L546:
	movss	xmm1, DWORD PTR _x_t1_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L205
.L547:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L549
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L549
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t1_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t1_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L549
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L550
.L549:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L205
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L550
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L205
.L550:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	je	.L553
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	jne	.L553
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L553
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L553
	movss	xmm0, DWORD PTR _x_t1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L553
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L554
.L553:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	jne	.L554
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	jne	.L554
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L554
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L554
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L205
.L554:
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L556
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	jne	.L556
	movss	xmm1, DWORD PTR t1_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L556
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L556
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L556
	movss	xmm0, DWORD PTR t1_x[rip]
	movss	xmm1, DWORD PTR _x_t1_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L556
	ucomiss	xmm0, xmm1
	je	.L557
.L556:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	je	.L557
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	jne	.L557
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L557
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L557
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L205
.L557:
	movss	xmm0, DWORD PTR t1_x[rip]
	movss	xmm1, DWORD PTR _x_t1_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L559
	ucomiss	xmm0, xmm1
	jne	.L559
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	je	.L559
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L559
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L559
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L561
.L559:
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L561
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	jne	.L561
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L561
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L561
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L205
.L561:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	jne	.L562
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	jne	.L562
	movss	xmm1, DWORD PTR t1_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L562
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L562
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L562
	movss	xmm0, DWORD PTR t1_x[rip]
	movss	xmm1, DWORD PTR _x_t1_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L562
	ucomiss	xmm0, xmm1
	je	.L564
.L562:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	je	.L564
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L564
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L564
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L564
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L205
.L564:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	jne	.L566
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L567
.L566:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	je	.L568
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L567
.L568:
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L569
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	je	.L567
.L569:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L205
.L567:
	movzx	eax, BYTE PTR _x_t0_evt0[rip]
	test	al, al
	jne	.L570
	movzx	eax, BYTE PTR _x_t0_evt1[rip]
	test	al, al
	je	.L571
.L570:
	movzx	eax, BYTE PTR _x_t0_evt0[rip]
	test	al, al
	je	.L572
	movzx	eax, BYTE PTR _x_t0_evt1[rip]
	test	al, al
	je	.L571
.L572:
	movzx	eax, BYTE PTR _x_t0_evt1[rip]
	test	al, al
	je	.L573
	movzx	eax, BYTE PTR _x_t0_evt0[rip]
	test	al, al
	je	.L571
.L573:
	movzx	eax, BYTE PTR _x_t0_evt0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t0_evt1[rip]
	test	al, al
	je	.L205
.L571:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	jne	.L574
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L575
.L574:
	movss	xmm1, DWORD PTR _x_t0_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L205
.L575:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L577
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L577
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t0_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t0_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L577
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L578
.L577:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L205
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L578
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L205
.L578:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	je	.L581
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	jne	.L581
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L581
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L581
	movss	xmm0, DWORD PTR _x_t0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L581
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L582
.L581:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	jne	.L582
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	jne	.L582
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L582
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L582
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L205
.L582:
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L584
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	jne	.L584
	movss	xmm1, DWORD PTR t0_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L584
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L584
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L584
	movss	xmm0, DWORD PTR t0_x[rip]
	movss	xmm1, DWORD PTR _x_t0_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L584
	ucomiss	xmm0, xmm1
	je	.L585
.L584:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	je	.L585
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	jne	.L585
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L585
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L585
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L205
.L585:
	movss	xmm0, DWORD PTR t0_x[rip]
	movss	xmm1, DWORD PTR _x_t0_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L587
	ucomiss	xmm0, xmm1
	jne	.L587
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	je	.L587
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L587
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L587
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L589
.L587:
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L589
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	jne	.L589
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L589
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L589
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L205
.L589:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	jne	.L590
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	jne	.L590
	movss	xmm1, DWORD PTR t0_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L590
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L590
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L590
	movss	xmm0, DWORD PTR t0_x[rip]
	movss	xmm1, DWORD PTR _x_t0_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L590
	ucomiss	xmm0, xmm1
	je	.L592
.L590:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	je	.L592
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L592
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L592
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L592
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L205
.L592:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	jne	.L594
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L595
.L594:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L596
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L595
.L596:
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L597
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L595
.L597:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L205
.L595:
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	test	al, al
	jne	.L598
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	test	al, al
	jne	.L598
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	test	al, al
	je	.L599
.L598:
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	test	al, al
	jne	.L600
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	test	al, al
	je	.L600
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	test	al, al
	je	.L599
.L600:
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	test	al, al
	jne	.L601
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	test	al, al
	je	.L601
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	test	al, al
	je	.L599
.L601:
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	test	al, al
	jne	.L602
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	test	al, al
	je	.L602
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	test	al, al
	jne	.L599
.L602:
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	test	al, al
	jne	.L205
.L599:
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	test	eax, eax
	je	.L603
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 1
	je	.L603
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 2
	je	.L603
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 3
	je	.L603
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 4
	je	.L603
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 5
	je	.L603
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 6
	je	.L603
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 7
	je	.L603
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 8
	je	.L603
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 9
	je	.L603
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 10
	je	.L603
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 11
	je	.L603
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 12
	je	.L603
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 13
	je	.L603
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 14
	je	.L603
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 15
	jne	.L205
.L603:
	movss	xmm1, DWORD PTR _x_controller_z[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L604
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L605
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L205
.L605:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L604
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	jne	.L205
.L604:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L606
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L606
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR controller_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_controller_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L606
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L606
	mov	edx, DWORD PTR controller_cnt[rip]
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	edx, eax
	je	.L608
.L606:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L205
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L608
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L608
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L205
.L608:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L610
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	jne	.L610
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L610
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L610
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L610
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 1
	jne	.L610
	movss	xmm0, DWORD PTR _x_controller_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L610
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L611
.L610:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L611
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L611
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L611
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L611
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L205
.L611:
	movss	xmm0, DWORD PTR controller_z[rip]
	movss	xmm1, DWORD PTR _x_controller_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L613
	ucomiss	xmm0, xmm1
	jne	.L613
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L615
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L616
.L615:
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L613
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L616
.L613:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L616
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L616
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L616
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L616
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L205
.L616:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L617
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L617
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L617
	mov	eax, DWORD PTR controller_cnt[rip]
	mov	edx, DWORD PTR _x_controller_cnt[rip]
	sub	eax, edx
	cmp	eax, -1
	je	.L618
.L617:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L619
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L619
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L619
	mov	eax, DWORD PTR controller_cnt[rip]
	mov	edx, DWORD PTR _x_controller_cnt[rip]
	sub	eax, edx
	cmp	eax, 1
	je	.L618
.L619:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L618
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L618
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L620
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L620
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L618
.L620:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L618
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L618
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L618
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L205
.L618:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L621
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L621
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L621
	mov	edx, DWORD PTR controller_cnt[rip]
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	edx, eax
	jne	.L621
	movss	xmm0, DWORD PTR controller_z[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	ucomiss	xmm0, xmm1
	jp	.L621
	movss	xmm1, DWORD PTR .LC2[rip]
	ucomiss	xmm0, xmm1
	je	.L622
.L621:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L622
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L622
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L624
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L624
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L622
.L624:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L622
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L622
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L622
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L205
.L622:
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L625
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L626
.L625:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L627
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	jne	.L626
.L627:
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L626
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L626
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L626
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L626
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L205
.L626:
	movss	xmm0, DWORD PTR controller_z[rip]
	movss	xmm1, DWORD PTR _x_controller_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L628
	ucomiss	xmm0, xmm1
	jne	.L628
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L630
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L630
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L630
	mov	eax, DWORD PTR controller_cnt[rip]
	mov	edx, DWORD PTR _x_controller_cnt[rip]
	sub	eax, edx
	cmp	eax, -1
	je	.L631
.L630:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L628
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L628
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L628
	mov	eax, DWORD PTR controller_cnt[rip]
	mov	edx, DWORD PTR _x_controller_cnt[rip]
	sub	eax, edx
	cmp	eax, 1
	jne	.L628
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 1
	jg	.L631
.L628:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L631
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L631
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L632
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L632
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L631
.L632:
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L631
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L631
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L631
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L205
.L631:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L633
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L633
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L633
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 1
	jne	.L633
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	test	eax, eax
	jne	.L633
	movss	xmm0, DWORD PTR _x_controller_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L633
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L634
.L633:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L634
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L634
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L636
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L636
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L634
.L636:
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L634
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L634
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L634
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	jne	.L205
.L634:
	movss	xmm0, DWORD PTR controller_z[rip]
	movss	xmm1, DWORD PTR _x_controller_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L637
	ucomiss	xmm0, xmm1
	jne	.L637
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	jne	.L639
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L640
.L639:
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L637
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L640
.L637:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L640
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L640
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L640
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L640
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L205
.L640:
	mov	eax, DWORD PTR controller_cnt[rip]
	mov	edx, DWORD PTR _x_controller_cnt[rip]
	sub	eax, edx
	cmp	eax, -1
	jne	.L641
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L641
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L641
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L641
	movss	xmm1, DWORD PTR controller_z[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L642
.L641:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L642
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L642
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L643
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L643
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L642
.L643:
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L642
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	jne	.L642
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L642
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L205
.L642:
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	jne	.L644
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L645
.L644:
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L646
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L645
.L646:
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L647
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L645
.L647:
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L205
.L645:
	movzx	eax, BYTE PTR _x_gate_evt0[rip]
	test	al, al
	jne	.L648
	movzx	eax, BYTE PTR _x_gate_evt1[rip]
	test	al, al
	je	.L649
.L648:
	movzx	eax, BYTE PTR _x_gate_evt0[rip]
	test	al, al
	je	.L650
	movzx	eax, BYTE PTR _x_gate_evt1[rip]
	test	al, al
	je	.L649
.L650:
	movzx	eax, BYTE PTR _x_gate_evt1[rip]
	test	al, al
	je	.L651
	movzx	eax, BYTE PTR _x_gate_evt0[rip]
	test	al, al
	je	.L649
.L651:
	movzx	eax, BYTE PTR _x_gate_evt0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_gate_evt1[rip]
	test	al, al
	je	.L205
.L649:
	movss	xmm1, DWORD PTR _x_gate_y[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L652
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L652
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L205
.L652:
	movss	xmm1, DWORD PTR _x_gate_y[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	jnb	.L653
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L653
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	jne	.L205
.L653:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L654
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L654
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR gate_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_gate_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L654
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L655
.L654:
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L657
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L205
.L657:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L205
.L655:
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L659
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	jne	.L659
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L659
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L659
	movss	xmm0, DWORD PTR _x_gate_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L659
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L660
.L659:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	jne	.L660
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	jne	.L660
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L660
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L660
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L205
.L660:
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L662
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	jne	.L662
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L662
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L662
	movss	xmm1, DWORD PTR gate_y[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jb	.L662
	movss	xmm0, DWORD PTR gate_y[rip]
	movss	xmm1, DWORD PTR _x_gate_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L662
	ucomiss	xmm0, xmm1
	je	.L664
.L662:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L664
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	jne	.L664
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L664
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L664
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L205
.L664:
	movss	xmm0, DWORD PTR _x_gate_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L666
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L666
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L666
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L666
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L666
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L668
.L666:
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L668
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	jne	.L668
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L668
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L668
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L205
.L668:
	movss	xmm0, DWORD PTR gate_y[rip]
	movss	xmm1, DWORD PTR _x_gate_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L669
	ucomiss	xmm0, xmm1
	jne	.L669
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	jne	.L669
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	jne	.L669
	movss	xmm0, DWORD PTR gate_y[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jb	.L669
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L669
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L669
	movss	xmm1, DWORD PTR gate_y[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	jnb	.L672
.L669:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L672
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L672
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L672
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L672
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L205
.L672:
	movss	xmm0, DWORD PTR _x_delta[rip]
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jb	.L205
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L674
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L675
.L674:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L675
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L675
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L205
.L675:
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L676
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L677
.L676:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L677
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L677
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L205
.L677:
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L678
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L679
.L678:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L679
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L679
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	jne	.L205
.L679:
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L680
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L681
.L680:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L681
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L681
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	jne	.L205
.L681:
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L682
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L683
.L682:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L683
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L683
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	jne	.L205
.L683:
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L684
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L685
.L684:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L685
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L685
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	jne	.L205
.L685:
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L686
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L687
.L686:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L687
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L687
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	jne	.L205
.L687:
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L688
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L689
.L688:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L689
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L689
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	jne	.L205
.L689:
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L690
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L691
.L690:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L691
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L691
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	jne	.L205
.L691:
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L692
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L693
.L692:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L693
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L693
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	jne	.L205
.L693:
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L694
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L695
.L694:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L695
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L695
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	jne	.L205
.L695:
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L696
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L697
.L696:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L697
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L697
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	jne	.L205
.L697:
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L698
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L699
.L698:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L699
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L699
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	jne	.L205
.L699:
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L700
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L701
.L700:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L701
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L701
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	jne	.L205
.L701:
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L702
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L702
	mov	eax, 1
	jmp	.L703
.L702:
	mov	eax, 0
.L703:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L704
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L704
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L704
	mov	eax, 1
	jmp	.L705
.L704:
	mov	eax, 0
.L705:
	and	eax, 1
	xor	eax, edx
	test	al, al
	jne	.L706
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L706
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L205
.L706:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L708
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L708
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L709
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L709
	mov	eax, 1
	jmp	.L710
.L709:
	mov	eax, 0
.L710:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	je	.L711
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L711
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L711
	mov	eax, 1
	jmp	.L712
.L711:
	mov	eax, 0
.L712:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L205
.L708:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L713
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L713
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L714
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L714
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L714
	mov	eax, 1
	jmp	.L715
.L714:
	mov	eax, 0
.L715:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	je	.L716
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L717
.L716:
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L718
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L717
.L718:
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L719
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L717
.L719:
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L720
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L717
.L720:
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L721
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L717
.L721:
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L722
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L717
.L722:
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L723
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L717
.L723:
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L724
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L717
.L724:
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L725
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L717
.L725:
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L726
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L717
.L726:
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L727
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L717
.L727:
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L728
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L717
.L728:
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L729
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L717
.L729:
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L730
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L730
.L717:
	mov	eax, 1
	jmp	.L731
.L730:
	mov	eax, 0
.L731:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L205
.L713:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L732
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L732
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L733
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L733
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L733
	mov	eax, 1
	jmp	.L734
.L733:
	mov	eax, 0
.L734:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L735
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	je	.L736
.L735:
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L737
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L736
.L737:
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L738
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L736
.L738:
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L739
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L736
.L739:
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L740
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L736
.L740:
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L741
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L736
.L741:
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L742
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L736
.L742:
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L743
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L736
.L743:
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L744
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L736
.L744:
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L745
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L736
.L745:
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L746
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L736
.L746:
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L747
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L736
.L747:
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L748
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L736
.L748:
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L749
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L749
.L736:
	mov	eax, 1
	jmp	.L750
.L749:
	mov	eax, 0
.L750:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L205
.L732:
	movss	xmm0, DWORD PTR delta[rip]
	movss	xmm1, DWORD PTR _x__diverge_delta[rip]
	ucomiss	xmm0, xmm1
	jp	.L828
	ucomiss	xmm0, xmm1
	je	.L751
.L828:
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L205
.L751:
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L753
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x__diverge_delta[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L205
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L205
.L753:
	mov	eax, 1
	jmp	.L755
.L205:
	mov	eax, 0
.L755:
	mov	DWORD PTR -4[rbp], eax
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	mov	BYTE PTR t13_l1[rip], al
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	mov	BYTE PTR t13_l0[rip], al
	movzx	eax, BYTE PTR _x_t13_evt1[rip]
	mov	BYTE PTR t13_evt1[rip], al
	movzx	eax, BYTE PTR _x_t13_evt0[rip]
	mov	BYTE PTR t13_evt0[rip], al
	movss	xmm0, DWORD PTR _x_t13_x[rip]
	movss	DWORD PTR t13_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	mov	BYTE PTR t12_l1[rip], al
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	mov	BYTE PTR t12_l0[rip], al
	movzx	eax, BYTE PTR _x_t12_evt1[rip]
	mov	BYTE PTR t12_evt1[rip], al
	movzx	eax, BYTE PTR _x_t12_evt0[rip]
	mov	BYTE PTR t12_evt0[rip], al
	movss	xmm0, DWORD PTR _x_t12_x[rip]
	movss	DWORD PTR t12_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	mov	BYTE PTR t11_l1[rip], al
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	mov	BYTE PTR t11_l0[rip], al
	movzx	eax, BYTE PTR _x_t11_evt1[rip]
	mov	BYTE PTR t11_evt1[rip], al
	movzx	eax, BYTE PTR _x_t11_evt0[rip]
	mov	BYTE PTR t11_evt0[rip], al
	movss	xmm0, DWORD PTR _x_t11_x[rip]
	movss	DWORD PTR t11_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t10_evt1[rip]
	mov	BYTE PTR t10_evt1[rip], al
	movzx	eax, BYTE PTR _x_t10_evt0[rip]
	mov	BYTE PTR t10_evt0[rip], al
	movss	xmm0, DWORD PTR _x_t10_x[rip]
	movss	DWORD PTR t10_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	mov	BYTE PTR t9_l1[rip], al
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	mov	BYTE PTR t9_l0[rip], al
	movzx	eax, BYTE PTR _x_t9_evt1[rip]
	mov	BYTE PTR t9_evt1[rip], al
	movzx	eax, BYTE PTR _x_t9_evt0[rip]
	mov	BYTE PTR t9_evt0[rip], al
	movss	xmm0, DWORD PTR _x_t3_x[rip]
	movss	DWORD PTR t3_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t2_evt1[rip]
	mov	BYTE PTR t2_evt1[rip], al
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	mov	BYTE PTR controller_l1[rip], al
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	mov	BYTE PTR t2_l0[rip], al
	movzx	eax, BYTE PTR _x_t2_evt0[rip]
	mov	BYTE PTR t2_evt0[rip], al
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	mov	BYTE PTR t1_l1[rip], al
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	mov	BYTE PTR controller_l0[rip], al
	movss	xmm0, DWORD PTR _x_t2_x[rip]
	movss	DWORD PTR t2_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t1_evt1[rip]
	mov	BYTE PTR t1_evt1[rip], al
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	mov	BYTE PTR controller_evt0[rip], al
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	mov	BYTE PTR t1_l0[rip], al
	movss	xmm0, DWORD PTR _x_t1_x[rip]
	movss	DWORD PTR t1_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	mov	BYTE PTR t2_l1[rip], al
	movzx	eax, BYTE PTR _x_t3_evt0[rip]
	mov	BYTE PTR t3_evt0[rip], al
	movss	xmm0, DWORD PTR _x_delta[rip]
	movss	DWORD PTR delta[rip], xmm0
	movzx	eax, BYTE PTR _x_t0_evt0[rip]
	mov	BYTE PTR t0_evt0[rip], al
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	mov	BYTE PTR gate_l0[rip], al
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	mov	BYTE PTR t5_l0[rip], al
	movzx	eax, BYTE PTR _x_t0_evt1[rip]
	mov	BYTE PTR t0_evt1[rip], al
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	mov	BYTE PTR gate_l1[rip], al
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	mov	BYTE PTR t5_l1[rip], al
	movzx	eax, BYTE PTR _x_t6_evt0[rip]
	mov	BYTE PTR t6_evt0[rip], al
	movss	xmm0, DWORD PTR _x_gate_y[rip]
	movss	DWORD PTR gate_y[rip], xmm0
	movzx	eax, BYTE PTR _x_t4_evt1[rip]
	mov	BYTE PTR t4_evt1[rip], al
	movss	xmm0, DWORD PTR _x_t5_x[rip]
	movss	DWORD PTR t5_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	mov	BYTE PTR t4_l1[rip], al
	movzx	eax, BYTE PTR _x_t5_evt0[rip]
	mov	BYTE PTR t5_evt0[rip], al
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	mov	BYTE PTR t0_l0[rip], al
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	mov	BYTE PTR t0_l1[rip], al
	movzx	eax, BYTE PTR _x_t1_evt0[rip]
	mov	BYTE PTR t1_evt0[rip], al
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	mov	BYTE PTR t10_l0[rip], al
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	mov	BYTE PTR controller_evt1[rip], al
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	mov	BYTE PTR t8_l0[rip], al
	movzx	eax, BYTE PTR _x_gate_evt1[rip]
	mov	BYTE PTR gate_evt1[rip], al
	movzx	eax, BYTE PTR _x_t5_evt1[rip]
	mov	BYTE PTR t5_evt1[rip], al
	movss	xmm0, DWORD PTR _x_t6_x[rip]
	movss	DWORD PTR t6_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_controller_z[rip]
	movss	DWORD PTR controller_z[rip], xmm0
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	mov	BYTE PTR t6_l0[rip], al
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	mov	BYTE PTR t10_l1[rip], al
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	mov	BYTE PTR controller_evt2[rip], al
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	mov	BYTE PTR t8_l1[rip], al
	movzx	eax, BYTE PTR _x_gate_evt0[rip]
	mov	BYTE PTR gate_evt0[rip], al
	movss	xmm0, DWORD PTR _x_t0_x[rip]
	movss	DWORD PTR t0_x[rip], xmm0
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	mov	DWORD PTR controller_cnt[rip], eax
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	mov	BYTE PTR t6_l1[rip], al
	movzx	eax, BYTE PTR _x_t7_evt0[rip]
	mov	BYTE PTR t7_evt0[rip], al
	movzx	eax, BYTE PTR _x_t3_evt1[rip]
	mov	BYTE PTR t3_evt1[rip], al
	movss	xmm0, DWORD PTR _x_t4_x[rip]
	movss	DWORD PTR t4_x[rip], xmm0
	movss	xmm0, DWORD PTR _x__diverge_delta[rip]
	movss	DWORD PTR _diverge_delta[rip], xmm0
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	mov	BYTE PTR t3_l0[rip], al
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	mov	BYTE PTR t3_l1[rip], al
	movzx	eax, BYTE PTR _x_t4_evt0[rip]
	mov	BYTE PTR t4_evt0[rip], al
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	mov	BYTE PTR t4_l0[rip], al
	movzx	eax, BYTE PTR _x_t6_evt1[rip]
	mov	BYTE PTR t6_evt1[rip], al
	movss	xmm0, DWORD PTR _x_t7_x[rip]
	movss	DWORD PTR t7_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t7_evt1[rip]
	mov	BYTE PTR t7_evt1[rip], al
	movss	xmm0, DWORD PTR _x_t8_x[rip]
	movss	DWORD PTR t8_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	mov	BYTE PTR t7_l0[rip], al
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	mov	BYTE PTR t7_l1[rip], al
	movzx	eax, BYTE PTR _x_t8_evt0[rip]
	mov	BYTE PTR t8_evt0[rip], al
	movzx	eax, BYTE PTR _x_t8_evt1[rip]
	mov	BYTE PTR t8_evt1[rip], al
	movss	xmm0, DWORD PTR _x_t9_x[rip]
	movss	DWORD PTR t9_x[rip], xmm0
.L200:
	cmp	DWORD PTR -4[rbp], 0
	jne	.L756
	mov	eax, 0
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	main, .-main
	.section	.rodata
	.align 4
.LC1:
	.long	1084227584
	.align 4
.LC2:
	.long	1065353216
	.align 4
.LC3:
	.long	1073741824
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"76526.c"
	.text
	.align	2
	.global	__VERIFIER_nondet_bool
	.syntax unified
	.arm
	.fpu softvfp
	.type	__VERIFIER_nondet_bool, %function
__VERIFIER_nondet_bool:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	mov	r0, r3
	pop	{fp, pc}
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.comm	t13_l1,1,1
	.comm	_x_t13_l1,1,1
	.comm	t13_l0,1,1
	.comm	_x_t13_l0,1,1
	.comm	t13_evt1,1,1
	.comm	_x_t13_evt1,1,1
	.comm	t13_evt0,1,1
	.comm	_x_t13_evt0,1,1
	.comm	t13_x,4,4
	.comm	_x_t13_x,4,4
	.comm	t12_l1,1,1
	.comm	_x_t12_l1,1,1
	.comm	t12_l0,1,1
	.comm	_x_t12_l0,1,1
	.comm	t12_evt1,1,1
	.comm	_x_t12_evt1,1,1
	.comm	t12_evt0,1,1
	.comm	_x_t12_evt0,1,1
	.comm	t12_x,4,4
	.comm	_x_t12_x,4,4
	.comm	t11_l1,1,1
	.comm	_x_t11_l1,1,1
	.comm	t11_l0,1,1
	.comm	_x_t11_l0,1,1
	.comm	t11_evt1,1,1
	.comm	_x_t11_evt1,1,1
	.comm	t11_evt0,1,1
	.comm	_x_t11_evt0,1,1
	.comm	t11_x,4,4
	.comm	_x_t11_x,4,4
	.comm	t10_evt1,1,1
	.comm	_x_t10_evt1,1,1
	.comm	t10_evt0,1,1
	.comm	_x_t10_evt0,1,1
	.comm	t10_x,4,4
	.comm	_x_t10_x,4,4
	.comm	t9_l1,1,1
	.comm	_x_t9_l1,1,1
	.comm	t9_l0,1,1
	.comm	_x_t9_l0,1,1
	.comm	t9_evt1,1,1
	.comm	_x_t9_evt1,1,1
	.comm	t9_evt0,1,1
	.comm	_x_t9_evt0,1,1
	.comm	t3_x,4,4
	.comm	_x_t3_x,4,4
	.comm	t2_evt1,1,1
	.comm	_x_t2_evt1,1,1
	.comm	controller_l1,1,1
	.comm	_x_controller_l1,1,1
	.comm	t2_l0,1,1
	.comm	_x_t2_l0,1,1
	.comm	t2_evt0,1,1
	.comm	_x_t2_evt0,1,1
	.comm	t1_l1,1,1
	.comm	_x_t1_l1,1,1
	.comm	controller_l0,1,1
	.comm	_x_controller_l0,1,1
	.comm	t2_x,4,4
	.comm	_x_t2_x,4,4
	.comm	t1_evt1,1,1
	.comm	_x_t1_evt1,1,1
	.comm	controller_evt0,1,1
	.comm	_x_controller_evt0,1,1
	.comm	t1_l0,1,1
	.comm	_x_t1_l0,1,1
	.comm	t1_x,4,4
	.comm	_x_t1_x,4,4
	.comm	t2_l1,1,1
	.comm	_x_t2_l1,1,1
	.comm	t3_evt0,1,1
	.comm	_x_t3_evt0,1,1
	.comm	delta,4,4
	.comm	_x_delta,4,4
	.comm	t0_evt0,1,1
	.comm	_x_t0_evt0,1,1
	.comm	gate_l0,1,1
	.comm	_x_gate_l0,1,1
	.comm	t5_l0,1,1
	.comm	_x_t5_l0,1,1
	.comm	t0_evt1,1,1
	.comm	_x_t0_evt1,1,1
	.comm	gate_l1,1,1
	.comm	_x_gate_l1,1,1
	.comm	t5_l1,1,1
	.comm	_x_t5_l1,1,1
	.comm	t6_evt0,1,1
	.comm	_x_t6_evt0,1,1
	.comm	gate_y,4,4
	.comm	_x_gate_y,4,4
	.comm	t4_evt1,1,1
	.comm	_x_t4_evt1,1,1
	.comm	t5_x,4,4
	.comm	_x_t5_x,4,4
	.comm	t4_l1,1,1
	.comm	_x_t4_l1,1,1
	.comm	t5_evt0,1,1
	.comm	_x_t5_evt0,1,1
	.comm	t0_l0,1,1
	.comm	_x_t0_l0,1,1
	.comm	t0_l1,1,1
	.comm	_x_t0_l1,1,1
	.comm	t1_evt0,1,1
	.comm	_x_t1_evt0,1,1
	.comm	t10_l0,1,1
	.comm	_x_t10_l0,1,1
	.comm	controller_evt1,1,1
	.comm	_x_controller_evt1,1,1
	.comm	t8_l0,1,1
	.comm	_x_t8_l0,1,1
	.comm	gate_evt1,1,1
	.comm	_x_gate_evt1,1,1
	.comm	t5_evt1,1,1
	.comm	_x_t5_evt1,1,1
	.comm	t6_x,4,4
	.comm	_x_t6_x,4,4
	.comm	controller_z,4,4
	.comm	_x_controller_z,4,4
	.comm	t6_l0,1,1
	.comm	_x_t6_l0,1,1
	.comm	t10_l1,1,1
	.comm	_x_t10_l1,1,1
	.comm	controller_evt2,1,1
	.comm	_x_controller_evt2,1,1
	.comm	t8_l1,1,1
	.comm	_x_t8_l1,1,1
	.comm	gate_evt0,1,1
	.comm	_x_gate_evt0,1,1
	.comm	t0_x,4,4
	.comm	_x_t0_x,4,4
	.comm	controller_cnt,4,4
	.comm	_x_controller_cnt,4,4
	.comm	t6_l1,1,1
	.comm	_x_t6_l1,1,1
	.comm	t7_evt0,1,1
	.comm	_x_t7_evt0,1,1
	.comm	t3_evt1,1,1
	.comm	_x_t3_evt1,1,1
	.comm	t4_x,4,4
	.comm	_x_t4_x,4,4
	.comm	_diverge_delta,4,4
	.comm	_x__diverge_delta,4,4
	.comm	t3_l0,1,1
	.comm	_x_t3_l0,1,1
	.comm	t3_l1,1,1
	.comm	_x_t3_l1,1,1
	.comm	t4_evt0,1,1
	.comm	_x_t4_evt0,1,1
	.comm	t4_l0,1,1
	.comm	_x_t4_l0,1,1
	.comm	t6_evt1,1,1
	.comm	_x_t6_evt1,1,1
	.comm	t7_x,4,4
	.comm	_x_t7_x,4,4
	.comm	t7_evt1,1,1
	.comm	_x_t7_evt1,1,1
	.comm	t8_x,4,4
	.comm	_x_t8_x,4,4
	.comm	t7_l0,1,1
	.comm	_x_t7_l0,1,1
	.comm	t7_l1,1,1
	.comm	_x_t7_l1,1,1
	.comm	t8_evt0,1,1
	.comm	_x_t8_evt0,1,1
	.comm	t8_evt1,1,1
	.comm	_x_t8_evt1,1,1
	.comm	t9_x,4,4
	.comm	_x_t9_x,4,4
	.global	__aeabi_fcmpeq
	.global	__aeabi_fcmple
	.global	__aeabi_fcmpge
	.global	__aeabi_f2d
	.global	__aeabi_dsub
	.global	__aeabi_dadd
	.global	__aeabi_dcmpeq
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, fp, lr}
	add	fp, sp, #20
	sub	sp, sp, #8
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+4
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+8
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+12
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L780+16
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+20
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+24
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+28
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+32
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L780+36
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+40
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+44
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+48
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+52
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L780+56
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+60
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+64
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L780+68
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+72
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+76
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+80
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+84
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L780+224
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+232
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+316
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+236
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+228
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+260
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+312
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L780+244
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+252
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+296
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+256
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L780+264
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+240
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+208
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L780+88
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+268
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+336
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+176
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+272
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+328
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+180
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+148
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L780+332
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+192
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L780+184
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+200
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+168
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+276
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+280
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+248
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+92
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+300
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+96
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+324
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+172
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L780+164
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L780+308
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+156
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+100
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+292
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+104
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+320
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L780+284
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L780+304
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+160
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+128
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+212
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L780+204
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L780+108
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+216
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+220
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+188
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+196
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+152
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L780+144
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+132
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L780+112
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+136
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+140
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+116
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L780+120
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L780+124
	str	r3, [r2]	@ float
	ldr	r3, .L780+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L6
	ldr	r3, .L780
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L6:
	ldr	r3, .L780+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L780
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L8:
	ldr	r3, .L780
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L9
	ldr	r3, .L780+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L9:
	ldr	r3, .L780+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L7:
	ldr	r3, .L780+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L10
	ldr	r3, .L780+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L11
.L10:
	ldr	r3, .L780+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L12
	ldr	r3, .L780+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L11
.L12:
	ldr	r3, .L780+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L13
	ldr	r3, .L780+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L11
.L13:
	ldr	r3, .L780+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L11:
	ldr	r3, .L780+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L14
	ldr	r3, .L780
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L15
.L14:
	ldr	r3, .L780+16
	ldr	r3, [r3]	@ float
	ldr	r1, .L780+288
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L15:
	ldr	r3, .L780+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+36
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L18
	ldr	r3, .L780+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L19
.L18:
	ldr	r3, .L780+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L20
	ldr	r3, .L780+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L19
.L20:
	ldr	r3, .L780+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L21
	ldr	r3, .L780+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L19
.L21:
	ldr	r3, .L780+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L19:
	ldr	r3, .L780+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L22
	ldr	r3, .L780+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L23
.L22:
	ldr	r3, .L780+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L24
	ldr	r3, .L780+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L23
.L24:
	ldr	r3, .L780+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L25
	ldr	r3, .L780+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L23
.L25:
	ldr	r3, .L780+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L23:
	ldr	r3, .L780+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L26
	ldr	r3, .L780+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L27
.L26:
	ldr	r3, .L780+36
	ldr	r3, [r3]	@ float
	ldr	r1, .L780+288
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L27:
	ldr	r3, .L780+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+56
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L30
	ldr	r3, .L780+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
.L30:
	ldr	r3, .L780+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L32
	ldr	r3, .L780+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
.L32:
	ldr	r3, .L780+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L33
	ldr	r3, .L780+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
.L33:
	ldr	r3, .L780+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L31:
	ldr	r3, .L780+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L34
	ldr	r3, .L780+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
.L34:
	ldr	r3, .L780+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L36
	ldr	r3, .L780+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
.L36:
	ldr	r3, .L780+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L37
	ldr	r3, .L780+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
.L37:
	ldr	r3, .L780+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L35:
	ldr	r3, .L780+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L38
	ldr	r3, .L780+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L39
.L38:
	ldr	r3, .L780+56
	ldr	r3, [r3]	@ float
	ldr	r1, .L780+288
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L39:
	ldr	r3, .L780+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L42
	ldr	r3, .L780+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L43
.L42:
	ldr	r3, .L780+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L44
	ldr	r3, .L780+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L43
.L44:
	ldr	r3, .L780+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L45
	ldr	r3, .L780+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L43
.L45:
	ldr	r3, .L780+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L43:
	ldr	r3, .L780+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L46
	ldr	r3, .L780+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L47
.L46:
	ldr	r3, .L780+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L48
	ldr	r3, .L780+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L47
.L48:
	ldr	r3, .L780+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L49
	ldr	r3, .L780+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L47
.L49:
	ldr	r3, .L780+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L47:
	ldr	r3, .L780+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L50
	ldr	r3, .L780+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L51
.L50:
	ldr	r3, .L780+68
	ldr	r3, [r3]	@ float
	ldr	r1, .L780+288
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L51:
	ldr	r3, .L780+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+124
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L54
	ldr	r3, .L780+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L55
.L54:
	ldr	r3, .L780+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L56
	ldr	r3, .L780+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L55
.L56:
	ldr	r3, .L780+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L57
	ldr	r3, .L780+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L55
.L57:
	ldr	r3, .L780+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L55:
	ldr	r3, .L780+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L58
	ldr	r3, .L780+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L58:
	ldr	r3, .L780+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L60
	ldr	r3, .L780+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L60:
	ldr	r3, .L780+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L780+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L61:
	ldr	r3, .L780+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L59:
	ldr	r3, .L780+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L62
	ldr	r3, .L780+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
.L62:
	ldr	r3, .L780+124
	ldr	r3, [r3]	@ float
	ldr	r1, .L780+288
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L63:
	ldr	r3, .L780+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L66
	ldr	r3, .L780+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L67
.L66:
	ldr	r3, .L780+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L68
	ldr	r3, .L780+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L67
.L68:
	ldr	r3, .L780+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L69
	ldr	r3, .L780+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L67
.L69:
	ldr	r3, .L780+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L67:
	ldr	r3, .L780+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L70
	ldr	r3, .L780+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L71
.L70:
	ldr	r3, .L780+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L72
	ldr	r3, .L780+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L71
.L72:
	ldr	r3, .L780+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L73
	ldr	r3, .L780+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L71
.L73:
	ldr	r3, .L780+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L71:
	ldr	r3, .L780+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L74
	ldr	r3, .L780+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L75
.L74:
	ldr	r3, .L780+112
	ldr	r3, [r3]	@ float
	ldr	r1, .L780+288
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L75:
	ldr	r3, .L780+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L78
	ldr	r3, .L780+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L79
.L78:
	ldr	r3, .L780+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L80
	ldr	r3, .L780+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L79
.L80:
	ldr	r3, .L780+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L780+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L79
.L81:
	ldr	r3, .L780+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	b	.L781
.L782:
	.align	2
.L780:
	.word	t13_l1
	.word	t13_l0
	.word	t13_evt1
	.word	t13_evt0
	.word	t13_x
	.word	t12_l1
	.word	t12_l0
	.word	t12_evt1
	.word	t12_evt0
	.word	t12_x
	.word	t11_l1
	.word	t11_l0
	.word	t11_evt1
	.word	t11_evt0
	.word	t11_x
	.word	t10_evt1
	.word	t10_evt0
	.word	t10_x
	.word	t9_l1
	.word	t9_l0
	.word	t9_evt1
	.word	t9_evt0
	.word	delta
	.word	t10_l0
	.word	t8_l0
	.word	t10_l1
	.word	t8_l1
	.word	_diverge_delta
	.word	t8_x
	.word	t8_evt0
	.word	t8_evt1
	.word	t9_x
	.word	t7_evt0
	.word	t7_evt1
	.word	t7_l0
	.word	t7_l1
	.word	t7_x
	.word	t6_evt0
	.word	t6_evt1
	.word	t6_l0
	.word	t6_l1
	.word	t6_x
	.word	t5_evt0
	.word	t5_evt1
	.word	t5_l0
	.word	t5_l1
	.word	t5_x
	.word	t4_evt0
	.word	t4_evt1
	.word	t4_l0
	.word	t4_l1
	.word	t4_x
	.word	t3_evt0
	.word	t3_evt1
	.word	t3_l0
	.word	t3_l1
	.word	t3_x
	.word	t2_evt0
	.word	t2_evt1
	.word	t2_l0
	.word	t2_l1
	.word	t2_x
	.word	t1_evt0
	.word	t1_evt1
	.word	t1_l0
	.word	t1_l1
	.word	t1_x
	.word	t0_evt0
	.word	t0_evt1
	.word	t0_l0
	.word	t0_l1
	.word	t0_x
	.word	1084227584
	.word	controller_evt2
	.word	controller_evt0
	.word	controller_evt1
	.word	controller_cnt
	.word	controller_z
	.word	controller_l0
	.word	controller_l1
	.word	gate_evt0
	.word	gate_evt1
	.word	gate_l1
	.word	gate_y
	.word	gate_l0
.L781:
.L79:
	ldr	r3, .L780+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L82
	ldr	r3, .L780+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L83
.L82:
	ldr	r3, .L780+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L84
	ldr	r3, .L780+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L83
.L84:
	ldr	r3, .L780+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L85
	ldr	r3, .L780+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L83
.L85:
	ldr	r3, .L780+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L83:
	ldr	r3, .L780+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L86
	ldr	r3, .L780+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L87
.L86:
	ldr	r3, .L780+144
	ldr	r3, [r3]	@ float
	ldr	r1, .L780+288
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L87:
	ldr	r3, .L780+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+164
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L90
	ldr	r3, .L780+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L91
.L90:
	ldr	r3, .L780+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L92
	ldr	r3, .L780+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L91
.L92:
	ldr	r3, .L780+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L93
	ldr	r3, .L780+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L91
.L93:
	ldr	r3, .L780+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L91:
	ldr	r3, .L780+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L94
	ldr	r3, .L780+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L95
.L94:
	ldr	r3, .L780+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L96
	ldr	r3, .L780+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L95
.L96:
	ldr	r3, .L780+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L97
	ldr	r3, .L780+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L95
.L97:
	ldr	r3, .L780+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L95:
	ldr	r3, .L780+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L98
	ldr	r3, .L780+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L99
.L98:
	ldr	r3, .L780+164
	ldr	r3, [r3]	@ float
	ldr	r1, .L780+288
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L99:
	ldr	r3, .L780+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+184
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L102
	ldr	r3, .L780+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L103
.L102:
	ldr	r3, .L780+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L104
	ldr	r3, .L780+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L103
.L104:
	ldr	r3, .L780+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L105
	ldr	r3, .L780+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L103
.L105:
	ldr	r3, .L780+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L103:
	ldr	r3, .L780+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L106
	ldr	r3, .L780+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L107
.L106:
	ldr	r3, .L780+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L108
	ldr	r3, .L780+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L107
.L108:
	ldr	r3, .L780+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L109
	ldr	r3, .L780+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L107
.L109:
	ldr	r3, .L780+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L107:
	ldr	r3, .L780+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L110
	ldr	r3, .L780+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L111
.L110:
	ldr	r3, .L780+184
	ldr	r3, [r3]	@ float
	ldr	r1, .L780+288
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L111:
	ldr	r3, .L780+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L114
	ldr	r3, .L780+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L115
.L114:
	ldr	r3, .L780+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L116
	ldr	r3, .L780+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L115
.L116:
	ldr	r3, .L780+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L117
	ldr	r3, .L780+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L115
.L117:
	ldr	r3, .L780+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L115:
	ldr	r3, .L780+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L118
	ldr	r3, .L780+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L119
.L118:
	ldr	r3, .L780+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L120
	ldr	r3, .L780+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L119
.L120:
	ldr	r3, .L780+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L121
	ldr	r3, .L780+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L119
.L121:
	ldr	r3, .L780+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L119:
	ldr	r3, .L780+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L122
	ldr	r3, .L780+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L123
.L122:
	ldr	r3, .L780+204
	ldr	r3, [r3]	@ float
	ldr	r1, .L780+288
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L123:
	ldr	r3, .L780+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L126
	ldr	r3, .L780+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L127
.L126:
	ldr	r3, .L780+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L128
	ldr	r3, .L780+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L127
.L128:
	ldr	r3, .L780+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L129
	ldr	r3, .L780+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L127
.L129:
	ldr	r3, .L780+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L127:
	ldr	r3, .L780+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L130
	ldr	r3, .L780+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L131
.L130:
	ldr	r3, .L780+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L132
	ldr	r3, .L780+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L131
.L132:
	ldr	r3, .L780+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L133
	ldr	r3, .L780+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L131
.L133:
	ldr	r3, .L780+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L131:
	ldr	r3, .L780+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L134
	ldr	r3, .L780+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L135
.L134:
	ldr	r3, .L780+224
	ldr	r3, [r3]	@ float
	ldr	r1, .L780+288
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L135:
	ldr	r3, .L780+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+244
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L138
	ldr	r3, .L780+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L139
.L138:
	ldr	r3, .L780+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L140
	ldr	r3, .L780+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L139
.L140:
	ldr	r3, .L780+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L141
	ldr	r3, .L780+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L139
.L141:
	ldr	r3, .L780+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L139:
	ldr	r3, .L780+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L142
	ldr	r3, .L780+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L143
.L142:
	ldr	r3, .L780+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L144
	ldr	r3, .L780+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L143
.L144:
	ldr	r3, .L780+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L145
	ldr	r3, .L780+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L143
.L145:
	ldr	r3, .L780+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L143:
	ldr	r3, .L780+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L146
	ldr	r3, .L780+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L147
.L146:
	ldr	r3, .L780+244
	ldr	r3, [r3]	@ float
	ldr	r1, .L780+288
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L147:
	ldr	r3, .L780+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+264
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L150
	ldr	r3, .L780+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
.L150:
	ldr	r3, .L780+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L152
	ldr	r3, .L780+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
.L152:
	ldr	r3, .L780+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L153
	ldr	r3, .L780+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
.L153:
	ldr	r3, .L780+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L151:
	ldr	r3, .L780+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L154
	ldr	r3, .L780+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L155
.L154:
	ldr	r3, .L780+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L156
	ldr	r3, .L780+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L155
.L156:
	ldr	r3, .L780+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L157
	ldr	r3, .L780+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L155
.L157:
	ldr	r3, .L780+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L155:
	ldr	r3, .L780+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L158
	ldr	r3, .L780+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L159
.L158:
	ldr	r3, .L780+264
	ldr	r3, [r3]	@ float
	ldr	r1, .L780+288
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L159:
	ldr	r3, .L780+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+284
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L162
	ldr	r3, .L780+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L163
.L162:
	ldr	r3, .L780+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L164
	ldr	r3, .L780+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L163
.L164:
	ldr	r3, .L780+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L165
	ldr	r3, .L780+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L163
.L165:
	ldr	r3, .L780+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L163:
	ldr	r3, .L780+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L166
	ldr	r3, .L780+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L167
.L166:
	ldr	r3, .L780+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L168
	ldr	r3, .L780+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L167
.L168:
	ldr	r3, .L780+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L169
	ldr	r3, .L780+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L167
.L169:
	ldr	r3, .L780+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L167:
	ldr	r3, .L780+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L170
	ldr	r3, .L780+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L171
.L170:
	ldr	r3, .L780+284
	ldr	r3, [r3]	@ float
	ldr	r1, .L780+288
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L171:
	ldr	r3, .L780+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+308
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L174
	ldr	r3, .L780+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L175
.L174:
	ldr	r3, .L780+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L176
	ldr	r3, .L780+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L175
.L176:
	ldr	r3, .L780+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L177
	ldr	r3, .L780+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L175
.L177:
	ldr	r3, .L780+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L175:
	ldr	r3, .L780+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L178
	ldr	r3, .L780+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L178
	ldr	r3, .L780+300
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L179
.L178:
	ldr	r3, .L780+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L180
	ldr	r3, .L780+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L180
	ldr	r3, .L780+300
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L179
.L180:
	ldr	r3, .L780+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L181
	ldr	r3, .L780+300
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L181
	ldr	r3, .L780+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L179
.L181:
	ldr	r3, .L780+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L182
	ldr	r3, .L780+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L182
	ldr	r3, .L780+300
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L179
.L182:
	ldr	r3, .L780+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+300
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L179:
	ldr	r3, .L780+304
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L183
	ldr	r3, .L780+304
	ldr	r3, [r3]
	cmp	r3, #1
	beq	.L183
	ldr	r3, .L780+304
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L183
	ldr	r3, .L780+304
	ldr	r3, [r3]
	cmp	r3, #3
	beq	.L183
	ldr	r3, .L780+304
	ldr	r3, [r3]
	cmp	r3, #4
	beq	.L183
	ldr	r3, .L780+304
	ldr	r3, [r3]
	cmp	r3, #5
	beq	.L183
	ldr	r3, .L780+304
	ldr	r3, [r3]
	cmp	r3, #6
	beq	.L183
	ldr	r3, .L780+304
	ldr	r3, [r3]
	cmp	r3, #7
	beq	.L183
	ldr	r3, .L780+304
	ldr	r3, [r3]
	cmp	r3, #8
	beq	.L183
	ldr	r3, .L780+304
	ldr	r3, [r3]
	cmp	r3, #9
	beq	.L183
	ldr	r3, .L780+304
	ldr	r3, [r3]
	cmp	r3, #10
	beq	.L183
	ldr	r3, .L780+304
	ldr	r3, [r3]
	cmp	r3, #11
	beq	.L183
	ldr	r3, .L780+304
	ldr	r3, [r3]
	cmp	r3, #12
	beq	.L183
	ldr	r3, .L780+304
	ldr	r3, [r3]
	cmp	r3, #13
	beq	.L183
	ldr	r3, .L780+304
	ldr	r3, [r3]
	cmp	r3, #14
	beq	.L183
	ldr	r3, .L780+304
	ldr	r3, [r3]
	cmp	r3, #15
	bne	.L4
.L183:
	ldr	r3, .L780+308
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L184
	ldr	r3, .L780+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L185
	ldr	r3, .L780+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L185:
	ldr	r3, .L780+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L184
	ldr	r3, .L780+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L184:
	ldr	r3, .L780+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L780+332
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L187
	ldr	r3, .L780+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L188
.L187:
	ldr	r3, .L780+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L189
	ldr	r3, .L780+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L188
.L189:
	ldr	r3, .L780+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L190
	ldr	r3, .L780+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L188
.L190:
	ldr	r3, .L780+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L188:
	ldr	r3, .L780+320
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L191
	ldr	r3, .L780+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L192
.L191:
	ldr	r3, .L780+320
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L780+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L192
.L193:
	ldr	r3, .L780+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L194
	ldr	r3, .L780+320
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L192
.L194:
	ldr	r3, .L780+320
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L780+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L192:
	ldr	r3, .L780+332
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L780+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L780+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L195:
	ldr	r3, .L780+332
	ldr	r3, [r3]	@ float
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L196
	ldr	r3, .L780+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L196
	ldr	r3, .L783
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L196:
	ldr	r3, .L783+368
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L783+368
	ldr	r3, [r3]	@ float
	ldr	r2, .L783+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	mov	r3, #1
	b	.L199
.L4:
	mov	r3, #0
.L199:
	str	r3, [fp, #-24]
	b	.L200
.L784:
	.align	2
.L783:
	.word	gate_l1
	.word	_diverge_delta
	.word	_x_t11_l1
	.word	_x_t11_l0
	.word	_x_t11_evt1
	.word	_x_t11_evt0
	.word	_x_t11_x
	.word	_x_t10_evt1
	.word	_x_t10_evt0
	.word	_x_t10_x
	.word	_x_t9_l1
	.word	_x_t9_l0
	.word	_x_t9_evt1
	.word	_x_t9_evt0
	.word	_x_t3_x
	.word	_x_t2_evt1
	.word	_x_controller_l1
	.word	_x_t2_l0
	.word	_x_t2_evt0
	.word	_x_t1_l1
	.word	_x_controller_l0
	.word	_x_t2_x
	.word	_x_t1_evt1
	.word	_x_controller_evt0
	.word	_x_t1_l0
	.word	_x_t1_x
	.word	_x_t2_l1
	.word	_x_t3_evt0
	.word	_x_delta
	.word	_x_t0_evt0
	.word	_x_gate_l0
	.word	_x_t5_l0
	.word	_x_t0_evt1
	.word	_x_gate_l1
	.word	_x_t5_l1
	.word	_x_t6_evt0
	.word	_x_gate_y
	.word	_x_t4_evt1
	.word	_x_t5_x
	.word	_x_t4_l1
	.word	_x_t5_evt0
	.word	_x_t0_l0
	.word	_x_t0_l1
	.word	_x_t1_evt0
	.word	_x_t10_l0
	.word	_x_controller_evt1
	.word	_x_t8_l0
	.word	_x_gate_evt1
	.word	_x_t5_evt1
	.word	_x_t6_x
	.word	_x_controller_z
	.word	_x_t6_l0
	.word	_x_t10_l1
	.word	_x_controller_evt2
	.word	_x_t8_l1
	.word	_x_gate_evt0
	.word	_x_t0_x
	.word	_x_controller_cnt
	.word	_x_t6_l1
	.word	_x_t7_evt0
	.word	_x_t3_evt1
	.word	_x_t4_x
	.word	_x__diverge_delta
	.word	_x_t3_l0
	.word	_x_t3_l1
	.word	_x_t4_evt0
	.word	_x_t4_l0
	.word	_x_t6_evt1
	.word	_x_t7_x
	.word	_x_t7_evt1
	.word	_x_t8_x
	.word	_x_t7_l0
	.word	_x_t7_l1
	.word	_x_t8_evt0
	.word	_x_t8_evt1
	.word	_x_t9_x
	.word	_x_t13_evt0
	.word	_x_t13_evt1
	.word	_x_t13_l0
	.word	_x_t13_l1
	.word	t13_x
	.word	_x_t13_x
	.word	t13_l0
	.word	t13_l1
	.word	t13_evt0
	.word	t13_evt1
	.word	_x_t12_evt0
	.word	_x_t12_evt1
	.word	1084227584
	.word	_x_t12_x
	.word	t12_l0
	.word	t12_l1
	.word	delta
	.word	t12_evt0
	.word	t12_evt1
	.word	_x_t12_l1
	.word	_x_t12_l0
	.word	t12_x
.L708:
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+316
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+312
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+308
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+304
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L783+324
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+380
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+384
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+348
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+344
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L783+356
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+8
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+12
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+16
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+20
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L783+24
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+28
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+32
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L783+36
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+40
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+44
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+48
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+52
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L783+56
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+60
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+64
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+68
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+72
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+76
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+80
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L783+84
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+88
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+92
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+96
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L783+100
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+104
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+108
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L783+112
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+116
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+120
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+124
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+128
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+132
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+136
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+140
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L783+144
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+148
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L783+152
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+156
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+160
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+164
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+168
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+172
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+176
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+180
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+184
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+188
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+192
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L783+196
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L783+200
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+204
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+208
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+212
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+216
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+220
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L783+224
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L783+228
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+232
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+236
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+240
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L783+244
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L783+248
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+252
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+256
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+260
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+264
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+268
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L783+272
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+276
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L783+280
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+284
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+288
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+292
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L783+296
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L783+300
	str	r3, [r2]	@ float
	ldr	r3, .L783+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L201
	ldr	r3, .L783+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L202
.L201:
	ldr	r3, .L783+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L203
	ldr	r3, .L783+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L202
.L203:
	ldr	r3, .L783+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L204
	ldr	r3, .L783+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L202
.L204:
	ldr	r3, .L783+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L783+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L202:
	ldr	r3, .L783+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L206
	ldr	r3, .L783+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L207
.L206:
	ldr	r3, .L783+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L208
	ldr	r3, .L783+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L207
.L208:
	ldr	r3, .L783+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L209
	ldr	r3, .L783+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L207
.L209:
	ldr	r3, .L783+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L783+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L207:
	ldr	r3, .L783+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L210
	ldr	r3, .L783+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L211
.L210:
	ldr	r3, .L783+324
	ldr	r3, [r3]	@ float
	ldr	r1, .L783+352
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
.L211:
	ldr	r3, .L783+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L783+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L213
	ldr	r3, .L783+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L783+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L213
	ldr	r3, .L783+368
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L783+320
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L783+324
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L214
.L213:
	ldr	r3, .L783+368
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L783+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L214
	ldr	r3, .L783+340
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L214:
	ldr	r3, .L783+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L216
	ldr	r3, .L783+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L216
	ldr	r3, .L783+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L216
	ldr	r3, .L783+340
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L216
	ldr	r3, .L783+324
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L217
.L216:
	ldr	r3, .L783+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L217
	ldr	r3, .L783+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L217
	ldr	r3, .L783+368
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L217
	ldr	r3, .L783+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L783+340
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L217:
	ldr	r3, .L783+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L218
	ldr	r3, .L783+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L218
	ldr	r3, .L783+320
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L219
	mov	r3, #0
	mov	r4, r3
.L219:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L218
	ldr	r3, .L783+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L218
	ldr	r3, .L783+340
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L218
	ldr	r3, .L783+320
	ldr	r3, [r3]	@ float
	ldr	r2, .L783+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L220
.L218:
	ldr	r3, .L783+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L220
	ldr	r3, .L783+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L220
	ldr	r3, .L783+368
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L220
	ldr	r3, .L783+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L783+340
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L220:
	ldr	r3, .L783+320
	ldr	r3, [r3]	@ float
	ldr	r2, .L783+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L221
	ldr	r3, .L783+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L221
	ldr	r3, .L783+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L221
	ldr	r3, .L783+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L221
	ldr	r3, .L783+340
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L223
.L221:
	ldr	r3, .L783+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L223
	ldr	r3, .L783+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L223
	ldr	r3, .L783+368
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L223
	ldr	r3, .L783+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L783+340
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L223:
	ldr	r3, .L783+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L224
	ldr	r3, .L783+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L224
	ldr	r3, .L783+320
	ldr	r3, [r3]	@ float
	ldr	r1, .L783+352
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L224
	ldr	r3, .L783+340
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L224
	ldr	r3, .L783+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L224
	ldr	r3, .L783+320
	ldr	r3, [r3]	@ float
	ldr	r2, .L783+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L226
.L224:
	ldr	r3, .L783+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L226
	ldr	r3, .L783+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L226
	ldr	r3, .L783+368
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L226
	ldr	r3, .L783+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L783+340
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L226:
	ldr	r3, .L783+384
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L227
	ldr	r3, .L783+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L228
.L227:
	ldr	r3, .L783+384
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L229
	ldr	r3, .L783+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L228
.L229:
	ldr	r3, .L783+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L230
	ldr	r3, .L783+384
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L228
.L230:
	ldr	r3, .L783+384
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L783+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L228:
	ldr	r3, .L783+344
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L231
	ldr	r3, .L783+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L232
.L231:
	ldr	r3, .L783+344
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L233
	ldr	r3, .L783+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L232
.L233:
	ldr	r3, .L783+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L234
	ldr	r3, .L783+344
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L232
.L234:
	ldr	r3, .L783+344
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L783+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L232:
	ldr	r3, .L783+384
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L235
	ldr	r3, .L783+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L236
.L235:
	ldr	r3, .L783+356
	ldr	r3, [r3]	@ float
	ldr	r1, .L783+352
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
.L236:
	ldr	r3, .L783+360
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L783+384
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L238
	ldr	r3, .L783+364
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L783+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L238
	ldr	r3, .L783+368
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L783+388
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L783+356
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L239
.L238:
	ldr	r3, .L783+368
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L783+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L239
	ldr	r3, .L783+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L239:
	ldr	r3, .L783+384
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L783+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L783+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L783+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L783+356
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L242
.L241:
	ldr	r3, .L783+360
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L242
	ldr	r3, .L783+364
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L242
	ldr	r3, .L783+368
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L242
	ldr	r3, .L783+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L783+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L242:
	ldr	r3, .L783+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L243
	ldr	r3, .L783+384
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L243
	ldr	r3, .L783+388
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L244
	mov	r3, #0
	mov	r4, r3
.L244:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L243
	ldr	r3, .L785
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L243
	ldr	r3, .L785+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L243
	ldr	r3, .L785+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L785+12
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L245
.L243:
	ldr	r3, .L785+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L785+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L785+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L785
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L785+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L245:
	ldr	r3, .L785+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L785+12
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L246
	ldr	r3, .L785+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L246
	ldr	r3, .L785+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L246
	ldr	r3, .L785
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L246
	ldr	r3, .L785+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L248
.L246:
	ldr	r3, .L785+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L248
	ldr	r3, .L785+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L248
	ldr	r3, .L785+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L248
	ldr	r3, .L785
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L785+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L248:
	ldr	r3, .L785+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L249
	ldr	r3, .L785+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L249
	ldr	r3, .L785+8
	ldr	r3, [r3]	@ float
	ldr	r1, .L785+236
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L249
	ldr	r3, .L785+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L249
	ldr	r3, .L785
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L249
	ldr	r3, .L785+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L785+12
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L251
.L249:
	ldr	r3, .L785+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L251
	ldr	r3, .L785+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L251
	ldr	r3, .L785+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L251
	ldr	r3, .L785
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L785+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L251:
	ldr	r3, .L785+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L252
	ldr	r3, .L785+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L252:
	ldr	r3, .L785+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L254
	ldr	r3, .L785+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L254:
	ldr	r3, .L785+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L255
	ldr	r3, .L785+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L255:
	ldr	r3, .L785+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L785+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L253:
	ldr	r3, .L785+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L256
	ldr	r3, .L785+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L257
.L256:
	ldr	r3, .L785+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L258
	ldr	r3, .L785+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L257
.L258:
	ldr	r3, .L785+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L259
	ldr	r3, .L785+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L257
.L259:
	ldr	r3, .L785+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L785+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L257:
	ldr	r3, .L785+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L260
	ldr	r3, .L785+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L261
.L260:
	ldr	r3, .L785+52
	ldr	r3, [r3]	@ float
	ldr	r1, .L785+236
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
.L261:
	ldr	r3, .L785+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L785+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L263
	ldr	r3, .L785+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L785+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L263
	ldr	r3, .L785+24
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L785+64
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L785+52
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L264
.L263:
	ldr	r3, .L785+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L785+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L264
	ldr	r3, .L785+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L264:
	ldr	r3, .L785+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L266
	ldr	r3, .L785+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L266
	ldr	r3, .L785+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L266
	ldr	r3, .L785+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L266
	ldr	r3, .L785+52
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L267
.L266:
	ldr	r3, .L785+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L267
	ldr	r3, .L785+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L267
	ldr	r3, .L785+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L267
	ldr	r3, .L785+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L785+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L267:
	ldr	r3, .L785+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L268
	ldr	r3, .L785+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L268
	ldr	r3, .L785+64
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L269
	mov	r3, #0
	mov	r4, r3
.L269:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L268
	ldr	r3, .L785+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L268
	ldr	r3, .L785+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L268
	ldr	r3, .L785+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L785+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L270
.L268:
	ldr	r3, .L785+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L270
	ldr	r3, .L785+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L270
	ldr	r3, .L785+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L270
	ldr	r3, .L785+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L785+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L270:
	ldr	r3, .L785+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L785+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L271
	ldr	r3, .L785+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L271
	ldr	r3, .L785+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L271
	ldr	r3, .L785+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L271
	ldr	r3, .L785+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L273
.L271:
	ldr	r3, .L785+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L273
	ldr	r3, .L785+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L273
	ldr	r3, .L785+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L273
	ldr	r3, .L785+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L785+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L273:
	ldr	r3, .L785+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L274
	ldr	r3, .L785+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L274
	ldr	r3, .L785+64
	ldr	r3, [r3]	@ float
	ldr	r1, .L785+236
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L274
	ldr	r3, .L785+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L274
	ldr	r3, .L785+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L274
	ldr	r3, .L785+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L785+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L276
.L274:
	ldr	r3, .L785+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L276
	ldr	r3, .L785+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L276
	ldr	r3, .L785+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L276
	ldr	r3, .L785+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L785+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L276:
	ldr	r3, .L785+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L277
	ldr	r3, .L785+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L278
.L277:
	ldr	r3, .L785+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L279
	ldr	r3, .L785+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L278
.L279:
	ldr	r3, .L785+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L280
	ldr	r3, .L785+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L278
.L280:
	ldr	r3, .L785+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L785+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L278:
	ldr	r3, .L785+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L281
	ldr	r3, .L785+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L282
.L281:
	ldr	r3, .L785+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L283
	ldr	r3, .L785+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L282
.L283:
	ldr	r3, .L785+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L284
	ldr	r3, .L785+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L282
.L284:
	ldr	r3, .L785+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L785+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L282:
	ldr	r3, .L785+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L285
	ldr	r3, .L785+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L286
.L285:
	ldr	r3, .L785+92
	ldr	r3, [r3]	@ float
	ldr	r1, .L785+236
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
.L286:
	ldr	r3, .L785+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L785+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L288
	ldr	r3, .L785+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L785+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L288
	ldr	r3, .L785+24
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L785+104
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L785+92
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L289
.L288:
	ldr	r3, .L785+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L785+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L289
	ldr	r3, .L785+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L289:
	ldr	r3, .L785+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L291
	ldr	r3, .L785+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L291
	ldr	r3, .L785+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L291
	ldr	r3, .L785+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L291
	ldr	r3, .L785+92
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L292
.L291:
	ldr	r3, .L785+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L292
	ldr	r3, .L785+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L292
	ldr	r3, .L785+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L292
	ldr	r3, .L785+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L785+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L292:
	ldr	r3, .L785+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L293
	ldr	r3, .L785+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L785+104
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L294
	mov	r3, #0
	mov	r4, r3
.L294:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L293
	ldr	r3, .L785+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L293
	ldr	r3, .L785+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L293
	ldr	r3, .L785+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L785+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L295
.L293:
	ldr	r3, .L785+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L295
	ldr	r3, .L785+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L295
	ldr	r3, .L785+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L295
	ldr	r3, .L785+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L785+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L295:
	ldr	r3, .L785+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L785+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L296
	ldr	r3, .L785+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L296
	ldr	r3, .L785+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L296
	ldr	r3, .L785+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L296
	ldr	r3, .L785+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L298
.L296:
	ldr	r3, .L785+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L298
	ldr	r3, .L785+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L298
	ldr	r3, .L785+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L298
	ldr	r3, .L785+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L785+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L298:
	ldr	r3, .L785+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L299
	ldr	r3, .L785+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L299
	ldr	r3, .L785+104
	ldr	r3, [r3]	@ float
	ldr	r1, .L785+236
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L299
	ldr	r3, .L785+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L299
	ldr	r3, .L785+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L299
	ldr	r3, .L785+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L785+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L301
.L299:
	ldr	r3, .L785+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L301
	ldr	r3, .L785+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L301
	ldr	r3, .L785+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L301
	ldr	r3, .L785+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L785+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L301:
	ldr	r3, .L785+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L785+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L303
.L302:
	ldr	r3, .L785+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L304
	ldr	r3, .L785+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L303
.L304:
	ldr	r3, .L785+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L305
	ldr	r3, .L785+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L303
.L305:
	ldr	r3, .L785+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L785+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L303:
	ldr	r3, .L785+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L306
	ldr	r3, .L785+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L307
.L306:
	ldr	r3, .L785+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L308
	ldr	r3, .L785+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L307
.L308:
	ldr	r3, .L785+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L309
	ldr	r3, .L785+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L307
.L309:
	ldr	r3, .L785+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L785+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L307:
	ldr	r3, .L785+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L310
	ldr	r3, .L785+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L311
.L310:
	ldr	r3, .L785+136
	ldr	r3, [r3]	@ float
	ldr	r1, .L785+236
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
.L311:
	ldr	r3, .L785+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L785+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L313
	ldr	r3, .L785+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	b	.L786
.L787:
	.align	2
.L785:
	.word	t12_evt0
	.word	t12_evt1
	.word	t12_x
	.word	_x_t12_x
	.word	t12_l0
	.word	t12_l1
	.word	delta
	.word	_x_t12_l0
	.word	_x_t12_l1
	.word	_x_t11_l0
	.word	_x_t11_l1
	.word	_x_t11_evt0
	.word	_x_t11_evt1
	.word	_x_t11_x
	.word	t11_l0
	.word	t11_l1
	.word	t11_x
	.word	t11_evt0
	.word	t11_evt1
	.word	_x_t10_l0
	.word	_x_t10_l1
	.word	_x_t10_evt0
	.word	_x_t10_evt1
	.word	_x_t10_x
	.word	t10_l0
	.word	t10_l1
	.word	t10_x
	.word	t10_evt0
	.word	t10_evt1
	.word	_x_t9_evt0
	.word	_x_t9_evt1
	.word	_x_t9_l0
	.word	_x_t9_l1
	.word	t9_x
	.word	_x_t9_x
	.word	t9_l0
	.word	t9_l1
	.word	t9_evt0
	.word	t9_evt1
	.word	_x_t8_evt0
	.word	_x_t8_evt1
	.word	_x_t8_l0
	.word	_x_t8_l1
	.word	t8_x
	.word	_x_t8_x
	.word	t8_l0
	.word	t8_l1
	.word	t8_evt0
	.word	t8_evt1
	.word	_x_t7_evt0
	.word	_x_t7_evt1
	.word	_x_t7_x
	.word	t7_l1
	.word	t7_l0
	.word	delta
	.word	t7_evt0
	.word	_x_t7_l0
	.word	_x_t7_l1
	.word	t7_x
	.word	1084227584
	.word	t7_evt1
.L786:
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L785+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L313
	ldr	r3, .L785+216
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L785+132
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L785+136
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L314
.L313:
	ldr	r3, .L785+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L785+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L314
	ldr	r3, .L785+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L314:
	ldr	r3, .L785+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L316
	ldr	r3, .L785+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L316
	ldr	r3, .L785+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L316
	ldr	r3, .L785+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L316
	ldr	r3, .L785+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L317
.L316:
	ldr	r3, .L785+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L317
	ldr	r3, .L785+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L317
	ldr	r3, .L785+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L317
	ldr	r3, .L785+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L785+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L317:
	ldr	r3, .L785+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L318
	ldr	r3, .L785+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L318
	ldr	r3, .L785+132
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L319
	mov	r3, #0
	mov	r4, r3
.L319:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L318
	ldr	r3, .L785+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L318
	ldr	r3, .L785+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L318
	ldr	r3, .L785+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L785+136
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L320
.L318:
	ldr	r3, .L785+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L320
	ldr	r3, .L785+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L320
	ldr	r3, .L785+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L320
	ldr	r3, .L785+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L785+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L320:
	ldr	r3, .L785+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L785+136
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L321
	ldr	r3, .L785+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L321
	ldr	r3, .L785+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L321
	ldr	r3, .L785+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L321
	ldr	r3, .L785+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L323
.L321:
	ldr	r3, .L785+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L323
	ldr	r3, .L785+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L323
	ldr	r3, .L785+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L323
	ldr	r3, .L785+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L785+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L323:
	ldr	r3, .L785+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L324
	ldr	r3, .L785+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L324
	ldr	r3, .L785+132
	ldr	r3, [r3]	@ float
	ldr	r1, .L785+236
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L324
	ldr	r3, .L785+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L324
	ldr	r3, .L785+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L324
	ldr	r3, .L785+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L785+136
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L326
.L324:
	ldr	r3, .L785+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L326
	ldr	r3, .L785+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L326
	ldr	r3, .L785+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L326
	ldr	r3, .L785+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L785+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L326:
	ldr	r3, .L785+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L327
	ldr	r3, .L785+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L328
.L327:
	ldr	r3, .L785+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L329
	ldr	r3, .L785+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L328
.L329:
	ldr	r3, .L785+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L330
	ldr	r3, .L785+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L328
.L330:
	ldr	r3, .L785+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L785+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L328:
	ldr	r3, .L785+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L331
	ldr	r3, .L785+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L332
.L331:
	ldr	r3, .L785+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L333
	ldr	r3, .L785+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L332
.L333:
	ldr	r3, .L785+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L334
	ldr	r3, .L785+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L332
.L334:
	ldr	r3, .L785+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L785+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L332:
	ldr	r3, .L785+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L335
	ldr	r3, .L785+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L336
.L335:
	ldr	r3, .L785+176
	ldr	r3, [r3]	@ float
	ldr	r1, .L785+236
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
.L336:
	ldr	r3, .L785+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L785+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L338
	ldr	r3, .L785+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L785+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L338
	ldr	r3, .L785+216
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L785+172
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L785+176
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L339
.L338:
	ldr	r3, .L785+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L785+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L339
	ldr	r3, .L785+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L339:
	ldr	r3, .L785+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L341
	ldr	r3, .L785+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L341
	ldr	r3, .L785+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L341
	ldr	r3, .L785+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L341
	ldr	r3, .L785+176
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L342
.L341:
	ldr	r3, .L785+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L342
	ldr	r3, .L785+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L342
	ldr	r3, .L785+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L342
	ldr	r3, .L785+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L785+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L342:
	ldr	r3, .L785+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L343
	ldr	r3, .L785+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L343
	ldr	r3, .L785+172
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L344
	mov	r3, #0
	mov	r4, r3
.L344:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L343
	ldr	r3, .L785+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L343
	ldr	r3, .L785+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L343
	ldr	r3, .L785+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L785+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L345
.L343:
	ldr	r3, .L785+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L345
	ldr	r3, .L785+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L345
	ldr	r3, .L785+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L345
	ldr	r3, .L785+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L785+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L345:
	ldr	r3, .L785+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L785+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L346
	ldr	r3, .L785+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L346
	ldr	r3, .L785+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L346
	ldr	r3, .L785+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L346
	ldr	r3, .L785+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L348
.L346:
	ldr	r3, .L785+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L348
	ldr	r3, .L785+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L348
	ldr	r3, .L785+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L348
	ldr	r3, .L785+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L785+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L348:
	ldr	r3, .L785+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L349
	ldr	r3, .L785+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L349
	ldr	r3, .L785+172
	ldr	r3, [r3]	@ float
	ldr	r1, .L785+236
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L349
	ldr	r3, .L785+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L349
	ldr	r3, .L785+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L349
	ldr	r3, .L785+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L785+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L351
.L349:
	ldr	r3, .L785+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L351
	ldr	r3, .L785+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L351
	ldr	r3, .L785+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L351
	ldr	r3, .L785+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L785+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L351:
	ldr	r3, .L785+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L352
	ldr	r3, .L785+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L353
.L352:
	ldr	r3, .L785+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L354
	ldr	r3, .L785+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L353
.L354:
	ldr	r3, .L785+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L355
	ldr	r3, .L785+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L353
.L355:
	ldr	r3, .L785+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L785+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L353:
	ldr	r3, .L785+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L356
	ldr	r3, .L785+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L357
.L356:
	ldr	r3, .L785+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L358
	ldr	r3, .L785+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L357
.L358:
	ldr	r3, .L785+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L359
	ldr	r3, .L785+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L357
.L359:
	ldr	r3, .L785+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L785+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L357:
	ldr	r3, .L785+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L360
	ldr	r3, .L785+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L361
.L360:
	ldr	r3, .L785+204
	ldr	r3, [r3]	@ float
	ldr	r1, .L785+236
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
.L361:
	ldr	r3, .L785+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L785+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L363
	ldr	r3, .L785+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L785+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L363
	ldr	r3, .L785+216
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L785+232
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L785+204
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L364
.L363:
	ldr	r3, .L785+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L785+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L364
	ldr	r3, .L785+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L364:
	ldr	r3, .L785+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L366
	ldr	r3, .L785+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L366
	ldr	r3, .L785+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L366
	ldr	r3, .L785+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L366
	ldr	r3, .L785+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L367
.L366:
	ldr	r3, .L785+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L367
	ldr	r3, .L785+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L367
	ldr	r3, .L785+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L367
	ldr	r3, .L785+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L785+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L367:
	ldr	r3, .L785+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L368
	ldr	r3, .L785+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L368
	ldr	r3, .L785+232
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L369
	mov	r3, #0
	mov	r4, r3
.L369:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L368
	ldr	r3, .L785+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L368
	ldr	r3, .L785+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L368
	ldr	r3, .L785+232
	ldr	r3, [r3]	@ float
	ldr	r2, .L785+204
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L370
.L368:
	ldr	r3, .L785+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L370
	ldr	r3, .L785+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L370
	ldr	r3, .L785+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L370
	ldr	r3, .L785+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L785+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L370:
	ldr	r3, .L785+232
	ldr	r3, [r3]	@ float
	ldr	r2, .L785+204
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L371
	ldr	r3, .L785+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L371
	ldr	r3, .L785+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L371
	ldr	r3, .L785+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L371
	ldr	r3, .L785+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L373
.L371:
	ldr	r3, .L785+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L373
	ldr	r3, .L785+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L373
	ldr	r3, .L785+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L373
	ldr	r3, .L785+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L785+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L373:
	ldr	r3, .L785+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L374
	ldr	r3, .L785+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L374
	ldr	r3, .L785+232
	ldr	r3, [r3]	@ float
	ldr	r1, .L785+236
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L374
	ldr	r3, .L785+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L374
	ldr	r3, .L788
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L374
	ldr	r3, .L788+4
	ldr	r3, [r3]	@ float
	ldr	r2, .L788+8
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L376
.L374:
	ldr	r3, .L788+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L376
	ldr	r3, .L788+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L376
	ldr	r3, .L788+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L376
	ldr	r3, .L788
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L788+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L376:
	ldr	r3, .L788+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L377
	ldr	r3, .L788+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L378
.L377:
	ldr	r3, .L788+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L379
	ldr	r3, .L788+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L378
.L379:
	ldr	r3, .L788+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L380
	ldr	r3, .L788+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L378
.L380:
	ldr	r3, .L788+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L788+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L378:
	ldr	r3, .L788+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L381
	ldr	r3, .L788+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L382
.L381:
	ldr	r3, .L788+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L383
	ldr	r3, .L788+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L382
.L383:
	ldr	r3, .L788+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L384
	ldr	r3, .L788+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L382
.L384:
	ldr	r3, .L788+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L788+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L382:
	ldr	r3, .L788+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L385
	ldr	r3, .L788+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L386
.L385:
	ldr	r3, .L788+44
	ldr	r3, [r3]	@ float
	ldr	r1, .L788+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
.L386:
	ldr	r3, .L788+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L788+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L388
	ldr	r3, .L788+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L788+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L388
	ldr	r3, .L788+20
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L788+56
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L788+44
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L389
.L388:
	ldr	r3, .L788+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L788+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L389
	ldr	r3, .L788+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L389:
	ldr	r3, .L788+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L391
	ldr	r3, .L788+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L391
	ldr	r3, .L788+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L391
	ldr	r3, .L788+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L391
	ldr	r3, .L788+44
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L392
.L391:
	ldr	r3, .L788+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L392
	ldr	r3, .L788+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L392
	ldr	r3, .L788+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L392
	ldr	r3, .L788+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L788+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L392:
	ldr	r3, .L788+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L393
	ldr	r3, .L788+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L393
	ldr	r3, .L788+56
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L394
	mov	r3, #0
	mov	r4, r3
.L394:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L393
	ldr	r3, .L788+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L393
	ldr	r3, .L788+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L393
	ldr	r3, .L788+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L788+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L395
.L393:
	ldr	r3, .L788+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L395
	ldr	r3, .L788+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L395
	ldr	r3, .L788+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L395
	ldr	r3, .L788+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L788+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L395:
	ldr	r3, .L788+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L788+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L396
	ldr	r3, .L788+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L396
	ldr	r3, .L788+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L396
	ldr	r3, .L788+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L396
	ldr	r3, .L788+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L398
.L396:
	ldr	r3, .L788+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L398
	ldr	r3, .L788+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L398
	ldr	r3, .L788+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L398
	ldr	r3, .L788+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L788+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L398:
	ldr	r3, .L788+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L399
	ldr	r3, .L788+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L399
	ldr	r3, .L788+56
	ldr	r3, [r3]	@ float
	ldr	r1, .L788+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L399
	ldr	r3, .L788+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L399
	ldr	r3, .L788+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L399
	ldr	r3, .L788+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L788+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L401
.L399:
	ldr	r3, .L788+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L401
	ldr	r3, .L788+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L401
	ldr	r3, .L788+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L401
	ldr	r3, .L788+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L788+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L401:
	ldr	r3, .L788+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L402
	ldr	r3, .L788+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L403
.L402:
	ldr	r3, .L788+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L404
	ldr	r3, .L788+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L403
.L404:
	ldr	r3, .L788+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L405
	ldr	r3, .L788+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L403
.L405:
	ldr	r3, .L788+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L788+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L403:
	ldr	r3, .L788+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L406
	ldr	r3, .L788+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L407
.L406:
	ldr	r3, .L788+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L408
	ldr	r3, .L788+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L407
.L408:
	ldr	r3, .L788+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L409
	ldr	r3, .L788+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L407
.L409:
	ldr	r3, .L788+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L788+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L407:
	ldr	r3, .L788+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L410
	ldr	r3, .L788+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L411
.L410:
	ldr	r3, .L788+84
	ldr	r3, [r3]	@ float
	ldr	r1, .L788+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
.L411:
	ldr	r3, .L788+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L788+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L413
	ldr	r3, .L788+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L788+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L413
	ldr	r3, .L788+20
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L788+96
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L788+84
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L414
.L413:
	ldr	r3, .L788+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L788+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L414
	ldr	r3, .L788+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L414:
	ldr	r3, .L788+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L416
	ldr	r3, .L788+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L416
	ldr	r3, .L788+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L416
	ldr	r3, .L788+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L416
	ldr	r3, .L788+84
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L417
.L416:
	ldr	r3, .L788+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L417
	ldr	r3, .L788+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L417
	ldr	r3, .L788+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L417
	ldr	r3, .L788+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L788+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L417:
	ldr	r3, .L788+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L418
	ldr	r3, .L788+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L418
	ldr	r3, .L788+96
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L419
	mov	r3, #0
	mov	r4, r3
.L419:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L418
	ldr	r3, .L788+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L418
	ldr	r3, .L788+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L418
	ldr	r3, .L788+96
	ldr	r3, [r3]	@ float
	ldr	r2, .L788+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L420
.L418:
	ldr	r3, .L788+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L420
	ldr	r3, .L788+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L420
	ldr	r3, .L788+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L420
	ldr	r3, .L788+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L788+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L420:
	ldr	r3, .L788+96
	ldr	r3, [r3]	@ float
	ldr	r2, .L788+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L421
	ldr	r3, .L788+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L421
	ldr	r3, .L788+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L421
	ldr	r3, .L788+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L421
	ldr	r3, .L788+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L423
.L421:
	ldr	r3, .L788+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L423
	ldr	r3, .L788+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L423
	ldr	r3, .L788+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L423
	ldr	r3, .L788+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L788+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L423:
	ldr	r3, .L788+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L424
	ldr	r3, .L788+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L424
	ldr	r3, .L788+96
	ldr	r3, [r3]	@ float
	ldr	r1, .L788+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L424
	ldr	r3, .L788+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L424
	ldr	r3, .L788+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L424
	ldr	r3, .L788+96
	ldr	r3, [r3]	@ float
	ldr	r2, .L788+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L426
.L424:
	ldr	r3, .L788+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L426
	ldr	r3, .L788+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L426
	ldr	r3, .L788+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L426
	ldr	r3, .L788+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L788+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L426:
	ldr	r3, .L788+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L427
	ldr	r3, .L788+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L428
.L427:
	ldr	r3, .L788+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L429
	ldr	r3, .L788+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L428
.L429:
	ldr	r3, .L788+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L430
	ldr	r3, .L788+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L428
.L430:
	ldr	r3, .L788+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L788+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L428:
	ldr	r3, .L788+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L431
	ldr	r3, .L788+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L432
.L431:
	ldr	r3, .L788+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L433
	ldr	r3, .L788+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L432
.L433:
	ldr	r3, .L788+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L434
	ldr	r3, .L788+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L432
.L434:
	ldr	r3, .L788+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L788+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L432:
	ldr	r3, .L788+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L435
	ldr	r3, .L788+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L436
.L435:
	ldr	r3, .L788+128
	ldr	r3, [r3]	@ float
	ldr	r1, .L788+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
.L436:
	ldr	r3, .L788+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L788+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L438
	ldr	r3, .L788+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L788+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L438
	ldr	r3, .L788+20
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L788+124
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L788+128
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L439
.L438:
	ldr	r3, .L788+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L788+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L439
	ldr	r3, .L788+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L439:
	ldr	r3, .L788+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L441
	ldr	r3, .L788+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L441
	ldr	r3, .L788+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L441
	ldr	r3, .L788+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L441
	ldr	r3, .L788+128
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L442
.L441:
	ldr	r3, .L788+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L442
	ldr	r3, .L788+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L442
	ldr	r3, .L788+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L442
	ldr	r3, .L788+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L788+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	b	.L789
.L790:
	.align	2
.L788:
	.word	t7_evt0
	.word	t7_x
	.word	_x_t7_x
	.word	t7_l0
	.word	t7_l1
	.word	delta
	.word	t7_evt1
	.word	_x_t6_l0
	.word	_x_t6_l1
	.word	_x_t6_evt0
	.word	_x_t6_evt1
	.word	_x_t6_x
	.word	t6_l0
	.word	t6_l1
	.word	t6_x
	.word	t6_evt0
	.word	t6_evt1
	.word	_x_t5_l0
	.word	_x_t5_l1
	.word	_x_t5_evt0
	.word	_x_t5_evt1
	.word	_x_t5_x
	.word	t5_l0
	.word	t5_l1
	.word	t5_x
	.word	t5_evt0
	.word	t5_evt1
	.word	_x_t4_evt0
	.word	_x_t4_evt1
	.word	_x_t4_l0
	.word	_x_t4_l1
	.word	t4_x
	.word	_x_t4_x
	.word	t4_l0
	.word	t4_l1
	.word	t4_evt0
	.word	t4_evt1
	.word	_x_t3_evt0
	.word	_x_t3_evt1
	.word	_x_t3_l0
	.word	_x_t3_l1
	.word	t3_x
	.word	_x_t3_x
	.word	t3_l0
	.word	t3_l1
	.word	t3_evt0
	.word	t3_evt1
	.word	_x_t2_evt0
	.word	_x_t2_evt1
	.word	_x_t2_l0
	.word	_x_t2_l1
	.word	1084227584
	.word	t2_x
	.word	_x_t2_x
	.word	t2_l0
	.word	t2_l1
	.word	delta
	.word	t2_evt0
	.word	t2_evt1
	.word	_x_t1_evt0
	.word	_x_t1_evt1
	.word	_x_t1_l0
	.word	_x_t1_l1
.L789:
	bne	.L205
.L442:
	ldr	r3, .L788+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L443
	ldr	r3, .L788+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L443
	ldr	r3, .L788+124
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L444
	mov	r3, #0
	mov	r4, r3
.L444:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L443
	ldr	r3, .L788+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L443
	ldr	r3, .L788+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L443
	ldr	r3, .L788+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L788+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L445
.L443:
	ldr	r3, .L788+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L445
	ldr	r3, .L788+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L445
	ldr	r3, .L788+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L445
	ldr	r3, .L788+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L788+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L445:
	ldr	r3, .L788+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L788+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L446
	ldr	r3, .L788+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L446
	ldr	r3, .L788+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L446
	ldr	r3, .L788+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L446
	ldr	r3, .L788+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L448
.L446:
	ldr	r3, .L788+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L448
	ldr	r3, .L788+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L448
	ldr	r3, .L788+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L448
	ldr	r3, .L788+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L788+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L448:
	ldr	r3, .L788+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L449
	ldr	r3, .L788+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L449
	ldr	r3, .L788+124
	ldr	r3, [r3]	@ float
	ldr	r1, .L788+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L449
	ldr	r3, .L788+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L449
	ldr	r3, .L788+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L449
	ldr	r3, .L788+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L788+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L451
.L449:
	ldr	r3, .L788+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L451
	ldr	r3, .L788+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L451
	ldr	r3, .L788+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L451
	ldr	r3, .L788+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L788+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L451:
	ldr	r3, .L788+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L452
	ldr	r3, .L788+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L453
.L452:
	ldr	r3, .L788+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L454
	ldr	r3, .L788+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L453
.L454:
	ldr	r3, .L788+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L455
	ldr	r3, .L788+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L453
.L455:
	ldr	r3, .L788+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L788+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L453:
	ldr	r3, .L788+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L456
	ldr	r3, .L788+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L457
.L456:
	ldr	r3, .L788+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L458
	ldr	r3, .L788+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L457
.L458:
	ldr	r3, .L788+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L459
	ldr	r3, .L788+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L457
.L459:
	ldr	r3, .L788+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L788+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L457:
	ldr	r3, .L788+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L460
	ldr	r3, .L788+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L461
.L460:
	ldr	r3, .L788+168
	ldr	r3, [r3]	@ float
	ldr	r1, .L788+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
.L461:
	ldr	r3, .L788+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L788+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L463
	ldr	r3, .L788+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L788+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L463
	ldr	r3, .L788+224
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L788+164
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L788+168
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L464
.L463:
	ldr	r3, .L788+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L788+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L464
	ldr	r3, .L788+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L464:
	ldr	r3, .L788+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L466
	ldr	r3, .L788+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L466
	ldr	r3, .L788+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L466
	ldr	r3, .L788+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L466
	ldr	r3, .L788+168
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L467
.L466:
	ldr	r3, .L788+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L467
	ldr	r3, .L788+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L467
	ldr	r3, .L788+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L467
	ldr	r3, .L788+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L788+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L467:
	ldr	r3, .L788+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L468
	ldr	r3, .L788+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L468
	ldr	r3, .L788+164
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L469
	mov	r3, #0
	mov	r4, r3
.L469:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L468
	ldr	r3, .L788+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L468
	ldr	r3, .L788+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L468
	ldr	r3, .L788+164
	ldr	r3, [r3]	@ float
	ldr	r2, .L788+168
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L470
.L468:
	ldr	r3, .L788+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L470
	ldr	r3, .L788+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L470
	ldr	r3, .L788+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L470
	ldr	r3, .L788+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L788+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L470:
	ldr	r3, .L788+164
	ldr	r3, [r3]	@ float
	ldr	r2, .L788+168
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L471
	ldr	r3, .L788+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L471
	ldr	r3, .L788+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L471
	ldr	r3, .L788+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L471
	ldr	r3, .L788+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L473
.L471:
	ldr	r3, .L788+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L473
	ldr	r3, .L788+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L473
	ldr	r3, .L788+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L473
	ldr	r3, .L788+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L788+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L473:
	ldr	r3, .L788+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L474
	ldr	r3, .L788+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L474
	ldr	r3, .L788+164
	ldr	r3, [r3]	@ float
	ldr	r1, .L788+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L474
	ldr	r3, .L788+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L474
	ldr	r3, .L788+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L474
	ldr	r3, .L788+164
	ldr	r3, [r3]	@ float
	ldr	r2, .L788+168
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L476
.L474:
	ldr	r3, .L788+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L476
	ldr	r3, .L788+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L476
	ldr	r3, .L788+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L476
	ldr	r3, .L788+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L788+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L476:
	ldr	r3, .L788+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L477
	ldr	r3, .L788+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L478
.L477:
	ldr	r3, .L788+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L479
	ldr	r3, .L788+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L478
.L479:
	ldr	r3, .L788+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L480
	ldr	r3, .L788+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L478
.L480:
	ldr	r3, .L788+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L788+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L478:
	ldr	r3, .L788+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L481
	ldr	r3, .L788+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L482
.L481:
	ldr	r3, .L788+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L483
	ldr	r3, .L788+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L482
.L483:
	ldr	r3, .L788+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L484
	ldr	r3, .L788+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L482
.L484:
	ldr	r3, .L788+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L788+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L482:
	ldr	r3, .L788+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L485
	ldr	r3, .L788+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L486
.L485:
	ldr	r3, .L788+212
	ldr	r3, [r3]	@ float
	ldr	r1, .L788+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
.L486:
	ldr	r3, .L788+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L788+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L488
	ldr	r3, .L788+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L788+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L488
	ldr	r3, .L788+224
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L788+208
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L788+212
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L489
.L488:
	ldr	r3, .L788+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L788+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L489
	ldr	r3, .L788+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L489:
	ldr	r3, .L788+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L491
	ldr	r3, .L788+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L491
	ldr	r3, .L788+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L491
	ldr	r3, .L788+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L491
	ldr	r3, .L788+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L492
.L491:
	ldr	r3, .L788+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L492
	ldr	r3, .L788+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L492
	ldr	r3, .L788+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L492
	ldr	r3, .L788+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L788+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L492:
	ldr	r3, .L788+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L493
	ldr	r3, .L788+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L493
	ldr	r3, .L788+208
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L494
	mov	r3, #0
	mov	r4, r3
.L494:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L493
	ldr	r3, .L788+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L493
	ldr	r3, .L788+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L493
	ldr	r3, .L788+208
	ldr	r3, [r3]	@ float
	ldr	r2, .L788+212
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L495
.L493:
	ldr	r3, .L788+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L495
	ldr	r3, .L788+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L495
	ldr	r3, .L788+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L495
	ldr	r3, .L788+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L788+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L495:
	ldr	r3, .L788+208
	ldr	r3, [r3]	@ float
	ldr	r2, .L788+212
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L496
	ldr	r3, .L788+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L496
	ldr	r3, .L788+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L496
	ldr	r3, .L788+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L496
	ldr	r3, .L788+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L498
.L496:
	ldr	r3, .L788+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L498
	ldr	r3, .L788+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L498
	ldr	r3, .L788+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L498
	ldr	r3, .L788+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L788+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L498:
	ldr	r3, .L788+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L499
	ldr	r3, .L788+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L499
	ldr	r3, .L788+208
	ldr	r3, [r3]	@ float
	ldr	r1, .L788+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L499
	ldr	r3, .L788+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L499
	ldr	r3, .L788+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L499
	ldr	r3, .L788+208
	ldr	r3, [r3]	@ float
	ldr	r2, .L788+212
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L501
.L499:
	ldr	r3, .L788+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L501
	ldr	r3, .L788+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L501
	ldr	r3, .L788+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L501
	ldr	r3, .L788+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L788+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L501:
	ldr	r3, .L788+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L502
	ldr	r3, .L788+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L503
.L502:
	ldr	r3, .L788+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L504
	ldr	r3, .L788+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L503
.L504:
	ldr	r3, .L788+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L505
	ldr	r3, .L788+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L503
.L505:
	ldr	r3, .L788+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L788+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L503:
	ldr	r3, .L788+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L506
	ldr	r3, .L788+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L507
.L506:
	ldr	r3, .L788+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L508
	ldr	r3, .L788+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L507
.L508:
	ldr	r3, .L788+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L509
	ldr	r3, .L788+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L507
.L509:
	ldr	r3, .L788+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L788+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L507:
	ldr	r3, .L788+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L510
	ldr	r3, .L788+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L511
.L510:
	ldr	r3, .L791
	ldr	r3, [r3]	@ float
	ldr	r1, .L791+4
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
.L511:
	ldr	r3, .L791+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L791+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L513
	ldr	r3, .L791+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L791+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L513
	ldr	r3, .L791+88
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L791+24
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L791
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L514
.L513:
	ldr	r3, .L791+88
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L791+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L514
	ldr	r3, .L791+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L514:
	ldr	r3, .L791+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L516
	ldr	r3, .L791+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L516
	ldr	r3, .L791+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L516
	ldr	r3, .L791+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L516
	ldr	r3, .L791
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L517
.L516:
	ldr	r3, .L791+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L517
	ldr	r3, .L791+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L517
	ldr	r3, .L791+88
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L517
	ldr	r3, .L791+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L791+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L517:
	ldr	r3, .L791+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L518
	ldr	r3, .L791+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L518
	ldr	r3, .L791+24
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L519
	mov	r3, #0
	mov	r4, r3
.L519:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L518
	ldr	r3, .L791+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L518
	ldr	r3, .L791+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L518
	ldr	r3, .L791+24
	ldr	r3, [r3]	@ float
	ldr	r2, .L791
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L520
.L518:
	ldr	r3, .L791+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L520
	ldr	r3, .L791+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L520
	ldr	r3, .L791+88
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L520
	ldr	r3, .L791+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L791+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L520:
	ldr	r3, .L791+24
	ldr	r3, [r3]	@ float
	ldr	r2, .L791
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L521
	ldr	r3, .L791+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L521
	ldr	r3, .L791+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L521
	ldr	r3, .L791+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L521
	ldr	r3, .L791+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L523
.L521:
	ldr	r3, .L791+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L523
	ldr	r3, .L791+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L523
	ldr	r3, .L791+88
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L523
	ldr	r3, .L791+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L791+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L523:
	ldr	r3, .L791+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L524
	ldr	r3, .L791+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L524
	ldr	r3, .L791+24
	ldr	r3, [r3]	@ float
	ldr	r1, .L791+4
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L524
	ldr	r3, .L791+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L524
	ldr	r3, .L791+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L524
	ldr	r3, .L791+24
	ldr	r3, [r3]	@ float
	ldr	r2, .L791
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L526
.L524:
	ldr	r3, .L791+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L526
	ldr	r3, .L791+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L526
	ldr	r3, .L791+88
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L526
	ldr	r3, .L791+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L791+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L526:
	ldr	r3, .L791+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L527
	ldr	r3, .L791+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L528
.L527:
	ldr	r3, .L791+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L529
	ldr	r3, .L791+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L528
.L529:
	ldr	r3, .L791+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L530
	ldr	r3, .L791+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L528
.L530:
	ldr	r3, .L791+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L791+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L528:
	ldr	r3, .L791+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L531
	ldr	r3, .L791+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L532
.L531:
	ldr	r3, .L791+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L533
	ldr	r3, .L791+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L532
.L533:
	ldr	r3, .L791+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L534
	ldr	r3, .L791+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L532
.L534:
	ldr	r3, .L791+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L791+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L532:
	ldr	r3, .L791+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L535
	ldr	r3, .L791+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L536
.L535:
	ldr	r3, .L791+44
	ldr	r3, [r3]	@ float
	ldr	r1, .L791+4
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
.L536:
	ldr	r3, .L791+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L791+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L538
	ldr	r3, .L791+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L791+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L538
	ldr	r3, .L791+88
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L791+56
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L791+44
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L539
.L538:
	ldr	r3, .L791+88
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L791+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L539
	ldr	r3, .L791+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L539:
	ldr	r3, .L791+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L541
	ldr	r3, .L791+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L541
	ldr	r3, .L791+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L541
	ldr	r3, .L791+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L541
	ldr	r3, .L791+44
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L542
.L541:
	ldr	r3, .L791+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L542
	ldr	r3, .L791+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L542
	ldr	r3, .L791+88
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L542
	ldr	r3, .L791+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L791+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L542:
	ldr	r3, .L791+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L543
	ldr	r3, .L791+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L543
	ldr	r3, .L791+56
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L544
	mov	r3, #0
	mov	r4, r3
.L544:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L543
	ldr	r3, .L791+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L543
	ldr	r3, .L791+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L543
	ldr	r3, .L791+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L791+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L545
.L543:
	ldr	r3, .L791+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L545
	ldr	r3, .L791+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L545
	ldr	r3, .L791+88
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L545
	ldr	r3, .L791+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L791+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L545:
	ldr	r3, .L791+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L791+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L546
	ldr	r3, .L791+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L546
	ldr	r3, .L791+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L546
	ldr	r3, .L791+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L546
	ldr	r3, .L791+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L548
.L546:
	ldr	r3, .L791+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L548
	ldr	r3, .L791+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L548
	ldr	r3, .L791+88
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L548
	ldr	r3, .L791+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L791+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L548:
	ldr	r3, .L791+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L549
	ldr	r3, .L791+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L549
	ldr	r3, .L791+56
	ldr	r3, [r3]	@ float
	ldr	r1, .L791+4
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L549
	ldr	r3, .L791+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L549
	ldr	r3, .L791+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L549
	ldr	r3, .L791+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L791+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L551
.L549:
	ldr	r3, .L791+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L551
	ldr	r3, .L791+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L551
	ldr	r3, .L791+88
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L551
	ldr	r3, .L791+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L791+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L551:
	ldr	r3, .L791+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L552
	ldr	r3, .L791+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L553
.L552:
	ldr	r3, .L791+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L554
	ldr	r3, .L791+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L553
.L554:
	ldr	r3, .L791+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L555
	ldr	r3, .L791+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L553
.L555:
	ldr	r3, .L791+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L791+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L553:
	ldr	r3, .L791+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L556
	ldr	r3, .L791+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L556
	ldr	r3, .L791+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L557
.L556:
	ldr	r3, .L791+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L558
	ldr	r3, .L791+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L558
	ldr	r3, .L791+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L557
.L558:
	ldr	r3, .L791+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L559
	ldr	r3, .L791+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L559
	ldr	r3, .L791+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L557
.L559:
	ldr	r3, .L791+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L560
	ldr	r3, .L791+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L560
	ldr	r3, .L791+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L557
.L560:
	ldr	r3, .L791+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L791+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L791+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L557:
	ldr	r3, .L791+80
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L561
	ldr	r3, .L791+80
	ldr	r3, [r3]
	cmp	r3, #1
	beq	.L561
	ldr	r3, .L791+80
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L561
	ldr	r3, .L791+80
	ldr	r3, [r3]
	cmp	r3, #3
	beq	.L561
	ldr	r3, .L791+80
	ldr	r3, [r3]
	cmp	r3, #4
	beq	.L561
	ldr	r3, .L791+80
	ldr	r3, [r3]
	cmp	r3, #5
	beq	.L561
	ldr	r3, .L791+80
	ldr	r3, [r3]
	cmp	r3, #6
	beq	.L561
	ldr	r3, .L791+80
	ldr	r3, [r3]
	cmp	r3, #7
	beq	.L561
	ldr	r3, .L791+80
	ldr	r3, [r3]
	cmp	r3, #8
	beq	.L561
	ldr	r3, .L791+80
	ldr	r3, [r3]
	cmp	r3, #9
	beq	.L561
	ldr	r3, .L791+80
	ldr	r3, [r3]
	cmp	r3, #10
	beq	.L561
	ldr	r3, .L791+80
	ldr	r3, [r3]
	cmp	r3, #11
	beq	.L561
	ldr	r3, .L791+80
	ldr	r3, [r3]
	cmp	r3, #12
	beq	.L561
	ldr	r3, .L791+80
	ldr	r3, [r3]
	cmp	r3, #13
	beq	.L561
	ldr	r3, .L791+80
	ldr	r3, [r3]
	cmp	r3, #14
	beq	.L561
	ldr	r3, .L791+80
	ldr	r3, [r3]
	cmp	r3, #15
	bne	.L205
.L561:
	ldr	r3, .L791+72
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L562
	ldr	r3, .L791+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L563
	ldr	r3, .L791+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L563:
	ldr	r3, .L791+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L562
	ldr	r3, .L791+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L562:
	ldr	r3, .L791+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L791+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L564
	ldr	r3, .L791+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L791+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L564
	ldr	r3, .L791+88
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L791+84
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L791+72
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L564
	ldr	r3, .L791+76
	ldr	r2, [r3]
	ldr	r3, .L791+80
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L566
.L564:
	ldr	r3, .L791+88
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L791+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L566
	ldr	r3, .L791+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L566
	ldr	r3, .L791+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L566:
	ldr	r3, .L791+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L568
	ldr	r3, .L791+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L568
	ldr	r3, .L791+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L568
	ldr	r3, .L791+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L568
	ldr	r3, .L791+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L568
	ldr	r3, .L791+80
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L568
	ldr	r3, .L791+72
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L569
.L568:
	ldr	r3, .L791+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L569
	ldr	r3, .L791+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L569
	ldr	r3, .L791+88
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	b	.L792
.L793:
	.align	2
.L791:
	.word	_x_t1_x
	.word	1084227584
	.word	t1_l0
	.word	_x_t1_l0
	.word	t1_l1
	.word	_x_t1_l1
	.word	t1_x
	.word	_x_t0_l0
	.word	_x_t0_l1
	.word	_x_t0_evt0
	.word	_x_t0_evt1
	.word	_x_t0_x
	.word	t0_l0
	.word	t0_l1
	.word	t0_x
	.word	_x_controller_evt2
	.word	_x_controller_evt0
	.word	_x_controller_evt1
	.word	_x_controller_z
	.word	controller_cnt
	.word	_x_controller_cnt
	.word	controller_z
	.word	delta
	.word	controller_evt2
	.word	controller_evt0
	.word	controller_evt1
	.word	_x_controller_l1
	.word	_x_controller_l0
	.word	controller_l0
	.word	controller_l1
	.word	_x_gate_evt0
	.word	_x_gate_evt1
	.word	_x_gate_y
	.word	_x_gate_l0
	.word	_x_gate_l1
	.word	gate_y
	.word	gate_l0
	.word	gate_l1
	.word	gate_evt0
	.word	gate_evt1
	.word	_x_delta
	.word	t0_evt0
	.word	t0_evt1
	.word	t1_evt0
	.word	t1_evt1
	.word	t2_evt0
	.word	t2_evt1
	.word	t13_evt1
	.word	delta
	.word	t3_evt0
	.word	t3_evt1
	.word	t13_evt0
.L792:
	beq	.L569
	ldr	r3, .L791+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L791+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L791+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L569:
	ldr	r3, .L791+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L791+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L570
	ldr	r3, .L791+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L572
	ldr	r3, .L791+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L573
.L572:
	ldr	r3, .L791+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L570
	ldr	r3, .L791+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L573
.L570:
	ldr	r3, .L791+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L573
	ldr	r3, .L791+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L573
	ldr	r3, .L791+88
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L573
	ldr	r3, .L791+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L791+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L791+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L573:
	ldr	r3, .L791+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L574
	ldr	r3, .L791+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L574
	ldr	r3, .L791+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L574
	ldr	r3, .L791+76
	ldr	r2, [r3]
	ldr	r3, .L791+80
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmn	r3, #1
	beq	.L575
.L574:
	ldr	r3, .L791+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L576
	ldr	r3, .L791+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L576
	ldr	r3, .L791+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L576
	ldr	r3, .L791+76
	ldr	r2, [r3]
	ldr	r3, .L791+80
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmp	r3, #1
	beq	.L575
.L576:
	ldr	r3, .L791+88
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L575
	ldr	r3, .L791+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L577
	ldr	r3, .L791+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L577
	ldr	r3, .L791+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L575
.L577:
	ldr	r3, .L791+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L575
	ldr	r3, .L791+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L575
	ldr	r3, .L791+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L575
	ldr	r3, .L791+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L575:
	ldr	r3, .L791+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L578
	ldr	r3, .L791+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L578
	ldr	r3, .L791+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L578
	ldr	r3, .L791+76
	ldr	r2, [r3]
	ldr	r3, .L791+80
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L578
	ldr	r3, .L791+84
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L579
.L578:
	ldr	r3, .L791+88
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L579
	ldr	r3, .L791+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L580
	ldr	r3, .L791+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L580
	ldr	r3, .L791+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L579
.L580:
	ldr	r3, .L791+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L579
	ldr	r3, .L791+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L579
	ldr	r3, .L791+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L579
	ldr	r3, .L791+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L579:
	ldr	r3, .L791+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L581
	ldr	r3, .L791+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L582
.L581:
	ldr	r3, .L791+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L583
	ldr	r3, .L791+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L582
.L583:
	ldr	r3, .L791+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L582
	ldr	r3, .L791+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L582
	ldr	r3, .L791+88
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L582
	ldr	r3, .L791+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L791+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L791+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L582:
	ldr	r3, .L791+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L791+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L584
	ldr	r3, .L791+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L586
	ldr	r3, .L791+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L586
	ldr	r3, .L791+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L586
	ldr	r3, .L791+76
	ldr	r2, [r3]
	ldr	r3, .L791+80
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmn	r3, #1
	beq	.L587
.L586:
	ldr	r3, .L791+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L584
	ldr	r3, .L791+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L584
	ldr	r3, .L791+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L584
	ldr	r3, .L791+76
	ldr	r2, [r3]
	ldr	r3, .L791+80
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmp	r3, #1
	bne	.L584
	ldr	r3, .L791+76
	ldr	r3, [r3]
	cmp	r3, #1
	bgt	.L587
.L584:
	ldr	r3, .L791+88
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L587
	ldr	r3, .L791+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L588
	ldr	r3, .L791+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L588
	ldr	r3, .L791+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L587
.L588:
	ldr	r3, .L791+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L587
	ldr	r3, .L791+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L587
	ldr	r3, .L791+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L587
	ldr	r3, .L791+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L587:
	ldr	r3, .L791+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L589
	ldr	r3, .L791+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L589
	ldr	r3, .L791+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L589
	ldr	r3, .L791+76
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L589
	ldr	r3, .L791+80
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L589
	ldr	r3, .L791+72
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L590
.L589:
	ldr	r3, .L791+88
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L590
	ldr	r3, .L791+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L591
	ldr	r3, .L791+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L591
	ldr	r3, .L791+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L590
.L591:
	ldr	r3, .L791+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L590
	ldr	r3, .L791+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L590
	ldr	r3, .L791+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L590
	ldr	r3, .L791+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L590:
	ldr	r3, .L791+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L791+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L592
	ldr	r3, .L791+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L594
	ldr	r3, .L791+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L595
.L594:
	ldr	r3, .L791+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L592
	ldr	r3, .L791+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L595
.L592:
	ldr	r3, .L791+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L595
	ldr	r3, .L791+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L595
	ldr	r3, .L791+88
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L595
	ldr	r3, .L791+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L791+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L791+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L595:
	ldr	r3, .L791+76
	ldr	r2, [r3]
	ldr	r3, .L791+80
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmn	r3, #1
	bne	.L596
	ldr	r3, .L791+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L596
	ldr	r3, .L791+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L596
	ldr	r3, .L791+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L596
	ldr	r3, .L791+84
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L597
.L596:
	ldr	r3, .L791+88
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L597
	ldr	r3, .L791+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L598
	ldr	r3, .L791+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L598
	ldr	r3, .L791+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L597
.L598:
	ldr	r3, .L791+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L597
	ldr	r3, .L791+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L597
	ldr	r3, .L791+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L597
	ldr	r3, .L791+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L597:
	ldr	r3, .L791+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L599
	ldr	r3, .L791+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L600
.L599:
	ldr	r3, .L791+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L601
	ldr	r3, .L791+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L600
.L601:
	ldr	r3, .L791+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L602
	ldr	r3, .L791+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L600
.L602:
	ldr	r3, .L791+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L791+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L600:
	ldr	r3, .L791+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L603
	ldr	r3, .L791+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L604
.L603:
	ldr	r3, .L791+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L605
	ldr	r3, .L791+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L604
.L605:
	ldr	r3, .L791+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L606
	ldr	r3, .L791+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L604
.L606:
	ldr	r3, .L791+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L791+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L604:
	ldr	r3, .L791+128
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L607
	ldr	r3, .L791+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L607
	ldr	r3, .L791+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L607:
	ldr	r3, .L791+128
	ldr	r3, [r3]	@ float
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L608
	ldr	r3, .L791+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L608
	ldr	r3, .L791+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L608:
	ldr	r3, .L791+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L791+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L609
	ldr	r3, .L791+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L791+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L609
	ldr	r3, .L791+192
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L791+140
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L791+128
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L610
.L609:
	ldr	r3, .L791+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L611
	ldr	r3, .L791+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L611:
	ldr	r3, .L791+192
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
.L610:
	ldr	r3, .L791+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L613
	ldr	r3, .L791+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L613
	ldr	r3, .L791+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L613
	ldr	r3, .L791+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L613
	ldr	r3, .L791+128
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L614
.L613:
	ldr	r3, .L791+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L614
	ldr	r3, .L791+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L614
	ldr	r3, .L791+192
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L614
	ldr	r3, .L791+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L791+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L614:
	ldr	r3, .L791+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L615
	ldr	r3, .L791+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L615
	ldr	r3, .L791+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L615
	ldr	r3, .L791+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L615
	ldr	r3, .L791+140
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L615
	ldr	r3, .L791+140
	ldr	r3, [r3]	@ float
	ldr	r2, .L791+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L617
.L615:
	ldr	r3, .L791+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L617
	ldr	r3, .L791+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L617
	ldr	r3, .L791+192
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L617
	ldr	r3, .L791+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L791+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L617:
	ldr	r3, .L791+128
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L618
	ldr	r3, .L791+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L618
	ldr	r3, .L791+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L618
	ldr	r3, .L791+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L618
	ldr	r3, .L791+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L620
.L618:
	ldr	r3, .L791+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L620
	ldr	r3, .L791+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L620
	ldr	r3, .L791+192
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L620
	ldr	r3, .L791+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L791+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L620:
	ldr	r3, .L791+140
	ldr	r3, [r3]	@ float
	ldr	r2, .L791+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L621
	ldr	r3, .L791+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L621
	ldr	r3, .L791+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L621
	ldr	r3, .L791+140
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L621
	ldr	r3, .L791+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L621
	ldr	r3, .L791+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L621
	ldr	r3, .L791+140
	ldr	r3, [r3]	@ float
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L624
.L621:
	ldr	r3, .L791+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L624
	ldr	r3, .L791+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L624
	ldr	r3, .L791+192
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L624
	ldr	r3, .L791+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L791+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L624:
	ldr	r3, .L791+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L791+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L626
	ldr	r3, .L791+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L627
.L626:
	ldr	r3, .L791+192
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L627
	ldr	r3, .L791+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L791+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L627:
	ldr	r3, .L791+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L628
	ldr	r3, .L791+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L629
.L628:
	ldr	r3, .L791+192
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L629
	ldr	r3, .L791+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L791+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L629:
	ldr	r3, .L791+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L630
	ldr	r3, .L791+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L631
.L630:
	ldr	r3, .L791+192
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L631
	ldr	r3, .L791+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L791+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L631:
	ldr	r3, .L791+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L632
	ldr	r3, .L791+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L633
.L632:
	ldr	r3, .L791+192
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L633
	ldr	r3, .L791+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L791+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L633:
	ldr	r3, .L791+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L634
	ldr	r3, .L794+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L635
.L634:
	ldr	r3, .L794+292
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L635
	ldr	r3, .L794+588
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L794+364
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L635:
	ldr	r3, .L794+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L636
	ldr	r3, .L794+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L637
.L636:
	ldr	r3, .L794+292
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L637
	ldr	r3, .L794+388
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L794+452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L637:
	ldr	r3, .L794+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L638
	ldr	r3, .L794+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L639
.L638:
	ldr	r3, .L794+292
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L639
	ldr	r3, .L794+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L794+604
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L639:
	ldr	r3, .L794+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L640
	ldr	r3, .L794+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L641
.L640:
	ldr	r3, .L794+292
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L641
	ldr	r3, .L794+540
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L794+620
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L641:
	ldr	r3, .L794+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L642
	ldr	r3, .L794+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L643
.L642:
	ldr	r3, .L794+292
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L643
	ldr	r3, .L794+652
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L794+660
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L643:
	ldr	r3, .L794+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L644
	ldr	r3, .L794+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L645
.L644:
	ldr	r3, .L794+292
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L645
	ldr	r3, .L794+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L794+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L645:
	ldr	r3, .L794+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L646
	ldr	r3, .L794+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L647
.L646:
	ldr	r3, .L794+292
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L647
	ldr	r3, .L794+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L794+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L647:
	ldr	r3, .L794+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L648
	ldr	r3, .L794+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L649
.L648:
	ldr	r3, .L794+292
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L649
	ldr	r3, .L794+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L794+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L649:
	ldr	r3, .L794+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L650
	ldr	r3, .L794+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L651
.L650:
	ldr	r3, .L794+292
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L651
	ldr	r3, .L794+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L794+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L651:
	ldr	r3, .L794+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L652
	ldr	r3, .L794+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L653
.L652:
	ldr	r3, .L794+292
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L653
	ldr	r3, .L794+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L794+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
.L653:
	ldr	r3, .L794+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L654
	ldr	r3, .L794+444
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L654
	mov	r3, #1
	b	.L655
.L654:
	mov	r3, #0
.L655:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L794+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L656
	ldr	r3, .L794+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L656
	ldr	r3, .L794+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L656
	mov	r3, #1
	b	.L657
.L656:
	mov	r3, #0
.L657:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L658
	ldr	r3, .L794+292
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L205
.L658:
	ldr	r3, .L794+292
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L660
	ldr	r3, .L794+444
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L661
	ldr	r3, .L794+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L661
	mov	r3, #1
	b	.L662
.L661:
	mov	r3, #0
.L662:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L794+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L663
	ldr	r3, .L794+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L663
	ldr	r3, .L794+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L663
	mov	r3, #1
	b	.L664
.L663:
	mov	r3, #0
.L664:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L205
.L660:
	ldr	r3, .L794+292
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L665
	ldr	r3, .L794+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L666
	ldr	r3, .L794+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L666
	ldr	r3, .L794+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L666
	mov	r3, #1
	b	.L667
.L666:
	mov	r3, #0
.L667:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L794+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L668
	ldr	r3, .L794+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L669
.L668:
	ldr	r3, .L794+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L670
	ldr	r3, .L794+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L669
.L670:
	ldr	r3, .L794+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L671
	ldr	r3, .L794+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L669
.L671:
	ldr	r3, .L794+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L672
	ldr	r3, .L794+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L669
.L672:
	ldr	r3, .L794+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L673
	ldr	r3, .L794+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L669
.L673:
	ldr	r3, .L794+652
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L674
	ldr	r3, .L794+660
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L669
.L674:
	ldr	r3, .L794+540
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L675
	ldr	r3, .L794+620
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L669
.L675:
	ldr	r3, .L794+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L676
	ldr	r3, .L794+604
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L669
.L676:
	ldr	r3, .L794+388
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L677
	ldr	r3, .L794+452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L669
.L677:
	ldr	r3, .L794+588
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L678
	ldr	r3, .L794+364
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L669
.L678:
	ldr	r3, .L794+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L679
	ldr	r3, .L794+548
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L669
.L679:
	ldr	r3, .L794+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L680
	ldr	r3, .L794+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L669
.L680:
	ldr	r3, .L794+300
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L681
	ldr	r3, .L794+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L669
.L681:
	ldr	r3, .L794+412
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L682
	ldr	r3, .L794+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L682
.L669:
	mov	r3, #1
	b	.L683
.L682:
	mov	r3, #0
.L683:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L205
.L665:
	ldr	r3, .L794+292
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L684
	ldr	r3, .L794+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L685
	ldr	r3, .L794+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L685
	ldr	r3, .L794+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L685
	mov	r3, #1
	b	.L686
.L685:
	mov	r3, #0
.L686:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L794+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L687
	ldr	r3, .L794+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L688
.L687:
	ldr	r3, .L794+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L689
	ldr	r3, .L794+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L688
.L689:
	ldr	r3, .L794+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L690
	ldr	r3, .L794+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L688
.L690:
	ldr	r3, .L794+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L691
	ldr	r3, .L794+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L688
.L691:
	ldr	r3, .L794+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L692
	ldr	r3, .L794+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L688
.L692:
	ldr	r3, .L794+660
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L693
	ldr	r3, .L794+652
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L688
.L693:
	ldr	r3, .L794+620
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L694
	ldr	r3, .L794+540
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L688
.L694:
	ldr	r3, .L794+604
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L695
	ldr	r3, .L794+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L688
.L695:
	ldr	r3, .L794+452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L696
	ldr	r3, .L794+388
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L688
.L696:
	ldr	r3, .L794+364
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L697
	ldr	r3, .L794+588
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L688
.L697:
	ldr	r3, .L794+548
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L698
	ldr	r3, .L794+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L688
.L698:
	ldr	r3, .L794+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L699
	ldr	r3, .L794+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L688
.L699:
	ldr	r3, .L794+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L700
	ldr	r3, .L794+300
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L688
.L700:
	ldr	r3, .L794+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L701
	ldr	r3, .L794+412
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L701
.L688:
	mov	r3, #1
	b	.L702
.L701:
	mov	r3, #0
.L702:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L205
.L684:
	ldr	r3, .L794+292
	ldr	r3, [r3]	@ float
	ldr	r2, .L794+560
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L703
	ldr	r3, .L794+564
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L704
	mov	r3, #0
	mov	r4, r3
.L704:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L205
.L703:
	ldr	r3, .L794+564
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L705
	ldr	r3, .L794+292
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L794+564
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L794+560
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
.L705:
	mov	r3, #1
	b	.L707
.L795:
	.align	2
.L794:
	.word	_x_t13_l1
	.word	t13_l1
	.word	_x_t13_l0
	.word	t13_l0
	.word	_x_t13_evt1
	.word	t13_evt1
	.word	_x_t13_evt0
	.word	t13_evt0
	.word	_x_t13_x
	.word	t13_x
	.word	_x_t12_l1
	.word	t12_l1
	.word	_x_t12_l0
	.word	t12_l0
	.word	_x_t12_evt1
	.word	t12_evt1
	.word	_x_t12_evt0
	.word	t12_evt0
	.word	_x_t12_x
	.word	t12_x
	.word	_x_t11_l1
	.word	t11_l1
	.word	_x_t11_l0
	.word	t11_l0
	.word	_x_t11_evt1
	.word	t11_evt1
	.word	_x_t11_evt0
	.word	t11_evt0
	.word	_x_t11_x
	.word	t11_x
	.word	_x_t10_evt1
	.word	t10_evt1
	.word	_x_t10_evt0
	.word	t10_evt0
	.word	_x_t10_x
	.word	t10_x
	.word	_x_t9_l1
	.word	t9_l1
	.word	_x_t9_l0
	.word	t9_l0
	.word	_x_t9_evt1
	.word	t9_evt1
	.word	_x_t9_evt0
	.word	t9_evt0
	.word	_x_t3_x
	.word	t3_x
	.word	_x_t2_evt1
	.word	t2_evt1
	.word	_x_controller_l1
	.word	controller_l1
	.word	_x_t2_l0
	.word	t2_l0
	.word	_x_t2_evt0
	.word	t2_evt0
	.word	_x_t1_l1
	.word	t1_l1
	.word	_x_controller_l0
	.word	controller_l0
	.word	_x_t2_x
	.word	t2_x
	.word	_x_t1_evt1
	.word	t1_evt1
	.word	_x_controller_evt0
	.word	controller_evt0
	.word	_x_t1_l0
	.word	t1_l0
	.word	_x_t1_x
	.word	t1_x
	.word	_x_t2_l1
	.word	t2_l1
	.word	_x_t3_evt0
	.word	t3_evt0
	.word	_x_delta
	.word	delta
	.word	_x_t0_evt0
	.word	t0_evt0
	.word	_x_gate_l0
	.word	gate_l0
	.word	_x_t5_l0
	.word	t5_l0
	.word	_x_t0_evt1
	.word	t0_evt1
	.word	_x_gate_l1
	.word	gate_l1
	.word	_x_t5_l1
	.word	t5_l1
	.word	_x_t6_evt0
	.word	t6_evt0
	.word	_x_gate_y
	.word	gate_y
	.word	_x_t4_evt1
	.word	t4_evt1
	.word	_x_t5_x
	.word	t5_x
	.word	_x_t4_l1
	.word	t4_l1
	.word	_x_t5_evt0
	.word	t5_evt0
	.word	_x_t0_l0
	.word	t0_l0
	.word	_x_t0_l1
	.word	t0_l1
	.word	_x_t1_evt0
	.word	t1_evt0
	.word	_x_t10_l0
	.word	t10_l0
	.word	_x_controller_evt1
	.word	controller_evt1
	.word	_x_t8_l0
	.word	t8_l0
	.word	_x_gate_evt1
	.word	gate_evt1
	.word	_x_t5_evt1
	.word	t5_evt1
	.word	_x_t6_x
	.word	t6_x
	.word	_x_controller_z
	.word	controller_z
	.word	_x_t6_l0
	.word	t6_l0
	.word	_x_t10_l1
	.word	t10_l1
	.word	_x_controller_evt2
	.word	controller_evt2
	.word	_x_t8_l1
	.word	t8_l1
	.word	_x_gate_evt0
	.word	gate_evt0
	.word	_x_t0_x
	.word	t0_x
	.word	_x_controller_cnt
	.word	controller_cnt
	.word	_x_t6_l1
	.word	t6_l1
	.word	_x_t7_evt0
	.word	t7_evt0
	.word	_x_t3_evt1
	.word	t3_evt1
	.word	_x_t4_x
	.word	t4_x
	.word	_x__diverge_delta
	.word	_diverge_delta
	.word	_x_t3_l0
	.word	t3_l0
	.word	_x_t3_l1
	.word	t3_l1
	.word	_x_t4_evt0
	.word	t4_evt0
	.word	_x_t4_l0
	.word	t4_l0
	.word	_x_t6_evt1
	.word	t6_evt1
	.word	_x_t7_x
	.word	t7_x
	.word	_x_t7_evt1
	.word	t7_evt1
	.word	_x_t8_x
	.word	t8_x
	.word	_x_t7_l0
	.word	t7_l0
	.word	_x_t7_l1
	.word	t7_l1
	.word	_x_t8_evt0
	.word	t8_evt0
	.word	_x_t8_evt1
	.word	t8_evt1
	.word	_x_t9_x
	.word	t9_x
.L205:
	mov	r3, #0
.L707:
	str	r3, [fp, #-24]
	ldr	r3, .L794
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+4
	strb	r2, [r3]
	ldr	r3, .L794+8
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+12
	strb	r2, [r3]
	ldr	r3, .L794+16
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+20
	strb	r2, [r3]
	ldr	r3, .L794+24
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+28
	strb	r2, [r3]
	ldr	r3, .L794+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L794+36
	str	r3, [r2]	@ float
	ldr	r3, .L794+40
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+44
	strb	r2, [r3]
	ldr	r3, .L794+48
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+52
	strb	r2, [r3]
	ldr	r3, .L794+56
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+60
	strb	r2, [r3]
	ldr	r3, .L794+64
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+68
	strb	r2, [r3]
	ldr	r3, .L794+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L794+76
	str	r3, [r2]	@ float
	ldr	r3, .L794+80
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+84
	strb	r2, [r3]
	ldr	r3, .L794+88
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+92
	strb	r2, [r3]
	ldr	r3, .L794+96
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+100
	strb	r2, [r3]
	ldr	r3, .L794+104
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+108
	strb	r2, [r3]
	ldr	r3, .L794+112
	ldr	r3, [r3]	@ float
	ldr	r2, .L794+116
	str	r3, [r2]	@ float
	ldr	r3, .L794+120
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+124
	strb	r2, [r3]
	ldr	r3, .L794+128
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+132
	strb	r2, [r3]
	ldr	r3, .L794+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L794+140
	str	r3, [r2]	@ float
	ldr	r3, .L794+144
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+148
	strb	r2, [r3]
	ldr	r3, .L794+152
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+156
	strb	r2, [r3]
	ldr	r3, .L794+160
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+164
	strb	r2, [r3]
	ldr	r3, .L794+168
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+172
	strb	r2, [r3]
	ldr	r3, .L794+176
	ldr	r3, [r3]	@ float
	ldr	r2, .L794+180
	str	r3, [r2]	@ float
	ldr	r3, .L794+184
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+188
	strb	r2, [r3]
	ldr	r3, .L794+192
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+196
	strb	r2, [r3]
	ldr	r3, .L794+200
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+204
	strb	r2, [r3]
	ldr	r3, .L794+208
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+212
	strb	r2, [r3]
	ldr	r3, .L794+216
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+220
	strb	r2, [r3]
	ldr	r3, .L794+224
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+228
	strb	r2, [r3]
	ldr	r3, .L794+232
	ldr	r3, [r3]	@ float
	ldr	r2, .L794+236
	str	r3, [r2]	@ float
	ldr	r3, .L794+240
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+244
	strb	r2, [r3]
	ldr	r3, .L794+248
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+252
	strb	r2, [r3]
	ldr	r3, .L794+256
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+260
	strb	r2, [r3]
	ldr	r3, .L794+264
	ldr	r3, [r3]	@ float
	ldr	r2, .L794+268
	str	r3, [r2]	@ float
	ldr	r3, .L794+272
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+276
	strb	r2, [r3]
	ldr	r3, .L794+280
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+284
	strb	r2, [r3]
	ldr	r3, .L794+288
	ldr	r3, [r3]	@ float
	ldr	r2, .L794+292
	str	r3, [r2]	@ float
	ldr	r3, .L794+296
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+300
	strb	r2, [r3]
	ldr	r3, .L794+304
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+308
	strb	r2, [r3]
	ldr	r3, .L794+312
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+316
	strb	r2, [r3]
	ldr	r3, .L794+320
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+324
	strb	r2, [r3]
	ldr	r3, .L794+328
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+332
	strb	r2, [r3]
	ldr	r3, .L794+336
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+340
	strb	r2, [r3]
	ldr	r3, .L794+344
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+348
	strb	r2, [r3]
	ldr	r3, .L794+352
	ldr	r3, [r3]	@ float
	ldr	r2, .L794+356
	str	r3, [r2]	@ float
	ldr	r3, .L794+360
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+364
	strb	r2, [r3]
	ldr	r3, .L794+368
	ldr	r3, [r3]	@ float
	ldr	r2, .L794+372
	str	r3, [r2]	@ float
	ldr	r3, .L794+376
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+380
	strb	r2, [r3]
	ldr	r3, .L794+384
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+388
	strb	r2, [r3]
	ldr	r3, .L794+392
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+396
	strb	r2, [r3]
	ldr	r3, .L794+400
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+404
	strb	r2, [r3]
	ldr	r3, .L794+408
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+412
	strb	r2, [r3]
	ldr	r3, .L794+416
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+420
	strb	r2, [r3]
	ldr	r3, .L794+424
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+428
	strb	r2, [r3]
	ldr	r3, .L794+432
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+436
	strb	r2, [r3]
	ldr	r3, .L794+440
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+444
	strb	r2, [r3]
	ldr	r3, .L794+448
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+452
	strb	r2, [r3]
	ldr	r3, .L794+456
	ldr	r3, [r3]	@ float
	ldr	r2, .L794+460
	str	r3, [r2]	@ float
	ldr	r3, .L794+464
	ldr	r3, [r3]	@ float
	ldr	r2, .L794+468
	str	r3, [r2]	@ float
	ldr	r3, .L794+472
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+476
	strb	r2, [r3]
	ldr	r3, .L794+480
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+484
	strb	r2, [r3]
	ldr	r3, .L794+488
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+492
	strb	r2, [r3]
	ldr	r3, .L794+496
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+500
	strb	r2, [r3]
	ldr	r3, .L794+504
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+508
	strb	r2, [r3]
	ldr	r3, .L794+512
	ldr	r3, [r3]	@ float
	ldr	r2, .L794+516
	str	r3, [r2]	@ float
	ldr	r3, .L794+520
	ldr	r3, [r3]
	ldr	r2, .L794+524
	str	r3, [r2]
	ldr	r3, .L794+528
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+532
	strb	r2, [r3]
	ldr	r3, .L794+536
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+540
	strb	r2, [r3]
	ldr	r3, .L794+544
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+548
	strb	r2, [r3]
	ldr	r3, .L794+552
	ldr	r3, [r3]	@ float
	ldr	r2, .L794+556
	str	r3, [r2]	@ float
	ldr	r3, .L794+560
	ldr	r3, [r3]	@ float
	ldr	r2, .L794+564
	str	r3, [r2]	@ float
	ldr	r3, .L794+568
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+572
	strb	r2, [r3]
	ldr	r3, .L794+576
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+580
	strb	r2, [r3]
	ldr	r3, .L794+584
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+588
	strb	r2, [r3]
	ldr	r3, .L794+592
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+596
	strb	r2, [r3]
	ldr	r3, .L794+600
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+604
	strb	r2, [r3]
	ldr	r3, .L794+608
	ldr	r3, [r3]	@ float
	ldr	r2, .L794+612
	str	r3, [r2]	@ float
	ldr	r3, .L794+616
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+620
	strb	r2, [r3]
	ldr	r3, .L794+624
	ldr	r3, [r3]	@ float
	ldr	r2, .L794+628
	str	r3, [r2]	@ float
	ldr	r3, .L794+632
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+636
	strb	r2, [r3]
	ldr	r3, .L794+640
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+644
	strb	r2, [r3]
	ldr	r3, .L794+648
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+652
	strb	r2, [r3]
	ldr	r3, .L794+656
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L794+660
	strb	r2, [r3]
	ldr	r3, .L794+664
	ldr	r3, [r3]	@ float
	ldr	r2, .L794+668
	str	r3, [r2]	@ float
.L200:
	ldr	r3, [fp, #-24]
	cmp	r3, #0
	bne	.L708
	mov	r3, #0
	mov	r0, r3
	sub	sp, fp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, fp, pc}
	.size	main, .-main
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
