	.file	"984685.c"
	.intel_syntax noprefix
	.text
	.globl	globalState
	.section	.data.rel.local,"aw"
	.align 8
	.type	globalState, @object
	.size	globalState, 8
globalState:
	.quad	global_state
	.text
	.globl	__VERIFIER_nondet_int
	.type	__VERIFIER_nondet_int, @function
__VERIFIER_nondet_int:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, DWORD PTR -4[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	__VERIFIER_nondet_int, .-__VERIFIER_nondet_int
	.globl	__bss_start
	.bss
	.align 32
	.type	__bss_start, @object
	.size	__bss_start, 32
__bss_start:
	.zero	32
	.globl	STATE_REG_RAX
	.align 4
	.type	STATE_REG_RAX, @object
	.size	STATE_REG_RAX, 4
STATE_REG_RAX:
	.zero	4
	.globl	STATE_REG_RBX
	.align 4
	.type	STATE_REG_RBX, @object
	.size	STATE_REG_RBX, 4
STATE_REG_RBX:
	.zero	4
	.globl	STATE_REG_RCX
	.align 4
	.type	STATE_REG_RCX, @object
	.size	STATE_REG_RCX, 4
STATE_REG_RCX:
	.zero	4
	.globl	STATE_REG_RDX
	.align 4
	.type	STATE_REG_RDX, @object
	.size	STATE_REG_RDX, 4
STATE_REG_RDX:
	.zero	4
	.globl	STATE_REG_RSI
	.align 4
	.type	STATE_REG_RSI, @object
	.size	STATE_REG_RSI, 4
STATE_REG_RSI:
	.zero	4
	.globl	STATE_REG_RDI
	.align 4
	.type	STATE_REG_RDI, @object
	.size	STATE_REG_RDI, 4
STATE_REG_RDI:
	.zero	4
	.globl	STATE_REG_RSP
	.align 4
	.type	STATE_REG_RSP, @object
	.size	STATE_REG_RSP, 4
STATE_REG_RSP:
	.zero	4
	.globl	STATE_REG_RBP
	.align 4
	.type	STATE_REG_RBP, @object
	.size	STATE_REG_RBP, 4
STATE_REG_RBP:
	.zero	4
	.globl	STATE_REG_R8
	.align 4
	.type	STATE_REG_R8, @object
	.size	STATE_REG_R8, 4
STATE_REG_R8:
	.zero	4
	.globl	STATE_REG_R9
	.align 4
	.type	STATE_REG_R9, @object
	.size	STATE_REG_R9, 4
STATE_REG_R9:
	.zero	4
	.globl	STATE_REG_R10
	.align 4
	.type	STATE_REG_R10, @object
	.size	STATE_REG_R10, 4
STATE_REG_R10:
	.zero	4
	.globl	STATE_REG_R11
	.align 4
	.type	STATE_REG_R11, @object
	.size	STATE_REG_R11, 4
STATE_REG_R11:
	.zero	4
	.globl	STATE_REG_R12
	.align 4
	.type	STATE_REG_R12, @object
	.size	STATE_REG_R12, 4
STATE_REG_R12:
	.zero	4
	.globl	STATE_REG_R13
	.align 4
	.type	STATE_REG_R13, @object
	.size	STATE_REG_R13, 4
STATE_REG_R13:
	.zero	4
	.globl	STATE_REG_R14
	.align 4
	.type	STATE_REG_R14, @object
	.size	STATE_REG_R14, 4
STATE_REG_R14:
	.zero	4
	.globl	STATE_REG_R15
	.align 4
	.type	STATE_REG_R15, @object
	.size	STATE_REG_R15, 4
STATE_REG_R15:
	.zero	4
	.globl	STATE_REG_IP
	.align 4
	.type	STATE_REG_IP, @object
	.size	STATE_REG_IP, 4
STATE_REG_IP:
	.zero	4
	.text
	.type	llvm_OC_ctpop_OC_i32, @function
llvm_OC_ctpop_OC_i32:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	DWORD PTR -4[rbp], 0
	jmp	.L4
.L6:
	mov	eax, DWORD PTR -20[rbp]
	and	eax, 1
	test	eax, eax
	je	.L5
	add	DWORD PTR -4[rbp], 1
.L5:
	sar	DWORD PTR -20[rbp]
.L4:
	cmp	DWORD PTR -20[rbp], 0
	jne	.L6
	mov	eax, DWORD PTR -4[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	llvm_OC_ctpop_OC_i32, .-llvm_OC_ctpop_OC_i32
	.type	llvm_select_u32, @function
llvm_select_u32:
.LFB2:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	DWORD PTR -24[rbp], esi
	mov	DWORD PTR -28[rbp], edx
	cmp	DWORD PTR -20[rbp], 0
	je	.L9
	mov	eax, DWORD PTR -24[rbp]
	jmp	.L10
.L9:
	mov	eax, DWORD PTR -28[rbp]
.L10:
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE2:
	.size	llvm_select_u32, .-llvm_select_u32
	.type	llvm_add_u32, @function
llvm_add_u32:
.LFB3:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	DWORD PTR -24[rbp], esi
	mov	edx, DWORD PTR -20[rbp]
	mov	eax, DWORD PTR -24[rbp]
	add	eax, edx
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE3:
	.size	llvm_add_u32, .-llvm_add_u32
	.type	llvm_add_u64, @function
llvm_add_u64:
.LFB4:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	DWORD PTR -24[rbp], esi
	mov	edx, DWORD PTR -20[rbp]
	mov	eax, DWORD PTR -24[rbp]
	add	eax, edx
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE4:
	.size	llvm_add_u64, .-llvm_add_u64
	.type	llvm_lshr_u32, @function
llvm_lshr_u32:
.LFB5:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	DWORD PTR -24[rbp], esi
	mov	eax, DWORD PTR -24[rbp]
	mov	edx, DWORD PTR -20[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE5:
	.size	llvm_lshr_u32, .-llvm_lshr_u32
	.type	llvm_lshr_u64, @function
llvm_lshr_u64:
.LFB6:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	DWORD PTR -24[rbp], esi
	mov	eax, DWORD PTR -24[rbp]
	mov	edx, DWORD PTR -20[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE6:
	.size	llvm_lshr_u64, .-llvm_lshr_u64
	.type	llvm_and_u8, @function
llvm_and_u8:
.LFB7:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	DWORD PTR -24[rbp], esi
	mov	eax, DWORD PTR -20[rbp]
	and	eax, DWORD PTR -24[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE7:
	.size	llvm_and_u8, .-llvm_and_u8
	.type	llvm_xor_u8, @function
llvm_xor_u8:
.LFB8:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	DWORD PTR -24[rbp], esi
	mov	eax, DWORD PTR -20[rbp]
	xor	eax, DWORD PTR -24[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE8:
	.size	llvm_xor_u8, .-llvm_xor_u8
	.globl	global_state
	.bss
	.align 32
	.type	global_state, @object
	.size	global_state, 1704
global_state:
	.zero	1704
	.text
	.globl	main
	.type	main, @function
main:
.LFB9:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 304
	mov	rax, QWORD PTR globalState[rip]
	mov	QWORD PTR -80[rbp], rax
	mov	eax, DWORD PTR STATE_REG_RBP[rip]
	mov	DWORD PTR -280[rbp], eax
	mov	eax, DWORD PTR STATE_REG_RSP[rip]
	mov	DWORD PTR -276[rbp], eax
	mov	eax, DWORD PTR -276[rbp]
	sub	eax, 8
	mov	DWORD PTR -272[rbp], eax
	mov	eax, DWORD PTR -272[rbp]
	cdqe
	mov	rdx, rax
	mov	eax, DWORD PTR -280[rbp]
	mov	DWORD PTR [rdx], eax
	mov	eax, DWORD PTR -272[rbp]
	mov	DWORD PTR STATE_REG_RBP[rip], eax
	mov	eax, DWORD PTR -276[rbp]
	sub	eax, 24
	mov	DWORD PTR -268[rbp], eax
	mov	rax, QWORD PTR -80[rbp]
	add	rax, 1040
	mov	QWORD PTR -72[rbp], rax
	cmp	DWORD PTR -272[rbp], 15
	setle	al
	movzx	edx, al
	mov	rax, QWORD PTR -72[rbp]
	mov	DWORD PTR [rax], edx
	mov	eax, DWORD PTR -268[rbp]
	movzx	eax, al
	mov	edi, eax
	call	llvm_OC_ctpop_OC_i32
	mov	DWORD PTR -264[rbp], eax
	mov	rax, QWORD PTR -80[rbp]
	add	rax, 1048
	mov	QWORD PTR -64[rbp], rax
	mov	eax, DWORD PTR -264[rbp]
	and	eax, 1
	mov	DWORD PTR -260[rbp], eax
	mov	eax, DWORD PTR -260[rbp]
	xor	eax, 1
	mov	edx, eax
	mov	rax, QWORD PTR -64[rbp]
	mov	DWORD PTR [rax], edx
	mov	rax, QWORD PTR -80[rbp]
	add	rax, 1056
	mov	QWORD PTR -56[rbp], rax
	mov	eax, DWORD PTR -272[rbp]
	xor	eax, 16
	xor	eax, DWORD PTR -268[rbp]
	sar	eax, 4
	mov	DWORD PTR -256[rbp], eax
	mov	eax, DWORD PTR -256[rbp]
	and	eax, 1
	mov	edx, eax
	mov	rax, QWORD PTR -56[rbp]
	mov	DWORD PTR [rax], edx
	mov	rax, QWORD PTR -80[rbp]
	add	rax, 1064
	mov	QWORD PTR -48[rbp], rax
	cmp	DWORD PTR -268[rbp], 0
	sete	al
	movzx	edx, al
	mov	rax, QWORD PTR -48[rbp]
	mov	DWORD PTR [rax], edx
	mov	edx, 63
	mov	eax, DWORD PTR -268[rbp]
	mov	ecx, edx
	sar	eax, cl
	mov	DWORD PTR -252[rbp], eax
	mov	rax, QWORD PTR -80[rbp]
	add	rax, 1072
	mov	QWORD PTR -40[rbp], rax
	mov	rax, QWORD PTR -40[rbp]
	mov	edx, DWORD PTR -252[rbp]
	mov	DWORD PTR [rax], edx
	mov	edx, 63
	mov	eax, DWORD PTR -272[rbp]
	mov	ecx, edx
	sar	eax, cl
	mov	DWORD PTR -248[rbp], eax
	mov	rax, QWORD PTR -80[rbp]
	add	rax, 1088
	mov	QWORD PTR -32[rbp], rax
	mov	eax, DWORD PTR -252[rbp]
	xor	eax, DWORD PTR -248[rbp]
	mov	edx, eax
	mov	eax, DWORD PTR -248[rbp]
	add	eax, edx
	mov	DWORD PTR -244[rbp], eax
	cmp	DWORD PTR -244[rbp], 2
	sete	al
	movzx	edx, al
	mov	rax, QWORD PTR -32[rbp]
	mov	DWORD PTR [rax], edx
	mov	eax, DWORD PTR -276[rbp]
	sub	eax, 12
	mov	DWORD PTR -240[rbp], eax
	mov	eax, DWORD PTR -240[rbp]
	cdqe
	mov	DWORD PTR [rax], 0
	mov	eax, DWORD PTR -276[rbp]
	sub	eax, 16
	mov	DWORD PTR -236[rbp], eax
	mov	eax, DWORD PTR -236[rbp]
	cdqe
	mov	DWORD PTR [rax], 100
	mov	DWORD PTR STATE_REG_RAX[rip], 0
	mov	eax, DWORD PTR -276[rbp]
	sub	eax, 32
	mov	DWORD PTR -232[rbp], eax
	mov	eax, DWORD PTR -232[rbp]
	cdqe
	mov	rdx, rax
	mov	eax, DWORD PTR -228[rbp]
	add	eax, 36
	mov	DWORD PTR [rdx], eax
	mov	eax, DWORD PTR -232[rbp]
	mov	DWORD PTR STATE_REG_RSP[rip], eax
	mov	eax, 0
	call	__VERIFIER_nondet_int
	mov	DWORD PTR STATE_REG_RAX[rip], eax
	mov	eax, DWORD PTR STATE_REG_RBP[rip]
	mov	DWORD PTR -224[rbp], eax
	mov	eax, DWORD PTR STATE_REG_RAX[rip]
	mov	DWORD PTR -220[rbp], eax
	mov	eax, DWORD PTR -224[rbp]
	sub	eax, 12
	mov	DWORD PTR -216[rbp], eax
	mov	eax, DWORD PTR -216[rbp]
	cdqe
	mov	QWORD PTR -24[rbp], rax
	mov	rax, QWORD PTR -24[rbp]
	mov	edx, DWORD PTR -220[rbp]
	mov	DWORD PTR [rax], edx
	mov	eax, DWORD PTR -224[rbp]
	sub	eax, 4
	mov	DWORD PTR -212[rbp], eax
	mov	eax, DWORD PTR -212[rbp]
	cdqe
	mov	QWORD PTR -16[rbp], rax
	mov	rax, QWORD PTR -16[rbp]
	mov	eax, DWORD PTR [rax]
	mov	DWORD PTR -208[rbp], eax
	mov	eax, DWORD PTR -208[rbp]
	sub	eax, 39
	mov	DWORD PTR -204[rbp], eax
	mov	eax, DWORD PTR -204[rbp]
	sar	eax, 31
	mov	DWORD PTR -200[rbp], eax
	mov	eax, DWORD PTR -208[rbp]
	sar	eax, 31
	mov	DWORD PTR -196[rbp], eax
	mov	eax, DWORD PTR -200[rbp]
	xor	eax, DWORD PTR -196[rbp]
	mov	edx, eax
	mov	eax, DWORD PTR -196[rbp]
	add	eax, edx
	mov	DWORD PTR -192[rbp], eax
	cmp	DWORD PTR -204[rbp], 0
	setne	cl
	cmp	DWORD PTR -200[rbp], 0
	setne	al
	movzx	edx, al
	cmp	DWORD PTR -192[rbp], 2
	sete	al
	movzx	eax, al
	xor	eax, edx
	and	eax, 1
	xor	eax, 1
	and	eax, ecx
	test	al, al
	je	.L31
	mov	eax, DWORD PTR -208[rbp]
	mov	DWORD PTR -296[rbp], eax
	mov	eax, DWORD PTR -204[rbp]
	mov	DWORD PTR -292[rbp], eax
	mov	eax, DWORD PTR -200[rbp]
	mov	DWORD PTR -288[rbp], eax
	mov	eax, DWORD PTR -200[rbp]
	xor	eax, DWORD PTR -196[rbp]
	mov	edx, eax
	mov	eax, DWORD PTR -196[rbp]
	add	eax, edx
	mov	DWORD PTR -124[rbp], eax
	cmp	DWORD PTR -124[rbp], 2
	sete	al
	movzx	eax, al
	mov	DWORD PTR -284[rbp], eax
	jmp	.L26
.L31:
	nop
.L25:
	cmp	DWORD PTR -220[rbp], 0
	sete	al
	movzx	eax, al
	mov	edx, 2
	mov	esi, 1
	mov	edi, eax
	call	llvm_select_u32
	mov	DWORD PTR -188[rbp], eax
	mov	edx, DWORD PTR -188[rbp]
	mov	eax, DWORD PTR -208[rbp]
	add	eax, edx
	mov	DWORD PTR -184[rbp], eax
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR -184[rbp]
	mov	DWORD PTR [rax], edx
	mov	eax, DWORD PTR -184[rbp]
	sub	eax, 39
	mov	DWORD PTR -180[rbp], eax
	mov	eax, DWORD PTR -180[rbp]
	sar	eax, 31
	mov	DWORD PTR -176[rbp], eax
	mov	eax, DWORD PTR -184[rbp]
	sar	eax, 31
	mov	DWORD PTR -172[rbp], eax
	mov	eax, DWORD PTR -176[rbp]
	xor	eax, DWORD PTR -172[rbp]
	mov	edx, eax
	mov	eax, DWORD PTR -172[rbp]
	add	eax, edx
	mov	DWORD PTR -168[rbp], eax
	cmp	DWORD PTR -180[rbp], 0
	sete	cl
	cmp	DWORD PTR -176[rbp], 0
	setne	al
	movzx	edx, al
	cmp	DWORD PTR -168[rbp], 2
	sete	al
	movzx	eax, al
	xor	eax, edx
	and	eax, 1
	or	eax, ecx
	test	al, al
	je	.L27
	mov	eax, DWORD PTR -184[rbp]
	mov	DWORD PTR -300[rbp], eax
	jmp	.L28
.L27:
	mov	eax, DWORD PTR -184[rbp]
	mov	DWORD PTR -296[rbp], eax
	mov	eax, DWORD PTR -180[rbp]
	mov	DWORD PTR -292[rbp], eax
	mov	eax, DWORD PTR -176[rbp]
	mov	DWORD PTR -288[rbp], eax
	mov	eax, DWORD PTR -176[rbp]
	xor	eax, DWORD PTR -172[rbp]
	mov	edx, eax
	mov	eax, DWORD PTR -172[rbp]
	add	eax, edx
	mov	DWORD PTR -164[rbp], eax
	cmp	DWORD PTR -164[rbp], 2
	sete	al
	movzx	eax, al
	mov	DWORD PTR -284[rbp], eax
	jmp	.L26
.L28:
	mov	eax, DWORD PTR -300[rbp]
	mov	DWORD PTR -160[rbp], eax
	mov	rax, QWORD PTR -24[rbp]
	mov	eax, DWORD PTR [rax]
	mov	DWORD PTR -156[rbp], eax
	cmp	DWORD PTR -156[rbp], 0
	sete	al
	movzx	eax, al
	mov	edx, 2
	mov	esi, 1
	mov	edi, eax
	call	llvm_select_u32
	mov	DWORD PTR -152[rbp], eax
	mov	edx, DWORD PTR -152[rbp]
	mov	eax, DWORD PTR -160[rbp]
	add	eax, edx
	mov	DWORD PTR -148[rbp], eax
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR -148[rbp]
	mov	DWORD PTR [rax], edx
	mov	eax, DWORD PTR -148[rbp]
	sub	eax, 39
	mov	DWORD PTR -144[rbp], eax
	mov	eax, DWORD PTR -144[rbp]
	sar	eax, 31
	mov	DWORD PTR -140[rbp], eax
	mov	eax, DWORD PTR -148[rbp]
	sar	eax, 31
	mov	DWORD PTR -136[rbp], eax
	mov	eax, DWORD PTR -140[rbp]
	xor	eax, DWORD PTR -136[rbp]
	mov	edx, eax
	mov	eax, DWORD PTR -136[rbp]
	add	eax, edx
	mov	DWORD PTR -132[rbp], eax
	cmp	DWORD PTR -144[rbp], 0
	sete	cl
	cmp	DWORD PTR -140[rbp], 0
	setne	al
	movzx	edx, al
	cmp	DWORD PTR -132[rbp], 2
	sete	al
	movzx	eax, al
	xor	eax, edx
	and	eax, 1
	or	eax, ecx
	test	al, al
	je	.L29
	mov	eax, DWORD PTR -148[rbp]
	mov	DWORD PTR -300[rbp], eax
	jmp	.L28
.L29:
	mov	eax, DWORD PTR -148[rbp]
	mov	DWORD PTR -296[rbp], eax
	mov	eax, DWORD PTR -144[rbp]
	mov	DWORD PTR -292[rbp], eax
	mov	eax, DWORD PTR -140[rbp]
	mov	DWORD PTR -288[rbp], eax
	mov	eax, DWORD PTR -140[rbp]
	xor	eax, DWORD PTR -136[rbp]
	mov	edx, eax
	mov	eax, DWORD PTR -136[rbp]
	add	eax, edx
	mov	DWORD PTR -128[rbp], eax
	cmp	DWORD PTR -128[rbp], 2
	sete	al
	movzx	eax, al
	mov	DWORD PTR -284[rbp], eax
	nop
.L26:
	mov	eax, DWORD PTR -296[rbp]
	mov	DWORD PTR -120[rbp], eax
	mov	eax, DWORD PTR -292[rbp]
	mov	DWORD PTR -116[rbp], eax
	mov	eax, DWORD PTR -288[rbp]
	mov	DWORD PTR -112[rbp], eax
	mov	eax, DWORD PTR -284[rbp]
	and	eax, 1
	mov	DWORD PTR -108[rbp], eax
	mov	eax, DWORD PTR -116[rbp]
	movzx	eax, al
	mov	edi, eax
	call	llvm_OC_ctpop_OC_i32
	mov	DWORD PTR -104[rbp], eax
	cmp	DWORD PTR -120[rbp], 38
	setle	al
	movzx	edx, al
	mov	rax, QWORD PTR -72[rbp]
	mov	DWORD PTR [rax], edx
	mov	eax, DWORD PTR -104[rbp]
	and	eax, 1
	mov	DWORD PTR -100[rbp], eax
	mov	eax, DWORD PTR -100[rbp]
	xor	eax, 1
	mov	edx, eax
	mov	rax, QWORD PTR -64[rbp]
	mov	DWORD PTR [rax], edx
	mov	eax, DWORD PTR -116[rbp]
	xor	eax, DWORD PTR -120[rbp]
	sar	eax, 4
	mov	DWORD PTR -96[rbp], eax
	mov	eax, DWORD PTR -96[rbp]
	and	eax, 1
	mov	edx, eax
	mov	rax, QWORD PTR -56[rbp]
	mov	DWORD PTR [rax], edx
	mov	rax, QWORD PTR -48[rbp]
	mov	DWORD PTR [rax], 0
	mov	rax, QWORD PTR -40[rbp]
	mov	edx, DWORD PTR -112[rbp]
	mov	DWORD PTR [rax], edx
	mov	rax, QWORD PTR -32[rbp]
	mov	edx, DWORD PTR -108[rbp]
	mov	DWORD PTR [rax], edx
	mov	DWORD PTR STATE_REG_RAX[rip], 0
	mov	eax, DWORD PTR -224[rbp]
	cdqe
	mov	eax, DWORD PTR [rax]
	mov	DWORD PTR -92[rbp], eax
	mov	eax, DWORD PTR -92[rbp]
	mov	DWORD PTR STATE_REG_RBP[rip], eax
	mov	eax, DWORD PTR -224[rbp]
	add	eax, 8
	mov	DWORD PTR -88[rbp], eax
	mov	eax, DWORD PTR -88[rbp]
	cdqe
	mov	eax, DWORD PTR [rax]
	mov	DWORD PTR -84[rbp], eax
	mov	eax, DWORD PTR -84[rbp]
	mov	DWORD PTR STATE_REG_IP[rip], eax
	mov	eax, DWORD PTR -224[rbp]
	add	eax, 16
	mov	DWORD PTR STATE_REG_RSP[rip], eax
	mov	rax, QWORD PTR -8[rbp]
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE9:
	.size	main, .-main
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"984685.c"
	.text
	.global	globalState
	.data
	.align	2
	.type	globalState, %object
	.size	globalState, 4
globalState:
	.word	global_state
	.text
	.align	2
	.global	__VERIFIER_nondet_int
	.syntax unified
	.arm
	.fpu softvfp
	.type	__VERIFIER_nondet_int, %function
__VERIFIER_nondet_int:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	ldr	r3, [fp, #-8]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	__VERIFIER_nondet_int, .-__VERIFIER_nondet_int
	.comm	__bss_start,32,4
	.comm	STATE_REG_RAX,4,4
	.comm	STATE_REG_RBX,4,4
	.comm	STATE_REG_RCX,4,4
	.comm	STATE_REG_RDX,4,4
	.comm	STATE_REG_RSI,4,4
	.comm	STATE_REG_RDI,4,4
	.comm	STATE_REG_RSP,4,4
	.comm	STATE_REG_RBP,4,4
	.comm	STATE_REG_R8,4,4
	.comm	STATE_REG_R9,4,4
	.comm	STATE_REG_R10,4,4
	.comm	STATE_REG_R11,4,4
	.comm	STATE_REG_R12,4,4
	.comm	STATE_REG_R13,4,4
	.comm	STATE_REG_R14,4,4
	.comm	STATE_REG_R15,4,4
	.comm	STATE_REG_IP,4,4
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	llvm_OC_ctpop_OC_i32, %function
llvm_OC_ctpop_OC_i32:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L4
.L6:
	ldr	r3, [fp, #-16]
	and	r3, r3, #1
	cmp	r3, #0
	beq	.L5
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L5:
	ldr	r3, [fp, #-16]
	asr	r3, r3, #1
	str	r3, [fp, #-16]
.L4:
	ldr	r3, [fp, #-16]
	cmp	r3, #0
	bne	.L6
	ldr	r3, [fp, #-8]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	llvm_OC_ctpop_OC_i32, .-llvm_OC_ctpop_OC_i32
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	llvm_select_u32, %function
llvm_select_u32:
	@ args = 0, pretend = 0, frame = 24
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #28
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	str	r2, [fp, #-24]
	ldr	r3, [fp, #-16]
	cmp	r3, #0
	beq	.L9
	ldr	r3, [fp, #-20]
	b	.L10
.L9:
	ldr	r3, [fp, #-24]
.L10:
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	llvm_select_u32, .-llvm_select_u32
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	llvm_add_u32, %function
llvm_add_u32:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	ldr	r2, [fp, #-16]
	ldr	r3, [fp, #-20]
	add	r3, r2, r3
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	llvm_add_u32, .-llvm_add_u32
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	llvm_add_u64, %function
llvm_add_u64:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	ldr	r2, [fp, #-16]
	ldr	r3, [fp, #-20]
	add	r3, r2, r3
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	llvm_add_u64, .-llvm_add_u64
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	llvm_lshr_u32, %function
llvm_lshr_u32:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	ldr	r2, [fp, #-16]
	ldr	r3, [fp, #-20]
	asr	r3, r2, r3
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	llvm_lshr_u32, .-llvm_lshr_u32
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	llvm_lshr_u64, %function
llvm_lshr_u64:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	ldr	r2, [fp, #-16]
	ldr	r3, [fp, #-20]
	asr	r3, r2, r3
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	llvm_lshr_u64, .-llvm_lshr_u64
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	llvm_and_u8, %function
llvm_and_u8:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	ldr	r2, [fp, #-16]
	ldr	r3, [fp, #-20]
	and	r3, r3, r2
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	llvm_and_u8, .-llvm_and_u8
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	llvm_xor_u8, %function
llvm_xor_u8:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	ldr	r2, [fp, #-16]
	ldr	r3, [fp, #-20]
	eor	r3, r3, r2
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	llvm_xor_u8, .-llvm_xor_u8
	.comm	global_state,1704,8
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 264
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #264
	ldr	r3, .L32
	ldr	r3, [r3]
	str	r3, [fp, #-244]
	ldr	r3, .L32+4
	ldr	r3, [r3]
	str	r3, [fp, #-240]
	ldr	r3, .L32+8
	ldr	r3, [r3]
	str	r3, [fp, #-236]
	ldr	r3, [fp, #-236]
	sub	r3, r3, #8
	str	r3, [fp, #-232]
	ldr	r3, [fp, #-232]
	ldr	r2, [fp, #-240]
	str	r2, [r3]
	ldr	r2, .L32+4
	ldr	r3, [fp, #-232]
	str	r3, [r2]
	ldr	r3, [fp, #-236]
	sub	r3, r3, #24
	str	r3, [fp, #-228]
	ldr	r3, [fp, #-244]
	add	r3, r3, #1040
	str	r3, [fp, #-224]
	ldr	r3, [fp, #-232]
	cmp	r3, #15
	movle	r3, #1
	movgt	r3, #0
	and	r3, r3, #255
	mov	r2, r3
	ldr	r3, [fp, #-224]
	str	r2, [r3]
	ldr	r3, [fp, #-228]
	and	r3, r3, #255
	mov	r0, r3
	bl	llvm_OC_ctpop_OC_i32
	str	r0, [fp, #-220]
	ldr	r3, [fp, #-244]
	add	r3, r3, #1040
	add	r3, r3, #8
	str	r3, [fp, #-216]
	ldr	r3, [fp, #-220]
	and	r3, r3, #1
	str	r3, [fp, #-212]
	ldr	r3, [fp, #-212]
	eor	r2, r3, #1
	ldr	r3, [fp, #-216]
	str	r2, [r3]
	ldr	r3, [fp, #-244]
	add	r3, r3, #1056
	str	r3, [fp, #-208]
	ldr	r2, [fp, #-232]
	ldr	r3, [fp, #-228]
	eor	r3, r3, r2
	asr	r3, r3, #4
	eor	r3, r3, #1
	str	r3, [fp, #-204]
	ldr	r3, [fp, #-204]
	and	r2, r3, #1
	ldr	r3, [fp, #-208]
	str	r2, [r3]
	ldr	r3, [fp, #-244]
	add	r3, r3, #1056
	add	r3, r3, #8
	str	r3, [fp, #-200]
	ldr	r3, [fp, #-228]
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r3, r3, #255
	mov	r2, r3
	ldr	r3, [fp, #-200]
	str	r2, [r3]
	mov	r2, #63
	ldr	r3, [fp, #-228]
	asr	r3, r3, r2
	str	r3, [fp, #-196]
	ldr	r3, [fp, #-244]
	add	r3, r3, #1072
	str	r3, [fp, #-192]
	ldr	r3, [fp, #-192]
	ldr	r2, [fp, #-196]
	str	r2, [r3]
	mov	r2, #63
	ldr	r3, [fp, #-232]
	asr	r3, r3, r2
	str	r3, [fp, #-188]
	ldr	r3, [fp, #-244]
	add	r3, r3, #1088
	str	r3, [fp, #-184]
	ldr	r2, [fp, #-196]
	ldr	r3, [fp, #-188]
	eor	r3, r3, r2
	ldr	r2, [fp, #-188]
	add	r3, r2, r3
	str	r3, [fp, #-180]
	ldr	r3, [fp, #-180]
	cmp	r3, #2
	moveq	r3, #1
	movne	r3, #0
	and	r3, r3, #255
	mov	r2, r3
	ldr	r3, [fp, #-184]
	str	r2, [r3]
	ldr	r3, [fp, #-236]
	sub	r3, r3, #12
	str	r3, [fp, #-176]
	ldr	r3, [fp, #-176]
	mov	r2, #0
	str	r2, [r3]
	ldr	r3, [fp, #-236]
	sub	r3, r3, #16
	str	r3, [fp, #-172]
	ldr	r3, [fp, #-172]
	mov	r2, #100
	str	r2, [r3]
	ldr	r3, .L32+12
	mov	r2, #0
	str	r2, [r3]
	ldr	r3, [fp, #-236]
	sub	r3, r3, #32
	str	r3, [fp, #-168]
	ldr	r3, [fp, #-168]
	ldr	r2, [fp, #-164]
	add	r2, r2, #36
	str	r2, [r3]
	ldr	r2, .L32+8
	ldr	r3, [fp, #-168]
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L32+12
	str	r3, [r2]
	ldr	r3, .L32+4
	ldr	r3, [r3]
	str	r3, [fp, #-160]
	ldr	r3, .L32+12
	ldr	r3, [r3]
	str	r3, [fp, #-156]
	ldr	r3, [fp, #-160]
	sub	r3, r3, #12
	str	r3, [fp, #-152]
	ldr	r3, [fp, #-152]
	str	r3, [fp, #-148]
	ldr	r3, [fp, #-148]
	ldr	r2, [fp, #-156]
	str	r2, [r3]
	ldr	r3, [fp, #-160]
	sub	r3, r3, #4
	str	r3, [fp, #-144]
	ldr	r3, [fp, #-144]
	str	r3, [fp, #-140]
	ldr	r3, [fp, #-140]
	ldr	r3, [r3]
	str	r3, [fp, #-136]
	ldr	r3, [fp, #-136]
	sub	r3, r3, #39
	str	r3, [fp, #-132]
	ldr	r3, [fp, #-132]
	asr	r3, r3, #31
	str	r3, [fp, #-128]
	ldr	r3, [fp, #-136]
	asr	r3, r3, #31
	str	r3, [fp, #-124]
	ldr	r2, [fp, #-128]
	ldr	r3, [fp, #-124]
	eor	r3, r3, r2
	ldr	r2, [fp, #-124]
	add	r3, r2, r3
	str	r3, [fp, #-120]
	ldr	r3, [fp, #-132]
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r2, r3, #255
	ldr	r3, [fp, #-128]
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	mov	r1, r3
	ldr	r3, [fp, #-120]
	cmp	r3, #2
	moveq	r3, #1
	movne	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r1
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	and	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L31
	ldr	r3, [fp, #-136]
	str	r3, [fp, #-260]
	ldr	r3, [fp, #-132]
	str	r3, [fp, #-256]
	ldr	r3, [fp, #-128]
	str	r3, [fp, #-252]
	ldr	r2, [fp, #-128]
	ldr	r3, [fp, #-124]
	eor	r3, r3, r2
	ldr	r2, [fp, #-124]
	add	r3, r2, r3
	str	r3, [fp, #-52]
	ldr	r3, [fp, #-52]
	cmp	r3, #2
	moveq	r3, #1
	movne	r3, #0
	and	r3, r3, #255
	str	r3, [fp, #-248]
	b	.L26
.L31:
	nop
.L25:
	ldr	r3, [fp, #-156]
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r3, r3, #255
	mov	r2, #2
	mov	r1, #1
	mov	r0, r3
	bl	llvm_select_u32
	str	r0, [fp, #-116]
	ldr	r2, [fp, #-116]
	ldr	r3, [fp, #-136]
	add	r3, r2, r3
	str	r3, [fp, #-112]
	ldr	r3, [fp, #-140]
	ldr	r2, [fp, #-112]
	str	r2, [r3]
	ldr	r3, [fp, #-112]
	sub	r3, r3, #39
	str	r3, [fp, #-108]
	ldr	r3, [fp, #-108]
	asr	r3, r3, #31
	str	r3, [fp, #-104]
	ldr	r3, [fp, #-112]
	asr	r3, r3, #31
	str	r3, [fp, #-100]
	ldr	r2, [fp, #-104]
	ldr	r3, [fp, #-100]
	eor	r3, r3, r2
	ldr	r2, [fp, #-100]
	add	r3, r2, r3
	str	r3, [fp, #-96]
	ldr	r3, [fp, #-108]
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, [fp, #-104]
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	mov	r1, r3
	ldr	r3, [fp, #-96]
	cmp	r3, #2
	moveq	r3, #1
	movne	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r1
	and	r3, r3, #1
	and	r3, r3, #255
	orr	r3, r2, r3
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L27
	ldr	r3, [fp, #-112]
	str	r3, [fp, #-264]
	b	.L28
.L27:
	ldr	r3, [fp, #-112]
	str	r3, [fp, #-260]
	ldr	r3, [fp, #-108]
	str	r3, [fp, #-256]
	ldr	r3, [fp, #-104]
	str	r3, [fp, #-252]
	ldr	r2, [fp, #-104]
	ldr	r3, [fp, #-100]
	eor	r3, r3, r2
	ldr	r2, [fp, #-100]
	add	r3, r2, r3
	str	r3, [fp, #-92]
	ldr	r3, [fp, #-92]
	cmp	r3, #2
	moveq	r3, #1
	movne	r3, #0
	and	r3, r3, #255
	str	r3, [fp, #-248]
	b	.L26
.L28:
	ldr	r3, [fp, #-264]
	str	r3, [fp, #-88]
	ldr	r3, [fp, #-148]
	ldr	r3, [r3]
	str	r3, [fp, #-84]
	ldr	r3, [fp, #-84]
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r3, r3, #255
	mov	r2, #2
	mov	r1, #1
	mov	r0, r3
	bl	llvm_select_u32
	str	r0, [fp, #-80]
	ldr	r2, [fp, #-80]
	ldr	r3, [fp, #-88]
	add	r3, r2, r3
	str	r3, [fp, #-76]
	ldr	r3, [fp, #-140]
	ldr	r2, [fp, #-76]
	str	r2, [r3]
	ldr	r3, [fp, #-76]
	sub	r3, r3, #39
	str	r3, [fp, #-72]
	ldr	r3, [fp, #-72]
	asr	r3, r3, #31
	str	r3, [fp, #-68]
	ldr	r3, [fp, #-76]
	asr	r3, r3, #31
	str	r3, [fp, #-64]
	ldr	r2, [fp, #-68]
	ldr	r3, [fp, #-64]
	eor	r3, r3, r2
	ldr	r2, [fp, #-64]
	add	r3, r2, r3
	str	r3, [fp, #-60]
	ldr	r3, [fp, #-72]
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, [fp, #-68]
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	mov	r1, r3
	ldr	r3, [fp, #-60]
	cmp	r3, #2
	moveq	r3, #1
	movne	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r1
	and	r3, r3, #1
	and	r3, r3, #255
	orr	r3, r2, r3
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L29
	ldr	r3, [fp, #-76]
	str	r3, [fp, #-264]
	b	.L28
.L29:
	ldr	r3, [fp, #-76]
	str	r3, [fp, #-260]
	ldr	r3, [fp, #-72]
	str	r3, [fp, #-256]
	ldr	r3, [fp, #-68]
	str	r3, [fp, #-252]
	ldr	r2, [fp, #-68]
	ldr	r3, [fp, #-64]
	eor	r3, r3, r2
	ldr	r2, [fp, #-64]
	add	r3, r2, r3
	str	r3, [fp, #-56]
	ldr	r3, [fp, #-56]
	cmp	r3, #2
	moveq	r3, #1
	movne	r3, #0
	and	r3, r3, #255
	str	r3, [fp, #-248]
	nop
.L26:
	ldr	r3, [fp, #-260]
	str	r3, [fp, #-48]
	ldr	r3, [fp, #-256]
	str	r3, [fp, #-44]
	ldr	r3, [fp, #-252]
	str	r3, [fp, #-40]
	ldr	r3, [fp, #-248]
	and	r3, r3, #1
	str	r3, [fp, #-36]
	ldr	r3, [fp, #-44]
	and	r3, r3, #255
	mov	r0, r3
	bl	llvm_OC_ctpop_OC_i32
	str	r0, [fp, #-32]
	ldr	r3, [fp, #-48]
	cmp	r3, #38
	movle	r3, #1
	movgt	r3, #0
	and	r3, r3, #255
	mov	r2, r3
	ldr	r3, [fp, #-224]
	str	r2, [r3]
	ldr	r3, [fp, #-32]
	and	r3, r3, #1
	str	r3, [fp, #-28]
	ldr	r3, [fp, #-28]
	eor	r2, r3, #1
	ldr	r3, [fp, #-216]
	str	r2, [r3]
	ldr	r2, [fp, #-44]
	ldr	r3, [fp, #-48]
	eor	r3, r3, r2
	asr	r3, r3, #4
	str	r3, [fp, #-24]
	ldr	r3, [fp, #-24]
	and	r2, r3, #1
	ldr	r3, [fp, #-208]
	str	r2, [r3]
	ldr	r3, [fp, #-200]
	mov	r2, #0
	str	r2, [r3]
	ldr	r3, [fp, #-192]
	ldr	r2, [fp, #-40]
	str	r2, [r3]
	ldr	r3, [fp, #-184]
	ldr	r2, [fp, #-36]
	str	r2, [r3]
	ldr	r3, .L32+12
	mov	r2, #0
	str	r2, [r3]
	ldr	r3, [fp, #-160]
	ldr	r3, [r3]
	str	r3, [fp, #-20]
	ldr	r2, .L32+4
	ldr	r3, [fp, #-20]
	str	r3, [r2]
	ldr	r3, [fp, #-160]
	add	r3, r3, #8
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	ldr	r3, [r3]
	str	r3, [fp, #-12]
	ldr	r2, .L32+16
	ldr	r3, [fp, #-12]
	str	r3, [r2]
	ldr	r3, [fp, #-160]
	add	r3, r3, #16
	ldr	r2, .L32+8
	str	r3, [r2]
	ldr	r3, [fp, #-8]
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L33:
	.align	2
.L32:
	.word	globalState
	.word	STATE_REG_RBP
	.word	STATE_REG_RSP
	.word	STATE_REG_RAX
	.word	STATE_REG_IP
	.size	main, .-main
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
