	.file	"728111.c"
	.intel_syntax noprefix
	.text
	.globl	__VERIFIER_nondet_bool
	.type	__VERIFIER_nondet_bool, @function
__VERIFIER_nondet_bool:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	call	__VERIFIER_nondet_int@PLT
	test	eax, eax
	setne	al
	movzx	eax, al
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.globl	main
	.type	main, @function
main:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 112
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR -60[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -112[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -108[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -104[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -100[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -96[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -92[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -88[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -84[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -80[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -76[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -72[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -68[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -64[rbp], eax
	cmp	DWORD PTR -92[rbp], 0
	je	.L4
	cmp	DWORD PTR -96[rbp], 0
	jne	.L4
	cmp	DWORD PTR -104[rbp], 0
	jne	.L4
	mov	eax, 1
	jmp	.L5
.L4:
	mov	eax, 0
.L5:
	mov	DWORD PTR -56[rbp], eax
	jmp	.L6
.L107:
	cmp	DWORD PTR -96[rbp], 0
	je	.L7
	cmp	DWORD PTR -104[rbp], 0
	je	.L7
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR -60[rbp], eax
	jmp	.L8
.L7:
	sub	DWORD PTR -60[rbp], 1
.L8:
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -52[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -48[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -44[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -40[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -36[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -32[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -28[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -24[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -20[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -16[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -12[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -8[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -4[rbp], eax
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -100[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -12[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC0[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -12[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC1[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -76[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -12[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC2[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -64[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -12[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -100[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -12[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC0[rip]
	jp	.L113
	ucomisd	xmm0, QWORD PTR .LC0[rip]
	je	.L14
.L113:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -12[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	jp	.L114
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	je	.L14
.L114:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -76[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -12[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jp	.L115
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	je	.L14
.L115:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -64[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -12[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jp	.L9
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jne	.L9
.L14:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -16[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC1[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -88[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -16[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC4[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -72[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -16[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC5[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -64[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -16[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC6[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -16[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	jp	.L120
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	je	.L23
.L120:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -88[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -16[rbp]
	subsd	xmm0, xmm1
	movsd	xmm1, QWORD PTR .LC4[rip]
	ucomisd	xmm0, xmm1
	jp	.L121
	movsd	xmm1, QWORD PTR .LC4[rip]
	ucomisd	xmm0, xmm1
	je	.L23
.L121:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -72[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -16[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	jp	.L122
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	je	.L23
.L122:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -64[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -16[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	jp	.L9
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	jne	.L9
.L23:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -4[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC7[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -100[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -4[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC8[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -72[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -4[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC5[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -64[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -4[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC9[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -4[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC7[rip]
	jp	.L127
	ucomisd	xmm0, QWORD PTR .LC7[rip]
	je	.L32
.L127:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -100[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -4[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	jp	.L128
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	je	.L32
.L128:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -72[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -4[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	jp	.L129
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	je	.L32
.L129:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -64[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -4[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jp	.L9
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jne	.L9
.L32:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -28[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC10[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -28[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC10[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -72[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -28[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC9[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -64[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -28[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC11[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	jp	.L134
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	je	.L41
.L134:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	jp	.L135
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	je	.L41
.L135:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -72[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jp	.L136
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	je	.L41
.L136:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -64[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	jp	.L9
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	jne	.L9
.L41:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -20[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC9[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -100[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -20[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC8[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -72[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -20[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC12[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -76[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -20[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC9[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -20[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jp	.L141
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	je	.L50
.L141:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -100[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -20[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	jp	.L142
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	je	.L50
.L142:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -72[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -20[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC12[rip]
	jp	.L143
	ucomisd	xmm0, QWORD PTR .LC12[rip]
	je	.L50
.L143:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -76[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -20[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jp	.L9
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jne	.L9
.L50:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -8[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC13[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -100[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -8[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC6[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -88[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -8[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC2[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -8[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC6[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	jp	.L148
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	je	.L59
.L148:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -100[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	jp	.L149
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	je	.L59
.L149:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -88[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jp	.L150
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	je	.L59
.L150:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	jp	.L9
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	jne	.L9
.L59:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -40[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -88[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -40[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC5[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -72[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -40[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC14[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -76[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -40[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC15[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -40[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jp	.L155
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	je	.L68
.L155:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -88[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -40[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	jp	.L156
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	je	.L68
.L156:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -72[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -40[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC14[rip]
	jp	.L157
	ucomisd	xmm0, QWORD PTR .LC14[rip]
	je	.L68
.L157:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -76[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -40[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	jp	.L9
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	jne	.L9
.L68:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -100[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -52[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC12[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -68[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -52[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC13[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -72[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -52[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC6[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -52[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC2[rip]
	comisd	xmm0, xmm1
	jb	.L9
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -100[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -52[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC12[rip]
	jp	.L162
	ucomisd	xmm0, QWORD PTR .LC12[rip]
	je	.L77
.L162:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -68[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -52[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	jp	.L163
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	je	.L77
.L163:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -72[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -52[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	jp	.L164
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	je	.L77
.L164:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -52[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jp	.L9
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jne	.L9
.L77:
	cmp	DWORD PTR -24[rbp], 0
	jne	.L82
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -16[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	comisd	xmm0, QWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L82
	cmp	DWORD PTR -48[rbp], 0
	je	.L83
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -8[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -52[rbp]
	subsd	xmm0, xmm1
	comisd	xmm0, QWORD PTR .LC16[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L83
.L82:
	mov	edx, 1
	jmp	.L84
.L83:
	mov	edx, 0
.L84:
	mov	eax, DWORD PTR -92[rbp]
	cmp	edx, eax
	jne	.L9
	cmp	DWORD PTR -24[rbp], 0
	jne	.L85
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -16[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	comisd	xmm0, QWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L86
.L85:
	mov	edx, 1
	jmp	.L87
.L86:
	mov	edx, 0
.L87:
	mov	eax, DWORD PTR -84[rbp]
	cmp	edx, eax
	jne	.L9
	cmp	DWORD PTR -24[rbp], 0
	jne	.L88
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -16[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	comisd	xmm0, QWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L88
	cmp	DWORD PTR -48[rbp], 0
	je	.L89
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -8[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -52[rbp]
	subsd	xmm0, xmm1
	comisd	xmm0, QWORD PTR .LC16[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L89
.L88:
	mov	edx, 1
	jmp	.L90
.L89:
	mov	edx, 0
.L90:
	mov	eax, DWORD PTR -108[rbp]
	cmp	edx, eax
	jne	.L9
	cmp	DWORD PTR -96[rbp], 0
	je	.L91
	cmp	DWORD PTR -104[rbp], 0
	jne	.L92
.L91:
	cmp	DWORD PTR -96[rbp], 0
	je	.L93
	cmp	DWORD PTR -104[rbp], 0
	jne	.L94
.L93:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -76[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -68[rbp]
	subsd	xmm0, xmm1
	comisd	xmm0, QWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L94
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -76[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -68[rbp]
	subsd	xmm0, xmm1
	comisd	xmm0, QWORD PTR .LC2[rip]
	jb	.L95
	cmp	DWORD PTR -84[rbp], 0
	je	.L94
.L95:
	cmp	DWORD PTR -96[rbp], 0
	je	.L92
.L94:
	mov	edx, 1
	jmp	.L97
.L92:
	mov	edx, 0
.L97:
	mov	eax, DWORD PTR -36[rbp]
	cmp	edx, eax
	jne	.L9
	cmp	DWORD PTR -96[rbp], 0
	je	.L98
	cmp	DWORD PTR -104[rbp], 0
	jne	.L99
.L98:
	cmp	DWORD PTR -96[rbp], 0
	je	.L100
	cmp	DWORD PTR -104[rbp], 0
	jne	.L101
.L100:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -76[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -68[rbp]
	subsd	xmm0, xmm1
	comisd	xmm0, QWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L101
	cmp	DWORD PTR -84[rbp], 0
	jne	.L101
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -76[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -68[rbp]
	subsd	xmm0, xmm1
	comisd	xmm0, QWORD PTR .LC2[rip]
	jb	.L102
	cmp	DWORD PTR -84[rbp], 0
	jne	.L102
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -68[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -112[rbp]
	subsd	xmm0, xmm1
	comisd	xmm0, QWORD PTR .LC16[rip]
	jnb	.L101
	cmp	DWORD PTR -108[rbp], 0
	je	.L101
.L102:
	cmp	DWORD PTR -104[rbp], 0
	je	.L99
.L101:
	mov	edx, 1
	jmp	.L104
.L99:
	mov	edx, 0
.L104:
	mov	eax, DWORD PTR -44[rbp]
	cmp	edx, eax
	jne	.L9
	mov	eax, 1
	jmp	.L105
.L9:
	mov	eax, 0
.L105:
	mov	DWORD PTR -56[rbp], eax
	movss	xmm0, DWORD PTR -52[rbp]
	movss	DWORD PTR -112[rbp], xmm0
	mov	eax, DWORD PTR -48[rbp]
	mov	DWORD PTR -108[rbp], eax
	mov	eax, DWORD PTR -44[rbp]
	mov	DWORD PTR -104[rbp], eax
	movss	xmm0, DWORD PTR -40[rbp]
	movss	DWORD PTR -100[rbp], xmm0
	mov	eax, DWORD PTR -36[rbp]
	mov	DWORD PTR -96[rbp], eax
	mov	eax, DWORD PTR -32[rbp]
	mov	DWORD PTR -92[rbp], eax
	movss	xmm0, DWORD PTR -28[rbp]
	movss	DWORD PTR -88[rbp], xmm0
	mov	eax, DWORD PTR -24[rbp]
	mov	DWORD PTR -84[rbp], eax
	movss	xmm0, DWORD PTR -20[rbp]
	movss	DWORD PTR -80[rbp], xmm0
	movss	xmm0, DWORD PTR -16[rbp]
	movss	DWORD PTR -76[rbp], xmm0
	movss	xmm0, DWORD PTR -12[rbp]
	movss	DWORD PTR -72[rbp], xmm0
	movss	xmm0, DWORD PTR -8[rbp]
	movss	DWORD PTR -68[rbp], xmm0
	movss	xmm0, DWORD PTR -4[rbp]
	movss	DWORD PTR -64[rbp], xmm0
.L6:
	cmp	DWORD PTR -60[rbp], 0
	js	.L106
	cmp	DWORD PTR -56[rbp], 0
	jne	.L107
.L106:
	mov	eax, 0
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	main, .-main
	.section	.rodata
	.align 8
.LC0:
	.long	0
	.long	-1073741824
	.align 8
.LC1:
	.long	0
	.long	-1070465024
	.align 8
.LC2:
	.long	0
	.long	-1070858240
	.align 8
.LC3:
	.long	0
	.long	-1072693248
	.align 8
.LC4:
	.long	0
	.long	-1074790400
	.align 8
.LC5:
	.long	0
	.long	-1070530560
	.align 8
.LC6:
	.long	0
	.long	-1070989312
	.align 8
.LC7:
	.long	0
	.long	-1071906816
	.align 8
.LC8:
	.long	0
	.long	-1070399488
	.align 8
.LC9:
	.long	0
	.long	-1070727168
	.align 8
.LC10:
	.long	0
	.long	-1073217536
	.align 8
.LC11:
	.long	0
	.long	-1070596096
	.align 8
.LC12:
	.long	0
	.long	-1070333952
	.align 8
.LC13:
	.long	0
	.long	-1071120384
	.align 8
.LC14:
	.long	0
	.long	-1071644672
	.align 8
.LC15:
	.long	0
	.long	-1071513600
	.align 8
.LC16:
	.long	0
	.long	1075576832
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"728111.c"
	.text
	.align	2
	.global	__VERIFIER_nondet_bool
	.syntax unified
	.arm
	.fpu softvfp
	.type	__VERIFIER_nondet_bool, %function
__VERIFIER_nondet_bool:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	mov	r0, r3
	pop	{fp, pc}
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.global	__aeabi_f2d
	.global	__aeabi_dsub
	.global	__aeabi_dcmple
	.global	__aeabi_dcmpeq
	.global	__aeabi_dcmpge
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 112
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, fp, lr}
	add	fp, sp, #12
	sub	sp, sp, #112
	bl	__VERIFIER_nondet_int
	str	r0, [fp, #-72]
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-124]	@ float
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-120]
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-116]
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-112]	@ float
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-108]
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-104]
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-100]	@ float
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-96]
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-92]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-88]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-84]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-80]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-76]	@ float
	ldr	r3, [fp, #-104]
	cmp	r3, #0
	beq	.L4
	ldr	r3, [fp, #-108]
	cmp	r3, #0
	bne	.L4
	ldr	r3, [fp, #-116]
	cmp	r3, #0
	bne	.L4
	mov	r3, #1
	b	.L5
.L4:
	mov	r3, #0
.L5:
	str	r3, [fp, #-68]
	b	.L6
.L90:
	ldr	r3, [fp, #-108]
	cmp	r3, #0
	beq	.L7
	ldr	r3, [fp, #-116]
	cmp	r3, #0
	beq	.L7
	bl	__VERIFIER_nondet_int
	str	r0, [fp, #-72]
	b	.L8
.L7:
	ldr	r3, [fp, #-72]
	sub	r3, r3, #1
	str	r3, [fp, #-72]
.L8:
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-64]	@ float
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-60]
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-56]
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-52]	@ float
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-48]
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-44]
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-40]	@ float
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-36]
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-32]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-28]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-24]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-20]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-16]	@ float
	ldr	r0, [fp, #-112]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+56
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-76]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+28
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-112]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L14
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L14
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+56
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L14
	ldr	r0, [fp, #-76]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+28
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
.L14:
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+4
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+32
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-76]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+52
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L20
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+4
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L20
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+32
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L20
	ldr	r0, [fp, #-76]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+52
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
.L20:
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+8
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-112]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+12
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+32
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-76]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+16
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+8
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L26
	ldr	r0, [fp, #-112]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+12
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L26
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+32
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L26
	ldr	r0, [fp, #-76]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+16
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
.L26:
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+20
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+20
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+16
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-76]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+24
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+20
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L32
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+20
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L32
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+16
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L32
	ldr	r0, [fp, #-76]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+24
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
.L32:
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+16
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-112]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+12
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+16
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+16
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L38
	ldr	r0, [fp, #-112]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+12
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L38
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+44
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L38
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+16
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
.L38:
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+48
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-112]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+52
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+56
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+52
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+48
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L44
	ldr	r0, [fp, #-112]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+52
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L44
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+56
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L44
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+52
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
.L44:
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+28
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+32
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	b	.L127
.L128:
	.align	2
.L126:
	.word	-1070465024
	.word	-1074790400
	.word	-1071906816
	.word	-1070399488
	.word	-1070727168
	.word	-1073217536
	.word	-1070596096
	.word	-1072693248
	.word	-1070530560
	.word	-1071644672
	.word	-1071513600
	.word	-1070333952
	.word	-1071120384
	.word	-1070989312
	.word	-1070858240
	.word	1075576832
.L127:
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+36
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+40
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+28
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L50
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+32
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L50
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+36
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L50
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+40
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
.L50:
	ldr	r0, [fp, #-112]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+48
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+52
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+56
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
	ldr	r0, [fp, #-112]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+44
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L56
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+48
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L56
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+52
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L56
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+56
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L9
.L56:
	ldr	r3, [fp, #-36]
	cmp	r3, #0
	bne	.L58
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r3, #1
	mov	r4, r3
	mov	r2, #0
	ldr	r3, .L126+56
	bl	__aeabi_dcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L59
	mov	r3, #0
	mov	r4, r3
.L59:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L58
	ldr	r3, [fp, #-60]
	cmp	r3, #0
	beq	.L60
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r3, #1
	mov	r4, r3
	mov	r2, #0
	ldr	r3, .L126+60
	bl	__aeabi_dcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L61
	mov	r3, #0
	mov	r4, r3
.L61:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L60
.L58:
	mov	r2, #1
	b	.L62
.L60:
	mov	r2, #0
.L62:
	ldr	r3, [fp, #-104]
	cmp	r2, r3
	bne	.L9
	ldr	r3, [fp, #-36]
	cmp	r3, #0
	bne	.L63
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r3, #1
	mov	r4, r3
	mov	r2, #0
	ldr	r3, .L126+56
	bl	__aeabi_dcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L64
	mov	r3, #0
	mov	r4, r3
.L64:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L65
.L63:
	mov	r2, #1
	b	.L66
.L65:
	mov	r2, #0
.L66:
	ldr	r3, [fp, #-96]
	cmp	r2, r3
	bne	.L9
	ldr	r3, [fp, #-36]
	cmp	r3, #0
	bne	.L67
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r3, #1
	mov	r4, r3
	mov	r2, #0
	ldr	r3, .L126+56
	bl	__aeabi_dcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L68
	mov	r3, #0
	mov	r4, r3
.L68:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L67
	ldr	r3, [fp, #-60]
	cmp	r3, #0
	beq	.L69
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r3, #1
	mov	r4, r3
	mov	r2, #0
	ldr	r3, .L126+60
	bl	__aeabi_dcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L70
	mov	r3, #0
	mov	r4, r3
.L70:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L69
.L67:
	mov	r2, #1
	b	.L71
.L69:
	mov	r2, #0
.L71:
	ldr	r3, [fp, #-120]
	cmp	r2, r3
	bne	.L9
	ldr	r3, [fp, #-108]
	cmp	r3, #0
	beq	.L72
	ldr	r3, [fp, #-116]
	cmp	r3, #0
	bne	.L73
.L72:
	ldr	r3, [fp, #-108]
	cmp	r3, #0
	beq	.L74
	ldr	r3, [fp, #-116]
	cmp	r3, #0
	bne	.L75
.L74:
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r3, #1
	mov	r4, r3
	mov	r2, #0
	ldr	r3, .L126+56
	bl	__aeabi_dcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L76
	mov	r3, #0
	mov	r4, r3
.L76:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L75
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+56
	bl	__aeabi_dcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L77
	ldr	r3, [fp, #-96]
	cmp	r3, #0
	beq	.L75
.L77:
	ldr	r3, [fp, #-108]
	cmp	r3, #0
	beq	.L73
.L75:
	mov	r2, #1
	b	.L79
.L73:
	mov	r2, #0
.L79:
	ldr	r3, [fp, #-48]
	cmp	r2, r3
	bne	.L9
	ldr	r3, [fp, #-108]
	cmp	r3, #0
	beq	.L80
	ldr	r3, [fp, #-116]
	cmp	r3, #0
	bne	.L81
.L80:
	ldr	r3, [fp, #-108]
	cmp	r3, #0
	beq	.L82
	ldr	r3, [fp, #-116]
	cmp	r3, #0
	bne	.L83
.L82:
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r3, #1
	mov	r4, r3
	mov	r2, #0
	ldr	r3, .L126+56
	bl	__aeabi_dcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L84
	mov	r3, #0
	mov	r4, r3
.L84:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L83
	ldr	r3, [fp, #-96]
	cmp	r3, #0
	bne	.L83
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+56
	bl	__aeabi_dcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L85
	ldr	r3, [fp, #-96]
	cmp	r3, #0
	bne	.L85
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L126+60
	bl	__aeabi_dcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L83
	ldr	r3, [fp, #-120]
	cmp	r3, #0
	beq	.L83
.L85:
	ldr	r3, [fp, #-116]
	cmp	r3, #0
	beq	.L81
.L83:
	mov	r2, #1
	b	.L87
.L81:
	mov	r2, #0
.L87:
	ldr	r3, [fp, #-56]
	cmp	r2, r3
	bne	.L9
	mov	r3, #1
	b	.L88
.L9:
	mov	r3, #0
.L88:
	str	r3, [fp, #-68]
	ldr	r3, [fp, #-64]	@ float
	str	r3, [fp, #-124]	@ float
	ldr	r3, [fp, #-60]
	str	r3, [fp, #-120]
	ldr	r3, [fp, #-56]
	str	r3, [fp, #-116]
	ldr	r3, [fp, #-52]	@ float
	str	r3, [fp, #-112]	@ float
	ldr	r3, [fp, #-48]
	str	r3, [fp, #-108]
	ldr	r3, [fp, #-44]
	str	r3, [fp, #-104]
	ldr	r3, [fp, #-40]	@ float
	str	r3, [fp, #-100]	@ float
	ldr	r3, [fp, #-36]
	str	r3, [fp, #-96]
	ldr	r3, [fp, #-32]	@ float
	str	r3, [fp, #-92]	@ float
	ldr	r3, [fp, #-28]	@ float
	str	r3, [fp, #-88]	@ float
	ldr	r3, [fp, #-24]	@ float
	str	r3, [fp, #-84]	@ float
	ldr	r3, [fp, #-20]	@ float
	str	r3, [fp, #-80]	@ float
	ldr	r3, [fp, #-16]	@ float
	str	r3, [fp, #-76]	@ float
.L6:
	ldr	r3, [fp, #-72]
	cmp	r3, #0
	blt	.L89
	ldr	r3, [fp, #-68]
	cmp	r3, #0
	bne	.L90
.L89:
	mov	r3, #0
	mov	r0, r3
	sub	sp, fp, #12
	@ sp needed
	pop	{r4, r5, fp, pc}
	.size	main, .-main
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
