	.file	"411303.c"
	.intel_syntax noprefix
	.text
	.globl	__VERIFIER_nondet_bool
	.type	__VERIFIER_nondet_bool, @function
__VERIFIER_nondet_bool:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	call	__VERIFIER_nondet_int@PLT
	test	eax, eax
	setne	al
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.globl	p10_l0
	.bss
	.type	p10_l0, @object
	.size	p10_l0, 1
p10_l0:
	.zero	1
	.globl	_x_p10_l0
	.type	_x_p10_l0, @object
	.size	_x_p10_l0, 1
_x_p10_l0:
	.zero	1
	.globl	p9_l1
	.type	p9_l1, @object
	.size	p9_l1, 1
p9_l1:
	.zero	1
	.globl	_x_p9_l1
	.type	_x_p9_l1, @object
	.size	_x_p9_l1, 1
_x_p9_l1:
	.zero	1
	.globl	p9_l0
	.type	p9_l0, @object
	.size	p9_l0, 1
p9_l0:
	.zero	1
	.globl	_x_p9_l0
	.type	_x_p9_l0, @object
	.size	_x_p9_l0, 1
_x_p9_l0:
	.zero	1
	.globl	p6_l1
	.type	p6_l1, @object
	.size	p6_l1, 1
p6_l1:
	.zero	1
	.globl	_x_p6_l1
	.type	_x_p6_l1, @object
	.size	_x_p6_l1, 1
_x_p6_l1:
	.zero	1
	.globl	p6_l0
	.type	p6_l0, @object
	.size	p6_l0, 1
p6_l0:
	.zero	1
	.globl	_x_p6_l0
	.type	_x_p6_l0, @object
	.size	_x_p6_l0, 1
_x_p6_l0:
	.zero	1
	.globl	num6
	.align 4
	.type	num6, @object
	.size	num6, 4
num6:
	.zero	4
	.globl	_x_num6
	.align 4
	.type	_x_num6, @object
	.size	_x_num6, 4
_x_num6:
	.zero	4
	.globl	p3_l0
	.type	p3_l0, @object
	.size	p3_l0, 1
p3_l0:
	.zero	1
	.globl	_x_p3_l0
	.type	_x_p3_l0, @object
	.size	_x_p3_l0, 1
_x_p3_l0:
	.zero	1
	.globl	p8_l1
	.type	p8_l1, @object
	.size	p8_l1, 1
p8_l1:
	.zero	1
	.globl	_x_p8_l1
	.type	_x_p8_l1, @object
	.size	_x_p8_l1, 1
_x_p8_l1:
	.zero	1
	.globl	num5
	.align 4
	.type	num5, @object
	.size	num5, 4
num5:
	.zero	4
	.globl	_x_num5
	.align 4
	.type	_x_num5, @object
	.size	_x_num5, 4
_x_num5:
	.zero	4
	.globl	p2_l1
	.type	p2_l1, @object
	.size	p2_l1, 1
p2_l1:
	.zero	1
	.globl	_x_p2_l1
	.type	_x_p2_l1, @object
	.size	_x_p2_l1, 1
_x_p2_l1:
	.zero	1
	.globl	p8_l0
	.type	p8_l0, @object
	.size	p8_l0, 1
p8_l0:
	.zero	1
	.globl	_x_p8_l0
	.type	_x_p8_l0, @object
	.size	_x_p8_l0, 1
_x_p8_l0:
	.zero	1
	.globl	num4
	.align 4
	.type	num4, @object
	.size	num4, 4
num4:
	.zero	4
	.globl	_x_num4
	.align 4
	.type	_x_num4, @object
	.size	_x_num4, 4
_x_num4:
	.zero	4
	.globl	num3
	.align 4
	.type	num3, @object
	.size	num3, 4
num3:
	.zero	4
	.globl	_x_num3
	.align 4
	.type	_x_num3, @object
	.size	_x_num3, 4
_x_num3:
	.zero	4
	.globl	p0_l1
	.type	p0_l1, @object
	.size	p0_l1, 1
p0_l1:
	.zero	1
	.globl	_x_p0_l1
	.type	_x_p0_l1, @object
	.size	_x_p0_l1, 1
_x_p0_l1:
	.zero	1
	.globl	num2
	.align 4
	.type	num2, @object
	.size	num2, 4
num2:
	.zero	4
	.globl	_x_num2
	.align 4
	.type	_x_num2, @object
	.size	_x_num2, 4
_x_num2:
	.zero	4
	.globl	run2
	.type	run2, @object
	.size	run2, 1
run2:
	.zero	1
	.globl	_x_run2
	.type	_x_run2, @object
	.size	_x_run2, 1
_x_run2:
	.zero	1
	.globl	p10_l1
	.type	p10_l1, @object
	.size	p10_l1, 1
p10_l1:
	.zero	1
	.globl	_x_p10_l1
	.type	_x_p10_l1, @object
	.size	_x_p10_l1, 1
_x_p10_l1:
	.zero	1
	.globl	p0_l0
	.type	p0_l0, @object
	.size	p0_l0, 1
p0_l0:
	.zero	1
	.globl	_x_p0_l0
	.type	_x_p0_l0, @object
	.size	_x_p0_l0, 1
_x_p0_l0:
	.zero	1
	.globl	p7_l1
	.type	p7_l1, @object
	.size	p7_l1, 1
p7_l1:
	.zero	1
	.globl	_x_p7_l1
	.type	_x_p7_l1, @object
	.size	_x_p7_l1, 1
_x_p7_l1:
	.zero	1
	.globl	num1
	.align 4
	.type	num1, @object
	.size	num1, 4
num1:
	.zero	4
	.globl	_x_num1
	.align 4
	.type	_x_num1, @object
	.size	_x_num1, 4
_x_num1:
	.zero	4
	.globl	run1
	.type	run1, @object
	.size	run1, 1
run1:
	.zero	1
	.globl	_x_run1
	.type	_x_run1, @object
	.size	_x_run1, 1
_x_run1:
	.zero	1
	.globl	p7_l0
	.type	p7_l0, @object
	.size	p7_l0, 1
p7_l0:
	.zero	1
	.globl	_x_p7_l0
	.type	_x_p7_l0, @object
	.size	_x_p7_l0, 1
_x_p7_l0:
	.zero	1
	.globl	num0
	.align 4
	.type	num0, @object
	.size	num0, 4
num0:
	.zero	4
	.globl	_x_num0
	.align 4
	.type	_x_num0, @object
	.size	_x_num0, 4
_x_num0:
	.zero	4
	.globl	run0
	.type	run0, @object
	.size	run0, 1
run0:
	.zero	1
	.globl	_x_run0
	.type	_x_run0, @object
	.size	_x_run0, 1
_x_run0:
	.zero	1
	.globl	max_num
	.align 4
	.type	max_num, @object
	.size	max_num, 4
max_num:
	.zero	4
	.globl	_x_max_num
	.align 4
	.type	_x_max_num, @object
	.size	_x_max_num, 4
_x_max_num:
	.zero	4
	.globl	min_num
	.align 4
	.type	min_num, @object
	.size	min_num, 4
min_num:
	.zero	4
	.globl	_x_min_num
	.align 4
	.type	_x_min_num, @object
	.size	_x_min_num, 4
_x_min_num:
	.zero	4
	.globl	num7
	.align 4
	.type	num7, @object
	.size	num7, 4
num7:
	.zero	4
	.globl	_x_num7
	.align 4
	.type	_x_num7, @object
	.size	_x_num7, 4
_x_num7:
	.zero	4
	.globl	p3_l1
	.type	p3_l1, @object
	.size	p3_l1, 1
p3_l1:
	.zero	1
	.globl	_x_p3_l1
	.type	_x_p3_l1, @object
	.size	_x_p3_l1, 1
_x_p3_l1:
	.zero	1
	.globl	num8
	.align 4
	.type	num8, @object
	.size	num8, 4
num8:
	.zero	4
	.globl	_x_num8
	.align 4
	.type	_x_num8, @object
	.size	_x_num8, 4
_x_num8:
	.zero	4
	.globl	num9
	.align 4
	.type	num9, @object
	.size	num9, 4
num9:
	.zero	4
	.globl	_x_num9
	.align 4
	.type	_x_num9, @object
	.size	_x_num9, 4
_x_num9:
	.zero	4
	.globl	num10
	.align 4
	.type	num10, @object
	.size	num10, 4
num10:
	.zero	4
	.globl	_x_num10
	.align 4
	.type	_x_num10, @object
	.size	_x_num10, 4
_x_num10:
	.zero	4
	.globl	run3
	.type	run3, @object
	.size	run3, 1
run3:
	.zero	1
	.globl	_x_run3
	.type	_x_run3, @object
	.size	_x_run3, 1
_x_run3:
	.zero	1
	.globl	p1_l0
	.type	p1_l0, @object
	.size	p1_l0, 1
p1_l0:
	.zero	1
	.globl	_x_p1_l0
	.type	_x_p1_l0, @object
	.size	_x_p1_l0, 1
_x_p1_l0:
	.zero	1
	.globl	p2_l0
	.type	p2_l0, @object
	.size	p2_l0, 1
p2_l0:
	.zero	1
	.globl	_x_p2_l0
	.type	_x_p2_l0, @object
	.size	_x_p2_l0, 1
_x_p2_l0:
	.zero	1
	.globl	p1_l1
	.type	p1_l1, @object
	.size	p1_l1, 1
p1_l1:
	.zero	1
	.globl	_x_p1_l1
	.type	_x_p1_l1, @object
	.size	_x_p1_l1, 1
_x_p1_l1:
	.zero	1
	.globl	p4_l0
	.type	p4_l0, @object
	.size	p4_l0, 1
p4_l0:
	.zero	1
	.globl	_x_p4_l0
	.type	_x_p4_l0, @object
	.size	_x_p4_l0, 1
_x_p4_l0:
	.zero	1
	.globl	p4_l1
	.type	p4_l1, @object
	.size	p4_l1, 1
p4_l1:
	.zero	1
	.globl	_x_p4_l1
	.type	_x_p4_l1, @object
	.size	_x_p4_l1, 1
_x_p4_l1:
	.zero	1
	.globl	p5_l0
	.type	p5_l0, @object
	.size	p5_l0, 1
p5_l0:
	.zero	1
	.globl	_x_p5_l0
	.type	_x_p5_l0, @object
	.size	_x_p5_l0, 1
_x_p5_l0:
	.zero	1
	.globl	p5_l1
	.type	p5_l1, @object
	.size	p5_l1, 1
p5_l1:
	.zero	1
	.globl	_x_p5_l1
	.type	_x_p5_l1, @object
	.size	_x_p5_l1, 1
_x_p5_l1:
	.zero	1
	.text
	.globl	main
	.type	main, @function
main:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p10_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p9_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p9_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p6_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p6_l0[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR num6[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p3_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p8_l1[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR num5[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p2_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p8_l0[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR num4[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR num3[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p0_l1[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR num2[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR run2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p10_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p0_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p7_l1[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR num1[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR run1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p7_l0[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR num0[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR run0[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR max_num[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR min_num[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR num7[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p3_l1[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR num8[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR num9[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR num10[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR run3[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p1_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p2_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p1_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p4_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p4_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p5_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p5_l1[rip], al
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	jne	.L5
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	je	.L6
.L5:
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	je	.L7
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	je	.L6
.L7:
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	je	.L6
.L8:
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	je	.L4
.L6:
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	jne	.L9
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	je	.L10
.L9:
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	je	.L11
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	je	.L10
.L11:
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	je	.L12
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	je	.L10
.L12:
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	je	.L4
.L10:
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	jne	.L13
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	je	.L14
.L13:
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	je	.L15
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	je	.L14
.L15:
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	je	.L16
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	je	.L14
.L16:
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	je	.L4
.L14:
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	jne	.L17
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	je	.L18
.L17:
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	je	.L19
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	je	.L18
.L19:
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	je	.L20
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	je	.L18
.L20:
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	je	.L4
.L18:
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	jne	.L21
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	je	.L22
.L21:
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	je	.L23
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	je	.L22
.L23:
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	je	.L24
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	je	.L22
.L24:
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	je	.L4
.L22:
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	jne	.L25
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	je	.L26
.L25:
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	je	.L27
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	je	.L26
.L27:
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	je	.L28
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	je	.L26
.L28:
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	je	.L4
.L26:
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	jne	.L29
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	je	.L30
.L29:
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	je	.L31
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	je	.L30
.L31:
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	je	.L32
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	je	.L30
.L32:
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	je	.L4
.L30:
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	jne	.L33
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	je	.L34
.L33:
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	je	.L35
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	je	.L34
.L35:
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	je	.L36
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	je	.L34
.L36:
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	je	.L4
.L34:
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	jne	.L37
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L38
.L37:
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L39
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L38
.L39:
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L40
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L38
.L40:
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L4
.L38:
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	jne	.L41
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L42
.L41:
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L43
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L42
.L43:
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L44
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L42
.L44:
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L4
.L42:
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	jne	.L45
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L46
.L45:
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L47
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L46
.L47:
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L48
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L46
.L48:
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L4
.L46:
	mov	eax, DWORD PTR num0[rip]
	test	eax, eax
	jne	.L4
	mov	eax, DWORD PTR num1[rip]
	test	eax, eax
	jne	.L4
	mov	eax, DWORD PTR num2[rip]
	test	eax, eax
	jne	.L4
	mov	eax, DWORD PTR num3[rip]
	test	eax, eax
	jne	.L4
	mov	eax, DWORD PTR num4[rip]
	test	eax, eax
	jne	.L4
	mov	eax, DWORD PTR num5[rip]
	test	eax, eax
	jne	.L4
	mov	eax, DWORD PTR num6[rip]
	test	eax, eax
	jne	.L4
	mov	eax, DWORD PTR num7[rip]
	test	eax, eax
	jne	.L4
	mov	eax, DWORD PTR num8[rip]
	test	eax, eax
	jne	.L4
	mov	eax, DWORD PTR num9[rip]
	test	eax, eax
	jne	.L4
	mov	eax, DWORD PTR num10[rip]
	test	eax, eax
	jne	.L4
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	je	.L49
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L49
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L49
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L50
.L49:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	je	.L51
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L51
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L51
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L50
.L51:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	je	.L52
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L52
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L52
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L50
.L52:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L53
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	je	.L53
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L53
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L50
.L53:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L54
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	je	.L54
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L54
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L50
.L54:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L55
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	je	.L55
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L55
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L50
.L55:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L56
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	je	.L56
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L56
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L50
.L56:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L57
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L57
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L57
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L50
.L57:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L58
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L58
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L58
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L50
.L58:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L50
.L59:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L4
.L50:
	mov	edx, DWORD PTR num0[rip]
	mov	eax, DWORD PTR max_num[rip]
	cmp	edx, eax
	jg	.L4
	mov	edx, DWORD PTR num1[rip]
	mov	eax, DWORD PTR max_num[rip]
	cmp	edx, eax
	jg	.L4
	mov	edx, DWORD PTR num2[rip]
	mov	eax, DWORD PTR max_num[rip]
	cmp	edx, eax
	jg	.L4
	mov	edx, DWORD PTR num3[rip]
	mov	eax, DWORD PTR max_num[rip]
	cmp	edx, eax
	jg	.L4
	mov	edx, DWORD PTR num4[rip]
	mov	eax, DWORD PTR max_num[rip]
	cmp	edx, eax
	jg	.L4
	mov	edx, DWORD PTR num5[rip]
	mov	eax, DWORD PTR max_num[rip]
	cmp	edx, eax
	jg	.L4
	mov	edx, DWORD PTR num6[rip]
	mov	eax, DWORD PTR max_num[rip]
	cmp	edx, eax
	jg	.L4
	mov	edx, DWORD PTR num7[rip]
	mov	eax, DWORD PTR max_num[rip]
	cmp	edx, eax
	jg	.L4
	mov	edx, DWORD PTR num8[rip]
	mov	eax, DWORD PTR max_num[rip]
	cmp	edx, eax
	jg	.L4
	mov	edx, DWORD PTR num9[rip]
	mov	eax, DWORD PTR max_num[rip]
	cmp	edx, eax
	jg	.L4
	mov	edx, DWORD PTR num10[rip]
	mov	eax, DWORD PTR max_num[rip]
	cmp	edx, eax
	jg	.L4
	mov	edx, DWORD PTR num0[rip]
	mov	eax, DWORD PTR max_num[rip]
	cmp	edx, eax
	je	.L60
	mov	edx, DWORD PTR num1[rip]
	mov	eax, DWORD PTR max_num[rip]
	cmp	edx, eax
	je	.L60
	mov	edx, DWORD PTR num2[rip]
	mov	eax, DWORD PTR max_num[rip]
	cmp	edx, eax
	je	.L60
	mov	edx, DWORD PTR num3[rip]
	mov	eax, DWORD PTR max_num[rip]
	cmp	edx, eax
	je	.L60
	mov	edx, DWORD PTR num4[rip]
	mov	eax, DWORD PTR max_num[rip]
	cmp	edx, eax
	je	.L60
	mov	edx, DWORD PTR num5[rip]
	mov	eax, DWORD PTR max_num[rip]
	cmp	edx, eax
	je	.L60
	mov	edx, DWORD PTR num6[rip]
	mov	eax, DWORD PTR max_num[rip]
	cmp	edx, eax
	je	.L60
	mov	edx, DWORD PTR num7[rip]
	mov	eax, DWORD PTR max_num[rip]
	cmp	edx, eax
	je	.L60
	mov	edx, DWORD PTR num8[rip]
	mov	eax, DWORD PTR max_num[rip]
	cmp	edx, eax
	je	.L60
	mov	edx, DWORD PTR num9[rip]
	mov	eax, DWORD PTR max_num[rip]
	cmp	edx, eax
	je	.L60
	mov	edx, DWORD PTR num10[rip]
	mov	eax, DWORD PTR max_num[rip]
	cmp	edx, eax
	jne	.L4
.L60:
	mov	eax, DWORD PTR num0[rip]
	test	eax, eax
	jne	.L61
	mov	eax, DWORD PTR num1[rip]
	test	eax, eax
	jne	.L61
	mov	eax, DWORD PTR num2[rip]
	test	eax, eax
	jne	.L61
	mov	eax, DWORD PTR num3[rip]
	test	eax, eax
	jne	.L61
	mov	eax, DWORD PTR num4[rip]
	test	eax, eax
	jne	.L61
	mov	eax, DWORD PTR num5[rip]
	test	eax, eax
	jne	.L61
	mov	eax, DWORD PTR num6[rip]
	test	eax, eax
	jne	.L61
	mov	eax, DWORD PTR num7[rip]
	test	eax, eax
	jne	.L61
	mov	eax, DWORD PTR num8[rip]
	test	eax, eax
	jne	.L61
	mov	eax, DWORD PTR num9[rip]
	test	eax, eax
	jne	.L61
	mov	eax, DWORD PTR num10[rip]
	test	eax, eax
	jne	.L61
	mov	eax, 1
	jmp	.L62
.L61:
	mov	eax, 0
.L62:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	mov	eax, DWORD PTR min_num[rip]
	test	eax, eax
	sete	al
	xor	eax, edx
	test	al, al
	je	.L4
	mov	eax, DWORD PTR num0[rip]
	test	eax, eax
	jle	.L63
	mov	edx, DWORD PTR min_num[rip]
	mov	eax, DWORD PTR num0[rip]
	cmp	edx, eax
	jg	.L4
.L63:
	mov	eax, DWORD PTR num1[rip]
	test	eax, eax
	jle	.L64
	mov	edx, DWORD PTR min_num[rip]
	mov	eax, DWORD PTR num1[rip]
	cmp	edx, eax
	jg	.L4
.L64:
	mov	eax, DWORD PTR num2[rip]
	test	eax, eax
	jle	.L65
	mov	edx, DWORD PTR min_num[rip]
	mov	eax, DWORD PTR num2[rip]
	cmp	edx, eax
	jg	.L4
.L65:
	mov	eax, DWORD PTR num3[rip]
	test	eax, eax
	jle	.L66
	mov	edx, DWORD PTR min_num[rip]
	mov	eax, DWORD PTR num3[rip]
	cmp	edx, eax
	jg	.L4
.L66:
	mov	eax, DWORD PTR num4[rip]
	test	eax, eax
	jle	.L67
	mov	edx, DWORD PTR min_num[rip]
	mov	eax, DWORD PTR num4[rip]
	cmp	edx, eax
	jg	.L4
.L67:
	mov	eax, DWORD PTR num5[rip]
	test	eax, eax
	jle	.L68
	mov	edx, DWORD PTR min_num[rip]
	mov	eax, DWORD PTR num5[rip]
	cmp	edx, eax
	jg	.L4
.L68:
	mov	eax, DWORD PTR num6[rip]
	test	eax, eax
	jle	.L69
	mov	edx, DWORD PTR min_num[rip]
	mov	eax, DWORD PTR num6[rip]
	cmp	edx, eax
	jg	.L4
.L69:
	mov	eax, DWORD PTR num7[rip]
	test	eax, eax
	jle	.L70
	mov	edx, DWORD PTR min_num[rip]
	mov	eax, DWORD PTR num7[rip]
	cmp	edx, eax
	jg	.L4
.L70:
	mov	eax, DWORD PTR num8[rip]
	test	eax, eax
	jle	.L71
	mov	edx, DWORD PTR min_num[rip]
	mov	eax, DWORD PTR num8[rip]
	cmp	edx, eax
	jg	.L4
.L71:
	mov	eax, DWORD PTR num9[rip]
	test	eax, eax
	jle	.L72
	mov	edx, DWORD PTR min_num[rip]
	mov	eax, DWORD PTR num9[rip]
	cmp	edx, eax
	jg	.L4
.L72:
	mov	eax, DWORD PTR num10[rip]
	test	eax, eax
	jle	.L73
	mov	edx, DWORD PTR min_num[rip]
	mov	eax, DWORD PTR num10[rip]
	cmp	edx, eax
	jg	.L4
.L73:
	mov	edx, DWORD PTR num9[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L74
	mov	edx, DWORD PTR num8[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L74
	mov	edx, DWORD PTR num7[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L74
	mov	edx, DWORD PTR num6[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L74
	mov	edx, DWORD PTR num5[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L74
	mov	edx, DWORD PTR num4[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L74
	mov	edx, DWORD PTR num3[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L74
	mov	edx, DWORD PTR num2[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L74
	mov	edx, DWORD PTR num0[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L74
	mov	edx, DWORD PTR num1[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L74
	mov	edx, DWORD PTR num10[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	jne	.L4
.L74:
	mov	eax, 1
	jmp	.L75
.L4:
	mov	eax, 0
.L75:
	mov	DWORD PTR -4[rbp], eax
	jmp	.L76
.L334:
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p10_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p9_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p9_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p6_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p6_l0[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_num6[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p3_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p8_l1[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_num5[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p2_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p8_l0[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_num4[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_num3[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p0_l1[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_num2[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_run2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p10_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p0_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p7_l1[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_num1[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_run1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p7_l0[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_num0[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_run0[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_max_num[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_min_num[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_num7[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p3_l1[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_num8[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_num9[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_num10[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_run3[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p1_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p2_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p1_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p4_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p4_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p5_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p5_l1[rip], al
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	jne	.L77
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	je	.L78
.L77:
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	je	.L79
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	je	.L78
.L79:
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	je	.L80
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	je	.L78
.L80:
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	je	.L81
.L78:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	je	.L82
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L82
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L82
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L83
.L82:
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L81
	mov	edx, DWORD PTR num10[rip]
	mov	eax, DWORD PTR _x_num10[rip]
	cmp	edx, eax
	jne	.L81
.L83:
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	je	.L84
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	jne	.L84
	mov	eax, DWORD PTR _x_num10[rip]
	mov	edx, DWORD PTR max_num[rip]
	sub	eax, edx
	cmp	eax, 1
	je	.L85
.L84:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	je	.L85
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L85
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L85
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L85
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	jne	.L85
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	je	.L81
.L85:
	mov	edx, DWORD PTR num10[rip]
	mov	eax, DWORD PTR _x_num10[rip]
	cmp	edx, eax
	jne	.L86
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	je	.L87
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	je	.L88
.L87:
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	je	.L86
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	je	.L88
.L86:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	je	.L88
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L88
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L88
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L88
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	je	.L88
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	je	.L81
.L88:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	je	.L89
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L89
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L89
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L89
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	je	.L89
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	jne	.L89
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	je	.L90
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	jne	.L90
	mov	eax, 1
	jmp	.L91
.L90:
	mov	eax, 0
.L91:
	and	eax, 1
	xor	eax, 1
	mov	ecx, eax
	mov	edx, DWORD PTR num8[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L92
	mov	edx, DWORD PTR num7[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L92
	mov	edx, DWORD PTR num6[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L92
	mov	edx, DWORD PTR num5[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L92
	mov	edx, DWORD PTR num4[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L92
	mov	edx, DWORD PTR num3[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L92
	mov	edx, DWORD PTR num2[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L92
	mov	edx, DWORD PTR num1[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L92
	mov	edx, DWORD PTR num0[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L92
	mov	edx, DWORD PTR num10[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	jg	.L92
	mov	edx, DWORD PTR num9[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L92
	mov	eax, 1
	jmp	.L93
.L92:
	mov	eax, 0
.L93:
	and	eax, 1
	xor	eax, ecx
	test	al, al
	je	.L81
.L89:
	mov	edx, DWORD PTR num10[rip]
	mov	eax, DWORD PTR _x_num10[rip]
	cmp	edx, eax
	jne	.L94
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	je	.L95
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	je	.L96
.L95:
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	je	.L94
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	jne	.L96
.L94:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	je	.L96
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L96
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L96
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L96
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	je	.L96
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	je	.L81
.L96:
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	jne	.L97
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	jne	.L97
	mov	edx, DWORD PTR num10[rip]
	mov	eax, DWORD PTR _x_num10[rip]
	cmp	edx, eax
	je	.L98
.L97:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	je	.L98
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L98
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L98
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L98
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	je	.L98
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	jne	.L81
.L98:
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	jne	.L99
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	je	.L100
.L99:
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	je	.L101
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	je	.L100
.L101:
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	je	.L102
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	je	.L100
.L102:
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	je	.L81
.L100:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	je	.L103
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L103
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L103
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L104
.L103:
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L81
	mov	edx, DWORD PTR num9[rip]
	mov	eax, DWORD PTR _x_num9[rip]
	cmp	edx, eax
	jne	.L81
.L104:
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	je	.L105
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	jne	.L105
	mov	eax, DWORD PTR _x_num9[rip]
	mov	edx, DWORD PTR max_num[rip]
	sub	eax, edx
	cmp	eax, 1
	je	.L106
.L105:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	je	.L106
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L106
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L106
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L106
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	jne	.L106
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	je	.L81
.L106:
	mov	edx, DWORD PTR num9[rip]
	mov	eax, DWORD PTR _x_num9[rip]
	cmp	edx, eax
	jne	.L107
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	je	.L108
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	je	.L109
.L108:
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	je	.L107
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	je	.L109
.L107:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	je	.L109
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L109
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L109
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L109
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	je	.L109
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	je	.L81
.L109:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	je	.L110
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L110
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L110
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L110
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	je	.L110
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	jne	.L110
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	je	.L111
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	jne	.L111
	mov	eax, 1
	jmp	.L112
.L111:
	mov	eax, 0
.L112:
	and	eax, 1
	xor	eax, 1
	mov	ecx, eax
	mov	edx, DWORD PTR num7[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L113
	mov	edx, DWORD PTR num6[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L113
	mov	edx, DWORD PTR num5[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L113
	mov	edx, DWORD PTR num4[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L113
	mov	edx, DWORD PTR num3[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L113
	mov	edx, DWORD PTR num2[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L113
	mov	edx, DWORD PTR num1[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L113
	mov	edx, DWORD PTR num0[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L113
	mov	edx, DWORD PTR num9[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	jg	.L113
	mov	edx, DWORD PTR num8[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L113
	mov	eax, 1
	jmp	.L114
.L113:
	mov	eax, 0
.L114:
	and	eax, 1
	xor	eax, ecx
	test	al, al
	je	.L81
.L110:
	mov	edx, DWORD PTR num9[rip]
	mov	eax, DWORD PTR _x_num9[rip]
	cmp	edx, eax
	jne	.L115
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	je	.L116
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	je	.L117
.L116:
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	je	.L115
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	jne	.L117
.L115:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	je	.L117
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L117
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L117
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L117
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	je	.L117
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	je	.L81
.L117:
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	jne	.L118
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	jne	.L118
	mov	edx, DWORD PTR num9[rip]
	mov	eax, DWORD PTR _x_num9[rip]
	cmp	edx, eax
	je	.L119
.L118:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	je	.L119
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L119
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L119
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L119
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	je	.L119
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	jne	.L81
.L119:
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	jne	.L120
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	je	.L121
.L120:
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	je	.L122
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	je	.L121
.L122:
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	je	.L123
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	je	.L121
.L123:
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	je	.L81
.L121:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	je	.L124
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L124
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L124
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L125
.L124:
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L81
	mov	edx, DWORD PTR num8[rip]
	mov	eax, DWORD PTR _x_num8[rip]
	cmp	edx, eax
	jne	.L81
.L125:
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	je	.L126
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	jne	.L126
	mov	eax, DWORD PTR _x_num8[rip]
	mov	edx, DWORD PTR max_num[rip]
	sub	eax, edx
	cmp	eax, 1
	je	.L127
.L126:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	je	.L127
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L127
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L127
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L127
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	jne	.L127
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	je	.L81
.L127:
	mov	edx, DWORD PTR num8[rip]
	mov	eax, DWORD PTR _x_num8[rip]
	cmp	edx, eax
	jne	.L128
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	je	.L129
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	je	.L130
.L129:
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	je	.L128
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	je	.L130
.L128:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	je	.L130
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L130
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L130
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L130
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	je	.L130
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	je	.L81
.L130:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	je	.L131
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L131
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L131
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L131
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	je	.L131
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	jne	.L131
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	je	.L132
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	jne	.L132
	mov	eax, 1
	jmp	.L133
.L132:
	mov	eax, 0
.L133:
	and	eax, 1
	xor	eax, 1
	mov	ecx, eax
	mov	edx, DWORD PTR num6[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L134
	mov	edx, DWORD PTR num5[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L134
	mov	edx, DWORD PTR num4[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L134
	mov	edx, DWORD PTR num3[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L134
	mov	edx, DWORD PTR num2[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L134
	mov	edx, DWORD PTR num1[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L134
	mov	edx, DWORD PTR num0[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L134
	mov	edx, DWORD PTR num8[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	jg	.L134
	mov	edx, DWORD PTR num7[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L134
	mov	eax, 1
	jmp	.L135
.L134:
	mov	eax, 0
.L135:
	and	eax, 1
	xor	eax, ecx
	test	al, al
	je	.L81
.L131:
	mov	edx, DWORD PTR num8[rip]
	mov	eax, DWORD PTR _x_num8[rip]
	cmp	edx, eax
	jne	.L136
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	je	.L137
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	je	.L138
.L137:
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	je	.L136
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	jne	.L138
.L136:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	je	.L138
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L138
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L138
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L138
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	je	.L138
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	je	.L81
.L138:
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	jne	.L139
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	jne	.L139
	mov	edx, DWORD PTR num8[rip]
	mov	eax, DWORD PTR _x_num8[rip]
	cmp	edx, eax
	je	.L140
.L139:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	je	.L140
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L140
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L140
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L140
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	je	.L140
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	jne	.L81
.L140:
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	jne	.L141
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	je	.L142
.L141:
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	je	.L143
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	je	.L142
.L143:
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	je	.L144
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	je	.L142
.L144:
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	je	.L81
.L142:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L145
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	je	.L145
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L145
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L146
.L145:
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L81
	mov	edx, DWORD PTR num7[rip]
	mov	eax, DWORD PTR _x_num7[rip]
	cmp	edx, eax
	jne	.L81
.L146:
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	je	.L147
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	jne	.L147
	mov	eax, DWORD PTR _x_num7[rip]
	mov	edx, DWORD PTR max_num[rip]
	sub	eax, edx
	cmp	eax, 1
	je	.L148
.L147:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L148
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	je	.L148
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L148
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L148
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	jne	.L148
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	je	.L81
.L148:
	mov	edx, DWORD PTR num7[rip]
	mov	eax, DWORD PTR _x_num7[rip]
	cmp	edx, eax
	jne	.L149
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	je	.L150
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	je	.L151
.L150:
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	je	.L149
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	je	.L151
.L149:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L151
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	je	.L151
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L151
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L151
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	je	.L151
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	je	.L81
.L151:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L152
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	je	.L152
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L152
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L152
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	je	.L152
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	jne	.L152
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	je	.L153
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	jne	.L153
	mov	eax, 1
	jmp	.L154
.L153:
	mov	eax, 0
.L154:
	and	eax, 1
	xor	eax, 1
	mov	ecx, eax
	mov	edx, DWORD PTR num5[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L155
	mov	edx, DWORD PTR num4[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L155
	mov	edx, DWORD PTR num3[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L155
	mov	edx, DWORD PTR num2[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L155
	mov	edx, DWORD PTR num1[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L155
	mov	edx, DWORD PTR num0[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L155
	mov	edx, DWORD PTR num7[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	jg	.L155
	mov	edx, DWORD PTR num6[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L155
	mov	eax, 1
	jmp	.L156
.L155:
	mov	eax, 0
.L156:
	and	eax, 1
	xor	eax, ecx
	test	al, al
	je	.L81
.L152:
	mov	edx, DWORD PTR num7[rip]
	mov	eax, DWORD PTR _x_num7[rip]
	cmp	edx, eax
	jne	.L157
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	je	.L158
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	je	.L159
.L158:
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	je	.L157
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	jne	.L159
.L157:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L159
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	je	.L159
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L159
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L159
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	je	.L159
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	je	.L81
.L159:
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	jne	.L160
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	jne	.L160
	mov	edx, DWORD PTR num7[rip]
	mov	eax, DWORD PTR _x_num7[rip]
	cmp	edx, eax
	je	.L161
.L160:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L161
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	je	.L161
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L161
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L161
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	je	.L161
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	jne	.L81
.L161:
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	jne	.L162
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	je	.L163
.L162:
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	je	.L164
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	je	.L163
.L164:
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	je	.L165
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	je	.L163
.L165:
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	je	.L81
.L163:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L166
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	je	.L166
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L166
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L167
.L166:
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L81
	mov	edx, DWORD PTR num6[rip]
	mov	eax, DWORD PTR _x_num6[rip]
	cmp	edx, eax
	jne	.L81
.L167:
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	je	.L168
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	jne	.L168
	mov	eax, DWORD PTR _x_num6[rip]
	mov	edx, DWORD PTR max_num[rip]
	sub	eax, edx
	cmp	eax, 1
	je	.L169
.L168:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L169
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	je	.L169
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L169
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L169
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	jne	.L169
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	je	.L81
.L169:
	mov	edx, DWORD PTR num6[rip]
	mov	eax, DWORD PTR _x_num6[rip]
	cmp	edx, eax
	jne	.L170
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	je	.L171
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	je	.L172
.L171:
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	je	.L170
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	je	.L172
.L170:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L172
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	je	.L172
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L172
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L172
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	je	.L172
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	je	.L81
.L172:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L173
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	je	.L173
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L173
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L173
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	je	.L173
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	jne	.L173
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	je	.L174
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	jne	.L174
	mov	eax, 1
	jmp	.L175
.L174:
	mov	eax, 0
.L175:
	and	eax, 1
	xor	eax, 1
	mov	ecx, eax
	mov	edx, DWORD PTR num4[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L176
	mov	edx, DWORD PTR num3[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L176
	mov	edx, DWORD PTR num2[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L176
	mov	edx, DWORD PTR num1[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L176
	mov	edx, DWORD PTR num0[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L176
	mov	edx, DWORD PTR num6[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	jg	.L176
	mov	edx, DWORD PTR num5[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L176
	mov	eax, 1
	jmp	.L177
.L176:
	mov	eax, 0
.L177:
	and	eax, 1
	xor	eax, ecx
	test	al, al
	je	.L81
.L173:
	mov	edx, DWORD PTR num6[rip]
	mov	eax, DWORD PTR _x_num6[rip]
	cmp	edx, eax
	jne	.L178
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	je	.L179
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	je	.L180
.L179:
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	je	.L178
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	jne	.L180
.L178:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L180
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	je	.L180
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L180
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L180
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	je	.L180
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	je	.L81
.L180:
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	jne	.L181
	mov	edx, DWORD PTR num6[rip]
	mov	eax, DWORD PTR _x_num6[rip]
	cmp	edx, eax
	je	.L182
.L181:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L182
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	je	.L182
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L182
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L182
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	je	.L182
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	jne	.L81
.L182:
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	jne	.L183
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	je	.L184
.L183:
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	je	.L185
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	je	.L184
.L185:
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	je	.L186
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	je	.L184
.L186:
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	je	.L81
.L184:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L187
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	je	.L187
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L187
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L188
.L187:
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L81
	mov	edx, DWORD PTR num5[rip]
	mov	eax, DWORD PTR _x_num5[rip]
	cmp	edx, eax
	jne	.L81
.L188:
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	je	.L189
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	jne	.L189
	mov	eax, DWORD PTR _x_num5[rip]
	mov	edx, DWORD PTR max_num[rip]
	sub	eax, edx
	cmp	eax, 1
	je	.L190
.L189:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L190
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	je	.L190
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L190
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L190
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	jne	.L190
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	je	.L81
.L190:
	mov	edx, DWORD PTR num5[rip]
	mov	eax, DWORD PTR _x_num5[rip]
	cmp	edx, eax
	jne	.L191
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	je	.L192
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	je	.L193
.L192:
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	je	.L191
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	je	.L193
.L191:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	je	.L81
.L193:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L194
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	je	.L194
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L194
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L194
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	je	.L194
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	jne	.L194
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	je	.L195
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	jne	.L195
	mov	eax, 1
	jmp	.L196
.L195:
	mov	eax, 0
.L196:
	and	eax, 1
	xor	eax, 1
	mov	ecx, eax
	mov	edx, DWORD PTR num3[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L197
	mov	edx, DWORD PTR num2[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L197
	mov	edx, DWORD PTR num1[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L197
	mov	edx, DWORD PTR num0[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L197
	mov	edx, DWORD PTR num5[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	jg	.L197
	mov	edx, DWORD PTR num4[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L197
	mov	eax, 1
	jmp	.L198
.L197:
	mov	eax, 0
.L198:
	and	eax, 1
	xor	eax, ecx
	test	al, al
	je	.L81
.L194:
	mov	edx, DWORD PTR num5[rip]
	mov	eax, DWORD PTR _x_num5[rip]
	cmp	edx, eax
	jne	.L199
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	je	.L200
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	je	.L201
.L200:
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	je	.L199
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	jne	.L201
.L199:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L201
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	je	.L201
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L201
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L201
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	je	.L201
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	je	.L81
.L201:
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	jne	.L202
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	jne	.L202
	mov	edx, DWORD PTR num5[rip]
	mov	eax, DWORD PTR _x_num5[rip]
	cmp	edx, eax
	je	.L203
.L202:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L203
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	je	.L203
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L203
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L203
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	je	.L203
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	jne	.L81
.L203:
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	jne	.L204
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	je	.L205
.L204:
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	je	.L206
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	je	.L205
.L206:
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	je	.L207
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	je	.L205
.L207:
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	je	.L81
.L205:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L208
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	je	.L208
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L208
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L209
.L208:
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L81
	mov	edx, DWORD PTR num4[rip]
	mov	eax, DWORD PTR _x_num4[rip]
	cmp	edx, eax
	jne	.L81
.L209:
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	je	.L210
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	jne	.L210
	mov	eax, DWORD PTR _x_num4[rip]
	mov	edx, DWORD PTR max_num[rip]
	sub	eax, edx
	cmp	eax, 1
	je	.L211
.L210:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L211
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	je	.L211
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L211
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L211
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	jne	.L211
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	je	.L81
.L211:
	mov	edx, DWORD PTR num4[rip]
	mov	eax, DWORD PTR _x_num4[rip]
	cmp	edx, eax
	jne	.L212
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	je	.L213
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	je	.L214
.L213:
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	je	.L212
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	je	.L214
.L212:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L214
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	je	.L214
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L214
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L214
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	je	.L214
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	je	.L81
.L214:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L215
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	je	.L215
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L215
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L215
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	je	.L215
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	jne	.L215
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	je	.L216
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	jne	.L216
	mov	eax, 1
	jmp	.L217
.L216:
	mov	eax, 0
.L217:
	and	eax, 1
	xor	eax, 1
	mov	ecx, eax
	mov	edx, DWORD PTR num2[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L218
	mov	edx, DWORD PTR num1[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L218
	mov	edx, DWORD PTR num0[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L218
	mov	edx, DWORD PTR num4[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	jg	.L218
	mov	edx, DWORD PTR num3[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L218
	mov	eax, 1
	jmp	.L219
.L218:
	mov	eax, 0
.L219:
	and	eax, 1
	xor	eax, ecx
	test	al, al
	je	.L81
.L215:
	mov	edx, DWORD PTR num4[rip]
	mov	eax, DWORD PTR _x_num4[rip]
	cmp	edx, eax
	jne	.L220
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	je	.L221
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	je	.L222
.L221:
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	je	.L220
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	jne	.L222
.L220:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L222
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	je	.L222
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L222
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L222
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	je	.L222
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	je	.L81
.L222:
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	jne	.L223
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	jne	.L223
	mov	edx, DWORD PTR num4[rip]
	mov	eax, DWORD PTR _x_num4[rip]
	cmp	edx, eax
	je	.L224
.L223:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L224
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	je	.L224
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L224
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L224
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	je	.L224
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	jne	.L81
.L224:
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	jne	.L225
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	je	.L226
.L225:
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	je	.L227
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	je	.L226
.L227:
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	je	.L228
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	je	.L226
.L228:
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	je	.L81
.L226:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L229
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L229
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L229
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L230
.L229:
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L81
	mov	edx, DWORD PTR num3[rip]
	mov	eax, DWORD PTR _x_num3[rip]
	cmp	edx, eax
	jne	.L81
.L230:
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	je	.L231
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	jne	.L231
	mov	eax, DWORD PTR _x_num3[rip]
	mov	edx, DWORD PTR max_num[rip]
	sub	eax, edx
	cmp	eax, 1
	je	.L232
.L231:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L232
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L232
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L232
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L232
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	jne	.L232
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	je	.L81
.L232:
	mov	edx, DWORD PTR num3[rip]
	mov	eax, DWORD PTR _x_num3[rip]
	cmp	edx, eax
	jne	.L233
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	je	.L234
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	je	.L235
.L234:
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	je	.L233
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	je	.L235
.L233:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L235
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L235
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L235
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L235
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	je	.L235
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	je	.L81
.L235:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L236
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L236
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L236
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L236
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	je	.L236
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	jne	.L236
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	je	.L237
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	jne	.L237
	mov	eax, 1
	jmp	.L238
.L237:
	mov	eax, 0
.L238:
	and	eax, 1
	xor	eax, 1
	mov	ecx, eax
	mov	edx, DWORD PTR num1[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L239
	mov	edx, DWORD PTR num0[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L239
	mov	edx, DWORD PTR num3[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	jg	.L239
	mov	edx, DWORD PTR num2[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L239
	mov	eax, 1
	jmp	.L240
.L239:
	mov	eax, 0
.L240:
	and	eax, 1
	xor	eax, ecx
	test	al, al
	je	.L81
.L236:
	mov	edx, DWORD PTR num3[rip]
	mov	eax, DWORD PTR _x_num3[rip]
	cmp	edx, eax
	jne	.L241
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	je	.L242
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	je	.L243
.L242:
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	jne	.L243
.L241:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L243
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L243
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L243
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L243
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	je	.L243
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	je	.L81
.L243:
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	jne	.L244
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	jne	.L244
	mov	edx, DWORD PTR num3[rip]
	mov	eax, DWORD PTR _x_num3[rip]
	cmp	edx, eax
	je	.L245
.L244:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	jne	.L81
.L245:
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L247
.L246:
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L248
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L247
.L248:
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L249
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L247
.L249:
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L81
.L247:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L250
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L250
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L250
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L251
.L250:
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L81
	mov	edx, DWORD PTR num2[rip]
	mov	eax, DWORD PTR _x_num2[rip]
	cmp	edx, eax
	jne	.L81
.L251:
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L252
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	jne	.L252
	mov	eax, DWORD PTR _x_num2[rip]
	mov	edx, DWORD PTR max_num[rip]
	sub	eax, edx
	cmp	eax, 1
	je	.L253
.L252:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L81
.L253:
	mov	edx, DWORD PTR num2[rip]
	mov	eax, DWORD PTR _x_num2[rip]
	cmp	edx, eax
	jne	.L254
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L255
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L256
.L255:
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L254
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L256
.L254:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L256
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L256
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L256
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L256
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L256
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L81
.L256:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L257
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L257
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L257
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L257
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L257
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	jne	.L257
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L258
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	jne	.L258
	mov	eax, 1
	jmp	.L259
.L258:
	mov	eax, 0
.L259:
	and	eax, 1
	xor	eax, 1
	mov	ecx, eax
	mov	edx, DWORD PTR num0[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L260
	mov	edx, DWORD PTR num2[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	jg	.L260
	mov	edx, DWORD PTR num1[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L260
	mov	eax, 1
	jmp	.L261
.L260:
	mov	eax, 0
.L261:
	and	eax, 1
	xor	eax, ecx
	test	al, al
	je	.L81
.L257:
	mov	edx, DWORD PTR num2[rip]
	mov	eax, DWORD PTR _x_num2[rip]
	cmp	edx, eax
	jne	.L262
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L263
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L264
.L263:
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L262
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	jne	.L264
.L262:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L264
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L264
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L264
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L264
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L264
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L81
.L264:
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	jne	.L265
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	jne	.L265
	mov	edx, DWORD PTR num2[rip]
	mov	eax, DWORD PTR _x_num2[rip]
	cmp	edx, eax
	je	.L266
.L265:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L266
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L266
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L266
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L266
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L266
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	jne	.L81
.L266:
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L267
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L268
.L267:
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L269
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L268
.L269:
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L270
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L268
.L270:
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L81
.L268:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L271
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L271
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L271
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L272
.L271:
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L81
	mov	edx, DWORD PTR num1[rip]
	mov	eax, DWORD PTR _x_num1[rip]
	cmp	edx, eax
	jne	.L81
.L272:
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L273
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	jne	.L273
	mov	eax, DWORD PTR _x_num1[rip]
	mov	edx, DWORD PTR max_num[rip]
	sub	eax, edx
	cmp	eax, 1
	je	.L274
.L273:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L274
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L274
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L274
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L274
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	jne	.L274
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L81
.L274:
	mov	edx, DWORD PTR num1[rip]
	mov	eax, DWORD PTR _x_num1[rip]
	cmp	edx, eax
	jne	.L275
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L276
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L277
.L276:
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L275
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L277
.L275:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L277
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L277
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L277
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L277
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L277
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L81
.L277:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L278
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L278
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L278
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L278
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L278
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	jne	.L278
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L279
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L279
	mov	eax, 1
	jmp	.L280
.L279:
	mov	eax, 0
.L280:
	and	eax, 1
	xor	eax, 1
	mov	ecx, eax
	mov	edx, DWORD PTR num1[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	jg	.L281
	mov	edx, DWORD PTR num0[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	je	.L281
	mov	eax, 1
	jmp	.L282
.L281:
	mov	eax, 0
.L282:
	and	eax, 1
	xor	eax, ecx
	test	al, al
	je	.L81
.L278:
	mov	edx, DWORD PTR num1[rip]
	mov	eax, DWORD PTR _x_num1[rip]
	cmp	edx, eax
	jne	.L283
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L284
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L285
.L284:
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L283
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	jne	.L285
.L283:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L285
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L285
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L285
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L285
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L285
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L81
.L285:
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L286
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	jne	.L286
	mov	edx, DWORD PTR num1[rip]
	mov	eax, DWORD PTR _x_num1[rip]
	cmp	edx, eax
	je	.L287
.L286:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L287
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L287
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	je	.L287
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L287
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L287
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	jne	.L81
.L287:
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L288
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L289
.L288:
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L290
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L289
.L290:
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L291
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L289
.L291:
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L81
.L289:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L292
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L292
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L292
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	je	.L293
.L292:
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L81
	mov	edx, DWORD PTR num0[rip]
	mov	eax, DWORD PTR _x_num0[rip]
	cmp	edx, eax
	jne	.L81
.L293:
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L294
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	jne	.L294
	mov	eax, DWORD PTR _x_num0[rip]
	mov	edx, DWORD PTR max_num[rip]
	sub	eax, edx
	cmp	eax, 1
	je	.L295
.L294:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L295
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L295
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L295
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L295
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	jne	.L295
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L81
.L295:
	mov	edx, DWORD PTR num0[rip]
	mov	eax, DWORD PTR _x_num0[rip]
	cmp	edx, eax
	jne	.L296
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L297
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L298
.L297:
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L296
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L298
.L296:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L298
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L298
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L298
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L298
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L298
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L81
.L298:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L299
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L299
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L299
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L299
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L299
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	jne	.L299
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L300
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L300
	mov	eax, 1
	jmp	.L301
.L300:
	mov	eax, 0
.L301:
	and	eax, 1
	xor	eax, 1
	mov	ecx, eax
	mov	edx, DWORD PTR num0[rip]
	mov	eax, DWORD PTR min_num[rip]
	cmp	edx, eax
	setle	al
	xor	eax, ecx
	test	al, al
	je	.L81
.L299:
	mov	edx, DWORD PTR num0[rip]
	mov	eax, DWORD PTR _x_num0[rip]
	cmp	edx, eax
	jne	.L302
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L303
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L304
.L303:
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L302
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	jne	.L304
.L302:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L304
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L304
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L304
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L304
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L304
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L81
.L304:
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L305
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	jne	.L305
	mov	edx, DWORD PTR num0[rip]
	mov	eax, DWORD PTR _x_num0[rip]
	cmp	edx, eax
	je	.L306
.L305:
	movzx	eax, BYTE PTR run3[rip]
	test	al, al
	jne	.L306
	movzx	eax, BYTE PTR run2[rip]
	test	al, al
	jne	.L306
	movzx	eax, BYTE PTR run0[rip]
	test	al, al
	jne	.L306
	movzx	eax, BYTE PTR run1[rip]
	test	al, al
	jne	.L306
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L306
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	jne	.L81
.L306:
	movzx	eax, BYTE PTR _x_run3[rip]
	test	al, al
	je	.L307
	movzx	eax, BYTE PTR _x_run2[rip]
	test	al, al
	jne	.L307
	movzx	eax, BYTE PTR _x_run1[rip]
	test	al, al
	je	.L307
	movzx	eax, BYTE PTR _x_run0[rip]
	test	al, al
	je	.L308
.L307:
	movzx	eax, BYTE PTR _x_run3[rip]
	test	al, al
	je	.L309
	movzx	eax, BYTE PTR _x_run2[rip]
	test	al, al
	jne	.L309
	movzx	eax, BYTE PTR _x_run0[rip]
	test	al, al
	je	.L309
	movzx	eax, BYTE PTR _x_run1[rip]
	test	al, al
	je	.L308
.L309:
	movzx	eax, BYTE PTR _x_run3[rip]
	test	al, al
	je	.L310
	movzx	eax, BYTE PTR _x_run2[rip]
	test	al, al
	jne	.L310
	movzx	eax, BYTE PTR _x_run0[rip]
	test	al, al
	jne	.L310
	movzx	eax, BYTE PTR _x_run1[rip]
	test	al, al
	je	.L308
.L310:
	movzx	eax, BYTE PTR _x_run3[rip]
	test	al, al
	jne	.L311
	movzx	eax, BYTE PTR _x_run2[rip]
	test	al, al
	je	.L311
	movzx	eax, BYTE PTR _x_run0[rip]
	test	al, al
	je	.L311
	movzx	eax, BYTE PTR _x_run1[rip]
	test	al, al
	jne	.L308
.L311:
	movzx	eax, BYTE PTR _x_run3[rip]
	test	al, al
	jne	.L312
	movzx	eax, BYTE PTR _x_run2[rip]
	test	al, al
	je	.L312
	movzx	eax, BYTE PTR _x_run1[rip]
	test	al, al
	je	.L312
	movzx	eax, BYTE PTR _x_run0[rip]
	test	al, al
	je	.L308
.L312:
	movzx	eax, BYTE PTR _x_run3[rip]
	test	al, al
	jne	.L313
	movzx	eax, BYTE PTR _x_run2[rip]
	test	al, al
	je	.L313
	movzx	eax, BYTE PTR _x_run0[rip]
	test	al, al
	je	.L313
	movzx	eax, BYTE PTR _x_run1[rip]
	test	al, al
	je	.L308
.L313:
	movzx	eax, BYTE PTR _x_run3[rip]
	test	al, al
	jne	.L314
	movzx	eax, BYTE PTR _x_run2[rip]
	test	al, al
	je	.L314
	movzx	eax, BYTE PTR _x_run0[rip]
	test	al, al
	jne	.L314
	movzx	eax, BYTE PTR _x_run1[rip]
	test	al, al
	je	.L308
.L314:
	movzx	eax, BYTE PTR _x_run3[rip]
	test	al, al
	jne	.L315
	movzx	eax, BYTE PTR _x_run2[rip]
	test	al, al
	jne	.L315
	movzx	eax, BYTE PTR _x_run0[rip]
	test	al, al
	je	.L315
	movzx	eax, BYTE PTR _x_run1[rip]
	test	al, al
	jne	.L308
.L315:
	movzx	eax, BYTE PTR _x_run3[rip]
	test	al, al
	jne	.L316
	movzx	eax, BYTE PTR _x_run2[rip]
	test	al, al
	jne	.L316
	movzx	eax, BYTE PTR _x_run1[rip]
	test	al, al
	je	.L316
	movzx	eax, BYTE PTR _x_run0[rip]
	test	al, al
	je	.L308
.L316:
	movzx	eax, BYTE PTR _x_run3[rip]
	test	al, al
	jne	.L317
	movzx	eax, BYTE PTR _x_run2[rip]
	test	al, al
	jne	.L317
	movzx	eax, BYTE PTR _x_run0[rip]
	test	al, al
	jne	.L317
	movzx	eax, BYTE PTR _x_run1[rip]
	test	al, al
	je	.L308
.L317:
	movzx	eax, BYTE PTR _x_run3[rip]
	test	al, al
	jne	.L81
	movzx	eax, BYTE PTR _x_run2[rip]
	test	al, al
	jne	.L81
	movzx	eax, BYTE PTR _x_run0[rip]
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR _x_run1[rip]
	test	al, al
	jne	.L81
.L308:
	mov	edx, DWORD PTR _x_num0[rip]
	mov	eax, DWORD PTR _x_max_num[rip]
	cmp	edx, eax
	jg	.L81
	mov	edx, DWORD PTR _x_num1[rip]
	mov	eax, DWORD PTR _x_max_num[rip]
	cmp	edx, eax
	jg	.L81
	mov	edx, DWORD PTR _x_num2[rip]
	mov	eax, DWORD PTR _x_max_num[rip]
	cmp	edx, eax
	jg	.L81
	mov	edx, DWORD PTR _x_num3[rip]
	mov	eax, DWORD PTR _x_max_num[rip]
	cmp	edx, eax
	jg	.L81
	mov	edx, DWORD PTR _x_num4[rip]
	mov	eax, DWORD PTR _x_max_num[rip]
	cmp	edx, eax
	jg	.L81
	mov	edx, DWORD PTR _x_num5[rip]
	mov	eax, DWORD PTR _x_max_num[rip]
	cmp	edx, eax
	jg	.L81
	mov	edx, DWORD PTR _x_num6[rip]
	mov	eax, DWORD PTR _x_max_num[rip]
	cmp	edx, eax
	jg	.L81
	mov	edx, DWORD PTR _x_num7[rip]
	mov	eax, DWORD PTR _x_max_num[rip]
	cmp	edx, eax
	jg	.L81
	mov	edx, DWORD PTR _x_num8[rip]
	mov	eax, DWORD PTR _x_max_num[rip]
	cmp	edx, eax
	jg	.L81
	mov	edx, DWORD PTR _x_num9[rip]
	mov	eax, DWORD PTR _x_max_num[rip]
	cmp	edx, eax
	jg	.L81
	mov	edx, DWORD PTR _x_num10[rip]
	mov	eax, DWORD PTR _x_max_num[rip]
	cmp	edx, eax
	jg	.L81
	mov	edx, DWORD PTR _x_num0[rip]
	mov	eax, DWORD PTR _x_max_num[rip]
	cmp	edx, eax
	je	.L318
	mov	edx, DWORD PTR _x_num1[rip]
	mov	eax, DWORD PTR _x_max_num[rip]
	cmp	edx, eax
	je	.L318
	mov	edx, DWORD PTR _x_num2[rip]
	mov	eax, DWORD PTR _x_max_num[rip]
	cmp	edx, eax
	je	.L318
	mov	edx, DWORD PTR _x_num3[rip]
	mov	eax, DWORD PTR _x_max_num[rip]
	cmp	edx, eax
	je	.L318
	mov	edx, DWORD PTR _x_num4[rip]
	mov	eax, DWORD PTR _x_max_num[rip]
	cmp	edx, eax
	je	.L318
	mov	edx, DWORD PTR _x_num5[rip]
	mov	eax, DWORD PTR _x_max_num[rip]
	cmp	edx, eax
	je	.L318
	mov	edx, DWORD PTR _x_num6[rip]
	mov	eax, DWORD PTR _x_max_num[rip]
	cmp	edx, eax
	je	.L318
	mov	edx, DWORD PTR _x_num7[rip]
	mov	eax, DWORD PTR _x_max_num[rip]
	cmp	edx, eax
	je	.L318
	mov	edx, DWORD PTR _x_num8[rip]
	mov	eax, DWORD PTR _x_max_num[rip]
	cmp	edx, eax
	je	.L318
	mov	edx, DWORD PTR _x_num9[rip]
	mov	eax, DWORD PTR _x_max_num[rip]
	cmp	edx, eax
	je	.L318
	mov	edx, DWORD PTR _x_num10[rip]
	mov	eax, DWORD PTR _x_max_num[rip]
	cmp	edx, eax
	jne	.L81
.L318:
	mov	eax, DWORD PTR _x_num0[rip]
	test	eax, eax
	jne	.L319
	mov	eax, DWORD PTR _x_num1[rip]
	test	eax, eax
	jne	.L319
	mov	eax, DWORD PTR _x_num2[rip]
	test	eax, eax
	jne	.L319
	mov	eax, DWORD PTR _x_num3[rip]
	test	eax, eax
	jne	.L319
	mov	eax, DWORD PTR _x_num4[rip]
	test	eax, eax
	jne	.L319
	mov	eax, DWORD PTR _x_num5[rip]
	test	eax, eax
	jne	.L319
	mov	eax, DWORD PTR _x_num6[rip]
	test	eax, eax
	jne	.L319
	mov	eax, DWORD PTR _x_num7[rip]
	test	eax, eax
	jne	.L319
	mov	eax, DWORD PTR _x_num8[rip]
	test	eax, eax
	jne	.L319
	mov	eax, DWORD PTR _x_num9[rip]
	test	eax, eax
	jne	.L319
	mov	eax, DWORD PTR _x_num10[rip]
	test	eax, eax
	jne	.L319
	mov	eax, 1
	jmp	.L320
.L319:
	mov	eax, 0
.L320:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	mov	eax, DWORD PTR _x_min_num[rip]
	test	eax, eax
	sete	al
	xor	eax, edx
	test	al, al
	je	.L81
	mov	eax, DWORD PTR _x_num0[rip]
	test	eax, eax
	jle	.L321
	mov	edx, DWORD PTR _x_min_num[rip]
	mov	eax, DWORD PTR _x_num0[rip]
	cmp	edx, eax
	jg	.L81
.L321:
	mov	eax, DWORD PTR _x_num1[rip]
	test	eax, eax
	jle	.L322
	mov	edx, DWORD PTR _x_min_num[rip]
	mov	eax, DWORD PTR _x_num1[rip]
	cmp	edx, eax
	jg	.L81
.L322:
	mov	eax, DWORD PTR _x_num2[rip]
	test	eax, eax
	jle	.L323
	mov	edx, DWORD PTR _x_min_num[rip]
	mov	eax, DWORD PTR _x_num2[rip]
	cmp	edx, eax
	jg	.L81
.L323:
	mov	eax, DWORD PTR _x_num3[rip]
	test	eax, eax
	jle	.L324
	mov	edx, DWORD PTR _x_min_num[rip]
	mov	eax, DWORD PTR _x_num3[rip]
	cmp	edx, eax
	jg	.L81
.L324:
	mov	eax, DWORD PTR _x_num4[rip]
	test	eax, eax
	jle	.L325
	mov	edx, DWORD PTR _x_min_num[rip]
	mov	eax, DWORD PTR _x_num4[rip]
	cmp	edx, eax
	jg	.L81
.L325:
	mov	eax, DWORD PTR _x_num5[rip]
	test	eax, eax
	jle	.L326
	mov	edx, DWORD PTR _x_min_num[rip]
	mov	eax, DWORD PTR _x_num5[rip]
	cmp	edx, eax
	jg	.L81
.L326:
	mov	eax, DWORD PTR _x_num6[rip]
	test	eax, eax
	jle	.L327
	mov	edx, DWORD PTR _x_min_num[rip]
	mov	eax, DWORD PTR _x_num6[rip]
	cmp	edx, eax
	jg	.L81
.L327:
	mov	eax, DWORD PTR _x_num7[rip]
	test	eax, eax
	jle	.L328
	mov	edx, DWORD PTR _x_min_num[rip]
	mov	eax, DWORD PTR _x_num7[rip]
	cmp	edx, eax
	jg	.L81
.L328:
	mov	eax, DWORD PTR _x_num8[rip]
	test	eax, eax
	jle	.L329
	mov	edx, DWORD PTR _x_min_num[rip]
	mov	eax, DWORD PTR _x_num8[rip]
	cmp	edx, eax
	jg	.L81
.L329:
	mov	eax, DWORD PTR _x_num9[rip]
	test	eax, eax
	jle	.L330
	mov	edx, DWORD PTR _x_min_num[rip]
	mov	eax, DWORD PTR _x_num9[rip]
	cmp	edx, eax
	jg	.L81
.L330:
	mov	eax, DWORD PTR _x_num10[rip]
	test	eax, eax
	jle	.L331
	mov	edx, DWORD PTR _x_min_num[rip]
	mov	eax, DWORD PTR _x_num10[rip]
	cmp	edx, eax
	jg	.L81
.L331:
	mov	edx, DWORD PTR _x_num0[rip]
	mov	eax, DWORD PTR _x_min_num[rip]
	cmp	edx, eax
	je	.L332
	mov	edx, DWORD PTR _x_num1[rip]
	mov	eax, DWORD PTR _x_min_num[rip]
	cmp	edx, eax
	je	.L332
	mov	edx, DWORD PTR _x_num2[rip]
	mov	eax, DWORD PTR _x_min_num[rip]
	cmp	edx, eax
	je	.L332
	mov	edx, DWORD PTR _x_num3[rip]
	mov	eax, DWORD PTR _x_min_num[rip]
	cmp	edx, eax
	je	.L332
	mov	edx, DWORD PTR _x_num4[rip]
	mov	eax, DWORD PTR _x_min_num[rip]
	cmp	edx, eax
	je	.L332
	mov	edx, DWORD PTR _x_num5[rip]
	mov	eax, DWORD PTR _x_min_num[rip]
	cmp	edx, eax
	je	.L332
	mov	edx, DWORD PTR _x_num6[rip]
	mov	eax, DWORD PTR _x_min_num[rip]
	cmp	edx, eax
	je	.L332
	mov	edx, DWORD PTR _x_num7[rip]
	mov	eax, DWORD PTR _x_min_num[rip]
	cmp	edx, eax
	je	.L332
	mov	edx, DWORD PTR _x_num8[rip]
	mov	eax, DWORD PTR _x_min_num[rip]
	cmp	edx, eax
	je	.L332
	mov	edx, DWORD PTR _x_num9[rip]
	mov	eax, DWORD PTR _x_min_num[rip]
	cmp	edx, eax
	je	.L332
	mov	edx, DWORD PTR _x_num10[rip]
	mov	eax, DWORD PTR _x_min_num[rip]
	cmp	edx, eax
	jne	.L81
.L332:
	mov	eax, 1
	jmp	.L333
.L81:
	mov	eax, 0
.L333:
	mov	DWORD PTR -4[rbp], eax
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	mov	BYTE PTR p10_l0[rip], al
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	mov	BYTE PTR p9_l1[rip], al
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	mov	BYTE PTR p9_l0[rip], al
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	mov	BYTE PTR p6_l1[rip], al
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	mov	BYTE PTR p6_l0[rip], al
	mov	eax, DWORD PTR _x_num6[rip]
	mov	DWORD PTR num6[rip], eax
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	mov	BYTE PTR p3_l0[rip], al
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	mov	BYTE PTR p8_l1[rip], al
	mov	eax, DWORD PTR _x_num5[rip]
	mov	DWORD PTR num5[rip], eax
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	mov	BYTE PTR p2_l1[rip], al
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	mov	BYTE PTR p8_l0[rip], al
	mov	eax, DWORD PTR _x_num4[rip]
	mov	DWORD PTR num4[rip], eax
	mov	eax, DWORD PTR _x_num3[rip]
	mov	DWORD PTR num3[rip], eax
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	mov	BYTE PTR p0_l1[rip], al
	mov	eax, DWORD PTR _x_num2[rip]
	mov	DWORD PTR num2[rip], eax
	movzx	eax, BYTE PTR _x_run2[rip]
	mov	BYTE PTR run2[rip], al
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	mov	BYTE PTR p10_l1[rip], al
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	mov	BYTE PTR p0_l0[rip], al
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	mov	BYTE PTR p7_l1[rip], al
	mov	eax, DWORD PTR _x_num1[rip]
	mov	DWORD PTR num1[rip], eax
	movzx	eax, BYTE PTR _x_run1[rip]
	mov	BYTE PTR run1[rip], al
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	mov	BYTE PTR p7_l0[rip], al
	mov	eax, DWORD PTR _x_num0[rip]
	mov	DWORD PTR num0[rip], eax
	movzx	eax, BYTE PTR _x_run0[rip]
	mov	BYTE PTR run0[rip], al
	mov	eax, DWORD PTR _x_max_num[rip]
	mov	DWORD PTR max_num[rip], eax
	mov	eax, DWORD PTR _x_min_num[rip]
	mov	DWORD PTR min_num[rip], eax
	mov	eax, DWORD PTR _x_num7[rip]
	mov	DWORD PTR num7[rip], eax
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	mov	BYTE PTR p3_l1[rip], al
	mov	eax, DWORD PTR _x_num8[rip]
	mov	DWORD PTR num8[rip], eax
	mov	eax, DWORD PTR _x_num9[rip]
	mov	DWORD PTR num9[rip], eax
	mov	eax, DWORD PTR _x_num10[rip]
	mov	DWORD PTR num10[rip], eax
	movzx	eax, BYTE PTR _x_run3[rip]
	mov	BYTE PTR run3[rip], al
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	mov	BYTE PTR p1_l0[rip], al
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	mov	BYTE PTR p2_l0[rip], al
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	mov	BYTE PTR p1_l1[rip], al
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	mov	BYTE PTR p4_l0[rip], al
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	mov	BYTE PTR p4_l1[rip], al
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	mov	BYTE PTR p5_l0[rip], al
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	mov	BYTE PTR p5_l1[rip], al
.L76:
	cmp	DWORD PTR -4[rbp], 0
	jne	.L334
	mov	eax, 0
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	main, .-main
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"411303.c"
	.text
	.align	2
	.global	__VERIFIER_nondet_bool
	.syntax unified
	.arm
	.fpu softvfp
	.type	__VERIFIER_nondet_bool, %function
__VERIFIER_nondet_bool:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	mov	r0, r3
	pop	{fp, pc}
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.comm	p10_l0,1,1
	.comm	_x_p10_l0,1,1
	.comm	p9_l1,1,1
	.comm	_x_p9_l1,1,1
	.comm	p9_l0,1,1
	.comm	_x_p9_l0,1,1
	.comm	p6_l1,1,1
	.comm	_x_p6_l1,1,1
	.comm	p6_l0,1,1
	.comm	_x_p6_l0,1,1
	.comm	num6,4,4
	.comm	_x_num6,4,4
	.comm	p3_l0,1,1
	.comm	_x_p3_l0,1,1
	.comm	p8_l1,1,1
	.comm	_x_p8_l1,1,1
	.comm	num5,4,4
	.comm	_x_num5,4,4
	.comm	p2_l1,1,1
	.comm	_x_p2_l1,1,1
	.comm	p8_l0,1,1
	.comm	_x_p8_l0,1,1
	.comm	num4,4,4
	.comm	_x_num4,4,4
	.comm	num3,4,4
	.comm	_x_num3,4,4
	.comm	p0_l1,1,1
	.comm	_x_p0_l1,1,1
	.comm	num2,4,4
	.comm	_x_num2,4,4
	.comm	run2,1,1
	.comm	_x_run2,1,1
	.comm	p10_l1,1,1
	.comm	_x_p10_l1,1,1
	.comm	p0_l0,1,1
	.comm	_x_p0_l0,1,1
	.comm	p7_l1,1,1
	.comm	_x_p7_l1,1,1
	.comm	num1,4,4
	.comm	_x_num1,4,4
	.comm	run1,1,1
	.comm	_x_run1,1,1
	.comm	p7_l0,1,1
	.comm	_x_p7_l0,1,1
	.comm	num0,4,4
	.comm	_x_num0,4,4
	.comm	run0,1,1
	.comm	_x_run0,1,1
	.comm	max_num,4,4
	.comm	_x_max_num,4,4
	.comm	min_num,4,4
	.comm	_x_min_num,4,4
	.comm	num7,4,4
	.comm	_x_num7,4,4
	.comm	p3_l1,1,1
	.comm	_x_p3_l1,1,1
	.comm	num8,4,4
	.comm	_x_num8,4,4
	.comm	num9,4,4
	.comm	_x_num9,4,4
	.comm	num10,4,4
	.comm	_x_num10,4,4
	.comm	run3,1,1
	.comm	_x_run3,1,1
	.comm	p1_l0,1,1
	.comm	_x_p1_l0,1,1
	.comm	p2_l0,1,1
	.comm	_x_p2_l0,1,1
	.comm	p1_l1,1,1
	.comm	_x_p1_l1,1,1
	.comm	p4_l0,1,1
	.comm	_x_p4_l0,1,1
	.comm	p4_l1,1,1
	.comm	_x_p4_l1,1,1
	.comm	p5_l0,1,1
	.comm	_x_p5_l0,1,1
	.comm	p5_l1,1,1
	.comm	_x_p5_l1,1,1
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+4
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+8
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+12
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+16
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L336+20
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+24
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+28
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L336+92
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+32
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+36
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L336+96
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L336+100
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+40
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L336+104
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+44
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+240
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+48
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+52
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L336+332
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+288
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+56
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L336+336
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+284
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L336+268
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L336+348
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L336+308
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+60
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L336+344
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L336+340
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L336+252
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+276
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+64
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+68
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+72
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+76
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+80
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+84
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+88
	strb	r2, [r3]
	ldr	r3, .L336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L5
	ldr	r3, .L336+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L6
.L5:
	ldr	r3, .L336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
	ldr	r3, .L336+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L6
.L7:
	ldr	r3, .L336+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L6
.L8:
	ldr	r3, .L336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L336+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L6:
	ldr	r3, .L336+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L9
	ldr	r3, .L336+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L10
.L9:
	ldr	r3, .L336+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L11
	ldr	r3, .L336+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L10
.L11:
	ldr	r3, .L336+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L12
	ldr	r3, .L336+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L10
.L12:
	ldr	r3, .L336+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L336+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L10:
	ldr	r3, .L336+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L13
	ldr	r3, .L336+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L14
.L13:
	ldr	r3, .L336+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L15
	ldr	r3, .L336+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L14
.L15:
	ldr	r3, .L336+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L16
	ldr	r3, .L336+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L14
.L16:
	ldr	r3, .L336+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L336+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L14:
	ldr	r3, .L336+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L17
	ldr	r3, .L336+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L18
.L17:
	ldr	r3, .L336+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L19
	ldr	r3, .L336+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L18
.L19:
	ldr	r3, .L336+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L20
	ldr	r3, .L336+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L18
.L20:
	ldr	r3, .L336+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L336+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L18:
	ldr	r3, .L336+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L21
	ldr	r3, .L336+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L22
.L21:
	ldr	r3, .L336+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L23
	ldr	r3, .L336+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L22
.L23:
	ldr	r3, .L336+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L24
	ldr	r3, .L336+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L22
.L24:
	ldr	r3, .L336+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L336+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L22:
	ldr	r3, .L336+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L25
	ldr	r3, .L336+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L26
.L25:
	ldr	r3, .L336+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L27
	ldr	r3, .L336+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L26
.L27:
	ldr	r3, .L336+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L28
	ldr	r3, .L336+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L26
.L28:
	ldr	r3, .L336+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L336+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L26:
	ldr	r3, .L336+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L29
	ldr	r3, .L336+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L30
.L29:
	ldr	r3, .L336+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
	ldr	r3, .L336+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L30
.L31:
	ldr	r3, .L336+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L32
	ldr	r3, .L336+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L30
.L32:
	ldr	r3, .L336+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L336+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L30:
	ldr	r3, .L336+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L33
	ldr	r3, .L336+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L34
.L33:
	ldr	r3, .L336+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
	ldr	r3, .L336+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L34
.L35:
	ldr	r3, .L336+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L36
	ldr	r3, .L336+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L34
.L36:
	ldr	r3, .L336+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L336+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L34:
	ldr	r3, .L336+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L37
	ldr	r3, .L336+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L38
.L37:
	ldr	r3, .L336+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L39
	ldr	r3, .L336+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L38
.L39:
	ldr	r3, .L336+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L40
	ldr	r3, .L336+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L38
.L40:
	ldr	r3, .L336+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L336+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L38:
	ldr	r3, .L336+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L41
	ldr	r3, .L336+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L42
.L41:
	ldr	r3, .L336+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L43
	ldr	r3, .L336+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L42
.L43:
	ldr	r3, .L336+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L44
	ldr	r3, .L336+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L42
.L44:
	ldr	r3, .L336+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L336+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L42:
	ldr	r3, .L336+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L45
	ldr	r3, .L336+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L46
.L45:
	ldr	r3, .L336+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L47
	ldr	r3, .L336+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L46
.L47:
	ldr	r3, .L336+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L48
	ldr	r3, .L336+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L46
.L48:
	ldr	r3, .L336+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L336+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L46:
	ldr	r3, .L336+336
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+332
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+104
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+100
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+96
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+92
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+20
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+308
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+344
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+340
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+252
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L49
	ldr	r3, .L336+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L49
	ldr	r3, .L336+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L49
	ldr	r3, .L336+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L50
.L49:
	ldr	r3, .L336+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L51
	ldr	r3, .L336+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L51
	ldr	r3, .L336+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L51
	ldr	r3, .L336+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L50
.L51:
	ldr	r3, .L336+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L52
	ldr	r3, .L336+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L52
	ldr	r3, .L336+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L52
	ldr	r3, .L336+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L50
.L52:
	ldr	r3, .L336+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L53
	ldr	r3, .L336+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L53
	ldr	r3, .L336+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L53
	ldr	r3, .L336+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L50
.L53:
	ldr	r3, .L336+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L54
	ldr	r3, .L336+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L54
	ldr	r3, .L336+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L54
	ldr	r3, .L336+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L50
.L54:
	ldr	r3, .L336+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L55
	ldr	r3, .L336+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L55
	ldr	r3, .L336+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L55
	ldr	r3, .L336+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L50
.L55:
	ldr	r3, .L336+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L56
	ldr	r3, .L336+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L56
	ldr	r3, .L336+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L56
	ldr	r3, .L336+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L50
.L56:
	ldr	r3, .L336+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L57
	ldr	r3, .L336+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L57
	ldr	r3, .L336+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L57
	ldr	r3, .L336+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L50
.L57:
	ldr	r3, .L336+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L58
	ldr	r3, .L336+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L58
	ldr	r3, .L336+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L58
	ldr	r3, .L336+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L50
.L58:
	ldr	r3, .L336+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L336+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L336+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L336+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L50
.L59:
	ldr	r3, .L336+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L336+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L336+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L50:
	ldr	r3, .L336+336
	ldr	r2, [r3]
	ldr	r3, .L336+268
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L4
	ldr	r3, .L336+332
	ldr	r2, [r3]
	ldr	r3, .L336+268
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L4
	ldr	r3, .L336+104
	ldr	r2, [r3]
	ldr	r3, .L336+268
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L4
	ldr	r3, .L336+100
	ldr	r2, [r3]
	ldr	r3, .L336+268
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L4
	ldr	r3, .L336+96
	ldr	r2, [r3]
	ldr	r3, .L336+268
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L4
	ldr	r3, .L336+92
	ldr	r2, [r3]
	ldr	r3, .L336+268
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L4
	ldr	r3, .L336+20
	ldr	r2, [r3]
	ldr	r3, .L336+268
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L4
	ldr	r3, .L336+308
	ldr	r2, [r3]
	ldr	r3, .L336+268
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L4
	ldr	r3, .L336+344
	ldr	r2, [r3]
	ldr	r3, .L336+268
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L4
	ldr	r3, .L336+340
	ldr	r2, [r3]
	ldr	r3, .L336+268
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L4
	ldr	r3, .L336+252
	ldr	r2, [r3]
	ldr	r3, .L336+268
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L4
	ldr	r3, .L336+336
	ldr	r2, [r3]
	ldr	r3, .L336+268
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L60
	ldr	r3, .L336+332
	ldr	r2, [r3]
	ldr	r3, .L336+268
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L60
	ldr	r3, .L336+104
	ldr	r2, [r3]
	ldr	r3, .L336+268
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L60
	ldr	r3, .L336+100
	ldr	r2, [r3]
	ldr	r3, .L336+268
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L60
	ldr	r3, .L336+96
	ldr	r2, [r3]
	ldr	r3, .L336+268
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L60
	ldr	r3, .L336+92
	ldr	r2, [r3]
	ldr	r3, .L336+268
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L60
	ldr	r3, .L336+20
	ldr	r2, [r3]
	ldr	r3, .L336+268
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L60
	ldr	r3, .L336+308
	ldr	r2, [r3]
	ldr	r3, .L336+268
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L60
	ldr	r3, .L336+344
	ldr	r2, [r3]
	ldr	r3, .L336+268
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L60
	ldr	r3, .L336+340
	ldr	r2, [r3]
	ldr	r3, .L336+268
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L60
	ldr	r3, .L336+252
	ldr	r2, [r3]
	ldr	r3, .L336+268
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L4
.L60:
	ldr	r3, .L336+336
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L336+332
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L336+104
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L336+100
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L336+96
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L336+92
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L336+20
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L336+308
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L336+344
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L336+340
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L336+252
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L61
	mov	r3, #1
	b	.L62
.L337:
	.align	2
.L336:
	.word	p10_l0
	.word	p9_l1
	.word	p9_l0
	.word	p6_l1
	.word	p6_l0
	.word	num6
	.word	p3_l0
	.word	p8_l1
	.word	p2_l1
	.word	p8_l0
	.word	p0_l1
	.word	run2
	.word	p0_l0
	.word	p7_l1
	.word	p7_l0
	.word	p3_l1
	.word	p1_l0
	.word	p2_l0
	.word	p1_l1
	.word	p4_l0
	.word	p4_l1
	.word	p5_l0
	.word	p5_l1
	.word	num5
	.word	num4
	.word	num3
	.word	num2
	.word	_x_p6_l1
	.word	_x_p6_l0
	.word	_x_num6
	.word	_x_p3_l0
	.word	_x_p8_l1
	.word	_x_num5
	.word	_x_p2_l1
	.word	_x_p8_l0
	.word	_x_num4
	.word	_x_num3
	.word	_x_p0_l1
	.word	_x_num2
	.word	_x_run2
	.word	_x_p0_l0
	.word	_x_p7_l1
	.word	_x_num1
	.word	_x_run1
	.word	_x_p7_l0
	.word	_x_num0
	.word	_x_run0
	.word	_x_max_num
	.word	_x_min_num
	.word	_x_num7
	.word	_x_p3_l1
	.word	_x_num8
	.word	_x_run3
	.word	_x_p1_l0
	.word	_x_p2_l0
	.word	_x_p1_l1
	.word	_x_p4_l0
	.word	_x_p4_l1
	.word	_x_p5_l0
	.word	_x_p5_l1
	.word	p10_l1
	.word	_x_p10_l0
	.word	_x_p10_l1
	.word	num10
	.word	_x_num10
	.word	p10_l0
	.word	p10_l1
	.word	max_num
	.word	_x_num9
	.word	run3
	.word	run2
	.word	run0
	.word	run1
	.word	p9_l0
	.word	p9_l1
	.word	_x_p9_l1
	.word	_x_p9_l0
	.word	num7
	.word	num6
	.word	num5
	.word	num4
	.word	num3
	.word	num2
	.word	num1
	.word	num0
	.word	num9
	.word	num8
	.word	min_num
.L61:
	mov	r3, #0
.L62:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L336+336
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L63
	ldr	r3, .L336+348
	ldr	r2, [r3]
	ldr	r3, .L336+336
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L4
.L63:
	ldr	r3, .L336+332
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L64
	ldr	r3, .L336+348
	ldr	r2, [r3]
	ldr	r3, .L336+332
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L4
.L64:
	ldr	r3, .L336+104
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L65
	ldr	r3, .L336+348
	ldr	r2, [r3]
	ldr	r3, .L336+104
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L4
.L65:
	ldr	r3, .L336+100
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L66
	ldr	r3, .L336+348
	ldr	r2, [r3]
	ldr	r3, .L336+100
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L4
.L66:
	ldr	r3, .L336+96
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L67
	ldr	r3, .L336+348
	ldr	r2, [r3]
	ldr	r3, .L336+96
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L4
.L67:
	ldr	r3, .L336+92
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L68
	ldr	r3, .L336+348
	ldr	r2, [r3]
	ldr	r3, .L336+92
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L4
.L68:
	ldr	r3, .L336+312
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L69
	ldr	r3, .L336+348
	ldr	r2, [r3]
	ldr	r3, .L336+312
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L4
.L69:
	ldr	r3, .L336+308
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L70
	ldr	r3, .L336+348
	ldr	r2, [r3]
	ldr	r3, .L336+308
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L4
.L70:
	ldr	r3, .L336+344
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L71
	ldr	r3, .L336+348
	ldr	r2, [r3]
	ldr	r3, .L336+344
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L4
.L71:
	ldr	r3, .L336+340
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L72
	ldr	r3, .L336+348
	ldr	r2, [r3]
	ldr	r3, .L336+340
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L4
.L72:
	ldr	r3, .L336+252
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L73
	ldr	r3, .L336+348
	ldr	r2, [r3]
	ldr	r3, .L336+252
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L4
.L73:
	ldr	r3, .L336+340
	ldr	r2, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L74
	ldr	r3, .L336+344
	ldr	r2, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L74
	ldr	r3, .L336+308
	ldr	r2, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L74
	ldr	r3, .L336+312
	ldr	r2, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L74
	ldr	r3, .L336+92
	ldr	r2, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L74
	ldr	r3, .L336+96
	ldr	r2, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L74
	ldr	r3, .L336+100
	ldr	r2, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L74
	ldr	r3, .L336+104
	ldr	r2, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L74
	ldr	r3, .L336+336
	ldr	r2, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L74
	ldr	r3, .L336+332
	ldr	r2, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L74
	ldr	r3, .L336+252
	ldr	r2, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L4
.L74:
	mov	r3, #1
	b	.L75
.L4:
	mov	r3, #0
.L75:
	str	r3, [fp, #-8]
	b	.L76
.L334:
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+244
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+300
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+304
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+108
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+112
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L336+116
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+120
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+124
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L336+128
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+132
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+136
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L336+140
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L336+144
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+148
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L336+152
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+156
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+248
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+160
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+164
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L336+168
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+172
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+176
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L336+180
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+184
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L336+188
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L336+192
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L336+196
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+200
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L336+204
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L336+272
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L336+256
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+208
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+212
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+216
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+220
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+224
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+228
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+232
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L336+236
	strb	r2, [r3]
	ldr	r3, .L336+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L77
	ldr	r3, .L336+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L78
.L77:
	ldr	r3, .L336+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L79
	ldr	r3, .L336+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L78
.L79:
	ldr	r3, .L336+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L80
	ldr	r3, .L336+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L78
.L80:
	ldr	r3, .L336+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L336+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L78:
	ldr	r3, .L336+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L82
	ldr	r3, .L336+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L82
	ldr	r3, .L336+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L82
	ldr	r3, .L336+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L83
.L82:
	ldr	r3, .L336+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L336+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L336+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L336+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L336+252
	ldr	r2, [r3]
	ldr	r3, .L336+256
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L81
.L83:
	ldr	r3, .L336+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L84
	ldr	r3, .L336+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L84
	ldr	r3, .L336+256
	ldr	r2, [r3]
	ldr	r3, .L336+268
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmp	r3, #1
	beq	.L85
.L84:
	ldr	r3, .L336+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L85
	ldr	r3, .L336+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L85
	ldr	r3, .L336+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L85
	ldr	r3, .L336+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L85
	ldr	r3, .L336+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L85
	ldr	r3, .L336+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L85:
	ldr	r3, .L336+252
	ldr	r2, [r3]
	ldr	r3, .L336+256
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L86
	ldr	r3, .L336+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L87
	ldr	r3, .L336+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L88
.L87:
	ldr	r3, .L336+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L86
	ldr	r3, .L336+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L88
.L86:
	ldr	r3, .L336+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L88
	ldr	r3, .L336+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L88
	ldr	r3, .L336+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L88
	ldr	r3, .L336+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L88
	ldr	r3, .L336+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L88
	ldr	r3, .L336+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L88:
	ldr	r3, .L336+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L89
	ldr	r3, .L336+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L89
	ldr	r3, .L336+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L89
	ldr	r3, .L336+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L89
	ldr	r3, .L336+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L89
	ldr	r3, .L336+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L89
	ldr	r3, .L336+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L90
	ldr	r3, .L336+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L90
	mov	r3, #1
	b	.L91
.L90:
	mov	r3, #0
.L91:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L336+344
	ldr	r1, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L92
	ldr	r3, .L336+308
	ldr	r1, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L92
	ldr	r3, .L336+312
	ldr	r1, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L92
	ldr	r3, .L336+316
	ldr	r1, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L92
	ldr	r3, .L336+320
	ldr	r1, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L92
	ldr	r3, .L336+324
	ldr	r1, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L92
	ldr	r3, .L336+328
	ldr	r1, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L92
	ldr	r3, .L336+332
	ldr	r1, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L92
	ldr	r3, .L336+336
	ldr	r1, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L92
	ldr	r3, .L336+252
	ldr	r1, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r1, r3
	bgt	.L92
	ldr	r3, .L336+340
	ldr	r1, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L92
	mov	r3, #1
	b	.L93
.L92:
	mov	r3, #0
.L93:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
.L89:
	ldr	r3, .L336+252
	ldr	r2, [r3]
	ldr	r3, .L336+256
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L94
	ldr	r3, .L336+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L95
	ldr	r3, .L336+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L96
.L95:
	ldr	r3, .L336+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L94
	ldr	r3, .L336+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L96
.L94:
	ldr	r3, .L336+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L96
	ldr	r3, .L336+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L96
	ldr	r3, .L336+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L96
	ldr	r3, .L336+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L96
	ldr	r3, .L336+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L96
	ldr	r3, .L336+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L96:
	ldr	r3, .L336+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L97
	ldr	r3, .L336+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L97
	ldr	r3, .L336+252
	ldr	r2, [r3]
	ldr	r3, .L336+256
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L98
.L97:
	ldr	r3, .L336+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L98
	ldr	r3, .L336+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L98
	ldr	r3, .L336+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L98
	ldr	r3, .L336+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L98
	ldr	r3, .L336+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L98
	ldr	r3, .L336+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L81
.L98:
	ldr	r3, .L336+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L99
	ldr	r3, .L336+300
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L100
.L99:
	ldr	r3, .L336+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L101
	ldr	r3, .L336+300
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L100
.L101:
	ldr	r3, .L336+300
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L102
	ldr	r3, .L336+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L100
.L102:
	ldr	r3, .L336+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L336+300
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L100:
	ldr	r3, .L336+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L103
	ldr	r3, .L336+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L103
	ldr	r3, .L336+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L103
	ldr	r3, .L336+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L104
.L103:
	ldr	r3, .L336+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L336+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L336+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L336+300
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L336+340
	ldr	r2, [r3]
	ldr	r3, .L336+272
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L81
.L104:
	ldr	r3, .L336+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L105
	ldr	r3, .L336+300
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L105
	ldr	r3, .L336+272
	ldr	r2, [r3]
	ldr	r3, .L336+268
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmp	r3, #1
	beq	.L106
.L105:
	ldr	r3, .L336+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L106
	ldr	r3, .L336+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L106
	ldr	r3, .L336+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L106
	ldr	r3, .L336+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L106
	ldr	r3, .L336+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L106
	ldr	r3, .L336+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L106:
	ldr	r3, .L336+340
	ldr	r2, [r3]
	ldr	r3, .L336+272
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L107
	ldr	r3, .L336+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L108
	ldr	r3, .L336+300
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L109
.L108:
	ldr	r3, .L336+300
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L107
	ldr	r3, .L336+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L109
.L107:
	ldr	r3, .L336+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L109
	ldr	r3, .L336+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L109
	ldr	r3, .L336+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L109
	ldr	r3, .L336+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L109
	ldr	r3, .L336+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L109
	ldr	r3, .L336+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L109:
	ldr	r3, .L336+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L110
	ldr	r3, .L336+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L110
	ldr	r3, .L336+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L110
	ldr	r3, .L336+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L110
	ldr	r3, .L336+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L110
	ldr	r3, .L336+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L110
	ldr	r3, .L336+300
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L111
	ldr	r3, .L336+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L111
	mov	r3, #1
	b	.L112
.L111:
	mov	r3, #0
.L112:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L336+308
	ldr	r1, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L113
	ldr	r3, .L336+312
	ldr	r1, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L113
	ldr	r3, .L336+316
	ldr	r1, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L113
	ldr	r3, .L336+320
	ldr	r1, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L113
	ldr	r3, .L336+324
	ldr	r1, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L113
	ldr	r3, .L336+328
	ldr	r1, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L113
	ldr	r3, .L336+332
	ldr	r1, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L113
	ldr	r3, .L336+336
	ldr	r1, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L113
	ldr	r3, .L336+340
	ldr	r1, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r1, r3
	bgt	.L113
	ldr	r3, .L336+344
	ldr	r1, [r3]
	ldr	r3, .L336+348
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L113
	mov	r3, #1
	b	.L114
.L113:
	mov	r3, #0
.L114:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
.L110:
	ldr	r3, .L338
	ldr	r2, [r3]
	ldr	r3, .L338+4
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L115
	ldr	r3, .L338+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L116
	ldr	r3, .L338+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L117
.L116:
	ldr	r3, .L338+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L115
	ldr	r3, .L338+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L117
.L115:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L117
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L117
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L117
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L117
	ldr	r3, .L338+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L117
	ldr	r3, .L338+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L117:
	ldr	r3, .L338+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L118
	ldr	r3, .L338+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L118
	ldr	r3, .L338
	ldr	r2, [r3]
	ldr	r3, .L338+4
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L119
.L118:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L119
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L119
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L119
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L119
	ldr	r3, .L338+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L119
	ldr	r3, .L338+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L81
.L119:
	ldr	r3, .L338+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L120
	ldr	r3, .L338+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L121
.L120:
	ldr	r3, .L338+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L122
	ldr	r3, .L338+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L121
.L122:
	ldr	r3, .L338+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L123
	ldr	r3, .L338+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L121
.L123:
	ldr	r3, .L338+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L338+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L121:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L124
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L124
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L124
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L125
.L124:
	ldr	r3, .L338+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L338+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L338+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L338+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L338+40
	ldr	r2, [r3]
	ldr	r3, .L338+44
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L81
.L125:
	ldr	r3, .L338+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L126
	ldr	r3, .L338+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L126
	ldr	r3, .L338+44
	ldr	r2, [r3]
	ldr	r3, .L338+164
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmp	r3, #1
	beq	.L127
.L126:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L127
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L127
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L127
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L127
	ldr	r3, .L338+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L127
	ldr	r3, .L338+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L127:
	ldr	r3, .L338+40
	ldr	r2, [r3]
	ldr	r3, .L338+44
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L128
	ldr	r3, .L338+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L129
	ldr	r3, .L338+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L130
.L129:
	ldr	r3, .L338+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L128
	ldr	r3, .L338+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L130
.L128:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L130
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L130
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L130
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L130
	ldr	r3, .L338+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L130
	ldr	r3, .L338+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L130:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L131
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L131
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L131
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L131
	ldr	r3, .L338+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L131
	ldr	r3, .L338+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L131
	ldr	r3, .L338+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L132
	ldr	r3, .L338+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L132
	mov	r3, #1
	b	.L133
.L132:
	mov	r3, #0
.L133:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L338+80
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L134
	ldr	r3, .L338+104
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L134
	ldr	r3, .L338+144
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L134
	ldr	r3, .L338+168
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L134
	ldr	r3, .L338+120
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L134
	ldr	r3, .L338+124
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L134
	ldr	r3, .L338+128
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L134
	ldr	r3, .L338+40
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	bgt	.L134
	ldr	r3, .L338+48
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L134
	mov	r3, #1
	b	.L135
.L134:
	mov	r3, #0
.L135:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
.L131:
	ldr	r3, .L338+40
	ldr	r2, [r3]
	ldr	r3, .L338+44
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L136
	ldr	r3, .L338+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L137
	ldr	r3, .L338+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L138
.L137:
	ldr	r3, .L338+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L136
	ldr	r3, .L338+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L138
.L136:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L138
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L138
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L138
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L138
	ldr	r3, .L338+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L138
	ldr	r3, .L338+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L138:
	ldr	r3, .L338+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L139
	ldr	r3, .L338+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L139
	ldr	r3, .L338+40
	ldr	r2, [r3]
	ldr	r3, .L338+44
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L140
.L139:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L140
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L140
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L140
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L140
	ldr	r3, .L338+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L140
	ldr	r3, .L338+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L81
.L140:
	ldr	r3, .L338+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L141
	ldr	r3, .L338+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L142
.L141:
	ldr	r3, .L338+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L143
	ldr	r3, .L338+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L142
.L143:
	ldr	r3, .L338+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L144
	ldr	r3, .L338+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L142
.L144:
	ldr	r3, .L338+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L338+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L142:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L145
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L145
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L145
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L146
.L145:
	ldr	r3, .L338+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L338+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L338+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L338+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L338+48
	ldr	r2, [r3]
	ldr	r3, .L338+68
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L81
.L146:
	ldr	r3, .L338+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L147
	ldr	r3, .L338+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L147
	ldr	r3, .L338+68
	ldr	r2, [r3]
	ldr	r3, .L338+164
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmp	r3, #1
	beq	.L148
.L147:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L148
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L148
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L148
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L148
	ldr	r3, .L338+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L148
	ldr	r3, .L338+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L148:
	ldr	r3, .L338+48
	ldr	r2, [r3]
	ldr	r3, .L338+68
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L149
	ldr	r3, .L338+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L150
	ldr	r3, .L338+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
.L150:
	ldr	r3, .L338+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L149
	ldr	r3, .L338+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
.L149:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L151
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
	ldr	r3, .L338+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
	ldr	r3, .L338+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L151:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L152
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L152
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L152
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L152
	ldr	r3, .L338+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L152
	ldr	r3, .L338+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L152
	ldr	r3, .L338+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L153
	ldr	r3, .L338+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L153
	mov	r3, #1
	b	.L154
.L153:
	mov	r3, #0
.L154:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L338+104
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L155
	ldr	r3, .L338+144
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L155
	ldr	r3, .L338+168
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L155
	ldr	r3, .L338+120
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L155
	ldr	r3, .L338+124
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L155
	ldr	r3, .L338+128
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L155
	ldr	r3, .L338+48
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	bgt	.L155
	ldr	r3, .L338+80
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L155
	mov	r3, #1
	b	.L156
.L155:
	mov	r3, #0
.L156:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
.L152:
	ldr	r3, .L338+48
	ldr	r2, [r3]
	ldr	r3, .L338+68
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L157
	ldr	r3, .L338+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L158
	ldr	r3, .L338+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L159
.L158:
	ldr	r3, .L338+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L157
	ldr	r3, .L338+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L159
.L157:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L159
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L159
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L159
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L159
	ldr	r3, .L338+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L159
	ldr	r3, .L338+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L159:
	ldr	r3, .L338+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L160
	ldr	r3, .L338+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L160
	ldr	r3, .L338+48
	ldr	r2, [r3]
	ldr	r3, .L338+68
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L161
.L160:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L161
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L161
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L161
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L161
	ldr	r3, .L338+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L161
	ldr	r3, .L338+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L81
.L161:
	ldr	r3, .L338+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L162
	ldr	r3, .L338+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L163
.L162:
	ldr	r3, .L338+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L164
	ldr	r3, .L338+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L163
.L164:
	ldr	r3, .L338+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L165
	ldr	r3, .L338+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L163
.L165:
	ldr	r3, .L338+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L338+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L163:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L166
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L166
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L166
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L167
.L166:
	ldr	r3, .L338+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L338+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L338+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L338+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L338+80
	ldr	r2, [r3]
	ldr	r3, .L338+84
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L81
.L167:
	ldr	r3, .L338+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L168
	ldr	r3, .L338+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L168
	ldr	r3, .L338+84
	ldr	r2, [r3]
	ldr	r3, .L338+164
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmp	r3, #1
	beq	.L169
.L168:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L169
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L169
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L169
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L169
	ldr	r3, .L338+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L169
	ldr	r3, .L338+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L169:
	ldr	r3, .L338+80
	ldr	r2, [r3]
	ldr	r3, .L338+84
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L170
	ldr	r3, .L338+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L171
	ldr	r3, .L338+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L172
.L171:
	ldr	r3, .L338+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L170
	ldr	r3, .L338+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L172
.L170:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L172
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L172
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L172
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L172
	ldr	r3, .L338+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L172
	ldr	r3, .L338+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L172:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L173
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L173
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L173
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L173
	ldr	r3, .L338+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L173
	ldr	r3, .L338+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L173
	ldr	r3, .L338+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
	ldr	r3, .L338+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L174
	mov	r3, #1
	b	.L175
.L339:
	.align	2
.L338:
	.word	num9
	.word	_x_num9
	.word	_x_p9_l1
	.word	_x_p9_l0
	.word	p9_l1
	.word	p9_l0
	.word	_x_p8_l0
	.word	_x_p8_l1
	.word	p8_l0
	.word	p8_l1
	.word	num8
	.word	_x_num8
	.word	num7
	.word	_x_p7_l0
	.word	_x_p7_l1
	.word	p7_l0
	.word	p7_l1
	.word	_x_num7
	.word	_x_p6_l0
	.word	_x_p6_l1
	.word	num6
	.word	_x_num6
	.word	p6_l0
	.word	p6_l1
	.word	_x_p5_l0
	.word	_x_p5_l1
	.word	num5
	.word	_x_num5
	.word	p5_l0
	.word	p5_l1
	.word	num2
	.word	num1
	.word	num0
	.word	min_num
	.word	_x_p4_l0
	.word	_x_p4_l1
	.word	num4
	.word	_x_num4
	.word	p4_l0
	.word	p4_l1
	.word	run3
	.word	max_num
	.word	num3
	.word	_x_num3
	.word	run3
	.word	run2
	.word	run0
	.word	run1
	.word	p3_l0
	.word	p3_l1
	.word	_x_p3_l1
	.word	_x_p3_l0
.L174:
	mov	r3, #0
.L175:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L338+144
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L176
	ldr	r3, .L338+168
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L176
	ldr	r3, .L338+120
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L176
	ldr	r3, .L338+124
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L176
	ldr	r3, .L338+128
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L176
	ldr	r3, .L338+80
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	bgt	.L176
	ldr	r3, .L338+104
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L176
	mov	r3, #1
	b	.L177
.L176:
	mov	r3, #0
.L177:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
.L173:
	ldr	r3, .L338+80
	ldr	r2, [r3]
	ldr	r3, .L338+84
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L178
	ldr	r3, .L338+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L179
	ldr	r3, .L338+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L180
.L179:
	ldr	r3, .L338+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L178
	ldr	r3, .L338+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L180
.L178:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L180
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L180
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L180
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L180
	ldr	r3, .L338+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L180
	ldr	r3, .L338+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L180:
	ldr	r3, .L338+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L181
	ldr	r3, .L338+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L181
	ldr	r3, .L338+80
	ldr	r2, [r3]
	ldr	r3, .L338+84
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L182
.L181:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L182
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L182
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L182
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L182
	ldr	r3, .L338+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L182
	ldr	r3, .L338+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L81
.L182:
	ldr	r3, .L338+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L183
	ldr	r3, .L338+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L184
.L183:
	ldr	r3, .L338+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L185
	ldr	r3, .L338+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L184
.L185:
	ldr	r3, .L338+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L186
	ldr	r3, .L338+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L184
.L186:
	ldr	r3, .L338+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L338+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L184:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L187
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L187
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L187
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L188
.L187:
	ldr	r3, .L338+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L338+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L338+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L338+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L338+104
	ldr	r2, [r3]
	ldr	r3, .L338+108
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L81
.L188:
	ldr	r3, .L338+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L189
	ldr	r3, .L338+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L189
	ldr	r3, .L338+108
	ldr	r2, [r3]
	ldr	r3, .L338+164
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmp	r3, #1
	beq	.L190
.L189:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L190
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L190
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L190
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L190
	ldr	r3, .L338+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L190
	ldr	r3, .L338+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L190:
	ldr	r3, .L338+104
	ldr	r2, [r3]
	ldr	r3, .L338+108
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L191
	ldr	r3, .L338+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L192
	ldr	r3, .L338+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L192:
	ldr	r3, .L338+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L191
	ldr	r3, .L338+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L191:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L338+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L338+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L193:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L194
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L194
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L194
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L194
	ldr	r3, .L338+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L194
	ldr	r3, .L338+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L194
	ldr	r3, .L338+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L338+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	mov	r3, #1
	b	.L196
.L195:
	mov	r3, #0
.L196:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L338+168
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L197
	ldr	r3, .L338+120
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L197
	ldr	r3, .L338+124
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L197
	ldr	r3, .L338+128
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L197
	ldr	r3, .L338+104
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	bgt	.L197
	ldr	r3, .L338+144
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L197
	mov	r3, #1
	b	.L198
.L197:
	mov	r3, #0
.L198:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
.L194:
	ldr	r3, .L338+104
	ldr	r2, [r3]
	ldr	r3, .L338+108
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L199
	ldr	r3, .L338+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L200
	ldr	r3, .L338+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L201
.L200:
	ldr	r3, .L338+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L199
	ldr	r3, .L338+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L201
.L199:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L201
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L201
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L201
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L201
	ldr	r3, .L338+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L201
	ldr	r3, .L338+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L201:
	ldr	r3, .L338+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L202
	ldr	r3, .L338+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L202
	ldr	r3, .L338+104
	ldr	r2, [r3]
	ldr	r3, .L338+108
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L203
.L202:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L203
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L203
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L203
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L203
	ldr	r3, .L338+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L203
	ldr	r3, .L338+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L81
.L203:
	ldr	r3, .L338+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L204
	ldr	r3, .L338+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L204:
	ldr	r3, .L338+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L206
	ldr	r3, .L338+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L206:
	ldr	r3, .L338+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L207
	ldr	r3, .L338+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
.L207:
	ldr	r3, .L338+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L338+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L205:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L208
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L208
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L208
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L209
.L208:
	ldr	r3, .L338+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L338+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L338+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L338+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L338+144
	ldr	r2, [r3]
	ldr	r3, .L338+148
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L81
.L209:
	ldr	r3, .L338+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L210
	ldr	r3, .L338+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L210
	ldr	r3, .L338+148
	ldr	r2, [r3]
	ldr	r3, .L338+164
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmp	r3, #1
	beq	.L211
.L210:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L211
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L211
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L211
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L211
	ldr	r3, .L338+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L211
	ldr	r3, .L338+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L211:
	ldr	r3, .L338+144
	ldr	r2, [r3]
	ldr	r3, .L338+148
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L212
	ldr	r3, .L338+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L213
	ldr	r3, .L338+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
.L213:
	ldr	r3, .L338+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L212
	ldr	r3, .L338+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
.L212:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L214
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L214
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L214
	ldr	r3, .L338+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
	ldr	r3, .L338+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L214:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L215
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L215
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L215
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L215
	ldr	r3, .L338+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L215
	ldr	r3, .L338+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L215
	ldr	r3, .L338+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L216
	ldr	r3, .L338+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L216
	mov	r3, #1
	b	.L217
.L216:
	mov	r3, #0
.L217:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L338+120
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L218
	ldr	r3, .L338+124
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L218
	ldr	r3, .L338+128
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L218
	ldr	r3, .L338+144
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	bgt	.L218
	ldr	r3, .L338+168
	ldr	r1, [r3]
	ldr	r3, .L338+132
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L218
	mov	r3, #1
	b	.L219
.L218:
	mov	r3, #0
.L219:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
.L215:
	ldr	r3, .L338+144
	ldr	r2, [r3]
	ldr	r3, .L338+148
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L220
	ldr	r3, .L338+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L221
	ldr	r3, .L338+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L222
.L221:
	ldr	r3, .L338+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L220
	ldr	r3, .L338+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L222
.L220:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L222
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L222
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L222
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L222
	ldr	r3, .L338+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L222
	ldr	r3, .L338+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L222:
	ldr	r3, .L338+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L223
	ldr	r3, .L338+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L223
	ldr	r3, .L338+144
	ldr	r2, [r3]
	ldr	r3, .L338+148
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L224
.L223:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L224
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L224
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L224
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L224
	ldr	r3, .L338+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L224
	ldr	r3, .L338+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L81
.L224:
	ldr	r3, .L338+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L225
	ldr	r3, .L338+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L226
.L225:
	ldr	r3, .L338+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L227
	ldr	r3, .L338+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L226
.L227:
	ldr	r3, .L338+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L228
	ldr	r3, .L338+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L226
.L228:
	ldr	r3, .L338+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L338+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L226:
	ldr	r3, .L338+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L229
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L229
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L229
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L230
.L229:
	ldr	r3, .L338+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L338+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L338+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L338+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L338+168
	ldr	r2, [r3]
	ldr	r3, .L338+172
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L81
.L230:
	ldr	r3, .L338+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L231
	ldr	r3, .L338+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L231
	ldr	r3, .L338+172
	ldr	r2, [r3]
	ldr	r3, .L338+164
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmp	r3, #1
	beq	.L232
.L231:
	ldr	r3, .L338+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L232
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L232
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L232
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L232
	ldr	r3, .L338+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L232
	ldr	r3, .L338+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L232:
	ldr	r3, .L338+168
	ldr	r2, [r3]
	ldr	r3, .L338+172
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L233
	ldr	r3, .L338+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L234
	ldr	r3, .L338+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L235
.L234:
	ldr	r3, .L338+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L233
	ldr	r3, .L338+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L235
.L233:
	ldr	r3, .L338+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L235
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L235
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L235
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L235
	ldr	r3, .L338+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L235
	ldr	r3, .L338+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L235:
	ldr	r3, .L338+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L236
	ldr	r3, .L338+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L236
	ldr	r3, .L338+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L236
	ldr	r3, .L338+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L236
	ldr	r3, .L338+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L236
	ldr	r3, .L338+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L236
	ldr	r3, .L338+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L237
	ldr	r3, .L338+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L237
	mov	r3, #1
	b	.L238
.L237:
	mov	r3, #0
.L238:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L340+156
	ldr	r1, [r3]
	ldr	r3, .L340+204
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L239
	ldr	r3, .L340+180
	ldr	r1, [r3]
	ldr	r3, .L340+204
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L239
	ldr	r3, .L340+100
	ldr	r1, [r3]
	ldr	r3, .L340+204
	ldr	r3, [r3]
	cmp	r1, r3
	bgt	.L239
	ldr	r3, .L340+116
	ldr	r1, [r3]
	ldr	r3, .L340+204
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L239
	mov	r3, #1
	b	.L240
.L239:
	mov	r3, #0
.L240:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
.L236:
	ldr	r3, .L340+100
	ldr	r2, [r3]
	ldr	r3, .L340+96
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L241
	ldr	r3, .L340+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L242
	ldr	r3, .L340+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L243
.L242:
	ldr	r3, .L340+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L340+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L243
.L241:
	ldr	r3, .L340+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L243
	ldr	r3, .L340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L243
	ldr	r3, .L340+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L243
	ldr	r3, .L340+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L243
	ldr	r3, .L340+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L243
	ldr	r3, .L340+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L243:
	ldr	r3, .L340+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L244
	ldr	r3, .L340+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L244
	ldr	r3, .L340+100
	ldr	r2, [r3]
	ldr	r3, .L340+96
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L245
.L244:
	ldr	r3, .L340+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L340+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L340+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L340+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L340+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L81
.L245:
	ldr	r3, .L340+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L246
	ldr	r3, .L340+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L246:
	ldr	r3, .L340+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L248
	ldr	r3, .L340+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L248:
	ldr	r3, .L340+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L249
	ldr	r3, .L340+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L249:
	ldr	r3, .L340+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L340+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L247:
	ldr	r3, .L340+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L250
	ldr	r3, .L340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L250
	ldr	r3, .L340+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L250
	ldr	r3, .L340+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L251
.L250:
	ldr	r3, .L340+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L340+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L340+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L340+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L340+116
	ldr	r2, [r3]
	ldr	r3, .L340+112
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L81
.L251:
	ldr	r3, .L340+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L252
	ldr	r3, .L340+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L252
	ldr	r3, .L340+112
	ldr	r2, [r3]
	ldr	r3, .L340+196
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmp	r3, #1
	beq	.L253
.L252:
	ldr	r3, .L340+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L340+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L340+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L340+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L340+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L253:
	ldr	r3, .L340+116
	ldr	r2, [r3]
	ldr	r3, .L340+112
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L254
	ldr	r3, .L340+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L255
	ldr	r3, .L340+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L256
.L255:
	ldr	r3, .L340+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L254
	ldr	r3, .L340+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L256
.L254:
	ldr	r3, .L340+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L256
	ldr	r3, .L340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L256
	ldr	r3, .L340+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L256
	ldr	r3, .L340+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L256
	ldr	r3, .L340+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L256
	ldr	r3, .L340+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L256:
	ldr	r3, .L340+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L257
	ldr	r3, .L340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L257
	ldr	r3, .L340+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L257
	ldr	r3, .L340+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L257
	ldr	r3, .L340+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L257
	ldr	r3, .L340+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L257
	ldr	r3, .L340+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L258
	ldr	r3, .L340+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L258
	mov	r3, #1
	b	.L259
.L258:
	mov	r3, #0
.L259:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L340+180
	ldr	r1, [r3]
	ldr	r3, .L340+204
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L260
	ldr	r3, .L340+116
	ldr	r1, [r3]
	ldr	r3, .L340+204
	ldr	r3, [r3]
	cmp	r1, r3
	bgt	.L260
	ldr	r3, .L340+156
	ldr	r1, [r3]
	ldr	r3, .L340+204
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L260
	mov	r3, #1
	b	.L261
.L260:
	mov	r3, #0
.L261:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
.L257:
	ldr	r3, .L340+116
	ldr	r2, [r3]
	ldr	r3, .L340+112
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L262
	ldr	r3, .L340+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L263
	ldr	r3, .L340+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L264
.L263:
	ldr	r3, .L340+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L262
	ldr	r3, .L340+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L264
.L262:
	ldr	r3, .L340+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L264
	ldr	r3, .L340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L264
	ldr	r3, .L340+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L264
	ldr	r3, .L340+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L264
	ldr	r3, .L340+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L264
	ldr	r3, .L340+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L264:
	ldr	r3, .L340+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L265
	ldr	r3, .L340+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L265
	ldr	r3, .L340+116
	ldr	r2, [r3]
	ldr	r3, .L340+112
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L266
.L265:
	ldr	r3, .L340+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L266
	ldr	r3, .L340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L266
	ldr	r3, .L340+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L266
	ldr	r3, .L340+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L266
	ldr	r3, .L340+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L266
	ldr	r3, .L340+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L81
.L266:
	ldr	r3, .L340+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L267
	ldr	r3, .L340+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L268
.L267:
	ldr	r3, .L340+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L269
	ldr	r3, .L340+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L268
.L269:
	ldr	r3, .L340+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L270
	ldr	r3, .L340+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L268
.L270:
	ldr	r3, .L340+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L340+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L268:
	ldr	r3, .L340+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L271
	ldr	r3, .L340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L271
	ldr	r3, .L340+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L271
	ldr	r3, .L340+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L272
.L271:
	ldr	r3, .L340+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L340+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L340+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L340+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L340+156
	ldr	r2, [r3]
	ldr	r3, .L340+152
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L81
.L272:
	ldr	r3, .L340+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L273
	ldr	r3, .L340+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L273
	ldr	r3, .L340+152
	ldr	r2, [r3]
	ldr	r3, .L340+196
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmp	r3, #1
	beq	.L274
.L273:
	ldr	r3, .L340+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L274
	ldr	r3, .L340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L274
	ldr	r3, .L340+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L274
	ldr	r3, .L340+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L274
	ldr	r3, .L340+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L274
	ldr	r3, .L340+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L274:
	ldr	r3, .L340+156
	ldr	r2, [r3]
	ldr	r3, .L340+152
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L275
	ldr	r3, .L340+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L276
	ldr	r3, .L340+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L277
.L276:
	ldr	r3, .L340+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L275
	ldr	r3, .L340+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L277
.L275:
	ldr	r3, .L340+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L277
	ldr	r3, .L340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L277
	ldr	r3, .L340+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L277
	ldr	r3, .L340+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L277
	ldr	r3, .L340+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L277
	ldr	r3, .L340+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L277:
	ldr	r3, .L340+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L278
	ldr	r3, .L340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L278
	ldr	r3, .L340+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L278
	ldr	r3, .L340+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L278
	ldr	r3, .L340+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L278
	ldr	r3, .L340+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L278
	ldr	r3, .L340+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L279
	ldr	r3, .L340+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L279
	mov	r3, #1
	b	.L280
.L279:
	mov	r3, #0
.L280:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L340+156
	ldr	r1, [r3]
	ldr	r3, .L340+204
	ldr	r3, [r3]
	cmp	r1, r3
	bgt	.L281
	ldr	r3, .L340+180
	ldr	r1, [r3]
	ldr	r3, .L340+204
	ldr	r3, [r3]
	cmp	r1, r3
	beq	.L281
	mov	r3, #1
	b	.L282
.L281:
	mov	r3, #0
.L282:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
.L278:
	ldr	r3, .L340+156
	ldr	r2, [r3]
	ldr	r3, .L340+152
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L283
	ldr	r3, .L340+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L284
	ldr	r3, .L340+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L285
.L284:
	ldr	r3, .L340+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L283
	ldr	r3, .L340+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L285
.L283:
	ldr	r3, .L340+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L285
	ldr	r3, .L340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L285
	ldr	r3, .L340+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L285
	ldr	r3, .L340+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L285
	ldr	r3, .L340+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L285
	ldr	r3, .L340+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L285:
	ldr	r3, .L340+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L286
	ldr	r3, .L340+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L286
	ldr	r3, .L340+156
	ldr	r2, [r3]
	ldr	r3, .L340+152
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L287
.L286:
	ldr	r3, .L340+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L287
	ldr	r3, .L340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L287
	ldr	r3, .L340+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L287
	ldr	r3, .L340+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L287
	ldr	r3, .L340+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L287
	ldr	r3, .L340+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L81
.L287:
	ldr	r3, .L340+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L288
	ldr	r3, .L340+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L289
.L288:
	ldr	r3, .L340+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L290
	ldr	r3, .L340+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L289
.L290:
	ldr	r3, .L340+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L291
	ldr	r3, .L340+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L289
.L291:
	ldr	r3, .L340+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L340+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L289:
	ldr	r3, .L340+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L292
	ldr	r3, .L340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L292
	ldr	r3, .L340+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L292
	ldr	r3, .L340+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L293
.L292:
	ldr	r3, .L340+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L340+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L340+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L340+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L340+180
	ldr	r2, [r3]
	ldr	r3, .L340+176
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L81
.L293:
	ldr	r3, .L340+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L294
	ldr	r3, .L340+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L294
	ldr	r3, .L340+176
	ldr	r2, [r3]
	ldr	r3, .L340+196
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmp	r3, #1
	beq	.L295
.L294:
	ldr	r3, .L340+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L295
	ldr	r3, .L340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L295
	ldr	r3, .L340+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L295
	ldr	r3, .L340+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L295
	ldr	r3, .L340+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L295
	ldr	r3, .L340+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L295:
	ldr	r3, .L340+180
	ldr	r2, [r3]
	ldr	r3, .L340+176
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L296
	ldr	r3, .L340+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L297
	ldr	r3, .L340+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L298
.L297:
	ldr	r3, .L340+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L296
	ldr	r3, .L340+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L298
.L296:
	ldr	r3, .L340+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L298
	ldr	r3, .L340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L298
	ldr	r3, .L340+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L298
	ldr	r3, .L340+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L298
	ldr	r3, .L340+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L298
	ldr	r3, .L340+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L298:
	ldr	r3, .L340+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L299
	ldr	r3, .L340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L299
	ldr	r3, .L340+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L299
	ldr	r3, .L340+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L299
	ldr	r3, .L340+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L299
	ldr	r3, .L340+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L299
	ldr	r3, .L340+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L300
	ldr	r3, .L340+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L300
	mov	r3, #1
	b	.L301
.L341:
	.align	2
.L340:
	.word	_x_p10_l0
	.word	p10_l0
	.word	_x_p9_l1
	.word	p9_l1
	.word	_x_p9_l0
	.word	p9_l0
	.word	_x_p6_l1
	.word	p6_l1
	.word	_x_p6_l0
	.word	p6_l0
	.word	_x_num6
	.word	num6
	.word	_x_p3_l0
	.word	p3_l0
	.word	_x_p8_l1
	.word	p8_l1
	.word	_x_num5
	.word	num5
	.word	_x_p2_l1
	.word	p2_l1
	.word	_x_p8_l0
	.word	p8_l0
	.word	_x_num4
	.word	num4
	.word	_x_num3
	.word	num3
	.word	_x_p0_l1
	.word	p0_l1
	.word	_x_num2
	.word	num2
	.word	_x_run2
	.word	run2
	.word	_x_p10_l1
	.word	p10_l1
	.word	_x_p0_l0
	.word	p0_l0
	.word	_x_p7_l1
	.word	p7_l1
	.word	_x_num1
	.word	num1
	.word	_x_run1
	.word	run1
	.word	_x_p7_l0
	.word	p7_l0
	.word	_x_num0
	.word	num0
	.word	_x_run0
	.word	run0
	.word	_x_max_num
	.word	max_num
	.word	_x_min_num
	.word	min_num
	.word	_x_num7
	.word	num7
	.word	_x_p3_l1
	.word	p3_l1
	.word	_x_num8
	.word	num8
	.word	_x_num9
	.word	num9
	.word	_x_num10
	.word	num10
	.word	_x_run3
	.word	run3
	.word	_x_p1_l0
	.word	p1_l0
	.word	_x_p2_l0
	.word	p2_l0
	.word	_x_p1_l1
	.word	p1_l1
	.word	_x_p4_l0
	.word	p4_l0
	.word	_x_p4_l1
	.word	p4_l1
	.word	_x_p5_l0
	.word	p5_l0
	.word	_x_p5_l1
	.word	p5_l1
.L300:
	mov	r3, #0
.L301:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L340+180
	ldr	r1, [r3]
	ldr	r3, .L340+204
	ldr	r3, [r3]
	cmp	r1, r3
	movle	r3, #1
	movgt	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
.L299:
	ldr	r3, .L340+180
	ldr	r2, [r3]
	ldr	r3, .L340+176
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L302
	ldr	r3, .L340+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L303
	ldr	r3, .L340+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L304
.L303:
	ldr	r3, .L340+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L340+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L304
.L302:
	ldr	r3, .L340+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L304
	ldr	r3, .L340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L304
	ldr	r3, .L340+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L304
	ldr	r3, .L340+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L304
	ldr	r3, .L340+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L304
	ldr	r3, .L340+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
.L304:
	ldr	r3, .L340+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L305
	ldr	r3, .L340+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L305
	ldr	r3, .L340+180
	ldr	r2, [r3]
	ldr	r3, .L340+176
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L306
.L305:
	ldr	r3, .L340+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L306
	ldr	r3, .L340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L306
	ldr	r3, .L340+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L306
	ldr	r3, .L340+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L306
	ldr	r3, .L340+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L306
	ldr	r3, .L340+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L81
.L306:
	ldr	r3, .L340+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L307
	ldr	r3, .L340+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L307
	ldr	r3, .L340+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L307
	ldr	r3, .L340+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L308
.L307:
	ldr	r3, .L340+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L309
	ldr	r3, .L340+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L309
	ldr	r3, .L340+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L309
	ldr	r3, .L340+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L308
.L309:
	ldr	r3, .L340+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L310
	ldr	r3, .L340+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L310
	ldr	r3, .L340+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L310
	ldr	r3, .L340+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L308
.L310:
	ldr	r3, .L340+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L311
	ldr	r3, .L340+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L311
	ldr	r3, .L340+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L311
	ldr	r3, .L340+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L308
.L311:
	ldr	r3, .L340+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L312
	ldr	r3, .L340+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L312
	ldr	r3, .L340+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L312
	ldr	r3, .L340+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L308
.L312:
	ldr	r3, .L340+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L313
	ldr	r3, .L340+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L313
	ldr	r3, .L340+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L313
	ldr	r3, .L340+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L308
.L313:
	ldr	r3, .L340+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L314
	ldr	r3, .L340+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L314
	ldr	r3, .L340+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L314
	ldr	r3, .L340+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L308
.L314:
	ldr	r3, .L340+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L315
	ldr	r3, .L340+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L315
	ldr	r3, .L340+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L315
	ldr	r3, .L340+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L308
.L315:
	ldr	r3, .L340+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L316
	ldr	r3, .L340+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L316
	ldr	r3, .L340+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L316
	ldr	r3, .L340+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L308
.L316:
	ldr	r3, .L340+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L317
	ldr	r3, .L340+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L317
	ldr	r3, .L340+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L317
	ldr	r3, .L340+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L308
.L317:
	ldr	r3, .L340+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L81
	ldr	r3, .L340+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L81
	ldr	r3, .L340+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L340+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L81
.L308:
	ldr	r3, .L340+176
	ldr	r2, [r3]
	ldr	r3, .L340+192
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L81
	ldr	r3, .L340+152
	ldr	r2, [r3]
	ldr	r3, .L340+192
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L81
	ldr	r3, .L340+112
	ldr	r2, [r3]
	ldr	r3, .L340+192
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L81
	ldr	r3, .L340+96
	ldr	r2, [r3]
	ldr	r3, .L340+192
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L81
	ldr	r3, .L340+88
	ldr	r2, [r3]
	ldr	r3, .L340+192
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L81
	ldr	r3, .L340+64
	ldr	r2, [r3]
	ldr	r3, .L340+192
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L81
	ldr	r3, .L340+40
	ldr	r2, [r3]
	ldr	r3, .L340+192
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L81
	ldr	r3, .L340+208
	ldr	r2, [r3]
	ldr	r3, .L340+192
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L81
	ldr	r3, .L340+224
	ldr	r2, [r3]
	ldr	r3, .L340+192
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L81
	ldr	r3, .L340+232
	ldr	r2, [r3]
	ldr	r3, .L340+192
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L81
	ldr	r3, .L340+240
	ldr	r2, [r3]
	ldr	r3, .L340+192
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L81
	ldr	r3, .L340+176
	ldr	r2, [r3]
	ldr	r3, .L340+192
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L318
	ldr	r3, .L340+152
	ldr	r2, [r3]
	ldr	r3, .L340+192
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L318
	ldr	r3, .L340+112
	ldr	r2, [r3]
	ldr	r3, .L340+192
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L318
	ldr	r3, .L340+96
	ldr	r2, [r3]
	ldr	r3, .L340+192
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L318
	ldr	r3, .L340+88
	ldr	r2, [r3]
	ldr	r3, .L340+192
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L318
	ldr	r3, .L340+64
	ldr	r2, [r3]
	ldr	r3, .L340+192
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L318
	ldr	r3, .L340+40
	ldr	r2, [r3]
	ldr	r3, .L340+192
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L318
	ldr	r3, .L340+208
	ldr	r2, [r3]
	ldr	r3, .L340+192
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L318
	ldr	r3, .L340+224
	ldr	r2, [r3]
	ldr	r3, .L340+192
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L318
	ldr	r3, .L340+232
	ldr	r2, [r3]
	ldr	r3, .L340+192
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L318
	ldr	r3, .L340+240
	ldr	r2, [r3]
	ldr	r3, .L340+192
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L81
.L318:
	ldr	r3, .L340+176
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L319
	ldr	r3, .L340+152
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L319
	ldr	r3, .L340+112
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L319
	ldr	r3, .L340+96
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L319
	ldr	r3, .L340+88
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L319
	ldr	r3, .L340+64
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L319
	ldr	r3, .L340+40
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L319
	ldr	r3, .L340+208
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L319
	ldr	r3, .L340+224
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L319
	ldr	r3, .L340+232
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L319
	ldr	r3, .L340+240
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L319
	mov	r3, #1
	b	.L320
.L319:
	mov	r3, #0
.L320:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L340+200
	ldr	r3, [r3]
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L340+176
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L321
	ldr	r3, .L340+200
	ldr	r2, [r3]
	ldr	r3, .L340+176
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L81
.L321:
	ldr	r3, .L340+152
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L322
	ldr	r3, .L340+200
	ldr	r2, [r3]
	ldr	r3, .L340+152
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L81
.L322:
	ldr	r3, .L340+112
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L323
	ldr	r3, .L340+200
	ldr	r2, [r3]
	ldr	r3, .L340+112
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L81
.L323:
	ldr	r3, .L340+96
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L324
	ldr	r3, .L340+200
	ldr	r2, [r3]
	ldr	r3, .L340+96
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L81
.L324:
	ldr	r3, .L340+88
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L325
	ldr	r3, .L340+200
	ldr	r2, [r3]
	ldr	r3, .L340+88
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L81
.L325:
	ldr	r3, .L340+64
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L326
	ldr	r3, .L340+200
	ldr	r2, [r3]
	ldr	r3, .L340+64
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L81
.L326:
	ldr	r3, .L340+40
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L327
	ldr	r3, .L340+200
	ldr	r2, [r3]
	ldr	r3, .L340+40
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L81
.L327:
	ldr	r3, .L340+208
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L328
	ldr	r3, .L340+200
	ldr	r2, [r3]
	ldr	r3, .L340+208
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L81
.L328:
	ldr	r3, .L340+224
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L329
	ldr	r3, .L340+200
	ldr	r2, [r3]
	ldr	r3, .L340+224
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L81
.L329:
	ldr	r3, .L340+232
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L330
	ldr	r3, .L340+200
	ldr	r2, [r3]
	ldr	r3, .L340+232
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L81
.L330:
	ldr	r3, .L340+240
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L331
	ldr	r3, .L340+200
	ldr	r2, [r3]
	ldr	r3, .L340+240
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L81
.L331:
	ldr	r3, .L340+176
	ldr	r2, [r3]
	ldr	r3, .L340+200
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L332
	ldr	r3, .L340+152
	ldr	r2, [r3]
	ldr	r3, .L340+200
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L332
	ldr	r3, .L340+112
	ldr	r2, [r3]
	ldr	r3, .L340+200
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L332
	ldr	r3, .L340+96
	ldr	r2, [r3]
	ldr	r3, .L340+200
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L332
	ldr	r3, .L340+88
	ldr	r2, [r3]
	ldr	r3, .L340+200
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L332
	ldr	r3, .L340+64
	ldr	r2, [r3]
	ldr	r3, .L340+200
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L332
	ldr	r3, .L340+40
	ldr	r2, [r3]
	ldr	r3, .L340+200
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L332
	ldr	r3, .L340+208
	ldr	r2, [r3]
	ldr	r3, .L340+200
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L332
	ldr	r3, .L340+224
	ldr	r2, [r3]
	ldr	r3, .L340+200
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L332
	ldr	r3, .L340+232
	ldr	r2, [r3]
	ldr	r3, .L340+200
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L332
	ldr	r3, .L340+240
	ldr	r2, [r3]
	ldr	r3, .L340+200
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L81
.L332:
	mov	r3, #1
	b	.L333
.L81:
	mov	r3, #0
.L333:
	str	r3, [fp, #-8]
	ldr	r3, .L340
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L340+4
	strb	r2, [r3]
	ldr	r3, .L340+8
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L340+12
	strb	r2, [r3]
	ldr	r3, .L340+16
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L340+20
	strb	r2, [r3]
	ldr	r3, .L340+24
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L340+28
	strb	r2, [r3]
	ldr	r3, .L340+32
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L340+36
	strb	r2, [r3]
	ldr	r3, .L340+40
	ldr	r3, [r3]
	ldr	r2, .L340+44
	str	r3, [r2]
	ldr	r3, .L340+48
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L340+52
	strb	r2, [r3]
	ldr	r3, .L340+56
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L340+60
	strb	r2, [r3]
	ldr	r3, .L340+64
	ldr	r3, [r3]
	ldr	r2, .L340+68
	str	r3, [r2]
	ldr	r3, .L340+72
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L340+76
	strb	r2, [r3]
	ldr	r3, .L340+80
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L340+84
	strb	r2, [r3]
	ldr	r3, .L340+88
	ldr	r3, [r3]
	ldr	r2, .L340+92
	str	r3, [r2]
	ldr	r3, .L340+96
	ldr	r3, [r3]
	ldr	r2, .L340+100
	str	r3, [r2]
	ldr	r3, .L340+104
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L340+108
	strb	r2, [r3]
	ldr	r3, .L340+112
	ldr	r3, [r3]
	ldr	r2, .L340+116
	str	r3, [r2]
	ldr	r3, .L340+120
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L340+124
	strb	r2, [r3]
	ldr	r3, .L340+128
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L340+132
	strb	r2, [r3]
	ldr	r3, .L340+136
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L340+140
	strb	r2, [r3]
	ldr	r3, .L340+144
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L340+148
	strb	r2, [r3]
	ldr	r3, .L340+152
	ldr	r3, [r3]
	ldr	r2, .L340+156
	str	r3, [r2]
	ldr	r3, .L340+160
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L340+164
	strb	r2, [r3]
	ldr	r3, .L340+168
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L340+172
	strb	r2, [r3]
	ldr	r3, .L340+176
	ldr	r3, [r3]
	ldr	r2, .L340+180
	str	r3, [r2]
	ldr	r3, .L340+184
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L340+188
	strb	r2, [r3]
	ldr	r3, .L340+192
	ldr	r3, [r3]
	ldr	r2, .L340+196
	str	r3, [r2]
	ldr	r3, .L340+200
	ldr	r3, [r3]
	ldr	r2, .L340+204
	str	r3, [r2]
	ldr	r3, .L340+208
	ldr	r3, [r3]
	ldr	r2, .L340+212
	str	r3, [r2]
	ldr	r3, .L340+216
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L340+220
	strb	r2, [r3]
	ldr	r3, .L340+224
	ldr	r3, [r3]
	ldr	r2, .L340+228
	str	r3, [r2]
	ldr	r3, .L340+232
	ldr	r3, [r3]
	ldr	r2, .L340+236
	str	r3, [r2]
	ldr	r3, .L340+240
	ldr	r3, [r3]
	ldr	r2, .L340+244
	str	r3, [r2]
	ldr	r3, .L340+248
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L340+252
	strb	r2, [r3]
	ldr	r3, .L340+256
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L340+260
	strb	r2, [r3]
	ldr	r3, .L340+264
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L340+268
	strb	r2, [r3]
	ldr	r3, .L340+272
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L340+276
	strb	r2, [r3]
	ldr	r3, .L340+280
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L340+284
	strb	r2, [r3]
	ldr	r3, .L340+288
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L340+292
	strb	r2, [r3]
	ldr	r3, .L340+296
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L340+300
	strb	r2, [r3]
	ldr	r3, .L340+304
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L340+308
	strb	r2, [r3]
.L76:
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	bne	.L334
	mov	r3, #0
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	main, .-main
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
