	.file	"586534.c"
	.intel_syntax noprefix
	.text
	.globl	__VERIFIER_nondet_bool
	.type	__VERIFIER_nondet_bool, @function
__VERIFIER_nondet_bool:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	call	__VERIFIER_nondet_int@PLT
	test	eax, eax
	setne	al
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.globl	sm6_loop_len
	.bss
	.align 4
	.type	sm6_loop_len, @object
	.size	sm6_loop_len, 4
sm6_loop_len:
	.zero	4
	.globl	_x_sm6_loop_len
	.align 4
	.type	_x_sm6_loop_len, @object
	.size	_x_sm6_loop_len, 4
_x_sm6_loop_len:
	.zero	4
	.globl	sm6_state
	.type	sm6_state, @object
	.size	sm6_state, 1
sm6_state:
	.zero	1
	.globl	_x_sm6_state
	.type	_x_sm6_state, @object
	.size	_x_sm6_state, 1
_x_sm6_state:
	.zero	1
	.globl	sm5_loop_len
	.align 4
	.type	sm5_loop_len, @object
	.size	sm5_loop_len, 4
sm5_loop_len:
	.zero	4
	.globl	_x_sm5_loop_len
	.align 4
	.type	_x_sm5_loop_len, @object
	.size	_x_sm5_loop_len, 4
_x_sm5_loop_len:
	.zero	4
	.globl	sm5_state
	.type	sm5_state, @object
	.size	sm5_state, 1
sm5_state:
	.zero	1
	.globl	_x_sm5_state
	.type	_x_sm5_state, @object
	.size	_x_sm5_state, 1
_x_sm5_state:
	.zero	1
	.globl	sm4_loop_len
	.align 4
	.type	sm4_loop_len, @object
	.size	sm4_loop_len, 4
sm4_loop_len:
	.zero	4
	.globl	_x_sm4_loop_len
	.align 4
	.type	_x_sm4_loop_len, @object
	.size	_x_sm4_loop_len, 4
_x_sm4_loop_len:
	.zero	4
	.globl	sm6_l
	.align 4
	.type	sm6_l, @object
	.size	sm6_l, 4
sm6_l:
	.zero	4
	.globl	_x_sm6_l
	.align 4
	.type	_x_sm6_l, @object
	.size	_x_sm6_l, 4
_x_sm6_l:
	.zero	4
	.globl	sm4_state
	.type	sm4_state, @object
	.size	sm4_state, 1
sm4_state:
	.zero	1
	.globl	_x_sm4_state
	.type	_x_sm4_state, @object
	.size	_x_sm4_state, 1
_x_sm4_state:
	.zero	1
	.globl	run
	.align 4
	.type	run, @object
	.size	run, 4
run:
	.zero	4
	.globl	_x_run
	.align 4
	.type	_x_run, @object
	.size	_x_run, 4
_x_run:
	.zero	4
	.globl	sm5_l
	.align 4
	.type	sm5_l, @object
	.size	sm5_l, 4
sm5_l:
	.zero	4
	.globl	_x_sm5_l
	.align 4
	.type	_x_sm5_l, @object
	.size	_x_sm5_l, 4
_x_sm5_l:
	.zero	4
	.globl	sm3_state
	.type	sm3_state, @object
	.size	sm3_state, 1
sm3_state:
	.zero	1
	.globl	_x_sm3_state
	.type	_x_sm3_state, @object
	.size	_x_sm3_state, 1
_x_sm3_state:
	.zero	1
	.globl	sm1_l
	.align 4
	.type	sm1_l, @object
	.size	sm1_l, 4
sm1_l:
	.zero	4
	.globl	_x_sm1_l
	.align 4
	.type	_x_sm1_l, @object
	.size	_x_sm1_l, 4
_x_sm1_l:
	.zero	4
	.globl	semaphore
	.align 4
	.type	semaphore, @object
	.size	semaphore, 4
semaphore:
	.zero	4
	.globl	_x_semaphore
	.align 4
	.type	_x_semaphore, @object
	.size	_x_semaphore, 4
_x_semaphore:
	.zero	4
	.globl	sm1_loop_len
	.align 4
	.type	sm1_loop_len, @object
	.size	sm1_loop_len, 4
sm1_loop_len:
	.zero	4
	.globl	_x_sm1_loop_len
	.align 4
	.type	_x_sm1_loop_len, @object
	.size	_x_sm1_loop_len, 4
_x_sm1_loop_len:
	.zero	4
	.globl	sm2_loop_len
	.align 4
	.type	sm2_loop_len, @object
	.size	sm2_loop_len, 4
sm2_loop_len:
	.zero	4
	.globl	_x_sm2_loop_len
	.align 4
	.type	_x_sm2_loop_len, @object
	.size	_x_sm2_loop_len, 4
_x_sm2_loop_len:
	.zero	4
	.globl	sm0_loop_len
	.align 4
	.type	sm0_loop_len, @object
	.size	sm0_loop_len, 4
sm0_loop_len:
	.zero	4
	.globl	_x_sm0_loop_len
	.align 4
	.type	_x_sm0_loop_len, @object
	.size	_x_sm0_loop_len, 4
_x_sm0_loop_len:
	.zero	4
	.globl	sm3_loop_len
	.align 4
	.type	sm3_loop_len, @object
	.size	sm3_loop_len, 4
sm3_loop_len:
	.zero	4
	.globl	_x_sm3_loop_len
	.align 4
	.type	_x_sm3_loop_len, @object
	.size	_x_sm3_loop_len, 4
_x_sm3_loop_len:
	.zero	4
	.globl	sm3_l
	.align 4
	.type	sm3_l, @object
	.size	sm3_l, 4
sm3_l:
	.zero	4
	.globl	_x_sm3_l
	.align 4
	.type	_x_sm3_l, @object
	.size	_x_sm3_l, 4
_x_sm3_l:
	.zero	4
	.globl	sm1_state
	.type	sm1_state, @object
	.size	sm1_state, 1
sm1_state:
	.zero	1
	.globl	_x_sm1_state
	.type	_x_sm1_state, @object
	.size	_x_sm1_state, 1
_x_sm1_state:
	.zero	1
	.globl	sm4_l
	.align 4
	.type	sm4_l, @object
	.size	sm4_l, 4
sm4_l:
	.zero	4
	.globl	_x_sm4_l
	.align 4
	.type	_x_sm4_l, @object
	.size	_x_sm4_l, 4
_x_sm4_l:
	.zero	4
	.globl	sm0_state
	.type	sm0_state, @object
	.size	sm0_state, 1
sm0_state:
	.zero	1
	.globl	_x_sm0_state
	.type	_x_sm0_state, @object
	.size	_x_sm0_state, 1
_x_sm0_state:
	.zero	1
	.globl	sm2_state
	.type	sm2_state, @object
	.size	sm2_state, 1
sm2_state:
	.zero	1
	.globl	_x_sm2_state
	.type	_x_sm2_state, @object
	.size	_x_sm2_state, 1
_x_sm2_state:
	.zero	1
	.globl	sm0_l
	.align 4
	.type	sm0_l, @object
	.size	sm0_l, 4
sm0_l:
	.zero	4
	.globl	_x_sm0_l
	.align 4
	.type	_x_sm0_l, @object
	.size	_x_sm0_l, 4
_x_sm0_l:
	.zero	4
	.globl	sm2_l
	.align 4
	.type	sm2_l, @object
	.size	sm2_l, 4
sm2_l:
	.zero	4
	.globl	_x_sm2_l
	.align 4
	.type	_x_sm2_l, @object
	.size	_x_sm2_l, 4
_x_sm2_l:
	.zero	4
	.text
	.globl	main
	.type	main, @function
main:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR sm6_loop_len[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR sm6_state[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR sm5_loop_len[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR sm5_state[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR sm4_loop_len[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR sm6_l[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR sm4_state[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR run[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR sm5_l[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR sm3_state[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR sm1_l[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR semaphore[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR sm1_loop_len[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR sm2_loop_len[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR sm0_loop_len[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR sm3_loop_len[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR sm3_l[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR sm1_state[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR sm4_l[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR sm0_state[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR sm2_state[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR sm0_l[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR sm2_l[rip], eax
	mov	eax, DWORD PTR semaphore[rip]
	test	eax, eax
	jne	.L4
	movzx	eax, BYTE PTR sm0_state[rip]
	test	al, al
	je	.L4
	mov	eax, DWORD PTR sm0_loop_len[rip]
	test	eax, eax
	jle	.L4
	mov	eax, DWORD PTR sm0_l[rip]
	test	eax, eax
	jne	.L4
	movzx	eax, BYTE PTR sm1_state[rip]
	test	al, al
	je	.L4
	mov	eax, DWORD PTR sm1_loop_len[rip]
	test	eax, eax
	jle	.L4
	mov	eax, DWORD PTR sm1_l[rip]
	test	eax, eax
	jne	.L4
	movzx	eax, BYTE PTR sm2_state[rip]
	test	al, al
	je	.L4
	mov	eax, DWORD PTR sm2_loop_len[rip]
	test	eax, eax
	jle	.L4
	mov	eax, DWORD PTR sm2_l[rip]
	test	eax, eax
	jne	.L4
	movzx	eax, BYTE PTR sm3_state[rip]
	test	al, al
	je	.L4
	mov	eax, DWORD PTR sm3_loop_len[rip]
	test	eax, eax
	jle	.L4
	mov	eax, DWORD PTR sm3_l[rip]
	test	eax, eax
	jne	.L4
	movzx	eax, BYTE PTR sm4_state[rip]
	test	al, al
	je	.L4
	mov	eax, DWORD PTR sm4_loop_len[rip]
	test	eax, eax
	jle	.L4
	mov	eax, DWORD PTR sm4_l[rip]
	test	eax, eax
	jne	.L4
	movzx	eax, BYTE PTR sm5_state[rip]
	test	al, al
	je	.L4
	mov	eax, DWORD PTR sm5_loop_len[rip]
	test	eax, eax
	jle	.L4
	mov	eax, DWORD PTR sm5_l[rip]
	test	eax, eax
	jne	.L4
	movzx	eax, BYTE PTR sm6_state[rip]
	test	al, al
	je	.L4
	mov	eax, DWORD PTR sm6_loop_len[rip]
	test	eax, eax
	jle	.L4
	mov	eax, DWORD PTR sm6_l[rip]
	test	eax, eax
	jne	.L4
	mov	eax, 1
	jmp	.L5
.L4:
	mov	eax, 0
.L5:
	mov	DWORD PTR -4[rbp], eax
	jmp	.L6
.L87:
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_sm6_loop_len[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_sm6_state[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_sm5_loop_len[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_sm5_state[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_sm4_loop_len[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_sm6_l[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_sm4_state[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_run[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_sm5_l[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_sm3_state[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_sm1_l[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_semaphore[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_sm1_loop_len[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_sm2_loop_len[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_sm0_loop_len[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_sm3_loop_len[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_sm3_l[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_sm1_state[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_sm4_l[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_sm0_state[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_sm2_state[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_sm0_l[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_sm2_l[rip], eax
	mov	eax, DWORD PTR _x_semaphore[rip]
	test	eax, eax
	je	.L7
	mov	eax, DWORD PTR semaphore[rip]
	cmp	eax, 7
	je	.L8
.L7:
	mov	eax, DWORD PTR sm0_l[rip]
	test	eax, eax
	jne	.L9
	mov	edx, DWORD PTR _x_sm0_loop_len[rip]
	mov	eax, DWORD PTR sm0_loop_len[rip]
	cmp	edx, eax
	jg	.L10
.L9:
	movzx	eax, BYTE PTR _x_sm0_state[rip]
	test	al, al
	je	.L10
	movzx	eax, BYTE PTR sm0_state[rip]
	test	al, al
	je	.L8
.L10:
	movzx	eax, BYTE PTR _x_sm0_state[rip]
	test	al, al
	je	.L11
	movzx	eax, BYTE PTR sm0_state[rip]
	test	al, al
	je	.L12
.L11:
	mov	edx, DWORD PTR sm0_loop_len[rip]
	mov	eax, DWORD PTR _x_sm0_loop_len[rip]
	cmp	edx, eax
	jne	.L8
.L12:
	movzx	eax, BYTE PTR sm0_state[rip]
	test	al, al
	je	.L13
	mov	eax, DWORD PTR sm0_l[rip]
	mov	edx, DWORD PTR _x_sm0_l[rip]
	sub	eax, edx
	cmp	eax, 1
	jne	.L8
.L13:
	movzx	eax, BYTE PTR _x_sm0_state[rip]
	test	al, al
	jne	.L14
	movzx	eax, BYTE PTR sm0_state[rip]
	test	al, al
	je	.L14
	mov	edx, DWORD PTR sm0_loop_len[rip]
	mov	eax, DWORD PTR sm0_l[rip]
	cmp	edx, eax
	jg	.L8
.L14:
	movzx	eax, BYTE PTR _x_sm0_state[rip]
	test	al, al
	jne	.L15
	mov	eax, DWORD PTR semaphore[rip]
	cmp	eax, 7
	jne	.L15
	mov	eax, DWORD PTR _x_semaphore[rip]
	test	eax, eax
	jne	.L15
	movzx	eax, BYTE PTR sm0_state[rip]
	test	al, al
	je	.L8
.L15:
	movzx	eax, BYTE PTR sm0_state[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_sm0_state[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	jne	.L16
	mov	eax, DWORD PTR semaphore[rip]
	cmp	eax, 7
	jne	.L17
	mov	eax, DWORD PTR _x_semaphore[rip]
	test	eax, eax
	jne	.L17
	movzx	eax, BYTE PTR sm0_state[rip]
	test	al, al
	je	.L16
.L17:
	mov	eax, DWORD PTR run[rip]
	test	eax, eax
	jne	.L8
.L16:
	mov	edx, DWORD PTR semaphore[rip]
	mov	eax, DWORD PTR _x_semaphore[rip]
	cmp	edx, eax
	je	.L18
	mov	eax, DWORD PTR run[rip]
	test	eax, eax
	jne	.L18
	movzx	eax, BYTE PTR sm0_state[rip]
	test	al, al
	setne	dl
	movzx	eax, BYTE PTR _x_sm0_state[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L8
.L18:
	mov	eax, DWORD PTR semaphore[rip]
	mov	edx, DWORD PTR _x_semaphore[rip]
	sub	eax, edx
	cmp	eax, -1
	je	.L19
	movzx	eax, BYTE PTR _x_sm0_state[rip]
	test	al, al
	jne	.L19
	mov	eax, DWORD PTR run[rip]
	test	eax, eax
	jne	.L19
	movzx	eax, BYTE PTR sm0_state[rip]
	test	al, al
	jne	.L8
.L19:
	mov	eax, DWORD PTR sm1_l[rip]
	test	eax, eax
	jne	.L20
	mov	edx, DWORD PTR _x_sm1_loop_len[rip]
	mov	eax, DWORD PTR sm1_loop_len[rip]
	cmp	edx, eax
	jg	.L21
.L20:
	movzx	eax, BYTE PTR _x_sm1_state[rip]
	test	al, al
	je	.L21
	movzx	eax, BYTE PTR sm1_state[rip]
	test	al, al
	je	.L8
.L21:
	movzx	eax, BYTE PTR _x_sm1_state[rip]
	test	al, al
	je	.L22
	movzx	eax, BYTE PTR sm1_state[rip]
	test	al, al
	je	.L23
.L22:
	mov	edx, DWORD PTR sm1_loop_len[rip]
	mov	eax, DWORD PTR _x_sm1_loop_len[rip]
	cmp	edx, eax
	jne	.L8
.L23:
	movzx	eax, BYTE PTR sm1_state[rip]
	test	al, al
	je	.L24
	mov	eax, DWORD PTR sm1_l[rip]
	mov	edx, DWORD PTR _x_sm1_l[rip]
	sub	eax, edx
	cmp	eax, 1
	jne	.L8
.L24:
	movzx	eax, BYTE PTR _x_sm1_state[rip]
	test	al, al
	jne	.L25
	movzx	eax, BYTE PTR sm1_state[rip]
	test	al, al
	je	.L25
	mov	edx, DWORD PTR sm1_loop_len[rip]
	mov	eax, DWORD PTR sm1_l[rip]
	cmp	edx, eax
	jg	.L8
.L25:
	movzx	eax, BYTE PTR _x_sm1_state[rip]
	test	al, al
	jne	.L26
	mov	eax, DWORD PTR semaphore[rip]
	cmp	eax, 7
	jne	.L26
	mov	eax, DWORD PTR _x_semaphore[rip]
	test	eax, eax
	jne	.L26
	movzx	eax, BYTE PTR sm1_state[rip]
	test	al, al
	je	.L8
.L26:
	movzx	eax, BYTE PTR sm1_state[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_sm1_state[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	jne	.L27
	mov	eax, DWORD PTR semaphore[rip]
	cmp	eax, 7
	jne	.L28
	mov	eax, DWORD PTR _x_semaphore[rip]
	test	eax, eax
	jne	.L28
	movzx	eax, BYTE PTR sm1_state[rip]
	test	al, al
	je	.L27
.L28:
	mov	eax, DWORD PTR run[rip]
	cmp	eax, 1
	jne	.L8
.L27:
	mov	edx, DWORD PTR semaphore[rip]
	mov	eax, DWORD PTR _x_semaphore[rip]
	cmp	edx, eax
	je	.L29
	mov	eax, DWORD PTR run[rip]
	cmp	eax, 1
	jne	.L29
	movzx	eax, BYTE PTR sm1_state[rip]
	test	al, al
	setne	dl
	movzx	eax, BYTE PTR _x_sm1_state[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L8
.L29:
	mov	eax, DWORD PTR semaphore[rip]
	mov	edx, DWORD PTR _x_semaphore[rip]
	sub	eax, edx
	cmp	eax, -1
	je	.L30
	movzx	eax, BYTE PTR _x_sm1_state[rip]
	test	al, al
	jne	.L30
	mov	eax, DWORD PTR run[rip]
	cmp	eax, 1
	jne	.L30
	movzx	eax, BYTE PTR sm1_state[rip]
	test	al, al
	jne	.L8
.L30:
	mov	eax, DWORD PTR sm2_l[rip]
	test	eax, eax
	jne	.L31
	mov	edx, DWORD PTR _x_sm2_loop_len[rip]
	mov	eax, DWORD PTR sm2_loop_len[rip]
	cmp	edx, eax
	jg	.L32
.L31:
	movzx	eax, BYTE PTR _x_sm2_state[rip]
	test	al, al
	je	.L32
	movzx	eax, BYTE PTR sm2_state[rip]
	test	al, al
	je	.L8
.L32:
	movzx	eax, BYTE PTR _x_sm2_state[rip]
	test	al, al
	je	.L33
	movzx	eax, BYTE PTR sm2_state[rip]
	test	al, al
	je	.L34
.L33:
	mov	edx, DWORD PTR sm2_loop_len[rip]
	mov	eax, DWORD PTR _x_sm2_loop_len[rip]
	cmp	edx, eax
	jne	.L8
.L34:
	movzx	eax, BYTE PTR sm2_state[rip]
	test	al, al
	je	.L35
	mov	eax, DWORD PTR sm2_l[rip]
	mov	edx, DWORD PTR _x_sm2_l[rip]
	sub	eax, edx
	cmp	eax, 1
	jne	.L8
.L35:
	movzx	eax, BYTE PTR _x_sm2_state[rip]
	test	al, al
	jne	.L36
	movzx	eax, BYTE PTR sm2_state[rip]
	test	al, al
	je	.L36
	mov	edx, DWORD PTR sm2_loop_len[rip]
	mov	eax, DWORD PTR sm2_l[rip]
	cmp	edx, eax
	jg	.L8
.L36:
	movzx	eax, BYTE PTR _x_sm2_state[rip]
	test	al, al
	jne	.L37
	mov	eax, DWORD PTR semaphore[rip]
	cmp	eax, 7
	jne	.L37
	mov	eax, DWORD PTR _x_semaphore[rip]
	test	eax, eax
	jne	.L37
	movzx	eax, BYTE PTR sm2_state[rip]
	test	al, al
	je	.L8
.L37:
	movzx	eax, BYTE PTR sm2_state[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_sm2_state[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	jne	.L38
	mov	eax, DWORD PTR semaphore[rip]
	cmp	eax, 7
	jne	.L39
	mov	eax, DWORD PTR _x_semaphore[rip]
	test	eax, eax
	jne	.L39
	movzx	eax, BYTE PTR sm2_state[rip]
	test	al, al
	je	.L38
.L39:
	mov	eax, DWORD PTR run[rip]
	cmp	eax, 2
	jne	.L8
.L38:
	mov	edx, DWORD PTR semaphore[rip]
	mov	eax, DWORD PTR _x_semaphore[rip]
	cmp	edx, eax
	je	.L40
	mov	eax, DWORD PTR run[rip]
	cmp	eax, 2
	jne	.L40
	movzx	eax, BYTE PTR sm2_state[rip]
	test	al, al
	setne	dl
	movzx	eax, BYTE PTR _x_sm2_state[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L8
.L40:
	mov	eax, DWORD PTR semaphore[rip]
	mov	edx, DWORD PTR _x_semaphore[rip]
	sub	eax, edx
	cmp	eax, -1
	je	.L41
	movzx	eax, BYTE PTR _x_sm2_state[rip]
	test	al, al
	jne	.L41
	mov	eax, DWORD PTR run[rip]
	cmp	eax, 2
	jne	.L41
	movzx	eax, BYTE PTR sm2_state[rip]
	test	al, al
	jne	.L8
.L41:
	mov	eax, DWORD PTR sm3_l[rip]
	test	eax, eax
	jne	.L42
	mov	edx, DWORD PTR _x_sm3_loop_len[rip]
	mov	eax, DWORD PTR sm3_loop_len[rip]
	cmp	edx, eax
	jg	.L43
.L42:
	movzx	eax, BYTE PTR _x_sm3_state[rip]
	test	al, al
	je	.L43
	movzx	eax, BYTE PTR sm3_state[rip]
	test	al, al
	je	.L8
.L43:
	movzx	eax, BYTE PTR _x_sm3_state[rip]
	test	al, al
	je	.L44
	movzx	eax, BYTE PTR sm3_state[rip]
	test	al, al
	je	.L45
.L44:
	mov	edx, DWORD PTR sm3_loop_len[rip]
	mov	eax, DWORD PTR _x_sm3_loop_len[rip]
	cmp	edx, eax
	jne	.L8
.L45:
	movzx	eax, BYTE PTR sm3_state[rip]
	test	al, al
	je	.L46
	mov	eax, DWORD PTR sm3_l[rip]
	mov	edx, DWORD PTR _x_sm3_l[rip]
	sub	eax, edx
	cmp	eax, 1
	jne	.L8
.L46:
	movzx	eax, BYTE PTR _x_sm3_state[rip]
	test	al, al
	jne	.L47
	movzx	eax, BYTE PTR sm3_state[rip]
	test	al, al
	je	.L47
	mov	edx, DWORD PTR sm3_loop_len[rip]
	mov	eax, DWORD PTR sm3_l[rip]
	cmp	edx, eax
	jg	.L8
.L47:
	movzx	eax, BYTE PTR _x_sm3_state[rip]
	test	al, al
	jne	.L48
	mov	eax, DWORD PTR semaphore[rip]
	cmp	eax, 7
	jne	.L48
	mov	eax, DWORD PTR _x_semaphore[rip]
	test	eax, eax
	jne	.L48
	movzx	eax, BYTE PTR sm3_state[rip]
	test	al, al
	je	.L8
.L48:
	movzx	eax, BYTE PTR sm3_state[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_sm3_state[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	jne	.L49
	mov	eax, DWORD PTR semaphore[rip]
	cmp	eax, 7
	jne	.L50
	mov	eax, DWORD PTR _x_semaphore[rip]
	test	eax, eax
	jne	.L50
	movzx	eax, BYTE PTR sm3_state[rip]
	test	al, al
	je	.L49
.L50:
	mov	eax, DWORD PTR run[rip]
	cmp	eax, 3
	jne	.L8
.L49:
	mov	edx, DWORD PTR semaphore[rip]
	mov	eax, DWORD PTR _x_semaphore[rip]
	cmp	edx, eax
	je	.L51
	mov	eax, DWORD PTR run[rip]
	cmp	eax, 3
	jne	.L51
	movzx	eax, BYTE PTR sm3_state[rip]
	test	al, al
	setne	dl
	movzx	eax, BYTE PTR _x_sm3_state[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L8
.L51:
	mov	eax, DWORD PTR semaphore[rip]
	mov	edx, DWORD PTR _x_semaphore[rip]
	sub	eax, edx
	cmp	eax, -1
	je	.L52
	movzx	eax, BYTE PTR _x_sm3_state[rip]
	test	al, al
	jne	.L52
	mov	eax, DWORD PTR run[rip]
	cmp	eax, 3
	jne	.L52
	movzx	eax, BYTE PTR sm3_state[rip]
	test	al, al
	jne	.L8
.L52:
	mov	eax, DWORD PTR sm4_l[rip]
	test	eax, eax
	jne	.L53
	mov	edx, DWORD PTR _x_sm4_loop_len[rip]
	mov	eax, DWORD PTR sm4_loop_len[rip]
	cmp	edx, eax
	jg	.L54
.L53:
	movzx	eax, BYTE PTR _x_sm4_state[rip]
	test	al, al
	je	.L54
	movzx	eax, BYTE PTR sm4_state[rip]
	test	al, al
	je	.L8
.L54:
	movzx	eax, BYTE PTR _x_sm4_state[rip]
	test	al, al
	je	.L55
	movzx	eax, BYTE PTR sm4_state[rip]
	test	al, al
	je	.L56
.L55:
	mov	edx, DWORD PTR sm4_loop_len[rip]
	mov	eax, DWORD PTR _x_sm4_loop_len[rip]
	cmp	edx, eax
	jne	.L8
.L56:
	movzx	eax, BYTE PTR sm4_state[rip]
	test	al, al
	je	.L57
	mov	eax, DWORD PTR sm4_l[rip]
	mov	edx, DWORD PTR _x_sm4_l[rip]
	sub	eax, edx
	cmp	eax, 1
	jne	.L8
.L57:
	movzx	eax, BYTE PTR _x_sm4_state[rip]
	test	al, al
	jne	.L58
	movzx	eax, BYTE PTR sm4_state[rip]
	test	al, al
	je	.L58
	mov	edx, DWORD PTR sm4_loop_len[rip]
	mov	eax, DWORD PTR sm4_l[rip]
	cmp	edx, eax
	jg	.L8
.L58:
	movzx	eax, BYTE PTR _x_sm4_state[rip]
	test	al, al
	jne	.L59
	mov	eax, DWORD PTR semaphore[rip]
	cmp	eax, 7
	jne	.L59
	mov	eax, DWORD PTR _x_semaphore[rip]
	test	eax, eax
	jne	.L59
	movzx	eax, BYTE PTR sm4_state[rip]
	test	al, al
	je	.L8
.L59:
	movzx	eax, BYTE PTR sm4_state[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_sm4_state[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	jne	.L60
	mov	eax, DWORD PTR semaphore[rip]
	cmp	eax, 7
	jne	.L61
	mov	eax, DWORD PTR _x_semaphore[rip]
	test	eax, eax
	jne	.L61
	movzx	eax, BYTE PTR sm4_state[rip]
	test	al, al
	je	.L60
.L61:
	mov	eax, DWORD PTR run[rip]
	cmp	eax, 4
	jne	.L8
.L60:
	mov	edx, DWORD PTR semaphore[rip]
	mov	eax, DWORD PTR _x_semaphore[rip]
	cmp	edx, eax
	je	.L62
	mov	eax, DWORD PTR run[rip]
	cmp	eax, 4
	jne	.L62
	movzx	eax, BYTE PTR sm4_state[rip]
	test	al, al
	setne	dl
	movzx	eax, BYTE PTR _x_sm4_state[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L8
.L62:
	mov	eax, DWORD PTR semaphore[rip]
	mov	edx, DWORD PTR _x_semaphore[rip]
	sub	eax, edx
	cmp	eax, -1
	je	.L63
	movzx	eax, BYTE PTR _x_sm4_state[rip]
	test	al, al
	jne	.L63
	mov	eax, DWORD PTR run[rip]
	cmp	eax, 4
	jne	.L63
	movzx	eax, BYTE PTR sm4_state[rip]
	test	al, al
	jne	.L8
.L63:
	mov	eax, DWORD PTR sm5_l[rip]
	test	eax, eax
	jne	.L64
	mov	edx, DWORD PTR _x_sm5_loop_len[rip]
	mov	eax, DWORD PTR sm5_loop_len[rip]
	cmp	edx, eax
	jg	.L65
.L64:
	movzx	eax, BYTE PTR _x_sm5_state[rip]
	test	al, al
	je	.L65
	movzx	eax, BYTE PTR sm5_state[rip]
	test	al, al
	je	.L8
.L65:
	movzx	eax, BYTE PTR _x_sm5_state[rip]
	test	al, al
	je	.L66
	movzx	eax, BYTE PTR sm5_state[rip]
	test	al, al
	je	.L67
.L66:
	mov	edx, DWORD PTR sm5_loop_len[rip]
	mov	eax, DWORD PTR _x_sm5_loop_len[rip]
	cmp	edx, eax
	jne	.L8
.L67:
	movzx	eax, BYTE PTR sm5_state[rip]
	test	al, al
	je	.L68
	mov	eax, DWORD PTR sm5_l[rip]
	mov	edx, DWORD PTR _x_sm5_l[rip]
	sub	eax, edx
	cmp	eax, 1
	jne	.L8
.L68:
	movzx	eax, BYTE PTR _x_sm5_state[rip]
	test	al, al
	jne	.L69
	movzx	eax, BYTE PTR sm5_state[rip]
	test	al, al
	je	.L69
	mov	edx, DWORD PTR sm5_loop_len[rip]
	mov	eax, DWORD PTR sm5_l[rip]
	cmp	edx, eax
	jg	.L8
.L69:
	movzx	eax, BYTE PTR _x_sm5_state[rip]
	test	al, al
	jne	.L70
	mov	eax, DWORD PTR semaphore[rip]
	cmp	eax, 7
	jne	.L70
	mov	eax, DWORD PTR _x_semaphore[rip]
	test	eax, eax
	jne	.L70
	movzx	eax, BYTE PTR sm5_state[rip]
	test	al, al
	je	.L8
.L70:
	movzx	eax, BYTE PTR sm5_state[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_sm5_state[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	jne	.L71
	mov	eax, DWORD PTR semaphore[rip]
	cmp	eax, 7
	jne	.L72
	mov	eax, DWORD PTR _x_semaphore[rip]
	test	eax, eax
	jne	.L72
	movzx	eax, BYTE PTR sm5_state[rip]
	test	al, al
	je	.L71
.L72:
	mov	eax, DWORD PTR run[rip]
	cmp	eax, 5
	jne	.L8
.L71:
	mov	edx, DWORD PTR semaphore[rip]
	mov	eax, DWORD PTR _x_semaphore[rip]
	cmp	edx, eax
	je	.L73
	mov	eax, DWORD PTR run[rip]
	cmp	eax, 5
	jne	.L73
	movzx	eax, BYTE PTR sm5_state[rip]
	test	al, al
	setne	dl
	movzx	eax, BYTE PTR _x_sm5_state[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L8
.L73:
	mov	eax, DWORD PTR semaphore[rip]
	mov	edx, DWORD PTR _x_semaphore[rip]
	sub	eax, edx
	cmp	eax, -1
	je	.L74
	movzx	eax, BYTE PTR _x_sm5_state[rip]
	test	al, al
	jne	.L74
	mov	eax, DWORD PTR run[rip]
	cmp	eax, 5
	jne	.L74
	movzx	eax, BYTE PTR sm5_state[rip]
	test	al, al
	jne	.L8
.L74:
	mov	eax, DWORD PTR sm6_l[rip]
	test	eax, eax
	jne	.L75
	mov	edx, DWORD PTR _x_sm6_loop_len[rip]
	mov	eax, DWORD PTR sm6_loop_len[rip]
	cmp	edx, eax
	jg	.L76
.L75:
	movzx	eax, BYTE PTR _x_sm6_state[rip]
	test	al, al
	je	.L76
	movzx	eax, BYTE PTR sm6_state[rip]
	test	al, al
	je	.L8
.L76:
	movzx	eax, BYTE PTR _x_sm6_state[rip]
	test	al, al
	je	.L77
	movzx	eax, BYTE PTR sm6_state[rip]
	test	al, al
	je	.L78
.L77:
	mov	edx, DWORD PTR sm6_loop_len[rip]
	mov	eax, DWORD PTR _x_sm6_loop_len[rip]
	cmp	edx, eax
	jne	.L8
.L78:
	movzx	eax, BYTE PTR sm6_state[rip]
	test	al, al
	je	.L79
	mov	eax, DWORD PTR sm6_l[rip]
	mov	edx, DWORD PTR _x_sm6_l[rip]
	sub	eax, edx
	cmp	eax, 1
	jne	.L8
.L79:
	movzx	eax, BYTE PTR _x_sm6_state[rip]
	test	al, al
	jne	.L80
	movzx	eax, BYTE PTR sm6_state[rip]
	test	al, al
	je	.L80
	mov	edx, DWORD PTR sm6_loop_len[rip]
	mov	eax, DWORD PTR sm6_l[rip]
	cmp	edx, eax
	jg	.L8
.L80:
	movzx	eax, BYTE PTR _x_sm6_state[rip]
	test	al, al
	jne	.L81
	mov	eax, DWORD PTR semaphore[rip]
	cmp	eax, 7
	jne	.L81
	mov	eax, DWORD PTR _x_semaphore[rip]
	test	eax, eax
	jne	.L81
	movzx	eax, BYTE PTR sm6_state[rip]
	test	al, al
	je	.L8
.L81:
	movzx	eax, BYTE PTR sm6_state[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_sm6_state[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	jne	.L82
	mov	eax, DWORD PTR semaphore[rip]
	cmp	eax, 7
	jne	.L83
	mov	eax, DWORD PTR _x_semaphore[rip]
	test	eax, eax
	jne	.L83
	movzx	eax, BYTE PTR sm6_state[rip]
	test	al, al
	je	.L82
.L83:
	mov	eax, DWORD PTR run[rip]
	cmp	eax, 6
	jne	.L8
.L82:
	mov	edx, DWORD PTR semaphore[rip]
	mov	eax, DWORD PTR _x_semaphore[rip]
	cmp	edx, eax
	je	.L84
	mov	eax, DWORD PTR run[rip]
	cmp	eax, 6
	jne	.L84
	movzx	eax, BYTE PTR sm6_state[rip]
	test	al, al
	setne	dl
	movzx	eax, BYTE PTR _x_sm6_state[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L8
.L84:
	mov	eax, DWORD PTR semaphore[rip]
	mov	edx, DWORD PTR _x_semaphore[rip]
	sub	eax, edx
	cmp	eax, -1
	je	.L85
	movzx	eax, BYTE PTR _x_sm6_state[rip]
	test	al, al
	jne	.L85
	mov	eax, DWORD PTR run[rip]
	cmp	eax, 6
	jne	.L85
	movzx	eax, BYTE PTR sm6_state[rip]
	test	al, al
	jne	.L8
.L85:
	mov	eax, 1
	jmp	.L86
.L8:
	mov	eax, 0
.L86:
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR _x_sm6_loop_len[rip]
	mov	DWORD PTR sm6_loop_len[rip], eax
	movzx	eax, BYTE PTR _x_sm6_state[rip]
	mov	BYTE PTR sm6_state[rip], al
	mov	eax, DWORD PTR _x_sm5_loop_len[rip]
	mov	DWORD PTR sm5_loop_len[rip], eax
	movzx	eax, BYTE PTR _x_sm5_state[rip]
	mov	BYTE PTR sm5_state[rip], al
	mov	eax, DWORD PTR _x_sm4_loop_len[rip]
	mov	DWORD PTR sm4_loop_len[rip], eax
	mov	eax, DWORD PTR _x_sm6_l[rip]
	mov	DWORD PTR sm6_l[rip], eax
	movzx	eax, BYTE PTR _x_sm4_state[rip]
	mov	BYTE PTR sm4_state[rip], al
	mov	eax, DWORD PTR _x_run[rip]
	mov	DWORD PTR run[rip], eax
	mov	eax, DWORD PTR _x_sm5_l[rip]
	mov	DWORD PTR sm5_l[rip], eax
	movzx	eax, BYTE PTR _x_sm3_state[rip]
	mov	BYTE PTR sm3_state[rip], al
	mov	eax, DWORD PTR _x_sm1_l[rip]
	mov	DWORD PTR sm1_l[rip], eax
	mov	eax, DWORD PTR _x_semaphore[rip]
	mov	DWORD PTR semaphore[rip], eax
	mov	eax, DWORD PTR _x_sm1_loop_len[rip]
	mov	DWORD PTR sm1_loop_len[rip], eax
	mov	eax, DWORD PTR _x_sm2_loop_len[rip]
	mov	DWORD PTR sm2_loop_len[rip], eax
	mov	eax, DWORD PTR _x_sm0_loop_len[rip]
	mov	DWORD PTR sm0_loop_len[rip], eax
	mov	eax, DWORD PTR _x_sm3_loop_len[rip]
	mov	DWORD PTR sm3_loop_len[rip], eax
	mov	eax, DWORD PTR _x_sm3_l[rip]
	mov	DWORD PTR sm3_l[rip], eax
	movzx	eax, BYTE PTR _x_sm1_state[rip]
	mov	BYTE PTR sm1_state[rip], al
	mov	eax, DWORD PTR _x_sm4_l[rip]
	mov	DWORD PTR sm4_l[rip], eax
	movzx	eax, BYTE PTR _x_sm0_state[rip]
	mov	BYTE PTR sm0_state[rip], al
	movzx	eax, BYTE PTR _x_sm2_state[rip]
	mov	BYTE PTR sm2_state[rip], al
	mov	eax, DWORD PTR _x_sm0_l[rip]
	mov	DWORD PTR sm0_l[rip], eax
	mov	eax, DWORD PTR _x_sm2_l[rip]
	mov	DWORD PTR sm2_l[rip], eax
.L6:
	cmp	DWORD PTR -4[rbp], 0
	jne	.L87
	mov	eax, 0
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	main, .-main
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"586534.c"
	.text
	.align	2
	.global	__VERIFIER_nondet_bool
	.syntax unified
	.arm
	.fpu softvfp
	.type	__VERIFIER_nondet_bool, %function
__VERIFIER_nondet_bool:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	mov	r0, r3
	pop	{fp, pc}
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.comm	sm6_loop_len,4,4
	.comm	_x_sm6_loop_len,4,4
	.comm	sm6_state,1,1
	.comm	_x_sm6_state,1,1
	.comm	sm5_loop_len,4,4
	.comm	_x_sm5_loop_len,4,4
	.comm	sm5_state,1,1
	.comm	_x_sm5_state,1,1
	.comm	sm4_loop_len,4,4
	.comm	_x_sm4_loop_len,4,4
	.comm	sm6_l,4,4
	.comm	_x_sm6_l,4,4
	.comm	sm4_state,1,1
	.comm	_x_sm4_state,1,1
	.comm	run,4,4
	.comm	_x_run,4,4
	.comm	sm5_l,4,4
	.comm	_x_sm5_l,4,4
	.comm	sm3_state,1,1
	.comm	_x_sm3_state,1,1
	.comm	sm1_l,4,4
	.comm	_x_sm1_l,4,4
	.comm	semaphore,4,4
	.comm	_x_semaphore,4,4
	.comm	sm1_loop_len,4,4
	.comm	_x_sm1_loop_len,4,4
	.comm	sm2_loop_len,4,4
	.comm	_x_sm2_loop_len,4,4
	.comm	sm0_loop_len,4,4
	.comm	_x_sm0_loop_len,4,4
	.comm	sm3_loop_len,4,4
	.comm	_x_sm3_loop_len,4,4
	.comm	sm3_l,4,4
	.comm	_x_sm3_l,4,4
	.comm	sm1_state,1,1
	.comm	_x_sm1_state,1,1
	.comm	sm4_l,4,4
	.comm	_x_sm4_l,4,4
	.comm	sm0_state,1,1
	.comm	_x_sm0_state,1,1
	.comm	sm2_state,1,1
	.comm	_x_sm2_state,1,1
	.comm	sm0_l,4,4
	.comm	_x_sm0_l,4,4
	.comm	sm2_l,4,4
	.comm	_x_sm2_l,4,4
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+176
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L89
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+140
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L89+164
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+116
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+168
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L89+128
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+160
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+144
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L89+104
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+48
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+148
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+44
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+68
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+20
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+92
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+96
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L89+56
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+120
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L89+32
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L89+80
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+24
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+72
	str	r3, [r2]
	ldr	r3, .L89+148
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L89+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L89+20
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L4
	ldr	r3, .L89+24
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L89+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L89+44
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L4
	ldr	r3, .L89+48
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L89+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L89+68
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L4
	ldr	r3, .L89+72
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L89+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L89+92
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L4
	ldr	r3, .L89+96
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L89+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L89+116
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L4
	ldr	r3, .L89+120
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L89+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L89+140
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L4
	ldr	r3, .L89+144
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L89
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L89+176
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L4
	ldr	r3, .L89+168
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L4
	mov	r3, #1
	b	.L5
.L4:
	mov	r3, #0
.L5:
	str	r3, [fp, #-8]
	b	.L6
.L90:
	.align	2
.L89:
	.word	sm6_state
	.word	_x_sm6_l
	.word	_x_run
	.word	_x_sm0_loop_len
	.word	_x_sm0_l
	.word	sm0_loop_len
	.word	sm0_l
	.word	_x_sm0_state
	.word	sm0_state
	.word	_x_sm1_loop_len
	.word	_x_sm1_l
	.word	sm1_loop_len
	.word	sm1_l
	.word	_x_sm1_state
	.word	sm1_state
	.word	_x_sm2_loop_len
	.word	_x_sm2_l
	.word	sm2_loop_len
	.word	sm2_l
	.word	_x_sm2_state
	.word	sm2_state
	.word	_x_sm3_loop_len
	.word	_x_sm3_l
	.word	sm3_loop_len
	.word	sm3_l
	.word	_x_sm3_state
	.word	sm3_state
	.word	_x_sm4_loop_len
	.word	_x_sm4_l
	.word	sm4_loop_len
	.word	sm4_l
	.word	_x_sm4_state
	.word	sm4_state
	.word	_x_sm5_loop_len
	.word	_x_sm5_l
	.word	sm5_loop_len
	.word	sm5_l
	.word	semaphore
	.word	_x_semaphore
	.word	_x_sm5_state
	.word	run
	.word	sm5_state
	.word	sm6_l
	.word	_x_sm6_loop_len
	.word	sm6_loop_len
	.word	_x_sm6_state
.L87:
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+172
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L89+180
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+132
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L89+156
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+108
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+4
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L89+124
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+8
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+136
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L89+100
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+40
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+152
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+36
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+60
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+12
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+84
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+88
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L89+52
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+112
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L89+28
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L89+76
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+16
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L89+64
	str	r3, [r2]
	ldr	r3, .L89+152
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L7
	ldr	r3, .L89+148
	ldr	r3, [r3]
	cmp	r3, #7
	beq	.L8
.L7:
	ldr	r3, .L89+24
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L9
	ldr	r3, .L89+12
	ldr	r2, [r3]
	ldr	r3, .L89+20
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L10
.L9:
	ldr	r3, .L89+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L10
	ldr	r3, .L89+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L10:
	ldr	r3, .L89+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L11
	ldr	r3, .L89+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L12
.L11:
	ldr	r3, .L89+20
	ldr	r2, [r3]
	ldr	r3, .L89+12
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L8
.L12:
	ldr	r3, .L89+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L13
	ldr	r3, .L89+24
	ldr	r2, [r3]
	ldr	r3, .L89+16
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmp	r3, #1
	bne	.L8
.L13:
	ldr	r3, .L89+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L14
	ldr	r3, .L89+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L14
	ldr	r3, .L89+20
	ldr	r2, [r3]
	ldr	r3, .L89+24
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L8
.L14:
	ldr	r3, .L89+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L15
	ldr	r3, .L89+148
	ldr	r3, [r3]
	cmp	r3, #7
	bne	.L15
	ldr	r3, .L89+152
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L15
	ldr	r3, .L89+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L15:
	ldr	r3, .L89+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L89+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L16
	ldr	r3, .L89+148
	ldr	r3, [r3]
	cmp	r3, #7
	bne	.L17
	ldr	r3, .L89+152
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L17
	ldr	r3, .L89+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L16
.L17:
	ldr	r3, .L89+160
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L8
.L16:
	ldr	r3, .L89+148
	ldr	r2, [r3]
	ldr	r3, .L89+152
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L18
	ldr	r3, .L89+160
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L18
	ldr	r3, .L89+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r2, r3, #255
	ldr	r3, .L89+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L8
.L18:
	ldr	r3, .L89+148
	ldr	r2, [r3]
	ldr	r3, .L89+152
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmn	r3, #1
	beq	.L19
	ldr	r3, .L89+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L19
	ldr	r3, .L89+160
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L19
	ldr	r3, .L89+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
.L19:
	ldr	r3, .L89+48
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L20
	ldr	r3, .L89+36
	ldr	r2, [r3]
	ldr	r3, .L89+44
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L21
.L20:
	ldr	r3, .L89+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L21
	ldr	r3, .L89+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L21:
	ldr	r3, .L89+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L22
	ldr	r3, .L89+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L23
.L22:
	ldr	r3, .L89+44
	ldr	r2, [r3]
	ldr	r3, .L89+36
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L8
.L23:
	ldr	r3, .L89+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L24
	ldr	r3, .L89+48
	ldr	r2, [r3]
	ldr	r3, .L89+40
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmp	r3, #1
	bne	.L8
.L24:
	ldr	r3, .L89+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L25
	ldr	r3, .L89+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L25
	ldr	r3, .L89+44
	ldr	r2, [r3]
	ldr	r3, .L89+48
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L8
.L25:
	ldr	r3, .L89+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L26
	ldr	r3, .L89+148
	ldr	r3, [r3]
	cmp	r3, #7
	bne	.L26
	ldr	r3, .L89+152
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L26
	ldr	r3, .L89+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L26:
	ldr	r3, .L89+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L89+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L27
	ldr	r3, .L89+148
	ldr	r3, [r3]
	cmp	r3, #7
	bne	.L28
	ldr	r3, .L89+152
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L28
	ldr	r3, .L89+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L27
.L28:
	ldr	r3, .L89+160
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L8
.L27:
	ldr	r3, .L89+148
	ldr	r2, [r3]
	ldr	r3, .L89+152
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L29
	ldr	r3, .L89+160
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L29
	ldr	r3, .L89+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r2, r3, #255
	ldr	r3, .L89+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L8
.L29:
	ldr	r3, .L89+148
	ldr	r2, [r3]
	ldr	r3, .L89+152
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmn	r3, #1
	beq	.L30
	ldr	r3, .L89+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L30
	ldr	r3, .L89+160
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L30
	ldr	r3, .L89+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
.L30:
	ldr	r3, .L89+72
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L31
	ldr	r3, .L89+60
	ldr	r2, [r3]
	ldr	r3, .L89+68
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L32
.L31:
	ldr	r3, .L89+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L32
	ldr	r3, .L89+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L32:
	ldr	r3, .L89+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L33
	ldr	r3, .L89+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L34
.L33:
	ldr	r3, .L89+68
	ldr	r2, [r3]
	ldr	r3, .L89+60
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L8
.L34:
	ldr	r3, .L89+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
	ldr	r3, .L89+72
	ldr	r2, [r3]
	ldr	r3, .L89+64
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmp	r3, #1
	bne	.L8
.L35:
	ldr	r3, .L89+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L36
	ldr	r3, .L89+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L36
	ldr	r3, .L89+68
	ldr	r2, [r3]
	ldr	r3, .L89+72
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L8
.L36:
	ldr	r3, .L89+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L37
	ldr	r3, .L89+148
	ldr	r3, [r3]
	cmp	r3, #7
	bne	.L37
	ldr	r3, .L89+152
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L37
	ldr	r3, .L89+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L37:
	ldr	r3, .L89+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L89+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L38
	ldr	r3, .L89+148
	ldr	r3, [r3]
	cmp	r3, #7
	bne	.L39
	ldr	r3, .L89+152
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L39
	ldr	r3, .L89+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L38
.L39:
	ldr	r3, .L89+160
	ldr	r3, [r3]
	cmp	r3, #2
	bne	.L8
.L38:
	ldr	r3, .L89+148
	ldr	r2, [r3]
	ldr	r3, .L89+152
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L40
	ldr	r3, .L89+160
	ldr	r3, [r3]
	cmp	r3, #2
	bne	.L40
	ldr	r3, .L89+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r2, r3, #255
	ldr	r3, .L89+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L8
.L40:
	ldr	r3, .L89+148
	ldr	r2, [r3]
	ldr	r3, .L89+152
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmn	r3, #1
	beq	.L41
	ldr	r3, .L89+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L41
	ldr	r3, .L89+160
	ldr	r3, [r3]
	cmp	r3, #2
	bne	.L41
	ldr	r3, .L89+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
.L41:
	ldr	r3, .L89+96
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L42
	ldr	r3, .L89+84
	ldr	r2, [r3]
	ldr	r3, .L89+92
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L43
.L42:
	ldr	r3, .L89+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L43
	ldr	r3, .L89+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L43:
	ldr	r3, .L89+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L44
	ldr	r3, .L89+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L45
.L44:
	ldr	r3, .L89+92
	ldr	r2, [r3]
	ldr	r3, .L89+84
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L8
.L45:
	ldr	r3, .L89+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L46
	ldr	r3, .L89+96
	ldr	r2, [r3]
	ldr	r3, .L89+88
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmp	r3, #1
	bne	.L8
.L46:
	ldr	r3, .L89+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L47
	ldr	r3, .L89+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L47
	ldr	r3, .L89+92
	ldr	r2, [r3]
	ldr	r3, .L89+96
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L8
.L47:
	ldr	r3, .L89+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L48
	ldr	r3, .L89+148
	ldr	r3, [r3]
	cmp	r3, #7
	bne	.L48
	ldr	r3, .L89+152
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L48
	ldr	r3, .L89+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L48:
	ldr	r3, .L89+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L89+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L49
	ldr	r3, .L89+148
	ldr	r3, [r3]
	cmp	r3, #7
	bne	.L50
	ldr	r3, .L89+152
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L50
	ldr	r3, .L89+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L49
.L50:
	ldr	r3, .L89+160
	ldr	r3, [r3]
	cmp	r3, #3
	bne	.L8
.L49:
	ldr	r3, .L89+148
	ldr	r2, [r3]
	ldr	r3, .L89+152
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L51
	ldr	r3, .L89+160
	ldr	r3, [r3]
	cmp	r3, #3
	bne	.L51
	ldr	r3, .L89+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r2, r3, #255
	ldr	r3, .L89+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L8
.L51:
	ldr	r3, .L89+148
	ldr	r2, [r3]
	ldr	r3, .L89+152
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmn	r3, #1
	beq	.L52
	ldr	r3, .L89+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L52
	ldr	r3, .L89+160
	ldr	r3, [r3]
	cmp	r3, #3
	bne	.L52
	ldr	r3, .L89+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
.L52:
	ldr	r3, .L89+120
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L53
	ldr	r3, .L89+108
	ldr	r2, [r3]
	ldr	r3, .L89+116
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L54
.L53:
	ldr	r3, .L89+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L54
	ldr	r3, .L89+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L54:
	ldr	r3, .L89+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L55
	ldr	r3, .L89+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L56
.L55:
	ldr	r3, .L89+116
	ldr	r2, [r3]
	ldr	r3, .L89+108
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L8
.L56:
	ldr	r3, .L89+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L57
	ldr	r3, .L89+120
	ldr	r2, [r3]
	ldr	r3, .L89+112
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmp	r3, #1
	bne	.L8
.L57:
	ldr	r3, .L89+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L58
	ldr	r3, .L89+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L58
	ldr	r3, .L89+116
	ldr	r2, [r3]
	ldr	r3, .L89+120
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L8
.L58:
	ldr	r3, .L89+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L89+148
	ldr	r3, [r3]
	cmp	r3, #7
	bne	.L59
	ldr	r3, .L89+152
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L89+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L59:
	ldr	r3, .L89+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L89+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L60
	ldr	r3, .L89+148
	ldr	r3, [r3]
	cmp	r3, #7
	bne	.L61
	ldr	r3, .L89+152
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L89+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L60
.L61:
	ldr	r3, .L89+160
	ldr	r3, [r3]
	cmp	r3, #4
	bne	.L8
.L60:
	ldr	r3, .L89+148
	ldr	r2, [r3]
	ldr	r3, .L89+152
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L62
	ldr	r3, .L89+160
	ldr	r3, [r3]
	cmp	r3, #4
	bne	.L62
	ldr	r3, .L89+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r2, r3, #255
	ldr	r3, .L89+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L8
.L62:
	ldr	r3, .L89+148
	ldr	r2, [r3]
	ldr	r3, .L89+152
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmn	r3, #1
	beq	.L63
	ldr	r3, .L89+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L89+160
	ldr	r3, [r3]
	cmp	r3, #4
	bne	.L63
	ldr	r3, .L89+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
.L63:
	ldr	r3, .L89+144
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L64
	ldr	r3, .L89+132
	ldr	r2, [r3]
	ldr	r3, .L89+140
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L65
.L64:
	ldr	r3, .L89+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L65
	ldr	r3, .L89+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L65:
	ldr	r3, .L89+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L66
	ldr	r3, .L89+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L67
.L66:
	ldr	r3, .L89+140
	ldr	r2, [r3]
	ldr	r3, .L89+132
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L8
.L67:
	ldr	r3, .L89+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L68
	ldr	r3, .L89+144
	ldr	r2, [r3]
	ldr	r3, .L89+136
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmp	r3, #1
	bne	.L8
.L68:
	ldr	r3, .L89+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L69
	ldr	r3, .L89+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L69
	ldr	r3, .L89+140
	ldr	r2, [r3]
	ldr	r3, .L89+144
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L8
.L69:
	ldr	r3, .L89+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L70
	ldr	r3, .L89+148
	ldr	r3, [r3]
	cmp	r3, #7
	bne	.L70
	ldr	r3, .L89+152
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L70
	ldr	r3, .L89+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L70:
	ldr	r3, .L89+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L89+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L71
	ldr	r3, .L89+148
	ldr	r3, [r3]
	cmp	r3, #7
	bne	.L72
	ldr	r3, .L89+152
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L72
	ldr	r3, .L89+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L71
.L72:
	ldr	r3, .L89+160
	ldr	r3, [r3]
	cmp	r3, #5
	bne	.L8
.L71:
	ldr	r3, .L89+148
	ldr	r2, [r3]
	ldr	r3, .L89+152
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L73
	ldr	r3, .L89+160
	ldr	r3, [r3]
	cmp	r3, #5
	bne	.L73
	ldr	r3, .L89+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r2, r3, #255
	ldr	r3, .L89+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L8
.L73:
	ldr	r3, .L89+148
	ldr	r2, [r3]
	ldr	r3, .L89+152
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmn	r3, #1
	beq	.L74
	ldr	r3, .L89+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L74
	ldr	r3, .L89+160
	ldr	r3, [r3]
	cmp	r3, #5
	bne	.L74
	ldr	r3, .L89+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
.L74:
	ldr	r3, .L89+168
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L75
	ldr	r3, .L89+172
	ldr	r2, [r3]
	ldr	r3, .L89+176
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L76
.L75:
	ldr	r3, .L89+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L76
	ldr	r3, .L91
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L76:
	ldr	r3, .L91+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L77
	ldr	r3, .L91
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L78
.L77:
	ldr	r3, .L91+8
	ldr	r2, [r3]
	ldr	r3, .L91+12
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L8
.L78:
	ldr	r3, .L91
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L79
	ldr	r3, .L91+16
	ldr	r2, [r3]
	ldr	r3, .L91+20
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmp	r3, #1
	bne	.L8
.L79:
	ldr	r3, .L91+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L80
	ldr	r3, .L91
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L80
	ldr	r3, .L91+8
	ldr	r2, [r3]
	ldr	r3, .L91+16
	ldr	r3, [r3]
	cmp	r2, r3
	bgt	.L8
.L80:
	ldr	r3, .L91+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L81
	ldr	r3, .L91+24
	ldr	r3, [r3]
	cmp	r3, #7
	bne	.L81
	ldr	r3, .L91+28
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L81
	ldr	r3, .L91
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L81:
	ldr	r3, .L91
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L91+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L82
	ldr	r3, .L91+24
	ldr	r3, [r3]
	cmp	r3, #7
	bne	.L83
	ldr	r3, .L91+28
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L83
	ldr	r3, .L91
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L82
.L83:
	ldr	r3, .L91+32
	ldr	r3, [r3]
	cmp	r3, #6
	bne	.L8
.L82:
	ldr	r3, .L91+24
	ldr	r2, [r3]
	ldr	r3, .L91+28
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L84
	ldr	r3, .L91+32
	ldr	r3, [r3]
	cmp	r3, #6
	bne	.L84
	ldr	r3, .L91
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r2, r3, #255
	ldr	r3, .L91+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L8
.L84:
	ldr	r3, .L91+24
	ldr	r2, [r3]
	ldr	r3, .L91+28
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmn	r3, #1
	beq	.L85
	ldr	r3, .L91+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L85
	ldr	r3, .L91+32
	ldr	r3, [r3]
	cmp	r3, #6
	bne	.L85
	ldr	r3, .L91
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
.L85:
	mov	r3, #1
	b	.L86
.L8:
	mov	r3, #0
.L86:
	str	r3, [fp, #-8]
	ldr	r3, .L91+12
	ldr	r3, [r3]
	ldr	r2, .L91+8
	str	r3, [r2]
	ldr	r3, .L91+4
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L91
	strb	r2, [r3]
	ldr	r3, .L91+36
	ldr	r3, [r3]
	ldr	r2, .L91+40
	str	r3, [r2]
	ldr	r3, .L91+44
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L91+48
	strb	r2, [r3]
	ldr	r3, .L91+52
	ldr	r3, [r3]
	ldr	r2, .L91+56
	str	r3, [r2]
	ldr	r3, .L91+20
	ldr	r3, [r3]
	ldr	r2, .L91+16
	str	r3, [r2]
	ldr	r3, .L91+60
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L91+64
	strb	r2, [r3]
	ldr	r3, .L91+68
	ldr	r3, [r3]
	ldr	r2, .L91+32
	str	r3, [r2]
	ldr	r3, .L91+72
	ldr	r3, [r3]
	ldr	r2, .L91+76
	str	r3, [r2]
	ldr	r3, .L91+80
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L91+84
	strb	r2, [r3]
	ldr	r3, .L91+88
	ldr	r3, [r3]
	ldr	r2, .L91+92
	str	r3, [r2]
	ldr	r3, .L91+28
	ldr	r3, [r3]
	ldr	r2, .L91+24
	str	r3, [r2]
	ldr	r3, .L91+96
	ldr	r3, [r3]
	ldr	r2, .L91+100
	str	r3, [r2]
	ldr	r3, .L91+104
	ldr	r3, [r3]
	ldr	r2, .L91+108
	str	r3, [r2]
	ldr	r3, .L91+112
	ldr	r3, [r3]
	ldr	r2, .L91+116
	str	r3, [r2]
	ldr	r3, .L91+120
	ldr	r3, [r3]
	ldr	r2, .L91+124
	str	r3, [r2]
	ldr	r3, .L91+128
	ldr	r3, [r3]
	ldr	r2, .L91+132
	str	r3, [r2]
	ldr	r3, .L91+136
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L91+140
	strb	r2, [r3]
	ldr	r3, .L91+144
	ldr	r3, [r3]
	ldr	r2, .L91+148
	str	r3, [r2]
	ldr	r3, .L91+152
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L91+156
	strb	r2, [r3]
	ldr	r3, .L91+160
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L91+164
	strb	r2, [r3]
	ldr	r3, .L91+168
	ldr	r3, [r3]
	ldr	r2, .L91+172
	str	r3, [r2]
	ldr	r3, .L91+176
	ldr	r3, [r3]
	ldr	r2, .L91+180
	str	r3, [r2]
.L6:
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	bne	.L87
	mov	r3, #0
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L92:
	.align	2
.L91:
	.word	sm6_state
	.word	_x_sm6_state
	.word	sm6_loop_len
	.word	_x_sm6_loop_len
	.word	sm6_l
	.word	_x_sm6_l
	.word	semaphore
	.word	_x_semaphore
	.word	run
	.word	_x_sm5_loop_len
	.word	sm5_loop_len
	.word	_x_sm5_state
	.word	sm5_state
	.word	_x_sm4_loop_len
	.word	sm4_loop_len
	.word	_x_sm4_state
	.word	sm4_state
	.word	_x_run
	.word	_x_sm5_l
	.word	sm5_l
	.word	_x_sm3_state
	.word	sm3_state
	.word	_x_sm1_l
	.word	sm1_l
	.word	_x_sm1_loop_len
	.word	sm1_loop_len
	.word	_x_sm2_loop_len
	.word	sm2_loop_len
	.word	_x_sm0_loop_len
	.word	sm0_loop_len
	.word	_x_sm3_loop_len
	.word	sm3_loop_len
	.word	_x_sm3_l
	.word	sm3_l
	.word	_x_sm1_state
	.word	sm1_state
	.word	_x_sm4_l
	.word	sm4_l
	.word	_x_sm0_state
	.word	sm0_state
	.word	_x_sm2_state
	.word	sm2_state
	.word	_x_sm0_l
	.word	sm0_l
	.word	_x_sm2_l
	.word	sm2_l
	.size	main, .-main
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
