	.file	"998923.c"
	.intel_syntax noprefix
	.text
	.globl	BUF_SWAP_32BIT
	.bss
	.align 4
	.type	BUF_SWAP_32BIT, @object
	.size	BUF_SWAP_32BIT, 4
BUF_SWAP_32BIT:
	.zero	4
	.globl	CAYMAN_RING_TYPE_CP1_INDEX
	.align 4
	.type	CAYMAN_RING_TYPE_CP1_INDEX, @object
	.size	CAYMAN_RING_TYPE_CP1_INDEX, 4
CAYMAN_RING_TYPE_CP1_INDEX:
	.zero	4
	.globl	CAYMAN_RING_TYPE_CP2_INDEX
	.align 4
	.type	CAYMAN_RING_TYPE_CP2_INDEX, @object
	.size	CAYMAN_RING_TYPE_CP2_INDEX, 4
CAYMAN_RING_TYPE_CP2_INDEX:
	.zero	4
	.globl	CIK_WB_CP1_WPTR_OFFSET
	.align 4
	.type	CIK_WB_CP1_WPTR_OFFSET, @object
	.size	CIK_WB_CP1_WPTR_OFFSET, 4
CIK_WB_CP1_WPTR_OFFSET:
	.zero	4
	.globl	CIK_WB_CP2_WPTR_OFFSET
	.align 4
	.type	CIK_WB_CP2_WPTR_OFFSET, @object
	.size	CIK_WB_CP2_WPTR_OFFSET, 4
CIK_WB_CP2_WPTR_OFFSET:
	.zero	4
	.globl	CP_CPF_DEBUG
	.align 4
	.type	CP_CPF_DEBUG, @object
	.size	CP_CPF_DEBUG, 4
CP_CPF_DEBUG:
	.zero	4
	.globl	CP_HPD_EOP_BASE_ADDR
	.align 4
	.type	CP_HPD_EOP_BASE_ADDR, @object
	.size	CP_HPD_EOP_BASE_ADDR, 4
CP_HPD_EOP_BASE_ADDR:
	.zero	4
	.globl	CP_HPD_EOP_BASE_ADDR_HI
	.align 4
	.type	CP_HPD_EOP_BASE_ADDR_HI, @object
	.size	CP_HPD_EOP_BASE_ADDR_HI, 4
CP_HPD_EOP_BASE_ADDR_HI:
	.zero	4
	.globl	CP_HPD_EOP_CONTROL
	.align 4
	.type	CP_HPD_EOP_CONTROL, @object
	.size	CP_HPD_EOP_CONTROL, 4
CP_HPD_EOP_CONTROL:
	.zero	4
	.globl	CP_HPD_EOP_VMID
	.align 4
	.type	CP_HPD_EOP_VMID, @object
	.size	CP_HPD_EOP_VMID, 4
CP_HPD_EOP_VMID:
	.zero	4
	.globl	CP_HQD_ACTIVE
	.align 4
	.type	CP_HQD_ACTIVE, @object
	.size	CP_HQD_ACTIVE, 4
CP_HQD_ACTIVE:
	.zero	4
	.globl	CP_HQD_DEQUEUE_REQUEST
	.align 4
	.type	CP_HQD_DEQUEUE_REQUEST, @object
	.size	CP_HQD_DEQUEUE_REQUEST, 4
CP_HQD_DEQUEUE_REQUEST:
	.zero	4
	.globl	CP_HQD_PQ_BASE
	.align 4
	.type	CP_HQD_PQ_BASE, @object
	.size	CP_HQD_PQ_BASE, 4
CP_HQD_PQ_BASE:
	.zero	4
	.globl	CP_HQD_PQ_BASE_HI
	.align 4
	.type	CP_HQD_PQ_BASE_HI, @object
	.size	CP_HQD_PQ_BASE_HI, 4
CP_HQD_PQ_BASE_HI:
	.zero	4
	.globl	CP_HQD_PQ_CONTROL
	.align 4
	.type	CP_HQD_PQ_CONTROL, @object
	.size	CP_HQD_PQ_CONTROL, 4
CP_HQD_PQ_CONTROL:
	.zero	4
	.globl	CP_HQD_PQ_DOORBELL_CONTROL
	.align 4
	.type	CP_HQD_PQ_DOORBELL_CONTROL, @object
	.size	CP_HQD_PQ_DOORBELL_CONTROL, 4
CP_HQD_PQ_DOORBELL_CONTROL:
	.zero	4
	.globl	CP_HQD_PQ_RPTR
	.align 4
	.type	CP_HQD_PQ_RPTR, @object
	.size	CP_HQD_PQ_RPTR, 4
CP_HQD_PQ_RPTR:
	.zero	4
	.globl	CP_HQD_PQ_RPTR_REPORT_ADDR
	.align 4
	.type	CP_HQD_PQ_RPTR_REPORT_ADDR, @object
	.size	CP_HQD_PQ_RPTR_REPORT_ADDR, 4
CP_HQD_PQ_RPTR_REPORT_ADDR:
	.zero	4
	.globl	CP_HQD_PQ_RPTR_REPORT_ADDR_HI
	.align 4
	.type	CP_HQD_PQ_RPTR_REPORT_ADDR_HI, @object
	.size	CP_HQD_PQ_RPTR_REPORT_ADDR_HI, 4
CP_HQD_PQ_RPTR_REPORT_ADDR_HI:
	.zero	4
	.globl	CP_HQD_PQ_WPTR
	.align 4
	.type	CP_HQD_PQ_WPTR, @object
	.size	CP_HQD_PQ_WPTR, 4
CP_HQD_PQ_WPTR:
	.zero	4
	.globl	CP_HQD_PQ_WPTR_POLL_ADDR
	.align 4
	.type	CP_HQD_PQ_WPTR_POLL_ADDR, @object
	.size	CP_HQD_PQ_WPTR_POLL_ADDR, 4
CP_HQD_PQ_WPTR_POLL_ADDR:
	.zero	4
	.globl	CP_HQD_PQ_WPTR_POLL_ADDR_HI
	.align 4
	.type	CP_HQD_PQ_WPTR_POLL_ADDR_HI, @object
	.size	CP_HQD_PQ_WPTR_POLL_ADDR_HI, 4
CP_HQD_PQ_WPTR_POLL_ADDR_HI:
	.zero	4
	.globl	CP_HQD_VMID
	.align 4
	.type	CP_HQD_VMID, @object
	.size	CP_HQD_VMID, 4
CP_HQD_VMID:
	.zero	4
	.globl	CP_MQD_BASE_ADDR
	.align 4
	.type	CP_MQD_BASE_ADDR, @object
	.size	CP_MQD_BASE_ADDR, 4
CP_MQD_BASE_ADDR:
	.zero	4
	.globl	CP_MQD_BASE_ADDR_HI
	.align 4
	.type	CP_MQD_BASE_ADDR_HI, @object
	.size	CP_MQD_BASE_ADDR_HI, 4
CP_MQD_BASE_ADDR_HI:
	.zero	4
	.globl	CP_MQD_CONTROL
	.align 4
	.type	CP_MQD_CONTROL, @object
	.size	CP_MQD_CONTROL, 4
CP_MQD_CONTROL:
	.zero	4
	.globl	CP_PQ_WPTR_POLL_CNTL
	.align 4
	.type	CP_PQ_WPTR_POLL_CNTL, @object
	.size	CP_PQ_WPTR_POLL_CNTL, 4
CP_PQ_WPTR_POLL_CNTL:
	.zero	4
	.globl	DOORBELL_EN
	.align 4
	.type	DOORBELL_EN, @object
	.size	DOORBELL_EN, 4
DOORBELL_EN:
	.zero	4
	.globl	DOORBELL_HIT
	.align 4
	.type	DOORBELL_HIT, @object
	.size	DOORBELL_HIT, 4
DOORBELL_HIT:
	.zero	4
	.globl	DOORBELL_OFFSET_MASK
	.align 4
	.type	DOORBELL_OFFSET_MASK, @object
	.size	DOORBELL_OFFSET_MASK, 4
DOORBELL_OFFSET_MASK:
	.zero	4
	.globl	DOORBELL_SOURCE
	.align 4
	.type	DOORBELL_SOURCE, @object
	.size	DOORBELL_SOURCE, 4
DOORBELL_SOURCE:
	.zero	4
	.globl	EOP_SIZE_MASK
	.align 4
	.type	EOP_SIZE_MASK, @object
	.size	EOP_SIZE_MASK, 4
EOP_SIZE_MASK:
	.zero	4
	.globl	KMD_QUEUE
	.align 4
	.type	KMD_QUEUE, @object
	.size	KMD_QUEUE, 4
KMD_QUEUE:
	.zero	4
	.globl	MEC_HPD_SIZE
	.align 4
	.type	MEC_HPD_SIZE, @object
	.size	MEC_HPD_SIZE, 4
MEC_HPD_SIZE:
	.zero	4
	.globl	MQD_VMID_MASK
	.align 4
	.type	MQD_VMID_MASK, @object
	.size	MQD_VMID_MASK, 4
MQD_VMID_MASK:
	.zero	4
	.globl	PAGE_SIZE
	.align 4
	.type	PAGE_SIZE, @object
	.size	PAGE_SIZE, 4
PAGE_SIZE:
	.zero	4
	.globl	PQ_VOLATILE
	.align 4
	.type	PQ_VOLATILE, @object
	.size	PQ_VOLATILE, 4
PQ_VOLATILE:
	.zero	4
	.globl	PRIV_STATE
	.align 4
	.type	PRIV_STATE, @object
	.size	PRIV_STATE, 4
PRIV_STATE:
	.zero	4
	.globl	QUEUE_SIZE_MASK
	.align 4
	.type	QUEUE_SIZE_MASK, @object
	.size	QUEUE_SIZE_MASK, 4
QUEUE_SIZE_MASK:
	.zero	4
	.globl	RADEON_GEM_DOMAIN_GTT
	.align 4
	.type	RADEON_GEM_DOMAIN_GTT, @object
	.size	RADEON_GEM_DOMAIN_GTT, 4
RADEON_GEM_DOMAIN_GTT:
	.zero	4
	.globl	RADEON_GPU_PAGE_SIZE
	.align 4
	.type	RADEON_GPU_PAGE_SIZE, @object
	.size	RADEON_GPU_PAGE_SIZE, 4
RADEON_GPU_PAGE_SIZE:
	.zero	4
	.globl	RADEON_WB_CP1_RPTR_OFFSET
	.align 4
	.type	RADEON_WB_CP1_RPTR_OFFSET, @object
	.size	RADEON_WB_CP1_RPTR_OFFSET, 4
RADEON_WB_CP1_RPTR_OFFSET:
	.zero	4
	.globl	RADEON_WB_CP2_RPTR_OFFSET
	.align 4
	.type	RADEON_WB_CP2_RPTR_OFFSET, @object
	.size	RADEON_WB_CP2_RPTR_OFFSET, 4
RADEON_WB_CP2_RPTR_OFFSET:
	.zero	4
	.globl	ROQ_PQ_IB_FLIP
	.align 4
	.type	ROQ_PQ_IB_FLIP, @object
	.size	ROQ_PQ_IB_FLIP, 4
ROQ_PQ_IB_FLIP:
	.zero	4
	.globl	RPTR_BLOCK_SIZE_MASK
	.align 4
	.type	RPTR_BLOCK_SIZE_MASK, @object
	.size	RPTR_BLOCK_SIZE_MASK, 4
RPTR_BLOCK_SIZE_MASK:
	.zero	4
	.globl	UNORD_DISPATCH
	.align 4
	.type	UNORD_DISPATCH, @object
	.size	UNORD_DISPATCH, 4
UNORD_DISPATCH:
	.zero	4
	.globl	WPTR_POLL_EN
	.align 4
	.type	WPTR_POLL_EN, @object
	.size	WPTR_POLL_EN, 4
WPTR_POLL_EN:
	.zero	4
	.section	.rodata
.LC0:
	.string	"(%d) create MQD bo failed\n"
.LC1:
	.string	"(%d) pin MQD bo failed\n"
.LC2:
	.string	"(%d) map MQD bo failed\n"
	.text
	.type	cik_cp_compute_resume, @function
cik_cp_compute_resume:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 96
	mov	QWORD PTR -88[rbp], rdi
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -8[rbp], rax
	xor	eax, eax
	mov	DWORD PTR -52[rbp], 1
	mov	rax, QWORD PTR -88[rbp]
	mov	rdi, rax
	call	cik_cp_compute_start@PLT
	mov	DWORD PTR -48[rbp], eax
	cmp	DWORD PTR -48[rbp], 0
	je	.L2
	mov	eax, DWORD PTR -48[rbp]
	jmp	.L32
.L2:
	mov	eax, DWORD PTR CP_CPF_DEBUG[rip]
	mov	edi, eax
	call	RREG32@PLT
	mov	DWORD PTR -44[rbp], eax
	or	DWORD PTR -44[rbp], 8388608
	mov	eax, DWORD PTR CP_CPF_DEBUG[rip]
	mov	edx, DWORD PTR -44[rbp]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	mov	rax, QWORD PTR -88[rbp]
	add	rax, 16
	mov	rdi, rax
	call	mutex_lock@PLT
	mov	DWORD PTR -68[rbp], 0
	jmp	.L4
.L9:
	cmp	DWORD PTR -68[rbp], 3
	jg	.L5
	mov	eax, 1
	jmp	.L6
.L5:
	mov	eax, 2
.L6:
	mov	DWORD PTR -36[rbp], eax
	cmp	DWORD PTR -68[rbp], 3
	jle	.L7
	mov	eax, DWORD PTR -68[rbp]
	sub	eax, 4
	jmp	.L8
.L7:
	mov	eax, DWORD PTR -68[rbp]
.L8:
	mov	DWORD PTR -32[rbp], eax
	mov	edx, DWORD PTR -32[rbp]
	mov	esi, DWORD PTR -36[rbp]
	mov	rax, QWORD PTR -88[rbp]
	mov	r8d, 0
	mov	ecx, 0
	mov	rdi, rax
	call	cik_srbm_select@PLT
	mov	rax, QWORD PTR -88[rbp]
	mov	edx, DWORD PTR 36[rax]
	mov	eax, DWORD PTR MEC_HPD_SIZE[rip]
	imul	eax, DWORD PTR -68[rbp]
	add	eax, eax
	add	eax, edx
	mov	DWORD PTR -28[rbp], eax
	mov	eax, DWORD PTR -28[rbp]
	sar	eax, 8
	mov	edx, eax
	mov	eax, DWORD PTR CP_HPD_EOP_BASE_ADDR[rip]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	mov	eax, DWORD PTR -28[rbp]
	mov	edi, eax
	call	upper_32_bits@PLT
	sar	eax, 8
	mov	edx, eax
	mov	eax, DWORD PTR CP_HPD_EOP_BASE_ADDR_HI[rip]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	mov	eax, DWORD PTR CP_HPD_EOP_VMID[rip]
	mov	esi, 0
	mov	edi, eax
	call	WREG32@PLT
	mov	eax, DWORD PTR CP_HPD_EOP_CONTROL[rip]
	mov	edi, eax
	call	RREG32@PLT
	mov	DWORD PTR -44[rbp], eax
	mov	eax, DWORD PTR EOP_SIZE_MASK[rip]
	not	eax
	and	DWORD PTR -44[rbp], eax
	mov	eax, DWORD PTR MEC_HPD_SIZE[rip]
	lea	edx, 7[rax]
	test	eax, eax
	cmovs	eax, edx
	sar	eax, 3
	mov	edi, eax
	call	order_base_2@PLT
	or	DWORD PTR -44[rbp], eax
	mov	eax, DWORD PTR CP_HPD_EOP_CONTROL[rip]
	mov	edx, DWORD PTR -44[rbp]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	add	DWORD PTR -68[rbp], 1
.L4:
	mov	rax, QWORD PTR -88[rbp]
	mov	edx, DWORD PTR 28[rax]
	mov	rax, QWORD PTR -88[rbp]
	mov	eax, DWORD PTR 32[rax]
	imul	eax, edx
	cmp	DWORD PTR -68[rbp], eax
	jl	.L9
	mov	rax, QWORD PTR -88[rbp]
	mov	r8d, 0
	mov	ecx, 0
	mov	edx, 0
	mov	esi, 0
	mov	rdi, rax
	call	cik_srbm_select@PLT
	mov	rax, QWORD PTR -88[rbp]
	add	rax, 16
	mov	rdi, rax
	call	mutex_unlock@PLT
	mov	DWORD PTR -68[rbp], 0
	jmp	.L10
.L31:
	cmp	DWORD PTR -68[rbp], 0
	jne	.L11
	mov	eax, DWORD PTR CAYMAN_RING_TYPE_CP1_INDEX[rip]
	mov	DWORD PTR -60[rbp], eax
	jmp	.L12
.L11:
	mov	eax, DWORD PTR CAYMAN_RING_TYPE_CP2_INDEX[rip]
	mov	DWORD PTR -60[rbp], eax
.L12:
	mov	rax, QWORD PTR -88[rbp]
	mov	rcx, QWORD PTR 8[rax]
	mov	eax, DWORD PTR -60[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	sal	rax, 3
	add	rax, rcx
	mov	rax, QWORD PTR 24[rax]
	test	rax, rax
	jne	.L13
	mov	rax, QWORD PTR -88[rbp]
	mov	rcx, QWORD PTR 8[rax]
	mov	eax, DWORD PTR -60[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	sal	rax, 3
	add	rax, rcx
	lea	rcx, 24[rax]
	mov	esi, DWORD PTR RADEON_GEM_DOMAIN_GTT[rip]
	mov	edx, DWORD PTR PAGE_SIZE[rip]
	mov	rax, QWORD PTR -88[rbp]
	sub	rsp, 8
	push	rcx
	push	0
	push	0
	mov	r9d, 0
	mov	r8d, esi
	mov	ecx, 1
	mov	esi, 88
	mov	rdi, rax
	call	radeon_bo_create@PLT
	add	rsp, 32
	mov	DWORD PTR -48[rbp], eax
	cmp	DWORD PTR -48[rbp], 0
	je	.L13
	mov	rax, QWORD PTR -88[rbp]
	mov	eax, DWORD PTR 24[rax]
	mov	edx, DWORD PTR -48[rbp]
	lea	rsi, .LC0[rip]
	mov	edi, eax
	call	dev_warn@PLT
	mov	eax, DWORD PTR -48[rbp]
	jmp	.L32
.L13:
	mov	rax, QWORD PTR -88[rbp]
	mov	rcx, QWORD PTR 8[rax]
	mov	eax, DWORD PTR -60[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	sal	rax, 3
	add	rax, rcx
	mov	rax, QWORD PTR 24[rax]
	mov	esi, 0
	mov	rdi, rax
	call	radeon_bo_reserve@PLT
	mov	DWORD PTR -48[rbp], eax
	cmp	DWORD PTR -48[rbp], 0
	setne	al
	movzx	eax, al
	mov	edi, eax
	call	unlikely@PLT
	test	rax, rax
	je	.L14
	mov	rax, QWORD PTR -88[rbp]
	mov	rdi, rax
	call	cik_cp_compute_fini@PLT
	mov	eax, DWORD PTR -48[rbp]
	jmp	.L32
.L14:
	mov	ecx, DWORD PTR RADEON_GEM_DOMAIN_GTT[rip]
	mov	rax, QWORD PTR -88[rbp]
	mov	rsi, QWORD PTR 8[rax]
	mov	eax, DWORD PTR -60[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	sal	rax, 3
	add	rax, rsi
	mov	rax, QWORD PTR 24[rax]
	lea	rdx, -72[rbp]
	mov	esi, ecx
	mov	rdi, rax
	call	radeon_bo_pin@PLT
	mov	DWORD PTR -48[rbp], eax
	cmp	DWORD PTR -48[rbp], 0
	je	.L15
	mov	rax, QWORD PTR -88[rbp]
	mov	eax, DWORD PTR 24[rax]
	mov	edx, DWORD PTR -48[rbp]
	lea	rsi, .LC1[rip]
	mov	edi, eax
	call	dev_warn@PLT
	mov	rax, QWORD PTR -88[rbp]
	mov	rdi, rax
	call	cik_cp_compute_fini@PLT
	mov	eax, DWORD PTR -48[rbp]
	jmp	.L32
.L15:
	mov	rax, QWORD PTR -88[rbp]
	mov	rcx, QWORD PTR 8[rax]
	mov	eax, DWORD PTR -60[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	sal	rax, 3
	add	rax, rcx
	mov	rax, QWORD PTR 24[rax]
	lea	rdx, -24[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	radeon_bo_kmap@PLT
	mov	DWORD PTR -48[rbp], eax
	cmp	DWORD PTR -48[rbp], 0
	je	.L16
	mov	rax, QWORD PTR -88[rbp]
	mov	eax, DWORD PTR 24[rax]
	mov	edx, DWORD PTR -48[rbp]
	lea	rsi, .LC2[rip]
	mov	edi, eax
	call	dev_warn@PLT
	mov	rax, QWORD PTR -88[rbp]
	mov	rdi, rax
	call	cik_cp_compute_fini@PLT
	mov	eax, DWORD PTR -48[rbp]
	jmp	.L32
.L16:
	mov	rax, QWORD PTR -24[rbp]
	mov	edx, 88
	mov	esi, 0
	mov	rdi, rax
	call	memset@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	QWORD PTR -16[rbp], rax
	mov	rax, QWORD PTR -16[rbp]
	mov	DWORD PTR [rax], -1070528512
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	DWORD PTR [rax], -1
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 4
	mov	DWORD PTR [rax], -1
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR 16[rax]
	mov	DWORD PTR [rax], -1
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR 16[rax]
	add	rax, 4
	mov	DWORD PTR [rax], -1
	mov	rax, QWORD PTR -88[rbp]
	add	rax, 16
	mov	rdi, rax
	call	mutex_lock@PLT
	mov	rax, QWORD PTR -88[rbp]
	mov	rcx, QWORD PTR 8[rax]
	mov	eax, DWORD PTR -60[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	sal	rax, 3
	add	rax, rcx
	mov	ecx, DWORD PTR 36[rax]
	mov	rax, QWORD PTR -88[rbp]
	mov	rsi, QWORD PTR 8[rax]
	mov	eax, DWORD PTR -60[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	sal	rax, 3
	add	rax, rsi
	mov	edx, DWORD PTR 4[rax]
	mov	rax, QWORD PTR -88[rbp]
	mov	rdi, QWORD PTR 8[rax]
	mov	eax, DWORD PTR -60[rbp]
	movsx	rsi, eax
	mov	rax, rsi
	sal	rax, 2
	add	rax, rsi
	sal	rax, 3
	add	rax, rdi
	mov	esi, DWORD PTR [rax]
	mov	rax, QWORD PTR -88[rbp]
	mov	r8d, 0
	mov	rdi, rax
	call	cik_srbm_select@PLT
	mov	eax, DWORD PTR CP_PQ_WPTR_POLL_CNTL[rip]
	mov	edi, eax
	call	RREG32@PLT
	mov	DWORD PTR -44[rbp], eax
	mov	eax, DWORD PTR WPTR_POLL_EN[rip]
	not	eax
	and	DWORD PTR -44[rbp], eax
	mov	eax, DWORD PTR CP_PQ_WPTR_POLL_CNTL[rip]
	mov	edx, DWORD PTR -44[rbp]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	mov	eax, DWORD PTR CP_HQD_PQ_DOORBELL_CONTROL[rip]
	mov	edi, eax
	call	RREG32@PLT
	mov	rdx, QWORD PTR -16[rbp]
	mov	DWORD PTR 24[rdx], eax
	cmp	DWORD PTR -52[rbp], 0
	je	.L17
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR 24[rax]
	mov	eax, DWORD PTR DOORBELL_EN[rip]
	or	edx, eax
	mov	rax, QWORD PTR -16[rbp]
	mov	DWORD PTR 24[rax], edx
	jmp	.L18
.L17:
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR 24[rax]
	mov	eax, DWORD PTR DOORBELL_EN[rip]
	not	eax
	and	edx, eax
	mov	rax, QWORD PTR -16[rbp]
	mov	DWORD PTR 24[rax], edx
.L18:
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR 24[rax]
	mov	eax, DWORD PTR CP_HQD_PQ_DOORBELL_CONTROL[rip]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	mov	rax, QWORD PTR -16[rbp]
	mov	DWORD PTR 28[rax], 0
	mov	rax, QWORD PTR -16[rbp]
	mov	DWORD PTR 32[rax], 0
	mov	rax, QWORD PTR -16[rbp]
	mov	DWORD PTR 36[rax], 0
	mov	eax, DWORD PTR CP_HQD_ACTIVE[rip]
	mov	edi, eax
	call	RREG32@PLT
	and	eax, 1
	test	eax, eax
	je	.L19
	mov	eax, DWORD PTR CP_HQD_DEQUEUE_REQUEST[rip]
	mov	esi, 1
	mov	edi, eax
	call	WREG32@PLT
	mov	DWORD PTR -64[rbp], 0
	jmp	.L20
.L23:
	mov	eax, DWORD PTR CP_HQD_ACTIVE[rip]
	mov	edi, eax
	call	RREG32@PLT
	and	eax, 1
	test	eax, eax
	je	.L34
	mov	edi, 1
	call	udelay@PLT
	add	DWORD PTR -64[rbp], 1
.L20:
	mov	rax, QWORD PTR -88[rbp]
	mov	eax, DWORD PTR [rax]
	cmp	DWORD PTR -64[rbp], eax
	jl	.L23
	jmp	.L22
.L34:
	nop
.L22:
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR 28[rax]
	mov	eax, DWORD PTR CP_HQD_DEQUEUE_REQUEST[rip]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR 32[rax]
	mov	eax, DWORD PTR CP_HQD_PQ_RPTR[rip]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR 36[rax]
	mov	eax, DWORD PTR CP_HQD_PQ_WPTR[rip]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
.L19:
	mov	eax, DWORD PTR -72[rbp]
	and	eax, -4
	mov	edx, eax
	mov	rax, QWORD PTR -16[rbp]
	mov	DWORD PTR 40[rax], edx
	mov	eax, DWORD PTR -72[rbp]
	mov	edi, eax
	call	upper_32_bits@PLT
	mov	rdx, QWORD PTR -16[rbp]
	mov	DWORD PTR 44[rdx], eax
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR 40[rax]
	mov	eax, DWORD PTR CP_MQD_BASE_ADDR[rip]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR 44[rax]
	mov	eax, DWORD PTR CP_MQD_BASE_ADDR_HI[rip]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	mov	eax, DWORD PTR CP_MQD_CONTROL[rip]
	mov	edi, eax
	call	RREG32@PLT
	mov	rdx, QWORD PTR -16[rbp]
	mov	DWORD PTR 48[rdx], eax
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR 48[rax]
	mov	eax, DWORD PTR MQD_VMID_MASK[rip]
	not	eax
	and	edx, eax
	mov	rax, QWORD PTR -16[rbp]
	mov	DWORD PTR 48[rax], edx
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR 48[rax]
	mov	eax, DWORD PTR CP_MQD_CONTROL[rip]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	mov	rax, QWORD PTR -88[rbp]
	mov	rcx, QWORD PTR 8[rax]
	mov	eax, DWORD PTR -60[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	sal	rax, 3
	add	rax, rcx
	mov	eax, DWORD PTR 8[rax]
	sar	eax, 8
	mov	DWORD PTR -40[rbp], eax
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR -40[rbp]
	mov	DWORD PTR 52[rax], edx
	mov	eax, DWORD PTR -40[rbp]
	mov	edi, eax
	call	upper_32_bits@PLT
	mov	rdx, QWORD PTR -16[rbp]
	mov	DWORD PTR 56[rdx], eax
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR 52[rax]
	mov	eax, DWORD PTR CP_HQD_PQ_BASE[rip]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR 56[rax]
	mov	eax, DWORD PTR CP_HQD_PQ_BASE_HI[rip]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	mov	eax, DWORD PTR CP_HQD_PQ_CONTROL[rip]
	mov	edi, eax
	call	RREG32@PLT
	mov	rdx, QWORD PTR -16[rbp]
	mov	DWORD PTR 60[rdx], eax
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR 60[rax]
	mov	ecx, DWORD PTR QUEUE_SIZE_MASK[rip]
	mov	eax, DWORD PTR RPTR_BLOCK_SIZE_MASK[rip]
	or	eax, ecx
	not	eax
	and	edx, eax
	mov	rax, QWORD PTR -16[rbp]
	mov	DWORD PTR 60[rax], edx
	mov	rax, QWORD PTR -88[rbp]
	mov	rcx, QWORD PTR 8[rax]
	mov	eax, DWORD PTR -60[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	sal	rax, 3
	add	rax, rcx
	mov	eax, DWORD PTR 12[rax]
	lea	edx, 7[rax]
	test	eax, eax
	cmovs	eax, edx
	sar	eax, 3
	mov	edi, eax
	call	order_base_2@PLT
	mov	edx, eax
	mov	rax, QWORD PTR -16[rbp]
	mov	eax, DWORD PTR 60[rax]
	or	edx, eax
	mov	rax, QWORD PTR -16[rbp]
	mov	DWORD PTR 60[rax], edx
	mov	eax, DWORD PTR RADEON_GPU_PAGE_SIZE[rip]
	lea	edx, 7[rax]
	test	eax, eax
	cmovs	eax, edx
	sar	eax, 3
	mov	edi, eax
	call	order_base_2@PLT
	sal	eax, 8
	mov	edx, eax
	mov	rax, QWORD PTR -16[rbp]
	mov	eax, DWORD PTR 60[rax]
	or	edx, eax
	mov	rax, QWORD PTR -16[rbp]
	mov	DWORD PTR 60[rax], edx
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR 60[rax]
	mov	ecx, DWORD PTR UNORD_DISPATCH[rip]
	mov	eax, DWORD PTR ROQ_PQ_IB_FLIP[rip]
	or	ecx, eax
	mov	eax, DWORD PTR PQ_VOLATILE[rip]
	or	eax, ecx
	not	eax
	and	edx, eax
	mov	rax, QWORD PTR -16[rbp]
	mov	DWORD PTR 60[rax], edx
	mov	rax, QWORD PTR -16[rbp]
	mov	eax, DWORD PTR 60[rax]
	mov	ecx, DWORD PTR PRIV_STATE[rip]
	mov	edx, DWORD PTR KMD_QUEUE[rip]
	or	edx, ecx
	or	edx, eax
	mov	rax, QWORD PTR -16[rbp]
	mov	DWORD PTR 60[rax], edx
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR 60[rax]
	mov	eax, DWORD PTR CP_HQD_PQ_CONTROL[rip]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	cmp	DWORD PTR -68[rbp], 0
	jne	.L24
	mov	rax, QWORD PTR -88[rbp]
	mov	edx, DWORD PTR 20[rax]
	mov	eax, DWORD PTR CIK_WB_CP1_WPTR_OFFSET[rip]
	add	eax, edx
	mov	DWORD PTR -56[rbp], eax
	jmp	.L25
.L24:
	mov	rax, QWORD PTR -88[rbp]
	mov	edx, DWORD PTR 20[rax]
	mov	eax, DWORD PTR CIK_WB_CP2_WPTR_OFFSET[rip]
	add	eax, edx
	mov	DWORD PTR -56[rbp], eax
.L25:
	mov	eax, DWORD PTR -56[rbp]
	and	eax, -4
	mov	edx, eax
	mov	rax, QWORD PTR -16[rbp]
	mov	DWORD PTR 64[rax], edx
	mov	eax, DWORD PTR -56[rbp]
	mov	edi, eax
	call	upper_32_bits@PLT
	movzx	edx, ax
	mov	rax, QWORD PTR -16[rbp]
	mov	DWORD PTR 68[rax], edx
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR 64[rax]
	mov	eax, DWORD PTR CP_HQD_PQ_WPTR_POLL_ADDR[rip]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR 68[rax]
	mov	eax, DWORD PTR CP_HQD_PQ_WPTR_POLL_ADDR_HI[rip]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	cmp	DWORD PTR -68[rbp], 0
	jne	.L26
	mov	rax, QWORD PTR -88[rbp]
	mov	edx, DWORD PTR 20[rax]
	mov	eax, DWORD PTR RADEON_WB_CP1_RPTR_OFFSET[rip]
	add	eax, edx
	mov	DWORD PTR -56[rbp], eax
	jmp	.L27
.L26:
	mov	rax, QWORD PTR -88[rbp]
	mov	edx, DWORD PTR 20[rax]
	mov	eax, DWORD PTR RADEON_WB_CP2_RPTR_OFFSET[rip]
	add	eax, edx
	mov	DWORD PTR -56[rbp], eax
.L27:
	mov	eax, DWORD PTR -56[rbp]
	and	eax, -4
	mov	edx, eax
	mov	rax, QWORD PTR -16[rbp]
	mov	DWORD PTR 72[rax], edx
	mov	eax, DWORD PTR -56[rbp]
	mov	edi, eax
	call	upper_32_bits@PLT
	movzx	edx, ax
	mov	rax, QWORD PTR -16[rbp]
	mov	DWORD PTR 76[rax], edx
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR 72[rax]
	mov	eax, DWORD PTR CP_HQD_PQ_RPTR_REPORT_ADDR[rip]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR 76[rax]
	mov	eax, DWORD PTR CP_HQD_PQ_RPTR_REPORT_ADDR_HI[rip]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	cmp	DWORD PTR -52[rbp], 0
	je	.L28
	mov	eax, DWORD PTR CP_HQD_PQ_DOORBELL_CONTROL[rip]
	mov	edi, eax
	call	RREG32@PLT
	mov	rdx, QWORD PTR -16[rbp]
	mov	DWORD PTR 24[rdx], eax
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR 24[rax]
	mov	eax, DWORD PTR DOORBELL_OFFSET_MASK[rip]
	not	eax
	and	edx, eax
	mov	rax, QWORD PTR -16[rbp]
	mov	DWORD PTR 24[rax], edx
	mov	rax, QWORD PTR -88[rbp]
	mov	rcx, QWORD PTR 8[rax]
	mov	eax, DWORD PTR -60[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	sal	rax, 3
	add	rax, rcx
	mov	eax, DWORD PTR 32[rax]
	mov	edi, eax
	call	DOORBELL_OFFSET@PLT
	mov	edx, eax
	mov	rax, QWORD PTR -16[rbp]
	mov	eax, DWORD PTR 24[rax]
	or	edx, eax
	mov	rax, QWORD PTR -16[rbp]
	mov	DWORD PTR 24[rax], edx
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR 24[rax]
	mov	eax, DWORD PTR DOORBELL_EN[rip]
	or	edx, eax
	mov	rax, QWORD PTR -16[rbp]
	mov	DWORD PTR 24[rax], edx
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR 24[rax]
	mov	ecx, DWORD PTR DOORBELL_SOURCE[rip]
	mov	eax, DWORD PTR DOORBELL_HIT[rip]
	or	eax, ecx
	not	eax
	and	edx, eax
	mov	rax, QWORD PTR -16[rbp]
	mov	DWORD PTR 24[rax], edx
	jmp	.L29
.L28:
	mov	rax, QWORD PTR -16[rbp]
	mov	DWORD PTR 24[rax], 0
.L29:
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR 24[rax]
	mov	eax, DWORD PTR CP_HQD_PQ_DOORBELL_CONTROL[rip]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	mov	rax, QWORD PTR -88[rbp]
	mov	rcx, QWORD PTR 8[rax]
	mov	eax, DWORD PTR -60[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	sal	rax, 3
	add	rax, rcx
	mov	DWORD PTR 16[rax], 0
	mov	rax, QWORD PTR -88[rbp]
	mov	rcx, QWORD PTR 8[rax]
	mov	eax, DWORD PTR -60[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	sal	rax, 3
	add	rax, rcx
	mov	edx, DWORD PTR 16[rax]
	mov	rax, QWORD PTR -16[rbp]
	mov	DWORD PTR 36[rax], edx
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR 36[rax]
	mov	eax, DWORD PTR CP_HQD_PQ_WPTR[rip]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	mov	eax, DWORD PTR CP_HQD_PQ_RPTR[rip]
	mov	edi, eax
	call	RREG32@PLT
	mov	rdx, QWORD PTR -16[rbp]
	mov	DWORD PTR 32[rdx], eax
	mov	rax, QWORD PTR -16[rbp]
	mov	DWORD PTR 80[rax], 0
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR 80[rax]
	mov	eax, DWORD PTR CP_HQD_VMID[rip]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	mov	rax, QWORD PTR -16[rbp]
	mov	DWORD PTR 84[rax], 1
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR 84[rax]
	mov	eax, DWORD PTR CP_HQD_ACTIVE[rip]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	mov	rax, QWORD PTR -88[rbp]
	mov	r8d, 0
	mov	ecx, 0
	mov	edx, 0
	mov	esi, 0
	mov	rdi, rax
	call	cik_srbm_select@PLT
	mov	rax, QWORD PTR -88[rbp]
	add	rax, 16
	mov	rdi, rax
	call	mutex_unlock@PLT
	mov	rax, QWORD PTR -88[rbp]
	mov	rcx, QWORD PTR 8[rax]
	mov	eax, DWORD PTR -60[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	sal	rax, 3
	add	rax, rcx
	mov	rax, QWORD PTR 24[rax]
	mov	rdi, rax
	call	radeon_bo_kunmap@PLT
	mov	rax, QWORD PTR -88[rbp]
	mov	rcx, QWORD PTR 8[rax]
	mov	eax, DWORD PTR -60[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	sal	rax, 3
	add	rax, rcx
	mov	rax, QWORD PTR 24[rax]
	mov	rdi, rax
	call	radeon_bo_unreserve@PLT
	mov	rax, QWORD PTR -88[rbp]
	mov	rcx, QWORD PTR 8[rax]
	mov	eax, DWORD PTR -60[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	sal	rax, 3
	add	rax, rcx
	mov	DWORD PTR 20[rax], 1
	mov	rax, QWORD PTR -88[rbp]
	mov	rcx, QWORD PTR 8[rax]
	mov	eax, DWORD PTR -60[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	sal	rax, 3
	lea	rdx, [rcx+rax]
	mov	ecx, DWORD PTR -60[rbp]
	mov	rax, QWORD PTR -88[rbp]
	mov	esi, ecx
	mov	rdi, rax
	call	radeon_ring_test@PLT
	mov	DWORD PTR -48[rbp], eax
	cmp	DWORD PTR -48[rbp], 0
	je	.L30
	mov	rax, QWORD PTR -88[rbp]
	mov	rcx, QWORD PTR 8[rax]
	mov	eax, DWORD PTR -60[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	sal	rax, 3
	add	rax, rcx
	mov	DWORD PTR 20[rax], 0
.L30:
	add	DWORD PTR -68[rbp], 1
.L10:
	cmp	DWORD PTR -68[rbp], 1
	jle	.L31
	mov	eax, 0
.L32:
	mov	rsi, QWORD PTR -8[rbp]
	sub	rsi, QWORD PTR fs:40
	je	.L33
	call	__stack_chk_fail@PLT
.L33:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	cik_cp_compute_resume, .-cik_cp_compute_resume
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"998923.c"
	.text
	.comm	BUF_SWAP_32BIT,4,4
	.comm	CAYMAN_RING_TYPE_CP1_INDEX,4,4
	.comm	CAYMAN_RING_TYPE_CP2_INDEX,4,4
	.comm	CIK_WB_CP1_WPTR_OFFSET,4,4
	.comm	CIK_WB_CP2_WPTR_OFFSET,4,4
	.comm	CP_CPF_DEBUG,4,4
	.comm	CP_HPD_EOP_BASE_ADDR,4,4
	.comm	CP_HPD_EOP_BASE_ADDR_HI,4,4
	.comm	CP_HPD_EOP_CONTROL,4,4
	.comm	CP_HPD_EOP_VMID,4,4
	.comm	CP_HQD_ACTIVE,4,4
	.comm	CP_HQD_DEQUEUE_REQUEST,4,4
	.comm	CP_HQD_PQ_BASE,4,4
	.comm	CP_HQD_PQ_BASE_HI,4,4
	.comm	CP_HQD_PQ_CONTROL,4,4
	.comm	CP_HQD_PQ_DOORBELL_CONTROL,4,4
	.comm	CP_HQD_PQ_RPTR,4,4
	.comm	CP_HQD_PQ_RPTR_REPORT_ADDR,4,4
	.comm	CP_HQD_PQ_RPTR_REPORT_ADDR_HI,4,4
	.comm	CP_HQD_PQ_WPTR,4,4
	.comm	CP_HQD_PQ_WPTR_POLL_ADDR,4,4
	.comm	CP_HQD_PQ_WPTR_POLL_ADDR_HI,4,4
	.comm	CP_HQD_VMID,4,4
	.comm	CP_MQD_BASE_ADDR,4,4
	.comm	CP_MQD_BASE_ADDR_HI,4,4
	.comm	CP_MQD_CONTROL,4,4
	.comm	CP_PQ_WPTR_POLL_CNTL,4,4
	.comm	DOORBELL_EN,4,4
	.comm	DOORBELL_HIT,4,4
	.comm	DOORBELL_OFFSET_MASK,4,4
	.comm	DOORBELL_SOURCE,4,4
	.comm	EOP_SIZE_MASK,4,4
	.comm	KMD_QUEUE,4,4
	.comm	MEC_HPD_SIZE,4,4
	.comm	MQD_VMID_MASK,4,4
	.comm	PAGE_SIZE,4,4
	.comm	PQ_VOLATILE,4,4
	.comm	PRIV_STATE,4,4
	.comm	QUEUE_SIZE_MASK,4,4
	.comm	RADEON_GEM_DOMAIN_GTT,4,4
	.comm	RADEON_GPU_PAGE_SIZE,4,4
	.comm	RADEON_WB_CP1_RPTR_OFFSET,4,4
	.comm	RADEON_WB_CP2_RPTR_OFFSET,4,4
	.comm	ROQ_PQ_IB_FLIP,4,4
	.comm	RPTR_BLOCK_SIZE_MASK,4,4
	.comm	UNORD_DISPATCH,4,4
	.comm	WPTR_POLL_EN,4,4
	.section	.rodata
	.align	2
.LC0:
	.ascii	"(%d) create MQD bo failed\012\000"
	.align	2
.LC1:
	.ascii	"(%d) pin MQD bo failed\012\000"
	.align	2
.LC2:
	.ascii	"(%d) map MQD bo failed\012\000"
	.align	2
.LC3:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	cik_cp_compute_resume, %function
cik_cp_compute_resume:
	@ args = 0, pretend = 0, frame = 72
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, fp, lr}
	add	fp, sp, #8
	sub	sp, sp, #100
	str	r0, [fp, #-80]
	ldr	r3, .L35
	ldr	r3, [r3]
	str	r3, [fp, #-16]
	mov	r3,#0
	mov	r3, #1
	str	r3, [fp, #-48]
	ldr	r0, [fp, #-80]
	bl	cik_cp_compute_start
	str	r0, [fp, #-44]
	ldr	r3, [fp, #-44]
	cmp	r3, #0
	beq	.L2
	ldr	r3, [fp, #-44]
	b	.L32
.L2:
	ldr	r3, .L35+4
	ldr	r3, [r3]
	mov	r0, r3
	bl	RREG32
	str	r0, [fp, #-40]
	ldr	r3, [fp, #-40]
	orr	r3, r3, #8388608
	str	r3, [fp, #-40]
	ldr	r3, .L35+4
	ldr	r3, [r3]
	ldr	r1, [fp, #-40]
	mov	r0, r3
	bl	WREG32
	ldr	r3, [fp, #-80]
	add	r3, r3, #8
	mov	r0, r3
	bl	mutex_lock
	mov	r3, #0
	str	r3, [fp, #-64]
	b	.L4
.L9:
	ldr	r3, [fp, #-64]
	cmp	r3, #3
	bgt	.L5
	mov	r3, #1
	b	.L6
.L5:
	mov	r3, #2
.L6:
	str	r3, [fp, #-28]
	ldr	r3, [fp, #-64]
	cmp	r3, #3
	ble	.L7
	ldr	r3, [fp, #-64]
	sub	r3, r3, #4
	b	.L8
.L7:
	ldr	r3, [fp, #-64]
.L8:
	str	r3, [fp, #-24]
	mov	r3, #0
	str	r3, [sp]
	mov	r3, #0
	ldr	r2, [fp, #-24]
	ldr	r1, [fp, #-28]
	ldr	r0, [fp, #-80]
	bl	cik_srbm_select
	ldr	r3, [fp, #-80]
	ldr	r2, [r3, #28]
	ldr	r3, .L35+8
	ldr	r3, [r3]
	ldr	r1, [fp, #-64]
	mul	r3, r1, r3
	lsl	r3, r3, #1
	add	r3, r2, r3
	str	r3, [fp, #-20]
	ldr	r3, .L35+12
	ldr	r2, [r3]
	ldr	r3, [fp, #-20]
	asr	r3, r3, #8
	mov	r1, r3
	mov	r0, r2
	bl	WREG32
	ldr	r3, .L35+16
	ldr	r4, [r3]
	ldr	r0, [fp, #-20]
	bl	upper_32_bits
	mov	r3, r0
	asr	r3, r3, #8
	mov	r1, r3
	mov	r0, r4
	bl	WREG32
	ldr	r3, .L35+20
	ldr	r3, [r3]
	mov	r1, #0
	mov	r0, r3
	bl	WREG32
	ldr	r3, .L35+24
	ldr	r3, [r3]
	mov	r0, r3
	bl	RREG32
	str	r0, [fp, #-40]
	ldr	r3, .L35+28
	ldr	r3, [r3]
	mvn	r3, r3
	ldr	r2, [fp, #-40]
	and	r3, r3, r2
	str	r3, [fp, #-40]
	ldr	r3, .L35+8
	ldr	r3, [r3]
	add	r2, r3, #7
	cmp	r3, #0
	movlt	r3, r2
	movge	r3, r3
	asr	r3, r3, #3
	mov	r0, r3
	bl	order_base_2
	mov	r2, r0
	ldr	r3, [fp, #-40]
	orr	r3, r3, r2
	str	r3, [fp, #-40]
	ldr	r3, .L35+24
	ldr	r3, [r3]
	ldr	r1, [fp, #-40]
	mov	r0, r3
	bl	WREG32
	ldr	r3, [fp, #-64]
	add	r3, r3, #1
	str	r3, [fp, #-64]
.L4:
	ldr	r3, [fp, #-80]
	ldr	r3, [r3, #20]
	ldr	r2, [fp, #-80]
	ldr	r2, [r2, #24]
	mul	r3, r2, r3
	ldr	r2, [fp, #-64]
	cmp	r2, r3
	blt	.L9
	mov	r3, #0
	str	r3, [sp]
	mov	r3, #0
	mov	r2, #0
	mov	r1, #0
	ldr	r0, [fp, #-80]
	bl	cik_srbm_select
	ldr	r3, [fp, #-80]
	add	r3, r3, #8
	mov	r0, r3
	bl	mutex_unlock
	mov	r3, #0
	str	r3, [fp, #-64]
	b	.L10
.L31:
	ldr	r3, [fp, #-64]
	cmp	r3, #0
	bne	.L11
	ldr	r3, .L35+32
	ldr	r3, [r3]
	str	r3, [fp, #-56]
	b	.L12
.L11:
	ldr	r3, .L35+36
	ldr	r3, [r3]
	str	r3, [fp, #-56]
.L12:
	ldr	r3, [fp, #-80]
	ldr	r1, [r3, #4]
	ldr	r2, [fp, #-56]
	mov	r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r3, [r3, #24]
	cmp	r3, #0
	bne	.L13
	ldr	r3, .L35+40
	ldr	ip, [r3]
	ldr	r3, .L35+44
	ldr	r1, [r3]
	ldr	r3, [fp, #-80]
	ldr	r0, [r3, #4]
	ldr	r2, [fp, #-56]
	mov	r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r0, r3
	add	r3, r3, #24
	str	r3, [sp, #16]
	mov	r3, #0
	str	r3, [sp, #12]
	mov	r3, #0
	str	r3, [sp, #8]
	mov	r3, #0
	str	r3, [sp, #4]
	str	r1, [sp]
	mov	r3, #1
	mov	r2, ip
	mov	r1, #76
	ldr	r0, [fp, #-80]
	bl	radeon_bo_create
	str	r0, [fp, #-44]
	ldr	r3, [fp, #-44]
	cmp	r3, #0
	beq	.L13
	ldr	r3, [fp, #-80]
	ldr	r3, [r3, #16]
	ldr	r2, [fp, #-44]
	ldr	r1, .L35+48
	mov	r0, r3
	bl	dev_warn
	ldr	r3, [fp, #-44]
	b	.L32
.L13:
	ldr	r3, [fp, #-80]
	ldr	r1, [r3, #4]
	ldr	r2, [fp, #-56]
	mov	r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r3, [r3, #24]
	mov	r1, #0
	mov	r0, r3
	bl	radeon_bo_reserve
	str	r0, [fp, #-44]
	ldr	r3, [fp, #-44]
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	mov	r0, r3
	bl	unlikely
	mov	r3, r0
	cmp	r3, #0
	beq	.L14
	ldr	r0, [fp, #-80]
	bl	cik_cp_compute_fini
	ldr	r3, [fp, #-44]
	b	.L32
.L14:
	ldr	r3, [fp, #-80]
	ldr	r1, [r3, #4]
	ldr	r2, [fp, #-56]
	mov	r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r3, [r3, #24]
	ldr	r2, .L35+44
	ldr	r1, [r2]
	sub	r2, fp, #72
	mov	r0, r3
	bl	radeon_bo_pin
	str	r0, [fp, #-44]
	ldr	r3, [fp, #-44]
	cmp	r3, #0
	beq	.L15
	ldr	r3, [fp, #-80]
	ldr	r3, [r3, #16]
	ldr	r2, [fp, #-44]
	ldr	r1, .L35+52
	mov	r0, r3
	bl	dev_warn
	ldr	r0, [fp, #-80]
	bl	cik_cp_compute_fini
	ldr	r3, [fp, #-44]
	b	.L32
.L15:
	ldr	r3, [fp, #-80]
	ldr	r1, [r3, #4]
	ldr	r2, [fp, #-56]
	mov	r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r3, [r3, #24]
	sub	r2, fp, #68
	mov	r1, r2
	mov	r0, r3
	bl	radeon_bo_kmap
	str	r0, [fp, #-44]
	ldr	r3, [fp, #-44]
	cmp	r3, #0
	beq	.L16
	ldr	r3, [fp, #-80]
	ldr	r3, [r3, #16]
	ldr	r2, [fp, #-44]
	ldr	r1, .L35+56
	mov	r0, r3
	bl	dev_warn
	ldr	r0, [fp, #-80]
	bl	cik_cp_compute_fini
	ldr	r3, [fp, #-44]
	b	.L32
.L16:
	ldr	r3, [fp, #-68]
	mov	r2, #76
	mov	r1, #0
	mov	r0, r3
	bl	memset
	ldr	r3, [fp, #-68]
	str	r3, [fp, #-36]
	ldr	r3, [fp, #-36]
	ldr	r2, .L35+60
	str	r2, [r3]
	ldr	r3, [fp, #-36]
	ldr	r3, [r3, #4]
	mvn	r2, #0
	str	r2, [r3]
	ldr	r3, [fp, #-36]
	ldr	r3, [r3, #4]
	add	r3, r3, #4
	mvn	r2, #0
	str	r2, [r3]
	ldr	r3, [fp, #-36]
	ldr	r3, [r3, #8]
	mvn	r2, #0
	str	r2, [r3]
	ldr	r3, [fp, #-36]
	ldr	r3, [r3, #8]
	add	r3, r3, #4
	mvn	r2, #0
	str	r2, [r3]
	ldr	r3, [fp, #-80]
	add	r3, r3, #8
	mov	r0, r3
	bl	mutex_lock
	ldr	r3, [fp, #-80]
	ldr	r1, [r3, #4]
	ldr	r2, [fp, #-56]
	mov	r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r0, [r3]
	ldr	r3, [fp, #-80]
	ldr	r1, [r3, #4]
	ldr	r2, [fp, #-56]
	mov	r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	ip, [r3, #4]
	ldr	r3, [fp, #-80]
	ldr	r1, [r3, #4]
	ldr	r2, [fp, #-56]
	mov	r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r3, [r3, #32]
	mov	r2, #0
	str	r2, [sp]
	mov	r2, ip
	mov	r1, r0
	ldr	r0, [fp, #-80]
	bl	cik_srbm_select
	ldr	r3, .L35+64
	ldr	r3, [r3]
	mov	r0, r3
	bl	RREG32
	str	r0, [fp, #-40]
	ldr	r3, .L35+68
	ldr	r3, [r3]
	mvn	r3, r3
	ldr	r2, [fp, #-40]
	and	r3, r3, r2
	str	r3, [fp, #-40]
	ldr	r3, .L35+64
	ldr	r3, [r3]
	ldr	r1, [fp, #-40]
	mov	r0, r3
	bl	WREG32
	ldr	r3, .L35+72
	ldr	r3, [r3]
	mov	r0, r3
	bl	RREG32
	mov	r2, r0
	ldr	r3, [fp, #-36]
	str	r2, [r3, #12]
	ldr	r3, [fp, #-48]
	cmp	r3, #0
	beq	.L17
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #12]
	ldr	r3, .L35+76
	ldr	r3, [r3]
	orr	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #12]
	b	.L18
.L17:
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #12]
	ldr	r3, .L35+76
	ldr	r3, [r3]
	mvn	r3, r3
	and	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #12]
.L18:
	ldr	r3, .L35+72
	ldr	r2, [r3]
	ldr	r3, [fp, #-36]
	ldr	r3, [r3, #12]
	mov	r1, r3
	mov	r0, r2
	bl	WREG32
	ldr	r3, [fp, #-36]
	mov	r2, #0
	str	r2, [r3, #16]
	ldr	r3, [fp, #-36]
	mov	r2, #0
	str	r2, [r3, #20]
	ldr	r3, [fp, #-36]
	mov	r2, #0
	str	r2, [r3, #24]
	ldr	r3, .L35+80
	ldr	r3, [r3]
	mov	r0, r3
	bl	RREG32
	mov	r3, r0
	and	r3, r3, #1
	cmp	r3, #0
	beq	.L19
	ldr	r3, .L35+84
	ldr	r3, [r3]
	mov	r1, #1
	mov	r0, r3
	bl	WREG32
	mov	r3, #0
	str	r3, [fp, #-60]
	b	.L20
.L23:
	ldr	r3, .L35+80
	ldr	r3, [r3]
	mov	r0, r3
	bl	RREG32
	mov	r3, r0
	and	r3, r3, #1
	cmp	r3, #0
	beq	.L34
	mov	r0, #1
	bl	udelay
	ldr	r3, [fp, #-60]
	add	r3, r3, #1
	str	r3, [fp, #-60]
.L20:
	ldr	r3, [fp, #-80]
	ldr	r3, [r3]
	ldr	r2, [fp, #-60]
	cmp	r2, r3
	blt	.L23
	b	.L22
.L34:
	nop
.L22:
	ldr	r3, .L35+84
	ldr	r2, [r3]
	ldr	r3, [fp, #-36]
	ldr	r3, [r3, #16]
	mov	r1, r3
	mov	r0, r2
	bl	WREG32
	ldr	r3, .L35+88
	ldr	r2, [r3]
	ldr	r3, [fp, #-36]
	ldr	r3, [r3, #20]
	mov	r1, r3
	mov	r0, r2
	bl	WREG32
	ldr	r3, .L35+92
	ldr	r2, [r3]
	ldr	r3, [fp, #-36]
	ldr	r3, [r3, #24]
	mov	r1, r3
	mov	r0, r2
	bl	WREG32
.L19:
	ldr	r3, [fp, #-72]
	bic	r2, r3, #3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #28]
	ldr	r3, [fp, #-72]
	mov	r0, r3
	bl	upper_32_bits
	mov	r2, r0
	ldr	r3, [fp, #-36]
	str	r2, [r3, #32]
	ldr	r3, .L35+96
	ldr	r2, [r3]
	ldr	r3, [fp, #-36]
	ldr	r3, [r3, #28]
	mov	r1, r3
	mov	r0, r2
	bl	WREG32
	ldr	r3, .L35+100
	ldr	r2, [r3]
	ldr	r3, [fp, #-36]
	ldr	r3, [r3, #32]
	mov	r1, r3
	mov	r0, r2
	bl	WREG32
	ldr	r3, .L35+104
	ldr	r3, [r3]
	mov	r0, r3
	bl	RREG32
	mov	r2, r0
	ldr	r3, [fp, #-36]
	str	r2, [r3, #36]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #36]
	ldr	r3, .L35+108
	ldr	r3, [r3]
	mvn	r3, r3
	and	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #36]
	ldr	r3, .L35+104
	ldr	r2, [r3]
	ldr	r3, [fp, #-36]
	ldr	r3, [r3, #36]
	mov	r1, r3
	mov	r0, r2
	bl	WREG32
	ldr	r3, [fp, #-80]
	ldr	r1, [r3, #4]
	ldr	r2, [fp, #-56]
	mov	r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r3, [r3, #8]
	asr	r3, r3, #8
	str	r3, [fp, #-32]
	ldr	r3, [fp, #-36]
	ldr	r2, [fp, #-32]
	str	r2, [r3, #40]
	ldr	r0, [fp, #-32]
	bl	upper_32_bits
	mov	r2, r0
	ldr	r3, [fp, #-36]
	str	r2, [r3, #44]
	ldr	r3, .L35+112
	ldr	r2, [r3]
	ldr	r3, [fp, #-36]
	ldr	r3, [r3, #40]
	mov	r1, r3
	mov	r0, r2
	bl	WREG32
	ldr	r3, .L35+116
	ldr	r2, [r3]
	ldr	r3, [fp, #-36]
	ldr	r3, [r3, #44]
	mov	r1, r3
	mov	r0, r2
	bl	WREG32
	ldr	r3, .L35+120
	ldr	r3, [r3]
	mov	r0, r3
	bl	RREG32
	mov	r2, r0
	ldr	r3, [fp, #-36]
	str	r2, [r3, #48]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #48]
	ldr	r3, .L35+124
	ldr	r1, [r3]
	ldr	r3, .L35+128
	ldr	r3, [r3]
	orr	r3, r1, r3
	mvn	r3, r3
	and	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #48]
	ldr	r3, [fp, #-80]
	ldr	r1, [r3, #4]
	ldr	r2, [fp, #-56]
	mov	r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r3, [r3, #12]
	add	r2, r3, #7
	cmp	r3, #0
	movlt	r3, r2
	movge	r3, r3
	asr	r3, r3, #3
	mov	r0, r3
	bl	order_base_2
	mov	r2, r0
	ldr	r3, [fp, #-36]
	ldr	r3, [r3, #48]
	orr	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #48]
	ldr	r3, .L35+132
	ldr	r3, [r3]
	add	r2, r3, #7
	cmp	r3, #0
	movlt	r3, r2
	movge	r3, r3
	asr	r3, r3, #3
	mov	r0, r3
	bl	order_base_2
	mov	r3, r0
	lsl	r2, r3, #8
	ldr	r3, [fp, #-36]
	ldr	r3, [r3, #48]
	orr	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #48]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #48]
	ldr	r3, .L35+136
	ldr	r1, [r3]
	ldr	r3, .L35+140
	ldr	r3, [r3]
	orr	r1, r1, r3
	ldr	r3, .L35+144
	ldr	r3, [r3]
	orr	r3, r1, r3
	mvn	r3, r3
	and	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #48]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #48]
	ldr	r3, .L35+148
	ldr	r1, [r3]
	ldr	r3, .L35+152
	ldr	r3, [r3]
	orr	r3, r1, r3
	orr	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #48]
	ldr	r3, .L35+120
	ldr	r2, [r3]
	ldr	r3, [fp, #-36]
	ldr	r3, [r3, #48]
	mov	r1, r3
	mov	r0, r2
	bl	WREG32
	ldr	r3, [fp, #-64]
	cmp	r3, #0
	bne	.L24
	ldr	r3, [fp, #-80]
	ldr	r2, [r3, #12]
	ldr	r3, .L35+156
	ldr	r3, [r3]
	add	r3, r2, r3
	str	r3, [fp, #-52]
	b	.L25
.L24:
	ldr	r3, [fp, #-80]
	ldr	r2, [r3, #12]
	ldr	r3, .L35+160
	ldr	r3, [r3]
	add	r3, r2, r3
	str	r3, [fp, #-52]
.L25:
	ldr	r3, [fp, #-52]
	bic	r2, r3, #3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #52]
	ldr	r0, [fp, #-52]
	bl	upper_32_bits
	mov	r3, r0
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	ldr	r2, [fp, #-36]
	str	r3, [r2, #56]
	ldr	r3, .L35+164
	ldr	r2, [r3]
	ldr	r3, [fp, #-36]
	ldr	r3, [r3, #52]
	mov	r1, r3
	mov	r0, r2
	bl	WREG32
	ldr	r3, .L35+168
	ldr	r2, [r3]
	ldr	r3, [fp, #-36]
	ldr	r3, [r3, #56]
	mov	r1, r3
	mov	r0, r2
	bl	WREG32
	ldr	r3, [fp, #-64]
	cmp	r3, #0
	bne	.L26
	ldr	r3, [fp, #-80]
	ldr	r2, [r3, #12]
	ldr	r3, .L35+172
	ldr	r3, [r3]
	add	r3, r2, r3
	str	r3, [fp, #-52]
	b	.L27
.L26:
	ldr	r3, [fp, #-80]
	ldr	r2, [r3, #12]
	ldr	r3, .L35+176
	ldr	r3, [r3]
	add	r3, r2, r3
	str	r3, [fp, #-52]
.L27:
	ldr	r3, [fp, #-52]
	bic	r2, r3, #3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #60]
	ldr	r0, [fp, #-52]
	bl	upper_32_bits
	mov	r3, r0
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	ldr	r2, [fp, #-36]
	str	r3, [r2, #64]
	ldr	r3, .L35+180
	ldr	r2, [r3]
	ldr	r3, [fp, #-36]
	ldr	r3, [r3, #60]
	mov	r1, r3
	mov	r0, r2
	bl	WREG32
	ldr	r3, .L35+184
	ldr	r2, [r3]
	ldr	r3, [fp, #-36]
	ldr	r3, [r3, #64]
	mov	r1, r3
	mov	r0, r2
	bl	WREG32
	ldr	r3, [fp, #-48]
	cmp	r3, #0
	beq	.L28
	ldr	r3, .L35+72
	ldr	r3, [r3]
	mov	r0, r3
	bl	RREG32
	mov	r2, r0
	ldr	r3, [fp, #-36]
	str	r2, [r3, #12]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #12]
	ldr	r3, .L35+188
	ldr	r3, [r3]
	mvn	r3, r3
	and	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #12]
	ldr	r3, [fp, #-80]
	ldr	r1, [r3, #4]
	ldr	r2, [fp, #-56]
	mov	r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r3, [r3, #28]
	mov	r0, r3
	bl	DOORBELL_OFFSET
	mov	r2, r0
	ldr	r3, [fp, #-36]
	ldr	r3, [r3, #12]
	orr	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #12]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #12]
	ldr	r3, .L35+76
	ldr	r3, [r3]
	orr	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #12]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #12]
	ldr	r3, .L35+192
	ldr	r1, [r3]
	ldr	r3, .L35+196
	ldr	r3, [r3]
	orr	r3, r1, r3
	mvn	r3, r3
	and	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #12]
	b	.L29
.L28:
	ldr	r3, [fp, #-36]
	mov	r2, #0
	str	r2, [r3, #12]
.L29:
	ldr	r3, .L35+72
	ldr	r2, [r3]
	ldr	r3, [fp, #-36]
	ldr	r3, [r3, #12]
	mov	r1, r3
	mov	r0, r2
	bl	WREG32
	ldr	r3, [fp, #-80]
	ldr	r1, [r3, #4]
	ldr	r2, [fp, #-56]
	mov	r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	mov	r2, #0
	str	r2, [r3, #16]
	ldr	r3, [fp, #-80]
	ldr	r1, [r3, #4]
	ldr	r2, [fp, #-56]
	mov	r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r2, [r3, #16]
	ldr	r3, [fp, #-36]
	str	r2, [r3, #24]
	ldr	r3, .L35+92
	ldr	r2, [r3]
	ldr	r3, [fp, #-36]
	ldr	r3, [r3, #24]
	mov	r1, r3
	mov	r0, r2
	bl	WREG32
	ldr	r3, .L35+88
	ldr	r3, [r3]
	mov	r0, r3
	bl	RREG32
	mov	r2, r0
	ldr	r3, [fp, #-36]
	str	r2, [r3, #20]
	ldr	r3, [fp, #-36]
	mov	r2, #0
	str	r2, [r3, #68]
	ldr	r3, .L35+200
	ldr	r2, [r3]
	ldr	r3, [fp, #-36]
	ldr	r3, [r3, #68]
	mov	r1, r3
	mov	r0, r2
	bl	WREG32
	ldr	r3, [fp, #-36]
	mov	r2, #1
	str	r2, [r3, #72]
	ldr	r3, .L35+80
	ldr	r2, [r3]
	ldr	r3, [fp, #-36]
	ldr	r3, [r3, #72]
	mov	r1, r3
	mov	r0, r2
	bl	WREG32
	mov	r3, #0
	str	r3, [sp]
	mov	r3, #0
	mov	r2, #0
	mov	r1, #0
	ldr	r0, [fp, #-80]
	bl	cik_srbm_select
	ldr	r3, [fp, #-80]
	add	r3, r3, #8
	mov	r0, r3
	bl	mutex_unlock
	ldr	r3, [fp, #-80]
	ldr	r1, [r3, #4]
	ldr	r2, [fp, #-56]
	mov	r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r3, [r3, #24]
	mov	r0, r3
	bl	radeon_bo_kunmap
	ldr	r3, [fp, #-80]
	ldr	r1, [r3, #4]
	ldr	r2, [fp, #-56]
	mov	r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r3, [r3, #24]
	mov	r0, r3
	bl	radeon_bo_unreserve
	ldr	r3, [fp, #-80]
	ldr	r1, [r3, #4]
	ldr	r2, [fp, #-56]
	mov	r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	mov	r2, #1
	str	r2, [r3, #20]
	ldr	r3, [fp, #-80]
	ldr	r1, [r3, #4]
	ldr	r2, [fp, #-56]
	mov	r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	mov	r2, r3
	ldr	r1, [fp, #-56]
	ldr	r0, [fp, #-80]
	bl	radeon_ring_test
	str	r0, [fp, #-44]
	ldr	r3, [fp, #-44]
	cmp	r3, #0
	beq	.L30
	ldr	r3, [fp, #-80]
	ldr	r1, [r3, #4]
	ldr	r2, [fp, #-56]
	mov	r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	mov	r2, #0
	str	r2, [r3, #20]
.L30:
	ldr	r3, [fp, #-64]
	add	r3, r3, #1
	str	r3, [fp, #-64]
.L10:
	ldr	r3, [fp, #-64]
	cmp	r3, #1
	ble	.L31
	mov	r3, #0
.L32:
	ldr	r2, .L35
	ldr	r1, [r2]
	ldr	r2, [fp, #-16]
	eors	r1, r2, r1
	mov	r2, #0
	beq	.L33
	bl	__stack_chk_fail
.L33:
	mov	r0, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, fp, pc}
.L36:
	.align	2
.L35:
	.word	.LC3
	.word	CP_CPF_DEBUG
	.word	MEC_HPD_SIZE
	.word	CP_HPD_EOP_BASE_ADDR
	.word	CP_HPD_EOP_BASE_ADDR_HI
	.word	CP_HPD_EOP_VMID
	.word	CP_HPD_EOP_CONTROL
	.word	EOP_SIZE_MASK
	.word	CAYMAN_RING_TYPE_CP1_INDEX
	.word	CAYMAN_RING_TYPE_CP2_INDEX
	.word	PAGE_SIZE
	.word	RADEON_GEM_DOMAIN_GTT
	.word	.LC0
	.word	.LC1
	.word	.LC2
	.word	-1070528512
	.word	CP_PQ_WPTR_POLL_CNTL
	.word	WPTR_POLL_EN
	.word	CP_HQD_PQ_DOORBELL_CONTROL
	.word	DOORBELL_EN
	.word	CP_HQD_ACTIVE
	.word	CP_HQD_DEQUEUE_REQUEST
	.word	CP_HQD_PQ_RPTR
	.word	CP_HQD_PQ_WPTR
	.word	CP_MQD_BASE_ADDR
	.word	CP_MQD_BASE_ADDR_HI
	.word	CP_MQD_CONTROL
	.word	MQD_VMID_MASK
	.word	CP_HQD_PQ_BASE
	.word	CP_HQD_PQ_BASE_HI
	.word	CP_HQD_PQ_CONTROL
	.word	QUEUE_SIZE_MASK
	.word	RPTR_BLOCK_SIZE_MASK
	.word	RADEON_GPU_PAGE_SIZE
	.word	UNORD_DISPATCH
	.word	ROQ_PQ_IB_FLIP
	.word	PQ_VOLATILE
	.word	PRIV_STATE
	.word	KMD_QUEUE
	.word	CIK_WB_CP1_WPTR_OFFSET
	.word	CIK_WB_CP2_WPTR_OFFSET
	.word	CP_HQD_PQ_WPTR_POLL_ADDR
	.word	CP_HQD_PQ_WPTR_POLL_ADDR_HI
	.word	RADEON_WB_CP1_RPTR_OFFSET
	.word	RADEON_WB_CP2_RPTR_OFFSET
	.word	CP_HQD_PQ_RPTR_REPORT_ADDR
	.word	CP_HQD_PQ_RPTR_REPORT_ADDR_HI
	.word	DOORBELL_OFFSET_MASK
	.word	DOORBELL_SOURCE
	.word	DOORBELL_HIT
	.word	CP_HQD_VMID
	.size	cik_cp_compute_resume, .-cik_cp_compute_resume
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
