	.file	"584441.c"
	.intel_syntax noprefix
	.text
	.globl	__VERIFIER_nondet_bool
	.type	__VERIFIER_nondet_bool, @function
__VERIFIER_nondet_bool:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	call	__VERIFIER_nondet_int@PLT
	test	eax, eax
	setne	al
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.globl	t12_l1
	.bss
	.type	t12_l1, @object
	.size	t12_l1, 1
t12_l1:
	.zero	1
	.globl	_x_t12_l1
	.type	_x_t12_l1, @object
	.size	_x_t12_l1, 1
_x_t12_l1:
	.zero	1
	.globl	t12_l0
	.type	t12_l0, @object
	.size	t12_l0, 1
t12_l0:
	.zero	1
	.globl	_x_t12_l0
	.type	_x_t12_l0, @object
	.size	_x_t12_l0, 1
_x_t12_l0:
	.zero	1
	.globl	t12_evt1
	.type	t12_evt1, @object
	.size	t12_evt1, 1
t12_evt1:
	.zero	1
	.globl	_x_t12_evt1
	.type	_x_t12_evt1, @object
	.size	_x_t12_evt1, 1
_x_t12_evt1:
	.zero	1
	.globl	t12_evt0
	.type	t12_evt0, @object
	.size	t12_evt0, 1
t12_evt0:
	.zero	1
	.globl	_x_t12_evt0
	.type	_x_t12_evt0, @object
	.size	_x_t12_evt0, 1
_x_t12_evt0:
	.zero	1
	.globl	t12_x
	.align 4
	.type	t12_x, @object
	.size	t12_x, 4
t12_x:
	.zero	4
	.globl	_x_t12_x
	.align 4
	.type	_x_t12_x, @object
	.size	_x_t12_x, 4
_x_t12_x:
	.zero	4
	.globl	t11_l1
	.type	t11_l1, @object
	.size	t11_l1, 1
t11_l1:
	.zero	1
	.globl	_x_t11_l1
	.type	_x_t11_l1, @object
	.size	_x_t11_l1, 1
_x_t11_l1:
	.zero	1
	.globl	t11_l0
	.type	t11_l0, @object
	.size	t11_l0, 1
t11_l0:
	.zero	1
	.globl	_x_t11_l0
	.type	_x_t11_l0, @object
	.size	_x_t11_l0, 1
_x_t11_l0:
	.zero	1
	.globl	t11_evt1
	.type	t11_evt1, @object
	.size	t11_evt1, 1
t11_evt1:
	.zero	1
	.globl	_x_t11_evt1
	.type	_x_t11_evt1, @object
	.size	_x_t11_evt1, 1
_x_t11_evt1:
	.zero	1
	.globl	t11_evt0
	.type	t11_evt0, @object
	.size	t11_evt0, 1
t11_evt0:
	.zero	1
	.globl	_x_t11_evt0
	.type	_x_t11_evt0, @object
	.size	_x_t11_evt0, 1
_x_t11_evt0:
	.zero	1
	.globl	t11_x
	.align 4
	.type	t11_x, @object
	.size	t11_x, 4
t11_x:
	.zero	4
	.globl	_x_t11_x
	.align 4
	.type	_x_t11_x, @object
	.size	_x_t11_x, 4
_x_t11_x:
	.zero	4
	.globl	t10_l1
	.type	t10_l1, @object
	.size	t10_l1, 1
t10_l1:
	.zero	1
	.globl	_x_t10_l1
	.type	_x_t10_l1, @object
	.size	_x_t10_l1, 1
_x_t10_l1:
	.zero	1
	.globl	t10_l0
	.type	t10_l0, @object
	.size	t10_l0, 1
t10_l0:
	.zero	1
	.globl	_x_t10_l0
	.type	_x_t10_l0, @object
	.size	_x_t10_l0, 1
_x_t10_l0:
	.zero	1
	.globl	t10_evt1
	.type	t10_evt1, @object
	.size	t10_evt1, 1
t10_evt1:
	.zero	1
	.globl	_x_t10_evt1
	.type	_x_t10_evt1, @object
	.size	_x_t10_evt1, 1
_x_t10_evt1:
	.zero	1
	.globl	t10_evt0
	.type	t10_evt0, @object
	.size	t10_evt0, 1
t10_evt0:
	.zero	1
	.globl	_x_t10_evt0
	.type	_x_t10_evt0, @object
	.size	_x_t10_evt0, 1
_x_t10_evt0:
	.zero	1
	.globl	t10_x
	.align 4
	.type	t10_x, @object
	.size	t10_x, 4
t10_x:
	.zero	4
	.globl	_x_t10_x
	.align 4
	.type	_x_t10_x, @object
	.size	_x_t10_x, 4
_x_t10_x:
	.zero	4
	.globl	t9_l1
	.type	t9_l1, @object
	.size	t9_l1, 1
t9_l1:
	.zero	1
	.globl	_x_t9_l1
	.type	_x_t9_l1, @object
	.size	_x_t9_l1, 1
_x_t9_l1:
	.zero	1
	.globl	t9_l0
	.type	t9_l0, @object
	.size	t9_l0, 1
t9_l0:
	.zero	1
	.globl	_x_t9_l0
	.type	_x_t9_l0, @object
	.size	_x_t9_l0, 1
_x_t9_l0:
	.zero	1
	.globl	t9_evt1
	.type	t9_evt1, @object
	.size	t9_evt1, 1
t9_evt1:
	.zero	1
	.globl	_x_t9_evt1
	.type	_x_t9_evt1, @object
	.size	_x_t9_evt1, 1
_x_t9_evt1:
	.zero	1
	.globl	t9_evt0
	.type	t9_evt0, @object
	.size	t9_evt0, 1
t9_evt0:
	.zero	1
	.globl	_x_t9_evt0
	.type	_x_t9_evt0, @object
	.size	_x_t9_evt0, 1
_x_t9_evt0:
	.zero	1
	.globl	t3_x
	.align 4
	.type	t3_x, @object
	.size	t3_x, 4
t3_x:
	.zero	4
	.globl	_x_t3_x
	.align 4
	.type	_x_t3_x, @object
	.size	_x_t3_x, 4
_x_t3_x:
	.zero	4
	.globl	t2_evt1
	.type	t2_evt1, @object
	.size	t2_evt1, 1
t2_evt1:
	.zero	1
	.globl	_x_t2_evt1
	.type	_x_t2_evt1, @object
	.size	_x_t2_evt1, 1
_x_t2_evt1:
	.zero	1
	.globl	t2_evt0
	.type	t2_evt0, @object
	.size	t2_evt0, 1
t2_evt0:
	.zero	1
	.globl	_x_t2_evt0
	.type	_x_t2_evt0, @object
	.size	_x_t2_evt0, 1
_x_t2_evt0:
	.zero	1
	.globl	t1_l1
	.type	t1_l1, @object
	.size	t1_l1, 1
t1_l1:
	.zero	1
	.globl	_x_t1_l1
	.type	_x_t1_l1, @object
	.size	_x_t1_l1, 1
_x_t1_l1:
	.zero	1
	.globl	t0_l1
	.type	t0_l1, @object
	.size	t0_l1, 1
t0_l1:
	.zero	1
	.globl	_x_t0_l1
	.type	_x_t0_l1, @object
	.size	_x_t0_l1, 1
_x_t0_l1:
	.zero	1
	.globl	t1_evt0
	.type	t1_evt0, @object
	.size	t1_evt0, 1
t1_evt0:
	.zero	1
	.globl	_x_t1_evt0
	.type	_x_t1_evt0, @object
	.size	_x_t1_evt0, 1
_x_t1_evt0:
	.zero	1
	.globl	t0_l0
	.type	t0_l0, @object
	.size	t0_l0, 1
t0_l0:
	.zero	1
	.globl	_x_t0_l0
	.type	_x_t0_l0, @object
	.size	_x_t0_l0, 1
_x_t0_l0:
	.zero	1
	.globl	t0_x
	.align 4
	.type	t0_x, @object
	.size	t0_x, 4
t0_x:
	.zero	4
	.globl	_x_t0_x
	.align 4
	.type	_x_t0_x, @object
	.size	_x_t0_x, 4
_x_t0_x:
	.zero	4
	.globl	t0_evt0
	.type	t0_evt0, @object
	.size	t0_evt0, 1
t0_evt0:
	.zero	1
	.globl	_x_t0_evt0
	.type	_x_t0_evt0, @object
	.size	_x_t0_evt0, 1
_x_t0_evt0:
	.zero	1
	.globl	delta
	.align 4
	.type	delta, @object
	.size	delta, 4
delta:
	.zero	4
	.globl	_x_delta
	.align 4
	.type	_x_delta, @object
	.size	_x_delta, 4
_x_delta:
	.zero	4
	.globl	t5_l0
	.type	t5_l0, @object
	.size	t5_l0, 1
t5_l0:
	.zero	1
	.globl	_x_t5_l0
	.type	_x_t5_l0, @object
	.size	_x_t5_l0, 1
_x_t5_l0:
	.zero	1
	.globl	t1_l0
	.type	t1_l0, @object
	.size	t1_l0, 1
t1_l0:
	.zero	1
	.globl	_x_t1_l0
	.type	_x_t1_l0, @object
	.size	_x_t1_l0, 1
_x_t1_l0:
	.zero	1
	.globl	t0_evt1
	.type	t0_evt1, @object
	.size	t0_evt1, 1
t0_evt1:
	.zero	1
	.globl	_x_t0_evt1
	.type	_x_t0_evt1, @object
	.size	_x_t0_evt1, 1
_x_t0_evt1:
	.zero	1
	.globl	t1_x
	.align 4
	.type	t1_x, @object
	.size	t1_x, 4
t1_x:
	.zero	4
	.globl	_x_t1_x
	.align 4
	.type	_x_t1_x, @object
	.size	_x_t1_x, 4
_x_t1_x:
	.zero	4
	.globl	controller_l0
	.type	controller_l0, @object
	.size	controller_l0, 1
controller_l0:
	.zero	1
	.globl	_x_controller_l0
	.type	_x_controller_l0, @object
	.size	_x_controller_l0, 1
_x_controller_l0:
	.zero	1
	.globl	t6_evt1
	.type	t6_evt1, @object
	.size	t6_evt1, 1
t6_evt1:
	.zero	1
	.globl	_x_t6_evt1
	.type	_x_t6_evt1, @object
	.size	_x_t6_evt1, 1
_x_t6_evt1:
	.zero	1
	.globl	t7_x
	.align 4
	.type	t7_x, @object
	.size	t7_x, 4
t7_x:
	.zero	4
	.globl	_x_t7_x
	.align 4
	.type	_x_t7_x, @object
	.size	_x_t7_x, 4
_x_t7_x:
	.zero	4
	.globl	gate_l1
	.type	gate_l1, @object
	.size	gate_l1, 1
gate_l1:
	.zero	1
	.globl	_x_gate_l1
	.type	_x_gate_l1, @object
	.size	_x_gate_l1, 1
_x_gate_l1:
	.zero	1
	.globl	controller_l1
	.type	controller_l1, @object
	.size	controller_l1, 1
controller_l1:
	.zero	1
	.globl	_x_controller_l1
	.type	_x_controller_l1, @object
	.size	_x_controller_l1, 1
_x_controller_l1:
	.zero	1
	.globl	t2_l0
	.type	t2_l0, @object
	.size	t2_l0, 1
t2_l0:
	.zero	1
	.globl	_x_t2_l0
	.type	_x_t2_l0, @object
	.size	_x_t2_l0, 1
_x_t2_l0:
	.zero	1
	.globl	controller_evt0
	.type	controller_evt0, @object
	.size	controller_evt0, 1
controller_evt0:
	.zero	1
	.globl	_x_controller_evt0
	.type	_x_controller_evt0, @object
	.size	_x_controller_evt0, 1
_x_controller_evt0:
	.zero	1
	.globl	t2_l1
	.type	t2_l1, @object
	.size	t2_l1, 1
t2_l1:
	.zero	1
	.globl	_x_t2_l1
	.type	_x_t2_l1, @object
	.size	_x_t2_l1, 1
_x_t2_l1:
	.zero	1
	.globl	_diverge_delta
	.align 4
	.type	_diverge_delta, @object
	.size	_diverge_delta, 4
_diverge_delta:
	.zero	4
	.globl	_x__diverge_delta
	.align 4
	.type	_x__diverge_delta, @object
	.size	_x__diverge_delta, 4
_x__diverge_delta:
	.zero	4
	.globl	t3_evt0
	.type	t3_evt0, @object
	.size	t3_evt0, 1
t3_evt0:
	.zero	1
	.globl	_x_t3_evt0
	.type	_x_t3_evt0, @object
	.size	_x_t3_evt0, 1
_x_t3_evt0:
	.zero	1
	.globl	controller_evt1
	.type	controller_evt1, @object
	.size	controller_evt1, 1
controller_evt1:
	.zero	1
	.globl	_x_controller_evt1
	.type	_x_controller_evt1, @object
	.size	_x_controller_evt1, 1
_x_controller_evt1:
	.zero	1
	.globl	t1_evt1
	.type	t1_evt1, @object
	.size	t1_evt1, 1
t1_evt1:
	.zero	1
	.globl	_x_t1_evt1
	.type	_x_t1_evt1, @object
	.size	_x_t1_evt1, 1
_x_t1_evt1:
	.zero	1
	.globl	t2_x
	.align 4
	.type	t2_x, @object
	.size	t2_x, 4
t2_x:
	.zero	4
	.globl	_x_t2_x
	.align 4
	.type	_x_t2_x, @object
	.size	_x_t2_x, 4
_x_t2_x:
	.zero	4
	.globl	gate_evt1
	.type	gate_evt1, @object
	.size	gate_evt1, 1
gate_evt1:
	.zero	1
	.globl	_x_gate_evt1
	.type	_x_gate_evt1, @object
	.size	_x_gate_evt1, 1
_x_gate_evt1:
	.zero	1
	.globl	controller_z
	.align 4
	.type	controller_z, @object
	.size	controller_z, 4
controller_z:
	.zero	4
	.globl	_x_controller_z
	.align 4
	.type	_x_controller_z, @object
	.size	_x_controller_z, 4
_x_controller_z:
	.zero	4
	.globl	controller_evt2
	.type	controller_evt2, @object
	.size	controller_evt2, 1
controller_evt2:
	.zero	1
	.globl	_x_controller_evt2
	.type	_x_controller_evt2, @object
	.size	_x_controller_evt2, 1
_x_controller_evt2:
	.zero	1
	.globl	controller_cnt
	.align 4
	.type	controller_cnt, @object
	.size	controller_cnt, 4
controller_cnt:
	.zero	4
	.globl	_x_controller_cnt
	.align 4
	.type	_x_controller_cnt, @object
	.size	_x_controller_cnt, 4
_x_controller_cnt:
	.zero	4
	.globl	t3_evt1
	.type	t3_evt1, @object
	.size	t3_evt1, 1
t3_evt1:
	.zero	1
	.globl	_x_t3_evt1
	.type	_x_t3_evt1, @object
	.size	_x_t3_evt1, 1
_x_t3_evt1:
	.zero	1
	.globl	t4_x
	.align 4
	.type	t4_x, @object
	.size	t4_x, 4
t4_x:
	.zero	4
	.globl	_x_t4_x
	.align 4
	.type	_x_t4_x, @object
	.size	_x_t4_x, 4
_x_t4_x:
	.zero	4
	.globl	t3_l0
	.type	t3_l0, @object
	.size	t3_l0, 1
t3_l0:
	.zero	1
	.globl	_x_t3_l0
	.type	_x_t3_l0, @object
	.size	_x_t3_l0, 1
_x_t3_l0:
	.zero	1
	.globl	t3_l1
	.type	t3_l1, @object
	.size	t3_l1, 1
t3_l1:
	.zero	1
	.globl	_x_t3_l1
	.type	_x_t3_l1, @object
	.size	_x_t3_l1, 1
_x_t3_l1:
	.zero	1
	.globl	t4_evt0
	.type	t4_evt0, @object
	.size	t4_evt0, 1
t4_evt0:
	.zero	1
	.globl	_x_t4_evt0
	.type	_x_t4_evt0, @object
	.size	_x_t4_evt0, 1
_x_t4_evt0:
	.zero	1
	.globl	gate_y
	.align 4
	.type	gate_y, @object
	.size	gate_y, 4
gate_y:
	.zero	4
	.globl	_x_gate_y
	.align 4
	.type	_x_gate_y, @object
	.size	_x_gate_y, 4
_x_gate_y:
	.zero	4
	.globl	t4_evt1
	.type	t4_evt1, @object
	.size	t4_evt1, 1
t4_evt1:
	.zero	1
	.globl	_x_t4_evt1
	.type	_x_t4_evt1, @object
	.size	_x_t4_evt1, 1
_x_t4_evt1:
	.zero	1
	.globl	t5_x
	.align 4
	.type	t5_x, @object
	.size	t5_x, 4
t5_x:
	.zero	4
	.globl	_x_t5_x
	.align 4
	.type	_x_t5_x, @object
	.size	_x_t5_x, 4
_x_t5_x:
	.zero	4
	.globl	t4_l0
	.type	t4_l0, @object
	.size	t4_l0, 1
t4_l0:
	.zero	1
	.globl	_x_t4_l0
	.type	_x_t4_l0, @object
	.size	_x_t4_l0, 1
_x_t4_l0:
	.zero	1
	.globl	gate_evt0
	.type	gate_evt0, @object
	.size	gate_evt0, 1
gate_evt0:
	.zero	1
	.globl	_x_gate_evt0
	.type	_x_gate_evt0, @object
	.size	_x_gate_evt0, 1
_x_gate_evt0:
	.zero	1
	.globl	t4_l1
	.type	t4_l1, @object
	.size	t4_l1, 1
t4_l1:
	.zero	1
	.globl	_x_t4_l1
	.type	_x_t4_l1, @object
	.size	_x_t4_l1, 1
_x_t4_l1:
	.zero	1
	.globl	t5_evt0
	.type	t5_evt0, @object
	.size	t5_evt0, 1
t5_evt0:
	.zero	1
	.globl	_x_t5_evt0
	.type	_x_t5_evt0, @object
	.size	_x_t5_evt0, 1
_x_t5_evt0:
	.zero	1
	.globl	t5_evt1
	.type	t5_evt1, @object
	.size	t5_evt1, 1
t5_evt1:
	.zero	1
	.globl	_x_t5_evt1
	.type	_x_t5_evt1, @object
	.size	_x_t5_evt1, 1
_x_t5_evt1:
	.zero	1
	.globl	gate_l0
	.type	gate_l0, @object
	.size	gate_l0, 1
gate_l0:
	.zero	1
	.globl	_x_gate_l0
	.type	_x_gate_l0, @object
	.size	_x_gate_l0, 1
_x_gate_l0:
	.zero	1
	.globl	t6_x
	.align 4
	.type	t6_x, @object
	.size	t6_x, 4
t6_x:
	.zero	4
	.globl	_x_t6_x
	.align 4
	.type	_x_t6_x, @object
	.size	_x_t6_x, 4
_x_t6_x:
	.zero	4
	.globl	t5_l1
	.type	t5_l1, @object
	.size	t5_l1, 1
t5_l1:
	.zero	1
	.globl	_x_t5_l1
	.type	_x_t5_l1, @object
	.size	_x_t5_l1, 1
_x_t5_l1:
	.zero	1
	.globl	t6_evt0
	.type	t6_evt0, @object
	.size	t6_evt0, 1
t6_evt0:
	.zero	1
	.globl	_x_t6_evt0
	.type	_x_t6_evt0, @object
	.size	_x_t6_evt0, 1
_x_t6_evt0:
	.zero	1
	.globl	t6_l0
	.type	t6_l0, @object
	.size	t6_l0, 1
t6_l0:
	.zero	1
	.globl	_x_t6_l0
	.type	_x_t6_l0, @object
	.size	_x_t6_l0, 1
_x_t6_l0:
	.zero	1
	.globl	t6_l1
	.type	t6_l1, @object
	.size	t6_l1, 1
t6_l1:
	.zero	1
	.globl	_x_t6_l1
	.type	_x_t6_l1, @object
	.size	_x_t6_l1, 1
_x_t6_l1:
	.zero	1
	.globl	t7_evt0
	.type	t7_evt0, @object
	.size	t7_evt0, 1
t7_evt0:
	.zero	1
	.globl	_x_t7_evt0
	.type	_x_t7_evt0, @object
	.size	_x_t7_evt0, 1
_x_t7_evt0:
	.zero	1
	.globl	t7_evt1
	.type	t7_evt1, @object
	.size	t7_evt1, 1
t7_evt1:
	.zero	1
	.globl	_x_t7_evt1
	.type	_x_t7_evt1, @object
	.size	_x_t7_evt1, 1
_x_t7_evt1:
	.zero	1
	.globl	t8_x
	.align 4
	.type	t8_x, @object
	.size	t8_x, 4
t8_x:
	.zero	4
	.globl	_x_t8_x
	.align 4
	.type	_x_t8_x, @object
	.size	_x_t8_x, 4
_x_t8_x:
	.zero	4
	.globl	t7_l0
	.type	t7_l0, @object
	.size	t7_l0, 1
t7_l0:
	.zero	1
	.globl	_x_t7_l0
	.type	_x_t7_l0, @object
	.size	_x_t7_l0, 1
_x_t7_l0:
	.zero	1
	.globl	t7_l1
	.type	t7_l1, @object
	.size	t7_l1, 1
t7_l1:
	.zero	1
	.globl	_x_t7_l1
	.type	_x_t7_l1, @object
	.size	_x_t7_l1, 1
_x_t7_l1:
	.zero	1
	.globl	t8_evt0
	.type	t8_evt0, @object
	.size	t8_evt0, 1
t8_evt0:
	.zero	1
	.globl	_x_t8_evt0
	.type	_x_t8_evt0, @object
	.size	_x_t8_evt0, 1
_x_t8_evt0:
	.zero	1
	.globl	t8_evt1
	.type	t8_evt1, @object
	.size	t8_evt1, 1
t8_evt1:
	.zero	1
	.globl	_x_t8_evt1
	.type	_x_t8_evt1, @object
	.size	_x_t8_evt1, 1
_x_t8_evt1:
	.zero	1
	.globl	t9_x
	.align 4
	.type	t9_x, @object
	.size	t9_x, 4
t9_x:
	.zero	4
	.globl	_x_t9_x
	.align 4
	.type	_x_t9_x, @object
	.size	_x_t9_x, 4
_x_t9_x:
	.zero	4
	.globl	t8_l0
	.type	t8_l0, @object
	.size	t8_l0, 1
t8_l0:
	.zero	1
	.globl	_x_t8_l0
	.type	_x_t8_l0, @object
	.size	_x_t8_l0, 1
_x_t8_l0:
	.zero	1
	.globl	t8_l1
	.type	t8_l1, @object
	.size	t8_l1, 1
t8_l1:
	.zero	1
	.globl	_x_t8_l1
	.type	_x_t8_l1, @object
	.size	_x_t8_l1, 1
_x_t8_l1:
	.zero	1
	.text
	.globl	main
	.type	main, @function
main:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t12_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t12_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t12_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t12_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t12_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t11_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t11_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t11_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t11_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t11_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t10_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t10_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t10_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t10_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t10_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t9_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t9_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t9_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t9_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t3_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t2_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t2_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t1_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t0_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t1_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t0_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t0_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t0_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t5_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t1_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t0_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t1_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR controller_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t6_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t7_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR gate_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR controller_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t2_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR controller_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t2_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _diverge_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t3_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR controller_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t1_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t2_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR gate_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR controller_z[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR controller_evt2[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR controller_cnt[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t3_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t4_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t3_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t3_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t4_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR gate_y[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t4_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t5_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t4_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR gate_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t4_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t5_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t5_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR gate_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t6_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t5_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t6_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t6_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t6_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t7_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t7_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t8_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t7_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t7_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t8_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t8_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t9_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t8_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t8_l1[rip], al
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t12_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	jne	.L6
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	je	.L7
.L6:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	je	.L7
.L8:
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	je	.L9
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	je	.L7
.L9:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	je	.L4
.L7:
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L10
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L11
.L10:
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L12
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L11
.L12:
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L13
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L11
.L13:
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L4
.L11:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	jne	.L14
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	je	.L15
.L14:
	movss	xmm1, DWORD PTR t12_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L15:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t11_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	jne	.L18
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	je	.L19
.L18:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	je	.L20
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	je	.L19
.L20:
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	je	.L21
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	je	.L19
.L21:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	je	.L4
.L19:
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L22
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L23
.L22:
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L24
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L23
.L24:
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L25
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L23
.L25:
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L4
.L23:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	jne	.L26
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	je	.L27
.L26:
	movss	xmm1, DWORD PTR t11_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L27:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t10_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	jne	.L30
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	je	.L31
.L30:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	je	.L32
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	je	.L31
.L32:
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	je	.L33
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	je	.L31
.L33:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	je	.L4
.L31:
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L34
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L35
.L34:
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L36
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L35
.L36:
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L37
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L35
.L37:
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L4
.L35:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	jne	.L38
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	je	.L39
.L38:
	movss	xmm1, DWORD PTR t10_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L39:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t9_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	jne	.L42
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	je	.L43
.L42:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	je	.L44
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	je	.L43
.L44:
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	je	.L45
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	je	.L43
.L45:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	je	.L4
.L43:
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L46
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L47
.L46:
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L48
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L47
.L48:
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L49
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L47
.L49:
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L4
.L47:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	jne	.L50
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	je	.L51
.L50:
	movss	xmm1, DWORD PTR t9_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L51:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t8_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	jne	.L54
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	je	.L55
.L54:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	je	.L56
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	je	.L55
.L56:
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	je	.L57
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	je	.L55
.L57:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	je	.L4
.L55:
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L58
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L59
.L58:
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L60
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L59
.L60:
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L59
.L61:
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L4
.L59:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	jne	.L62
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	je	.L63
.L62:
	movss	xmm1, DWORD PTR t8_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L63:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t7_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	jne	.L66
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	je	.L67
.L66:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	je	.L68
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	je	.L67
.L68:
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	je	.L69
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	je	.L67
.L69:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	je	.L4
.L67:
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L70
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L71
.L70:
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L72
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L71
.L72:
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L73
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L71
.L73:
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L4
.L71:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	jne	.L74
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	je	.L75
.L74:
	movss	xmm1, DWORD PTR t7_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L75:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t6_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	jne	.L78
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	je	.L79
.L78:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	je	.L80
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	je	.L79
.L80:
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	je	.L79
.L81:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	je	.L4
.L79:
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L82
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L83
.L82:
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L84
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L83
.L84:
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L85
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L83
.L85:
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L4
.L83:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	jne	.L86
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	je	.L87
.L86:
	movss	xmm1, DWORD PTR t6_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L87:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t5_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	jne	.L90
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	je	.L91
.L90:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	je	.L92
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	je	.L91
.L92:
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	je	.L93
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	je	.L91
.L93:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	je	.L4
.L91:
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L94
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L95
.L94:
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L96
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L95
.L96:
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L97
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L95
.L97:
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L4
.L95:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	jne	.L98
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	je	.L99
.L98:
	movss	xmm1, DWORD PTR t5_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L99:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t4_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	jne	.L102
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	je	.L103
.L102:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	je	.L104
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	je	.L103
.L104:
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	je	.L105
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	je	.L103
.L105:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	je	.L4
.L103:
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L106
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L107
.L106:
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L108
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L107
.L108:
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L109
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L107
.L109:
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L4
.L107:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	jne	.L110
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	je	.L111
.L110:
	movss	xmm1, DWORD PTR t4_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L111:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t3_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	jne	.L114
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	je	.L115
.L114:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	je	.L116
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	je	.L115
.L116:
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	je	.L117
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	je	.L115
.L117:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	je	.L4
.L115:
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L118
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L119
.L118:
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L120
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L119
.L120:
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L121
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L119
.L121:
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L4
.L119:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	jne	.L122
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	je	.L123
.L122:
	movss	xmm1, DWORD PTR t3_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L123:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	jne	.L126
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	je	.L127
.L126:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	je	.L128
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	je	.L127
.L128:
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	je	.L129
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	je	.L127
.L129:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	je	.L4
.L127:
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L130
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L131
.L130:
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L132
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L131
.L132:
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L133
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L131
.L133:
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L4
.L131:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	jne	.L134
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	je	.L135
.L134:
	movss	xmm1, DWORD PTR t2_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L135:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	jne	.L138
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L139
.L138:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	je	.L140
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L139
.L140:
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L141
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	je	.L139
.L141:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L4
.L139:
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L142
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L143
.L142:
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L144
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L143
.L144:
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L145
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L143
.L145:
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L4
.L143:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	jne	.L146
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L147
.L146:
	movss	xmm1, DWORD PTR t1_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L147:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	jne	.L150
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L151
.L150:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	je	.L152
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L151
.L152:
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L153
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	je	.L151
.L153:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L4
.L151:
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L154
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L155
.L154:
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L156
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L155
.L156:
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L157
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L155
.L157:
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L4
.L155:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	jne	.L158
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L159
.L158:
	movss	xmm1, DWORD PTR t0_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L159:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR controller_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L162
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L163
.L162:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L164
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L163
.L164:
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L165
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L163
.L165:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L4
.L163:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L166
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L166
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L167
.L166:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L168
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L168
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L167
.L168:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L169
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L169
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L167
.L169:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L170
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L170
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L167
.L170:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L4
.L167:
	mov	eax, DWORD PTR controller_cnt[rip]
	test	eax, eax
	je	.L171
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 1
	je	.L171
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 2
	je	.L171
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 3
	je	.L171
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 4
	je	.L171
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 5
	je	.L171
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 6
	je	.L171
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 7
	je	.L171
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 8
	je	.L171
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 9
	je	.L171
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 10
	je	.L171
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 11
	je	.L171
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 12
	je	.L171
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 13
	je	.L171
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 14
	jne	.L4
.L171:
	movss	xmm1, DWORD PTR controller_z[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L172
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L173
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L4
.L173:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L172
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L4
.L172:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR gate_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	jne	.L175
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L176
.L175:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L177
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L176
.L177:
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L178
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L176
.L178:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L4
.L176:
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L179
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L180
.L179:
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L180
.L181:
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L182
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L180
.L182:
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L4
.L180:
	movss	xmm1, DWORD PTR gate_y[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L183
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L183
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L4
.L183:
	movss	xmm1, DWORD PTR gate_y[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	jnb	.L184
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L184
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	jne	.L4
.L184:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm0, DWORD PTR delta[rip]
	movss	xmm1, DWORD PTR _diverge_delta[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	mov	eax, 1
	jmp	.L187
.L4:
	mov	eax, 0
.L187:
	mov	DWORD PTR -4[rbp], eax
	jmp	.L188
.L712:
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t12_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t12_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t12_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t12_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t12_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t11_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t11_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t11_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t11_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t11_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t10_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t10_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t10_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t10_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t10_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t9_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t9_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t9_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t9_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t3_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t2_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t2_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t1_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t0_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t1_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t0_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t0_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t0_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t5_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t1_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t0_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t1_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_controller_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t6_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t7_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_gate_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_controller_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t2_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_controller_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t2_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x__diverge_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t3_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_controller_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t1_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t2_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_gate_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_controller_z[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_controller_evt2[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_controller_cnt[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t3_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t4_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t3_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t3_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t4_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_gate_y[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t4_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t5_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t4_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_gate_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t4_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t5_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t5_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_gate_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t6_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t5_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t6_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t6_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t6_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t7_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t7_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t8_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t7_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t7_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t8_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t8_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t9_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t8_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t8_l1[rip], al
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	jne	.L189
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	je	.L190
.L189:
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	je	.L191
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	je	.L190
.L191:
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	je	.L192
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	je	.L190
.L192:
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	je	.L193
.L190:
	movzx	eax, BYTE PTR _x_t12_evt0[rip]
	test	al, al
	jne	.L194
	movzx	eax, BYTE PTR _x_t12_evt1[rip]
	test	al, al
	je	.L195
.L194:
	movzx	eax, BYTE PTR _x_t12_evt0[rip]
	test	al, al
	je	.L196
	movzx	eax, BYTE PTR _x_t12_evt1[rip]
	test	al, al
	je	.L195
.L196:
	movzx	eax, BYTE PTR _x_t12_evt1[rip]
	test	al, al
	je	.L197
	movzx	eax, BYTE PTR _x_t12_evt0[rip]
	test	al, al
	je	.L195
.L197:
	movzx	eax, BYTE PTR _x_t12_evt0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_t12_evt1[rip]
	test	al, al
	je	.L193
.L195:
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	jne	.L198
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	je	.L199
.L198:
	movss	xmm1, DWORD PTR _x_t12_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L193
.L199:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L201
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L201
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t12_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t12_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L201
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L202
.L201:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L193
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L202
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L193
.L202:
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	jne	.L205
	movss	xmm0, DWORD PTR _x_t12_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L205
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L206
.L205:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	jne	.L206
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	jne	.L206
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L206
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L206
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	jne	.L193
.L206:
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	je	.L208
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	jne	.L208
	movss	xmm1, DWORD PTR t12_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L208
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L208
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L208
	movss	xmm0, DWORD PTR t12_x[rip]
	movss	xmm1, DWORD PTR _x_t12_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L208
	ucomiss	xmm0, xmm1
	je	.L209
.L208:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	je	.L209
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	jne	.L209
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L209
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L209
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	jne	.L193
.L209:
	movss	xmm0, DWORD PTR t12_x[rip]
	movss	xmm1, DWORD PTR _x_t12_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L211
	ucomiss	xmm0, xmm1
	jne	.L211
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	je	.L211
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	je	.L211
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L211
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	jne	.L213
.L211:
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	je	.L213
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	jne	.L213
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L213
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L213
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	jne	.L193
.L213:
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	jne	.L214
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	jne	.L214
	movss	xmm1, DWORD PTR t12_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L214
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L214
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L214
	movss	xmm0, DWORD PTR t12_x[rip]
	movss	xmm1, DWORD PTR _x_t12_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L214
	ucomiss	xmm0, xmm1
	je	.L216
.L214:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	je	.L216
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	je	.L216
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L216
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L216
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	jne	.L193
.L216:
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	jne	.L218
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	je	.L219
.L218:
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	je	.L220
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	je	.L219
.L220:
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	je	.L221
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	je	.L219
.L221:
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	je	.L193
.L219:
	movzx	eax, BYTE PTR _x_t11_evt0[rip]
	test	al, al
	jne	.L222
	movzx	eax, BYTE PTR _x_t11_evt1[rip]
	test	al, al
	je	.L223
.L222:
	movzx	eax, BYTE PTR _x_t11_evt0[rip]
	test	al, al
	je	.L224
	movzx	eax, BYTE PTR _x_t11_evt1[rip]
	test	al, al
	je	.L223
.L224:
	movzx	eax, BYTE PTR _x_t11_evt1[rip]
	test	al, al
	je	.L225
	movzx	eax, BYTE PTR _x_t11_evt0[rip]
	test	al, al
	je	.L223
.L225:
	movzx	eax, BYTE PTR _x_t11_evt0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_t11_evt1[rip]
	test	al, al
	je	.L193
.L223:
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	jne	.L226
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	je	.L227
.L226:
	movss	xmm1, DWORD PTR _x_t11_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L193
.L227:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L229
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L229
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t11_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t11_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L229
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L230
.L229:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L193
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L230
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L193
.L230:
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	je	.L233
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	jne	.L233
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L233
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	jne	.L233
	movss	xmm0, DWORD PTR _x_t11_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L233
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L234
.L233:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	jne	.L234
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	jne	.L234
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L234
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L234
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	jne	.L193
.L234:
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	je	.L236
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	jne	.L236
	movss	xmm1, DWORD PTR t11_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L236
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L236
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L236
	movss	xmm0, DWORD PTR t11_x[rip]
	movss	xmm1, DWORD PTR _x_t11_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L236
	ucomiss	xmm0, xmm1
	je	.L237
.L236:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	je	.L237
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	jne	.L237
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L237
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L237
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	jne	.L193
.L237:
	movss	xmm0, DWORD PTR t11_x[rip]
	movss	xmm1, DWORD PTR _x_t11_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L239
	ucomiss	xmm0, xmm1
	jne	.L239
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	je	.L239
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	je	.L239
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L239
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	jne	.L241
.L239:
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	jne	.L241
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L241
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L241
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	jne	.L193
.L241:
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	jne	.L242
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	jne	.L242
	movss	xmm1, DWORD PTR t11_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L242
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L242
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L242
	movss	xmm0, DWORD PTR t11_x[rip]
	movss	xmm1, DWORD PTR _x_t11_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L242
	ucomiss	xmm0, xmm1
	je	.L244
.L242:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	je	.L244
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	je	.L244
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L244
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L244
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	jne	.L193
.L244:
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	je	.L247
.L246:
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	je	.L248
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	je	.L247
.L248:
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	je	.L249
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	je	.L247
.L249:
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	je	.L193
.L247:
	movzx	eax, BYTE PTR _x_t10_evt0[rip]
	test	al, al
	jne	.L250
	movzx	eax, BYTE PTR _x_t10_evt1[rip]
	test	al, al
	je	.L251
.L250:
	movzx	eax, BYTE PTR _x_t10_evt0[rip]
	test	al, al
	je	.L252
	movzx	eax, BYTE PTR _x_t10_evt1[rip]
	test	al, al
	je	.L251
.L252:
	movzx	eax, BYTE PTR _x_t10_evt1[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t10_evt0[rip]
	test	al, al
	je	.L251
.L253:
	movzx	eax, BYTE PTR _x_t10_evt0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_t10_evt1[rip]
	test	al, al
	je	.L193
.L251:
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	jne	.L254
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	je	.L255
.L254:
	movss	xmm1, DWORD PTR _x_t10_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L193
.L255:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L257
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L257
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t10_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t10_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L257
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L258
.L257:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L193
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L258
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L193
.L258:
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	je	.L261
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	jne	.L261
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L261
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	jne	.L261
	movss	xmm0, DWORD PTR _x_t10_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L261
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L262
.L261:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	jne	.L262
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	jne	.L262
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L262
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L262
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	jne	.L193
.L262:
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	je	.L264
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	jne	.L264
	movss	xmm1, DWORD PTR t10_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L264
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L264
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L264
	movss	xmm0, DWORD PTR t10_x[rip]
	movss	xmm1, DWORD PTR _x_t10_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L264
	ucomiss	xmm0, xmm1
	je	.L265
.L264:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	je	.L265
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	jne	.L265
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L265
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L265
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	jne	.L193
.L265:
	movss	xmm0, DWORD PTR t10_x[rip]
	movss	xmm1, DWORD PTR _x_t10_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L267
	ucomiss	xmm0, xmm1
	jne	.L267
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	je	.L267
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	je	.L267
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L267
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	jne	.L269
.L267:
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	je	.L269
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	jne	.L269
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L269
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L269
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	jne	.L193
.L269:
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	jne	.L270
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	jne	.L270
	movss	xmm1, DWORD PTR t10_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L270
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L270
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L270
	movss	xmm0, DWORD PTR t10_x[rip]
	movss	xmm1, DWORD PTR _x_t10_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L270
	ucomiss	xmm0, xmm1
	je	.L272
.L270:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	je	.L272
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	je	.L272
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L272
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L272
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	jne	.L193
.L272:
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	jne	.L274
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	je	.L275
.L274:
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	je	.L276
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	je	.L275
.L276:
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	je	.L277
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	je	.L275
.L277:
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	je	.L193
.L275:
	movzx	eax, BYTE PTR _x_t9_evt0[rip]
	test	al, al
	jne	.L278
	movzx	eax, BYTE PTR _x_t9_evt1[rip]
	test	al, al
	je	.L279
.L278:
	movzx	eax, BYTE PTR _x_t9_evt0[rip]
	test	al, al
	je	.L280
	movzx	eax, BYTE PTR _x_t9_evt1[rip]
	test	al, al
	je	.L279
.L280:
	movzx	eax, BYTE PTR _x_t9_evt1[rip]
	test	al, al
	je	.L281
	movzx	eax, BYTE PTR _x_t9_evt0[rip]
	test	al, al
	je	.L279
.L281:
	movzx	eax, BYTE PTR _x_t9_evt0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_t9_evt1[rip]
	test	al, al
	je	.L193
.L279:
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	jne	.L282
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	je	.L283
.L282:
	movss	xmm1, DWORD PTR _x_t9_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L193
.L283:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L285
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L285
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t9_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t9_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L285
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L286
.L285:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L193
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L286
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L193
.L286:
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	je	.L289
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	jne	.L289
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L289
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	jne	.L289
	movss	xmm0, DWORD PTR _x_t9_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L289
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L290
.L289:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	jne	.L290
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	jne	.L290
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L290
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L290
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	jne	.L193
.L290:
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	je	.L292
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	jne	.L292
	movss	xmm1, DWORD PTR t9_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L292
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L292
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L292
	movss	xmm0, DWORD PTR t9_x[rip]
	movss	xmm1, DWORD PTR _x_t9_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L292
	ucomiss	xmm0, xmm1
	je	.L293
.L292:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	je	.L293
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	jne	.L293
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L293
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L293
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	jne	.L193
.L293:
	movss	xmm0, DWORD PTR t9_x[rip]
	movss	xmm1, DWORD PTR _x_t9_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L295
	ucomiss	xmm0, xmm1
	jne	.L295
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	je	.L295
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	je	.L295
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L295
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	jne	.L297
.L295:
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	je	.L297
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	jne	.L297
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L297
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L297
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	jne	.L193
.L297:
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	jne	.L298
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	jne	.L298
	movss	xmm1, DWORD PTR t9_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L298
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L298
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L298
	movss	xmm0, DWORD PTR t9_x[rip]
	movss	xmm1, DWORD PTR _x_t9_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L298
	ucomiss	xmm0, xmm1
	je	.L300
.L298:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	je	.L300
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	je	.L300
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L300
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L300
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	jne	.L193
.L300:
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	jne	.L302
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	je	.L303
.L302:
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	je	.L304
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	je	.L303
.L304:
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	je	.L305
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	je	.L303
.L305:
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	je	.L193
.L303:
	movzx	eax, BYTE PTR _x_t8_evt0[rip]
	test	al, al
	jne	.L306
	movzx	eax, BYTE PTR _x_t8_evt1[rip]
	test	al, al
	je	.L307
.L306:
	movzx	eax, BYTE PTR _x_t8_evt0[rip]
	test	al, al
	je	.L308
	movzx	eax, BYTE PTR _x_t8_evt1[rip]
	test	al, al
	je	.L307
.L308:
	movzx	eax, BYTE PTR _x_t8_evt1[rip]
	test	al, al
	je	.L309
	movzx	eax, BYTE PTR _x_t8_evt0[rip]
	test	al, al
	je	.L307
.L309:
	movzx	eax, BYTE PTR _x_t8_evt0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_t8_evt1[rip]
	test	al, al
	je	.L193
.L307:
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	jne	.L310
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	je	.L311
.L310:
	movss	xmm1, DWORD PTR _x_t8_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L193
.L311:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L313
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L313
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t8_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t8_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L313
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L314
.L313:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L193
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L314
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L193
.L314:
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	je	.L317
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	jne	.L317
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L317
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	jne	.L317
	movss	xmm0, DWORD PTR _x_t8_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L317
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L318
.L317:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	jne	.L318
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	jne	.L318
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L318
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L318
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	jne	.L193
.L318:
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	je	.L320
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	jne	.L320
	movss	xmm1, DWORD PTR t8_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L320
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L320
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L320
	movss	xmm0, DWORD PTR t8_x[rip]
	movss	xmm1, DWORD PTR _x_t8_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L320
	ucomiss	xmm0, xmm1
	je	.L321
.L320:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	je	.L321
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	jne	.L321
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L321
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L321
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	jne	.L193
.L321:
	movss	xmm0, DWORD PTR t8_x[rip]
	movss	xmm1, DWORD PTR _x_t8_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L323
	ucomiss	xmm0, xmm1
	jne	.L323
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	je	.L323
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	je	.L323
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L323
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	jne	.L325
.L323:
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	je	.L325
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	jne	.L325
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L325
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L325
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	jne	.L193
.L325:
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	jne	.L326
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	jne	.L326
	movss	xmm1, DWORD PTR t8_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L326
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L326
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L326
	movss	xmm0, DWORD PTR t8_x[rip]
	movss	xmm1, DWORD PTR _x_t8_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L326
	ucomiss	xmm0, xmm1
	je	.L328
.L326:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	je	.L328
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	je	.L328
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L328
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L328
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	jne	.L193
.L328:
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	jne	.L330
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	je	.L331
.L330:
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	je	.L332
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	je	.L331
.L332:
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	je	.L333
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	je	.L331
.L333:
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	je	.L193
.L331:
	movzx	eax, BYTE PTR _x_t7_evt0[rip]
	test	al, al
	jne	.L334
	movzx	eax, BYTE PTR _x_t7_evt1[rip]
	test	al, al
	je	.L335
.L334:
	movzx	eax, BYTE PTR _x_t7_evt0[rip]
	test	al, al
	je	.L336
	movzx	eax, BYTE PTR _x_t7_evt1[rip]
	test	al, al
	je	.L335
.L336:
	movzx	eax, BYTE PTR _x_t7_evt1[rip]
	test	al, al
	je	.L337
	movzx	eax, BYTE PTR _x_t7_evt0[rip]
	test	al, al
	je	.L335
.L337:
	movzx	eax, BYTE PTR _x_t7_evt0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_t7_evt1[rip]
	test	al, al
	je	.L193
.L335:
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	jne	.L338
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	je	.L339
.L338:
	movss	xmm1, DWORD PTR _x_t7_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L193
.L339:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L341
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L341
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t7_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t7_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L341
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L342
.L341:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L193
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L342
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L193
.L342:
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	je	.L345
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	jne	.L345
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L345
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	jne	.L345
	movss	xmm0, DWORD PTR _x_t7_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L345
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L346
.L345:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	jne	.L346
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	jne	.L346
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L346
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L346
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	jne	.L193
.L346:
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	je	.L348
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	jne	.L348
	movss	xmm1, DWORD PTR t7_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L348
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L348
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L348
	movss	xmm0, DWORD PTR t7_x[rip]
	movss	xmm1, DWORD PTR _x_t7_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L348
	ucomiss	xmm0, xmm1
	je	.L349
.L348:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	je	.L349
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	jne	.L349
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L349
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L349
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	jne	.L193
.L349:
	movss	xmm0, DWORD PTR t7_x[rip]
	movss	xmm1, DWORD PTR _x_t7_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L351
	ucomiss	xmm0, xmm1
	jne	.L351
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	je	.L351
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	je	.L351
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L351
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	jne	.L353
.L351:
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	je	.L353
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	jne	.L353
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L353
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L353
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	jne	.L193
.L353:
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	jne	.L354
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	jne	.L354
	movss	xmm1, DWORD PTR t7_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L354
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L354
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L354
	movss	xmm0, DWORD PTR t7_x[rip]
	movss	xmm1, DWORD PTR _x_t7_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L354
	ucomiss	xmm0, xmm1
	je	.L356
.L354:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	je	.L356
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	je	.L356
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L356
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L356
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	jne	.L193
.L356:
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	jne	.L358
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	je	.L359
.L358:
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	je	.L360
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	je	.L359
.L360:
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	je	.L361
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	je	.L359
.L361:
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	je	.L193
.L359:
	movzx	eax, BYTE PTR _x_t6_evt0[rip]
	test	al, al
	jne	.L362
	movzx	eax, BYTE PTR _x_t6_evt1[rip]
	test	al, al
	je	.L363
.L362:
	movzx	eax, BYTE PTR _x_t6_evt0[rip]
	test	al, al
	je	.L364
	movzx	eax, BYTE PTR _x_t6_evt1[rip]
	test	al, al
	je	.L363
.L364:
	movzx	eax, BYTE PTR _x_t6_evt1[rip]
	test	al, al
	je	.L365
	movzx	eax, BYTE PTR _x_t6_evt0[rip]
	test	al, al
	je	.L363
.L365:
	movzx	eax, BYTE PTR _x_t6_evt0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_t6_evt1[rip]
	test	al, al
	je	.L193
.L363:
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	jne	.L366
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	je	.L367
.L366:
	movss	xmm1, DWORD PTR _x_t6_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L193
.L367:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L369
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L369
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t6_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t6_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L369
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L370
.L369:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L193
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L370
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L193
.L370:
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	je	.L373
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	jne	.L373
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L373
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	jne	.L373
	movss	xmm0, DWORD PTR _x_t6_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L373
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L374
.L373:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	jne	.L374
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	jne	.L374
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L374
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L374
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	jne	.L193
.L374:
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	je	.L376
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	jne	.L376
	movss	xmm1, DWORD PTR t6_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L376
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L376
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L376
	movss	xmm0, DWORD PTR t6_x[rip]
	movss	xmm1, DWORD PTR _x_t6_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L376
	ucomiss	xmm0, xmm1
	je	.L377
.L376:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	je	.L377
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	jne	.L377
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L377
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L377
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	jne	.L193
.L377:
	movss	xmm0, DWORD PTR t6_x[rip]
	movss	xmm1, DWORD PTR _x_t6_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L379
	ucomiss	xmm0, xmm1
	jne	.L379
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	je	.L379
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	je	.L379
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L379
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	jne	.L381
.L379:
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	je	.L381
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	jne	.L381
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L381
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L381
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	jne	.L193
.L381:
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	jne	.L382
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	jne	.L382
	movss	xmm1, DWORD PTR t6_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L382
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L382
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L382
	movss	xmm0, DWORD PTR t6_x[rip]
	movss	xmm1, DWORD PTR _x_t6_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L382
	ucomiss	xmm0, xmm1
	je	.L384
.L382:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	je	.L384
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	je	.L384
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L384
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L384
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	jne	.L193
.L384:
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	jne	.L386
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	je	.L387
.L386:
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	je	.L388
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	je	.L387
.L388:
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	je	.L389
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	je	.L387
.L389:
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	je	.L193
.L387:
	movzx	eax, BYTE PTR _x_t5_evt0[rip]
	test	al, al
	jne	.L390
	movzx	eax, BYTE PTR _x_t5_evt1[rip]
	test	al, al
	je	.L391
.L390:
	movzx	eax, BYTE PTR _x_t5_evt0[rip]
	test	al, al
	je	.L392
	movzx	eax, BYTE PTR _x_t5_evt1[rip]
	test	al, al
	je	.L391
.L392:
	movzx	eax, BYTE PTR _x_t5_evt1[rip]
	test	al, al
	je	.L393
	movzx	eax, BYTE PTR _x_t5_evt0[rip]
	test	al, al
	je	.L391
.L393:
	movzx	eax, BYTE PTR _x_t5_evt0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_t5_evt1[rip]
	test	al, al
	je	.L193
.L391:
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	jne	.L394
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	je	.L395
.L394:
	movss	xmm1, DWORD PTR _x_t5_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L193
.L395:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L397
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L397
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t5_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t5_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L397
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L398
.L397:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L193
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L398
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L193
.L398:
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	je	.L401
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	jne	.L401
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L401
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	jne	.L401
	movss	xmm0, DWORD PTR _x_t5_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L401
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L402
.L401:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	jne	.L402
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	jne	.L402
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L402
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L402
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	jne	.L193
.L402:
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	je	.L404
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	jne	.L404
	movss	xmm1, DWORD PTR t5_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L404
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L404
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L404
	movss	xmm0, DWORD PTR t5_x[rip]
	movss	xmm1, DWORD PTR _x_t5_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L404
	ucomiss	xmm0, xmm1
	je	.L405
.L404:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	je	.L405
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	jne	.L405
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L405
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L405
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	jne	.L193
.L405:
	movss	xmm0, DWORD PTR t5_x[rip]
	movss	xmm1, DWORD PTR _x_t5_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L407
	ucomiss	xmm0, xmm1
	jne	.L407
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	je	.L407
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	je	.L407
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L407
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	jne	.L409
.L407:
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	je	.L409
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	jne	.L409
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L409
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L409
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	jne	.L193
.L409:
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	jne	.L410
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	jne	.L410
	movss	xmm1, DWORD PTR t5_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L410
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L410
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L410
	movss	xmm0, DWORD PTR t5_x[rip]
	movss	xmm1, DWORD PTR _x_t5_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L410
	ucomiss	xmm0, xmm1
	je	.L412
.L410:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	je	.L412
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	je	.L412
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L412
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L412
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	jne	.L193
.L412:
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	jne	.L414
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	je	.L415
.L414:
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	je	.L416
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	je	.L415
.L416:
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	je	.L417
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	je	.L415
.L417:
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	je	.L193
.L415:
	movzx	eax, BYTE PTR _x_t4_evt0[rip]
	test	al, al
	jne	.L418
	movzx	eax, BYTE PTR _x_t4_evt1[rip]
	test	al, al
	je	.L419
.L418:
	movzx	eax, BYTE PTR _x_t4_evt0[rip]
	test	al, al
	je	.L420
	movzx	eax, BYTE PTR _x_t4_evt1[rip]
	test	al, al
	je	.L419
.L420:
	movzx	eax, BYTE PTR _x_t4_evt1[rip]
	test	al, al
	je	.L421
	movzx	eax, BYTE PTR _x_t4_evt0[rip]
	test	al, al
	je	.L419
.L421:
	movzx	eax, BYTE PTR _x_t4_evt0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_t4_evt1[rip]
	test	al, al
	je	.L193
.L419:
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	jne	.L422
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	je	.L423
.L422:
	movss	xmm1, DWORD PTR _x_t4_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L193
.L423:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L425
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L425
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t4_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t4_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L425
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L426
.L425:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L193
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L426
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L193
.L426:
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	je	.L429
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	jne	.L429
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L429
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	jne	.L429
	movss	xmm0, DWORD PTR _x_t4_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L429
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L430
.L429:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	jne	.L430
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	jne	.L430
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L430
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L430
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	jne	.L193
.L430:
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	je	.L432
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	jne	.L432
	movss	xmm1, DWORD PTR t4_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L432
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L432
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L432
	movss	xmm0, DWORD PTR t4_x[rip]
	movss	xmm1, DWORD PTR _x_t4_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L432
	ucomiss	xmm0, xmm1
	je	.L433
.L432:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	je	.L433
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	jne	.L433
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L433
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L433
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	jne	.L193
.L433:
	movss	xmm0, DWORD PTR t4_x[rip]
	movss	xmm1, DWORD PTR _x_t4_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L435
	ucomiss	xmm0, xmm1
	jne	.L435
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	je	.L435
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	je	.L435
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L435
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	jne	.L437
.L435:
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	je	.L437
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	jne	.L437
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L437
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L437
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	jne	.L193
.L437:
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	jne	.L438
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	jne	.L438
	movss	xmm1, DWORD PTR t4_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L438
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L438
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L438
	movss	xmm0, DWORD PTR t4_x[rip]
	movss	xmm1, DWORD PTR _x_t4_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L438
	ucomiss	xmm0, xmm1
	je	.L440
.L438:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	je	.L440
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	je	.L440
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L440
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L440
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	jne	.L193
.L440:
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	jne	.L442
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	je	.L443
.L442:
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	je	.L444
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	je	.L443
.L444:
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	je	.L445
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	je	.L443
.L445:
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	je	.L193
.L443:
	movzx	eax, BYTE PTR _x_t3_evt0[rip]
	test	al, al
	jne	.L446
	movzx	eax, BYTE PTR _x_t3_evt1[rip]
	test	al, al
	je	.L447
.L446:
	movzx	eax, BYTE PTR _x_t3_evt0[rip]
	test	al, al
	je	.L448
	movzx	eax, BYTE PTR _x_t3_evt1[rip]
	test	al, al
	je	.L447
.L448:
	movzx	eax, BYTE PTR _x_t3_evt1[rip]
	test	al, al
	je	.L449
	movzx	eax, BYTE PTR _x_t3_evt0[rip]
	test	al, al
	je	.L447
.L449:
	movzx	eax, BYTE PTR _x_t3_evt0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_t3_evt1[rip]
	test	al, al
	je	.L193
.L447:
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	jne	.L450
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	je	.L451
.L450:
	movss	xmm1, DWORD PTR _x_t3_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L193
.L451:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L453
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L453
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t3_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t3_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L453
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L454
.L453:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L193
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L454
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L193
.L454:
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	je	.L457
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	jne	.L457
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L457
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	jne	.L457
	movss	xmm0, DWORD PTR _x_t3_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L457
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L458
.L457:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	jne	.L458
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	jne	.L458
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L458
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L458
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	jne	.L193
.L458:
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	je	.L460
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	jne	.L460
	movss	xmm1, DWORD PTR t3_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L460
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L460
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L460
	movss	xmm0, DWORD PTR t3_x[rip]
	movss	xmm1, DWORD PTR _x_t3_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L460
	ucomiss	xmm0, xmm1
	je	.L461
.L460:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	je	.L461
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	jne	.L461
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L461
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L461
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	jne	.L193
.L461:
	movss	xmm0, DWORD PTR t3_x[rip]
	movss	xmm1, DWORD PTR _x_t3_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L463
	ucomiss	xmm0, xmm1
	jne	.L463
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	je	.L463
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	je	.L463
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L463
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	jne	.L465
.L463:
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	je	.L465
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	jne	.L465
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L465
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L465
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	jne	.L193
.L465:
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	jne	.L466
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	jne	.L466
	movss	xmm1, DWORD PTR t3_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L466
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L466
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L466
	movss	xmm0, DWORD PTR t3_x[rip]
	movss	xmm1, DWORD PTR _x_t3_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L466
	ucomiss	xmm0, xmm1
	je	.L468
.L466:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	je	.L468
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	je	.L468
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L468
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L468
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	jne	.L193
.L468:
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	jne	.L470
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	je	.L471
.L470:
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	je	.L472
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	je	.L471
.L472:
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	je	.L473
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	je	.L471
.L473:
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	je	.L193
.L471:
	movzx	eax, BYTE PTR _x_t2_evt0[rip]
	test	al, al
	jne	.L474
	movzx	eax, BYTE PTR _x_t2_evt1[rip]
	test	al, al
	je	.L475
.L474:
	movzx	eax, BYTE PTR _x_t2_evt0[rip]
	test	al, al
	je	.L476
	movzx	eax, BYTE PTR _x_t2_evt1[rip]
	test	al, al
	je	.L475
.L476:
	movzx	eax, BYTE PTR _x_t2_evt1[rip]
	test	al, al
	je	.L477
	movzx	eax, BYTE PTR _x_t2_evt0[rip]
	test	al, al
	je	.L475
.L477:
	movzx	eax, BYTE PTR _x_t2_evt0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_t2_evt1[rip]
	test	al, al
	je	.L193
.L475:
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	jne	.L478
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	je	.L479
.L478:
	movss	xmm1, DWORD PTR _x_t2_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L193
.L479:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L481
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L481
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t2_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t2_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L481
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L482
.L481:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L193
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L482
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L193
.L482:
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	je	.L485
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	jne	.L485
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L485
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	jne	.L485
	movss	xmm0, DWORD PTR _x_t2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L485
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L486
.L485:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	jne	.L486
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	jne	.L486
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L486
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L486
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	jne	.L193
.L486:
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	je	.L488
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	jne	.L488
	movss	xmm1, DWORD PTR t2_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L488
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L488
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L488
	movss	xmm0, DWORD PTR t2_x[rip]
	movss	xmm1, DWORD PTR _x_t2_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L488
	ucomiss	xmm0, xmm1
	je	.L489
.L488:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	je	.L489
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	jne	.L489
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L489
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L489
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	jne	.L193
.L489:
	movss	xmm0, DWORD PTR t2_x[rip]
	movss	xmm1, DWORD PTR _x_t2_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L491
	ucomiss	xmm0, xmm1
	jne	.L491
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	je	.L491
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	je	.L491
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L491
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	jne	.L493
.L491:
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	je	.L493
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	jne	.L493
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L493
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L493
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	jne	.L193
.L493:
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	jne	.L494
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	jne	.L494
	movss	xmm1, DWORD PTR t2_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L494
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L494
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L494
	movss	xmm0, DWORD PTR t2_x[rip]
	movss	xmm1, DWORD PTR _x_t2_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L494
	ucomiss	xmm0, xmm1
	je	.L496
.L494:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	je	.L496
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	je	.L496
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L496
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L496
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	jne	.L193
.L496:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	jne	.L498
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L499
.L498:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	je	.L500
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L499
.L500:
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L501
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	je	.L499
.L501:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L193
.L499:
	movzx	eax, BYTE PTR _x_t1_evt0[rip]
	test	al, al
	jne	.L502
	movzx	eax, BYTE PTR _x_t1_evt1[rip]
	test	al, al
	je	.L503
.L502:
	movzx	eax, BYTE PTR _x_t1_evt0[rip]
	test	al, al
	je	.L504
	movzx	eax, BYTE PTR _x_t1_evt1[rip]
	test	al, al
	je	.L503
.L504:
	movzx	eax, BYTE PTR _x_t1_evt1[rip]
	test	al, al
	je	.L505
	movzx	eax, BYTE PTR _x_t1_evt0[rip]
	test	al, al
	je	.L503
.L505:
	movzx	eax, BYTE PTR _x_t1_evt0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_t1_evt1[rip]
	test	al, al
	je	.L193
.L503:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	jne	.L506
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L507
.L506:
	movss	xmm1, DWORD PTR _x_t1_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L193
.L507:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L509
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L509
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t1_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t1_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L509
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L510
.L509:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L193
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L510
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L193
.L510:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	je	.L513
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	jne	.L513
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L513
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L513
	movss	xmm0, DWORD PTR _x_t1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L513
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L514
.L513:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	jne	.L514
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	jne	.L514
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L514
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L514
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L193
.L514:
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L516
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	jne	.L516
	movss	xmm1, DWORD PTR t1_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L516
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L516
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L516
	movss	xmm0, DWORD PTR t1_x[rip]
	movss	xmm1, DWORD PTR _x_t1_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L516
	ucomiss	xmm0, xmm1
	je	.L517
.L516:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	je	.L517
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	jne	.L517
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L517
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L517
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L193
.L517:
	movss	xmm0, DWORD PTR t1_x[rip]
	movss	xmm1, DWORD PTR _x_t1_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L519
	ucomiss	xmm0, xmm1
	jne	.L519
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	je	.L519
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L519
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L519
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L521
.L519:
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L521
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	jne	.L521
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L521
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L521
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L193
.L521:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	jne	.L522
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	jne	.L522
	movss	xmm1, DWORD PTR t1_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L522
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L522
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L522
	movss	xmm0, DWORD PTR t1_x[rip]
	movss	xmm1, DWORD PTR _x_t1_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L522
	ucomiss	xmm0, xmm1
	je	.L524
.L522:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	je	.L524
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L524
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L524
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L524
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L193
.L524:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	jne	.L526
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L527
.L526:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	je	.L528
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L527
.L528:
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L529
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	je	.L527
.L529:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L193
.L527:
	movzx	eax, BYTE PTR _x_t0_evt0[rip]
	test	al, al
	jne	.L530
	movzx	eax, BYTE PTR _x_t0_evt1[rip]
	test	al, al
	je	.L531
.L530:
	movzx	eax, BYTE PTR _x_t0_evt0[rip]
	test	al, al
	je	.L532
	movzx	eax, BYTE PTR _x_t0_evt1[rip]
	test	al, al
	je	.L531
.L532:
	movzx	eax, BYTE PTR _x_t0_evt1[rip]
	test	al, al
	je	.L533
	movzx	eax, BYTE PTR _x_t0_evt0[rip]
	test	al, al
	je	.L531
.L533:
	movzx	eax, BYTE PTR _x_t0_evt0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_t0_evt1[rip]
	test	al, al
	je	.L193
.L531:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	jne	.L534
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L535
.L534:
	movss	xmm1, DWORD PTR _x_t0_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L193
.L535:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L537
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L537
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t0_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t0_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L537
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L538
.L537:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L193
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L538
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L193
.L538:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	je	.L541
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	jne	.L541
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L541
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L541
	movss	xmm0, DWORD PTR _x_t0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L541
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L542
.L541:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	jne	.L542
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	jne	.L542
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L542
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L542
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L193
.L542:
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L544
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	jne	.L544
	movss	xmm1, DWORD PTR t0_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L544
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L544
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L544
	movss	xmm0, DWORD PTR t0_x[rip]
	movss	xmm1, DWORD PTR _x_t0_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L544
	ucomiss	xmm0, xmm1
	je	.L545
.L544:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	je	.L545
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	jne	.L545
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L545
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L545
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L193
.L545:
	movss	xmm0, DWORD PTR t0_x[rip]
	movss	xmm1, DWORD PTR _x_t0_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L547
	ucomiss	xmm0, xmm1
	jne	.L547
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	je	.L547
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L547
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L547
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L549
.L547:
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L549
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	jne	.L549
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L549
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L549
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L193
.L549:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	jne	.L550
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	jne	.L550
	movss	xmm1, DWORD PTR t0_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L550
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L550
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L550
	movss	xmm0, DWORD PTR t0_x[rip]
	movss	xmm1, DWORD PTR _x_t0_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L550
	ucomiss	xmm0, xmm1
	je	.L552
.L550:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	je	.L552
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L552
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L552
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L552
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L193
.L552:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	jne	.L554
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L555
.L554:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L556
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L555
.L556:
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L557
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L555
.L557:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L193
.L555:
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	test	al, al
	jne	.L558
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	test	al, al
	jne	.L558
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	test	al, al
	je	.L559
.L558:
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	test	al, al
	jne	.L560
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	test	al, al
	je	.L560
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	test	al, al
	je	.L559
.L560:
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	test	al, al
	jne	.L561
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	test	al, al
	je	.L561
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	test	al, al
	je	.L559
.L561:
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	test	al, al
	jne	.L562
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	test	al, al
	je	.L562
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	test	al, al
	jne	.L559
.L562:
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	test	al, al
	jne	.L193
.L559:
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	test	eax, eax
	je	.L563
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 1
	je	.L563
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 2
	je	.L563
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 3
	je	.L563
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 4
	je	.L563
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 5
	je	.L563
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 6
	je	.L563
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 7
	je	.L563
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 8
	je	.L563
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 9
	je	.L563
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 10
	je	.L563
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 11
	je	.L563
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 12
	je	.L563
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 13
	je	.L563
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 14
	jne	.L193
.L563:
	movss	xmm1, DWORD PTR _x_controller_z[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L564
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L565
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L193
.L565:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L564
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	jne	.L193
.L564:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L566
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L566
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR controller_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_controller_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L566
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L566
	mov	edx, DWORD PTR controller_cnt[rip]
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	edx, eax
	je	.L568
.L566:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L193
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L568
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L568
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L193
.L568:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L570
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	jne	.L570
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L570
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L570
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L570
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 1
	jne	.L570
	movss	xmm0, DWORD PTR _x_controller_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L570
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L571
.L570:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L571
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L571
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L571
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L571
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L193
.L571:
	movss	xmm0, DWORD PTR controller_z[rip]
	movss	xmm1, DWORD PTR _x_controller_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L573
	ucomiss	xmm0, xmm1
	jne	.L573
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L575
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L576
.L575:
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L573
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L576
.L573:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L576
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L576
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L576
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L576
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L193
.L576:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L577
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L577
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L577
	mov	eax, DWORD PTR controller_cnt[rip]
	mov	edx, DWORD PTR _x_controller_cnt[rip]
	sub	eax, edx
	cmp	eax, -1
	je	.L578
.L577:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L579
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L579
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L579
	mov	eax, DWORD PTR controller_cnt[rip]
	mov	edx, DWORD PTR _x_controller_cnt[rip]
	sub	eax, edx
	cmp	eax, 1
	je	.L578
.L579:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L578
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L578
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L580
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L580
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L578
.L580:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L578
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L578
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L578
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L193
.L578:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L581
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L581
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L581
	mov	edx, DWORD PTR controller_cnt[rip]
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	edx, eax
	jne	.L581
	movss	xmm0, DWORD PTR controller_z[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	ucomiss	xmm0, xmm1
	jp	.L581
	movss	xmm1, DWORD PTR .LC2[rip]
	ucomiss	xmm0, xmm1
	je	.L582
.L581:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L582
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L582
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L584
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L584
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L582
.L584:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L582
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L582
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L582
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L193
.L582:
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L585
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L586
.L585:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L587
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	jne	.L586
.L587:
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L586
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L586
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L586
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L586
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L193
.L586:
	movss	xmm0, DWORD PTR controller_z[rip]
	movss	xmm1, DWORD PTR _x_controller_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L588
	ucomiss	xmm0, xmm1
	jne	.L588
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L590
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L590
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L590
	mov	eax, DWORD PTR controller_cnt[rip]
	mov	edx, DWORD PTR _x_controller_cnt[rip]
	sub	eax, edx
	cmp	eax, -1
	je	.L591
.L590:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L588
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L588
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L588
	mov	eax, DWORD PTR controller_cnt[rip]
	mov	edx, DWORD PTR _x_controller_cnt[rip]
	sub	eax, edx
	cmp	eax, 1
	jne	.L588
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 1
	jg	.L591
.L588:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L591
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L591
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L592
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L592
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L591
.L592:
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L591
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L591
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L591
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L193
.L591:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L593
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L593
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L593
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 1
	jne	.L593
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	test	eax, eax
	jne	.L593
	movss	xmm0, DWORD PTR _x_controller_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L593
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L594
.L593:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L594
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L594
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L596
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L596
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L594
.L596:
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L594
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L594
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L594
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	jne	.L193
.L594:
	movss	xmm0, DWORD PTR controller_z[rip]
	movss	xmm1, DWORD PTR _x_controller_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L597
	ucomiss	xmm0, xmm1
	jne	.L597
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	jne	.L599
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L600
.L599:
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L597
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L600
.L597:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L600
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L600
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L600
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L600
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L193
.L600:
	mov	eax, DWORD PTR controller_cnt[rip]
	mov	edx, DWORD PTR _x_controller_cnt[rip]
	sub	eax, edx
	cmp	eax, -1
	jne	.L601
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L601
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L601
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L601
	movss	xmm1, DWORD PTR controller_z[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L602
.L601:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L602
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L602
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L603
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L603
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L602
.L603:
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L602
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	jne	.L602
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L602
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L193
.L602:
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	jne	.L604
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L605
.L604:
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L606
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L605
.L606:
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L607
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L605
.L607:
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L193
.L605:
	movzx	eax, BYTE PTR _x_gate_evt0[rip]
	test	al, al
	jne	.L608
	movzx	eax, BYTE PTR _x_gate_evt1[rip]
	test	al, al
	je	.L609
.L608:
	movzx	eax, BYTE PTR _x_gate_evt0[rip]
	test	al, al
	je	.L610
	movzx	eax, BYTE PTR _x_gate_evt1[rip]
	test	al, al
	je	.L609
.L610:
	movzx	eax, BYTE PTR _x_gate_evt1[rip]
	test	al, al
	je	.L611
	movzx	eax, BYTE PTR _x_gate_evt0[rip]
	test	al, al
	je	.L609
.L611:
	movzx	eax, BYTE PTR _x_gate_evt0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_gate_evt1[rip]
	test	al, al
	je	.L193
.L609:
	movss	xmm1, DWORD PTR _x_gate_y[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L612
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L612
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L193
.L612:
	movss	xmm1, DWORD PTR _x_gate_y[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	jnb	.L613
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L613
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	jne	.L193
.L613:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L614
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L614
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR gate_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_gate_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L614
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L615
.L614:
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L617
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L193
.L617:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L193
.L615:
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L619
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	jne	.L619
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L619
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L619
	movss	xmm0, DWORD PTR _x_gate_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L619
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L620
.L619:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	jne	.L620
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	jne	.L620
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L620
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L620
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L193
.L620:
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L622
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	jne	.L622
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L622
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L622
	movss	xmm1, DWORD PTR gate_y[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jb	.L622
	movss	xmm0, DWORD PTR gate_y[rip]
	movss	xmm1, DWORD PTR _x_gate_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L622
	ucomiss	xmm0, xmm1
	je	.L624
.L622:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L624
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	jne	.L624
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L624
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L624
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L193
.L624:
	movss	xmm0, DWORD PTR _x_gate_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L626
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L626
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L626
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L626
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L626
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L628
.L626:
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L628
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	jne	.L628
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L628
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L628
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L193
.L628:
	movss	xmm0, DWORD PTR gate_y[rip]
	movss	xmm1, DWORD PTR _x_gate_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L629
	ucomiss	xmm0, xmm1
	jne	.L629
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	jne	.L629
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	jne	.L629
	movss	xmm0, DWORD PTR gate_y[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jb	.L629
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L629
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L629
	movss	xmm1, DWORD PTR gate_y[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	jnb	.L632
.L629:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L632
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L632
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L632
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L632
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L193
.L632:
	movss	xmm0, DWORD PTR _x_delta[rip]
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jb	.L193
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L634
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L635
.L634:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L635
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L635
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L193
.L635:
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L636
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L637
.L636:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L637
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L637
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L193
.L637:
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L638
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L639
.L638:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L639
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L639
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	jne	.L193
.L639:
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L640
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L641
.L640:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L641
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L641
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	jne	.L193
.L641:
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L642
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L643
.L642:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L643
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L643
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	jne	.L193
.L643:
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L644
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L645
.L644:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L645
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L645
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	jne	.L193
.L645:
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L646
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L647
.L646:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L647
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L647
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	jne	.L193
.L647:
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L648
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L649
.L648:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L649
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L649
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	jne	.L193
.L649:
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L650
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L651
.L650:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L651
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L651
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	jne	.L193
.L651:
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L652
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L653
.L652:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L653
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L653
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	jne	.L193
.L653:
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L654
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L655
.L654:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L655
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L655
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	jne	.L193
.L655:
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L656
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L657
.L656:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L657
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L657
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	jne	.L193
.L657:
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L658
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L659
.L658:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L659
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L659
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	jne	.L193
.L659:
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L660
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L660
	mov	eax, 1
	jmp	.L661
.L660:
	mov	eax, 0
.L661:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L662
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L662
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L662
	mov	eax, 1
	jmp	.L663
.L662:
	mov	eax, 0
.L663:
	and	eax, 1
	xor	eax, edx
	test	al, al
	jne	.L664
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L664
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L193
.L664:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L666
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L666
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L667
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L667
	mov	eax, 1
	jmp	.L668
.L667:
	mov	eax, 0
.L668:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	je	.L669
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L669
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L669
	mov	eax, 1
	jmp	.L670
.L669:
	mov	eax, 0
.L670:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L193
.L666:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L671
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L671
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L672
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L672
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L672
	mov	eax, 1
	jmp	.L673
.L672:
	mov	eax, 0
.L673:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L674
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L675
.L674:
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L676
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L675
.L676:
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L677
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L675
.L677:
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L678
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L675
.L678:
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L679
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L675
.L679:
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L680
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L675
.L680:
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L681
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L675
.L681:
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L682
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L675
.L682:
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L683
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L675
.L683:
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L684
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L675
.L684:
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L685
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L675
.L685:
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L686
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L675
.L686:
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L687
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L687
.L675:
	mov	eax, 1
	jmp	.L688
.L687:
	mov	eax, 0
.L688:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L193
.L671:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L689
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L689
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L690
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L690
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L690
	mov	eax, 1
	jmp	.L691
.L690:
	mov	eax, 0
.L691:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L692
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L693
.L692:
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L694
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L693
.L694:
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L695
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L693
.L695:
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L696
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L693
.L696:
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L697
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L693
.L697:
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L698
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L693
.L698:
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L699
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L693
.L699:
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L700
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L693
.L700:
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L701
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L693
.L701:
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L702
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L693
.L702:
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L703
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L693
.L703:
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L704
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L693
.L704:
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L705
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L705
.L693:
	mov	eax, 1
	jmp	.L706
.L705:
	mov	eax, 0
.L706:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L193
.L689:
	movss	xmm0, DWORD PTR delta[rip]
	movss	xmm1, DWORD PTR _x__diverge_delta[rip]
	ucomiss	xmm0, xmm1
	jp	.L780
	ucomiss	xmm0, xmm1
	je	.L707
.L780:
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L193
.L707:
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L709
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x__diverge_delta[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L193
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L193
.L709:
	mov	eax, 1
	jmp	.L711
.L193:
	mov	eax, 0
.L711:
	mov	DWORD PTR -4[rbp], eax
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	mov	BYTE PTR t12_l1[rip], al
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	mov	BYTE PTR t12_l0[rip], al
	movzx	eax, BYTE PTR _x_t12_evt1[rip]
	mov	BYTE PTR t12_evt1[rip], al
	movzx	eax, BYTE PTR _x_t12_evt0[rip]
	mov	BYTE PTR t12_evt0[rip], al
	movss	xmm0, DWORD PTR _x_t12_x[rip]
	movss	DWORD PTR t12_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	mov	BYTE PTR t11_l1[rip], al
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	mov	BYTE PTR t11_l0[rip], al
	movzx	eax, BYTE PTR _x_t11_evt1[rip]
	mov	BYTE PTR t11_evt1[rip], al
	movzx	eax, BYTE PTR _x_t11_evt0[rip]
	mov	BYTE PTR t11_evt0[rip], al
	movss	xmm0, DWORD PTR _x_t11_x[rip]
	movss	DWORD PTR t11_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	mov	BYTE PTR t10_l1[rip], al
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	mov	BYTE PTR t10_l0[rip], al
	movzx	eax, BYTE PTR _x_t10_evt1[rip]
	mov	BYTE PTR t10_evt1[rip], al
	movzx	eax, BYTE PTR _x_t10_evt0[rip]
	mov	BYTE PTR t10_evt0[rip], al
	movss	xmm0, DWORD PTR _x_t10_x[rip]
	movss	DWORD PTR t10_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	mov	BYTE PTR t9_l1[rip], al
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	mov	BYTE PTR t9_l0[rip], al
	movzx	eax, BYTE PTR _x_t9_evt1[rip]
	mov	BYTE PTR t9_evt1[rip], al
	movzx	eax, BYTE PTR _x_t9_evt0[rip]
	mov	BYTE PTR t9_evt0[rip], al
	movss	xmm0, DWORD PTR _x_t3_x[rip]
	movss	DWORD PTR t3_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t2_evt1[rip]
	mov	BYTE PTR t2_evt1[rip], al
	movzx	eax, BYTE PTR _x_t2_evt0[rip]
	mov	BYTE PTR t2_evt0[rip], al
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	mov	BYTE PTR t1_l1[rip], al
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	mov	BYTE PTR t0_l1[rip], al
	movzx	eax, BYTE PTR _x_t1_evt0[rip]
	mov	BYTE PTR t1_evt0[rip], al
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	mov	BYTE PTR t0_l0[rip], al
	movss	xmm0, DWORD PTR _x_t0_x[rip]
	movss	DWORD PTR t0_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t0_evt0[rip]
	mov	BYTE PTR t0_evt0[rip], al
	movss	xmm0, DWORD PTR _x_delta[rip]
	movss	DWORD PTR delta[rip], xmm0
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	mov	BYTE PTR t5_l0[rip], al
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	mov	BYTE PTR t1_l0[rip], al
	movzx	eax, BYTE PTR _x_t0_evt1[rip]
	mov	BYTE PTR t0_evt1[rip], al
	movss	xmm0, DWORD PTR _x_t1_x[rip]
	movss	DWORD PTR t1_x[rip], xmm0
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	mov	BYTE PTR controller_l0[rip], al
	movzx	eax, BYTE PTR _x_t6_evt1[rip]
	mov	BYTE PTR t6_evt1[rip], al
	movss	xmm0, DWORD PTR _x_t7_x[rip]
	movss	DWORD PTR t7_x[rip], xmm0
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	mov	BYTE PTR gate_l1[rip], al
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	mov	BYTE PTR controller_l1[rip], al
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	mov	BYTE PTR t2_l0[rip], al
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	mov	BYTE PTR controller_evt0[rip], al
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	mov	BYTE PTR t2_l1[rip], al
	movss	xmm0, DWORD PTR _x__diverge_delta[rip]
	movss	DWORD PTR _diverge_delta[rip], xmm0
	movzx	eax, BYTE PTR _x_t3_evt0[rip]
	mov	BYTE PTR t3_evt0[rip], al
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	mov	BYTE PTR controller_evt1[rip], al
	movzx	eax, BYTE PTR _x_t1_evt1[rip]
	mov	BYTE PTR t1_evt1[rip], al
	movss	xmm0, DWORD PTR _x_t2_x[rip]
	movss	DWORD PTR t2_x[rip], xmm0
	movzx	eax, BYTE PTR _x_gate_evt1[rip]
	mov	BYTE PTR gate_evt1[rip], al
	movss	xmm0, DWORD PTR _x_controller_z[rip]
	movss	DWORD PTR controller_z[rip], xmm0
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	mov	BYTE PTR controller_evt2[rip], al
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	mov	DWORD PTR controller_cnt[rip], eax
	movzx	eax, BYTE PTR _x_t3_evt1[rip]
	mov	BYTE PTR t3_evt1[rip], al
	movss	xmm0, DWORD PTR _x_t4_x[rip]
	movss	DWORD PTR t4_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	mov	BYTE PTR t3_l0[rip], al
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	mov	BYTE PTR t3_l1[rip], al
	movzx	eax, BYTE PTR _x_t4_evt0[rip]
	mov	BYTE PTR t4_evt0[rip], al
	movss	xmm0, DWORD PTR _x_gate_y[rip]
	movss	DWORD PTR gate_y[rip], xmm0
	movzx	eax, BYTE PTR _x_t4_evt1[rip]
	mov	BYTE PTR t4_evt1[rip], al
	movss	xmm0, DWORD PTR _x_t5_x[rip]
	movss	DWORD PTR t5_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	mov	BYTE PTR t4_l0[rip], al
	movzx	eax, BYTE PTR _x_gate_evt0[rip]
	mov	BYTE PTR gate_evt0[rip], al
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	mov	BYTE PTR t4_l1[rip], al
	movzx	eax, BYTE PTR _x_t5_evt0[rip]
	mov	BYTE PTR t5_evt0[rip], al
	movzx	eax, BYTE PTR _x_t5_evt1[rip]
	mov	BYTE PTR t5_evt1[rip], al
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	mov	BYTE PTR gate_l0[rip], al
	movss	xmm0, DWORD PTR _x_t6_x[rip]
	movss	DWORD PTR t6_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	mov	BYTE PTR t5_l1[rip], al
	movzx	eax, BYTE PTR _x_t6_evt0[rip]
	mov	BYTE PTR t6_evt0[rip], al
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	mov	BYTE PTR t6_l0[rip], al
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	mov	BYTE PTR t6_l1[rip], al
	movzx	eax, BYTE PTR _x_t7_evt0[rip]
	mov	BYTE PTR t7_evt0[rip], al
	movzx	eax, BYTE PTR _x_t7_evt1[rip]
	mov	BYTE PTR t7_evt1[rip], al
	movss	xmm0, DWORD PTR _x_t8_x[rip]
	movss	DWORD PTR t8_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	mov	BYTE PTR t7_l0[rip], al
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	mov	BYTE PTR t7_l1[rip], al
	movzx	eax, BYTE PTR _x_t8_evt0[rip]
	mov	BYTE PTR t8_evt0[rip], al
	movzx	eax, BYTE PTR _x_t8_evt1[rip]
	mov	BYTE PTR t8_evt1[rip], al
	movss	xmm0, DWORD PTR _x_t9_x[rip]
	movss	DWORD PTR t9_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	mov	BYTE PTR t8_l0[rip], al
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	mov	BYTE PTR t8_l1[rip], al
.L188:
	cmp	DWORD PTR -4[rbp], 0
	jne	.L712
	mov	eax, 0
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	main, .-main
	.section	.rodata
	.align 4
.LC1:
	.long	1084227584
	.align 4
.LC2:
	.long	1065353216
	.align 4
.LC3:
	.long	1073741824
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"584441.c"
	.text
	.align	2
	.global	__VERIFIER_nondet_bool
	.syntax unified
	.arm
	.fpu softvfp
	.type	__VERIFIER_nondet_bool, %function
__VERIFIER_nondet_bool:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	mov	r0, r3
	pop	{fp, pc}
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.comm	t12_l1,1,1
	.comm	_x_t12_l1,1,1
	.comm	t12_l0,1,1
	.comm	_x_t12_l0,1,1
	.comm	t12_evt1,1,1
	.comm	_x_t12_evt1,1,1
	.comm	t12_evt0,1,1
	.comm	_x_t12_evt0,1,1
	.comm	t12_x,4,4
	.comm	_x_t12_x,4,4
	.comm	t11_l1,1,1
	.comm	_x_t11_l1,1,1
	.comm	t11_l0,1,1
	.comm	_x_t11_l0,1,1
	.comm	t11_evt1,1,1
	.comm	_x_t11_evt1,1,1
	.comm	t11_evt0,1,1
	.comm	_x_t11_evt0,1,1
	.comm	t11_x,4,4
	.comm	_x_t11_x,4,4
	.comm	t10_l1,1,1
	.comm	_x_t10_l1,1,1
	.comm	t10_l0,1,1
	.comm	_x_t10_l0,1,1
	.comm	t10_evt1,1,1
	.comm	_x_t10_evt1,1,1
	.comm	t10_evt0,1,1
	.comm	_x_t10_evt0,1,1
	.comm	t10_x,4,4
	.comm	_x_t10_x,4,4
	.comm	t9_l1,1,1
	.comm	_x_t9_l1,1,1
	.comm	t9_l0,1,1
	.comm	_x_t9_l0,1,1
	.comm	t9_evt1,1,1
	.comm	_x_t9_evt1,1,1
	.comm	t9_evt0,1,1
	.comm	_x_t9_evt0,1,1
	.comm	t3_x,4,4
	.comm	_x_t3_x,4,4
	.comm	t2_evt1,1,1
	.comm	_x_t2_evt1,1,1
	.comm	t2_evt0,1,1
	.comm	_x_t2_evt0,1,1
	.comm	t1_l1,1,1
	.comm	_x_t1_l1,1,1
	.comm	t0_l1,1,1
	.comm	_x_t0_l1,1,1
	.comm	t1_evt0,1,1
	.comm	_x_t1_evt0,1,1
	.comm	t0_l0,1,1
	.comm	_x_t0_l0,1,1
	.comm	t0_x,4,4
	.comm	_x_t0_x,4,4
	.comm	t0_evt0,1,1
	.comm	_x_t0_evt0,1,1
	.comm	delta,4,4
	.comm	_x_delta,4,4
	.comm	t5_l0,1,1
	.comm	_x_t5_l0,1,1
	.comm	t1_l0,1,1
	.comm	_x_t1_l0,1,1
	.comm	t0_evt1,1,1
	.comm	_x_t0_evt1,1,1
	.comm	t1_x,4,4
	.comm	_x_t1_x,4,4
	.comm	controller_l0,1,1
	.comm	_x_controller_l0,1,1
	.comm	t6_evt1,1,1
	.comm	_x_t6_evt1,1,1
	.comm	t7_x,4,4
	.comm	_x_t7_x,4,4
	.comm	gate_l1,1,1
	.comm	_x_gate_l1,1,1
	.comm	controller_l1,1,1
	.comm	_x_controller_l1,1,1
	.comm	t2_l0,1,1
	.comm	_x_t2_l0,1,1
	.comm	controller_evt0,1,1
	.comm	_x_controller_evt0,1,1
	.comm	t2_l1,1,1
	.comm	_x_t2_l1,1,1
	.comm	_diverge_delta,4,4
	.comm	_x__diverge_delta,4,4
	.comm	t3_evt0,1,1
	.comm	_x_t3_evt0,1,1
	.comm	controller_evt1,1,1
	.comm	_x_controller_evt1,1,1
	.comm	t1_evt1,1,1
	.comm	_x_t1_evt1,1,1
	.comm	t2_x,4,4
	.comm	_x_t2_x,4,4
	.comm	gate_evt1,1,1
	.comm	_x_gate_evt1,1,1
	.comm	controller_z,4,4
	.comm	_x_controller_z,4,4
	.comm	controller_evt2,1,1
	.comm	_x_controller_evt2,1,1
	.comm	controller_cnt,4,4
	.comm	_x_controller_cnt,4,4
	.comm	t3_evt1,1,1
	.comm	_x_t3_evt1,1,1
	.comm	t4_x,4,4
	.comm	_x_t4_x,4,4
	.comm	t3_l0,1,1
	.comm	_x_t3_l0,1,1
	.comm	t3_l1,1,1
	.comm	_x_t3_l1,1,1
	.comm	t4_evt0,1,1
	.comm	_x_t4_evt0,1,1
	.comm	gate_y,4,4
	.comm	_x_gate_y,4,4
	.comm	t4_evt1,1,1
	.comm	_x_t4_evt1,1,1
	.comm	t5_x,4,4
	.comm	_x_t5_x,4,4
	.comm	t4_l0,1,1
	.comm	_x_t4_l0,1,1
	.comm	gate_evt0,1,1
	.comm	_x_gate_evt0,1,1
	.comm	t4_l1,1,1
	.comm	_x_t4_l1,1,1
	.comm	t5_evt0,1,1
	.comm	_x_t5_evt0,1,1
	.comm	t5_evt1,1,1
	.comm	_x_t5_evt1,1,1
	.comm	gate_l0,1,1
	.comm	_x_gate_l0,1,1
	.comm	t6_x,4,4
	.comm	_x_t6_x,4,4
	.comm	t5_l1,1,1
	.comm	_x_t5_l1,1,1
	.comm	t6_evt0,1,1
	.comm	_x_t6_evt0,1,1
	.comm	t6_l0,1,1
	.comm	_x_t6_l0,1,1
	.comm	t6_l1,1,1
	.comm	_x_t6_l1,1,1
	.comm	t7_evt0,1,1
	.comm	_x_t7_evt0,1,1
	.comm	t7_evt1,1,1
	.comm	_x_t7_evt1,1,1
	.comm	t8_x,4,4
	.comm	_x_t8_x,4,4
	.comm	t7_l0,1,1
	.comm	_x_t7_l0,1,1
	.comm	t7_l1,1,1
	.comm	_x_t7_l1,1,1
	.comm	t8_evt0,1,1
	.comm	_x_t8_evt0,1,1
	.comm	t8_evt1,1,1
	.comm	_x_t8_evt1,1,1
	.comm	t9_x,4,4
	.comm	_x_t9_x,4,4
	.comm	t8_l0,1,1
	.comm	_x_t8_l0,1,1
	.comm	t8_l1,1,1
	.comm	_x_t8_l1,1,1
	.global	__aeabi_fcmpeq
	.global	__aeabi_fcmple
	.global	__aeabi_fcmpge
	.global	__aeabi_f2d
	.global	__aeabi_dsub
	.global	__aeabi_dadd
	.global	__aeabi_dcmpeq
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, fp, lr}
	add	fp, sp, #20
	sub	sp, sp, #8
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+4
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+8
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+12
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L735+16
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+20
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+24
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+28
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+32
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L735+36
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+40
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+44
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+48
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+52
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L735+56
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+60
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+64
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+68
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+72
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L735+196
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+204
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+200
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+232
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+252
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+220
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+248
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L735+256
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+240
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L735+312
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+148
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+228
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+244
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L735+236
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+284
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+124
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L735+76
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+308
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+288
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+208
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+268
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+212
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L735+316
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+180
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+272
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+224
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L735+216
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+296
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L735+280
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+264
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L735+276
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+184
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L735+176
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+188
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+192
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+160
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L735+300
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+164
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L735+156
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+168
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+292
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+172
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+140
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+144
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+304
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L735+136
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+152
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+120
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+128
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+132
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+80
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+84
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L735+88
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+92
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+96
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+100
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+104
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L735+108
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+112
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+116
	strb	r2, [r3]
	ldr	r3, .L735+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L6
	ldr	r3, .L735
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L6:
	ldr	r3, .L735+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L735
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L8:
	ldr	r3, .L735
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L9
	ldr	r3, .L735+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L9:
	ldr	r3, .L735+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L7:
	ldr	r3, .L735+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L10
	ldr	r3, .L735+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L11
.L10:
	ldr	r3, .L735+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L12
	ldr	r3, .L735+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L11
.L12:
	ldr	r3, .L735+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L13
	ldr	r3, .L735+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L11
.L13:
	ldr	r3, .L735+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L11:
	ldr	r3, .L735+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L14
	ldr	r3, .L735
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L15
.L14:
	ldr	r3, .L735+16
	ldr	r3, [r3]	@ float
	ldr	r1, .L735+260
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L15:
	ldr	r3, .L735+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+36
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L18
	ldr	r3, .L735+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L19
.L18:
	ldr	r3, .L735+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L20
	ldr	r3, .L735+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L19
.L20:
	ldr	r3, .L735+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L21
	ldr	r3, .L735+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L19
.L21:
	ldr	r3, .L735+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L19:
	ldr	r3, .L735+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L22
	ldr	r3, .L735+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L23
.L22:
	ldr	r3, .L735+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L24
	ldr	r3, .L735+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L23
.L24:
	ldr	r3, .L735+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L25
	ldr	r3, .L735+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L23
.L25:
	ldr	r3, .L735+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L23:
	ldr	r3, .L735+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L26
	ldr	r3, .L735+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L27
.L26:
	ldr	r3, .L735+36
	ldr	r3, [r3]	@ float
	ldr	r1, .L735+260
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L27:
	ldr	r3, .L735+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+56
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L30
	ldr	r3, .L735+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
.L30:
	ldr	r3, .L735+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L32
	ldr	r3, .L735+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
.L32:
	ldr	r3, .L735+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L33
	ldr	r3, .L735+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
.L33:
	ldr	r3, .L735+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L31:
	ldr	r3, .L735+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L34
	ldr	r3, .L735+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
.L34:
	ldr	r3, .L735+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L36
	ldr	r3, .L735+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
.L36:
	ldr	r3, .L735+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L37
	ldr	r3, .L735+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
.L37:
	ldr	r3, .L735+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L35:
	ldr	r3, .L735+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L38
	ldr	r3, .L735+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L39
.L38:
	ldr	r3, .L735+56
	ldr	r3, [r3]	@ float
	ldr	r1, .L735+260
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L39:
	ldr	r3, .L735+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+108
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L42
	ldr	r3, .L735+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L43
.L42:
	ldr	r3, .L735+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L44
	ldr	r3, .L735+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L43
.L44:
	ldr	r3, .L735+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L45
	ldr	r3, .L735+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L43
.L45:
	ldr	r3, .L735+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L43:
	ldr	r3, .L735+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L46
	ldr	r3, .L735+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L47
.L46:
	ldr	r3, .L735+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L48
	ldr	r3, .L735+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L47
.L48:
	ldr	r3, .L735+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L49
	ldr	r3, .L735+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L47
.L49:
	ldr	r3, .L735+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L47:
	ldr	r3, .L735+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L50
	ldr	r3, .L735+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L51
.L50:
	ldr	r3, .L735+108
	ldr	r3, [r3]	@ float
	ldr	r1, .L735+260
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L51:
	ldr	r3, .L735+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+88
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L54
	ldr	r3, .L735+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L55
.L54:
	ldr	r3, .L735+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L56
	ldr	r3, .L735+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L55
.L56:
	ldr	r3, .L735+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L57
	ldr	r3, .L735+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L55
.L57:
	ldr	r3, .L735+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L55:
	ldr	r3, .L735+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L58
	ldr	r3, .L735+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L58:
	ldr	r3, .L735+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L60
	ldr	r3, .L735+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L60:
	ldr	r3, .L735+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L735+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L61:
	ldr	r3, .L735+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L59:
	ldr	r3, .L735+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L62
	ldr	r3, .L735+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
.L62:
	ldr	r3, .L735+88
	ldr	r3, [r3]	@ float
	ldr	r1, .L735+260
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L63:
	ldr	r3, .L735+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L66
	ldr	r3, .L735+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L67
.L66:
	ldr	r3, .L735+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L68
	ldr	r3, .L735+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L67
.L68:
	ldr	r3, .L735+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L69
	ldr	r3, .L735+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L67
.L69:
	ldr	r3, .L735+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L67:
	ldr	r3, .L735+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L70
	ldr	r3, .L735+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L71
.L70:
	ldr	r3, .L735+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L72
	ldr	r3, .L735+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L71
.L72:
	ldr	r3, .L735+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L73
	ldr	r3, .L735+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L71
.L73:
	ldr	r3, .L735+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L71:
	ldr	r3, .L735+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L74
	ldr	r3, .L735+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L75
.L74:
	ldr	r3, .L735+76
	ldr	r3, [r3]	@ float
	ldr	r1, .L735+260
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L75:
	ldr	r3, .L735+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L78
	ldr	r3, .L735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L79
.L78:
	ldr	r3, .L735+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L80
	ldr	r3, .L735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L79
.L80:
	ldr	r3, .L735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L735+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L79
.L81:
	ldr	r3, .L735+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L79:
	ldr	r3, .L735+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L82
	ldr	r3, .L735+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L83
.L82:
	ldr	r3, .L735+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L84
	ldr	r3, .L735+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L83
.L84:
	ldr	r3, .L735+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L85
	ldr	r3, .L735+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L83
	b	.L736
.L737:
	.align	2
.L735:
	.word	t12_l1
	.word	t12_l0
	.word	t12_evt1
	.word	t12_evt0
	.word	t12_x
	.word	t11_l1
	.word	t11_l0
	.word	t11_evt1
	.word	t11_evt0
	.word	t11_x
	.word	t10_l1
	.word	t10_l0
	.word	t10_evt1
	.word	t10_evt0
	.word	t10_x
	.word	t9_l1
	.word	t9_l0
	.word	t9_evt1
	.word	t9_evt0
	.word	t7_x
	.word	t7_evt0
	.word	t7_evt1
	.word	t8_x
	.word	t7_l0
	.word	t7_l1
	.word	t8_evt0
	.word	t8_evt1
	.word	t9_x
	.word	t8_l0
	.word	t8_l1
	.word	t6_evt0
	.word	t6_evt1
	.word	t6_l0
	.word	t6_l1
	.word	t6_x
	.word	t5_evt0
	.word	t5_evt1
	.word	t5_l0
	.word	t5_l1
	.word	t5_x
	.word	t4_evt0
	.word	t4_evt1
	.word	t4_l0
	.word	t4_l1
	.word	t4_x
	.word	t3_evt0
	.word	t3_evt1
	.word	t3_l0
	.word	t3_l1
	.word	t3_x
	.word	t2_evt0
	.word	t2_evt1
	.word	t2_l0
	.word	t2_l1
	.word	t2_x
	.word	t1_evt0
	.word	t1_evt1
	.word	t1_l0
	.word	t1_l1
	.word	t1_x
	.word	t0_evt0
	.word	t0_evt1
	.word	t0_l0
	.word	t0_l1
	.word	t0_x
	.word	1084227584
	.word	controller_evt2
	.word	controller_evt0
	.word	controller_evt1
	.word	controller_cnt
	.word	controller_z
	.word	controller_l0
	.word	controller_l1
	.word	gate_evt0
	.word	gate_evt1
	.word	gate_y
	.word	gate_l0
	.word	gate_l1
	.word	delta
	.word	_diverge_delta
	.word	_x_t12_l1
	.word	_x_t12_l0
	.word	_x_t12_evt1
	.word	_x_t12_evt0
	.word	_x_t12_x
	.word	_x_t11_l1
	.word	_x_t11_l0
	.word	_x_t11_evt1
	.word	_x_t11_evt0
	.word	_x_t11_x
	.word	_x_t10_l1
	.word	_x_t10_l0
	.word	_x_t10_evt1
	.word	_x_t10_evt0
	.word	_x_t10_x
	.word	_x_t9_l1
	.word	_x_t9_l0
	.word	_x_t9_evt1
	.word	_x_t9_evt0
.L736:
.L85:
	ldr	r3, .L735+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L83:
	ldr	r3, .L735+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L86
	ldr	r3, .L735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L87
.L86:
	ldr	r3, .L735+136
	ldr	r3, [r3]	@ float
	ldr	r1, .L735+260
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L87:
	ldr	r3, .L735+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+156
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L90
	ldr	r3, .L735+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L91
.L90:
	ldr	r3, .L735+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L92
	ldr	r3, .L735+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L91
.L92:
	ldr	r3, .L735+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L93
	ldr	r3, .L735+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L91
.L93:
	ldr	r3, .L735+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L91:
	ldr	r3, .L735+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L94
	ldr	r3, .L735+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L95
.L94:
	ldr	r3, .L735+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L96
	ldr	r3, .L735+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L95
.L96:
	ldr	r3, .L735+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L97
	ldr	r3, .L735+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L95
.L97:
	ldr	r3, .L735+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L95:
	ldr	r3, .L735+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L98
	ldr	r3, .L735+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L99
.L98:
	ldr	r3, .L735+156
	ldr	r3, [r3]	@ float
	ldr	r1, .L735+260
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L99:
	ldr	r3, .L735+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+176
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L102
	ldr	r3, .L735+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L103
.L102:
	ldr	r3, .L735+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L104
	ldr	r3, .L735+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L103
.L104:
	ldr	r3, .L735+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L105
	ldr	r3, .L735+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L103
.L105:
	ldr	r3, .L735+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L103:
	ldr	r3, .L735+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L106
	ldr	r3, .L735+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L107
.L106:
	ldr	r3, .L735+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L108
	ldr	r3, .L735+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L107
.L108:
	ldr	r3, .L735+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L109
	ldr	r3, .L735+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L107
.L109:
	ldr	r3, .L735+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L107:
	ldr	r3, .L735+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L110
	ldr	r3, .L735+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L111
.L110:
	ldr	r3, .L735+176
	ldr	r3, [r3]	@ float
	ldr	r1, .L735+260
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L111:
	ldr	r3, .L735+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+196
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L114
	ldr	r3, .L735+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L115
.L114:
	ldr	r3, .L735+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L116
	ldr	r3, .L735+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L115
.L116:
	ldr	r3, .L735+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L117
	ldr	r3, .L735+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L115
.L117:
	ldr	r3, .L735+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L115:
	ldr	r3, .L735+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L118
	ldr	r3, .L735+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L119
.L118:
	ldr	r3, .L735+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L120
	ldr	r3, .L735+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L119
.L120:
	ldr	r3, .L735+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L121
	ldr	r3, .L735+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L119
.L121:
	ldr	r3, .L735+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L119:
	ldr	r3, .L735+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L122
	ldr	r3, .L735+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L123
.L122:
	ldr	r3, .L735+196
	ldr	r3, [r3]	@ float
	ldr	r1, .L735+260
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L123:
	ldr	r3, .L735+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L126
	ldr	r3, .L735+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L127
.L126:
	ldr	r3, .L735+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L128
	ldr	r3, .L735+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L127
.L128:
	ldr	r3, .L735+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L129
	ldr	r3, .L735+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L127
.L129:
	ldr	r3, .L735+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L127:
	ldr	r3, .L735+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L130
	ldr	r3, .L735+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L131
.L130:
	ldr	r3, .L735+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L132
	ldr	r3, .L735+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L131
.L132:
	ldr	r3, .L735+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L133
	ldr	r3, .L735+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L131
.L133:
	ldr	r3, .L735+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L131:
	ldr	r3, .L735+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L134
	ldr	r3, .L735+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L135
.L134:
	ldr	r3, .L735+216
	ldr	r3, [r3]	@ float
	ldr	r1, .L735+260
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L135:
	ldr	r3, .L735+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+236
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L138
	ldr	r3, .L735+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L139
.L138:
	ldr	r3, .L735+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L140
	ldr	r3, .L735+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L139
.L140:
	ldr	r3, .L735+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L141
	ldr	r3, .L735+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L139
.L141:
	ldr	r3, .L735+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L139:
	ldr	r3, .L735+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L142
	ldr	r3, .L735+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L143
.L142:
	ldr	r3, .L735+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L144
	ldr	r3, .L735+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L143
.L144:
	ldr	r3, .L735+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L145
	ldr	r3, .L735+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L143
.L145:
	ldr	r3, .L735+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L143:
	ldr	r3, .L735+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L146
	ldr	r3, .L735+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L147
.L146:
	ldr	r3, .L735+236
	ldr	r3, [r3]	@ float
	ldr	r1, .L735+260
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L147:
	ldr	r3, .L735+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+256
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L150
	ldr	r3, .L735+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
.L150:
	ldr	r3, .L735+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L152
	ldr	r3, .L735+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
.L152:
	ldr	r3, .L735+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L153
	ldr	r3, .L735+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
.L153:
	ldr	r3, .L735+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L151:
	ldr	r3, .L735+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L154
	ldr	r3, .L735+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L155
.L154:
	ldr	r3, .L735+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L156
	ldr	r3, .L735+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L155
.L156:
	ldr	r3, .L735+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L157
	ldr	r3, .L735+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L155
.L157:
	ldr	r3, .L735+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L155:
	ldr	r3, .L735+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L158
	ldr	r3, .L735+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L159
.L158:
	ldr	r3, .L735+256
	ldr	r3, [r3]	@ float
	ldr	r1, .L735+260
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L159:
	ldr	r3, .L735+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+280
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L162
	ldr	r3, .L735+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L163
.L162:
	ldr	r3, .L735+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L164
	ldr	r3, .L735+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L163
.L164:
	ldr	r3, .L735+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L165
	ldr	r3, .L735+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L163
.L165:
	ldr	r3, .L735+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L163:
	ldr	r3, .L735+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L166
	ldr	r3, .L735+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L166
	ldr	r3, .L735+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L167
.L166:
	ldr	r3, .L735+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L168
	ldr	r3, .L735+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L168
	ldr	r3, .L735+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L167
.L168:
	ldr	r3, .L735+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L169
	ldr	r3, .L735+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L169
	ldr	r3, .L735+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L167
.L169:
	ldr	r3, .L735+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L170
	ldr	r3, .L735+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L170
	ldr	r3, .L735+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L167
.L170:
	ldr	r3, .L735+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L167:
	ldr	r3, .L735+276
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L171
	ldr	r3, .L735+276
	ldr	r3, [r3]
	cmp	r3, #1
	beq	.L171
	ldr	r3, .L735+276
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L171
	ldr	r3, .L735+276
	ldr	r3, [r3]
	cmp	r3, #3
	beq	.L171
	ldr	r3, .L735+276
	ldr	r3, [r3]
	cmp	r3, #4
	beq	.L171
	ldr	r3, .L735+276
	ldr	r3, [r3]
	cmp	r3, #5
	beq	.L171
	ldr	r3, .L735+276
	ldr	r3, [r3]
	cmp	r3, #6
	beq	.L171
	ldr	r3, .L735+276
	ldr	r3, [r3]
	cmp	r3, #7
	beq	.L171
	ldr	r3, .L735+276
	ldr	r3, [r3]
	cmp	r3, #8
	beq	.L171
	ldr	r3, .L735+276
	ldr	r3, [r3]
	cmp	r3, #9
	beq	.L171
	ldr	r3, .L735+276
	ldr	r3, [r3]
	cmp	r3, #10
	beq	.L171
	ldr	r3, .L735+276
	ldr	r3, [r3]
	cmp	r3, #11
	beq	.L171
	ldr	r3, .L735+276
	ldr	r3, [r3]
	cmp	r3, #12
	beq	.L171
	ldr	r3, .L735+276
	ldr	r3, [r3]
	cmp	r3, #13
	beq	.L171
	ldr	r3, .L735+276
	ldr	r3, [r3]
	cmp	r3, #14
	bne	.L4
.L171:
	ldr	r3, .L735+280
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L172
	ldr	r3, .L735+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L173
	ldr	r3, .L735+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L173:
	ldr	r3, .L735+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L172
	ldr	r3, .L735+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L172:
	ldr	r3, .L735+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L735+300
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L175
	ldr	r3, .L735+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L176
.L175:
	ldr	r3, .L735+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L177
	ldr	r3, .L735+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L176
.L177:
	ldr	r3, .L735+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L178
	ldr	r3, .L735+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L176
.L178:
	ldr	r3, .L735+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L176:
	ldr	r3, .L735+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L179
	ldr	r3, .L735+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L180
.L179:
	ldr	r3, .L735+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L181
	ldr	r3, .L735+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L180
.L181:
	ldr	r3, .L735+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L182
	ldr	r3, .L735+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L180
.L182:
	ldr	r3, .L735+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L180:
	ldr	r3, .L735+300
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L183
	ldr	r3, .L735+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L183
	ldr	r3, .L735+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L183:
	ldr	r3, .L735+300
	ldr	r3, [r3]	@ float
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L184
	ldr	r3, .L735+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L184
	ldr	r3, .L735+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L184:
	ldr	r3, .L735+312
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L735+312
	ldr	r3, [r3]	@ float
	ldr	r2, .L735+316
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	mov	r3, #1
	b	.L187
.L4:
	mov	r3, #0
.L187:
	str	r3, [fp, #-24]
	b	.L188
.L667:
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+320
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+324
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+328
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+332
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L735+336
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+340
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+344
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+348
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+352
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L735+356
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+360
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+364
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+368
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+372
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L735+376
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+380
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+384
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+388
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L735+392
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L738
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+4
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+8
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+12
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+16
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+20
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+24
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L738+28
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+32
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L738+36
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+40
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+44
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+48
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L738+52
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+56
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+60
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L738+64
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+68
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+72
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+76
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+80
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+84
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L738+88
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+92
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+96
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+100
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L738+104
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+108
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L738+112
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+116
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L738+120
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+124
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L738+128
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+132
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+136
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+140
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L738+144
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+148
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L738+152
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+156
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+160
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+164
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+168
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+172
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+176
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L738+180
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+184
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+188
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+192
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+196
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+200
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+204
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L738+396
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+208
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+212
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+376
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+380
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L738+356
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+392
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L738+420
	strb	r2, [r3]
	ldr	r3, .L738+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L189
	ldr	r3, .L738+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L190
.L189:
	ldr	r3, .L738+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L191
	ldr	r3, .L738+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L190
.L191:
	ldr	r3, .L738+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L192
	ldr	r3, .L738+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L190
.L192:
	ldr	r3, .L738+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L738+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L190:
	ldr	r3, .L738+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L194
	ldr	r3, .L738+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L194:
	ldr	r3, .L738+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L196
	ldr	r3, .L738+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L196:
	ldr	r3, .L738+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L197
	ldr	r3, .L738+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L197:
	ldr	r3, .L738+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L738+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L195:
	ldr	r3, .L738+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L198
	ldr	r3, .L738+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L199
.L198:
	ldr	r3, .L738+232
	ldr	r3, [r3]	@ float
	ldr	r1, .L738+384
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
.L199:
	ldr	r3, .L738+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L738+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L201
	ldr	r3, .L738+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L738+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L201
	ldr	r3, .L738+408
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L738+244
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L738+232
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L202
.L201:
	ldr	r3, .L738+408
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L738+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L202
	ldr	r3, .L738+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L202:
	ldr	r3, .L738+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L204
	ldr	r3, .L738+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L204
	ldr	r3, .L738+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L204
	ldr	r3, .L738+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L204
	ldr	r3, .L738+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L205
.L204:
	ldr	r3, .L738+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L738+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L738+408
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L738+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L738+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L205:
	ldr	r3, .L738+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L206
	ldr	r3, .L738+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L206
	ldr	r3, .L738+244
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L207
	mov	r3, #0
	mov	r4, r3
.L207:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L206
	ldr	r3, .L738+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L206
	ldr	r3, .L738+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L206
	ldr	r3, .L738+244
	ldr	r3, [r3]	@ float
	ldr	r2, .L738+232
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L208
.L206:
	ldr	r3, .L738+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L208
	ldr	r3, .L738+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L208
	ldr	r3, .L738+408
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L208
	ldr	r3, .L738+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L738+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L208:
	ldr	r3, .L738+244
	ldr	r3, [r3]	@ float
	ldr	r2, .L738+232
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L209
	ldr	r3, .L738+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L209
	ldr	r3, .L738+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L209
	ldr	r3, .L738+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L209
	ldr	r3, .L738+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L211
.L209:
	ldr	r3, .L738+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L211
	ldr	r3, .L738+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L211
	ldr	r3, .L738+408
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L211
	ldr	r3, .L738+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L738+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L211:
	ldr	r3, .L738+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L212
	ldr	r3, .L738+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L212
	ldr	r3, .L738+244
	ldr	r3, [r3]	@ float
	ldr	r1, .L738+384
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L212
	ldr	r3, .L738+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L212
	ldr	r3, .L738+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L212
	ldr	r3, .L738+244
	ldr	r3, [r3]	@ float
	ldr	r2, .L738+232
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L214
.L212:
	ldr	r3, .L738+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
	ldr	r3, .L738+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
	ldr	r3, .L738+408
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L214
	ldr	r3, .L738+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L738+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L214:
	ldr	r3, .L738+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L215
	ldr	r3, .L738+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L216
.L215:
	ldr	r3, .L738+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L217
	ldr	r3, .L738+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L216
.L217:
	ldr	r3, .L738+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L218
	ldr	r3, .L738+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L216
.L218:
	ldr	r3, .L738+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L738+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L216:
	ldr	r3, .L738+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L219
	ldr	r3, .L738+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L220
.L219:
	ldr	r3, .L738+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L221
	ldr	r3, .L738+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L220
.L221:
	ldr	r3, .L738+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L222
	ldr	r3, .L738+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L220
.L222:
	ldr	r3, .L738+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L738+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L220:
	ldr	r3, .L738+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L223
	ldr	r3, .L738+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L224
.L223:
	ldr	r3, .L738+276
	ldr	r3, [r3]	@ float
	ldr	r1, .L738+384
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
.L224:
	ldr	r3, .L738+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L738+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L226
	ldr	r3, .L738+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L738+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L226
	ldr	r3, .L738+408
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L738+272
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L738+276
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L227
.L226:
	ldr	r3, .L738+408
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L738+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L227
	ldr	r3, .L738+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L227:
	ldr	r3, .L738+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L229
	ldr	r3, .L738+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L229
	ldr	r3, .L738+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L229
	ldr	r3, .L738+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L229
	ldr	r3, .L738+276
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L230
.L229:
	ldr	r3, .L738+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L230
	ldr	r3, .L738+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L230
	ldr	r3, .L738+408
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L230
	ldr	r3, .L738+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L738+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L230:
	ldr	r3, .L738+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L231
	ldr	r3, .L738+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L231
	ldr	r3, .L738+272
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L232
	mov	r3, #0
	mov	r4, r3
.L232:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L231
	ldr	r3, .L738+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L231
	ldr	r3, .L738+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L231
	ldr	r3, .L738+272
	ldr	r3, [r3]	@ float
	ldr	r2, .L738+276
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L233
.L231:
	ldr	r3, .L738+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L233
	ldr	r3, .L738+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L233
	ldr	r3, .L738+408
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L233
	ldr	r3, .L738+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L738+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L233:
	ldr	r3, .L738+272
	ldr	r3, [r3]	@ float
	ldr	r2, .L738+276
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L234
	ldr	r3, .L738+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L234
	ldr	r3, .L738+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L234
	ldr	r3, .L738+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L234
	ldr	r3, .L738+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L236
.L234:
	ldr	r3, .L738+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L236
	ldr	r3, .L738+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L236
	ldr	r3, .L738+408
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L236
	ldr	r3, .L738+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L738+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L236:
	ldr	r3, .L738+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L237
	ldr	r3, .L738+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L237
	ldr	r3, .L738+272
	ldr	r3, [r3]	@ float
	ldr	r1, .L738+384
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L237
	ldr	r3, .L738+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L237
	ldr	r3, .L738+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L237
	b	.L739
.L740:
	.align	2
.L738:
	.word	_x_t3_x
	.word	_x_t2_evt1
	.word	_x_t2_evt0
	.word	_x_t1_l1
	.word	_x_t0_l1
	.word	_x_t1_evt0
	.word	_x_t0_l0
	.word	_x_t0_x
	.word	_x_t0_evt0
	.word	_x_delta
	.word	_x_t5_l0
	.word	_x_t1_l0
	.word	_x_t0_evt1
	.word	_x_t1_x
	.word	_x_controller_l0
	.word	_x_t6_evt1
	.word	_x_t7_x
	.word	_x_gate_l1
	.word	_x_controller_l1
	.word	_x_t2_l0
	.word	_x_controller_evt0
	.word	_x_t2_l1
	.word	_x__diverge_delta
	.word	_x_t3_evt0
	.word	_x_controller_evt1
	.word	_x_t1_evt1
	.word	_x_t2_x
	.word	_x_gate_evt1
	.word	_x_controller_z
	.word	_x_controller_evt2
	.word	_x_controller_cnt
	.word	_x_t3_evt1
	.word	_x_t4_x
	.word	_x_t3_l0
	.word	_x_t3_l1
	.word	_x_t4_evt0
	.word	_x_gate_y
	.word	_x_t4_evt1
	.word	_x_t5_x
	.word	_x_t4_l0
	.word	_x_gate_evt0
	.word	_x_t4_l1
	.word	_x_t5_evt0
	.word	_x_t5_evt1
	.word	_x_gate_l0
	.word	_x_t6_x
	.word	_x_t5_l1
	.word	_x_t6_evt0
	.word	_x_t6_l0
	.word	_x_t6_l1
	.word	_x_t7_evt0
	.word	_x_t7_evt1
	.word	_x_t7_l0
	.word	_x_t7_l1
	.word	_x_t12_l0
	.word	_x_t12_l1
	.word	_x_t12_evt0
	.word	_x_t12_evt1
	.word	_x_t12_x
	.word	t12_l0
	.word	t12_l1
	.word	t12_x
	.word	t12_evt0
	.word	t12_evt1
	.word	_x_t11_l0
	.word	_x_t11_l1
	.word	_x_t11_evt0
	.word	_x_t11_evt1
	.word	t11_x
	.word	_x_t11_x
	.word	t11_l0
	.word	t11_l1
	.word	t11_evt0
	.word	t11_evt1
	.word	_x_t10_evt0
	.word	_x_t10_evt1
	.word	_x_t10_l0
	.word	_x_t10_l1
	.word	t10_x
	.word	_x_t10_x
	.word	t10_l0
	.word	t10_l1
	.word	t10_evt0
	.word	t10_evt1
	.word	_x_t9_evt0
	.word	_x_t9_evt1
	.word	_x_t9_l0
	.word	_x_t9_l1
	.word	t9_x
	.word	_x_t9_x
	.word	t9_l0
	.word	t9_l1
	.word	t9_evt0
	.word	t9_evt1
	.word	_x_t8_evt0
	.word	_x_t8_evt1
	.word	1084227584
	.word	t8_x
	.word	_x_t8_l0
	.word	_x_t8_x
	.word	t8_l0
	.word	t8_l1
	.word	delta
	.word	t8_evt0
	.word	t8_evt1
	.word	_x_t8_l1
.L739:
	ldr	r3, .L738+272
	ldr	r3, [r3]	@ float
	ldr	r2, .L738+276
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L239
.L237:
	ldr	r3, .L738+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L239
	ldr	r3, .L738+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L239
	ldr	r3, .L738+408
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L239
	ldr	r3, .L738+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L738+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L239:
	ldr	r3, .L738+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L240
	ldr	r3, .L738+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L240:
	ldr	r3, .L738+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L242
	ldr	r3, .L738+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L242:
	ldr	r3, .L738+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L243
	ldr	r3, .L738+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L243:
	ldr	r3, .L738+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L738+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L241:
	ldr	r3, .L738+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L244
	ldr	r3, .L738+300
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L244:
	ldr	r3, .L738+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L246
	ldr	r3, .L738+300
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L246:
	ldr	r3, .L738+300
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L738+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L247:
	ldr	r3, .L738+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L738+300
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L245:
	ldr	r3, .L738+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L248
	ldr	r3, .L738+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L249
.L248:
	ldr	r3, .L738+316
	ldr	r3, [r3]	@ float
	ldr	r1, .L738+384
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
.L249:
	ldr	r3, .L738+320
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L738+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L251
	ldr	r3, .L738+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L738+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L251
	ldr	r3, .L738+408
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L738+312
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L738+316
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L252
.L251:
	ldr	r3, .L738+408
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L738+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L252
	ldr	r3, .L738+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L252:
	ldr	r3, .L738+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L254
	ldr	r3, .L738+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L254
	ldr	r3, .L738+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L254
	ldr	r3, .L738+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L254
	ldr	r3, .L738+316
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L255
.L254:
	ldr	r3, .L738+320
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L255
	ldr	r3, .L738+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L255
	ldr	r3, .L738+408
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L255
	ldr	r3, .L738+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L738+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L255:
	ldr	r3, .L738+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L256
	ldr	r3, .L738+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L256
	ldr	r3, .L738+312
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L257
	mov	r3, #0
	mov	r4, r3
.L257:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L256
	ldr	r3, .L738+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L256
	ldr	r3, .L738+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L256
	ldr	r3, .L738+312
	ldr	r3, [r3]	@ float
	ldr	r2, .L738+316
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L258
.L256:
	ldr	r3, .L738+320
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L258
	ldr	r3, .L738+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L258
	ldr	r3, .L738+408
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L258
	ldr	r3, .L738+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L738+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L258:
	ldr	r3, .L738+312
	ldr	r3, [r3]	@ float
	ldr	r2, .L738+316
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L259
	ldr	r3, .L738+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L259
	ldr	r3, .L738+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L259
	ldr	r3, .L738+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L259
	ldr	r3, .L738+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L261
.L259:
	ldr	r3, .L738+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L261
	ldr	r3, .L738+320
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L261
	ldr	r3, .L738+408
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L261
	ldr	r3, .L738+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L738+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L261:
	ldr	r3, .L738+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L262
	ldr	r3, .L738+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L262
	ldr	r3, .L738+312
	ldr	r3, [r3]	@ float
	ldr	r1, .L738+384
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L262
	ldr	r3, .L738+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L262
	ldr	r3, .L738+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L262
	ldr	r3, .L738+312
	ldr	r3, [r3]	@ float
	ldr	r2, .L738+316
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L264
.L262:
	ldr	r3, .L738+320
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L264
	ldr	r3, .L738+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L264
	ldr	r3, .L738+408
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L264
	ldr	r3, .L738+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L738+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L264:
	ldr	r3, .L738+344
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L265
	ldr	r3, .L738+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L266
.L265:
	ldr	r3, .L738+344
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L267
	ldr	r3, .L738+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L266
.L267:
	ldr	r3, .L738+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L268
	ldr	r3, .L738+344
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L266
.L268:
	ldr	r3, .L738+344
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L738+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L266:
	ldr	r3, .L738+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L269
	ldr	r3, .L738+340
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L270
.L269:
	ldr	r3, .L738+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L271
	ldr	r3, .L738+340
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L270
.L271:
	ldr	r3, .L738+340
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L272
	ldr	r3, .L738+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L270
.L272:
	ldr	r3, .L738+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L738+340
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L270:
	ldr	r3, .L738+344
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L273
	ldr	r3, .L738+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L274
.L273:
	ldr	r3, .L738+356
	ldr	r3, [r3]	@ float
	ldr	r1, .L738+384
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
.L274:
	ldr	r3, .L738+360
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L738+344
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L276
	ldr	r3, .L738+364
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L738+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L276
	ldr	r3, .L738+408
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L738+352
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L738+356
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L277
.L276:
	ldr	r3, .L738+408
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L738+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L277
	ldr	r3, .L738+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L277:
	ldr	r3, .L738+344
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L279
	ldr	r3, .L738+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L279
	ldr	r3, .L738+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L279
	ldr	r3, .L738+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L279
	ldr	r3, .L738+356
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L280
.L279:
	ldr	r3, .L738+360
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L280
	ldr	r3, .L738+364
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L280
	ldr	r3, .L738+408
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L280
	ldr	r3, .L738+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L738+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L280:
	ldr	r3, .L738+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L281
	ldr	r3, .L738+344
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L281
	ldr	r3, .L738+352
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L282
	mov	r3, #0
	mov	r4, r3
.L282:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L281
	ldr	r3, .L738+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L281
	ldr	r3, .L738+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L281
	ldr	r3, .L738+352
	ldr	r3, [r3]	@ float
	ldr	r2, .L738+356
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L283
.L281:
	ldr	r3, .L738+360
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L283
	ldr	r3, .L738+364
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L283
	ldr	r3, .L738+408
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L283
	ldr	r3, .L738+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L738+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L283:
	ldr	r3, .L738+352
	ldr	r3, [r3]	@ float
	ldr	r2, .L738+356
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L284
	ldr	r3, .L738+344
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L284
	ldr	r3, .L738+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L284
	ldr	r3, .L738+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L284
	ldr	r3, .L738+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L286
.L284:
	ldr	r3, .L738+364
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L286
	ldr	r3, .L738+360
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L286
	ldr	r3, .L738+408
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L286
	ldr	r3, .L738+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L738+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L286:
	ldr	r3, .L738+344
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L287
	ldr	r3, .L738+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L287
	ldr	r3, .L738+352
	ldr	r3, [r3]	@ float
	ldr	r1, .L738+384
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L287
	ldr	r3, .L738+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L287
	ldr	r3, .L738+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L287
	ldr	r3, .L738+352
	ldr	r3, [r3]	@ float
	ldr	r2, .L738+356
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L289
.L287:
	ldr	r3, .L738+360
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L289
	ldr	r3, .L738+364
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L289
	ldr	r3, .L738+408
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L289
	ldr	r3, .L738+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L738+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L289:
	ldr	r3, .L738+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L290
	ldr	r3, .L738+420
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L291
.L290:
	ldr	r3, .L738+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L292
	ldr	r3, .L738+420
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L291
.L292:
	ldr	r3, .L738+420
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L293
	ldr	r3, .L738+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L291
.L293:
	ldr	r3, .L738+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L738+420
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L291:
	ldr	r3, .L738+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L294
	ldr	r3, .L738+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L295
.L294:
	ldr	r3, .L738+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L296
	ldr	r3, .L738+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L295
.L296:
	ldr	r3, .L738+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L297
	ldr	r3, .L738+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L295
.L297:
	ldr	r3, .L738+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L738+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L295:
	ldr	r3, .L738+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L298
	ldr	r3, .L738+420
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L299
.L298:
	ldr	r3, .L738+396
	ldr	r3, [r3]	@ float
	ldr	r1, .L738+384
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
.L299:
	ldr	r3, .L738+400
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L738+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L301
	ldr	r3, .L738+404
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L738+420
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L301
	ldr	r3, .L738+408
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L738+388
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L738+396
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L301:
	ldr	r3, .L738+408
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L738+412
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L738+416
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L302:
	ldr	r3, .L738+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L304
	ldr	r3, .L738+420
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L304
	ldr	r3, .L738+412
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L304
	ldr	r3, .L738+416
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L304
	ldr	r3, .L738+396
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L305
.L304:
	ldr	r3, .L738+400
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L305
	ldr	r3, .L738+404
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L305
	ldr	r3, .L738+408
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L305
	ldr	r3, .L738+412
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L738+416
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L305:
	ldr	r3, .L738+420
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L306
	ldr	r3, .L741
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L306
	ldr	r3, .L741+4
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L307
	mov	r3, #0
	mov	r4, r3
.L307:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L306
	ldr	r3, .L741+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L306
	ldr	r3, .L741+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L306
	ldr	r3, .L741+4
	ldr	r3, [r3]	@ float
	ldr	r2, .L741+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L308
.L306:
	ldr	r3, .L741+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L308
	ldr	r3, .L741+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L308
	ldr	r3, .L741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L308
	ldr	r3, .L741+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L741+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L308:
	ldr	r3, .L741+4
	ldr	r3, [r3]	@ float
	ldr	r2, .L741+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L309
	ldr	r3, .L741
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L309
	ldr	r3, .L741+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L309
	ldr	r3, .L741+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L309
	ldr	r3, .L741+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L311
.L309:
	ldr	r3, .L741+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L311
	ldr	r3, .L741+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L311
	ldr	r3, .L741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L311
	ldr	r3, .L741+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L741+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L311:
	ldr	r3, .L741
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L312
	ldr	r3, .L741+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L312
	ldr	r3, .L741+4
	ldr	r3, [r3]	@ float
	ldr	r1, .L741+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L312
	ldr	r3, .L741+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L312
	ldr	r3, .L741+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L312
	ldr	r3, .L741+4
	ldr	r3, [r3]	@ float
	ldr	r2, .L741+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L314
.L312:
	ldr	r3, .L741+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L314
	ldr	r3, .L741+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L314
	ldr	r3, .L741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L314
	ldr	r3, .L741+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L741+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L314:
	ldr	r3, .L741+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L315
	ldr	r3, .L741+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L316
.L315:
	ldr	r3, .L741+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L317
	ldr	r3, .L741+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L316
.L317:
	ldr	r3, .L741+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L318
	ldr	r3, .L741+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L316
.L318:
	ldr	r3, .L741+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L741+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L316:
	ldr	r3, .L741+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L319
	ldr	r3, .L741+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L320
.L319:
	ldr	r3, .L741+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L321
	ldr	r3, .L741+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L320
.L321:
	ldr	r3, .L741+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L322
	ldr	r3, .L741+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L320
.L322:
	ldr	r3, .L741+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L741+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L320:
	ldr	r3, .L741+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L323
	ldr	r3, .L741+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L324
.L323:
	ldr	r3, .L741+48
	ldr	r3, [r3]	@ float
	ldr	r1, .L741+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
.L324:
	ldr	r3, .L741+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L741+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L326
	ldr	r3, .L741+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L741+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L326
	ldr	r3, .L741+160
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L741+60
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L741+48
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L327
.L326:
	ldr	r3, .L741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L741+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L327
	ldr	r3, .L741+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L327:
	ldr	r3, .L741+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L329
	ldr	r3, .L741+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L329
	ldr	r3, .L741+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L329
	ldr	r3, .L741+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L329
	ldr	r3, .L741+48
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L330
.L329:
	ldr	r3, .L741+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L330
	ldr	r3, .L741+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L330
	ldr	r3, .L741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L330
	ldr	r3, .L741+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L741+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L330:
	ldr	r3, .L741+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L331
	ldr	r3, .L741+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L331
	ldr	r3, .L741+60
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L332
	mov	r3, #0
	mov	r4, r3
.L332:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L331
	ldr	r3, .L741+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L331
	ldr	r3, .L741+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L331
	ldr	r3, .L741+60
	ldr	r3, [r3]	@ float
	ldr	r2, .L741+48
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L333
.L331:
	ldr	r3, .L741+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L333
	ldr	r3, .L741+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L333
	ldr	r3, .L741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L333
	ldr	r3, .L741+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L741+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L333:
	ldr	r3, .L741+60
	ldr	r3, [r3]	@ float
	ldr	r2, .L741+48
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L334
	ldr	r3, .L741+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L334
	ldr	r3, .L741+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L334
	ldr	r3, .L741+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L334
	ldr	r3, .L741+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L336
.L334:
	ldr	r3, .L741+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L336
	ldr	r3, .L741+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L336
	ldr	r3, .L741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L336
	ldr	r3, .L741+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L741+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L336:
	ldr	r3, .L741+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L337
	ldr	r3, .L741+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L337
	ldr	r3, .L741+60
	ldr	r3, [r3]	@ float
	ldr	r1, .L741+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L337
	ldr	r3, .L741+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L337
	ldr	r3, .L741+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L337
	ldr	r3, .L741+60
	ldr	r3, [r3]	@ float
	ldr	r2, .L741+48
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L339
.L337:
	ldr	r3, .L741+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L339
	ldr	r3, .L741+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L339
	ldr	r3, .L741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L339
	ldr	r3, .L741+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L741+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L339:
	ldr	r3, .L741+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L340
	ldr	r3, .L741+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L341
.L340:
	ldr	r3, .L741+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L342
	ldr	r3, .L741+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L341
.L342:
	ldr	r3, .L741+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L343
	ldr	r3, .L741+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L341
.L343:
	ldr	r3, .L741+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L741+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L341:
	ldr	r3, .L741+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L344
	ldr	r3, .L741+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L345
.L344:
	ldr	r3, .L741+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L346
	ldr	r3, .L741+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L345
.L346:
	ldr	r3, .L741+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L347
	ldr	r3, .L741+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L345
.L347:
	ldr	r3, .L741+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L741+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L345:
	ldr	r3, .L741+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L348
	ldr	r3, .L741+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L349
.L348:
	ldr	r3, .L741+88
	ldr	r3, [r3]	@ float
	ldr	r1, .L741+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
.L349:
	ldr	r3, .L741+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L741+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L351
	ldr	r3, .L741+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L741+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L351
	ldr	r3, .L741+160
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L741+100
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L741+88
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L352
.L351:
	ldr	r3, .L741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L741+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L352
	ldr	r3, .L741+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L352:
	ldr	r3, .L741+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L354
	ldr	r3, .L741+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L354
	ldr	r3, .L741+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L354
	ldr	r3, .L741+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L354
	ldr	r3, .L741+88
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L355
.L354:
	ldr	r3, .L741+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L355
	ldr	r3, .L741+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L355
	ldr	r3, .L741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L355
	ldr	r3, .L741+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L741+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L355:
	ldr	r3, .L741+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L356
	ldr	r3, .L741+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L356
	ldr	r3, .L741+100
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L357
	mov	r3, #0
	mov	r4, r3
.L357:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L356
	ldr	r3, .L741+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L356
	ldr	r3, .L741+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L356
	ldr	r3, .L741+100
	ldr	r3, [r3]	@ float
	ldr	r2, .L741+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L358
.L356:
	ldr	r3, .L741+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L358
	ldr	r3, .L741+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L358
	ldr	r3, .L741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L358
	ldr	r3, .L741+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L741+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L358:
	ldr	r3, .L741+100
	ldr	r3, [r3]	@ float
	ldr	r2, .L741+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L359
	ldr	r3, .L741+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L359
	ldr	r3, .L741+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L359
	ldr	r3, .L741+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L359
	ldr	r3, .L741+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L361
.L359:
	ldr	r3, .L741+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L361
	ldr	r3, .L741+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L361
	ldr	r3, .L741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L361
	ldr	r3, .L741+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L741+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L361:
	ldr	r3, .L741+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L362
	ldr	r3, .L741+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L362
	ldr	r3, .L741+100
	ldr	r3, [r3]	@ float
	ldr	r1, .L741+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L362
	ldr	r3, .L741+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L362
	ldr	r3, .L741+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L362
	ldr	r3, .L741+100
	ldr	r3, [r3]	@ float
	ldr	r2, .L741+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L364
.L362:
	ldr	r3, .L741+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L364
	ldr	r3, .L741+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L364
	ldr	r3, .L741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L364
	ldr	r3, .L741+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L741+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L364:
	ldr	r3, .L741+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L365
	ldr	r3, .L741+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L366
.L365:
	ldr	r3, .L741+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L367
	ldr	r3, .L741+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L366
.L367:
	ldr	r3, .L741+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L368
	ldr	r3, .L741+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L366
.L368:
	ldr	r3, .L741+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L741+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L366:
	ldr	r3, .L741+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L369
	ldr	r3, .L741+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L370
.L369:
	ldr	r3, .L741+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L371
	ldr	r3, .L741+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L370
.L371:
	ldr	r3, .L741+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L372
	ldr	r3, .L741+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L370
.L372:
	ldr	r3, .L741+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L741+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L370:
	ldr	r3, .L741+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L373
	ldr	r3, .L741+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L374
.L373:
	ldr	r3, .L741+132
	ldr	r3, [r3]	@ float
	ldr	r1, .L741+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	b	.L742
.L743:
	.align	2
.L741:
	.word	_x_t8_l0
	.word	t8_x
	.word	t8_evt0
	.word	t8_evt1
	.word	_x_t8_x
	.word	t8_l0
	.word	t8_l1
	.word	_x_t8_l1
	.word	_x_t7_l0
	.word	_x_t7_l1
	.word	_x_t7_evt0
	.word	_x_t7_evt1
	.word	_x_t7_x
	.word	t7_l0
	.word	t7_l1
	.word	t7_x
	.word	t7_evt0
	.word	t7_evt1
	.word	_x_t6_l0
	.word	_x_t6_l1
	.word	_x_t6_evt0
	.word	_x_t6_evt1
	.word	_x_t6_x
	.word	t6_l0
	.word	t6_l1
	.word	t6_x
	.word	t6_evt0
	.word	t6_evt1
	.word	_x_t5_evt0
	.word	_x_t5_evt1
	.word	_x_t5_l0
	.word	_x_t5_l1
	.word	t5_x
	.word	_x_t5_x
	.word	t5_l0
	.word	t5_l1
	.word	t5_evt0
	.word	t5_evt1
	.word	_x_t4_evt0
	.word	_x_t4_evt1
	.word	delta
	.word	_x_t4_l0
	.word	_x_t4_l1
	.word	t4_x
	.word	_x_t4_x
	.word	t4_l0
	.word	t4_l1
	.word	t4_evt0
	.word	t4_evt1
	.word	_x_t3_evt0
	.word	_x_t3_evt1
	.word	1084227584
	.word	t3_x
	.word	_x_t3_x
	.word	_x_t3_l0
	.word	_x_t3_l1
	.word	t3_evt1
	.word	t3_l1
	.word	t3_l0
	.word	delta
	.word	t3_evt0
.L742:
	cmp	r3, #0
	beq	.L193
.L374:
	ldr	r3, .L741+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L741+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L376
	ldr	r3, .L741+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L741+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L376
	ldr	r3, .L741+160
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L741+128
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L741+132
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L377
.L376:
	ldr	r3, .L741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L741+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L377
	ldr	r3, .L741+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L377:
	ldr	r3, .L741+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L379
	ldr	r3, .L741+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L379
	ldr	r3, .L741+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L379
	ldr	r3, .L741+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L379
	ldr	r3, .L741+132
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L380
.L379:
	ldr	r3, .L741+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L380
	ldr	r3, .L741+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L380
	ldr	r3, .L741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L380
	ldr	r3, .L741+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L741+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L380:
	ldr	r3, .L741+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L381
	ldr	r3, .L741+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L381
	ldr	r3, .L741+128
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L382
	mov	r3, #0
	mov	r4, r3
.L382:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L381
	ldr	r3, .L741+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L381
	ldr	r3, .L741+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L381
	ldr	r3, .L741+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L741+132
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L383
.L381:
	ldr	r3, .L741+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L383
	ldr	r3, .L741+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L383
	ldr	r3, .L741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L383
	ldr	r3, .L741+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L741+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L383:
	ldr	r3, .L741+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L741+132
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L384
	ldr	r3, .L741+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L384
	ldr	r3, .L741+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L384
	ldr	r3, .L741+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L384
	ldr	r3, .L741+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L386
.L384:
	ldr	r3, .L741+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L386
	ldr	r3, .L741+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L386
	ldr	r3, .L741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L386
	ldr	r3, .L741+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L741+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L386:
	ldr	r3, .L741+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L387
	ldr	r3, .L741+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L387
	ldr	r3, .L741+128
	ldr	r3, [r3]	@ float
	ldr	r1, .L741+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L387
	ldr	r3, .L741+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L387
	ldr	r3, .L741+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L387
	ldr	r3, .L741+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L741+132
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L389
.L387:
	ldr	r3, .L741+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L389
	ldr	r3, .L741+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L389
	ldr	r3, .L741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L389
	ldr	r3, .L741+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L741+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L389:
	ldr	r3, .L741+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L390
	ldr	r3, .L741+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L391
.L390:
	ldr	r3, .L741+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L392
	ldr	r3, .L741+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L391
.L392:
	ldr	r3, .L741+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L393
	ldr	r3, .L741+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L391
.L393:
	ldr	r3, .L741+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L741+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L391:
	ldr	r3, .L741+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L394
	ldr	r3, .L741+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L395
.L394:
	ldr	r3, .L741+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L396
	ldr	r3, .L741+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L395
.L396:
	ldr	r3, .L741+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L397
	ldr	r3, .L741+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L395
.L397:
	ldr	r3, .L741+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L741+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L395:
	ldr	r3, .L741+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L398
	ldr	r3, .L741+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L399
.L398:
	ldr	r3, .L741+176
	ldr	r3, [r3]	@ float
	ldr	r1, .L741+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
.L399:
	ldr	r3, .L741+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L741+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L401
	ldr	r3, .L741+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L741+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L401
	ldr	r3, .L741+160
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L741+172
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L741+176
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L402
.L401:
	ldr	r3, .L741+236
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L741+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L402
	ldr	r3, .L741+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L402:
	ldr	r3, .L741+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L404
	ldr	r3, .L741+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L404
	ldr	r3, .L741+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L404
	ldr	r3, .L741+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L404
	ldr	r3, .L741+176
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L405
.L404:
	ldr	r3, .L741+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L405
	ldr	r3, .L741+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L405
	ldr	r3, .L741+236
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L405
	ldr	r3, .L741+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L741+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L405:
	ldr	r3, .L741+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L406
	ldr	r3, .L741+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L406
	ldr	r3, .L741+172
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L407
	mov	r3, #0
	mov	r4, r3
.L407:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L406
	ldr	r3, .L741+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L406
	ldr	r3, .L741+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L406
	ldr	r3, .L741+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L741+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L408
.L406:
	ldr	r3, .L741+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L408
	ldr	r3, .L741+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L408
	ldr	r3, .L741+236
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L408
	ldr	r3, .L741+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L741+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L408:
	ldr	r3, .L741+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L741+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L409
	ldr	r3, .L741+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L409
	ldr	r3, .L741+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L409
	ldr	r3, .L741+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L409
	ldr	r3, .L741+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L411
.L409:
	ldr	r3, .L741+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L411
	ldr	r3, .L741+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L411
	ldr	r3, .L741+236
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L411
	ldr	r3, .L741+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L741+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L411:
	ldr	r3, .L741+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L412
	ldr	r3, .L741+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L412
	ldr	r3, .L741+172
	ldr	r3, [r3]	@ float
	ldr	r1, .L741+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L412
	ldr	r3, .L741+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L412
	ldr	r3, .L741+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L412
	ldr	r3, .L741+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L741+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L414
.L412:
	ldr	r3, .L741+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L414
	ldr	r3, .L741+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L414
	ldr	r3, .L741+236
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L414
	ldr	r3, .L741+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L741+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L414:
	ldr	r3, .L741+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L415
	ldr	r3, .L741+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L416
.L415:
	ldr	r3, .L741+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L417
	ldr	r3, .L741+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L416
.L417:
	ldr	r3, .L741+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L418
	ldr	r3, .L741+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L416
.L418:
	ldr	r3, .L741+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L741+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L416:
	ldr	r3, .L741+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L419
	ldr	r3, .L741+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L420
.L419:
	ldr	r3, .L741+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L421
	ldr	r3, .L741+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L420
.L421:
	ldr	r3, .L741+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L422
	ldr	r3, .L741+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L420
.L422:
	ldr	r3, .L741+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L741+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L420:
	ldr	r3, .L741+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L423
	ldr	r3, .L741+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L424
.L423:
	ldr	r3, .L741+212
	ldr	r3, [r3]	@ float
	ldr	r1, .L741+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
.L424:
	ldr	r3, .L741+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L741+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L426
	ldr	r3, .L741+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L741+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L426
	ldr	r3, .L741+236
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L741+208
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L741+212
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L427
.L426:
	ldr	r3, .L741+236
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L741+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L427
	ldr	r3, .L741+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L427:
	ldr	r3, .L741+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L429
	ldr	r3, .L741+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L429
	ldr	r3, .L741+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L429
	ldr	r3, .L741+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L429
	ldr	r3, .L741+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L430
.L429:
	ldr	r3, .L741+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L430
	ldr	r3, .L741+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L430
	ldr	r3, .L741+236
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L430
	ldr	r3, .L741+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L741+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L430:
	ldr	r3, .L741+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L431
	ldr	r3, .L741+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L431
	ldr	r3, .L741+208
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L432
	mov	r3, #0
	mov	r4, r3
.L432:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L431
	ldr	r3, .L741+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L431
	ldr	r3, .L741+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L431
	ldr	r3, .L741+208
	ldr	r3, [r3]	@ float
	ldr	r2, .L741+212
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L433
.L431:
	ldr	r3, .L741+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L433
	ldr	r3, .L741+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L433
	ldr	r3, .L741+236
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L433
	ldr	r3, .L741+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L741+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L433:
	ldr	r3, .L741+208
	ldr	r3, [r3]	@ float
	ldr	r2, .L741+212
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L434
	ldr	r3, .L741+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L434
	ldr	r3, .L741+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L434
	ldr	r3, .L741+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L434
	ldr	r3, .L741+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L436
.L434:
	ldr	r3, .L741+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L436
	ldr	r3, .L741+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L436
	ldr	r3, .L741+236
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L436
	ldr	r3, .L741+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L744
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L436:
	ldr	r3, .L744+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L437
	ldr	r3, .L744+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L437
	ldr	r3, .L744+12
	ldr	r3, [r3]	@ float
	ldr	r1, .L744+16
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L437
	ldr	r3, .L744
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L437
	ldr	r3, .L744+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L437
	ldr	r3, .L744+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L744+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L439
.L437:
	ldr	r3, .L744+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L439
	ldr	r3, .L744+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L439
	ldr	r3, .L744+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L439
	ldr	r3, .L744+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L744
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L439:
	ldr	r3, .L744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L440
	ldr	r3, .L744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L441
.L440:
	ldr	r3, .L744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L442
	ldr	r3, .L744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L441
.L442:
	ldr	r3, .L744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L443
	ldr	r3, .L744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L441
.L443:
	ldr	r3, .L744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L441:
	ldr	r3, .L744+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L444
	ldr	r3, .L744+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L445
.L444:
	ldr	r3, .L744+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L446
	ldr	r3, .L744+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L445
.L446:
	ldr	r3, .L744+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L447
	ldr	r3, .L744+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L445
.L447:
	ldr	r3, .L744+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L744+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L445:
	ldr	r3, .L744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L448
	ldr	r3, .L744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L449
.L448:
	ldr	r3, .L744+52
	ldr	r3, [r3]	@ float
	ldr	r1, .L744+16
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
.L449:
	ldr	r3, .L744+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L451
	ldr	r3, .L744+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L451
	ldr	r3, .L744+152
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L744+64
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L744+52
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L452
.L451:
	ldr	r3, .L744+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L744+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L452
	ldr	r3, .L744+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L452:
	ldr	r3, .L744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L454
	ldr	r3, .L744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L454
	ldr	r3, .L744+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L454
	ldr	r3, .L744+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L454
	ldr	r3, .L744+52
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L455
.L454:
	ldr	r3, .L744+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L455
	ldr	r3, .L744+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L455
	ldr	r3, .L744+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L455
	ldr	r3, .L744+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L744+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L455:
	ldr	r3, .L744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L456
	ldr	r3, .L744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L456
	ldr	r3, .L744+64
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L457
	mov	r3, #0
	mov	r4, r3
.L457:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L456
	ldr	r3, .L744+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L456
	ldr	r3, .L744+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L456
	ldr	r3, .L744+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L744+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L458
.L456:
	ldr	r3, .L744+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L458
	ldr	r3, .L744+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L458
	ldr	r3, .L744+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L458
	ldr	r3, .L744+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L744+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L458:
	ldr	r3, .L744+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L744+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L459
	ldr	r3, .L744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L459
	ldr	r3, .L744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L459
	ldr	r3, .L744+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L459
	ldr	r3, .L744+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L461
.L459:
	ldr	r3, .L744+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L461
	ldr	r3, .L744+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L461
	ldr	r3, .L744+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L461
	ldr	r3, .L744+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L744+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L461:
	ldr	r3, .L744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L462
	ldr	r3, .L744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L462
	ldr	r3, .L744+64
	ldr	r3, [r3]	@ float
	ldr	r1, .L744+16
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L462
	ldr	r3, .L744+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L462
	ldr	r3, .L744+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L462
	ldr	r3, .L744+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L744+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L464
.L462:
	ldr	r3, .L744+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L464
	ldr	r3, .L744+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L464
	ldr	r3, .L744+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L464
	ldr	r3, .L744+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L744+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L464:
	ldr	r3, .L744+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L465
	ldr	r3, .L744+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L466
.L465:
	ldr	r3, .L744+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L467
	ldr	r3, .L744+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L466
.L467:
	ldr	r3, .L744+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L468
	ldr	r3, .L744+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L466
.L468:
	ldr	r3, .L744+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L744+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L466:
	ldr	r3, .L744+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L469
	ldr	r3, .L744+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L470
.L469:
	ldr	r3, .L744+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L471
	ldr	r3, .L744+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L470
.L471:
	ldr	r3, .L744+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L472
	ldr	r3, .L744+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L470
.L472:
	ldr	r3, .L744+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L744+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L470:
	ldr	r3, .L744+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L473
	ldr	r3, .L744+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L474
.L473:
	ldr	r3, .L744+92
	ldr	r3, [r3]	@ float
	ldr	r1, .L744+16
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
.L474:
	ldr	r3, .L744+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L744+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L476
	ldr	r3, .L744+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L744+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L476
	ldr	r3, .L744+152
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L744+104
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L744+92
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L477
.L476:
	ldr	r3, .L744+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L744+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L477
	ldr	r3, .L744+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L477:
	ldr	r3, .L744+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L479
	ldr	r3, .L744+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L479
	ldr	r3, .L744+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L479
	ldr	r3, .L744+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L479
	ldr	r3, .L744+92
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L480
.L479:
	ldr	r3, .L744+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L480
	ldr	r3, .L744+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L480
	ldr	r3, .L744+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L480
	ldr	r3, .L744+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L744+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L480:
	ldr	r3, .L744+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L481
	ldr	r3, .L744+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L481
	ldr	r3, .L744+104
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L482
	mov	r3, #0
	mov	r4, r3
.L482:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L481
	ldr	r3, .L744+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L481
	ldr	r3, .L744+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L481
	ldr	r3, .L744+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L744+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L483
.L481:
	ldr	r3, .L744+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L483
	ldr	r3, .L744+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L483
	ldr	r3, .L744+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L483
	ldr	r3, .L744+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L744+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L483:
	ldr	r3, .L744+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L744+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L484
	ldr	r3, .L744+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L484
	ldr	r3, .L744+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L484
	ldr	r3, .L744+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L484
	ldr	r3, .L744+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L486
.L484:
	ldr	r3, .L744+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L486
	ldr	r3, .L744+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L486
	ldr	r3, .L744+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L486
	ldr	r3, .L744+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L744+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L486:
	ldr	r3, .L744+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L487
	ldr	r3, .L744+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L487
	ldr	r3, .L744+104
	ldr	r3, [r3]	@ float
	ldr	r1, .L744+16
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L487
	ldr	r3, .L744+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L487
	ldr	r3, .L744+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L487
	ldr	r3, .L744+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L744+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L489
.L487:
	ldr	r3, .L744+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L489
	ldr	r3, .L744+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L489
	ldr	r3, .L744+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L489
	ldr	r3, .L744+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L744+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L489:
	ldr	r3, .L744+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L490
	ldr	r3, .L744+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L491
.L490:
	ldr	r3, .L744+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L492
	ldr	r3, .L744+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L491
.L492:
	ldr	r3, .L744+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L493
	ldr	r3, .L744+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L491
.L493:
	ldr	r3, .L744+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L744+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L491:
	ldr	r3, .L744+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L494
	ldr	r3, .L744+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L495
.L494:
	ldr	r3, .L744+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L496
	ldr	r3, .L744+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L495
.L496:
	ldr	r3, .L744+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L497
	ldr	r3, .L744+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L495
.L497:
	ldr	r3, .L744+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L744+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L495:
	ldr	r3, .L744+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L498
	ldr	r3, .L744+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L499
.L498:
	ldr	r3, .L744+140
	ldr	r3, [r3]	@ float
	ldr	r1, .L744+16
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
.L499:
	ldr	r3, .L744+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L744+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L501
	ldr	r3, .L744+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L744+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L501
	ldr	r3, .L744+152
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L744+136
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L744+140
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L502
.L501:
	ldr	r3, .L744+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L744+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L502
	ldr	r3, .L744+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L502:
	ldr	r3, .L744+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L504
	ldr	r3, .L744+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L504
	ldr	r3, .L744+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L504
	ldr	r3, .L744+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L504
	ldr	r3, .L744+140
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	b	.L745
.L746:
	.align	2
.L744:
	.word	t3_evt1
	.word	_x_t3_l0
	.word	_x_t3_l1
	.word	t3_x
	.word	1084227584
	.word	t3_evt0
	.word	_x_t3_x
	.word	t3_l0
	.word	t3_l1
	.word	_x_t2_l0
	.word	_x_t2_l1
	.word	_x_t2_evt0
	.word	_x_t2_evt1
	.word	_x_t2_x
	.word	t2_l0
	.word	t2_l1
	.word	t2_x
	.word	t2_evt0
	.word	t2_evt1
	.word	_x_t1_l0
	.word	_x_t1_l1
	.word	_x_t1_evt0
	.word	_x_t1_evt1
	.word	_x_t1_x
	.word	t1_l0
	.word	t1_l1
	.word	t1_x
	.word	t1_evt0
	.word	t1_evt1
	.word	_x_t0_evt0
	.word	_x_t0_evt1
	.word	_x_t0_l0
	.word	_x_t0_l1
	.word	1084227584
	.word	t0_x
	.word	_x_t0_x
	.word	t0_l0
	.word	t0_l1
	.word	delta
	.word	t0_evt0
	.word	t0_evt1
	.word	_x_controller_evt2
	.word	_x_controller_evt0
	.word	_x_controller_evt1
	.word	_x_controller_z
	.word	_x_controller_l0
	.word	controller_l0
	.word	controller_l1
	.word	controller_cnt
	.word	_x_controller_cnt
	.word	controller_z
	.word	delta
	.word	controller_evt2
	.word	controller_evt0
	.word	controller_evt1
	.word	_x_controller_l1
.L745:
	bne	.L505
.L504:
	ldr	r3, .L744+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L505
	ldr	r3, .L744+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L505
	ldr	r3, .L744+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L505
	ldr	r3, .L744+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L744+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L505:
	ldr	r3, .L744+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L506
	ldr	r3, .L744+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L506
	ldr	r3, .L744+136
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L507
	mov	r3, #0
	mov	r4, r3
.L507:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L506
	ldr	r3, .L744+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L506
	ldr	r3, .L744+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L506
	ldr	r3, .L744+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L744+140
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L508
.L506:
	ldr	r3, .L744+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L508
	ldr	r3, .L744+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L508
	ldr	r3, .L744+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L508
	ldr	r3, .L744+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L744+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L508:
	ldr	r3, .L744+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L744+140
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L509
	ldr	r3, .L744+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L509
	ldr	r3, .L744+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L509
	ldr	r3, .L744+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L509
	ldr	r3, .L744+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L511
.L509:
	ldr	r3, .L744+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L511
	ldr	r3, .L744+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L511
	ldr	r3, .L744+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L511
	ldr	r3, .L744+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L744+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L511:
	ldr	r3, .L744+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L512
	ldr	r3, .L744+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L512
	ldr	r3, .L744+136
	ldr	r3, [r3]	@ float
	ldr	r1, .L744+132
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L512
	ldr	r3, .L744+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L512
	ldr	r3, .L744+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L512
	ldr	r3, .L744+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L744+140
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L514
.L512:
	ldr	r3, .L744+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L514
	ldr	r3, .L744+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L514
	ldr	r3, .L744+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L514
	ldr	r3, .L744+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L744+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L514:
	ldr	r3, .L744+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L515
	ldr	r3, .L744+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L516
.L515:
	ldr	r3, .L744+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L517
	ldr	r3, .L744+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L516
.L517:
	ldr	r3, .L744+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L518
	ldr	r3, .L744+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L516
.L518:
	ldr	r3, .L744+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L744+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L516:
	ldr	r3, .L744+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L519
	ldr	r3, .L744+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L519
	ldr	r3, .L744+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L520
.L519:
	ldr	r3, .L744+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L521
	ldr	r3, .L744+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L521
	ldr	r3, .L744+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L520
.L521:
	ldr	r3, .L744+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L522
	ldr	r3, .L744+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L522
	ldr	r3, .L744+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L520
.L522:
	ldr	r3, .L744+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L523
	ldr	r3, .L744+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L523
	ldr	r3, .L744+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L520
.L523:
	ldr	r3, .L744+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L744+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L744+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L520:
	ldr	r3, .L744+196
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L524
	ldr	r3, .L744+196
	ldr	r3, [r3]
	cmp	r3, #1
	beq	.L524
	ldr	r3, .L744+196
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L524
	ldr	r3, .L744+196
	ldr	r3, [r3]
	cmp	r3, #3
	beq	.L524
	ldr	r3, .L744+196
	ldr	r3, [r3]
	cmp	r3, #4
	beq	.L524
	ldr	r3, .L744+196
	ldr	r3, [r3]
	cmp	r3, #5
	beq	.L524
	ldr	r3, .L744+196
	ldr	r3, [r3]
	cmp	r3, #6
	beq	.L524
	ldr	r3, .L744+196
	ldr	r3, [r3]
	cmp	r3, #7
	beq	.L524
	ldr	r3, .L744+196
	ldr	r3, [r3]
	cmp	r3, #8
	beq	.L524
	ldr	r3, .L744+196
	ldr	r3, [r3]
	cmp	r3, #9
	beq	.L524
	ldr	r3, .L744+196
	ldr	r3, [r3]
	cmp	r3, #10
	beq	.L524
	ldr	r3, .L744+196
	ldr	r3, [r3]
	cmp	r3, #11
	beq	.L524
	ldr	r3, .L744+196
	ldr	r3, [r3]
	cmp	r3, #12
	beq	.L524
	ldr	r3, .L744+196
	ldr	r3, [r3]
	cmp	r3, #13
	beq	.L524
	ldr	r3, .L744+196
	ldr	r3, [r3]
	cmp	r3, #14
	bne	.L193
.L524:
	ldr	r3, .L744+176
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L525
	ldr	r3, .L744+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L526
	ldr	r3, .L744+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L526:
	ldr	r3, .L744+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L525
	ldr	r3, .L744+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L525:
	ldr	r3, .L744+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L744+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L527
	ldr	r3, .L744+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L744+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L527
	ldr	r3, .L744+204
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L744+200
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L744+176
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L527
	ldr	r3, .L744+192
	ldr	r2, [r3]
	ldr	r3, .L744+196
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L529
.L527:
	ldr	r3, .L744+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L744+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L529
	ldr	r3, .L744+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L529
	ldr	r3, .L744+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L529:
	ldr	r3, .L744+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L531
	ldr	r3, .L744+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L531
	ldr	r3, .L744+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L531
	ldr	r3, .L744+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L531
	ldr	r3, .L744+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L531
	ldr	r3, .L744+196
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L531
	ldr	r3, .L744+176
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L532
.L531:
	ldr	r3, .L744+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L532
	ldr	r3, .L744+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L532
	ldr	r3, .L744+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L532
	ldr	r3, .L744+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L744+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L744+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L532:
	ldr	r3, .L744+200
	ldr	r3, [r3]	@ float
	ldr	r2, .L744+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L533
	ldr	r3, .L744+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L535
	ldr	r3, .L744+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L536
.L535:
	ldr	r3, .L744+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L533
	ldr	r3, .L744+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L536
.L533:
	ldr	r3, .L744+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L536
	ldr	r3, .L744+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L536
	ldr	r3, .L744+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L536
	ldr	r3, .L744+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L744+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L744+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L536:
	ldr	r3, .L744+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L537
	ldr	r3, .L744+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L537
	ldr	r3, .L744+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L537
	ldr	r3, .L744+192
	ldr	r2, [r3]
	ldr	r3, .L744+196
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmn	r3, #1
	beq	.L538
.L537:
	ldr	r3, .L744+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L539
	ldr	r3, .L744+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L539
	ldr	r3, .L744+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L539
	ldr	r3, .L744+192
	ldr	r2, [r3]
	ldr	r3, .L744+196
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmp	r3, #1
	beq	.L538
.L539:
	ldr	r3, .L744+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L538
	ldr	r3, .L744+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L540
	ldr	r3, .L744+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L540
	ldr	r3, .L744+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L538
.L540:
	ldr	r3, .L744+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L538
	ldr	r3, .L744+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L538
	ldr	r3, .L744+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L538
	ldr	r3, .L744+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L538:
	ldr	r3, .L744+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L541
	ldr	r3, .L744+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L541
	ldr	r3, .L744+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L541
	ldr	r3, .L744+192
	ldr	r2, [r3]
	ldr	r3, .L744+196
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L541
	ldr	r3, .L744+200
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L542
.L541:
	ldr	r3, .L744+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L542
	ldr	r3, .L744+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L543
	ldr	r3, .L744+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L543
	ldr	r3, .L744+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L542
.L543:
	ldr	r3, .L744+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L542
	ldr	r3, .L744+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L542
	ldr	r3, .L744+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L542
	ldr	r3, .L744+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L542:
	ldr	r3, .L744+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L544
	ldr	r3, .L744+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L545
.L544:
	ldr	r3, .L744+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L546
	ldr	r3, .L744+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L545
.L546:
	ldr	r3, .L744+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L545
	ldr	r3, .L744+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L545
	ldr	r3, .L744+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L545
	ldr	r3, .L744+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L744+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L744+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L545:
	ldr	r3, .L744+200
	ldr	r3, [r3]	@ float
	ldr	r2, .L744+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L547
	ldr	r3, .L744+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L549
	ldr	r3, .L744+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L549
	ldr	r3, .L744+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L549
	ldr	r3, .L744+192
	ldr	r2, [r3]
	ldr	r3, .L744+196
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmn	r3, #1
	beq	.L550
.L549:
	ldr	r3, .L744+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L547
	ldr	r3, .L744+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L547
	ldr	r3, .L744+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L547
	ldr	r3, .L744+192
	ldr	r2, [r3]
	ldr	r3, .L744+196
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmp	r3, #1
	bne	.L547
	ldr	r3, .L744+192
	ldr	r3, [r3]
	cmp	r3, #1
	bgt	.L550
.L547:
	ldr	r3, .L744+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L550
	ldr	r3, .L744+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L551
	ldr	r3, .L744+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L551
	ldr	r3, .L744+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L550
.L551:
	ldr	r3, .L744+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L550
	ldr	r3, .L744+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L550
	ldr	r3, .L744+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L550
	ldr	r3, .L744+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L550:
	ldr	r3, .L744+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L552
	ldr	r3, .L744+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L552
	ldr	r3, .L744+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L552
	ldr	r3, .L744+192
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L552
	ldr	r3, .L744+196
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L552
	ldr	r3, .L744+176
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L553
.L552:
	ldr	r3, .L744+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L553
	ldr	r3, .L744+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L554
	ldr	r3, .L744+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L554
	ldr	r3, .L744+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L553
.L554:
	ldr	r3, .L744+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L553
	ldr	r3, .L744+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L553
	ldr	r3, .L744+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L553
	ldr	r3, .L744+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L553:
	ldr	r3, .L744+200
	ldr	r3, [r3]	@ float
	ldr	r2, .L744+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L555
	ldr	r3, .L744+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L557
	ldr	r3, .L744+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L558
.L557:
	ldr	r3, .L744+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L555
	ldr	r3, .L744+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L558
.L555:
	ldr	r3, .L744+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L558
	ldr	r3, .L744+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L558
	ldr	r3, .L744+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L558
	ldr	r3, .L744+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L744+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L744+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L558:
	ldr	r3, .L744+192
	ldr	r2, [r3]
	ldr	r3, .L744+196
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmn	r3, #1
	bne	.L559
	ldr	r3, .L744+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L559
	ldr	r3, .L744+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L559
	ldr	r3, .L744+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L559
	ldr	r3, .L744+200
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L560
.L559:
	ldr	r3, .L744+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L560
	ldr	r3, .L744+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L561
	ldr	r3, .L744+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L561
	ldr	r3, .L744+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L560
.L561:
	ldr	r3, .L744+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L560
	ldr	r3, .L747
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L560
	ldr	r3, .L747+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L560
	ldr	r3, .L747+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L560:
	ldr	r3, .L747+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L562
	ldr	r3, .L747+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L563
.L562:
	ldr	r3, .L747+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L564
	ldr	r3, .L747+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L563
.L564:
	ldr	r3, .L747+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L565
	ldr	r3, .L747+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L563
.L565:
	ldr	r3, .L747+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L747+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L563:
	ldr	r3, .L747+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L566
	ldr	r3, .L747+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L567
.L566:
	ldr	r3, .L747+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L568
	ldr	r3, .L747+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L567
.L568:
	ldr	r3, .L747+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L569
	ldr	r3, .L747+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L567
.L569:
	ldr	r3, .L747+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L747+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L567:
	ldr	r3, .L747+28
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L570
	ldr	r3, .L747+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L570
	ldr	r3, .L747+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L570:
	ldr	r3, .L747+28
	ldr	r3, [r3]	@ float
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L571
	ldr	r3, .L747+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L571
	ldr	r3, .L747+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L571:
	ldr	r3, .L747+540
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L747+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L572
	ldr	r3, .L747+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L747+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L572
	ldr	r3, .L747+260
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L747+476
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L747+28
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L573
.L572:
	ldr	r3, .L747+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L574
	ldr	r3, .L747+404
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L574:
	ldr	r3, .L747+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
.L573:
	ldr	r3, .L747+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L576
	ldr	r3, .L747+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L576
	ldr	r3, .L747+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L576
	ldr	r3, .L747+404
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L576
	ldr	r3, .L747+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L577
.L576:
	ldr	r3, .L747+540
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L577
	ldr	r3, .L747+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L577
	ldr	r3, .L747+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L577
	ldr	r3, .L747+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L747+404
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L577:
	ldr	r3, .L747+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L578
	ldr	r3, .L747+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L578
	ldr	r3, .L747+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L578
	ldr	r3, .L747+404
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L578
	ldr	r3, .L747+476
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L578
	ldr	r3, .L747+476
	ldr	r3, [r3]	@ float
	ldr	r2, .L747+28
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L580
.L578:
	ldr	r3, .L747+540
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L580
	ldr	r3, .L747+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L580
	ldr	r3, .L747+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L580
	ldr	r3, .L747+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L747+404
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L580:
	ldr	r3, .L747+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L581
	ldr	r3, .L747+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L581
	ldr	r3, .L747+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L581
	ldr	r3, .L747+404
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L581
	ldr	r3, .L747+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L583
.L581:
	ldr	r3, .L747+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L583
	ldr	r3, .L747+540
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L583
	ldr	r3, .L747+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L583
	ldr	r3, .L747+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L747+404
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L583:
	ldr	r3, .L747+476
	ldr	r3, [r3]	@ float
	ldr	r2, .L747+28
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L584
	ldr	r3, .L747+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L584
	ldr	r3, .L747+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L584
	ldr	r3, .L747+476
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L584
	ldr	r3, .L747+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L584
	ldr	r3, .L747+404
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L584
	ldr	r3, .L747+476
	ldr	r3, [r3]	@ float
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L587
.L584:
	ldr	r3, .L747+540
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L587
	ldr	r3, .L747+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L587
	ldr	r3, .L747+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L587
	ldr	r3, .L747+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L747+404
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L587:
	ldr	r3, .L747+256
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L747+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L589
	ldr	r3, .L747+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L590
.L589:
	ldr	r3, .L747+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L590
	ldr	r3, .L747+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L747+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L590:
	ldr	r3, .L747+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L591
	ldr	r3, .L747+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L592
.L591:
	ldr	r3, .L747+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L592
	ldr	r3, .L747+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L747+388
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L592:
	ldr	r3, .L747+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L593
	ldr	r3, .L747+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L594
.L593:
	ldr	r3, .L747+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L594
	ldr	r3, .L747+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L747+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L594:
	ldr	r3, .L747+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L595
	ldr	r3, .L747+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L596
.L595:
	ldr	r3, .L747+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L596
	ldr	r3, .L747+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L747+436
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L596:
	ldr	r3, .L747+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L597
	ldr	r3, .L747+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L598
.L597:
	ldr	r3, .L747+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L598
	ldr	r3, .L747+468
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L747+484
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L598:
	ldr	r3, .L747+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L599
	ldr	r3, .L747+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L600
.L599:
	ldr	r3, .L747+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L600
	ldr	r3, .L747+524
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L747+532
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L600:
	ldr	r3, .L747+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L601
	ldr	r3, .L747+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L602
.L601:
	ldr	r3, .L747+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L602
	ldr	r3, .L747+564
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L747+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L602:
	ldr	r3, .L747+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L603
	ldr	r3, .L747+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L604
.L603:
	ldr	r3, .L747+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L604
	ldr	r3, .L747+588
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L747+596
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L604:
	ldr	r3, .L747+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L605
	ldr	r3, .L747+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L606
.L605:
	ldr	r3, .L747+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L606
	ldr	r3, .L747+628
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L747+636
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L606:
	ldr	r3, .L747+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L607
	ldr	r3, .L747+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L608
.L607:
	ldr	r3, .L747+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L608
	ldr	r3, .L747+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L747+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L608:
	ldr	r3, .L747+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L609
	ldr	r3, .L747+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L610
.L609:
	ldr	r3, .L747+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L610
	ldr	r3, .L747+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L747+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L610:
	ldr	r3, .L747+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L611
	ldr	r3, .L747+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L612
.L611:
	ldr	r3, .L747+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L612
	ldr	r3, .L747+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L747+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L612:
	ldr	r3, .L747+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L613
	ldr	r3, .L747+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L614
.L613:
	ldr	r3, .L747+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L614
	ldr	r3, .L747+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L747+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L614:
	ldr	r3, .L747+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L615
	ldr	r3, .L747+404
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L615
	mov	r3, #1
	b	.L616
.L615:
	mov	r3, #0
.L616:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L747+420
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L617
	ldr	r3, .L747+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L617
	ldr	r3, .L747+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L617
	mov	r3, #1
	b	.L618
.L617:
	mov	r3, #0
.L618:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L619
	ldr	r3, .L747+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L193
.L619:
	ldr	r3, .L747+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L621
	ldr	r3, .L747+404
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L622
	ldr	r3, .L747+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L622
	mov	r3, #1
	b	.L623
.L622:
	mov	r3, #0
.L623:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L747+420
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L624
	ldr	r3, .L747+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L624
	ldr	r3, .L747+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L624
	mov	r3, #1
	b	.L625
.L624:
	mov	r3, #0
.L625:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L193
.L621:
	ldr	r3, .L747+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L626
	ldr	r3, .L747+420
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L627
	ldr	r3, .L747+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L627
	ldr	r3, .L747+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L627
	mov	r3, #1
	b	.L628
.L627:
	mov	r3, #0
.L628:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L747+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L629
	ldr	r3, .L747+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L630
.L629:
	ldr	r3, .L747+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L631
	ldr	r3, .L747+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L630
.L631:
	ldr	r3, .L747+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L632
	ldr	r3, .L747+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L630
.L632:
	ldr	r3, .L747+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L633
	ldr	r3, .L747+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L630
.L633:
	ldr	r3, .L747+628
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L634
	ldr	r3, .L747+636
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L630
.L634:
	ldr	r3, .L747+588
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L635
	ldr	r3, .L747+596
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L630
.L635:
	ldr	r3, .L747+564
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L636
	ldr	r3, .L747+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L630
.L636:
	ldr	r3, .L747+524
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L637
	ldr	r3, .L747+532
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L630
.L637:
	ldr	r3, .L747+468
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L638
	ldr	r3, .L747+484
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L630
.L638:
	ldr	r3, .L747+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L639
	ldr	r3, .L747+436
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L630
.L639:
	ldr	r3, .L747+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L640
	ldr	r3, .L747+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L630
.L640:
	ldr	r3, .L747+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L641
	ldr	r3, .L747+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L630
.L641:
	ldr	r3, .L747+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L642
	ldr	r3, .L747+388
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L642
.L630:
	mov	r3, #1
	b	.L643
.L642:
	mov	r3, #0
.L643:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L193
.L626:
	ldr	r3, .L747+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L644
	ldr	r3, .L747+420
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L645
	ldr	r3, .L747+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L645
	ldr	r3, .L747+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L645
	mov	r3, #1
	b	.L646
.L748:
	.align	2
.L747:
	.word	_x_controller_l0
	.word	controller_l0
	.word	controller_l1
	.word	_x_gate_l0
	.word	_x_gate_l1
	.word	_x_gate_evt0
	.word	_x_gate_evt1
	.word	_x_gate_y
	.word	_x_t12_l1
	.word	t12_l1
	.word	_x_t12_l0
	.word	t12_l0
	.word	_x_t12_evt1
	.word	t12_evt1
	.word	_x_t12_evt0
	.word	t12_evt0
	.word	_x_t12_x
	.word	t12_x
	.word	_x_t11_l1
	.word	t11_l1
	.word	_x_t11_l0
	.word	t11_l0
	.word	_x_t11_evt1
	.word	t11_evt1
	.word	_x_t11_evt0
	.word	t11_evt0
	.word	_x_t11_x
	.word	t11_x
	.word	_x_t10_l1
	.word	t10_l1
	.word	_x_t10_l0
	.word	t10_l0
	.word	_x_t10_evt1
	.word	t10_evt1
	.word	_x_t10_evt0
	.word	t10_evt0
	.word	_x_t10_x
	.word	t10_x
	.word	_x_t9_l1
	.word	t9_l1
	.word	_x_t9_l0
	.word	t9_l0
	.word	_x_t9_evt1
	.word	t9_evt1
	.word	_x_t9_evt0
	.word	t9_evt0
	.word	_x_t3_x
	.word	t3_x
	.word	_x_t2_evt1
	.word	t2_evt1
	.word	_x_t2_evt0
	.word	t2_evt0
	.word	_x_t1_l1
	.word	t1_l1
	.word	_x_t0_l1
	.word	t0_l1
	.word	_x_t1_evt0
	.word	t1_evt0
	.word	_x_t0_l0
	.word	t0_l0
	.word	_x_t0_x
	.word	t0_x
	.word	_x_t0_evt0
	.word	t0_evt0
	.word	_x_delta
	.word	delta
	.word	_x_t5_l0
	.word	t5_l0
	.word	_x_t1_l0
	.word	t1_l0
	.word	_x_t0_evt1
	.word	t0_evt1
	.word	_x_t1_x
	.word	t1_x
	.word	_x_controller_l0
	.word	controller_l0
	.word	_x_t6_evt1
	.word	t6_evt1
	.word	_x_t7_x
	.word	t7_x
	.word	_x_gate_l1
	.word	gate_l1
	.word	_x_controller_l1
	.word	controller_l1
	.word	_x_t2_l0
	.word	t2_l0
	.word	_x_controller_evt0
	.word	controller_evt0
	.word	_x_t2_l1
	.word	t2_l1
	.word	_x__diverge_delta
	.word	_diverge_delta
	.word	_x_t3_evt0
	.word	t3_evt0
	.word	_x_controller_evt1
	.word	controller_evt1
	.word	_x_t1_evt1
	.word	t1_evt1
	.word	_x_t2_x
	.word	t2_x
	.word	_x_gate_evt1
	.word	gate_evt1
	.word	_x_controller_z
	.word	controller_z
	.word	_x_controller_evt2
	.word	controller_evt2
	.word	_x_controller_cnt
	.word	controller_cnt
	.word	_x_t3_evt1
	.word	t3_evt1
	.word	_x_t4_x
	.word	t4_x
	.word	_x_t3_l0
	.word	t3_l0
	.word	_x_t3_l1
	.word	t3_l1
	.word	_x_t4_evt0
	.word	t4_evt0
	.word	_x_gate_y
	.word	gate_y
	.word	_x_t4_evt1
	.word	t4_evt1
	.word	_x_t5_x
	.word	t5_x
	.word	_x_t4_l0
	.word	t4_l0
	.word	_x_gate_evt0
	.word	gate_evt0
	.word	_x_t4_l1
	.word	t4_l1
	.word	_x_t5_evt0
	.word	t5_evt0
	.word	_x_t5_evt1
	.word	t5_evt1
	.word	_x_gate_l0
	.word	gate_l0
	.word	_x_t6_x
	.word	t6_x
	.word	_x_t5_l1
	.word	t5_l1
	.word	_x_t6_evt0
	.word	t6_evt0
	.word	_x_t6_l0
	.word	t6_l0
	.word	_x_t6_l1
	.word	t6_l1
	.word	_x_t7_evt0
	.word	t7_evt0
	.word	_x_t7_evt1
	.word	t7_evt1
	.word	_x_t8_x
	.word	t8_x
	.word	_x_t7_l0
	.word	t7_l0
	.word	_x_t7_l1
	.word	t7_l1
	.word	_x_t8_evt0
	.word	t8_evt0
	.word	_x_t8_evt1
	.word	t8_evt1
	.word	_x_t9_x
	.word	t9_x
	.word	_x_t8_l0
	.word	t8_l0
	.word	_x_t8_l1
	.word	t8_l1
.L645:
	mov	r3, #0
.L646:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L747+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L647
	ldr	r3, .L747+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L648
.L647:
	ldr	r3, .L747+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L649
	ldr	r3, .L747+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L648
.L649:
	ldr	r3, .L747+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L650
	ldr	r3, .L747+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L648
.L650:
	ldr	r3, .L747+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L651
	ldr	r3, .L747+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L648
.L651:
	ldr	r3, .L747+636
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L652
	ldr	r3, .L747+628
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L648
.L652:
	ldr	r3, .L747+596
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L653
	ldr	r3, .L747+588
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L648
.L653:
	ldr	r3, .L747+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L654
	ldr	r3, .L747+564
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L648
.L654:
	ldr	r3, .L747+532
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L655
	ldr	r3, .L747+524
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L648
.L655:
	ldr	r3, .L747+484
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L656
	ldr	r3, .L747+468
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L648
.L656:
	ldr	r3, .L747+436
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L657
	ldr	r3, .L747+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L648
.L657:
	ldr	r3, .L747+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L658
	ldr	r3, .L747+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L648
.L658:
	ldr	r3, .L747+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L659
	ldr	r3, .L747+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L648
.L659:
	ldr	r3, .L747+388
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L660
	ldr	r3, .L747+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L660
.L648:
	mov	r3, #1
	b	.L661
.L660:
	mov	r3, #0
.L661:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L193
.L644:
	ldr	r3, .L747+260
	ldr	r3, [r3]	@ float
	ldr	r2, .L747+360
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L662
	ldr	r3, .L747+364
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L663
	mov	r3, #0
	mov	r4, r3
.L663:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L193
.L662:
	ldr	r3, .L747+364
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L664
	ldr	r3, .L747+260
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L747+364
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L747+360
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
.L664:
	mov	r3, #1
	b	.L666
.L193:
	mov	r3, #0
.L666:
	str	r3, [fp, #-24]
	ldr	r3, .L747+32
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+36
	strb	r2, [r3]
	ldr	r3, .L747+40
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+44
	strb	r2, [r3]
	ldr	r3, .L747+48
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+52
	strb	r2, [r3]
	ldr	r3, .L747+56
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+60
	strb	r2, [r3]
	ldr	r3, .L747+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L747+68
	str	r3, [r2]	@ float
	ldr	r3, .L747+72
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+76
	strb	r2, [r3]
	ldr	r3, .L747+80
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+84
	strb	r2, [r3]
	ldr	r3, .L747+88
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+92
	strb	r2, [r3]
	ldr	r3, .L747+96
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+100
	strb	r2, [r3]
	ldr	r3, .L747+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L747+108
	str	r3, [r2]	@ float
	ldr	r3, .L747+112
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+116
	strb	r2, [r3]
	ldr	r3, .L747+120
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+124
	strb	r2, [r3]
	ldr	r3, .L747+128
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+132
	strb	r2, [r3]
	ldr	r3, .L747+136
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+140
	strb	r2, [r3]
	ldr	r3, .L747+144
	ldr	r3, [r3]	@ float
	ldr	r2, .L747+148
	str	r3, [r2]	@ float
	ldr	r3, .L747+152
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+156
	strb	r2, [r3]
	ldr	r3, .L747+160
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+164
	strb	r2, [r3]
	ldr	r3, .L747+168
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+172
	strb	r2, [r3]
	ldr	r3, .L747+176
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+180
	strb	r2, [r3]
	ldr	r3, .L747+184
	ldr	r3, [r3]	@ float
	ldr	r2, .L747+188
	str	r3, [r2]	@ float
	ldr	r3, .L747+192
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+196
	strb	r2, [r3]
	ldr	r3, .L747+200
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+204
	strb	r2, [r3]
	ldr	r3, .L747+208
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+212
	strb	r2, [r3]
	ldr	r3, .L747+216
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+220
	strb	r2, [r3]
	ldr	r3, .L747+224
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+228
	strb	r2, [r3]
	ldr	r3, .L747+232
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+236
	strb	r2, [r3]
	ldr	r3, .L747+240
	ldr	r3, [r3]	@ float
	ldr	r2, .L747+244
	str	r3, [r2]	@ float
	ldr	r3, .L747+248
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+252
	strb	r2, [r3]
	ldr	r3, .L747+256
	ldr	r3, [r3]	@ float
	ldr	r2, .L747+260
	str	r3, [r2]	@ float
	ldr	r3, .L747+264
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+268
	strb	r2, [r3]
	ldr	r3, .L747+272
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+276
	strb	r2, [r3]
	ldr	r3, .L747+280
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+284
	strb	r2, [r3]
	ldr	r3, .L747+288
	ldr	r3, [r3]	@ float
	ldr	r2, .L747+292
	str	r3, [r2]	@ float
	ldr	r3, .L747+296
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+300
	strb	r2, [r3]
	ldr	r3, .L747+304
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+308
	strb	r2, [r3]
	ldr	r3, .L747+312
	ldr	r3, [r3]	@ float
	ldr	r2, .L747+316
	str	r3, [r2]	@ float
	ldr	r3, .L747+320
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+324
	strb	r2, [r3]
	ldr	r3, .L747+328
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+332
	strb	r2, [r3]
	ldr	r3, .L747+336
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+340
	strb	r2, [r3]
	ldr	r3, .L747+344
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+348
	strb	r2, [r3]
	ldr	r3, .L747+352
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+356
	strb	r2, [r3]
	ldr	r3, .L747+360
	ldr	r3, [r3]	@ float
	ldr	r2, .L747+364
	str	r3, [r2]	@ float
	ldr	r3, .L747+368
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+372
	strb	r2, [r3]
	ldr	r3, .L747+376
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+380
	strb	r2, [r3]
	ldr	r3, .L747+384
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+388
	strb	r2, [r3]
	ldr	r3, .L747+392
	ldr	r3, [r3]	@ float
	ldr	r2, .L747+396
	str	r3, [r2]	@ float
	ldr	r3, .L747+400
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+404
	strb	r2, [r3]
	ldr	r3, .L747+408
	ldr	r3, [r3]	@ float
	ldr	r2, .L747+412
	str	r3, [r2]	@ float
	ldr	r3, .L747+416
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+420
	strb	r2, [r3]
	ldr	r3, .L747+424
	ldr	r3, [r3]
	ldr	r2, .L747+428
	str	r3, [r2]
	ldr	r3, .L747+432
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+436
	strb	r2, [r3]
	ldr	r3, .L747+440
	ldr	r3, [r3]	@ float
	ldr	r2, .L747+444
	str	r3, [r2]	@ float
	ldr	r3, .L747+448
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+452
	strb	r2, [r3]
	ldr	r3, .L747+456
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+460
	strb	r2, [r3]
	ldr	r3, .L747+464
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+468
	strb	r2, [r3]
	ldr	r3, .L747+472
	ldr	r3, [r3]	@ float
	ldr	r2, .L747+476
	str	r3, [r2]	@ float
	ldr	r3, .L747+480
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+484
	strb	r2, [r3]
	ldr	r3, .L747+488
	ldr	r3, [r3]	@ float
	ldr	r2, .L747+492
	str	r3, [r2]	@ float
	ldr	r3, .L747+496
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+500
	strb	r2, [r3]
	ldr	r3, .L747+504
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+508
	strb	r2, [r3]
	ldr	r3, .L747+512
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+516
	strb	r2, [r3]
	ldr	r3, .L747+520
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+524
	strb	r2, [r3]
	ldr	r3, .L747+528
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+532
	strb	r2, [r3]
	ldr	r3, .L747+536
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+540
	strb	r2, [r3]
	ldr	r3, .L747+544
	ldr	r3, [r3]	@ float
	ldr	r2, .L747+548
	str	r3, [r2]	@ float
	ldr	r3, .L747+552
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+556
	strb	r2, [r3]
	ldr	r3, .L747+560
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+564
	strb	r2, [r3]
	ldr	r3, .L747+568
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+572
	strb	r2, [r3]
	ldr	r3, .L747+576
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+580
	strb	r2, [r3]
	ldr	r3, .L747+584
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+588
	strb	r2, [r3]
	ldr	r3, .L747+592
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+596
	strb	r2, [r3]
	ldr	r3, .L747+600
	ldr	r3, [r3]	@ float
	ldr	r2, .L747+604
	str	r3, [r2]	@ float
	ldr	r3, .L747+608
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+612
	strb	r2, [r3]
	ldr	r3, .L747+616
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+620
	strb	r2, [r3]
	ldr	r3, .L747+624
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+628
	strb	r2, [r3]
	ldr	r3, .L747+632
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+636
	strb	r2, [r3]
	ldr	r3, .L747+640
	ldr	r3, [r3]	@ float
	ldr	r2, .L747+644
	str	r3, [r2]	@ float
	ldr	r3, .L747+648
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+652
	strb	r2, [r3]
	ldr	r3, .L747+656
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L747+660
	strb	r2, [r3]
.L188:
	ldr	r3, [fp, #-24]
	cmp	r3, #0
	bne	.L667
	mov	r3, #0
	mov	r0, r3
	sub	sp, fp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, fp, pc}
	.size	main, .-main
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
