	.file	"336590.c"
	.intel_syntax noprefix
	.text
	.globl	tilegx_register_names
	.section	.rodata
.LC0:
	.string	"r0"
.LC1:
	.string	"r1"
.LC2:
	.string	"r2"
.LC3:
	.string	"r3"
.LC4:
	.string	"r4"
.LC5:
	.string	"r5"
.LC6:
	.string	"r6"
.LC7:
	.string	"r7"
.LC8:
	.string	"r8"
.LC9:
	.string	"r9"
.LC10:
	.string	"r10"
.LC11:
	.string	"r11"
.LC12:
	.string	"r12"
.LC13:
	.string	"r13"
.LC14:
	.string	"r14"
.LC15:
	.string	"r15"
.LC16:
	.string	"r16"
.LC17:
	.string	"r17"
.LC18:
	.string	"r18"
.LC19:
	.string	"r19"
.LC20:
	.string	"r20"
.LC21:
	.string	"r21"
.LC22:
	.string	"r22"
.LC23:
	.string	"r23"
.LC24:
	.string	"r24"
.LC25:
	.string	"r25"
.LC26:
	.string	"r26"
.LC27:
	.string	"r27"
.LC28:
	.string	"r28"
.LC29:
	.string	"r29"
.LC30:
	.string	"r30"
.LC31:
	.string	"r31"
.LC32:
	.string	"r32"
.LC33:
	.string	"r33"
.LC34:
	.string	"r34"
.LC35:
	.string	"r35"
.LC36:
	.string	"r36"
.LC37:
	.string	"r37"
.LC38:
	.string	"r38"
.LC39:
	.string	"r39"
.LC40:
	.string	"r40"
.LC41:
	.string	"r41"
.LC42:
	.string	"r42"
.LC43:
	.string	"r43"
.LC44:
	.string	"r44"
.LC45:
	.string	"r45"
.LC46:
	.string	"r46"
.LC47:
	.string	"r47"
.LC48:
	.string	"r48"
.LC49:
	.string	"r49"
.LC50:
	.string	"r50"
.LC51:
	.string	"r51"
.LC52:
	.string	"r52"
.LC53:
	.string	"tp"
.LC54:
	.string	"sp"
.LC55:
	.string	"lr"
.LC56:
	.string	"sn"
.LC57:
	.string	"idn0"
.LC58:
	.string	"idn1"
.LC59:
	.string	"udn0"
.LC60:
	.string	"udn1"
.LC61:
	.string	"udn2"
.LC62:
	.string	"udn3"
.LC63:
	.string	"zero"
	.section	.data.rel.ro.local,"aw"
	.align 32
	.type	tilegx_register_names, @object
	.size	tilegx_register_names, 512
tilegx_register_names:
	.quad	.LC0
	.quad	.LC1
	.quad	.LC2
	.quad	.LC3
	.quad	.LC4
	.quad	.LC5
	.quad	.LC6
	.quad	.LC7
	.quad	.LC8
	.quad	.LC9
	.quad	.LC10
	.quad	.LC11
	.quad	.LC12
	.quad	.LC13
	.quad	.LC14
	.quad	.LC15
	.quad	.LC16
	.quad	.LC17
	.quad	.LC18
	.quad	.LC19
	.quad	.LC20
	.quad	.LC21
	.quad	.LC22
	.quad	.LC23
	.quad	.LC24
	.quad	.LC25
	.quad	.LC26
	.quad	.LC27
	.quad	.LC28
	.quad	.LC29
	.quad	.LC30
	.quad	.LC31
	.quad	.LC32
	.quad	.LC33
	.quad	.LC34
	.quad	.LC35
	.quad	.LC36
	.quad	.LC37
	.quad	.LC38
	.quad	.LC39
	.quad	.LC40
	.quad	.LC41
	.quad	.LC42
	.quad	.LC43
	.quad	.LC44
	.quad	.LC45
	.quad	.LC46
	.quad	.LC47
	.quad	.LC48
	.quad	.LC49
	.quad	.LC50
	.quad	.LC51
	.quad	.LC52
	.quad	.LC53
	.quad	.LC54
	.quad	.LC55
	.quad	.LC56
	.quad	.LC57
	.quad	.LC58
	.quad	.LC59
	.quad	.LC60
	.quad	.LC61
	.quad	.LC62
	.quad	.LC63
	.text
	.type	get_BFEnd_X0, @function
get_BFEnd_X0:
.LFB6:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	rax, QWORD PTR -24[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	shr	eax, 12
	and	eax, 63
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE6:
	.size	get_BFEnd_X0, .-get_BFEnd_X0
	.type	get_BFStart_X0, @function
get_BFStart_X0:
.LFB8:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	rax, QWORD PTR -24[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	shr	eax, 18
	and	eax, 63
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE8:
	.size	get_BFStart_X0, .-get_BFStart_X0
	.type	get_BrOff_X1, @function
get_BrOff_X1:
.LFB9:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	shr	rax, 31
	and	eax, 63
	mov	edx, eax
	mov	rax, QWORD PTR -8[rbp]
	shr	rax, 37
	and	eax, 131008
	or	eax, edx
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE9:
	.size	get_BrOff_X1, .-get_BrOff_X1
	.type	get_Dest_Imm8_X1, @function
get_Dest_Imm8_X1:
.LFB11:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	shr	rax, 31
	and	eax, 63
	mov	edx, eax
	mov	rax, QWORD PTR -8[rbp]
	shr	rax, 43
	and	eax, 192
	or	eax, edx
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE11:
	.size	get_Dest_Imm8_X1, .-get_Dest_Imm8_X1
	.type	get_Dest_X0, @function
get_Dest_X0:
.LFB12:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	rax, QWORD PTR -24[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	and	eax, 63
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE12:
	.size	get_Dest_X0, .-get_Dest_X0
	.type	get_Dest_X1, @function
get_Dest_X1:
.LFB13:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	shr	rax, 31
	and	eax, 63
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE13:
	.size	get_Dest_X1, .-get_Dest_X1
	.type	get_Dest_Y0, @function
get_Dest_Y0:
.LFB14:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	rax, QWORD PTR -24[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	and	eax, 63
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE14:
	.size	get_Dest_Y0, .-get_Dest_Y0
	.type	get_Dest_Y1, @function
get_Dest_Y1:
.LFB15:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	shr	rax, 31
	and	eax, 63
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE15:
	.size	get_Dest_Y1, .-get_Dest_Y1
	.type	get_Imm16_X0, @function
get_Imm16_X0:
.LFB16:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	rax, QWORD PTR -24[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	shr	eax, 12
	movzx	eax, ax
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE16:
	.size	get_Imm16_X0, .-get_Imm16_X0
	.type	get_Imm16_X1, @function
get_Imm16_X1:
.LFB17:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	shr	rax, 43
	movzx	eax, ax
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE17:
	.size	get_Imm16_X1, .-get_Imm16_X1
	.type	get_Imm8_X0, @function
get_Imm8_X0:
.LFB20:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	rax, QWORD PTR -24[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	shr	eax, 12
	movzx	eax, al
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE20:
	.size	get_Imm8_X0, .-get_Imm8_X0
	.type	get_Imm8_X1, @function
get_Imm8_X1:
.LFB21:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	shr	rax, 43
	movzx	eax, al
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE21:
	.size	get_Imm8_X1, .-get_Imm8_X1
	.type	get_Imm8_Y0, @function
get_Imm8_Y0:
.LFB22:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	rax, QWORD PTR -24[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	shr	eax, 12
	movzx	eax, al
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE22:
	.size	get_Imm8_Y0, .-get_Imm8_Y0
	.type	get_Imm8_Y1, @function
get_Imm8_Y1:
.LFB23:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	shr	rax, 43
	movzx	eax, al
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE23:
	.size	get_Imm8_Y1, .-get_Imm8_Y1
	.type	get_JumpOff_X1, @function
get_JumpOff_X1:
.LFB24:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	shr	rax, 31
	and	eax, 134217727
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE24:
	.size	get_JumpOff_X1, .-get_JumpOff_X1
	.type	get_MF_Imm14_X1, @function
get_MF_Imm14_X1:
.LFB26:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	shr	rax, 37
	and	eax, 16383
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE26:
	.size	get_MF_Imm14_X1, .-get_MF_Imm14_X1
	.type	get_MT_Imm14_X1, @function
get_MT_Imm14_X1:
.LFB27:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	shr	rax, 31
	and	eax, 63
	mov	edx, eax
	mov	rax, QWORD PTR -8[rbp]
	shr	rax, 37
	and	eax, 16320
	or	eax, edx
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE27:
	.size	get_MT_Imm14_X1, .-get_MT_Imm14_X1
	.type	get_ShAmt_X0, @function
get_ShAmt_X0:
.LFB38:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	rax, QWORD PTR -24[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	shr	eax, 12
	and	eax, 63
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE38:
	.size	get_ShAmt_X0, .-get_ShAmt_X0
	.type	get_ShAmt_X1, @function
get_ShAmt_X1:
.LFB39:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	shr	rax, 43
	and	eax, 63
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE39:
	.size	get_ShAmt_X1, .-get_ShAmt_X1
	.type	get_ShAmt_Y0, @function
get_ShAmt_Y0:
.LFB40:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	rax, QWORD PTR -24[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	shr	eax, 12
	and	eax, 63
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE40:
	.size	get_ShAmt_Y0, .-get_ShAmt_Y0
	.type	get_ShAmt_Y1, @function
get_ShAmt_Y1:
.LFB41:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	shr	rax, 43
	and	eax, 63
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE41:
	.size	get_ShAmt_Y1, .-get_ShAmt_Y1
	.type	get_SrcA_X0, @function
get_SrcA_X0:
.LFB46:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	rax, QWORD PTR -24[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	shr	eax, 6
	and	eax, 63
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE46:
	.size	get_SrcA_X0, .-get_SrcA_X0
	.type	get_SrcA_X1, @function
get_SrcA_X1:
.LFB47:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	shr	rax, 37
	and	eax, 63
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE47:
	.size	get_SrcA_X1, .-get_SrcA_X1
	.type	get_SrcA_Y0, @function
get_SrcA_Y0:
.LFB48:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	rax, QWORD PTR -24[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	shr	eax, 6
	and	eax, 63
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE48:
	.size	get_SrcA_Y0, .-get_SrcA_Y0
	.type	get_SrcA_Y1, @function
get_SrcA_Y1:
.LFB49:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	shr	rax, 37
	and	eax, 63
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE49:
	.size	get_SrcA_Y1, .-get_SrcA_Y1
	.type	get_SrcA_Y2, @function
get_SrcA_Y2:
.LFB50:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	rax, QWORD PTR -24[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	shr	eax, 20
	and	eax, 63
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE50:
	.size	get_SrcA_Y2, .-get_SrcA_Y2
	.type	get_SrcBDest_Y2, @function
get_SrcBDest_Y2:
.LFB51:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	shr	rax, 51
	and	eax, 63
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE51:
	.size	get_SrcBDest_Y2, .-get_SrcBDest_Y2
	.type	get_SrcB_X0, @function
get_SrcB_X0:
.LFB52:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	rax, QWORD PTR -24[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	shr	eax, 12
	and	eax, 63
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE52:
	.size	get_SrcB_X0, .-get_SrcB_X0
	.type	get_SrcB_X1, @function
get_SrcB_X1:
.LFB53:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	shr	rax, 43
	and	eax, 63
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE53:
	.size	get_SrcB_X1, .-get_SrcB_X1
	.type	get_SrcB_Y0, @function
get_SrcB_Y0:
.LFB54:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	rax, QWORD PTR -24[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	shr	eax, 12
	and	eax, 63
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE54:
	.size	get_SrcB_Y0, .-get_SrcB_Y0
	.type	get_SrcB_Y1, @function
get_SrcB_Y1:
.LFB55:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	shr	rax, 43
	and	eax, 63
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE55:
	.size	get_SrcB_Y1, .-get_SrcB_Y1
	.type	create_BFEnd_X0, @function
create_BFEnd_X0:
.LFB61:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	eax, 12
	mov	eax, eax
	and	eax, 258048
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE61:
	.size	create_BFEnd_X0, .-create_BFEnd_X0
	.type	create_BFStart_X0, @function
create_BFStart_X0:
.LFB63:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	eax, 18
	mov	eax, eax
	and	eax, 16515072
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE63:
	.size	create_BFStart_X0, .-create_BFStart_X0
	.type	create_BrOff_X1, @function
create_BrOff_X1:
.LFB64:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	rax, 31
	mov	rdx, rax
	movabs	rax, 135291469824
	and	rdx, rax
	mov	eax, DWORD PTR -4[rbp]
	sal	rax, 37
	mov	rcx, rax
	movabs	rax, 18005602416459776
	and	rax, rcx
	or	rax, rdx
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE64:
	.size	create_BrOff_X1, .-create_BrOff_X1
	.type	create_Dest_Imm8_X1, @function
create_Dest_Imm8_X1:
.LFB66:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	rax, 31
	mov	rdx, rax
	movabs	rax, 135291469824
	and	rdx, rax
	mov	eax, DWORD PTR -4[rbp]
	sal	rax, 43
	mov	rcx, rax
	movabs	rax, 1688849860263936
	and	rax, rcx
	or	rax, rdx
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE66:
	.size	create_Dest_Imm8_X1, .-create_Dest_Imm8_X1
	.type	create_Dest_X0, @function
create_Dest_X0:
.LFB67:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	and	eax, 63
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE67:
	.size	create_Dest_X0, .-create_Dest_X0
	.type	create_Dest_X1, @function
create_Dest_X1:
.LFB68:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	rax, 31
	mov	rdx, rax
	movabs	rax, 135291469824
	and	rax, rdx
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE68:
	.size	create_Dest_X1, .-create_Dest_X1
	.type	create_Dest_Y0, @function
create_Dest_Y0:
.LFB69:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	and	eax, 63
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE69:
	.size	create_Dest_Y0, .-create_Dest_Y0
	.type	create_Dest_Y1, @function
create_Dest_Y1:
.LFB70:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	rax, 31
	mov	rdx, rax
	movabs	rax, 135291469824
	and	rax, rdx
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE70:
	.size	create_Dest_Y1, .-create_Dest_Y1
	.type	create_Imm16_X0, @function
create_Imm16_X0:
.LFB71:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	eax, 12
	mov	eax, eax
	and	eax, 268431360
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE71:
	.size	create_Imm16_X0, .-create_Imm16_X0
	.type	create_Imm16_X1, @function
create_Imm16_X1:
.LFB72:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	rax, 43
	mov	rdx, rax
	movabs	rax, 576451956210401280
	and	rax, rdx
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE72:
	.size	create_Imm16_X1, .-create_Imm16_X1
	.type	create_Imm8_X0, @function
create_Imm8_X0:
.LFB75:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	eax, 12
	mov	eax, eax
	and	eax, 1044480
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE75:
	.size	create_Imm8_X0, .-create_Imm8_X0
	.type	create_Imm8_X1, @function
create_Imm8_X1:
.LFB76:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	rax, 43
	mov	rdx, rax
	movabs	rax, 2243003720663040
	and	rax, rdx
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE76:
	.size	create_Imm8_X1, .-create_Imm8_X1
	.type	create_Imm8_Y0, @function
create_Imm8_Y0:
.LFB77:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	eax, 12
	mov	eax, eax
	and	eax, 1044480
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE77:
	.size	create_Imm8_Y0, .-create_Imm8_Y0
	.type	create_Imm8_Y1, @function
create_Imm8_Y1:
.LFB78:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	rax, 43
	mov	rdx, rax
	movabs	rax, 2243003720663040
	and	rax, rdx
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE78:
	.size	create_Imm8_Y1, .-create_Imm8_Y1
	.type	create_JumpOff_X1, @function
create_JumpOff_X1:
.LFB79:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	rax, 31
	mov	rdx, rax
	movabs	rax, 288230374004228096
	and	rax, rdx
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE79:
	.size	create_JumpOff_X1, .-create_JumpOff_X1
	.type	create_MF_Imm14_X1, @function
create_MF_Imm14_X1:
.LFB81:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	rax, 37
	mov	rdx, rax
	movabs	rax, 2251662374731776
	and	rax, rdx
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE81:
	.size	create_MF_Imm14_X1, .-create_MF_Imm14_X1
	.type	create_MT_Imm14_X1, @function
create_MT_Imm14_X1:
.LFB82:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	rax, 31
	mov	rdx, rax
	movabs	rax, 135291469824
	and	rdx, rax
	mov	eax, DWORD PTR -4[rbp]
	sal	rax, 37
	mov	rcx, rax
	movabs	rax, 2243003720663040
	and	rax, rcx
	or	rax, rdx
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE82:
	.size	create_MT_Imm14_X1, .-create_MT_Imm14_X1
	.type	create_ShAmt_X0, @function
create_ShAmt_X0:
.LFB93:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	eax, 12
	mov	eax, eax
	and	eax, 258048
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE93:
	.size	create_ShAmt_X0, .-create_ShAmt_X0
	.type	create_ShAmt_X1, @function
create_ShAmt_X1:
.LFB94:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	rax, 43
	mov	rdx, rax
	movabs	rax, 554153860399104
	and	rax, rdx
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE94:
	.size	create_ShAmt_X1, .-create_ShAmt_X1
	.type	create_ShAmt_Y0, @function
create_ShAmt_Y0:
.LFB95:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	eax, 12
	mov	eax, eax
	and	eax, 258048
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE95:
	.size	create_ShAmt_Y0, .-create_ShAmt_Y0
	.type	create_ShAmt_Y1, @function
create_ShAmt_Y1:
.LFB96:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	rax, 43
	mov	rdx, rax
	movabs	rax, 554153860399104
	and	rax, rdx
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE96:
	.size	create_ShAmt_Y1, .-create_ShAmt_Y1
	.type	create_SrcA_X0, @function
create_SrcA_X0:
.LFB101:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	eax, 6
	mov	eax, eax
	and	eax, 4032
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE101:
	.size	create_SrcA_X0, .-create_SrcA_X0
	.type	create_SrcA_X1, @function
create_SrcA_X1:
.LFB102:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	rax, 37
	mov	rdx, rax
	movabs	rax, 8658654068736
	and	rax, rdx
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE102:
	.size	create_SrcA_X1, .-create_SrcA_X1
	.type	create_SrcA_Y0, @function
create_SrcA_Y0:
.LFB103:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	eax, 6
	mov	eax, eax
	and	eax, 4032
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE103:
	.size	create_SrcA_Y0, .-create_SrcA_Y0
	.type	create_SrcA_Y1, @function
create_SrcA_Y1:
.LFB104:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	rax, 37
	mov	rdx, rax
	movabs	rax, 8658654068736
	and	rax, rdx
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE104:
	.size	create_SrcA_Y1, .-create_SrcA_Y1
	.type	create_SrcA_Y2, @function
create_SrcA_Y2:
.LFB105:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	eax, 20
	mov	eax, eax
	and	eax, 66060288
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE105:
	.size	create_SrcA_Y2, .-create_SrcA_Y2
	.type	create_SrcBDest_Y2, @function
create_SrcBDest_Y2:
.LFB106:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	rax, 51
	mov	rdx, rax
	movabs	rax, 141863388262170624
	and	rax, rdx
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE106:
	.size	create_SrcBDest_Y2, .-create_SrcBDest_Y2
	.type	create_SrcB_X0, @function
create_SrcB_X0:
.LFB107:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	eax, 12
	mov	eax, eax
	and	eax, 258048
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE107:
	.size	create_SrcB_X0, .-create_SrcB_X0
	.type	create_SrcB_X1, @function
create_SrcB_X1:
.LFB108:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	rax, 43
	mov	rdx, rax
	movabs	rax, 554153860399104
	and	rax, rdx
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE108:
	.size	create_SrcB_X1, .-create_SrcB_X1
	.type	create_SrcB_Y0, @function
create_SrcB_Y0:
.LFB109:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	eax, 12
	mov	eax, eax
	and	eax, 258048
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE109:
	.size	create_SrcB_Y0, .-create_SrcB_Y0
	.type	create_SrcB_Y1, @function
create_SrcB_Y1:
.LFB110:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	sal	rax, 43
	mov	rdx, rax
	movabs	rax, 554153860399104
	and	rax, rdx
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE110:
	.size	create_SrcB_Y1, .-create_SrcB_Y1
	.globl	tilegx_opcodes
	.section	.rodata
.LC64:
	.string	"bpt"
.LC65:
	.string	"info"
.LC66:
	.string	"infol"
.LC67:
	.string	"ld4s_tls"
.LC68:
	.string	"ld_tls"
.LC69:
	.string	"move"
.LC70:
	.string	"movei"
.LC71:
	.string	"moveli"
.LC72:
	.string	"prefetch"
.LC73:
	.string	"prefetch_add_l1"
.LC74:
	.string	"prefetch_add_l1_fault"
.LC75:
	.string	"prefetch_add_l2"
.LC76:
	.string	"prefetch_add_l2_fault"
.LC77:
	.string	"prefetch_add_l3"
.LC78:
	.string	"prefetch_add_l3_fault"
.LC79:
	.string	"prefetch_l1"
.LC80:
	.string	"prefetch_l1_fault"
.LC81:
	.string	"prefetch_l2"
.LC82:
	.string	"prefetch_l2_fault"
.LC83:
	.string	"prefetch_l3"
.LC84:
	.string	"prefetch_l3_fault"
.LC85:
	.string	"raise"
.LC86:
	.string	"add"
.LC87:
	.string	"addi"
.LC88:
	.string	"addli"
.LC89:
	.string	"addx"
.LC90:
	.string	"addxi"
.LC91:
	.string	"addxli"
.LC92:
	.string	"addxsc"
.LC93:
	.string	"and"
.LC94:
	.string	"andi"
.LC95:
	.string	"beqz"
.LC96:
	.string	"beqzt"
.LC97:
	.string	"bfexts"
.LC98:
	.string	"bfextu"
.LC99:
	.string	"bfins"
.LC100:
	.string	"bgez"
.LC101:
	.string	"bgezt"
.LC102:
	.string	"bgtz"
.LC103:
	.string	"bgtzt"
.LC104:
	.string	"blbc"
.LC105:
	.string	"blbct"
.LC106:
	.string	"blbs"
.LC107:
	.string	"blbst"
.LC108:
	.string	"blez"
.LC109:
	.string	"blezt"
.LC110:
	.string	"bltz"
.LC111:
	.string	"bltzt"
.LC112:
	.string	"bnez"
.LC113:
	.string	"bnezt"
.LC114:
	.string	"clz"
.LC115:
	.string	"cmoveqz"
.LC116:
	.string	"cmovnez"
.LC117:
	.string	"cmpeq"
.LC118:
	.string	"cmpeqi"
.LC119:
	.string	"cmpexch"
.LC120:
	.string	"cmpexch4"
.LC121:
	.string	"cmples"
.LC122:
	.string	"cmpleu"
.LC123:
	.string	"cmplts"
.LC124:
	.string	"cmpltsi"
.LC125:
	.string	"cmpltu"
.LC126:
	.string	"cmpltui"
.LC127:
	.string	"cmpne"
.LC128:
	.string	"cmul"
.LC129:
	.string	"cmula"
.LC130:
	.string	"cmulaf"
.LC131:
	.string	"cmulf"
.LC132:
	.string	"cmulfr"
.LC133:
	.string	"cmulh"
.LC134:
	.string	"cmulhr"
.LC135:
	.string	"crc32_32"
.LC136:
	.string	"crc32_8"
.LC137:
	.string	"ctz"
.LC138:
	.string	"dblalign"
.LC139:
	.string	"dblalign2"
.LC140:
	.string	"dblalign4"
.LC141:
	.string	"dblalign6"
.LC142:
	.string	"drain"
.LC143:
	.string	"dtlbpr"
.LC144:
	.string	"exch"
.LC145:
	.string	"exch4"
.LC146:
	.string	"fdouble_add_flags"
.LC147:
	.string	"fdouble_addsub"
.LC148:
	.string	"fdouble_mul_flags"
.LC149:
	.string	"fdouble_pack1"
.LC150:
	.string	"fdouble_pack2"
.LC151:
	.string	"fdouble_sub_flags"
.LC152:
	.string	"fdouble_unpack_max"
.LC153:
	.string	"fdouble_unpack_min"
.LC154:
	.string	"fetchadd"
.LC155:
	.string	"fetchadd4"
.LC156:
	.string	"fetchaddgez"
.LC157:
	.string	"fetchaddgez4"
.LC158:
	.string	"fetchand"
.LC159:
	.string	"fetchand4"
.LC160:
	.string	"fetchor"
.LC161:
	.string	"fetchor4"
.LC162:
	.string	"finv"
.LC163:
	.string	"flush"
.LC164:
	.string	"flushwb"
.LC165:
	.string	"fnop"
.LC166:
	.string	"fsingle_add1"
.LC167:
	.string	"fsingle_addsub2"
.LC168:
	.string	"fsingle_mul1"
.LC169:
	.string	"fsingle_mul2"
.LC170:
	.string	"fsingle_pack1"
.LC171:
	.string	"fsingle_pack2"
.LC172:
	.string	"fsingle_sub1"
.LC173:
	.string	"icoh"
.LC174:
	.string	"ill"
.LC175:
	.string	"inv"
.LC176:
	.string	"iret"
.LC177:
	.string	"j"
.LC178:
	.string	"jal"
.LC179:
	.string	"jalr"
.LC180:
	.string	"jalrp"
.LC181:
	.string	"jr"
.LC182:
	.string	"jrp"
.LC183:
	.string	"ld"
.LC184:
	.string	"ld1s"
.LC185:
	.string	"ld1s_add"
.LC186:
	.string	"ld1u"
.LC187:
	.string	"ld1u_add"
.LC188:
	.string	"ld2s"
.LC189:
	.string	"ld2s_add"
.LC190:
	.string	"ld2u"
.LC191:
	.string	"ld2u_add"
.LC192:
	.string	"ld4s"
.LC193:
	.string	"ld4s_add"
.LC194:
	.string	"ld4u"
.LC195:
	.string	"ld4u_add"
.LC196:
	.string	"ld_add"
.LC197:
	.string	"ldna"
.LC198:
	.string	"ldna_add"
.LC199:
	.string	"ldnt"
.LC200:
	.string	"ldnt1s"
.LC201:
	.string	"ldnt1s_add"
.LC202:
	.string	"ldnt1u"
.LC203:
	.string	"ldnt1u_add"
.LC204:
	.string	"ldnt2s"
.LC205:
	.string	"ldnt2s_add"
.LC206:
	.string	"ldnt2u"
.LC207:
	.string	"ldnt2u_add"
.LC208:
	.string	"ldnt4s"
.LC209:
	.string	"ldnt4s_add"
.LC210:
	.string	"ldnt4u"
.LC211:
	.string	"ldnt4u_add"
.LC212:
	.string	"ldnt_add"
.LC213:
	.string	"lnk"
.LC214:
	.string	"mf"
.LC215:
	.string	"mfspr"
.LC216:
	.string	"mm"
.LC217:
	.string	"mnz"
.LC218:
	.string	"mtspr"
.LC219:
	.string	"mul_hs_hs"
.LC220:
	.string	"mul_hs_hu"
.LC221:
	.string	"mul_hs_ls"
.LC222:
	.string	"mul_hs_lu"
.LC223:
	.string	"mul_hu_hu"
.LC224:
	.string	"mul_hu_ls"
.LC225:
	.string	"mul_hu_lu"
.LC226:
	.string	"mul_ls_ls"
.LC227:
	.string	"mul_ls_lu"
.LC228:
	.string	"mul_lu_lu"
.LC229:
	.string	"mula_hs_hs"
.LC230:
	.string	"mula_hs_hu"
.LC231:
	.string	"mula_hs_ls"
.LC232:
	.string	"mula_hs_lu"
.LC233:
	.string	"mula_hu_hu"
.LC234:
	.string	"mula_hu_ls"
.LC235:
	.string	"mula_hu_lu"
.LC236:
	.string	"mula_ls_ls"
.LC237:
	.string	"mula_ls_lu"
.LC238:
	.string	"mula_lu_lu"
.LC239:
	.string	"mulax"
.LC240:
	.string	"mulx"
.LC241:
	.string	"mz"
.LC242:
	.string	"nap"
.LC243:
	.string	"nop"
.LC244:
	.string	"nor"
.LC245:
	.string	"or"
.LC246:
	.string	"ori"
.LC247:
	.string	"pcnt"
.LC248:
	.string	"revbits"
.LC249:
	.string	"revbytes"
.LC250:
	.string	"rotl"
.LC251:
	.string	"rotli"
.LC252:
	.string	"shl"
.LC253:
	.string	"shl16insli"
.LC254:
	.string	"shl1add"
.LC255:
	.string	"shl1addx"
.LC256:
	.string	"shl2add"
.LC257:
	.string	"shl2addx"
.LC258:
	.string	"shl3add"
.LC259:
	.string	"shl3addx"
.LC260:
	.string	"shli"
.LC261:
	.string	"shlx"
.LC262:
	.string	"shlxi"
.LC263:
	.string	"shrs"
.LC264:
	.string	"shrsi"
.LC265:
	.string	"shru"
.LC266:
	.string	"shrui"
.LC267:
	.string	"shrux"
.LC268:
	.string	"shruxi"
.LC269:
	.string	"shufflebytes"
.LC270:
	.string	"st"
.LC271:
	.string	"st1"
.LC272:
	.string	"st1_add"
.LC273:
	.string	"st2"
.LC274:
	.string	"st2_add"
.LC275:
	.string	"st4"
.LC276:
	.string	"st4_add"
.LC277:
	.string	"st_add"
.LC278:
	.string	"stnt"
.LC279:
	.string	"stnt1"
.LC280:
	.string	"stnt1_add"
.LC281:
	.string	"stnt2"
.LC282:
	.string	"stnt2_add"
.LC283:
	.string	"stnt4"
.LC284:
	.string	"stnt4_add"
.LC285:
	.string	"stnt_add"
.LC286:
	.string	"sub"
.LC287:
	.string	"subx"
.LC288:
	.string	"subxsc"
.LC289:
	.string	"swint0"
.LC290:
	.string	"swint1"
.LC291:
	.string	"swint2"
.LC292:
	.string	"swint3"
.LC293:
	.string	"tblidxb0"
.LC294:
	.string	"tblidxb1"
.LC295:
	.string	"tblidxb2"
.LC296:
	.string	"tblidxb3"
.LC297:
	.string	"v1add"
.LC298:
	.string	"v1addi"
.LC299:
	.string	"v1adduc"
.LC300:
	.string	"v1adiffu"
.LC301:
	.string	"v1avgu"
.LC302:
	.string	"v1cmpeq"
.LC303:
	.string	"v1cmpeqi"
.LC304:
	.string	"v1cmples"
.LC305:
	.string	"v1cmpleu"
.LC306:
	.string	"v1cmplts"
.LC307:
	.string	"v1cmpltsi"
.LC308:
	.string	"v1cmpltu"
.LC309:
	.string	"v1cmpltui"
.LC310:
	.string	"v1cmpne"
.LC311:
	.string	"v1ddotpu"
.LC312:
	.string	"v1ddotpua"
.LC313:
	.string	"v1ddotpus"
.LC314:
	.string	"v1ddotpusa"
.LC315:
	.string	"v1dotp"
.LC316:
	.string	"v1dotpa"
.LC317:
	.string	"v1dotpu"
.LC318:
	.string	"v1dotpua"
.LC319:
	.string	"v1dotpus"
.LC320:
	.string	"v1dotpusa"
.LC321:
	.string	"v1int_h"
.LC322:
	.string	"v1int_l"
.LC323:
	.string	"v1maxu"
.LC324:
	.string	"v1maxui"
.LC325:
	.string	"v1minu"
.LC326:
	.string	"v1minui"
.LC327:
	.string	"v1mnz"
.LC328:
	.string	"v1multu"
.LC329:
	.string	"v1mulu"
.LC330:
	.string	"v1mulus"
.LC331:
	.string	"v1mz"
.LC332:
	.string	"v1sadau"
.LC333:
	.string	"v1sadu"
.LC334:
	.string	"v1shl"
.LC335:
	.string	"v1shli"
.LC336:
	.string	"v1shrs"
.LC337:
	.string	"v1shrsi"
.LC338:
	.string	"v1shru"
.LC339:
	.string	"v1shrui"
.LC340:
	.string	"v1sub"
.LC341:
	.string	"v1subuc"
.LC342:
	.string	"v2add"
.LC343:
	.string	"v2addi"
.LC344:
	.string	"v2addsc"
.LC345:
	.string	"v2adiffs"
.LC346:
	.string	"v2avgs"
.LC347:
	.string	"v2cmpeq"
.LC348:
	.string	"v2cmpeqi"
.LC349:
	.string	"v2cmples"
.LC350:
	.string	"v2cmpleu"
.LC351:
	.string	"v2cmplts"
.LC352:
	.string	"v2cmpltsi"
.LC353:
	.string	"v2cmpltu"
.LC354:
	.string	"v2cmpltui"
.LC355:
	.string	"v2cmpne"
.LC356:
	.string	"v2dotp"
.LC357:
	.string	"v2dotpa"
.LC358:
	.string	"v2int_h"
.LC359:
	.string	"v2int_l"
.LC360:
	.string	"v2maxs"
.LC361:
	.string	"v2maxsi"
.LC362:
	.string	"v2mins"
.LC363:
	.string	"v2minsi"
.LC364:
	.string	"v2mnz"
.LC365:
	.string	"v2mulfsc"
.LC366:
	.string	"v2muls"
.LC367:
	.string	"v2mults"
.LC368:
	.string	"v2mz"
.LC369:
	.string	"v2packh"
.LC370:
	.string	"v2packl"
.LC371:
	.string	"v2packuc"
.LC372:
	.string	"v2sadas"
.LC373:
	.string	"v2sadau"
.LC374:
	.string	"v2sads"
.LC375:
	.string	"v2sadu"
.LC376:
	.string	"v2shl"
.LC377:
	.string	"v2shli"
.LC378:
	.string	"v2shlsc"
.LC379:
	.string	"v2shrs"
.LC380:
	.string	"v2shrsi"
.LC381:
	.string	"v2shru"
.LC382:
	.string	"v2shrui"
.LC383:
	.string	"v2sub"
.LC384:
	.string	"v2subsc"
.LC385:
	.string	"v4add"
.LC386:
	.string	"v4addsc"
.LC387:
	.string	"v4int_h"
.LC388:
	.string	"v4int_l"
.LC389:
	.string	"v4packsc"
.LC390:
	.string	"v4shl"
.LC391:
	.string	"v4shlsc"
.LC392:
	.string	"v4shrs"
.LC393:
	.string	"v4shru"
.LC394:
	.string	"v4sub"
.LC395:
	.string	"v4subsc"
.LC396:
	.string	"wh64"
.LC397:
	.string	"xor"
.LC398:
	.string	"xori"
	.section	.data.rel.ro.local
	.align 32
	.type	tilegx_opcodes, @object
	.size	tilegx_opcodes, 40320
tilegx_opcodes:
	.quad	.LC64
	.long	0
	.byte	2
	.byte	0
	.byte	63
	.byte	0
	.string	""
	.string	""
	.zero	2
	.string	""
	.zero	3
	.string	""
	.string	""
	.zero	2
	.string	""
	.string	""
	.zero	2
	.string	""
	.string	""
	.zero	2
	.zero	4
	.quad	0
	.quad	-2147483648
	.quad	0
	.quad	0
	.quad	0
	.quad	-1
	.quad	2912215623163445248
	.quad	-1
	.quad	-1
	.quad	-1
	.quad	.LC65
	.long	1
	.byte	15
	.byte	1
	.byte	63
	.byte	1
	.string	""
	.string	""
	.zero	2
	.string	"\001"
	.zero	2
	.string	"\002"
	.zero	2
	.string	"\003"
	.zero	2
	.string	""
	.string	""
	.zero	2
	.zero	4
	.quad	-4611686016280948737
	.quad	-2243005868146688
	.quad	2013270015
	.quad	4323464436221214720
	.quad	0
	.quad	1076891647
	.quad	1736146450296864768
	.quad	268439551
	.quad	864699922400673792
	.quad	-1
	.quad	.LC66
	.long	2
	.byte	3
	.byte	1
	.byte	63
	.byte	1
	.string	"\004"
	.zero	2
	.string	"\005"
	.zero	2
	.string	""
	.string	""
	.zero	2
	.string	""
	.string	""
	.zero	2
	.string	""
	.string	""
	.zero	2
	.zero	4
	.quad	-4611686016548335617
	.quad	-576451958357884928
	.quad	0
	.quad	0
	.quad	0
	.quad	1879052287
	.quad	4035234060069502976
	.quad	-1
	.quad	-1
	.quad	-1
	.quad	.LC67
	.long	3
	.byte	2
	.byte	3
	.byte	63
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	.align 32
	.type	decode_Y0_fsm, @object
	.size	decode_Y0_fsm, 356
decode_Y0_fsm:
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	.align 32
	.type	decode_Y1_fsm, @object
	.size	decode_Y1_fsm, 334
decode_Y1_fsm:
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	.value	30
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	.align 32
	.type	decode_Y2_fsm, @object
	.size	decode_Y2_fsm, 236
decode_Y2_fsm:
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	.value	122
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	.value	8
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	.value	126
	.value	90
	.value	381
	.value	391
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	.value	386
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	.value	124
	.value	124
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	.value	18
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	.value	126
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	.value	245
	.value	126
	.value	126
	.value	126
	.value	17
	.value	248
	.value	406
	.value	409
	.value	425
	.value	428
	.value	90
	.value	335
	.value	128
	.value	90
	.value	335
	.value	412
	.value	243
	.value	128
	.value	128
	.value	128
	.value	417
	.value	245
	.value	128
	.value	128
	.value	128
	.value	422
	.value	119
	.value	128
	.value	20
	.value	90
	.value	130
	.value	119
	.value	90
	.value	431
	.value	119
	.value	243
	.value	130
	.value	130
	.value	130
	.value	436
	.value	245
	.value	130
	.value	130
	.value	130
	.value	441
	.value	119
	.value	130
	.value	19
	.value	90
	.value	447
	.value	450
	.value	121
	.value	207
	.value	211
	.value	121
	.value	209
	.value	206
	.globl	tilegx_bundle_decoder_fsms
	.section	.data.rel.ro.local
	.align 32
	.type	tilegx_bundle_decoder_fsms, @object
	.size	tilegx_bundle_decoder_fsms, 40
tilegx_bundle_decoder_fsms:
	.quad	decode_X0_fsm
	.quad	decode_X1_fsm
	.quad	decode_Y0_fsm
	.quad	decode_Y1_fsm
	.quad	decode_Y2_fsm
	.globl	tilegx_operands
	.align 32
	.type	tilegx_operands, @object
	.size	tilegx_operands, 840
tilegx_operands:
	.long	1
	.value	23
	.byte	40
	.byte	0
	.quad	create_Imm8_X0
	.quad	get_Imm8_X0
	.long	1
	.value	25
	.byte	40
	.byte	0
	.quad	create_Imm8_X1
	.quad	get_Imm8_X1
	.long	1
	.value	24
	.byte	40
	.byte	0
	.quad	create_Imm8_Y0
	.quad	get_Imm8_Y0
	.long	1
	.value	26
	.byte	40
	.byte	0
	.quad	create_Imm8_Y1
	.quad	get_Imm8_Y1
	.long	1
	.value	44
	.byte	48
	.byte	0
	.quad	create_Imm16_X0
	.quad	get_Imm16_X0
	.long	1
	.value	45
	.byte	48
	.byte	0
	.quad	create_Imm16_X1
	.quad	get_Imm16_X1
	.long	0
	.value	0
	.byte	134
	.byte	0
	.quad	create_Dest_X1
	.quad	get_Dest_X1
	.long	0
	.value	0
	.byte	70
	.byte	0
	.quad	create_SrcA_X1
	.quad	get_SrcA_X1
	.long	0
	.value	0
	.byte	134
	.byte	0
	.quad	create_Dest_X0
	.quad	get_Dest_X0
	.long	0
	.value	0
	.byte	70
	.byte	0
	.quad	create_SrcA_X0
	.quad	get_SrcA_X0
	.long	0
	.value	0
	.byte	134
	.byte	0
	.quad	create_Dest_Y0
	.quad	get_Dest_Y0
	.long	0
	.value	0
	.byte	70
	.byte	0
	.quad	create_SrcA_Y0
	.quad	get_SrcA_Y0
	.long	0
	.value	0
	.byte	134
	.byte	0
	.quad	create_Dest_Y1
	.quad	get_Dest_Y1
	.long	0
	.value	0
	.byte	70
	.byte	0
	.quad	create_SrcA_Y1
	.quad	get_SrcA_Y1
	.long	0
	.value	0
	.byte	70
	.byte	0
	.quad	create_SrcA_Y2
	.quad	get_SrcA_Y2
	.long	0
	.value	0
	.byte	198
	.byte	0
	.quad	create_SrcA_X1
	.quad	get_SrcA_X1
	.long	0
	.value	0
	.byte	70
	.byte	0
	.quad	create_SrcB_X0
	.quad	get_SrcB_X0
	.long	0
	.value	0
	.byte	70
	.byte	0
	.quad	create_SrcB_X1
	.quad	get_SrcB_X1
	.long	0
	.value	0
	.byte	70
	.byte	0
	.quad	create_SrcB_Y0
	.quad	get_SrcB_Y0
	.long	0
	.value	0
	.byte	70
	.byte	0
	.quad	create_SrcB_Y1
	.quad	get_SrcB_Y1
	.long	2
	.value	20
	.byte	49
	.byte	7
	.quad	create_BrOff_X1
	.quad	get_BrOff_X1
	.long	1
	.value	30
	.byte	6
	.byte	0
	.quad	create_BFStart_X0
	.quad	get_BFStart_X0
	.long	1
	.value	31
	.byte	6
	.byte	0
	.quad	create_BFEnd_X0
	.quad	get_BFEnd_X0
	.long	0
	.value	0
	.byte	198
	.byte	0
	.quad	create_Dest_X0
	.quad	get_Dest_X0
	.long	0
	.value	0
	.byte	198
	.byte	0
	.quad	create_Dest_Y0
	.quad	get_Dest_Y0
	.long	2
	.value	21
	.byte	59
	.byte	7
	.quad	create_JumpOff_X1
	.quad	get_JumpOff_X1
	.long	0
	.value	0
	.byte	134
	.byte	0
	.quad	create_SrcBDest_Y2
	.quad	get_SrcBDest_Y2
	.long	3
	.value	29
	.byte	14
	.byte	0
	.quad	create_MF_Imm14_X1
	.quad	get_MF_Imm14_X1
	.long	3
	.value	28
	.byte	14
	.byte	0
	.quad	create_MT_Imm14_X1
	.quad	get_MT_Imm14_X1
	.long	1
	.value	32
	.byte	6
	.byte	0
	.quad	create_ShAmt_X0
	.quad	get_ShAmt_X0
	.long	1
	.value	33
	.byte	6
	.byte	0
	.quad	create_ShAmt_X1
	.quad	get_ShAmt_X1
	.long	1
	.value	34
	.byte	6
	.byte	0
	.quad	create_ShAmt_Y0
	.quad	get_ShAmt_Y0
	.long	1
	.value	35
	.byte	6
	.byte	0
	.quad	create_ShAmt_Y1
	.quad	get_ShAmt_Y1
	.long	0
	.value	0
	.byte	70
	.byte	0
	.quad	create_SrcBDest_Y2
	.quad	get_SrcBDest_Y2
	.long	1
	.value	27
	.byte	40
	.byte	0
	.quad	create_Dest_Imm8_X1
	.quad	get_Dest_Imm8_X1
	.text
	.globl	find_opcode
	.type	find_opcode, @function
find_opcode:
.LFB115:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -40[rbp], rdi
	mov	DWORD PTR -44[rbp], esi
	mov	eax, DWORD PTR -44[rbp]
	lea	rdx, 0[0+rax*8]
	lea	rax, tilegx_bundle_decoder_fsms[rip]
	mov	rax, QWORD PTR [rdx+rax]
	mov	QWORD PTR -8[rbp], rax
	mov	DWORD PTR -16[rbp], 0
.L128:
	mov	eax, DWORD PTR -16[rbp]
	cdqe
	lea	rdx, [rax+rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, rdx
	movzx	eax, WORD PTR [rax]
	mov	WORD PTR -20[rbp], ax
	movzx	eax, WORD PTR -20[rbp]
	and	eax, 63
	mov	rdx, QWORD PTR -40[rbp]
	mov	ecx, eax
	shr	rdx, cl
	mov	rax, rdx
	mov	edx, eax
	movzx	eax, WORD PTR -20[rbp]
	shr	ax, 6
	movzx	eax, ax
	and	eax, edx
	mov	DWORD PTR -12[rbp], eax
	mov	edx, DWORD PTR -16[rbp]
	mov	eax, DWORD PTR -12[rbp]
	add	eax, edx
	add	eax, 1
	mov	eax, eax
	lea	rdx, [rax+rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, rdx
	movzx	eax, WORD PTR [rax]
	mov	WORD PTR -18[rbp], ax
	cmp	WORD PTR -18[rbp], 335
	ja	.L126
	movzx	eax, WORD PTR -18[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 4
	sub	rax, rdx
	sal	rax, 3
	lea	rdx, tilegx_opcodes[rip]
	add	rax, rdx
	jmp	.L129
.L126:
	movzx	eax, WORD PTR -18[rbp]
	sub	eax, 335
	mov	DWORD PTR -16[rbp], eax
	jmp	.L128
.L129:
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE115:
	.size	find_opcode, .-find_opcode
	.globl	parse_insn_tilegx
	.type	parse_insn_tilegx, @function
parse_insn_tilegx:
.LFB116:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 96
	mov	QWORD PTR -72[rbp], rdi
	mov	QWORD PTR -80[rbp], rsi
	mov	QWORD PTR -88[rbp], rdx
	mov	DWORD PTR -60[rbp], 0
	movabs	rax, -4611686018427387904
	and	rax, QWORD PTR -72[rbp]
	test	rax, rax
	jne	.L131
	mov	DWORD PTR -52[rbp], 0
	mov	DWORD PTR -48[rbp], 1
	jmp	.L132
.L131:
	mov	DWORD PTR -52[rbp], 2
	mov	DWORD PTR -48[rbp], 4
.L132:
	mov	eax, DWORD PTR -52[rbp]
	mov	DWORD PTR -56[rbp], eax
	jmp	.L133
.L139:
	mov	eax, DWORD PTR -60[rbp]
	lea	edx, 1[rax]
	mov	DWORD PTR -60[rbp], edx
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 3
	add	rax, rdx
	sal	rax, 3
	mov	rdx, rax
	mov	rax, QWORD PTR -88[rbp]
	add	rax, rdx
	mov	QWORD PTR -24[rbp], rax
	mov	edx, DWORD PTR -56[rbp]
	mov	rax, QWORD PTR -72[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	find_opcode
	mov	QWORD PTR -16[rbp], rax
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR -16[rbp]
	mov	QWORD PTR [rax], rdx
	mov	DWORD PTR -44[rbp], 0
	jmp	.L134
.L138:
	mov	rcx, QWORD PTR -16[rbp]
	mov	eax, DWORD PTR -44[rbp]
	movsx	rdx, eax
	mov	eax, DWORD PTR -56[rbp]
	cdqe
	sal	rax, 2
	add	rax, rcx
	add	rax, rdx
	add	rax, 16
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	sal	rax, 3
	lea	rdx, tilegx_operands[rip]
	add	rax, rdx
	mov	QWORD PTR -8[rbp], rax
	mov	rax, QWORD PTR -8[rbp]
	mov	rdx, QWORD PTR 16[rax]
	mov	rax, QWORD PTR -72[rbp]
	mov	rdi, rax
	call	rdx
	mov	DWORD PTR -40[rbp], eax
	mov	rax, QWORD PTR -8[rbp]
	movzx	eax, BYTE PTR 6[rax]
	and	eax, 32
	test	al, al
	je	.L135
	mov	rax, QWORD PTR -8[rbp]
	movzx	eax, BYTE PTR 6[rax]
	and	eax, 31
	movzx	edx, al
	mov	eax, 32
	sub	eax, edx
	mov	DWORD PTR -36[rbp], eax
	mov	eax, DWORD PTR -36[rbp]
	mov	edx, DWORD PTR -40[rbp]
	mov	ecx, eax
	sal	edx, cl
	mov	eax, DWORD PTR -36[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	mov	DWORD PTR -40[rbp], eax
.L135:
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR [rax]
	cmp	eax, 2
	jne	.L136
	mov	eax, DWORD PTR -40[rbp]
	sal	eax, 3
	movsx	rdx, eax
	mov	rax, QWORD PTR -80[rbp]
	add	rax, rdx
	mov	QWORD PTR -32[rbp], rax
	jmp	.L137
.L136:
	mov	eax, DWORD PTR -40[rbp]
	cdqe
	mov	QWORD PTR -32[rbp], rax
.L137:
	mov	rax, QWORD PTR -24[rbp]
	mov	edx, DWORD PTR -44[rbp]
	movsx	rdx, edx
	mov	rcx, QWORD PTR -8[rbp]
	mov	QWORD PTR 8[rax+rdx*8], rcx
	mov	rax, QWORD PTR -24[rbp]
	mov	edx, DWORD PTR -44[rbp]
	movsx	rdx, edx
	lea	rcx, 4[rdx]
	mov	rdx, QWORD PTR -32[rbp]
	mov	QWORD PTR 8[rax+rcx*8], rdx
	add	DWORD PTR -44[rbp], 1
.L134:
	mov	rax, QWORD PTR -16[rbp]
	movzx	eax, BYTE PTR 13[rax]
	movzx	eax, al
	cmp	DWORD PTR -44[rbp], eax
	jl	.L138
	add	DWORD PTR -56[rbp], 1
.L133:
	mov	eax, DWORD PTR -56[rbp]
	cmp	eax, DWORD PTR -48[rbp]
	jle	.L139
	mov	eax, DWORD PTR -60[rbp]
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE116:
	.size	parse_insn_tilegx, .-parse_insn_tilegx
	.type	tilegx_spr_compare, @function
tilegx_spr_compare:
.LFB117:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	QWORD PTR -32[rbp], rsi
	mov	rax, QWORD PTR -24[rbp]
	mov	QWORD PTR -16[rbp], rax
	mov	rax, QWORD PTR -32[rbp]
	mov	QWORD PTR -8[rbp], rax
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, DWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	mov	ecx, DWORD PTR [rax]
	mov	eax, edx
	sub	eax, ecx
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE117:
	.size	tilegx_spr_compare, .-tilegx_spr_compare
	.globl	tilegx_sprs
	.section	.rodata
.LC399:
	.string	"MPL_MEM_ERROR_SET_0"
.LC400:
	.string	"MPL_MEM_ERROR_SET_1"
.LC401:
	.string	"MPL_MEM_ERROR_SET_2"
.LC402:
	.string	"MPL_MEM_ERROR_SET_3"
.LC403:
	.string	"MPL_MEM_ERROR"
.LC404:
	.string	"MEM_ERROR_CBOX_ADDR"
.LC405:
	.string	"MEM_ERROR_CBOX_STATUS"
.LC406:
	.string	"MEM_ERROR_ENABLE"
.LC407:
	.string	"MEM_ERROR_MBOX_ADDR"
.LC408:
	.string	"MEM_ERROR_MBOX_STATUS"
.LC409:
	.string	"SBOX_ERROR"
.LC410:
	.string	"XDN_DEMUX_ERROR"
.LC411:
	.string	"MPL_SINGLE_STEP_3_SET_0"
.LC412:
	.string	"MPL_SINGLE_STEP_3_SET_1"
.LC413:
	.string	"MPL_SINGLE_STEP_3_SET_2"
.LC414:
	.string	"MPL_SINGLE_STEP_3_SET_3"
.LC415:
	.string	"MPL_SINGLE_STEP_3"
.LC416:
	.string	"SINGLE_STEP_CONTROL_3"
.LC417:
	.string	"MPL_SINGLE_STEP_2_SET_0"
.LC418:
	.string	"MPL_SINGLE_STEP_2_SET_1"
.LC419:
	.string	"MPL_SINGLE_STEP_2_SET_2"
.LC420:
	.string	"MPL_SINGLE_STEP_2_SET_3"
.LC421:
	.string	"MPL_SINGLE_STEP_2"
.LC422:
	.string	"SINGLE_STEP_CONTROL_2"
.LC423:
	.string	"MPL_SINGLE_STEP_1_SET_0"
.LC424:
	.string	"MPL_SINGLE_STEP_1_SET_1"
.LC425:
	.string	"MPL_SINGLE_STEP_1_SET_2"
.LC426:
	.string	"MPL_SINGLE_STEP_1_SET_3"
.LC427:
	.string	"MPL_SINGLE_STEP_1"
.LC428:
	.string	"SINGLE_STEP_CONTROL_1"
.LC429:
	.string	"MPL_SINGLE_STEP_0_SET_0"
.LC430:
	.string	"MPL_SINGLE_STEP_0_SET_1"
.LC431:
	.string	"MPL_SINGLE_STEP_0_SET_2"
.LC432:
	.string	"MPL_SINGLE_STEP_0_SET_3"
.LC433:
	.string	"MPL_SINGLE_STEP_0"
.LC434:
	.string	"SINGLE_STEP_CONTROL_0"
.LC435:
	.string	"MPL_IDN_COMPLETE_SET_0"
.LC436:
	.string	"MPL_IDN_COMPLETE_SET_1"
.LC437:
	.string	"MPL_IDN_COMPLETE_SET_2"
.LC438:
	.string	"MPL_IDN_COMPLETE_SET_3"
.LC439:
	.string	"MPL_IDN_COMPLETE"
.LC440:
	.string	"IDN_COMPLETE_PENDING"
.LC441:
	.string	"MPL_UDN_COMPLETE_SET_0"
.LC442:
	.string	"MPL_UDN_COMPLETE_SET_1"
.LC443:
	.string	"MPL_UDN_COMPLETE_SET_2"
.LC444:
	.string	"MPL_UDN_COMPLETE_SET_3"
.LC445:
	.string	"MPL_UDN_COMPLETE"
.LC446:
	.string	"UDN_COMPLETE_PENDING"
.LC447:
	.string	"MPL_ITLB_MISS_SET_0"
.LC448:
	.string	"MPL_ITLB_MISS_SET_1"
.LC449:
	.string	"MPL_ITLB_MISS_SET_2"
.LC450:
	.string	"MPL_ITLB_MISS_SET_3"
.LC451:
	.string	"MPL_ITLB_MISS"
.LC452:
	.string	"ITLB_TSB_BASE_ADDR_0"
.LC453:
	.string	"ITLB_TSB_BASE_ADDR_1"
.LC454:
	.string	"ITLB_CURRENT_ATTR"
.LC455:
	.string	"ITLB_CURRENT_PA"
.LC456:
	.string	"ITLB_CURRENT_VA"
.LC457:
	.string	"ITLB_INDEX"
.LC458:
	.string	"ITLB_MATCH_0"
.LC459:
	.string	"ITLB_PERF"
.LC460:
	.string	"ITLB_PR"
.LC461:
	.string	"ITLB_TSB_ADDR_0"
.LC462:
	.string	"ITLB_TSB_ADDR_1"
.LC463:
	.string	"ITLB_TSB_FILL_CURRENT_ATTR"
.LC464:
	.string	"ITLB_TSB_FILL_MATCH"
.LC465:
	.string	"NUMBER_ITLB"
.LC466:
	.string	"REPLACEMENT_ITLB"
.LC467:
	.string	"WIRED_ITLB"
.LC468:
	.string	"MPL_ILL_SET_0"
.LC469:
	.string	"MPL_ILL_SET_1"
.LC470:
	.string	"MPL_ILL_SET_2"
.LC471:
	.string	"MPL_ILL_SET_3"
.LC472:
	.string	"MPL_ILL"
.LC473:
	.string	"MPL_GPV_SET_0"
.LC474:
	.string	"MPL_GPV_SET_1"
.LC475:
	.string	"MPL_GPV_SET_2"
.LC476:
	.string	"MPL_GPV_SET_3"
.LC477:
	.string	"MPL_GPV"
.LC478:
	.string	"GPV_REASON"
.LC479:
	.string	"MPL_IDN_ACCESS_SET_0"
.LC480:
	.string	"MPL_IDN_ACCESS_SET_1"
.LC481:
	.string	"MPL_IDN_ACCESS_SET_2"
.LC482:
	.string	"MPL_IDN_ACCESS_SET_3"
.LC483:
	.string	"MPL_IDN_ACCESS"
.LC484:
	.string	"IDN_DEMUX_COUNT_0"
.LC485:
	.string	"IDN_DEMUX_COUNT_1"
.LC486:
	.string	"IDN_FLUSH_EGRESS"
.LC487:
	.string	"IDN_PENDING"
.LC488:
	.string	"IDN_ROUTE_ORDER"
.LC489:
	.string	"IDN_SP_FIFO_CNT"
.LC490:
	.string	"IDN_DATA_AVAIL"
.LC491:
	.string	"MPL_UDN_ACCESS_SET_0"
.LC492:
	.string	"MPL_UDN_ACCESS_SET_1"
.LC493:
	.string	"MPL_UDN_ACCESS_SET_2"
.LC494:
	.string	"MPL_UDN_ACCESS_SET_3"
.LC495:
	.string	"MPL_UDN_ACCESS"
.LC496:
	.string	"UDN_DEMUX_COUNT_0"
.LC497:
	.string	"UDN_DEMUX_COUNT_1"
.LC498:
	.string	"UDN_DEMUX_COUNT_2"
.LC499:
	.string	"UDN_DEMUX_COUNT_3"
.LC500:
	.string	"UDN_FLUSH_EGRESS"
.LC501:
	.string	"UDN_PENDING"
.LC502:
	.string	"UDN_ROUTE_ORDER"
.LC503:
	.string	"UDN_SP_FIFO_CNT"
.LC504:
	.string	"UDN_DATA_AVAIL"
.LC505:
	.string	"MPL_SWINT_3_SET_0"
.LC506:
	.string	"MPL_SWINT_3_SET_1"
.LC507:
	.string	"MPL_SWINT_3_SET_2"
.LC508:
	.string	"MPL_SWINT_3_SET_3"
.LC509:
	.string	"MPL_SWINT_3"
.LC510:
	.string	"MPL_SWINT_2_SET_0"
.LC511:
	.string	"MPL_SWINT_2_SET_1"
.LC512:
	.string	"MPL_SWINT_2_SET_2"
.LC513:
	.string	"MPL_SWINT_2_SET_3"
.LC514:
	.string	"MPL_SWINT_2"
.LC515:
	.string	"MPL_SWINT_1_SET_0"
.LC516:
	.string	"MPL_SWINT_1_SET_1"
.LC517:
	.string	"MPL_SWINT_1_SET_2"
.LC518:
	.string	"MPL_SWINT_1_SET_3"
.LC519:
	.string	"MPL_SWINT_1"
.LC520:
	.string	"MPL_SWINT_0_SET_0"
.LC521:
	.string	"MPL_SWINT_0_SET_1"
.LC522:
	.string	"MPL_SWINT_0_SET_2"
.LC523:
	.string	"MPL_SWINT_0_SET_3"
.LC524:
	.string	"MPL_SWINT_0"
.LC525:
	.string	"MPL_ILL_TRANS_SET_0"
.LC526:
	.string	"MPL_ILL_TRANS_SET_1"
.LC527:
	.string	"MPL_ILL_TRANS_SET_2"
.LC528:
	.string	"MPL_ILL_TRANS_SET_3"
.LC529:
	.string	"MPL_ILL_TRANS"
.LC530:
	.string	"ILL_TRANS_REASON"
.LC531:
	.string	"ILL_VA_PC"
.LC532:
	.string	"MPL_UNALIGN_DATA_SET_0"
.LC533:
	.string	"MPL_UNALIGN_DATA_SET_1"
.LC534:
	.string	"MPL_UNALIGN_DATA_SET_2"
.LC535:
	.string	"MPL_UNALIGN_DATA_SET_3"
.LC536:
	.string	"MPL_UNALIGN_DATA"
.LC537:
	.string	"MPL_DTLB_MISS_SET_0"
.LC538:
	.string	"MPL_DTLB_MISS_SET_1"
.LC539:
	.string	"MPL_DTLB_MISS_SET_2"
.LC540:
	.string	"MPL_DTLB_MISS_SET_3"
.LC541:
	.string	"MPL_DTLB_MISS"
.LC542:
	.string	"DTLB_TSB_BASE_ADDR_0"
.LC543:
	.string	"DTLB_TSB_BASE_ADDR_1"
.LC544:
	.string	"AAR"
.LC545:
	.string	"CACHE_PINNED_WAYS"
.LC546:
	.string	"DTLB_BAD_ADDR"
.LC547:
	.string	"DTLB_BAD_ADDR_REASON"
.LC548:
	.string	"DTLB_CURRENT_ATTR"
.LC549:
	.string	"DTLB_CURRENT_PA"
.LC550:
	.string	"DTLB_CURRENT_VA"
.LC551:
	.string	"DTLB_INDEX"
.LC552:
	.string	"DTLB_MATCH_0"
.LC553:
	.string	"DTLB_PERF"
.LC554:
	.string	"DTLB_TSB_ADDR_0"
.LC555:
	.string	"DTLB_TSB_ADDR_1"
.LC556:
	.string	"DTLB_TSB_FILL_CURRENT_ATTR"
.LC557:
	.string	"DTLB_TSB_FILL_MATCH"
.LC558:
	.string	"NUMBER_DTLB"
.LC559:
	.string	"REPLACEMENT_DTLB"
.LC560:
	.string	"WIRED_DTLB"
.LC561:
	.string	"MPL_DTLB_ACCESS_SET_0"
.LC562:
	.string	"MPL_DTLB_ACCESS_SET_1"
.LC563:
	.string	"MPL_DTLB_ACCESS_SET_2"
.LC564:
	.string	"MPL_DTLB_ACCESS_SET_3"
.LC565:
	.string	"MPL_DTLB_ACCESS"
.LC566:
	.string	"MPL_IDN_FIREWALL_SET_0"
.LC567:
	.string	"MPL_IDN_FIREWALL_SET_1"
.LC568:
	.string	"MPL_IDN_FIREWALL_SET_2"
.LC569:
	.string	"MPL_IDN_FIREWALL_SET_3"
.LC570:
	.string	"MPL_IDN_FIREWALL"
.LC571:
	.string	"IDN_DIRECTION_PROTECT"
.LC572:
	.string	"MPL_UDN_FIREWALL_SET_0"
.LC573:
	.string	"MPL_UDN_FIREWALL_SET_1"
.LC574:
	.string	"MPL_UDN_FIREWALL_SET_2"
.LC575:
	.string	"MPL_UDN_FIREWALL_SET_3"
.LC576:
	.string	"MPL_UDN_FIREWALL"
.LC577:
	.string	"UDN_DIRECTION_PROTECT"
.LC578:
	.string	"MPL_TILE_TIMER_SET_0"
.LC579:
	.string	"MPL_TILE_TIMER_SET_1"
.LC580:
	.string	"MPL_TILE_TIMER_SET_2"
.LC581:
	.string	"MPL_TILE_TIMER_SET_3"
.LC582:
	.string	"MPL_TILE_TIMER"
.LC583:
	.string	"TILE_TIMER_CONTROL"
.LC584:
	.string	"MPL_AUX_TILE_TIMER_SET_0"
.LC585:
	.string	"MPL_AUX_TILE_TIMER_SET_1"
.LC586:
	.string	"MPL_AUX_TILE_TIMER_SET_2"
.LC587:
	.string	"MPL_AUX_TILE_TIMER_SET_3"
.LC588:
	.string	"MPL_AUX_TILE_TIMER"
.LC589:
	.string	"AUX_TILE_TIMER_CONTROL"
.LC590:
	.string	"MPL_IDN_TIMER_SET_0"
.LC591:
	.string	"MPL_IDN_TIMER_SET_1"
.LC592:
	.string	"MPL_IDN_TIMER_SET_2"
.LC593:
	.string	"MPL_IDN_TIMER_SET_3"
.LC594:
	.string	"MPL_IDN_TIMER"
.LC595:
	.string	"IDN_DEADLOCK_COUNT"
.LC596:
	.string	"IDN_DEADLOCK_TIMEOUT"
.LC597:
	.string	"MPL_UDN_TIMER_SET_0"
.LC598:
	.string	"MPL_UDN_TIMER_SET_1"
.LC599:
	.string	"MPL_UDN_TIMER_SET_2"
.LC600:
	.string	"MPL_UDN_TIMER_SET_3"
.LC601:
	.string	"MPL_UDN_TIMER"
.LC602:
	.string	"UDN_DEADLOCK_COUNT"
.LC603:
	.string	"UDN_DEADLOCK_TIMEOUT"
.LC604:
	.string	"MPL_IDN_AVAIL_SET_0"
.LC605:
	.string	"MPL_IDN_AVAIL_SET_1"
.LC606:
	.string	"MPL_IDN_AVAIL_SET_2"
.LC607:
	.string	"MPL_IDN_AVAIL_SET_3"
.LC608:
	.string	"MPL_IDN_AVAIL"
.LC609:
	.string	"IDN_AVAIL_EN"
.LC610:
	.string	"MPL_UDN_AVAIL_SET_0"
.LC611:
	.string	"MPL_UDN_AVAIL_SET_1"
.LC612:
	.string	"MPL_UDN_AVAIL_SET_2"
.LC613:
	.string	"MPL_UDN_AVAIL_SET_3"
.LC614:
	.string	"MPL_UDN_AVAIL"
.LC615:
	.string	"UDN_AVAIL_EN"
.LC616:
	.string	"MPL_IPI_3_SET_0"
.LC617:
	.string	"MPL_IPI_3_SET_1"
.LC618:
	.string	"MPL_IPI_3_SET_2"
.LC619:
	.string	"MPL_IPI_3_SET_3"
.LC620:
	.string	"MPL_IPI_3"
.LC621:
	.string	"IPI_EVENT_3"
.LC622:
	.string	"IPI_EVENT_RESET_3"
.LC623:
	.string	"IPI_EVENT_SET_3"
.LC624:
	.string	"IPI_MASK_3"
.LC625:
	.string	"IPI_MASK_RESET_3"
.LC626:
	.string	"IPI_MASK_SET_3"
.LC627:
	.string	"MPL_IPI_2_SET_0"
.LC628:
	.string	"MPL_IPI_2_SET_1"
.LC629:
	.string	"MPL_IPI_2_SET_2"
.LC630:
	.string	"MPL_IPI_2_SET_3"
.LC631:
	.string	"MPL_IPI_2"
.LC632:
	.string	"IPI_EVENT_2"
.LC633:
	.string	"IPI_EVENT_RESET_2"
.LC634:
	.string	"IPI_EVENT_SET_2"
.LC635:
	.string	"IPI_MASK_2"
.LC636:
	.string	"IPI_MASK_RESET_2"
.LC637:
	.string	"IPI_MASK_SET_2"
.LC638:
	.string	"MPL_IPI_1_SET_0"
.LC639:
	.string	"MPL_IPI_1_SET_1"
.LC640:
	.string	"MPL_IPI_1_SET_2"
.LC641:
	.string	"MPL_IPI_1_SET_3"
.LC642:
	.string	"MPL_IPI_1"
.LC643:
	.string	"IPI_EVENT_1"
.LC644:
	.string	"IPI_EVENT_RESET_1"
.LC645:
	.string	"IPI_EVENT_SET_1"
.LC646:
	.string	"IPI_MASK_1"
.LC647:
	.string	"IPI_MASK_RESET_1"
.LC648:
	.string	"IPI_MASK_SET_1"
.LC649:
	.string	"MPL_IPI_0_SET_0"
.LC650:
	.string	"MPL_IPI_0_SET_1"
.LC651:
	.string	"MPL_IPI_0_SET_2"
.LC652:
	.string	"MPL_IPI_0_SET_3"
.LC653:
	.string	"MPL_IPI_0"
.LC654:
	.string	"IPI_EVENT_0"
.LC655:
	.string	"IPI_EVENT_RESET_0"
.LC656:
	.string	"IPI_EVENT_SET_0"
.LC657:
	.string	"IPI_MASK_0"
.LC658:
	.string	"IPI_MASK_RESET_0"
.LC659:
	.string	"IPI_MASK_SET_0"
.LC660:
	.string	"MPL_PERF_COUNT_SET_0"
.LC661:
	.string	"MPL_PERF_COUNT_SET_1"
.LC662:
	.string	"MPL_PERF_COUNT_SET_2"
.LC663:
	.string	"MPL_PERF_COUNT_SET_3"
.LC664:
	.string	"MPL_PERF_COUNT"
.LC665:
	.string	"PERF_COUNT_0"
.LC666:
	.string	"PERF_COUNT_1"
.LC667:
	.string	"PERF_COUNT_CTL"
.LC668:
	.string	"PERF_COUNT_DN_CTL"
.LC669:
	.string	"PERF_COUNT_STS"
.LC670:
	.string	"WATCH_MASK"
.LC671:
	.string	"WATCH_VAL"
.LC672:
	.string	"MPL_AUX_PERF_COUNT_SET_0"
.LC673:
	.string	"MPL_AUX_PERF_COUNT_SET_1"
.LC674:
	.string	"MPL_AUX_PERF_COUNT_SET_2"
.LC675:
	.string	"MPL_AUX_PERF_COUNT_SET_3"
.LC676:
	.string	"MPL_AUX_PERF_COUNT"
.LC677:
	.string	"AUX_PERF_COUNT_0"
.LC678:
	.string	"AUX_PERF_COUNT_1"
.LC679:
	.string	"AUX_PERF_COUNT_CTL"
.LC680:
	.string	"AUX_PERF_COUNT_STS"
.LC681:
	.string	"MPL_INTCTRL_3_SET_0"
.LC682:
	.string	"MPL_INTCTRL_3_SET_1"
.LC683:
	.string	"MPL_INTCTRL_3_SET_2"
.LC684:
	.string	"MPL_INTCTRL_3_SET_3"
.LC685:
	.string	"MPL_INTCTRL_3"
.LC686:
	.string	"INTCTRL_3_STATUS"
.LC687:
	.string	"INTERRUPT_MASK_3"
.LC688:
	.string	"INTERRUPT_MASK_RESET_3"
.LC689:
	.string	"INTERRUPT_MASK_SET_3"
.LC690:
	.string	"INTERRUPT_VECTOR_BASE_3"
.LC691:
	.string	"SINGLE_STEP_EN_0_3"
.LC692:
	.string	"SINGLE_STEP_EN_1_3"
.LC693:
	.string	"SINGLE_STEP_EN_2_3"
.LC694:
	.string	"SINGLE_STEP_EN_3_3"
.LC695:
	.string	"EX_CONTEXT_3_0"
.LC696:
	.string	"EX_CONTEXT_3_1"
.LC697:
	.string	"SYSTEM_SAVE_3_0"
.LC698:
	.string	"SYSTEM_SAVE_3_1"
.LC699:
	.string	"SYSTEM_SAVE_3_2"
.LC700:
	.string	"SYSTEM_SAVE_3_3"
.LC701:
	.string	"MPL_INTCTRL_2_SET_0"
.LC702:
	.string	"MPL_INTCTRL_2_SET_1"
.LC703:
	.string	"MPL_INTCTRL_2_SET_2"
.LC704:
	.string	"MPL_INTCTRL_2_SET_3"
.LC705:
	.string	"MPL_INTCTRL_2"
.LC706:
	.string	"INTCTRL_2_STATUS"
.LC707:
	.string	"INTERRUPT_MASK_2"
.LC708:
	.string	"INTERRUPT_MASK_RESET_2"
.LC709:
	.string	"INTERRUPT_MASK_SET_2"
.LC710:
	.string	"INTERRUPT_VECTOR_BASE_2"
.LC711:
	.string	"SINGLE_STEP_EN_0_2"
.LC712:
	.string	"SINGLE_STEP_EN_1_2"
.LC713:
	.string	"SINGLE_STEP_EN_2_2"
.LC714:
	.string	"SINGLE_STEP_EN_3_2"
.LC715:
	.string	"EX_CONTEXT_2_0"
.LC716:
	.string	"EX_CONTEXT_2_1"
.LC717:
	.string	"SYSTEM_SAVE_2_0"
.LC718:
	.string	"SYSTEM_SAVE_2_1"
.LC719:
	.string	"SYSTEM_SAVE_2_2"
.LC720:
	.string	"SYSTEM_SAVE_2_3"
.LC721:
	.string	"MPL_INTCTRL_1_SET_0"
.LC722:
	.string	"MPL_INTCTRL_1_SET_1"
.LC723:
	.string	"MPL_INTCTRL_1_SET_2"
.LC724:
	.string	"MPL_INTCTRL_1_SET_3"
.LC725:
	.string	"MPL_INTCTRL_1"
.LC726:
	.string	"INTCTRL_1_STATUS"
.LC727:
	.string	"INTERRUPT_MASK_1"
.LC728:
	.string	"INTERRUPT_MASK_RESET_1"
.LC729:
	.string	"INTERRUPT_MASK_SET_1"
.LC730:
	.string	"INTERRUPT_VECTOR_BASE_1"
.LC731:
	.string	"SINGLE_STEP_EN_0_1"
.LC732:
	.string	"SINGLE_STEP_EN_1_1"
.LC733:
	.string	"SINGLE_STEP_EN_2_1"
.LC734:
	.string	"SINGLE_STEP_EN_3_1"
.LC735:
	.string	"EX_CONTEXT_1_0"
.LC736:
	.string	"EX_CONTEXT_1_1"
.LC737:
	.string	"SYSTEM_SAVE_1_0"
.LC738:
	.string	"SYSTEM_SAVE_1_1"
.LC739:
	.string	"SYSTEM_SAVE_1_2"
.LC740:
	.string	"SYSTEM_SAVE_1_3"
.LC741:
	.string	"MPL_INTCTRL_0_SET_0"
.LC742:
	.string	"MPL_INTCTRL_0_SET_1"
.LC743:
	.string	"MPL_INTCTRL_0_SET_2"
.LC744:
	.string	"MPL_INTCTRL_0_SET_3"
.LC745:
	.string	"MPL_INTCTRL_0"
.LC746:
	.string	"INTCTRL_0_STATUS"
.LC747:
	.string	"INTERRUPT_MASK_0"
.LC748:
	.string	"INTERRUPT_MASK_RESET_0"
.LC749:
	.string	"INTERRUPT_MASK_SET_0"
.LC750:
	.string	"INTERRUPT_VECTOR_BASE_0"
.LC751:
	.string	"SINGLE_STEP_EN_0_0"
.LC752:
	.string	"SINGLE_STEP_EN_1_0"
.LC753:
	.string	"SINGLE_STEP_EN_2_0"
.LC754:
	.string	"SINGLE_STEP_EN_3_0"
.LC755:
	.string	"EX_CONTEXT_0_0"
.LC756:
	.string	"EX_CONTEXT_0_1"
.LC757:
	.string	"SYSTEM_SAVE_0_0"
.LC758:
	.string	"SYSTEM_SAVE_0_1"
.LC759:
	.string	"SYSTEM_SAVE_0_2"
.LC760:
	.string	"SYSTEM_SAVE_0_3"
.LC761:
	.string	"MPL_BOOT_ACCESS_SET_0"
.LC762:
	.string	"MPL_BOOT_ACCESS_SET_1"
.LC763:
	.string	"MPL_BOOT_ACCESS_SET_2"
.LC764:
	.string	"MPL_BOOT_ACCESS_SET_3"
.LC765:
	.string	"MPL_BOOT_ACCESS"
.LC766:
	.string	"BIG_ENDIAN_CONFIG"
	.align 8
.LC767:
	.string	"CACHE_INVALIDATION_COMPRESSION_MODE"
.LC768:
	.string	"CACHE_INVALIDATION_MASK_0"
.LC769:
	.string	"CACHE_INVALIDATION_MASK_1"
.LC770:
	.string	"CACHE_INVALIDATION_MASK_2"
.LC771:
	.string	"CBOX_CACHEASRAM_CONFIG"
.LC772:
	.string	"CBOX_CACHE_CONFIG"
.LC773:
	.string	"CBOX_HOME_MAP_ADDR"
.LC774:
	.string	"CBOX_HOME_MAP_DATA"
.LC775:
	.string	"CBOX_MMAP_0"
.LC776:
	.string	"CBOX_MMAP_1"
.LC777:
	.string	"CBOX_MMAP_2"
.LC778:
	.string	"CBOX_MMAP_3"
.LC779:
	.string	"CBOX_MSR"
.LC780:
	.string	"DIAG_BCST_CTL"
.LC781:
	.string	"DIAG_BCST_MASK"
.LC782:
	.string	"DIAG_BCST_TRIGGER"
.LC783:
	.string	"DIAG_MUX_CTL"
.LC784:
	.string	"DIAG_TRACE_CTL"
.LC785:
	.string	"DIAG_TRACE_DATA"
.LC786:
	.string	"DIAG_TRACE_STS"
.LC787:
	.string	"IDN_DEMUX_BUF_THRESH"
.LC788:
	.string	"L1_I_PIN_WAY_0"
.LC789:
	.string	"MEM_ROUTE_ORDER"
.LC790:
	.string	"MEM_STRIPE_CONFIG"
.LC791:
	.string	"PERF_COUNT_PLS"
.LC792:
	.string	"PSEUDO_RANDOM_NUMBER_MODIFY"
.LC793:
	.string	"QUIESCE_CTL"
.LC794:
	.string	"RSHIM_COORD"
.LC795:
	.string	"SBOX_CONFIG"
.LC796:
	.string	"UDN_DEMUX_BUF_THRESH"
.LC797:
	.string	"XDN_CORE_STARVATION_COUNT"
.LC798:
	.string	"XDN_ROUND_ROBIN_ARB_CTL"
.LC799:
	.string	"CYCLE_MODIFY"
.LC800:
	.string	"I_AAR"
.LC801:
	.string	"MPL_WORLD_ACCESS_SET_0"
.LC802:
	.string	"MPL_WORLD_ACCESS_SET_1"
.LC803:
	.string	"MPL_WORLD_ACCESS_SET_2"
.LC804:
	.string	"MPL_WORLD_ACCESS_SET_3"
.LC805:
	.string	"MPL_WORLD_ACCESS"
.LC806:
	.string	"DONE"
.LC807:
	.string	"DSTREAM_PF"
.LC808:
	.string	"FAIL"
.LC809:
	.string	"INTERRUPT_CRITICAL_SECTION"
.LC810:
	.string	"PASS"
.LC811:
	.string	"PSEUDO_RANDOM_NUMBER"
.LC812:
	.string	"TILE_COORD"
.LC813:
	.string	"TILE_RTF_HWM"
.LC814:
	.string	"CMPEXCH_VALUE"
.LC815:
	.string	"CYCLE"
.LC816:
	.string	"EVENT_BEGIN"
.LC817:
	.string	"EVENT_END"
.LC818:
	.string	"PROC_STATUS"
.LC819:
	.string	"SIM_CONTROL"
.LC820:
	.string	"SIM_SOCKET"
.LC821:
	.string	"STATUS_SATURATE"
.LC822:
	.string	"MPL_I_ASID_SET_0"
.LC823:
	.string	"MPL_I_ASID_SET_1"
.LC824:
	.string	"MPL_I_ASID_SET_2"
.LC825:
	.string	"MPL_I_ASID_SET_3"
.LC826:
	.string	"MPL_I_ASID"
.LC827:
	.string	"I_ASID"
.LC828:
	.string	"MPL_D_ASID_SET_0"
.LC829:
	.string	"MPL_D_ASID_SET_1"
.LC830:
	.string	"MPL_D_ASID_SET_2"
.LC831:
	.string	"MPL_D_ASID_SET_3"
.LC832:
	.string	"MPL_D_ASID"
.LC833:
	.string	"D_ASID"
.LC834:
	.string	"MPL_DOUBLE_FAULT_SET_0"
.LC835:
	.string	"MPL_DOUBLE_FAULT_SET_1"
.LC836:
	.string	"MPL_DOUBLE_FAULT_SET_2"
.LC837:
	.string	"MPL_DOUBLE_FAULT_SET_3"
.LC838:
	.string	"MPL_DOUBLE_FAULT"
.LC839:
	.string	"LAST_INTERRUPT_REASON"
	.section	.data.rel.ro.local
	.align 32
	.type	tilegx_sprs, @object
	.size	tilegx_sprs, 7056
tilegx_sprs:
	.long	0
	.zero	4
	.quad	.LC399
	.long	1
	.zero	4
	.quad	.LC400
	.long	2
	.zero	4
	.quad	.LC401
	.long	3
	.zero	4
	.quad	.LC402
	.long	4
	.zero	4
	.quad	.LC403
	.long	5
	.zero	4
	.quad	.LC404
	.long	6
	.zero	4
	.quad	.LC405
	.long	7
	.zero	4
	.quad	.LC406
	.long	8
	.zero	4
	.quad	.LC407
	.long	9
	.zero	4
	.quad	.LC408
	.long	10
	.zero	4
	.quad	.LC409
	.long	11
	.zero	4
	.quad	.LC410
	.long	256
	.zero	4
	.quad	.LC411
	.long	257
	.zero	4
	.quad	.LC412
	.long	258
	.zero	4
	.quad	.LC413
	.long	259
	.zero	4
	.quad	.LC414
	.long	260
	.zero	4
	.quad	.LC415
	.long	261
	.zero	4
	.quad	.LC416
	.long	512
	.zero	4
	.quad	.LC417
	.long	513
	.zero	4
	.quad	.LC418
	.long	514
	.zero	4
	.quad	.LC419
	.long	515
	.zero	4
	.quad	.LC420
	.long	516
	.zero	4
	.quad	.LC421
	.long	517
	.zero	4
	.quad	.LC422
	.long	768
	.zero	4
	.quad	.LC423
	.long	769
	.zero	4
	.quad	.LC424
	.long	770
	.zero	4
	.quad	.LC425
	.long	771
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	.quad	.LC426
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	.quad	.LC427
	.long	773
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	.quad	.LC428
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	.quad	.LC429
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	.quad	.LC430
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	.quad	.LC431
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	.quad	.LC432
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	.quad	.LC433
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	.quad	.LC434
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	.quad	.LC435
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	.quad	.LC436
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	.quad	.LC437
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	.quad	.LC438
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	.quad	.LC439
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	.quad	.LC440
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	.quad	.LC441
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	.quad	.LC442
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	.quad	.LC443
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	.quad	.LC444
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	.quad	.LC445
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	.quad	.LC446
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	.quad	.LC447
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	.quad	.LC448
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	.quad	.LC449
	.long	1795
	.zero	4
	.quad	.LC450
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	.zero	4
	.quad	.LC451
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	.quad	.LC452
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	.quad	.LC453
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	.quad	.LC454
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	.zero	4
	.quad	.LC455
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	.zero	4
	.quad	.LC456
	.long	1923
	.zero	4
	.quad	.LC457
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	.zero	4
	.quad	.LC458
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	.zero	4
	.quad	.LC459
	.long	1926
	.zero	4
	.quad	.LC460
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	.zero	4
	.quad	.LC461
	.long	1928
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	.quad	.LC462
	.long	1929
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	.quad	.LC463
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	.quad	.LC464
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	.quad	.LC465
	.long	1932
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	.quad	.LC466
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	.quad	.LC467
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	.quad	.LC468
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	.quad	.LC469
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	.quad	.LC470
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	.quad	.LC471
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	.zero	4
	.quad	.LC472
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	.zero	4
	.quad	.LC473
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	.quad	.LC474
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	.quad	.LC475
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	.quad	.LC476
	.long	2308
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	.quad	.LC477
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	.quad	.LC478
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	.quad	.LC479
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	.quad	.LC480
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	.zero	4
	.quad	.LC481
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	.quad	.LC482
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	.quad	.LC483
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	.quad	.LC484
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	.quad	.LC485
	.long	2567
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	.quad	.LC486
	.long	2568
	.zero	4
	.quad	.LC487
	.long	2569
	.zero	4
	.quad	.LC488
	.long	2570
	.zero	4
	.quad	.LC489
	.long	2688
	.zero	4
	.quad	.LC490
	.long	2816
	.zero	4
	.quad	.LC491
	.long	2817
	.zero	4
	.quad	.LC492
	.long	2818
	.zero	4
	.quad	.LC493
	.long	2819
	.zero	4
	.quad	.LC494
	.long	2820
	.zero	4
	.quad	.LC495
	.long	2821
	.zero	4
	.quad	.LC496
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	.zero	4
	.quad	.LC497
	.long	2823
	.zero	4
	.quad	.LC498
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	.quad	.LC499
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	.zero	4
	.quad	.LC500
	.long	2826
	.zero	4
	.quad	.LC501
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	.zero	4
	.quad	.LC502
	.long	2828
	.zero	4
	.quad	.LC503
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	.zero	4
	.quad	.LC504
	.long	3072
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	.quad	.LC505
	.long	3073
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	.quad	.LC506
	.long	3074
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	.quad	.LC507
	.long	3075
	.zero	4
	.quad	.LC508
	.long	3076
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	.quad	.LC509
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	.quad	.LC510
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	.quad	.LC511
	.long	3330
	.zero	4
	.quad	.LC512
	.long	3331
	.zero	4
	.quad	.LC513
	.long	3332
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	.quad	.LC514
	.long	3584
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	.quad	.LC515
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	.zero	4
	.quad	.LC516
	.long	3586
	.zero	4
	.quad	.LC517
	.long	3587
	.zero	4
	.quad	.LC518
	.long	3588
	.zero	4
	.quad	.LC519
	.long	3840
	.zero	4
	.quad	.LC520
	.long	3841
	.zero	4
	.quad	.LC521
	.long	3842
	.zero	4
	.quad	.LC522
	.long	3843
	.zero	4
	.quad	.LC523
	.long	3844
	.zero	4
	.quad	.LC524
	.long	4096
	.zero	4
	.quad	.LC525
	.long	4097
	.zero	4
	.quad	.LC526
	.long	4098
	.zero	4
	.quad	.LC527
	.long	4099
	.zero	4
	.quad	.LC528
	.long	4100
	.zero	4
	.quad	.LC529
	.long	4101
	.zero	4
	.quad	.LC530
	.long	4102
	.zero	4
	.quad	.LC531
	.long	4352
	.zero	4
	.quad	.LC532
	.long	4353
	.zero	4
	.quad	.LC533
	.long	4354
	.zero	4
	.quad	.LC534
	.long	4355
	.zero	4
	.quad	.LC535
	.long	4356
	.zero	4
	.quad	.LC536
	.long	4608
	.zero	4
	.quad	.LC537
	.long	4609
	.zero	4
	.quad	.LC538
	.long	4610
	.zero	4
	.quad	.LC539
	.long	4611
	.zero	4
	.quad	.LC540
	.long	4612
	.zero	4
	.quad	.LC541
	.long	4613
	.zero	4
	.quad	.LC542
	.long	4614
	.zero	4
	.quad	.LC543
	.long	4736
	.zero	4
	.quad	.LC544
	.long	4737
	.zero	4
	.quad	.LC545
	.long	4738
	.zero	4
	.quad	.LC546
	.long	4739
	.zero	4
	.quad	.LC547
	.long	4740
	.zero	4
	.quad	.LC548
	.long	4741
	.zero	4
	.quad	.LC549
	.long	4742
	.zero	4
	.quad	.LC550
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	.zero	4
	.quad	.LC551
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	.zero	4
	.quad	.LC552
	.long	4745
	.zero	4
	.quad	.LC553
	.long	4746
	.zero	4
	.quad	.LC554
	.long	4747
	.zero	4
	.quad	.LC555
	.long	4748
	.zero	4
	.quad	.LC556
	.long	4749
	.zero	4
	.quad	.LC557
	.long	4750
	.zero	4
	.quad	.LC558
	.long	4751
	.zero	4
	.quad	.LC559
	.long	4752
	.zero	4
	.quad	.LC560
	.long	4864
	.zero	4
	.quad	.LC561
	.long	4865
	.zero	4
	.quad	.LC562
	.long	4866
	.zero	4
	.quad	.LC563
	.long	4867
	.zero	4
	.quad	.LC564
	.long	4868
	.zero	4
	.quad	.LC565
	.long	5120
	.zero	4
	.quad	.LC566
	.long	5121
	.zero	4
	.quad	.LC567
	.long	5122
	.zero	4
	.quad	.LC568
	.long	5123
	.zero	4
	.quad	.LC569
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	.zero	4
	.quad	.LC570
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	.zero	4
	.quad	.LC571
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	.zero	4
	.quad	.LC572
	.long	5377
	.zero	4
	.quad	.LC573
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	.zero	4
	.quad	.LC574
	.long	5379
	.zero	4
	.quad	.LC575
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	.zero	4
	.quad	.LC576
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	.zero	4
	.quad	.LC577
	.long	5632
	.zero	4
	.quad	.LC578
	.long	5633
	.zero	4
	.quad	.LC579
	.long	5634
	.zero	4
	.quad	.LC580
	.long	5635
	.zero	4
	.quad	.LC581
	.long	5636
	.zero	4
	.quad	.LC582
	.long	5637
	.zero	4
	.quad	.LC583
	.long	5888
	.zero	4
	.quad	.LC584
	.long	5889
	.zero	4
	.quad	.LC585
	.long	5890
	.zero	4
	.quad	.LC586
	.long	5891
	.zero	4
	.quad	.LC587
	.long	5892
	.zero	4
	.quad	.LC588
	.long	5893
	.zero	4
	.quad	.LC589
	.long	6144
	.zero	4
	.quad	.LC590
	.long	6145
	.zero	4
	.quad	.LC591
	.long	6146
	.zero	4
	.quad	.LC592
	.long	6147
	.zero	4
	.quad	.LC593
	.long	6148
	.zero	4
	.quad	.LC594
	.long	6149
	.zero	4
	.quad	.LC595
	.long	6150
	.zero	4
	.quad	.LC596
	.long	6400
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	.quad	.LC597
	.long	6401
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	.quad	.LC598
	.long	6402
	.zero	4
	.quad	.LC599
	.long	6403
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	.quad	.LC600
	.long	6404
	.zero	4
	.quad	.LC601
	.long	6405
	.zero	4
	.quad	.LC602
	.long	6406
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	.quad	.LC603
	.long	6656
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	.quad	.LC604
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	.quad	.LC605
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	.zero	4
	.quad	.LC606
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	.zero	4
	.quad	.LC607
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	.quad	.LC608
	.long	6661
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	.quad	.LC609
	.long	6912
	.zero	4
	.quad	.LC610
	.long	6913
	.zero	4
	.quad	.LC611
	.long	6914
	.zero	4
	.quad	.LC612
	.long	6915
	.zero	4
	.quad	.LC613
	.long	6916
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	.quad	.LC614
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	.quad	.LC615
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	.quad	.LC616
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	.quad	.LC617
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	.quad	.LC618
	.long	7171
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	.quad	.LC619
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	.quad	.LC620
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	.zero	4
	.quad	.LC621
	.long	7174
	.zero	4
	.quad	.LC622
	.long	7175
	.zero	4
	.quad	.LC623
	.long	7176
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	.quad	.LC624
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	.quad	.LC625
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	.quad	.LC626
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	.quad	.LC627
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	.quad	.LC628
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	.quad	.LC629
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	.quad	.LC630
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	.quad	.LC631
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	.quad	.LC632
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	.quad	.LC633
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	.quad	.LC634
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	.quad	.LC635
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	.quad	.LC636
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	.quad	.LC637
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	.quad	.LC638
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	.quad	.LC639
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	.quad	.LC640
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	.quad	.LC641
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	.quad	.LC642
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	.quad	.LC643
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	.quad	.LC644
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	.quad	.LC645
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	.quad	.LC646
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	.quad	.LC647
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	.quad	.LC648
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	.quad	.LC649
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	.quad	.LC650
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	.quad	.LC651
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	.quad	.LC652
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	.quad	.LC653
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	.quad	.LC654
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	.quad	.LC655
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	.quad	.LC656
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	.quad	.LC657
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	.quad	.LC658
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	.quad	.LC659
	.long	8192
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	.quad	.LC660
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	.quad	.LC661
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	.quad	.LC662
	.long	8195
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	.quad	.LC663
	.long	8196
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	.quad	.LC664
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	.quad	.LC665
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	.quad	.LC666
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	.quad	.LC667
	.long	8200
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	.quad	.LC668
	.long	8201
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	.quad	.LC669
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	.quad	.LC670
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	.quad	.LC671
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	.quad	.LC672
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	.quad	.LC673
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	.quad	.LC674
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	.quad	.LC675
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	.quad	.LC676
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	.quad	.LC677
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	.quad	.LC678
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	.quad	.LC679
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	.quad	.LC680
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	.quad	.LC681
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	.quad	.LC682
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	.quad	.LC683
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	.quad	.LC684
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	.quad	.LC685
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	.quad	.LC686
	.long	8710
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	.quad	.LC687
	.long	8711
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	.quad	.LC688
	.long	8712
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	.quad	.LC689
	.long	8713
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	.quad	.LC690
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	.quad	.LC691
	.long	8715
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	.quad	.LC692
	.long	8716
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	.quad	.LC693
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	.quad	.LC694
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	.quad	.LC695
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	.quad	.LC696
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	.quad	.LC697
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	.quad	.LC698
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	.quad	.LC699
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	.quad	.LC700
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	.quad	.LC701
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	.quad	.LC702
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	.quad	.LC703
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	.quad	.LC704
	.long	8964
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	.quad	.LC705
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	.quad	.LC706
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	.quad	.LC707
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	.quad	.LC708
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	.quad	.LC709
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	.quad	.LC710
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	.quad	.LC711
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	.quad	.LC712
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	.quad	.LC713
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	.quad	.LC714
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	.quad	.LC715
	.long	9089
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	.quad	.LC716
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	.quad	.LC717
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	.quad	.LC718
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	.quad	.LC719
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	.quad	.LC720
	.long	9216
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	.quad	.LC721
	.long	9217
	.zero	4
	.quad	.LC722
	.long	9218
	.zero	4
	.quad	.LC723
	.long	9219
	.zero	4
	.quad	.LC724
	.long	9220
	.zero	4
	.quad	.LC725
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	.zero	4
	.quad	.LC726
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	.quad	.LC727
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	.zero	4
	.quad	.LC728
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	.zero	4
	.quad	.LC729
	.long	9225
	.zero	4
	.quad	.LC730
	.long	9226
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	.quad	.LC731
	.long	9227
	.zero	4
	.quad	.LC732
	.long	9228
	.zero	4
	.quad	.LC733
	.long	9229
	.zero	4
	.quad	.LC734
	.long	9344
	.zero	4
	.quad	.LC735
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	.zero	4
	.quad	.LC736
	.long	9346
	.zero	4
	.quad	.LC737
	.long	9347
	.zero	4
	.quad	.LC738
	.long	9348
	.zero	4
	.quad	.LC739
	.long	9349
	.zero	4
	.quad	.LC740
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	.quad	.LC741
	.long	9473
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	.quad	.LC742
	.long	9474
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	.quad	.LC743
	.long	9475
	.zero	4
	.quad	.LC744
	.long	9476
	.zero	4
	.quad	.LC745
	.long	9477
	.zero	4
	.quad	.LC746
	.long	9478
	.zero	4
	.quad	.LC747
	.long	9479
	.zero	4
	.quad	.LC748
	.long	9480
	.zero	4
	.quad	.LC749
	.long	9481
	.zero	4
	.quad	.LC750
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	.zero	4
	.quad	.LC751
	.long	9483
	.zero	4
	.quad	.LC752
	.long	9484
	.zero	4
	.quad	.LC753
	.long	9485
	.zero	4
	.quad	.LC754
	.long	9600
	.zero	4
	.quad	.LC755
	.long	9601
	.zero	4
	.quad	.LC756
	.long	9602
	.zero	4
	.quad	.LC757
	.long	9603
	.zero	4
	.quad	.LC758
	.long	9604
	.zero	4
	.quad	.LC759
	.long	9605
	.zero	4
	.quad	.LC760
	.long	9728
	.zero	4
	.quad	.LC761
	.long	9729
	.zero	4
	.quad	.LC762
	.long	9730
	.zero	4
	.quad	.LC763
	.long	9731
	.zero	4
	.quad	.LC764
	.long	9732
	.zero	4
	.quad	.LC765
	.long	9733
	.zero	4
	.quad	.LC766
	.long	9734
	.zero	4
	.quad	.LC767
	.long	9735
	.zero	4
	.quad	.LC768
	.long	9736
	.zero	4
	.quad	.LC769
	.long	9737
	.zero	4
	.quad	.LC770
	.long	9738
	.zero	4
	.quad	.LC771
	.long	9739
	.zero	4
	.quad	.LC772
	.long	9740
	.zero	4
	.quad	.LC773
	.long	9741
	.zero	4
	.quad	.LC774
	.long	9742
	.zero	4
	.quad	.LC775
	.long	9743
	.zero	4
	.quad	.LC776
	.long	9744
	.zero	4
	.quad	.LC777
	.long	9745
	.zero	4
	.quad	.LC778
	.long	9746
	.zero	4
	.quad	.LC779
	.long	9747
	.zero	4
	.quad	.LC780
	.long	9748
	.zero	4
	.quad	.LC781
	.long	9749
	.zero	4
	.quad	.LC782
	.long	9750
	.zero	4
	.quad	.LC783
	.long	9751
	.zero	4
	.quad	.LC784
	.long	9752
	.zero	4
	.quad	.LC785
	.long	9753
	.zero	4
	.quad	.LC786
	.long	9754
	.zero	4
	.quad	.LC787
	.long	9755
	.zero	4
	.quad	.LC788
	.long	9756
	.zero	4
	.quad	.LC789
	.long	9757
	.zero	4
	.quad	.LC790
	.long	9758
	.zero	4
	.quad	.LC791
	.long	9759
	.zero	4
	.quad	.LC792
	.long	9760
	.zero	4
	.quad	.LC793
	.long	9761
	.zero	4
	.quad	.LC794
	.long	9762
	.zero	4
	.quad	.LC795
	.long	9763
	.zero	4
	.quad	.LC796
	.long	9764
	.zero	4
	.quad	.LC797
	.long	9765
	.zero	4
	.quad	.LC798
	.long	9856
	.zero	4
	.quad	.LC799
	.long	9857
	.zero	4
	.quad	.LC800
	.long	9984
	.zero	4
	.quad	.LC801
	.long	9985
	.zero	4
	.quad	.LC802
	.long	9986
	.zero	4
	.quad	.LC803
	.long	9987
	.zero	4
	.quad	.LC804
	.long	9988
	.zero	4
	.quad	.LC805
	.long	9989
	.zero	4
	.quad	.LC806
	.long	9990
	.zero	4
	.quad	.LC807
	.long	9991
	.zero	4
	.quad	.LC808
	.long	9992
	.zero	4
	.quad	.LC809
	.long	9993
	.zero	4
	.quad	.LC810
	.long	9994
	.zero	4
	.quad	.LC811
	.long	9995
	.zero	4
	.quad	.LC812
	.long	9996
	.zero	4
	.quad	.LC813
	.long	10112
	.zero	4
	.quad	.LC814
	.long	10113
	.zero	4
	.quad	.LC815
	.long	10114
	.zero	4
	.quad	.LC816
	.long	10115
	.zero	4
	.quad	.LC817
	.long	10116
	.zero	4
	.quad	.LC818
	.long	10117
	.zero	4
	.quad	.LC819
	.long	10118
	.zero	4
	.quad	.LC820
	.long	10119
	.zero	4
	.quad	.LC821
	.long	10240
	.zero	4
	.quad	.LC822
	.long	10241
	.zero	4
	.quad	.LC823
	.long	10242
	.zero	4
	.quad	.LC824
	.long	10243
	.zero	4
	.quad	.LC825
	.long	10244
	.zero	4
	.quad	.LC826
	.long	10245
	.zero	4
	.quad	.LC827
	.long	10496
	.zero	4
	.quad	.LC828
	.long	10497
	.zero	4
	.quad	.LC829
	.long	10498
	.zero	4
	.quad	.LC830
	.long	10499
	.zero	4
	.quad	.LC831
	.long	10500
	.zero	4
	.quad	.LC832
	.long	10501
	.zero	4
	.quad	.LC833
	.long	10752
	.zero	4
	.quad	.LC834
	.long	10753
	.zero	4
	.quad	.LC835
	.long	10754
	.zero	4
	.quad	.LC836
	.long	10755
	.zero	4
	.quad	.LC837
	.long	10756
	.zero	4
	.quad	.LC838
	.long	10757
	.zero	4
	.quad	.LC839
	.globl	tilegx_num_sprs
	.section	.rodata
	.align 4
	.type	tilegx_num_sprs, @object
	.size	tilegx_num_sprs, 4
tilegx_num_sprs:
	.long	441
	.text
	.globl	get_tilegx_spr_name
	.type	get_tilegx_spr_name, @function
get_tilegx_spr_name:
.LFB118:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 64
	mov	DWORD PTR -52[rbp], edi
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -8[rbp], rax
	xor	eax, eax
	mov	eax, DWORD PTR -52[rbp]
	mov	DWORD PTR -32[rbp], eax
	mov	eax, 441
	movsx	rdx, eax
	lea	rax, -32[rbp]
	lea	r8, tilegx_spr_compare[rip]
	mov	ecx, 16
	lea	rsi, tilegx_sprs[rip]
	mov	rdi, rax
	call	bsearch@PLT
	mov	QWORD PTR -48[rbp], rax
	cmp	QWORD PTR -48[rbp], 0
	jne	.L144
	mov	eax, 0
	jmp	.L146
.L144:
	mov	rax, QWORD PTR -48[rbp]
	mov	QWORD PTR -40[rbp], rax
	mov	rax, QWORD PTR -40[rbp]
	mov	rax, QWORD PTR 8[rax]
.L146:
	mov	rcx, QWORD PTR -8[rbp]
	sub	rcx, QWORD PTR fs:40
	je	.L147
	call	__stack_chk_fail@PLT
.L147:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE118:
	.size	get_tilegx_spr_name, .-get_tilegx_spr_name
	.section	.rodata
.LC840:
	.string	"{ "
.LC841:
	.string	" ; "
.LC842:
	.string	"<invalid>"
.LC843:
	.string	"%s"
.LC844:
	.string	"%d"
.LC845:
	.string	"0x%016llx"
.LC846:
	.string	" }"
	.text
	.globl	print_insn_tilegx
	.type	print_insn_tilegx, @function
print_insn_tilegx:
.LFB119:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 320
	mov	QWORD PTR -312[rbp], rdi
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -8[rbp], rax
	xor	eax, eax
	mov	rax, QWORD PTR -312[rbp]
	mov	rax, QWORD PTR [rax]
	mov	QWORD PTR -16[rbp], rax
	mov	rcx, QWORD PTR -312[rbp]
	lea	rax, -16[rbp]
	mov	rax, QWORD PTR [rax]
	lea	rdx, -240[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	parse_insn_tilegx
	mov	DWORD PTR -284[rbp], eax
	lea	rdi, .LC840[rip]
	mov	eax, 0
	call	printf@PLT
	mov	DWORD PTR -296[rbp], 0
	mov	DWORD PTR -292[rbp], 101
	mov	DWORD PTR -300[rbp], 0
	jmp	.L149
.L152:
	mov	eax, DWORD PTR -300[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 3
	add	rax, rdx
	sal	rax, 3
	add	rax, rbp
	sub	rax, 240
	mov	rax, QWORD PTR [rax]
	movzx	eax, BYTE PTR 15[rax]
	test	al, al
	jne	.L150
	mov	DWORD PTR -292[rbp], 179
	jmp	.L151
.L150:
	add	DWORD PTR -300[rbp], 1
.L149:
	mov	eax, DWORD PTR -300[rbp]
	cmp	eax, DWORD PTR -284[rbp]
	jl	.L152
.L151:
	mov	DWORD PTR -300[rbp], 0
	jmp	.L153
.L170:
	mov	eax, DWORD PTR -300[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 3
	add	rax, rdx
	sal	rax, 3
	add	rax, rbp
	sub	rax, 240
	mov	rax, QWORD PTR [rax]
	mov	QWORD PTR -272[rbp], rax
	mov	rax, QWORD PTR -272[rbp]
	mov	eax, DWORD PTR 8[rax]
	cmp	DWORD PTR -292[rbp], eax
	jne	.L154
	cmp	DWORD PTR -296[rbp], 0
	jg	.L173
	mov	eax, DWORD PTR -300[rbp]
	add	eax, 1
	cmp	DWORD PTR -284[rbp], eax
	jg	.L173
.L154:
	cmp	DWORD PTR -296[rbp], 0
	jle	.L157
	lea	rdi, .LC841[rip]
	mov	eax, 0
	call	printf@PLT
.L157:
	add	DWORD PTR -296[rbp], 1
	mov	rax, QWORD PTR -272[rbp]
	mov	rax, QWORD PTR [rax]
	mov	QWORD PTR -280[rbp], rax
	cmp	QWORD PTR -280[rbp], 0
	jne	.L158
	lea	rax, .LC842[rip]
	mov	QWORD PTR -280[rbp], rax
.L158:
	mov	rax, QWORD PTR -280[rbp]
	mov	rsi, rax
	lea	rdi, .LC843[rip]
	mov	eax, 0
	call	printf@PLT
	mov	DWORD PTR -288[rbp], 0
	jmp	.L159
.L169:
	cmp	DWORD PTR -288[rbp], 0
	jle	.L160
	mov	edi, 44
	call	putchar@PLT
.L160:
	mov	edi, 32
	call	putchar@PLT
	mov	eax, DWORD PTR -288[rbp]
	movsx	rcx, eax
	mov	eax, DWORD PTR -300[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 3
	add	rax, rdx
	add	rax, rcx
	add	rax, 4
	mov	rax, QWORD PTR -232[rbp+rax*8]
	mov	QWORD PTR -264[rbp], rax
	mov	eax, DWORD PTR -288[rbp]
	movsx	rcx, eax
	mov	eax, DWORD PTR -300[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 3
	add	rax, rdx
	add	rax, rcx
	mov	rax, QWORD PTR -232[rbp+rax*8]
	mov	QWORD PTR -256[rbp], rax
	mov	rax, QWORD PTR -256[rbp]
	mov	eax, DWORD PTR [rax]
	cmp	eax, 3
	je	.L161
	cmp	eax, 3
	ja	.L162
	cmp	eax, 2
	je	.L163
	cmp	eax, 2
	ja	.L162
	test	eax, eax
	je	.L164
	cmp	eax, 1
	je	.L165
	jmp	.L162
.L164:
	mov	rax, QWORD PTR -264[rbp]
	cdqe
	lea	rdx, 0[0+rax*8]
	lea	rax, tilegx_register_names[rip]
	mov	rax, QWORD PTR [rdx+rax]
	mov	rsi, rax
	lea	rdi, .LC843[rip]
	mov	eax, 0
	call	printf@PLT
	jmp	.L166
.L161:
	mov	rax, QWORD PTR -264[rbp]
	mov	edi, eax
	call	get_tilegx_spr_name
	mov	QWORD PTR -248[rbp], rax
	cmp	QWORD PTR -248[rbp], 0
	je	.L167
	mov	rax, QWORD PTR -248[rbp]
	mov	rsi, rax
	lea	rdi, .LC843[rip]
	mov	eax, 0
	call	printf@PLT
	jmp	.L166
.L167:
	mov	rax, QWORD PTR -264[rbp]
	mov	esi, eax
	lea	rdi, .LC844[rip]
	mov	eax, 0
	call	printf@PLT
	jmp	.L166
.L165:
	mov	rax, QWORD PTR -264[rbp]
	mov	esi, eax
	lea	rdi, .LC844[rip]
	mov	eax, 0
	call	printf@PLT
	jmp	.L166
.L163:
	mov	rax, QWORD PTR -264[rbp]
	mov	rsi, rax
	lea	rdi, .LC845[rip]
	mov	eax, 0
	call	printf@PLT
	jmp	.L166
.L162:
	call	abort@PLT
.L166:
	add	DWORD PTR -288[rbp], 1
.L159:
	mov	rax, QWORD PTR -272[rbp]
	movzx	eax, BYTE PTR 13[rax]
	movzx	eax, al
	cmp	DWORD PTR -288[rbp], eax
	jl	.L169
	jmp	.L156
.L173:
	nop
.L156:
	add	DWORD PTR -300[rbp], 1
.L153:
	mov	eax, DWORD PTR -300[rbp]
	cmp	eax, DWORD PTR -284[rbp]
	jl	.L170
	lea	rdi, .LC846[rip]
	call	puts@PLT
	mov	eax, 8
	mov	rcx, QWORD PTR -8[rbp]
	sub	rcx, QWORD PTR fs:40
	je	.L172
	call	__stack_chk_fail@PLT
.L172:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE119:
	.size	print_insn_tilegx, .-print_insn_tilegx
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"336590.c"
	.text
	.global	tilegx_register_names
	.section	.rodata
	.align	2
.LC0:
	.ascii	"r0\000"
	.align	2
.LC1:
	.ascii	"r1\000"
	.align	2
.LC2:
	.ascii	"r2\000"
	.align	2
.LC3:
	.ascii	"r3\000"
	.align	2
.LC4:
	.ascii	"r4\000"
	.align	2
.LC5:
	.ascii	"r5\000"
	.align	2
.LC6:
	.ascii	"r6\000"
	.align	2
.LC7:
	.ascii	"r7\000"
	.align	2
.LC8:
	.ascii	"r8\000"
	.align	2
.LC9:
	.ascii	"r9\000"
	.align	2
.LC10:
	.ascii	"r10\000"
	.align	2
.LC11:
	.ascii	"r11\000"
	.align	2
.LC12:
	.ascii	"r12\000"
	.align	2
.LC13:
	.ascii	"r13\000"
	.align	2
.LC14:
	.ascii	"r14\000"
	.align	2
.LC15:
	.ascii	"r15\000"
	.align	2
.LC16:
	.ascii	"r16\000"
	.align	2
.LC17:
	.ascii	"r17\000"
	.align	2
.LC18:
	.ascii	"r18\000"
	.align	2
.LC19:
	.ascii	"r19\000"
	.align	2
.LC20:
	.ascii	"r20\000"
	.align	2
.LC21:
	.ascii	"r21\000"
	.align	2
.LC22:
	.ascii	"r22\000"
	.align	2
.LC23:
	.ascii	"r23\000"
	.align	2
.LC24:
	.ascii	"r24\000"
	.align	2
.LC25:
	.ascii	"r25\000"
	.align	2
.LC26:
	.ascii	"r26\000"
	.align	2
.LC27:
	.ascii	"r27\000"
	.align	2
.LC28:
	.ascii	"r28\000"
	.align	2
.LC29:
	.ascii	"r29\000"
	.align	2
.LC30:
	.ascii	"r30\000"
	.align	2
.LC31:
	.ascii	"r31\000"
	.align	2
.LC32:
	.ascii	"r32\000"
	.align	2
.LC33:
	.ascii	"r33\000"
	.align	2
.LC34:
	.ascii	"r34\000"
	.align	2
.LC35:
	.ascii	"r35\000"
	.align	2
.LC36:
	.ascii	"r36\000"
	.align	2
.LC37:
	.ascii	"r37\000"
	.align	2
.LC38:
	.ascii	"r38\000"
	.align	2
.LC39:
	.ascii	"r39\000"
	.align	2
.LC40:
	.ascii	"r40\000"
	.align	2
.LC41:
	.ascii	"r41\000"
	.align	2
.LC42:
	.ascii	"r42\000"
	.align	2
.LC43:
	.ascii	"r43\000"
	.align	2
.LC44:
	.ascii	"r44\000"
	.align	2
.LC45:
	.ascii	"r45\000"
	.align	2
.LC46:
	.ascii	"r46\000"
	.align	2
.LC47:
	.ascii	"r47\000"
	.align	2
.LC48:
	.ascii	"r48\000"
	.align	2
.LC49:
	.ascii	"r49\000"
	.align	2
.LC50:
	.ascii	"r50\000"
	.align	2
.LC51:
	.ascii	"r51\000"
	.align	2
.LC52:
	.ascii	"r52\000"
	.align	2
.LC53:
	.ascii	"tp\000"
	.align	2
.LC54:
	.ascii	"sp\000"
	.align	2
.LC55:
	.ascii	"lr\000"
	.align	2
.LC56:
	.ascii	"sn\000"
	.align	2
.LC57:
	.ascii	"idn0\000"
	.align	2
.LC58:
	.ascii	"idn1\000"
	.align	2
.LC59:
	.ascii	"udn0\000"
	.align	2
.LC60:
	.ascii	"udn1\000"
	.align	2
.LC61:
	.ascii	"udn2\000"
	.align	2
.LC62:
	.ascii	"udn3\000"
	.align	2
.LC63:
	.ascii	"zero\000"
	.align	2
	.type	tilegx_register_names, %object
	.size	tilegx_register_names, 256
tilegx_register_names:
	.word	.LC0
	.word	.LC1
	.word	.LC2
	.word	.LC3
	.word	.LC4
	.word	.LC5
	.word	.LC6
	.word	.LC7
	.word	.LC8
	.word	.LC9
	.word	.LC10
	.word	.LC11
	.word	.LC12
	.word	.LC13
	.word	.LC14
	.word	.LC15
	.word	.LC16
	.word	.LC17
	.word	.LC18
	.word	.LC19
	.word	.LC20
	.word	.LC21
	.word	.LC22
	.word	.LC23
	.word	.LC24
	.word	.LC25
	.word	.LC26
	.word	.LC27
	.word	.LC28
	.word	.LC29
	.word	.LC30
	.word	.LC31
	.word	.LC32
	.word	.LC33
	.word	.LC34
	.word	.LC35
	.word	.LC36
	.word	.LC37
	.word	.LC38
	.word	.LC39
	.word	.LC40
	.word	.LC41
	.word	.LC42
	.word	.LC43
	.word	.LC44
	.word	.LC45
	.word	.LC46
	.word	.LC47
	.word	.LC48
	.word	.LC49
	.word	.LC50
	.word	.LC51
	.word	.LC52
	.word	.LC53
	.word	.LC54
	.word	.LC55
	.word	.LC56
	.word	.LC57
	.word	.LC58
	.word	.LC59
	.word	.LC60
	.word	.LC61
	.word	.LC62
	.word	.LC63
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_BFEnd_X0, %function
get_BFEnd_X0:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-20]
	str	r1, [fp, #-16]
	ldr	r3, [fp, #-20]
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	lsr	r3, r3, #12
	and	r3, r3, #63
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_BFEnd_X0, .-get_BFEnd_X0
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_BFStart_X0, %function
get_BFStart_X0:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-20]
	str	r1, [fp, #-16]
	ldr	r3, [fp, #-20]
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	lsr	r3, r3, #18
	and	r3, r3, #63
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_BFStart_X0, .-get_BFStart_X0
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_BrOff_X1, %function
get_BrOff_X1:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-12]
	str	r1, [fp, #-8]
	sub	r1, fp, #12
	ldmia	r1, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #31
	orr	r2, r2, r1, lsl #1
	lsr	r3, r1, #31
	mov	r3, r2
	and	ip, r3, #63
	sub	r1, fp, #12
	ldmia	r1, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r1, #5
	mov	r3, #0
	ldr	r3, .L7
	and	r3, r3, r2
	orr	r3, ip, r3
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
.L8:
	.align	2
.L7:
	.word	131008
	.size	get_BrOff_X1, .-get_BrOff_X1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_Dest_Imm8_X1, %function
get_Dest_Imm8_X1:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-12]
	str	r1, [fp, #-8]
	sub	r1, fp, #12
	ldmia	r1, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #31
	orr	r2, r2, r1, lsl #1
	lsr	r3, r1, #31
	mov	r3, r2
	and	ip, r3, #63
	sub	r1, fp, #12
	ldmia	r1, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r1, #11
	mov	r3, #0
	mov	r3, r2
	and	r3, r3, #192
	orr	r3, ip, r3
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_Dest_Imm8_X1, .-get_Dest_Imm8_X1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_Dest_X0, %function
get_Dest_X0:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-20]
	str	r1, [fp, #-16]
	ldr	r3, [fp, #-20]
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	and	r3, r3, #63
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_Dest_X0, .-get_Dest_X0
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_Dest_X1, %function
get_Dest_X1:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-12]
	str	r1, [fp, #-8]
	sub	r1, fp, #12
	ldmia	r1, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #31
	orr	r2, r2, r1, lsl #1
	lsr	r3, r1, #31
	mov	r3, r2
	and	r3, r3, #63
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_Dest_X1, .-get_Dest_X1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_Dest_Y0, %function
get_Dest_Y0:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-20]
	str	r1, [fp, #-16]
	ldr	r3, [fp, #-20]
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	and	r3, r3, #63
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_Dest_Y0, .-get_Dest_Y0
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_Dest_Y1, %function
get_Dest_Y1:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-12]
	str	r1, [fp, #-8]
	sub	r1, fp, #12
	ldmia	r1, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #31
	orr	r2, r2, r1, lsl #1
	lsr	r3, r1, #31
	mov	r3, r2
	and	r3, r3, #63
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_Dest_Y1, .-get_Dest_Y1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_Imm16_X0, %function
get_Imm16_X0:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-20]
	str	r1, [fp, #-16]
	ldr	r3, [fp, #-20]
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	lsr	r3, r3, #12
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_Imm16_X0, .-get_Imm16_X0
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_Imm16_X1, %function
get_Imm16_X1:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-12]
	str	r1, [fp, #-8]
	sub	r1, fp, #12
	ldmia	r1, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r1, #11
	mov	r3, #0
	mov	r3, r2
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_Imm16_X1, .-get_Imm16_X1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_Imm8_X0, %function
get_Imm8_X0:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-20]
	str	r1, [fp, #-16]
	ldr	r3, [fp, #-20]
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	lsr	r3, r3, #12
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_Imm8_X0, .-get_Imm8_X0
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_Imm8_X1, %function
get_Imm8_X1:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-12]
	str	r1, [fp, #-8]
	sub	r1, fp, #12
	ldmia	r1, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r1, #11
	mov	r3, #0
	mov	r3, r2
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_Imm8_X1, .-get_Imm8_X1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_Imm8_Y0, %function
get_Imm8_Y0:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-20]
	str	r1, [fp, #-16]
	ldr	r3, [fp, #-20]
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	lsr	r3, r3, #12
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_Imm8_Y0, .-get_Imm8_Y0
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_Imm8_Y1, %function
get_Imm8_Y1:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-12]
	str	r1, [fp, #-8]
	sub	r1, fp, #12
	ldmia	r1, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r1, #11
	mov	r3, #0
	mov	r3, r2
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_Imm8_Y1, .-get_Imm8_Y1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_JumpOff_X1, %function
get_JumpOff_X1:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-12]
	str	r1, [fp, #-8]
	sub	r1, fp, #12
	ldmia	r1, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #31
	orr	r2, r2, r1, lsl #1
	lsr	r3, r1, #31
	mov	r3, r2
	bic	r3, r3, #-134217728
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_JumpOff_X1, .-get_JumpOff_X1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_MF_Imm14_X1, %function
get_MF_Imm14_X1:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-12]
	str	r1, [fp, #-8]
	sub	r1, fp, #12
	ldmia	r1, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r1, #5
	mov	r3, #0
	mov	r3, r2
	lsl	r3, r3, #18
	lsr	r3, r3, #18
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_MF_Imm14_X1, .-get_MF_Imm14_X1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_MT_Imm14_X1, %function
get_MT_Imm14_X1:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-12]
	str	r1, [fp, #-8]
	sub	r1, fp, #12
	ldmia	r1, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #31
	orr	r2, r2, r1, lsl #1
	lsr	r3, r1, #31
	mov	r3, r2
	and	ip, r3, #63
	sub	r1, fp, #12
	ldmia	r1, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r1, #5
	mov	r3, #0
	mov	r3, r2
	and	r3, r3, #16320
	orr	r3, ip, r3
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_MT_Imm14_X1, .-get_MT_Imm14_X1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_ShAmt_X0, %function
get_ShAmt_X0:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-20]
	str	r1, [fp, #-16]
	ldr	r3, [fp, #-20]
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	lsr	r3, r3, #12
	and	r3, r3, #63
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_ShAmt_X0, .-get_ShAmt_X0
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_ShAmt_X1, %function
get_ShAmt_X1:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-12]
	str	r1, [fp, #-8]
	sub	r1, fp, #12
	ldmia	r1, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r1, #11
	mov	r3, #0
	mov	r3, r2
	and	r3, r3, #63
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_ShAmt_X1, .-get_ShAmt_X1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_ShAmt_Y0, %function
get_ShAmt_Y0:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-20]
	str	r1, [fp, #-16]
	ldr	r3, [fp, #-20]
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	lsr	r3, r3, #12
	and	r3, r3, #63
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_ShAmt_Y0, .-get_ShAmt_Y0
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_ShAmt_Y1, %function
get_ShAmt_Y1:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-12]
	str	r1, [fp, #-8]
	sub	r1, fp, #12
	ldmia	r1, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r1, #11
	mov	r3, #0
	mov	r3, r2
	and	r3, r3, #63
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_ShAmt_Y1, .-get_ShAmt_Y1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_SrcA_X0, %function
get_SrcA_X0:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-20]
	str	r1, [fp, #-16]
	ldr	r3, [fp, #-20]
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	lsr	r3, r3, #6
	and	r3, r3, #63
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_SrcA_X0, .-get_SrcA_X0
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_SrcA_X1, %function
get_SrcA_X1:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-12]
	str	r1, [fp, #-8]
	sub	r1, fp, #12
	ldmia	r1, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r1, #5
	mov	r3, #0
	mov	r3, r2
	and	r3, r3, #63
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_SrcA_X1, .-get_SrcA_X1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_SrcA_Y0, %function
get_SrcA_Y0:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-20]
	str	r1, [fp, #-16]
	ldr	r3, [fp, #-20]
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	lsr	r3, r3, #6
	and	r3, r3, #63
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_SrcA_Y0, .-get_SrcA_Y0
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_SrcA_Y1, %function
get_SrcA_Y1:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-12]
	str	r1, [fp, #-8]
	sub	r1, fp, #12
	ldmia	r1, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r1, #5
	mov	r3, #0
	mov	r3, r2
	and	r3, r3, #63
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_SrcA_Y1, .-get_SrcA_Y1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_SrcA_Y2, %function
get_SrcA_Y2:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-20]
	str	r1, [fp, #-16]
	ldr	r3, [fp, #-20]
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	lsr	r3, r3, #20
	and	r3, r3, #63
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_SrcA_Y2, .-get_SrcA_Y2
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_SrcBDest_Y2, %function
get_SrcBDest_Y2:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-12]
	str	r1, [fp, #-8]
	sub	r1, fp, #12
	ldmia	r1, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r1, #19
	mov	r3, #0
	mov	r3, r2
	and	r3, r3, #63
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_SrcBDest_Y2, .-get_SrcBDest_Y2
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_SrcB_X0, %function
get_SrcB_X0:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-20]
	str	r1, [fp, #-16]
	ldr	r3, [fp, #-20]
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	lsr	r3, r3, #12
	and	r3, r3, #63
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_SrcB_X0, .-get_SrcB_X0
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_SrcB_X1, %function
get_SrcB_X1:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-12]
	str	r1, [fp, #-8]
	sub	r1, fp, #12
	ldmia	r1, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r1, #11
	mov	r3, #0
	mov	r3, r2
	and	r3, r3, #63
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_SrcB_X1, .-get_SrcB_X1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_SrcB_Y0, %function
get_SrcB_Y0:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-20]
	str	r1, [fp, #-16]
	ldr	r3, [fp, #-20]
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	lsr	r3, r3, #12
	and	r3, r3, #63
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_SrcB_Y0, .-get_SrcB_Y0
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_SrcB_Y1, %function
get_SrcB_Y1:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-12]
	str	r1, [fp, #-8]
	sub	r1, fp, #12
	ldmia	r1, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r1, #11
	mov	r3, #0
	mov	r3, r2
	and	r3, r3, #63
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	get_SrcB_Y1, .-get_SrcB_Y1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_BFEnd_X0, %function
create_BFEnd_X0:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #20
	str	r0, [fp, #-24]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #12
	mov	r2, r3
	mov	r3, #0
	mov	r0, #258048
	mov	r1, #0
	and	r4, r2, r0
	and	r5, r3, r1
	mov	r2, r4
	mov	r3, r5
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
	.size	create_BFEnd_X0, .-create_BFEnd_X0
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_BFStart_X0, %function
create_BFStart_X0:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #20
	str	r0, [fp, #-24]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #18
	mov	r2, r3
	mov	r3, #0
	mov	r0, #16515072
	mov	r1, #0
	and	r4, r2, r0
	and	r5, r3, r1
	mov	r2, r4
	mov	r3, r5
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
	.size	create_BFStart_X0, .-create_BFStart_X0
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_BrOff_X1, %function
create_BrOff_X1:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, r6, r7, r8, r9, fp}
	add	fp, sp, #24
	sub	sp, sp, #20
	str	r0, [fp, #-40]
	ldr	r1, [fp, #-40]
	str	r1, [fp, #-32]
	ldr	r1, [fp, #-32]
	mov	r0, r1
	mov	r1, #0
	lsr	r7, r0, #1
	lsl	r6, r0, #31
	mov	r0, #-2147483648
	mov	r1, #31
	and	r4, r6, r0
	and	r5, r7, r1
	ldr	r1, [fp, #-32]
	mov	r6, r1
	mov	r7, #0
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r6, #5
	mov	r0, #0
	mov	r6, #0
	ldr	r7, .L71
	and	r2, r0, r6
	and	r3, r1, r7
	orr	r8, r4, r2
	orr	r9, r5, r3
	mov	r2, r8
	mov	r3, r9
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #24
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, fp}
	bx	lr
.L72:
	.align	2
.L71:
	.word	4192256
	.size	create_BrOff_X1, .-create_BrOff_X1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_Dest_Imm8_X1, %function
create_Dest_Imm8_X1:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, r6, r7, r8, r9, fp}
	add	fp, sp, #24
	sub	sp, sp, #20
	str	r0, [fp, #-40]
	ldr	r1, [fp, #-40]
	str	r1, [fp, #-32]
	ldr	r1, [fp, #-32]
	mov	r0, r1
	mov	r1, #0
	lsr	r7, r0, #1
	lsl	r6, r0, #31
	mov	r0, #-2147483648
	mov	r1, #31
	and	r4, r6, r0
	and	r5, r7, r1
	ldr	r1, [fp, #-32]
	mov	r6, r1
	mov	r7, #0
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r6, #11
	mov	r0, #0
	mov	r6, #0
	mov	r7, #393216
	and	r2, r0, r6
	and	r3, r1, r7
	orr	r8, r4, r2
	orr	r9, r5, r3
	mov	r2, r8
	mov	r3, r9
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #24
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, fp}
	bx	lr
	.size	create_Dest_Imm8_X1, .-create_Dest_Imm8_X1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_Dest_X0, %function
create_Dest_X0:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #20
	str	r0, [fp, #-24]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	mov	r2, r3
	mov	r3, #0
	mov	r0, #63
	mov	r1, #0
	and	r4, r2, r0
	and	r5, r3, r1
	mov	r2, r4
	mov	r3, r5
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
	.size	create_Dest_X0, .-create_Dest_X0
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_Dest_X1, %function
create_Dest_X1:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #20
	str	r0, [fp, #-24]
	ldr	r1, [fp, #-24]
	str	r1, [fp, #-16]
	ldr	r1, [fp, #-16]
	mov	r0, r1
	mov	r1, #0
	lsr	r3, r0, #1
	lsl	r2, r0, #31
	mov	r0, #-2147483648
	mov	r1, #31
	and	r4, r2, r0
	and	r5, r3, r1
	mov	r2, r4
	mov	r3, r5
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
	.size	create_Dest_X1, .-create_Dest_X1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_Dest_Y0, %function
create_Dest_Y0:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #20
	str	r0, [fp, #-24]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	mov	r2, r3
	mov	r3, #0
	mov	r0, #63
	mov	r1, #0
	and	r4, r2, r0
	and	r5, r3, r1
	mov	r2, r4
	mov	r3, r5
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
	.size	create_Dest_Y0, .-create_Dest_Y0
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_Dest_Y1, %function
create_Dest_Y1:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #20
	str	r0, [fp, #-24]
	ldr	r1, [fp, #-24]
	str	r1, [fp, #-16]
	ldr	r1, [fp, #-16]
	mov	r0, r1
	mov	r1, #0
	lsr	r3, r0, #1
	lsl	r2, r0, #31
	mov	r0, #-2147483648
	mov	r1, #31
	and	r4, r2, r0
	and	r5, r3, r1
	mov	r2, r4
	mov	r3, r5
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
	.size	create_Dest_Y1, .-create_Dest_Y1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_Imm16_X0, %function
create_Imm16_X0:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #20
	str	r0, [fp, #-24]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #12
	mov	r2, r3
	mov	r3, #0
	ldr	r0, .L85
	mov	r1, #0
	and	r4, r2, r0
	and	r5, r3, r1
	mov	r2, r4
	mov	r3, r5
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
.L86:
	.align	2
.L85:
	.word	268431360
	.size	create_Imm16_X0, .-create_Imm16_X0
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_Imm16_X1, %function
create_Imm16_X1:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #20
	str	r0, [fp, #-24]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	mov	r0, r3
	mov	r1, #0
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r0, #11
	mov	r2, #0
	mov	r0, #0
	ldr	r1, .L89
	and	r4, r2, r0
	and	r5, r3, r1
	mov	r2, r4
	mov	r3, r5
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
.L90:
	.align	2
.L89:
	.word	134215680
	.size	create_Imm16_X1, .-create_Imm16_X1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_Imm8_X0, %function
create_Imm8_X0:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #20
	str	r0, [fp, #-24]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #12
	mov	r2, r3
	mov	r3, #0
	mov	r0, #1044480
	mov	r1, #0
	and	r4, r2, r0
	and	r5, r3, r1
	mov	r2, r4
	mov	r3, r5
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
	.size	create_Imm8_X0, .-create_Imm8_X0
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_Imm8_X1, %function
create_Imm8_X1:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #20
	str	r0, [fp, #-24]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	mov	r0, r3
	mov	r1, #0
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r0, #11
	mov	r2, #0
	mov	r0, #0
	ldr	r1, .L95
	and	r4, r2, r0
	and	r5, r3, r1
	mov	r2, r4
	mov	r3, r5
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
.L96:
	.align	2
.L95:
	.word	522240
	.size	create_Imm8_X1, .-create_Imm8_X1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_Imm8_Y0, %function
create_Imm8_Y0:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #20
	str	r0, [fp, #-24]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #12
	mov	r2, r3
	mov	r3, #0
	mov	r0, #1044480
	mov	r1, #0
	and	r4, r2, r0
	and	r5, r3, r1
	mov	r2, r4
	mov	r3, r5
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
	.size	create_Imm8_Y0, .-create_Imm8_Y0
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_Imm8_Y1, %function
create_Imm8_Y1:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #20
	str	r0, [fp, #-24]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	mov	r0, r3
	mov	r1, #0
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r0, #11
	mov	r2, #0
	mov	r0, #0
	ldr	r1, .L101
	and	r4, r2, r0
	and	r5, r3, r1
	mov	r2, r4
	mov	r3, r5
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
.L102:
	.align	2
.L101:
	.word	522240
	.size	create_Imm8_Y1, .-create_Imm8_Y1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_JumpOff_X1, %function
create_JumpOff_X1:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #20
	str	r0, [fp, #-24]
	ldr	r1, [fp, #-24]
	str	r1, [fp, #-16]
	ldr	r1, [fp, #-16]
	mov	r0, r1
	mov	r1, #0
	lsr	r3, r0, #1
	lsl	r2, r0, #31
	mov	r0, #-2147483648
	mvn	r1, #-67108864
	and	r4, r2, r0
	and	r5, r3, r1
	mov	r2, r4
	mov	r3, r5
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
	.size	create_JumpOff_X1, .-create_JumpOff_X1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_MF_Imm14_X1, %function
create_MF_Imm14_X1:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #20
	str	r0, [fp, #-24]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	mov	r0, r3
	mov	r1, #0
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r0, #5
	mov	r2, #0
	mov	r0, #0
	ldr	r1, .L107
	and	r4, r2, r0
	and	r5, r3, r1
	mov	r2, r4
	mov	r3, r5
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
.L108:
	.align	2
.L107:
	.word	524256
	.size	create_MF_Imm14_X1, .-create_MF_Imm14_X1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_MT_Imm14_X1, %function
create_MT_Imm14_X1:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, r6, r7, r8, r9, fp}
	add	fp, sp, #24
	sub	sp, sp, #20
	str	r0, [fp, #-40]
	ldr	r1, [fp, #-40]
	str	r1, [fp, #-32]
	ldr	r1, [fp, #-32]
	mov	r0, r1
	mov	r1, #0
	lsr	r7, r0, #1
	lsl	r6, r0, #31
	mov	r0, #-2147483648
	mov	r1, #31
	and	r4, r6, r0
	and	r5, r7, r1
	ldr	r1, [fp, #-32]
	mov	r6, r1
	mov	r7, #0
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r6, #5
	mov	r0, #0
	mov	r6, #0
	ldr	r7, .L111
	and	r2, r0, r6
	and	r3, r1, r7
	orr	r8, r4, r2
	orr	r9, r5, r3
	mov	r2, r8
	mov	r3, r9
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #24
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, fp}
	bx	lr
.L112:
	.align	2
.L111:
	.word	522240
	.size	create_MT_Imm14_X1, .-create_MT_Imm14_X1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_ShAmt_X0, %function
create_ShAmt_X0:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #20
	str	r0, [fp, #-24]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #12
	mov	r2, r3
	mov	r3, #0
	mov	r0, #258048
	mov	r1, #0
	and	r4, r2, r0
	and	r5, r3, r1
	mov	r2, r4
	mov	r3, r5
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
	.size	create_ShAmt_X0, .-create_ShAmt_X0
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_ShAmt_X1, %function
create_ShAmt_X1:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #20
	str	r0, [fp, #-24]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	mov	r0, r3
	mov	r1, #0
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r0, #11
	mov	r2, #0
	mov	r0, #0
	mov	r1, #129024
	and	r4, r2, r0
	and	r5, r3, r1
	mov	r2, r4
	mov	r3, r5
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
	.size	create_ShAmt_X1, .-create_ShAmt_X1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_ShAmt_Y0, %function
create_ShAmt_Y0:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #20
	str	r0, [fp, #-24]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #12
	mov	r2, r3
	mov	r3, #0
	mov	r0, #258048
	mov	r1, #0
	and	r4, r2, r0
	and	r5, r3, r1
	mov	r2, r4
	mov	r3, r5
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
	.size	create_ShAmt_Y0, .-create_ShAmt_Y0
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_ShAmt_Y1, %function
create_ShAmt_Y1:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #20
	str	r0, [fp, #-24]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	mov	r0, r3
	mov	r1, #0
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r0, #11
	mov	r2, #0
	mov	r0, #0
	mov	r1, #129024
	and	r4, r2, r0
	and	r5, r3, r1
	mov	r2, r4
	mov	r3, r5
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
	.size	create_ShAmt_Y1, .-create_ShAmt_Y1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_SrcA_X0, %function
create_SrcA_X0:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #20
	str	r0, [fp, #-24]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #6
	mov	r2, r3
	mov	r3, #0
	mov	r0, #4032
	mov	r1, #0
	and	r4, r2, r0
	and	r5, r3, r1
	mov	r2, r4
	mov	r3, r5
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
	.size	create_SrcA_X0, .-create_SrcA_X0
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_SrcA_X1, %function
create_SrcA_X1:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #20
	str	r0, [fp, #-24]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	mov	r0, r3
	mov	r1, #0
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r0, #5
	mov	r2, #0
	mov	r0, #0
	mov	r1, #2016
	and	r4, r2, r0
	and	r5, r3, r1
	mov	r2, r4
	mov	r3, r5
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
	.size	create_SrcA_X1, .-create_SrcA_X1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_SrcA_Y0, %function
create_SrcA_Y0:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #20
	str	r0, [fp, #-24]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #6
	mov	r2, r3
	mov	r3, #0
	mov	r0, #4032
	mov	r1, #0
	and	r4, r2, r0
	and	r5, r3, r1
	mov	r2, r4
	mov	r3, r5
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
	.size	create_SrcA_Y0, .-create_SrcA_Y0
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_SrcA_Y1, %function
create_SrcA_Y1:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #20
	str	r0, [fp, #-24]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	mov	r0, r3
	mov	r1, #0
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r0, #5
	mov	r2, #0
	mov	r0, #0
	mov	r1, #2016
	and	r4, r2, r0
	and	r5, r3, r1
	mov	r2, r4
	mov	r3, r5
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
	.size	create_SrcA_Y1, .-create_SrcA_Y1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_SrcA_Y2, %function
create_SrcA_Y2:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #20
	str	r0, [fp, #-24]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #20
	mov	r2, r3
	mov	r3, #0
	mov	r0, #66060288
	mov	r1, #0
	and	r4, r2, r0
	and	r5, r3, r1
	mov	r2, r4
	mov	r3, r5
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
	.size	create_SrcA_Y2, .-create_SrcA_Y2
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_SrcBDest_Y2, %function
create_SrcBDest_Y2:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #20
	str	r0, [fp, #-24]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	mov	r0, r3
	mov	r1, #0
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r0, #19
	mov	r2, #0
	mov	r0, #0
	mov	r1, #33030144
	and	r4, r2, r0
	and	r5, r3, r1
	mov	r2, r4
	mov	r3, r5
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
	.size	create_SrcBDest_Y2, .-create_SrcBDest_Y2
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_SrcB_X0, %function
create_SrcB_X0:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #20
	str	r0, [fp, #-24]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #12
	mov	r2, r3
	mov	r3, #0
	mov	r0, #258048
	mov	r1, #0
	and	r4, r2, r0
	and	r5, r3, r1
	mov	r2, r4
	mov	r3, r5
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
	.size	create_SrcB_X0, .-create_SrcB_X0
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_SrcB_X1, %function
create_SrcB_X1:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #20
	str	r0, [fp, #-24]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	mov	r0, r3
	mov	r1, #0
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r0, #11
	mov	r2, #0
	mov	r0, #0
	mov	r1, #129024
	and	r4, r2, r0
	and	r5, r3, r1
	mov	r2, r4
	mov	r3, r5
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
	.size	create_SrcB_X1, .-create_SrcB_X1
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_SrcB_Y0, %function
create_SrcB_Y0:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #20
	str	r0, [fp, #-24]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #12
	mov	r2, r3
	mov	r3, #0
	mov	r0, #258048
	mov	r1, #0
	and	r4, r2, r0
	and	r5, r3, r1
	mov	r2, r4
	mov	r3, r5
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
	.size	create_SrcB_Y0, .-create_SrcB_Y0
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	create_SrcB_Y1, %function
create_SrcB_Y1:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #20
	str	r0, [fp, #-24]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	mov	r0, r3
	mov	r1, #0
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r0, #11
	mov	r2, #0
	mov	r0, #0
	mov	r1, #129024
	and	r4, r2, r0
	and	r5, r3, r1
	mov	r2, r4
	mov	r3, r5
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
	.size	create_SrcB_Y1, .-create_SrcB_Y1
	.global	tilegx_opcodes
	.section	.rodata
	.align	2
.LC64:
	.ascii	"bpt\000"
	.align	2
.LC65:
	.ascii	"info\000"
	.align	2
.LC66:
	.ascii	"infol\000"
	.align	2
.LC67:
	.ascii	"ld4s_tls\000"
	.align	2
.LC68:
	.ascii	"ld_tls\000"
	.align	2
.LC69:
	.ascii	"move\000"
	.align	2
.LC70:
	.ascii	"movei\000"
	.align	2
.LC71:
	.ascii	"moveli\000"
	.align	2
.LC72:
	.ascii	"prefetch\000"
	.align	2
.LC73:
	.ascii	"prefetch_add_l1\000"
	.align	2
.LC74:
	.ascii	"prefetch_add_l1_fault\000"
	.align	2
.LC75:
	.ascii	"prefetch_add_l2\000"
	.align	2
.LC76:
	.ascii	"prefetch_add_l2_fault\000"
	.align	2
.LC77:
	.ascii	"prefetch_add_l3\000"
	.align	2
.LC78:
	.ascii	"prefetch_add_l3_fault\000"
	.align	2
.LC79:
	.ascii	"prefetch_l1\000"
	.align	2
.LC80:
	.ascii	"prefetch_l1_fault\000"
	.align	2
.LC81:
	.ascii	"prefetch_l2\000"
	.align	2
.LC82:
	.ascii	"prefetch_l2_fault\000"
	.align	2
.LC83:
	.ascii	"prefetch_l3\000"
	.align	2
.LC84:
	.ascii	"prefetch_l3_fault\000"
	.align	2
.LC85:
	.ascii	"raise\000"
	.align	2
.LC86:
	.ascii	"add\000"
	.align	2
.LC87:
	.ascii	"addi\000"
	.align	2
.LC88:
	.ascii	"addli\000"
	.align	2
.LC89:
	.ascii	"addx\000"
	.align	2
.LC90:
	.ascii	"addxi\000"
	.align	2
.LC91:
	.ascii	"addxli\000"
	.align	2
.LC92:
	.ascii	"addxsc\000"
	.align	2
.LC93:
	.ascii	"and\000"
	.align	2
.LC94:
	.ascii	"andi\000"
	.align	2
.LC95:
	.ascii	"beqz\000"
	.align	2
.LC96:
	.ascii	"beqzt\000"
	.align	2
.LC97:
	.ascii	"bfexts\000"
	.align	2
.LC98:
	.ascii	"bfextu\000"
	.align	2
.LC99:
	.ascii	"bfins\000"
	.align	2
.LC100:
	.ascii	"bgez\000"
	.align	2
.LC101:
	.ascii	"bgezt\000"
	.align	2
.LC102:
	.ascii	"bgtz\000"
	.align	2
.LC103:
	.ascii	"bgtzt\000"
	.align	2
.LC104:
	.ascii	"blbc\000"
	.align	2
.LC105:
	.ascii	"blbct\000"
	.align	2
.LC106:
	.ascii	"blbs\000"
	.align	2
.LC107:
	.ascii	"blbst\000"
	.align	2
.LC108:
	.ascii	"blez\000"
	.align	2
.LC109:
	.ascii	"blezt\000"
	.align	2
.LC110:
	.ascii	"bltz\000"
	.align	2
.LC111:
	.ascii	"bltzt\000"
	.align	2
.LC112:
	.ascii	"bnez\000"
	.align	2
.LC113:
	.ascii	"bnezt\000"
	.align	2
.LC114:
	.ascii	"clz\000"
	.align	2
.LC115:
	.ascii	"cmoveqz\000"
	.align	2
.LC116:
	.ascii	"cmovnez\000"
	.align	2
.LC117:
	.ascii	"cmpeq\000"
	.align	2
.LC118:
	.ascii	"cmpeqi\000"
	.align	2
.LC119:
	.ascii	"cmpexch\000"
	.align	2
.LC120:
	.ascii	"cmpexch4\000"
	.align	2
.LC121:
	.ascii	"cmples\000"
	.align	2
.LC122:
	.ascii	"cmpleu\000"
	.align	2
.LC123:
	.ascii	"cmplts\000"
	.align	2
.LC124:
	.ascii	"cmpltsi\000"
	.align	2
.LC125:
	.ascii	"cmpltu\000"
	.align	2
.LC126:
	.ascii	"cmpltui\000"
	.align	2
.LC127:
	.ascii	"cmpne\000"
	.align	2
.LC128:
	.ascii	"cmul\000"
	.align	2
.LC129:
	.ascii	"cmula\000"
	.align	2
.LC130:
	.ascii	"cmulaf\000"
	.align	2
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	.short	233
	.short	30
	.short	30
	.short	30
	.short	1
	.short	241
	.short	25
	.short	22
	.short	223
	.short	222
	.short	1007
	.short	190
	.short	190
	.short	190
	.short	190
	.short	192
	.short	192
	.short	192
	.short	192
	.short	194
	.short	194
	.short	194
	.short	194
	.short	419
	.short	335
	.short	335
	.short	335
	.short	491
	.short	428
	.short	431
	.short	434
	.short	437
	.short	440
	.short	443
	.short	446
	.short	449
	.short	110
	.short	335
	.short	101
	.short	110
	.short	335
	.short	110
	.short	110
	.short	335
	.short	116
	.short	110
	.short	335
	.short	115
	.short	110
	.short	335
	.short	118
	.short	110
	.short	335
	.short	117
	.short	110
	.short	335
	.short	149
	.short	110
	.short	335
	.short	179
	.short	241
	.short	57
	.short	58
	.short	59
	.short	61
	.short	241
	.short	335
	.short	335
	.short	53
	.short	63
	.short	241
	.short	335
	.short	335
	.short	153
	.short	177
	.short	241
	.short	29
	.short	180
	.short	472
	.short	333
	.short	235
	.short	181
	.short	181
	.short	181
	.short	477
	.short	237
	.short	181
	.short	181
	.short	181
	.short	482
	.short	239
	.short	181
	.short	181
	.short	181
	.short	5
	.short	241
	.short	186
	.short	188
	.short	199
	.short	201
	.short	241
	.short	335
	.short	191
	.short	193
	.short	195
	.short	241
	.short	187
	.short	196
	.short	200
	.short	202
	.align	2
	.type	decode_Y2_fsm, %object
	.size	decode_Y2_fsm, 236
decode_Y2_fsm:
	.short	254
	.short	335
	.short	340
	.short	401
	.short	444
	.short	503
	.short	349
	.short	349
	.short	349
	.short	352
	.short	375
	.short	375
	.short	375
	.short	378
	.short	90
	.short	120
	.short	122
	.short	90
	.short	355
	.short	365
	.short	243
	.short	120
	.short	120
	.short	120
	.short	360
	.short	245
	.short	120
	.short	120
	.short	120
	.short	16
	.short	243
	.short	122
	.short	122
	.short	122
	.short	370
	.short	245
	.short	122
	.short	122
	.short	122
	.short	8
	.short	90
	.short	124
	.short	126
	.short	90
	.short	381
	.short	391
	.short	243
	.short	124
	.short	124
	.short	124
	.short	386
	.short	245
	.short	124
	.short	124
	.short	124
	.short	18
	.short	243
	.short	126
	.short	126
	.short	126
	.short	396
	.short	245
	.short	126
	.short	126
	.short	126
	.short	17
	.short	248
	.short	406
	.short	409
	.short	425
	.short	428
	.short	90
	.short	335
	.short	128
	.short	90
	.short	335
	.short	412
	.short	243
	.short	128
	.short	128
	.short	128
	.short	417
	.short	245
	.short	128
	.short	128
	.short	128
	.short	422
	.short	119
	.short	128
	.short	20
	.short	90
	.short	130
	.short	119
	.short	90
	.short	431
	.short	119
	.short	243
	.short	130
	.short	130
	.short	130
	.short	436
	.short	245
	.short	130
	.short	130
	.short	130
	.short	441
	.short	119
	.short	130
	.short	19
	.short	90
	.short	447
	.short	450
	.short	121
	.short	207
	.short	211
	.short	121
	.short	209
	.short	206
	.global	tilegx_bundle_decoder_fsms
	.align	2
	.type	tilegx_bundle_decoder_fsms, %object
	.size	tilegx_bundle_decoder_fsms, 20
tilegx_bundle_decoder_fsms:
	.word	decode_X0_fsm
	.word	decode_X1_fsm
	.word	decode_Y0_fsm
	.word	decode_Y1_fsm
	.word	decode_Y2_fsm
	.global	tilegx_operands
	.align	2
	.type	tilegx_operands, %object
	.size	tilegx_operands, 560
tilegx_operands:
	.word	1
	.short	23
	.byte	40
	.byte	0
	.word	create_Imm8_X0
	.word	get_Imm8_X0
	.word	1
	.short	25
	.byte	40
	.byte	0
	.word	create_Imm8_X1
	.word	get_Imm8_X1
	.word	1
	.short	24
	.byte	40
	.byte	0
	.word	create_Imm8_Y0
	.word	get_Imm8_Y0
	.word	1
	.short	26
	.byte	40
	.byte	0
	.word	create_Imm8_Y1
	.word	get_Imm8_Y1
	.word	1
	.short	44
	.byte	48
	.byte	0
	.word	create_Imm16_X0
	.word	get_Imm16_X0
	.word	1
	.short	45
	.byte	48
	.byte	0
	.word	create_Imm16_X1
	.word	get_Imm16_X1
	.word	0
	.short	0
	.byte	134
	.byte	0
	.word	create_Dest_X1
	.word	get_Dest_X1
	.word	0
	.short	0
	.byte	70
	.byte	0
	.word	create_SrcA_X1
	.word	get_SrcA_X1
	.word	0
	.short	0
	.byte	134
	.byte	0
	.word	create_Dest_X0
	.word	get_Dest_X0
	.word	0
	.short	0
	.byte	70
	.byte	0
	.word	create_SrcA_X0
	.word	get_SrcA_X0
	.word	0
	.short	0
	.byte	134
	.byte	0
	.word	create_Dest_Y0
	.word	get_Dest_Y0
	.word	0
	.short	0
	.byte	70
	.byte	0
	.word	create_SrcA_Y0
	.word	get_SrcA_Y0
	.word	0
	.short	0
	.byte	134
	.byte	0
	.word	create_Dest_Y1
	.word	get_Dest_Y1
	.word	0
	.short	0
	.byte	70
	.byte	0
	.word	create_SrcA_Y1
	.word	get_SrcA_Y1
	.word	0
	.short	0
	.byte	70
	.byte	0
	.word	create_SrcA_Y2
	.word	get_SrcA_Y2
	.word	0
	.short	0
	.byte	198
	.byte	0
	.word	create_SrcA_X1
	.word	get_SrcA_X1
	.word	0
	.short	0
	.byte	70
	.byte	0
	.word	create_SrcB_X0
	.word	get_SrcB_X0
	.word	0
	.short	0
	.byte	70
	.byte	0
	.word	create_SrcB_X1
	.word	get_SrcB_X1
	.word	0
	.short	0
	.byte	70
	.byte	0
	.word	create_SrcB_Y0
	.word	get_SrcB_Y0
	.word	0
	.short	0
	.byte	70
	.byte	0
	.word	create_SrcB_Y1
	.word	get_SrcB_Y1
	.word	2
	.short	20
	.byte	49
	.byte	7
	.word	create_BrOff_X1
	.word	get_BrOff_X1
	.word	1
	.short	30
	.byte	6
	.byte	0
	.word	create_BFStart_X0
	.word	get_BFStart_X0
	.word	1
	.short	31
	.byte	6
	.byte	0
	.word	create_BFEnd_X0
	.word	get_BFEnd_X0
	.word	0
	.short	0
	.byte	198
	.byte	0
	.word	create_Dest_X0
	.word	get_Dest_X0
	.word	0
	.short	0
	.byte	198
	.byte	0
	.word	create_Dest_Y0
	.word	get_Dest_Y0
	.word	2
	.short	21
	.byte	59
	.byte	7
	.word	create_JumpOff_X1
	.word	get_JumpOff_X1
	.word	0
	.short	0
	.byte	134
	.byte	0
	.word	create_SrcBDest_Y2
	.word	get_SrcBDest_Y2
	.word	3
	.short	29
	.byte	14
	.byte	0
	.word	create_MF_Imm14_X1
	.word	get_MF_Imm14_X1
	.word	3
	.short	28
	.byte	14
	.byte	0
	.word	create_MT_Imm14_X1
	.word	get_MT_Imm14_X1
	.word	1
	.short	32
	.byte	6
	.byte	0
	.word	create_ShAmt_X0
	.word	get_ShAmt_X0
	.word	1
	.short	33
	.byte	6
	.byte	0
	.word	create_ShAmt_X1
	.word	get_ShAmt_X1
	.word	1
	.short	34
	.byte	6
	.byte	0
	.word	create_ShAmt_Y0
	.word	get_ShAmt_Y0
	.word	1
	.short	35
	.byte	6
	.byte	0
	.word	create_ShAmt_Y1
	.word	get_ShAmt_Y1
	.word	0
	.short	0
	.byte	70
	.byte	0
	.word	create_SrcBDest_Y2
	.word	get_SrcBDest_Y2
	.word	1
	.short	27
	.byte	40
	.byte	0
	.word	create_Dest_Imm8_X1
	.word	get_Dest_Imm8_X1
	.text
	.align	2
	.global	find_opcode
	.syntax unified
	.arm
	.fpu softvfp
	.type	find_opcode, %function
find_opcode:
	@ args = 0, pretend = 0, frame = 32
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #36
	str	r0, [fp, #-36]
	str	r1, [fp, #-32]
	str	r2, [fp, #-40]
	ldr	r2, .L146
	ldr	r3, [fp, #-40]
	ldr	r3, [r2, r3, lsl #2]
	str	r3, [fp, #-20]
	mov	r3, #0
	str	r3, [fp, #-24]
.L144:
	ldr	r3, [fp, #-24]
	lsl	r3, r3, #1
	ldr	r2, [fp, #-20]
	add	r3, r2, r3
	ldrh	r3, [r3]	@ movhi
	strh	r3, [fp, #-28]	@ movhi
	ldrh	r3, [fp, #-28]
	and	r1, r3, #63
	sub	r3, fp, #36
	ldmia	r3, {r2-r3}
	rsb	ip, r1, #32
	sub	r0, r1, #32
	lsr	r4, r2, r1
	orr	r4, r4, r3, lsl ip
	orr	r4, r4, r3, lsr r0
	lsr	r5, r3, r1
	mov	r2, r4
	ldrh	r3, [fp, #-28]
	lsr	r3, r3, #6
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	and	r3, r3, r2
	str	r3, [fp, #-16]
	ldr	r2, [fp, #-24]
	ldr	r3, [fp, #-16]
	add	r3, r2, r3
	add	r3, r3, #1
	lsl	r3, r3, #1
	ldr	r2, [fp, #-20]
	add	r3, r2, r3
	ldrh	r3, [r3]	@ movhi
	strh	r3, [fp, #-26]	@ movhi
	ldrh	r3, [fp, #-26]
	cmp	r3, #336
	bcs	.L142
	ldrh	r2, [fp, #-26]
	mov	r3, r2
	lsl	r3, r3, #3
	sub	r3, r3, r2
	lsl	r3, r3, #4
	ldr	r2, .L146+4
	add	r3, r3, r2
	b	.L145
.L142:
	ldrh	r3, [fp, #-26]
	sub	r3, r3, #332
	sub	r3, r3, #3
	str	r3, [fp, #-24]
	b	.L144
.L145:
	mov	r0, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
.L147:
	.align	2
.L146:
	.word	tilegx_bundle_decoder_fsms
	.word	tilegx_opcodes
	.size	find_opcode, .-find_opcode
	.align	2
	.global	parse_insn_tilegx
	.syntax unified
	.arm
	.fpu softvfp
	.type	parse_insn_tilegx, %function
parse_insn_tilegx:
	@ args = 4, pretend = 0, frame = 64
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, fp, lr}
	add	fp, sp, #20
	sub	sp, sp, #64
	str	r0, [fp, #-76]
	str	r1, [fp, #-72]
	str	r2, [fp, #-84]
	str	r3, [fp, #-80]
	mov	r3, #0
	str	r3, [fp, #-68]
	sub	r3, fp, #76
	ldmia	r3, {r2-r3}
	mov	r0, #0
	mov	r1, #-1073741824
	and	r6, r2, r0
	and	r7, r3, r1
	orrs	r3, r6, r7
	bne	.L149
	mov	r3, #0
	str	r3, [fp, #-60]
	mov	r3, #1
	str	r3, [fp, #-56]
	b	.L150
.L149:
	mov	r3, #2
	str	r3, [fp, #-60]
	mov	r3, #4
	str	r3, [fp, #-56]
.L150:
	ldr	r3, [fp, #-60]
	str	r3, [fp, #-64]
	b	.L151
.L157:
	ldr	r3, [fp, #-68]
	add	r2, r3, #1
	str	r2, [fp, #-68]
	mov	r2, r3
	mov	r3, r2
	lsl	r3, r3, #3
	sub	r3, r3, r2
	lsl	r3, r3, #3
	mov	r2, r3
	ldr	r3, [fp, #4]
	add	r3, r3, r2
	str	r3, [fp, #-44]
	ldr	r3, [fp, #-64]
	mov	r2, r3
	sub	r1, fp, #76
	ldmia	r1, {r0-r1}
	bl	find_opcode
	str	r0, [fp, #-40]
	ldr	r3, [fp, #-44]
	ldr	r2, [fp, #-40]
	str	r2, [r3]
	mov	r3, #0
	str	r3, [fp, #-52]
	b	.L152
.L156:
	ldr	r2, [fp, #-40]
	ldr	r3, [fp, #-64]
	lsl	r3, r3, #2
	add	r2, r2, r3
	ldr	r3, [fp, #-52]
	add	r3, r2, r3
	add	r3, r3, #12
	ldrb	r3, [r3]	@ zero_extendqisi2
	lsl	r3, r3, #4
	ldr	r2, .L159
	add	r3, r3, r2
	str	r3, [fp, #-36]
	ldr	r3, [fp, #-36]
	ldr	r3, [r3, #12]
	sub	r1, fp, #76
	ldmia	r1, {r0-r1}
	blx	r3
	mov	r3, r0
	str	r3, [fp, #-48]
	ldr	r3, [fp, #-36]
	ldrb	r3, [r3, #6]	@ zero_extendqisi2
	and	r3, r3, #32
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L153
	ldr	r3, [fp, #-36]
	ldrb	r3, [r3, #6]
	and	r3, r3, #31
	and	r3, r3, #255
	rsb	r3, r3, #32
	str	r3, [fp, #-32]
	ldr	r2, [fp, #-48]
	ldr	r3, [fp, #-32]
	lsl	r2, r2, r3
	ldr	r3, [fp, #-32]
	asr	r3, r2, r3
	str	r3, [fp, #-48]
.L153:
	ldr	r3, [fp, #-36]
	ldr	r3, [r3]
	cmp	r3, #2
	bne	.L154
	ldr	r3, [fp, #-48]
	lsl	r3, r3, #3
	mov	r0, r3
	asr	r1, r0, #31
	sub	r3, fp, #84
	ldmia	r3, {r2-r3}
	adds	r4, r0, r2
	adc	r5, r1, r3
	str	r4, [fp, #-28]
	str	r5, [fp, #-24]
	b	.L155
.L154:
	ldr	r3, [fp, #-48]
	mov	r2, r3
	asr	r3, r2, #31
	str	r2, [fp, #-28]
	str	r3, [fp, #-24]
.L155:
	ldr	r2, [fp, #-44]
	ldr	r3, [fp, #-52]
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r2, [fp, #-36]
	str	r2, [r3, #4]
	ldr	r2, [fp, #-44]
	ldr	r3, [fp, #-52]
	add	r3, r3, #3
	lsl	r3, r3, #3
	add	r1, r2, r3
	sub	r3, fp, #28
	ldmia	r3, {r2-r3}
	stm	r1, {r2-r3}
	ldr	r3, [fp, #-52]
	add	r3, r3, #1
	str	r3, [fp, #-52]
.L152:
	ldr	r3, [fp, #-40]
	ldrb	r3, [r3, #9]	@ zero_extendqisi2
	mov	r2, r3
	ldr	r3, [fp, #-52]
	cmp	r3, r2
	blt	.L156
	ldr	r3, [fp, #-64]
	add	r3, r3, #1
	str	r3, [fp, #-64]
.L151:
	ldr	r2, [fp, #-64]
	ldr	r3, [fp, #-56]
	cmp	r2, r3
	ble	.L157
	ldr	r3, [fp, #-68]
	mov	r0, r3
	sub	sp, fp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, fp, pc}
.L160:
	.align	2
.L159:
	.word	tilegx_operands
	.size	parse_insn_tilegx, .-parse_insn_tilegx
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	tilegx_spr_compare, %function
tilegx_spr_compare:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	ldr	r3, [fp, #-16]
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-20]
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-12]
	ldr	r2, [r3]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3]
	sub	r3, r2, r3
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	tilegx_spr_compare, .-tilegx_spr_compare
	.global	tilegx_sprs
	.section	.rodata
	.align	2
.LC399:
	.ascii	"MPL_MEM_ERROR_SET_0\000"
	.align	2
.LC400:
	.ascii	"MPL_MEM_ERROR_SET_1\000"
	.align	2
.LC401:
	.ascii	"MPL_MEM_ERROR_SET_2\000"
	.align	2
.LC402:
	.ascii	"MPL_MEM_ERROR_SET_3\000"
	.align	2
.LC403:
	.ascii	"MPL_MEM_ERROR\000"
	.align	2
.LC404:
	.ascii	"MEM_ERROR_CBOX_ADDR\000"
	.align	2
.LC405:
	.ascii	"MEM_ERROR_CBOX_STATUS\000"
	.align	2
.LC406:
	.ascii	"MEM_ERROR_ENABLE\000"
	.align	2
.LC407:
	.ascii	"MEM_ERROR_MBOX_ADDR\000"
	.align	2
.LC408:
	.ascii	"MEM_ERROR_MBOX_STATUS\000"
	.align	2
.LC409:
	.ascii	"SBOX_ERROR\000"
	.align	2
.LC410:
	.ascii	"XDN_DEMUX_ERROR\000"
	.align	2
.LC411:
	.ascii	"MPL_SINGLE_STEP_3_SET_0\000"
	.align	2
.LC412:
	.ascii	"MPL_SINGLE_STEP_3_SET_1\000"
	.align	2
.LC413:
	.ascii	"MPL_SINGLE_STEP_3_SET_2\000"
	.align	2
.LC414:
	.ascii	"MPL_SINGLE_STEP_3_SET_3\000"
	.align	2
.LC415:
	.ascii	"MPL_SINGLE_STEP_3\000"
	.align	2
.LC416:
	.ascii	"SINGLE_STEP_CONTROL_3\000"
	.align	2
.LC417:
	.ascii	"MPL_SINGLE_STEP_2_SET_0\000"
	.align	2
.LC418:
	.ascii	"MPL_SINGLE_STEP_2_SET_1\000"
	.align	2
.LC419:
	.ascii	"MPL_SINGLE_STEP_2_SET_2\000"
	.align	2
.LC420:
	.ascii	"MPL_SINGLE_STEP_2_SET_3\000"
	.align	2
.LC421:
	.ascii	"MPL_SINGLE_STEP_2\000"
	.align	2
.LC422:
	.ascii	"SINGLE_STEP_CONTROL_2\000"
	.align	2
.LC423:
	.ascii	"MPL_SINGLE_STEP_1_SET_0\000"
	.align	2
.LC424:
	.ascii	"MPL_SINGLE_STEP_1_SET_1\000"
	.align	2
.LC425:
	.ascii	"MPL_SINGLE_STEP_1_SET_2\000"
	.align	2
.LC426:
	.ascii	"MPL_SINGLE_STEP_1_SET_3\000"
	.align	2
.LC427:
	.ascii	"MPL_SINGLE_STEP_1\000"
	.align	2
.LC428:
	.ascii	"SINGLE_STEP_CONTROL_1\000"
	.align	2
.LC429:
	.ascii	"MPL_SINGLE_STEP_0_SET_0\000"
	.align	2
.LC430:
	.ascii	"MPL_SINGLE_STEP_0_SET_1\000"
	.align	2
.LC431:
	.ascii	"MPL_SINGLE_STEP_0_SET_2\000"
	.align	2
.LC432:
	.ascii	"MPL_SINGLE_STEP_0_SET_3\000"
	.align	2
.LC433:
	.ascii	"MPL_SINGLE_STEP_0\000"
	.align	2
.LC434:
	.ascii	"SINGLE_STEP_CONTROL_0\000"
	.align	2
.LC435:
	.ascii	"MPL_IDN_COMPLETE_SET_0\000"
	.align	2
.LC436:
	.ascii	"MPL_IDN_COMPLETE_SET_1\000"
	.align	2
.LC437:
	.ascii	"MPL_IDN_COMPLETE_SET_2\000"
	.align	2
.LC438:
	.ascii	"MPL_IDN_COMPLETE_SET_3\000"
	.align	2
.LC439:
	.ascii	"MPL_IDN_COMPLETE\000"
	.align	2
.LC440:
	.ascii	"IDN_COMPLETE_PENDING\000"
	.align	2
.LC441:
	.ascii	"MPL_UDN_COMPLETE_SET_0\000"
	.align	2
.LC442:
	.ascii	"MPL_UDN_COMPLETE_SET_1\000"
	.align	2
.LC443:
	.ascii	"MPL_UDN_COMPLETE_SET_2\000"
	.align	2
.LC444:
	.ascii	"MPL_UDN_COMPLETE_SET_3\000"
	.align	2
.LC445:
	.ascii	"MPL_UDN_COMPLETE\000"
	.align	2
.LC446:
	.ascii	"UDN_COMPLETE_PENDING\000"
	.align	2
.LC447:
	.ascii	"MPL_ITLB_MISS_SET_0\000"
	.align	2
.LC448:
	.ascii	"MPL_ITLB_MISS_SET_1\000"
	.align	2
.LC449:
	.ascii	"MPL_ITLB_MISS_SET_2\000"
	.align	2
.LC450:
	.ascii	"MPL_ITLB_MISS_SET_3\000"
	.align	2
.LC451:
	.ascii	"MPL_ITLB_MISS\000"
	.align	2
.LC452:
	.ascii	"ITLB_TSB_BASE_ADDR_0\000"
	.align	2
.LC453:
	.ascii	"ITLB_TSB_BASE_ADDR_1\000"
	.align	2
.LC454:
	.ascii	"ITLB_CURRENT_ATTR\000"
	.align	2
.LC455:
	.ascii	"ITLB_CURRENT_PA\000"
	.align	2
.LC456:
	.ascii	"ITLB_CURRENT_VA\000"
	.align	2
.LC457:
	.ascii	"ITLB_INDEX\000"
	.align	2
.LC458:
	.ascii	"ITLB_MATCH_0\000"
	.align	2
.LC459:
	.ascii	"ITLB_PERF\000"
	.align	2
.LC460:
	.ascii	"ITLB_PR\000"
	.align	2
.LC461:
	.ascii	"ITLB_TSB_ADDR_0\000"
	.align	2
.LC462:
	.ascii	"ITLB_TSB_ADDR_1\000"
	.align	2
.LC463:
	.ascii	"ITLB_TSB_FILL_CURRENT_ATTR\000"
	.align	2
.LC464:
	.ascii	"ITLB_TSB_FILL_MATCH\000"
	.align	2
.LC465:
	.ascii	"NUMBER_ITLB\000"
	.align	2
.LC466:
	.ascii	"REPLACEMENT_ITLB\000"
	.align	2
.LC467:
	.ascii	"WIRED_ITLB\000"
	.align	2
.LC468:
	.ascii	"MPL_ILL_SET_0\000"
	.align	2
.LC469:
	.ascii	"MPL_ILL_SET_1\000"
	.align	2
.LC470:
	.ascii	"MPL_ILL_SET_2\000"
	.align	2
.LC471:
	.ascii	"MPL_ILL_SET_3\000"
	.align	2
.LC472:
	.ascii	"MPL_ILL\000"
	.align	2
.LC473:
	.ascii	"MPL_GPV_SET_0\000"
	.align	2
.LC474:
	.ascii	"MPL_GPV_SET_1\000"
	.align	2
.LC475:
	.ascii	"MPL_GPV_SET_2\000"
	.align	2
.LC476:
	.ascii	"MPL_GPV_SET_3\000"
	.align	2
.LC477:
	.ascii	"MPL_GPV\000"
	.align	2
.LC478:
	.ascii	"GPV_REASON\000"
	.align	2
.LC479:
	.ascii	"MPL_IDN_ACCESS_SET_0\000"
	.align	2
.LC480:
	.ascii	"MPL_IDN_ACCESS_SET_1\000"
	.align	2
.LC481:
	.ascii	"MPL_IDN_ACCESS_SET_2\000"
	.align	2
.LC482:
	.ascii	"MPL_IDN_ACCESS_SET_3\000"
	.align	2
.LC483:
	.ascii	"MPL_IDN_ACCESS\000"
	.align	2
.LC484:
	.ascii	"IDN_DEMUX_COUNT_0\000"
	.align	2
.LC485:
	.ascii	"IDN_DEMUX_COUNT_1\000"
	.align	2
.LC486:
	.ascii	"IDN_FLUSH_EGRESS\000"
	.align	2
.LC487:
	.ascii	"IDN_PENDING\000"
	.align	2
.LC488:
	.ascii	"IDN_ROUTE_ORDER\000"
	.align	2
.LC489:
	.ascii	"IDN_SP_FIFO_CNT\000"
	.align	2
.LC490:
	.ascii	"IDN_DATA_AVAIL\000"
	.align	2
.LC491:
	.ascii	"MPL_UDN_ACCESS_SET_0\000"
	.align	2
.LC492:
	.ascii	"MPL_UDN_ACCESS_SET_1\000"
	.align	2
.LC493:
	.ascii	"MPL_UDN_ACCESS_SET_2\000"
	.align	2
.LC494:
	.ascii	"MPL_UDN_ACCESS_SET_3\000"
	.align	2
.LC495:
	.ascii	"MPL_UDN_ACCESS\000"
	.align	2
.LC496:
	.ascii	"UDN_DEMUX_COUNT_0\000"
	.align	2
.LC497:
	.ascii	"UDN_DEMUX_COUNT_1\000"
	.align	2
.LC498:
	.ascii	"UDN_DEMUX_COUNT_2\000"
	.align	2
.LC499:
	.ascii	"UDN_DEMUX_COUNT_3\000"
	.align	2
.LC500:
	.ascii	"UDN_FLUSH_EGRESS\000"
	.align	2
.LC501:
	.ascii	"UDN_PENDING\000"
	.align	2
.LC502:
	.ascii	"UDN_ROUTE_ORDER\000"
	.align	2
.LC503:
	.ascii	"UDN_SP_FIFO_CNT\000"
	.align	2
.LC504:
	.ascii	"UDN_DATA_AVAIL\000"
	.align	2
.LC505:
	.ascii	"MPL_SWINT_3_SET_0\000"
	.align	2
.LC506:
	.ascii	"MPL_SWINT_3_SET_1\000"
	.align	2
.LC507:
	.ascii	"MPL_SWINT_3_SET_2\000"
	.align	2
.LC508:
	.ascii	"MPL_SWINT_3_SET_3\000"
	.align	2
.LC509:
	.ascii	"MPL_SWINT_3\000"
	.align	2
.LC510:
	.ascii	"MPL_SWINT_2_SET_0\000"
	.align	2
.LC511:
	.ascii	"MPL_SWINT_2_SET_1\000"
	.align	2
.LC512:
	.ascii	"MPL_SWINT_2_SET_2\000"
	.align	2
.LC513:
	.ascii	"MPL_SWINT_2_SET_3\000"
	.align	2
.LC514:
	.ascii	"MPL_SWINT_2\000"
	.align	2
.LC515:
	.ascii	"MPL_SWINT_1_SET_0\000"
	.align	2
.LC516:
	.ascii	"MPL_SWINT_1_SET_1\000"
	.align	2
.LC517:
	.ascii	"MPL_SWINT_1_SET_2\000"
	.align	2
.LC518:
	.ascii	"MPL_SWINT_1_SET_3\000"
	.align	2
.LC519:
	.ascii	"MPL_SWINT_1\000"
	.align	2
.LC520:
	.ascii	"MPL_SWINT_0_SET_0\000"
	.align	2
.LC521:
	.ascii	"MPL_SWINT_0_SET_1\000"
	.align	2
.LC522:
	.ascii	"MPL_SWINT_0_SET_2\000"
	.align	2
.LC523:
	.ascii	"MPL_SWINT_0_SET_3\000"
	.align	2
.LC524:
	.ascii	"MPL_SWINT_0\000"
	.align	2
.LC525:
	.ascii	"MPL_ILL_TRANS_SET_0\000"
	.align	2
.LC526:
	.ascii	"MPL_ILL_TRANS_SET_1\000"
	.align	2
.LC527:
	.ascii	"MPL_ILL_TRANS_SET_2\000"
	.align	2
.LC528:
	.ascii	"MPL_ILL_TRANS_SET_3\000"
	.align	2
.LC529:
	.ascii	"MPL_ILL_TRANS\000"
	.align	2
.LC530:
	.ascii	"ILL_TRANS_REASON\000"
	.align	2
.LC531:
	.ascii	"ILL_VA_PC\000"
	.align	2
.LC532:
	.ascii	"MPL_UNALIGN_DATA_SET_0\000"
	.align	2
.LC533:
	.ascii	"MPL_UNALIGN_DATA_SET_1\000"
	.align	2
.LC534:
	.ascii	"MPL_UNALIGN_DATA_SET_2\000"
	.align	2
.LC535:
	.ascii	"MPL_UNALIGN_DATA_SET_3\000"
	.align	2
.LC536:
	.ascii	"MPL_UNALIGN_DATA\000"
	.align	2
.LC537:
	.ascii	"MPL_DTLB_MISS_SET_0\000"
	.align	2
.LC538:
	.ascii	"MPL_DTLB_MISS_SET_1\000"
	.align	2
.LC539:
	.ascii	"MPL_DTLB_MISS_SET_2\000"
	.align	2
.LC540:
	.ascii	"MPL_DTLB_MISS_SET_3\000"
	.align	2
.LC541:
	.ascii	"MPL_DTLB_MISS\000"
	.align	2
.LC542:
	.ascii	"DTLB_TSB_BASE_ADDR_0\000"
	.align	2
.LC543:
	.ascii	"DTLB_TSB_BASE_ADDR_1\000"
	.align	2
.LC544:
	.ascii	"AAR\000"
	.align	2
.LC545:
	.ascii	"CACHE_PINNED_WAYS\000"
	.align	2
.LC546:
	.ascii	"DTLB_BAD_ADDR\000"
	.align	2
.LC547:
	.ascii	"DTLB_BAD_ADDR_REASON\000"
	.align	2
.LC548:
	.ascii	"DTLB_CURRENT_ATTR\000"
	.align	2
.LC549:
	.ascii	"DTLB_CURRENT_PA\000"
	.align	2
.LC550:
	.ascii	"DTLB_CURRENT_VA\000"
	.align	2
.LC551:
	.ascii	"DTLB_INDEX\000"
	.align	2
.LC552:
	.ascii	"DTLB_MATCH_0\000"
	.align	2
.LC553:
	.ascii	"DTLB_PERF\000"
	.align	2
.LC554:
	.ascii	"DTLB_TSB_ADDR_0\000"
	.align	2
.LC555:
	.ascii	"DTLB_TSB_ADDR_1\000"
	.align	2
.LC556:
	.ascii	"DTLB_TSB_FILL_CURRENT_ATTR\000"
	.align	2
.LC557:
	.ascii	"DTLB_TSB_FILL_MATCH\000"
	.align	2
.LC558:
	.ascii	"NUMBER_DTLB\000"
	.align	2
.LC559:
	.ascii	"REPLACEMENT_DTLB\000"
	.align	2
.LC560:
	.ascii	"WIRED_DTLB\000"
	.align	2
.LC561:
	.ascii	"MPL_DTLB_ACCESS_SET_0\000"
	.align	2
.LC562:
	.ascii	"MPL_DTLB_ACCESS_SET_1\000"
	.align	2
.LC563:
	.ascii	"MPL_DTLB_ACCESS_SET_2\000"
	.align	2
.LC564:
	.ascii	"MPL_DTLB_ACCESS_SET_3\000"
	.align	2
.LC565:
	.ascii	"MPL_DTLB_ACCESS\000"
	.align	2
.LC566:
	.ascii	"MPL_IDN_FIREWALL_SET_0\000"
	.align	2
.LC567:
	.ascii	"MPL_IDN_FIREWALL_SET_1\000"
	.align	2
.LC568:
	.ascii	"MPL_IDN_FIREWALL_SET_2\000"
	.align	2
.LC569:
	.ascii	"MPL_IDN_FIREWALL_SET_3\000"
	.align	2
.LC570:
	.ascii	"MPL_IDN_FIREWALL\000"
	.align	2
.LC571:
	.ascii	"IDN_DIRECTION_PROTECT\000"
	.align	2
.LC572:
	.ascii	"MPL_UDN_FIREWALL_SET_0\000"
	.align	2
.LC573:
	.ascii	"MPL_UDN_FIREWALL_SET_1\000"
	.align	2
.LC574:
	.ascii	"MPL_UDN_FIREWALL_SET_2\000"
	.align	2
.LC575:
	.ascii	"MPL_UDN_FIREWALL_SET_3\000"
	.align	2
.LC576:
	.ascii	"MPL_UDN_FIREWALL\000"
	.align	2
.LC577:
	.ascii	"UDN_DIRECTION_PROTECT\000"
	.align	2
.LC578:
	.ascii	"MPL_TILE_TIMER_SET_0\000"
	.align	2
.LC579:
	.ascii	"MPL_TILE_TIMER_SET_1\000"
	.align	2
.LC580:
	.ascii	"MPL_TILE_TIMER_SET_2\000"
	.align	2
.LC581:
	.ascii	"MPL_TILE_TIMER_SET_3\000"
	.align	2
.LC582:
	.ascii	"MPL_TILE_TIMER\000"
	.align	2
.LC583:
	.ascii	"TILE_TIMER_CONTROL\000"
	.align	2
.LC584:
	.ascii	"MPL_AUX_TILE_TIMER_SET_0\000"
	.align	2
.LC585:
	.ascii	"MPL_AUX_TILE_TIMER_SET_1\000"
	.align	2
.LC586:
	.ascii	"MPL_AUX_TILE_TIMER_SET_2\000"
	.align	2
.LC587:
	.ascii	"MPL_AUX_TILE_TIMER_SET_3\000"
	.align	2
.LC588:
	.ascii	"MPL_AUX_TILE_TIMER\000"
	.align	2
.LC589:
	.ascii	"AUX_TILE_TIMER_CONTROL\000"
	.align	2
.LC590:
	.ascii	"MPL_IDN_TIMER_SET_0\000"
	.align	2
.LC591:
	.ascii	"MPL_IDN_TIMER_SET_1\000"
	.align	2
.LC592:
	.ascii	"MPL_IDN_TIMER_SET_2\000"
	.align	2
.LC593:
	.ascii	"MPL_IDN_TIMER_SET_3\000"
	.align	2
.LC594:
	.ascii	"MPL_IDN_TIMER\000"
	.align	2
.LC595:
	.ascii	"IDN_DEADLOCK_COUNT\000"
	.align	2
.LC596:
	.ascii	"IDN_DEADLOCK_TIMEOUT\000"
	.align	2
.LC597:
	.ascii	"MPL_UDN_TIMER_SET_0\000"
	.align	2
.LC598:
	.ascii	"MPL_UDN_TIMER_SET_1\000"
	.align	2
.LC599:
	.ascii	"MPL_UDN_TIMER_SET_2\000"
	.align	2
.LC600:
	.ascii	"MPL_UDN_TIMER_SET_3\000"
	.align	2
.LC601:
	.ascii	"MPL_UDN_TIMER\000"
	.align	2
.LC602:
	.ascii	"UDN_DEADLOCK_COUNT\000"
	.align	2
.LC603:
	.ascii	"UDN_DEADLOCK_TIMEOUT\000"
	.align	2
.LC604:
	.ascii	"MPL_IDN_AVAIL_SET_0\000"
	.align	2
.LC605:
	.ascii	"MPL_IDN_AVAIL_SET_1\000"
	.align	2
.LC606:
	.ascii	"MPL_IDN_AVAIL_SET_2\000"
	.align	2
.LC607:
	.ascii	"MPL_IDN_AVAIL_SET_3\000"
	.align	2
.LC608:
	.ascii	"MPL_IDN_AVAIL\000"
	.align	2
.LC609:
	.ascii	"IDN_AVAIL_EN\000"
	.align	2
.LC610:
	.ascii	"MPL_UDN_AVAIL_SET_0\000"
	.align	2
.LC611:
	.ascii	"MPL_UDN_AVAIL_SET_1\000"
	.align	2
.LC612:
	.ascii	"MPL_UDN_AVAIL_SET_2\000"
	.align	2
.LC613:
	.ascii	"MPL_UDN_AVAIL_SET_3\000"
	.align	2
.LC614:
	.ascii	"MPL_UDN_AVAIL\000"
	.align	2
.LC615:
	.ascii	"UDN_AVAIL_EN\000"
	.align	2
.LC616:
	.ascii	"MPL_IPI_3_SET_0\000"
	.align	2
.LC617:
	.ascii	"MPL_IPI_3_SET_1\000"
	.align	2
.LC618:
	.ascii	"MPL_IPI_3_SET_2\000"
	.align	2
.LC619:
	.ascii	"MPL_IPI_3_SET_3\000"
	.align	2
.LC620:
	.ascii	"MPL_IPI_3\000"
	.align	2
.LC621:
	.ascii	"IPI_EVENT_3\000"
	.align	2
.LC622:
	.ascii	"IPI_EVENT_RESET_3\000"
	.align	2
.LC623:
	.ascii	"IPI_EVENT_SET_3\000"
	.align	2
.LC624:
	.ascii	"IPI_MASK_3\000"
	.align	2
.LC625:
	.ascii	"IPI_MASK_RESET_3\000"
	.align	2
.LC626:
	.ascii	"IPI_MASK_SET_3\000"
	.align	2
.LC627:
	.ascii	"MPL_IPI_2_SET_0\000"
	.align	2
.LC628:
	.ascii	"MPL_IPI_2_SET_1\000"
	.align	2
.LC629:
	.ascii	"MPL_IPI_2_SET_2\000"
	.align	2
.LC630:
	.ascii	"MPL_IPI_2_SET_3\000"
	.align	2
.LC631:
	.ascii	"MPL_IPI_2\000"
	.align	2
.LC632:
	.ascii	"IPI_EVENT_2\000"
	.align	2
.LC633:
	.ascii	"IPI_EVENT_RESET_2\000"
	.align	2
.LC634:
	.ascii	"IPI_EVENT_SET_2\000"
	.align	2
.LC635:
	.ascii	"IPI_MASK_2\000"
	.align	2
.LC636:
	.ascii	"IPI_MASK_RESET_2\000"
	.align	2
.LC637:
	.ascii	"IPI_MASK_SET_2\000"
	.align	2
.LC638:
	.ascii	"MPL_IPI_1_SET_0\000"
	.align	2
.LC639:
	.ascii	"MPL_IPI_1_SET_1\000"
	.align	2
.LC640:
	.ascii	"MPL_IPI_1_SET_2\000"
	.align	2
.LC641:
	.ascii	"MPL_IPI_1_SET_3\000"
	.align	2
.LC642:
	.ascii	"MPL_IPI_1\000"
	.align	2
.LC643:
	.ascii	"IPI_EVENT_1\000"
	.align	2
.LC644:
	.ascii	"IPI_EVENT_RESET_1\000"
	.align	2
.LC645:
	.ascii	"IPI_EVENT_SET_1\000"
	.align	2
.LC646:
	.ascii	"IPI_MASK_1\000"
	.align	2
.LC647:
	.ascii	"IPI_MASK_RESET_1\000"
	.align	2
.LC648:
	.ascii	"IPI_MASK_SET_1\000"
	.align	2
.LC649:
	.ascii	"MPL_IPI_0_SET_0\000"
	.align	2
.LC650:
	.ascii	"MPL_IPI_0_SET_1\000"
	.align	2
.LC651:
	.ascii	"MPL_IPI_0_SET_2\000"
	.align	2
.LC652:
	.ascii	"MPL_IPI_0_SET_3\000"
	.align	2
.LC653:
	.ascii	"MPL_IPI_0\000"
	.align	2
.LC654:
	.ascii	"IPI_EVENT_0\000"
	.align	2
.LC655:
	.ascii	"IPI_EVENT_RESET_0\000"
	.align	2
.LC656:
	.ascii	"IPI_EVENT_SET_0\000"
	.align	2
.LC657:
	.ascii	"IPI_MASK_0\000"
	.align	2
.LC658:
	.ascii	"IPI_MASK_RESET_0\000"
	.align	2
.LC659:
	.ascii	"IPI_MASK_SET_0\000"
	.align	2
.LC660:
	.ascii	"MPL_PERF_COUNT_SET_0\000"
	.align	2
.LC661:
	.ascii	"MPL_PERF_COUNT_SET_1\000"
	.align	2
.LC662:
	.ascii	"MPL_PERF_COUNT_SET_2\000"
	.align	2
.LC663:
	.ascii	"MPL_PERF_COUNT_SET_3\000"
	.align	2
.LC664:
	.ascii	"MPL_PERF_COUNT\000"
	.align	2
.LC665:
	.ascii	"PERF_COUNT_0\000"
	.align	2
.LC666:
	.ascii	"PERF_COUNT_1\000"
	.align	2
.LC667:
	.ascii	"PERF_COUNT_CTL\000"
	.align	2
.LC668:
	.ascii	"PERF_COUNT_DN_CTL\000"
	.align	2
.LC669:
	.ascii	"PERF_COUNT_STS\000"
	.align	2
.LC670:
	.ascii	"WATCH_MASK\000"
	.align	2
.LC671:
	.ascii	"WATCH_VAL\000"
	.align	2
.LC672:
	.ascii	"MPL_AUX_PERF_COUNT_SET_0\000"
	.align	2
.LC673:
	.ascii	"MPL_AUX_PERF_COUNT_SET_1\000"
	.align	2
.LC674:
	.ascii	"MPL_AUX_PERF_COUNT_SET_2\000"
	.align	2
.LC675:
	.ascii	"MPL_AUX_PERF_COUNT_SET_3\000"
	.align	2
.LC676:
	.ascii	"MPL_AUX_PERF_COUNT\000"
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	.word	.LC577
	.word	5632
	.word	.LC578
	.word	5633
	.word	.LC579
	.word	5634
	.word	.LC580
	.word	5635
	.word	.LC581
	.word	5636
	.word	.LC582
	.word	5637
	.word	.LC583
	.word	5888
	.word	.LC584
	.word	5889
	.word	.LC585
	.word	5890
	.word	.LC586
	.word	5891
	.word	.LC587
	.word	5892
	.word	.LC588
	.word	5893
	.word	.LC589
	.word	6144
	.word	.LC590
	.word	6145
	.word	.LC591
	.word	6146
	.word	.LC592
	.word	6147
	.word	.LC593
	.word	6148
	.word	.LC594
	.word	6149
	.word	.LC595
	.word	6150
	.word	.LC596
	.word	6400
	.word	.LC597
	.word	6401
	.word	.LC598
	.word	6402
	.word	.LC599
	.word	6403
	.word	.LC600
	.word	6404
	.word	.LC601
	.word	6405
	.word	.LC602
	.word	6406
	.word	.LC603
	.word	6656
	.word	.LC604
	.word	6657
	.word	.LC605
	.word	6658
	.word	.LC606
	.word	6659
	.word	.LC607
	.word	6660
	.word	.LC608
	.word	6661
	.word	.LC609
	.word	6912
	.word	.LC610
	.word	6913
	.word	.LC611
	.word	6914
	.word	.LC612
	.word	6915
	.word	.LC613
	.word	6916
	.word	.LC614
	.word	6917
	.word	.LC615
	.word	7168
	.word	.LC616
	.word	7169
	.word	.LC617
	.word	7170
	.word	.LC618
	.word	7171
	.word	.LC619
	.word	7172
	.word	.LC620
	.word	7173
	.word	.LC621
	.word	7174
	.word	.LC622
	.word	7175
	.word	.LC623
	.word	7176
	.word	.LC624
	.word	7177
	.word	.LC625
	.word	7178
	.word	.LC626
	.word	7424
	.word	.LC627
	.word	7425
	.word	.LC628
	.word	7426
	.word	.LC629
	.word	7427
	.word	.LC630
	.word	7428
	.word	.LC631
	.word	7429
	.word	.LC632
	.word	7430
	.word	.LC633
	.word	7431
	.word	.LC634
	.word	7432
	.word	.LC635
	.word	7433
	.word	.LC636
	.word	7434
	.word	.LC637
	.word	7680
	.word	.LC638
	.word	7681
	.word	.LC639
	.word	7682
	.word	.LC640
	.word	7683
	.word	.LC641
	.word	7684
	.word	.LC642
	.word	7685
	.word	.LC643
	.word	7686
	.word	.LC644
	.word	7687
	.word	.LC645
	.word	7688
	.word	.LC646
	.word	7689
	.word	.LC647
	.word	7690
	.word	.LC648
	.word	7936
	.word	.LC649
	.word	7937
	.word	.LC650
	.word	7938
	.word	.LC651
	.word	7939
	.word	.LC652
	.word	7940
	.word	.LC653
	.word	7941
	.word	.LC654
	.word	7942
	.word	.LC655
	.word	7943
	.word	.LC656
	.word	7944
	.word	.LC657
	.word	7945
	.word	.LC658
	.word	7946
	.word	.LC659
	.word	8192
	.word	.LC660
	.word	8193
	.word	.LC661
	.word	8194
	.word	.LC662
	.word	8195
	.word	.LC663
	.word	8196
	.word	.LC664
	.word	8197
	.word	.LC665
	.word	8198
	.word	.LC666
	.word	8199
	.word	.LC667
	.word	8200
	.word	.LC668
	.word	8201
	.word	.LC669
	.word	8202
	.word	.LC670
	.word	8203
	.word	.LC671
	.word	8448
	.word	.LC672
	.word	8449
	.word	.LC673
	.word	8450
	.word	.LC674
	.word	8451
	.word	.LC675
	.word	8452
	.word	.LC676
	.word	8453
	.word	.LC677
	.word	8454
	.word	.LC678
	.word	8455
	.word	.LC679
	.word	8456
	.word	.LC680
	.word	8704
	.word	.LC681
	.word	8705
	.word	.LC682
	.word	8706
	.word	.LC683
	.word	8707
	.word	.LC684
	.word	8708
	.word	.LC685
	.word	8709
	.word	.LC686
	.word	8710
	.word	.LC687
	.word	8711
	.word	.LC688
	.word	8712
	.word	.LC689
	.word	8713
	.word	.LC690
	.word	8714
	.word	.LC691
	.word	8715
	.word	.LC692
	.word	8716
	.word	.LC693
	.word	8717
	.word	.LC694
	.word	8832
	.word	.LC695
	.word	8833
	.word	.LC696
	.word	8834
	.word	.LC697
	.word	8835
	.word	.LC698
	.word	8836
	.word	.LC699
	.word	8837
	.word	.LC700
	.word	8960
	.word	.LC701
	.word	8961
	.word	.LC702
	.word	8962
	.word	.LC703
	.word	8963
	.word	.LC704
	.word	8964
	.word	.LC705
	.word	8965
	.word	.LC706
	.word	8966
	.word	.LC707
	.word	8967
	.word	.LC708
	.word	8968
	.word	.LC709
	.word	8969
	.word	.LC710
	.word	8970
	.word	.LC711
	.word	8971
	.word	.LC712
	.word	8972
	.word	.LC713
	.word	8973
	.word	.LC714
	.word	9088
	.word	.LC715
	.word	9089
	.word	.LC716
	.word	9090
	.word	.LC717
	.word	9091
	.word	.LC718
	.word	9092
	.word	.LC719
	.word	9093
	.word	.LC720
	.word	9216
	.word	.LC721
	.word	9217
	.word	.LC722
	.word	9218
	.word	.LC723
	.word	9219
	.word	.LC724
	.word	9220
	.word	.LC725
	.word	9221
	.word	.LC726
	.word	9222
	.word	.LC727
	.word	9223
	.word	.LC728
	.word	9224
	.word	.LC729
	.word	9225
	.word	.LC730
	.word	9226
	.word	.LC731
	.word	9227
	.word	.LC732
	.word	9228
	.word	.LC733
	.word	9229
	.word	.LC734
	.word	9344
	.word	.LC735
	.word	9345
	.word	.LC736
	.word	9346
	.word	.LC737
	.word	9347
	.word	.LC738
	.word	9348
	.word	.LC739
	.word	9349
	.word	.LC740
	.word	9472
	.word	.LC741
	.word	9473
	.word	.LC742
	.word	9474
	.word	.LC743
	.word	9475
	.word	.LC744
	.word	9476
	.word	.LC745
	.word	9477
	.word	.LC746
	.word	9478
	.word	.LC747
	.word	9479
	.word	.LC748
	.word	9480
	.word	.LC749
	.word	9481
	.word	.LC750
	.word	9482
	.word	.LC751
	.word	9483
	.word	.LC752
	.word	9484
	.word	.LC753
	.word	9485
	.word	.LC754
	.word	9600
	.word	.LC755
	.word	9601
	.word	.LC756
	.word	9602
	.word	.LC757
	.word	9603
	.word	.LC758
	.word	9604
	.word	.LC759
	.word	9605
	.word	.LC760
	.word	9728
	.word	.LC761
	.word	9729
	.word	.LC762
	.word	9730
	.word	.LC763
	.word	9731
	.word	.LC764
	.word	9732
	.word	.LC765
	.word	9733
	.word	.LC766
	.word	9734
	.word	.LC767
	.word	9735
	.word	.LC768
	.word	9736
	.word	.LC769
	.word	9737
	.word	.LC770
	.word	9738
	.word	.LC771
	.word	9739
	.word	.LC772
	.word	9740
	.word	.LC773
	.word	9741
	.word	.LC774
	.word	9742
	.word	.LC775
	.word	9743
	.word	.LC776
	.word	9744
	.word	.LC777
	.word	9745
	.word	.LC778
	.word	9746
	.word	.LC779
	.word	9747
	.word	.LC780
	.word	9748
	.word	.LC781
	.word	9749
	.word	.LC782
	.word	9750
	.word	.LC783
	.word	9751
	.word	.LC784
	.word	9752
	.word	.LC785
	.word	9753
	.word	.LC786
	.word	9754
	.word	.LC787
	.word	9755
	.word	.LC788
	.word	9756
	.word	.LC789
	.word	9757
	.word	.LC790
	.word	9758
	.word	.LC791
	.word	9759
	.word	.LC792
	.word	9760
	.word	.LC793
	.word	9761
	.word	.LC794
	.word	9762
	.word	.LC795
	.word	9763
	.word	.LC796
	.word	9764
	.word	.LC797
	.word	9765
	.word	.LC798
	.word	9856
	.word	.LC799
	.word	9857
	.word	.LC800
	.word	9984
	.word	.LC801
	.word	9985
	.word	.LC802
	.word	9986
	.word	.LC803
	.word	9987
	.word	.LC804
	.word	9988
	.word	.LC805
	.word	9989
	.word	.LC806
	.word	9990
	.word	.LC807
	.word	9991
	.word	.LC808
	.word	9992
	.word	.LC809
	.word	9993
	.word	.LC810
	.word	9994
	.word	.LC811
	.word	9995
	.word	.LC812
	.word	9996
	.word	.LC813
	.word	10112
	.word	.LC814
	.word	10113
	.word	.LC815
	.word	10114
	.word	.LC816
	.word	10115
	.word	.LC817
	.word	10116
	.word	.LC818
	.word	10117
	.word	.LC819
	.word	10118
	.word	.LC820
	.word	10119
	.word	.LC821
	.word	10240
	.word	.LC822
	.word	10241
	.word	.LC823
	.word	10242
	.word	.LC824
	.word	10243
	.word	.LC825
	.word	10244
	.word	.LC826
	.word	10245
	.word	.LC827
	.word	10496
	.word	.LC828
	.word	10497
	.word	.LC829
	.word	10498
	.word	.LC830
	.word	10499
	.word	.LC831
	.word	10500
	.word	.LC832
	.word	10501
	.word	.LC833
	.word	10752
	.word	.LC834
	.word	10753
	.word	.LC835
	.word	10754
	.word	.LC836
	.word	10755
	.word	.LC837
	.word	10756
	.word	.LC838
	.word	10757
	.word	.LC839
	.global	tilegx_num_sprs
	.align	2
	.type	tilegx_num_sprs, %object
	.size	tilegx_num_sprs, 4
tilegx_num_sprs:
	.word	441
	.align	2
.LC840:
	.word	__stack_chk_guard
	.text
	.align	2
	.global	get_tilegx_spr_name
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_tilegx_spr_name, %function
get_tilegx_spr_name:
	@ args = 0, pretend = 0, frame = 32
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #40
	str	r0, [fp, #-32]
	ldr	r3, .L168
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	mov	r3,#0
	ldr	r3, [fp, #-32]
	str	r3, [fp, #-16]
	ldr	r3, .L168+4
	mov	r2, r3
	sub	r0, fp, #16
	ldr	r3, .L168+8
	str	r3, [sp]
	mov	r3, #8
	ldr	r1, .L168+12
	bl	bsearch
	str	r0, [fp, #-24]
	ldr	r3, [fp, #-24]
	cmp	r3, #0
	bne	.L164
	mov	r3, #0
	b	.L166
.L164:
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-20]
	ldr	r3, [fp, #-20]
	ldr	r3, [r3, #4]
.L166:
	ldr	r2, .L168
	ldr	r1, [r2]
	ldr	r2, [fp, #-8]
	eors	r1, r2, r1
	mov	r2, #0
	beq	.L167
	bl	__stack_chk_fail
.L167:
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L169:
	.align	2
.L168:
	.word	.LC840
	.word	441
	.word	tilegx_spr_compare
	.word	tilegx_sprs
	.size	get_tilegx_spr_name, .-get_tilegx_spr_name
	.section	.rodata
	.align	2
.LC841:
	.ascii	"{ \000"
	.align	2
.LC842:
	.ascii	" ; \000"
	.align	2
.LC843:
	.ascii	"<invalid>\000"
	.align	2
.LC844:
	.ascii	"%s\000"
	.align	2
.LC845:
	.ascii	"%d\000"
	.align	2
.LC846:
	.ascii	"0x%016llx\000"
	.align	2
.LC847:
	.ascii	" }\000"
	.align	2
.LC848:
	.word	__stack_chk_guard
	.text
	.align	2
	.global	print_insn_tilegx
	.syntax unified
	.arm
	.fpu softvfp
	.type	print_insn_tilegx, %function
print_insn_tilegx:
	@ args = 0, pretend = 0, frame = 240
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #248
	str	r0, [fp, #-240]
	ldr	r3, .L197
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	mov	r3,#0
	ldr	r2, [fp, #-240]
	sub	r3, fp, #16
	mov	r1, r2
	mov	r2, #8
	mov	r0, r3
	bl	memcpy
	sub	r3, fp, #16
	ldmia	r3, {r0-r1}
	ldr	r3, [fp, #-240]
	mov	r2, r3
	asr	r3, r2, #31
	sub	ip, fp, #188
	str	ip, [sp]
	bl	parse_insn_tilegx
	str	r0, [fp, #-212]
	ldr	r0, .L197+4
	bl	printf
	mov	r3, #0
	str	r3, [fp, #-228]
	mov	r3, #101
	str	r3, [fp, #-224]
	mov	r3, #0
	str	r3, [fp, #-232]
	b	.L171
.L174:
	ldr	r2, [fp, #-232]
	mov	r3, r2
	lsl	r3, r3, #3
	sub	r3, r3, r2
	lsl	r3, r3, #3
	sub	r2, fp, #4
	add	r3, r2, r3
	sub	r3, r3, #184
	ldr	r3, [r3]
	ldrb	r3, [r3, #11]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L172
	mov	r3, #179
	str	r3, [fp, #-224]
	b	.L173
.L172:
	ldr	r3, [fp, #-232]
	add	r3, r3, #1
	str	r3, [fp, #-232]
.L171:
	ldr	r2, [fp, #-232]
	ldr	r3, [fp, #-212]
	cmp	r2, r3
	blt	.L174
.L173:
	mov	r3, #0
	str	r3, [fp, #-232]
	b	.L175
.L193:
	ldr	r2, [fp, #-232]
	mov	r3, r2
	lsl	r3, r3, #3
	sub	r3, r3, r2
	lsl	r3, r3, #3
	sub	r2, fp, #4
	add	r3, r2, r3
	sub	r3, r3, #184
	ldr	r3, [r3]
	str	r3, [fp, #-208]
	ldr	r3, [fp, #-208]
	ldr	r3, [r3, #4]
	ldr	r2, [fp, #-224]
	cmp	r2, r3
	bne	.L176
	ldr	r3, [fp, #-228]
	cmp	r3, #0
	bgt	.L196
	ldr	r3, [fp, #-232]
	add	r3, r3, #1
	ldr	r2, [fp, #-212]
	cmp	r2, r3
	bgt	.L196
.L176:
	ldr	r3, [fp, #-228]
	cmp	r3, #0
	ble	.L179
	ldr	r0, .L197+8
	bl	printf
.L179:
	ldr	r3, [fp, #-228]
	add	r3, r3, #1
	str	r3, [fp, #-228]
	ldr	r3, [fp, #-208]
	ldr	r3, [r3]
	str	r3, [fp, #-220]
	ldr	r3, [fp, #-220]
	cmp	r3, #0
	bne	.L180
	ldr	r3, .L197+12
	str	r3, [fp, #-220]
.L180:
	ldr	r1, [fp, #-220]
	ldr	r0, .L197+16
	bl	printf
	mov	r3, #0
	str	r3, [fp, #-216]
	b	.L181
.L192:
	ldr	r3, [fp, #-216]
	cmp	r3, #0
	ble	.L182
	mov	r0, #44
	bl	putchar
.L182:
	mov	r0, #32
	bl	putchar
	ldr	r2, [fp, #-232]
	mov	r3, r2
	lsl	r3, r3, #3
	sub	r3, r3, r2
	ldr	r2, [fp, #-216]
	add	r3, r3, r2
	add	r3, r3, #3
	lsl	r3, r3, #3
	sub	r2, fp, #4
	add	r3, r2, r3
	sub	r3, r3, #184
	ldmia	r3, {r2-r3}
	str	r2, [fp, #-196]
	str	r3, [fp, #-192]
	ldr	r2, [fp, #-232]
	mov	r3, r2
	lsl	r3, r3, #3
	sub	r3, r3, r2
	lsl	r3, r3, #1
	ldr	r2, [fp, #-216]
	add	r3, r3, r2
	lsl	r3, r3, #2
	sub	r2, fp, #4
	add	r3, r2, r3
	ldr	r3, [r3, #-180]
	str	r3, [fp, #-204]
	ldr	r3, [fp, #-204]
	ldr	r3, [r3]
	cmp	r3, #3
	ldrls	pc, [pc, r3, asl #2]
	b	.L183
.L185:
	.word	.L188
	.word	.L187
	.word	.L186
	.word	.L184
.L188:
	ldr	r3, [fp, #-196]
	ldr	r2, .L197+20
	ldr	r3, [r2, r3, lsl #2]
	mov	r1, r3
	ldr	r0, .L197+16
	bl	printf
	b	.L189
.L184:
	ldr	r3, [fp, #-196]
	mov	r0, r3
	bl	get_tilegx_spr_name
	str	r0, [fp, #-200]
	ldr	r3, [fp, #-200]
	cmp	r3, #0
	beq	.L190
	ldr	r1, [fp, #-200]
	ldr	r0, .L197+16
	bl	printf
	b	.L189
.L190:
	ldr	r3, [fp, #-196]
	mov	r1, r3
	ldr	r0, .L197+24
	bl	printf
	b	.L189
.L187:
	ldr	r3, [fp, #-196]
	mov	r1, r3
	ldr	r0, .L197+24
	bl	printf
	b	.L189
.L186:
	sub	r3, fp, #196
	ldmia	r3, {r2-r3}
	ldr	r0, .L197+28
	bl	printf
	b	.L189
.L183:
	bl	abort
.L189:
	ldr	r3, [fp, #-216]
	add	r3, r3, #1
	str	r3, [fp, #-216]
.L181:
	ldr	r3, [fp, #-208]
	ldrb	r3, [r3, #9]	@ zero_extendqisi2
	mov	r2, r3
	ldr	r3, [fp, #-216]
	cmp	r3, r2
	blt	.L192
	b	.L178
.L196:
	nop
.L178:
	ldr	r3, [fp, #-232]
	add	r3, r3, #1
	str	r3, [fp, #-232]
.L175:
	ldr	r2, [fp, #-232]
	ldr	r3, [fp, #-212]
	cmp	r2, r3
	blt	.L193
	ldr	r0, .L197+32
	bl	puts
	mov	r3, #8
	ldr	r2, .L197
	ldr	r1, [r2]
	ldr	r2, [fp, #-8]
	eors	r1, r2, r1
	mov	r2, #0
	beq	.L195
	bl	__stack_chk_fail
.L195:
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L198:
	.align	2
.L197:
	.word	.LC848
	.word	.LC841
	.word	.LC842
	.word	.LC843
	.word	.LC844
	.word	tilegx_register_names
	.word	.LC845
	.word	.LC846
	.word	.LC847
	.size	print_insn_tilegx, .-print_insn_tilegx
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
