	.file	"521167.c"
	.intel_syntax noprefix
	.text
	.type	RansDecInit_single, @function
RansDecInit_single:
.LFB6:
	.cfi_startproc
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	QWORD PTR -32[rbp], rsi
	mov	rax, QWORD PTR -32[rbp]
	mov	rax, QWORD PTR [rax]
	mov	QWORD PTR -8[rbp], rax
	mov	rax, QWORD PTR -8[rbp]
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	mov	DWORD PTR -12[rbp], eax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 1
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	eax, 8
	or	DWORD PTR -12[rbp], eax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 2
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	eax, 16
	or	DWORD PTR -12[rbp], eax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 3
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	eax, 24
	or	DWORD PTR -12[rbp], eax
	add	QWORD PTR -8[rbp], 4
	mov	rax, QWORD PTR -32[rbp]
	mov	rdx, QWORD PTR -8[rbp]
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -24[rbp]
	mov	edx, DWORD PTR -12[rbp]
	mov	DWORD PTR [rax], edx
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE6:
	.size	RansDecInit_single, .-RansDecInit_single
	.section	.rodata
.LC0:
	.string	"the_stack_data/521167.c"
.LC1:
	.string	"x < TOTFREQ"
	.text
	.globl	rans_uncompress_O0_32x16_NoSimd_single
	.type	rans_uncompress_O0_32x16_NoSimd_single, @function
rans_uncompress_O0_32x16_NoSimd_single:
.LFB7:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	lea	r11, -20480[rsp]
.LPSRL0:
	sub	rsp, 4096
	or	DWORD PTR [rsp], 0
	cmp	rsp, r11
	jne	.LPSRL0
	sub	rsp, 320
	mov	QWORD PTR -20776[rbp], rdi
	mov	DWORD PTR -20780[rbp], esi
	mov	QWORD PTR -20792[rbp], rdx
	mov	QWORD PTR -20800[rbp], rcx
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -8[rbp], rax
	xor	eax, eax
	mov	rax, QWORD PTR -20776[rbp]
	add	rax, 4
	mov	QWORD PTR -20704[rbp], rax
	mov	rax, QWORD PTR -20776[rbp]
	movzx	eax, BYTE PTR [rax]
	movzx	edx, al
	mov	rax, QWORD PTR -20776[rbp]
	add	rax, 1
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	eax, 8
	or	edx, eax
	mov	rax, QWORD PTR -20776[rbp]
	add	rax, 2
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	eax, 16
	or	edx, eax
	mov	rax, QWORD PTR -20776[rbp]
	add	rax, 3
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	eax, 24
	or	eax, edx
	mov	DWORD PTR -20724[rbp], eax
	cmp	QWORD PTR -20792[rbp], 0
	jne	.L3
	mov	eax, DWORD PTR -20724[rbp]
	cdqe
	mov	rdi, rax
	call	malloc@PLT
	mov	QWORD PTR -20792[rbp], rax
	mov	edx, DWORD PTR -20724[rbp]
	mov	rax, QWORD PTR -20800[rbp]
	mov	DWORD PTR [rax], edx
.L3:
	cmp	QWORD PTR -20792[rbp], 0
	je	.L4
	mov	eax, DWORD PTR -20724[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -20800[rbp]
	mov	eax, DWORD PTR [rax]
	mov	eax, eax
	cmp	rdx, rax
	jle	.L5
.L4:
	mov	eax, 0
	jmp	.L26
.L5:
	mov	DWORD PTR -20752[rbp], 0
	mov	eax, DWORD PTR -20752[rbp]
	mov	DWORD PTR -20756[rbp], eax
	mov	eax, DWORD PTR -20756[rbp]
	mov	DWORD PTR -20748[rbp], eax
	mov	rax, QWORD PTR -20704[rbp]
	lea	rdx, 1[rax]
	mov	QWORD PTR -20704[rbp], rdx
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	mov	DWORD PTR -20760[rbp], eax
.L13:
	mov	rax, QWORD PTR -20704[rbp]
	lea	rdx, 1[rax]
	mov	QWORD PTR -20704[rbp], rdx
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	mov	DWORD PTR -20744[rbp], eax
	cmp	DWORD PTR -20744[rbp], 127
	jle	.L7
	and	DWORD PTR -20744[rbp], -129
	mov	eax, DWORD PTR -20744[rbp]
	sal	eax, 8
	and	eax, 32512
	mov	ecx, eax
	mov	rax, QWORD PTR -20704[rbp]
	lea	rdx, 1[rax]
	mov	QWORD PTR -20704[rbp], rdx
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	or	eax, ecx
	mov	DWORD PTR -20744[rbp], eax
.L7:
	mov	eax, DWORD PTR -20756[rbp]
	mov	DWORD PTR -20720[rbp], eax
	mov	DWORD PTR -20752[rbp], 0
	jmp	.L8
.L9:
	mov	edx, DWORD PTR -20752[rbp]
	mov	eax, DWORD PTR -20720[rbp]
	add	eax, edx
	mov	edx, DWORD PTR -20760[rbp]
	cdqe
	mov	BYTE PTR -4176[rbp+rax], dl
	mov	eax, DWORD PTR -20744[rbp]
	sal	eax, 20
	mov	edx, eax
	mov	eax, DWORD PTR -20752[rbp]
	sal	eax, 8
	mov	esi, edx
	or	esi, eax
	mov	edx, DWORD PTR -20760[rbp]
	mov	ecx, DWORD PTR -20752[rbp]
	mov	eax, DWORD PTR -20720[rbp]
	add	eax, ecx
	or	edx, esi
	cdqe
	mov	DWORD PTR -20560[rbp+rax*4], edx
	add	DWORD PTR -20752[rbp], 1
.L8:
	mov	eax, DWORD PTR -20752[rbp]
	cmp	eax, DWORD PTR -20744[rbp]
	jl	.L9
	mov	eax, DWORD PTR -20744[rbp]
	add	DWORD PTR -20756[rbp], eax
	cmp	DWORD PTR -20748[rbp], 0
	jne	.L10
	mov	eax, DWORD PTR -20760[rbp]
	lea	edx, 1[rax]
	mov	rax, QWORD PTR -20704[rbp]
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	cmp	edx, eax
	jne	.L10
	mov	rax, QWORD PTR -20704[rbp]
	lea	rdx, 1[rax]
	mov	QWORD PTR -20704[rbp], rdx
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	mov	DWORD PTR -20760[rbp], eax
	mov	rax, QWORD PTR -20704[rbp]
	lea	rdx, 1[rax]
	mov	QWORD PTR -20704[rbp], rdx
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	mov	DWORD PTR -20748[rbp], eax
	jmp	.L11
.L10:
	cmp	DWORD PTR -20748[rbp], 0
	je	.L12
	sub	DWORD PTR -20748[rbp], 1
	add	DWORD PTR -20760[rbp], 1
	jmp	.L11
.L12:
	mov	rax, QWORD PTR -20704[rbp]
	lea	rdx, 1[rax]
	mov	QWORD PTR -20704[rbp], rdx
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	mov	DWORD PTR -20760[rbp], eax
.L11:
	cmp	DWORD PTR -20760[rbp], 0
	jne	.L13
	cmp	DWORD PTR -20756[rbp], 4095
	jle	.L14
	lea	rcx, __PRETTY_FUNCTION__.0[rip]
	mov	edx, 84
	lea	rsi, .LC0[rip]
	lea	rdi, .LC1[rip]
	call	__assert_fail@PLT
.L14:
	mov	DWORD PTR -20740[rbp], 0
	jmp	.L15
.L16:
	lea	rdx, -20688[rbp]
	mov	eax, DWORD PTR -20740[rbp]
	cdqe
	sal	rax, 2
	add	rdx, rax
	lea	rax, -20704[rbp]
	mov	rsi, rax
	mov	rdi, rdx
	call	RansDecInit_single
	add	DWORD PTR -20740[rbp], 1
.L15:
	cmp	DWORD PTR -20740[rbp], 31
	jle	.L16
	mov	eax, DWORD PTR -20724[rbp]
	and	eax, -32
	mov	DWORD PTR -20716[rbp], eax
	mov	DWORD PTR -20712[rbp], 4095
	mov	rax, QWORD PTR -20704[rbp]
	mov	QWORD PTR -20696[rbp], rax
	mov	DWORD PTR -20736[rbp], 0
	jmp	.L17
.L23:
	mov	DWORD PTR -20732[rbp], 0
	jmp	.L18
.L19:
	mov	eax, DWORD PTR -20732[rbp]
	cdqe
	mov	eax, DWORD PTR -20688[rbp+rax*4]
	and	eax, DWORD PTR -20712[rbp]
	mov	eax, eax
	mov	eax, DWORD PTR -20560[rbp+rax*4]
	mov	DWORD PTR -20708[rbp], eax
	mov	eax, DWORD PTR -20708[rbp]
	shr	eax, 20
	mov	edx, eax
	mov	eax, DWORD PTR -20732[rbp]
	cdqe
	mov	eax, DWORD PTR -20688[rbp+rax*4]
	shr	eax, 12
	imul	edx, eax
	mov	eax, DWORD PTR -20708[rbp]
	shr	eax, 8
	and	eax, DWORD PTR -20712[rbp]
	add	edx, eax
	mov	eax, DWORD PTR -20732[rbp]
	cdqe
	mov	DWORD PTR -20688[rbp+rax*4], edx
	mov	edx, DWORD PTR -20736[rbp]
	mov	eax, DWORD PTR -20732[rbp]
	add	eax, edx
	movsx	rdx, eax
	mov	rax, QWORD PTR -20792[rbp]
	add	rax, rdx
	mov	edx, DWORD PTR -20708[rbp]
	mov	BYTE PTR [rax], dl
	add	DWORD PTR -20732[rbp], 1
.L18:
	cmp	DWORD PTR -20732[rbp], 31
	jle	.L19
	mov	DWORD PTR -20728[rbp], 0
	jmp	.L20
.L22:
	mov	eax, DWORD PTR -20728[rbp]
	cdqe
	mov	eax, DWORD PTR -20688[rbp+rax*4]
	cmp	eax, 32767
	ja	.L21
	mov	eax, DWORD PTR -20728[rbp]
	cdqe
	mov	eax, DWORD PTR -20688[rbp+rax*4]
	sal	eax, 16
	mov	ecx, eax
	mov	rax, QWORD PTR -20696[rbp]
	lea	rdx, 2[rax]
	mov	QWORD PTR -20696[rbp], rdx
	movzx	eax, WORD PTR [rax]
	movzx	eax, ax
	or	ecx, eax
	mov	edx, ecx
	mov	eax, DWORD PTR -20728[rbp]
	cdqe
	mov	DWORD PTR -20688[rbp+rax*4], edx
.L21:
	add	DWORD PTR -20728[rbp], 1
.L20:
	cmp	DWORD PTR -20728[rbp], 31
	jle	.L22
	add	DWORD PTR -20736[rbp], 32
.L17:
	mov	eax, DWORD PTR -20736[rbp]
	cmp	eax, DWORD PTR -20716[rbp]
	jl	.L23
	mov	eax, DWORD PTR -20724[rbp]
	and	eax, 31
	mov	DWORD PTR -20740[rbp], eax
	jmp	.L24
.L25:
	mov	eax, DWORD PTR -20740[rbp]
	cdqe
	mov	eax, DWORD PTR -20688[rbp+rax*4]
	and	eax, DWORD PTR -20712[rbp]
	mov	ecx, eax
	mov	edx, DWORD PTR -20716[rbp]
	mov	eax, DWORD PTR -20740[rbp]
	add	eax, edx
	movsx	rdx, eax
	mov	rax, QWORD PTR -20792[rbp]
	add	rdx, rax
	mov	eax, ecx
	movzx	eax, BYTE PTR -4176[rbp+rax]
	mov	BYTE PTR [rdx], al
.L24:
	mov	eax, DWORD PTR -20740[rbp]
	lea	edx, -1[rax]
	mov	DWORD PTR -20740[rbp], edx
	test	eax, eax
	jg	.L25
	mov	edx, DWORD PTR -20724[rbp]
	mov	rax, QWORD PTR -20800[rbp]
	mov	DWORD PTR [rax], edx
	mov	rax, QWORD PTR -20792[rbp]
.L26:
	mov	rdi, QWORD PTR -8[rbp]
	sub	rdi, QWORD PTR fs:40
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE7:
	.size	rans_uncompress_O0_32x16_NoSimd_single, .-rans_uncompress_O0_32x16_NoSimd_single
	.section	.rodata
	.align 32
	.type	__PRETTY_FUNCTION__.0, @object
	.size	__PRETTY_FUNCTION__.0, 39
__PRETTY_FUNCTION__.0:
	.string	"rans_uncompress_O0_32x16_NoSimd_single"
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"521167.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	RansDecInit_single, %function
RansDecInit_single:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	ldr	r3, [fp, #-20]
	ldr	r3, [r3]
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-12]
	ldrb	r3, [r3]	@ zero_extendqisi2
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-12]
	add	r3, r3, #1
	ldrb	r3, [r3]	@ zero_extendqisi2
	lsl	r3, r3, #8
	mov	r2, r3
	ldr	r3, [fp, #-8]
	orr	r3, r3, r2
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-12]
	add	r3, r3, #2
	ldrb	r3, [r3]	@ zero_extendqisi2
	lsl	r3, r3, #16
	mov	r2, r3
	ldr	r3, [fp, #-8]
	orr	r3, r3, r2
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-12]
	add	r3, r3, #3
	ldrb	r3, [r3]	@ zero_extendqisi2
	lsl	r3, r3, #24
	mov	r2, r3
	ldr	r3, [fp, #-8]
	orr	r3, r3, r2
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-12]
	add	r3, r3, #4
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-20]
	ldr	r2, [fp, #-12]
	str	r2, [r3]
	ldr	r3, [fp, #-16]
	ldr	r2, [fp, #-8]
	str	r2, [r3]
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	RansDecInit_single, .-RansDecInit_single
	.section	.rodata
	.align	2
.LC0:
	.ascii	"the_stack_data/521167.c\000"
	.align	2
.LC1:
	.ascii	"x < TOTFREQ\000"
	.align	2
.LC2:
	.word	__stack_chk_guard
	.text
	.align	2
	.global	rans_uncompress_O0_32x16_NoSimd_single
	.syntax unified
	.arm
	.fpu softvfp
	.type	rans_uncompress_O0_32x16_NoSimd_single, %function
rans_uncompress_O0_32x16_NoSimd_single:
	@ args = 0, pretend = 0, frame = 20760
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, fp, lr}
	add	fp, sp, #8
	sub	sp, sp, #20736
	sub	sp, sp, #28
	sub	ip, fp, #20480
	sub	ip, ip, #12
	str	r0, [ip, #-268]
	sub	r0, fp, #20480
	sub	r0, r0, #12
	str	r1, [r0, #-272]
	sub	r1, fp, #20480
	sub	r1, r1, #12
	str	r2, [r1, #-276]
	sub	r2, fp, #20480
	sub	r2, r2, #12
	str	r3, [r2, #-280]
	ldr	r3, .L28
	ldr	r3, [r3]
	str	r3, [fp, #-16]
	mov	r3,#0
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-268]
	add	r3, r3, #4
	sub	r2, fp, #20480
	sub	r2, r2, #12
	str	r3, [r2, #-260]
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-268]
	ldrb	r3, [r3]	@ zero_extendqisi2
	mov	r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-268]
	add	r3, r3, #1
	ldrb	r3, [r3]	@ zero_extendqisi2
	lsl	r3, r3, #8
	orr	r2, r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-268]
	add	r3, r3, #2
	ldrb	r3, [r3]	@ zero_extendqisi2
	lsl	r3, r3, #16
	orr	r2, r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-268]
	add	r3, r3, #3
	ldrb	r3, [r3]	@ zero_extendqisi2
	lsl	r3, r3, #24
	sub	r1, fp, #20480
	sub	r1, r1, #12
	orr	r3, r2, r3
	str	r3, [r1, #-216]
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-276]
	cmp	r3, #0
	bne	.L3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-216]
	sub	r2, fp, #20480
	sub	r2, r2, #12
	mov	r4, r2
	mov	r0, r3
	bl	malloc
	mov	r3, r0
	str	r3, [r4, #-276]
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r2, [r3, #-216]
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-280]
	str	r2, [r3]
.L3:
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-276]
	cmp	r3, #0
	beq	.L4
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-216]
	mov	r2, r3
	asr	r3, r2, #31
	sub	r1, fp, #20480
	sub	r1, r1, #12
	ldr	r1, [r1, #-280]
	ldr	r1, [r1]
	mov	r0, r1
	mov	r1, #0
	cmp	r0, r2
	sbcs	r3, r1, r3
	bge	.L5
.L4:
	mov	r3, #0
	b	.L26
.L5:
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-248]
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-248]
	str	r3, [r2, #-252]
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-252]
	str	r3, [r2, #-244]
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-260]
	add	r2, r3, #1
	sub	r1, fp, #20480
	sub	r1, r1, #12
	str	r2, [r1, #-260]
	ldrb	r3, [r3]	@ zero_extendqisi2
	sub	r2, fp, #20480
	sub	r2, r2, #12
	str	r3, [r2, #-256]
.L13:
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-260]
	add	r2, r3, #1
	sub	r1, fp, #20480
	sub	r1, r1, #12
	str	r2, [r1, #-260]
	ldrb	r3, [r3]	@ zero_extendqisi2
	sub	r2, fp, #20480
	sub	r2, r2, #12
	str	r3, [r2, #-240]
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-240]
	cmp	r3, #127
	ble	.L7
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-240]
	bic	r3, r3, #128
	str	r3, [r2, #-240]
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-240]
	lsl	r3, r3, #8
	and	r2, r3, #32512
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-260]
	add	r1, r3, #1
	sub	r0, fp, #20480
	sub	r0, r0, #12
	str	r1, [r0, #-260]
	ldrb	r3, [r3]	@ zero_extendqisi2
	sub	r1, fp, #20480
	sub	r1, r1, #12
	orr	r3, r2, r3
	str	r3, [r1, #-240]
.L7:
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-252]
	str	r3, [r2, #-212]
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-248]
	b	.L8
.L9:
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r2, [r2, #-248]
	ldr	r3, [r3, #-212]
	add	r3, r2, r3
	sub	r2, fp, #20480
	sub	r2, r2, #12
	ldr	r2, [r2, #-256]
	and	r2, r2, #255
	sub	r1, fp, #4096
	sub	r1, r1, #12
	add	r3, r1, r3
	strb	r2, [r3, #-68]
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-240]
	lsl	r3, r3, #20
	sub	r2, fp, #20480
	sub	r2, r2, #12
	ldr	r2, [r2, #-248]
	lsl	r2, r2, #8
	orr	r1, r3, r2
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r2, [r3, #-256]
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r0, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r0, [r0, #-248]
	ldr	r3, [r3, #-212]
	add	r3, r0, r3
	orr	r2, r1, r2
	sub	r1, fp, #20480
	sub	r1, r1, #12
	lsl	r3, r3, #2
	add	r3, r1, r3
	str	r2, [r3, #-68]
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-248]
	add	r3, r3, #1
	str	r3, [r2, #-248]
.L8:
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r2, [r2, #-248]
	ldr	r3, [r3, #-240]
	cmp	r2, r3
	blt	.L9
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r1, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r2, [r2, #-252]
	ldr	r3, [r3, #-240]
	add	r3, r2, r3
	str	r3, [r1, #-252]
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-244]
	cmp	r3, #0
	bne	.L10
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-256]
	add	r3, r3, #1
	sub	r2, fp, #20480
	sub	r2, r2, #12
	ldr	r2, [r2, #-260]
	ldrb	r2, [r2]	@ zero_extendqisi2
	cmp	r3, r2
	bne	.L10
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-260]
	add	r2, r3, #1
	sub	r1, fp, #20480
	sub	r1, r1, #12
	str	r2, [r1, #-260]
	ldrb	r3, [r3]	@ zero_extendqisi2
	sub	r2, fp, #20480
	sub	r2, r2, #12
	str	r3, [r2, #-256]
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-260]
	add	r2, r3, #1
	sub	r1, fp, #20480
	sub	r1, r1, #12
	str	r2, [r1, #-260]
	ldrb	r3, [r3]	@ zero_extendqisi2
	sub	r2, fp, #20480
	sub	r2, r2, #12
	str	r3, [r2, #-244]
	b	.L11
.L10:
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-244]
	cmp	r3, #0
	beq	.L12
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-244]
	sub	r3, r3, #1
	str	r3, [r2, #-244]
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-256]
	add	r3, r3, #1
	str	r3, [r2, #-256]
	b	.L11
.L12:
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-260]
	add	r2, r3, #1
	sub	r1, fp, #20480
	sub	r1, r1, #12
	str	r2, [r1, #-260]
	ldrb	r3, [r3]	@ zero_extendqisi2
	sub	r2, fp, #20480
	sub	r2, r2, #12
	str	r3, [r2, #-256]
.L11:
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-256]
	cmp	r3, #0
	bne	.L13
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-252]
	cmp	r3, #4096
	blt	.L14
	ldr	r3, .L28+4
	mov	r2, #84
	ldr	r1, .L28+8
	ldr	r0, .L28+12
	bl	__assert_fail
.L14:
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-236]
	b	.L15
.L16:
	sub	r3, fp, #20480
	sub	r3, r3, #12
	sub	r3, r3, #196
	sub	r2, fp, #20480
	sub	r2, r2, #12
	ldr	r2, [r2, #-236]
	lsl	r2, r2, #2
	add	r2, r3, r2
	sub	r3, fp, #20736
	sub	r3, r3, #12
	sub	r3, r3, #4
	mov	r1, r3
	mov	r0, r2
	bl	RansDecInit_single
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-236]
	add	r3, r3, #1
	str	r3, [r2, #-236]
.L15:
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-236]
	cmp	r3, #31
	ble	.L16
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-216]
	bic	r3, r3, #31
	str	r3, [r2, #-208]
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	ldr	r3, .L28+16
	str	r3, [r2, #-204]
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-260]
	str	r3, [r2, #-232]
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-228]
	b	.L17
.L23:
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-224]
	b	.L18
.L19:
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-224]
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r2, [r3, #-196]
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-204]
	and	r3, r3, r2
	sub	r2, fp, #20480
	sub	r2, r2, #12
	sub	r1, fp, #20480
	sub	r1, r1, #12
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r3, [r3, #-68]
	str	r3, [r2, #-200]
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-200]
	lsr	r2, r3, #20
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r1, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-224]
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r3, [r3, #-196]
	lsr	r3, r3, #12
	mul	r2, r3, r2
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-200]
	lsr	r1, r3, #8
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-204]
	and	r3, r3, r1
	add	r2, r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r1, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-224]
	lsl	r3, r3, #2
	add	r3, r1, r3
	str	r2, [r3, #-196]
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r2, [r2, #-228]
	ldr	r3, [r3, #-224]
	add	r3, r2, r3
	mov	r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-276]
	add	r3, r3, r2
	sub	r2, fp, #20480
	sub	r2, r2, #12
	ldr	r2, [r2, #-200]
	and	r2, r2, #255
	strb	r2, [r3]
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-224]
	add	r3, r3, #1
	str	r3, [r2, #-224]
.L18:
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-224]
	cmp	r3, #31
	ble	.L19
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-220]
	b	.L20
.L22:
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-220]
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r3, [r3, #-196]
	cmp	r3, #32768
	bcs	.L21
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-220]
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r3, [r3, #-196]
	lsl	r2, r3, #16
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-232]
	sub	r1, fp, #20480
	sub	r1, r1, #12
	mov	r0, r1
	add	r1, r3, #2
	str	r1, [r0, #-232]
	ldrh	r3, [r3]
	orr	r2, r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r1, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-220]
	lsl	r3, r3, #2
	add	r3, r1, r3
	str	r2, [r3, #-196]
.L21:
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-220]
	add	r3, r3, #1
	str	r3, [r2, #-220]
.L20:
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-220]
	cmp	r3, #31
	ble	.L22
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-228]
	add	r3, r3, #32
	str	r3, [r2, #-228]
.L17:
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r2, [r2, #-228]
	ldr	r3, [r3, #-208]
	cmp	r2, r3
	blt	.L23
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-216]
	and	r3, r3, #31
	str	r3, [r2, #-236]
	b	.L24
.L25:
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-236]
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r2, [r3, #-196]
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-204]
	and	r2, r2, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	mov	r1, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r1, [r1, #-208]
	ldr	r3, [r3, #-236]
	add	r3, r1, r3
	mov	r1, r3
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-276]
	add	r3, r3, r1
	sub	r1, fp, #4096
	sub	r1, r1, #12
	add	r2, r1, r2
	ldrb	r2, [r2, #-68]	@ zero_extendqisi2
	strb	r2, [r3]
.L24:
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-236]
	sub	r2, fp, #20480
	sub	r2, r2, #12
	mov	r1, r2
	sub	r2, r3, #1
	str	r2, [r1, #-236]
	cmp	r3, #0
	bgt	.L25
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r2, [r3, #-216]
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-280]
	str	r2, [r3]
	sub	r3, fp, #20480
	sub	r3, r3, #12
	ldr	r3, [r3, #-276]
.L26:
	ldr	r2, .L28
	ldr	r1, [r2]
	ldr	r2, [fp, #-16]
	eors	r1, r2, r1
	mov	r2, #0
	beq	.L27
	bl	__stack_chk_fail
.L27:
	mov	r0, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, fp, pc}
.L29:
	.align	2
.L28:
	.word	.LC2
	.word	__PRETTY_FUNCTION__.5362
	.word	.LC0
	.word	.LC1
	.word	4095
	.size	rans_uncompress_O0_32x16_NoSimd_single, .-rans_uncompress_O0_32x16_NoSimd_single
	.section	.rodata
	.align	2
	.type	__PRETTY_FUNCTION__.5362, %object
	.size	__PRETTY_FUNCTION__.5362, 39
__PRETTY_FUNCTION__.5362:
	.ascii	"rans_uncompress_O0_32x16_NoSimd_single\000"
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
