	.file	"208490.c"
	.intel_syntax noprefix
	.text
	.globl	__VERIFIER_nondet_bool
	.type	__VERIFIER_nondet_bool, @function
__VERIFIER_nondet_bool:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	call	__VERIFIER_nondet_int@PLT
	test	eax, eax
	setne	al
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.globl	pc2_l2
	.bss
	.type	pc2_l2, @object
	.size	pc2_l2, 1
pc2_l2:
	.zero	1
	.globl	_x_pc2_l2
	.type	_x_pc2_l2, @object
	.size	_x_pc2_l2, 1
_x_pc2_l2:
	.zero	1
	.globl	pc2_l1
	.type	pc2_l1, @object
	.size	pc2_l1, 1
pc2_l1:
	.zero	1
	.globl	_x_pc2_l1
	.type	_x_pc2_l1, @object
	.size	_x_pc2_l1, 1
_x_pc2_l1:
	.zero	1
	.globl	a1_evt1
	.type	a1_evt1, @object
	.size	a1_evt1, 1
a1_evt1:
	.zero	1
	.globl	_x_a1_evt1
	.type	_x_a1_evt1, @object
	.size	_x_a1_evt1, 1
_x_a1_evt1:
	.zero	1
	.globl	a2_l
	.type	a2_l, @object
	.size	a2_l, 1
a2_l:
	.zero	1
	.globl	_x_a2_l
	.type	_x_a2_l, @object
	.size	_x_a2_l, 1
_x_a2_l:
	.zero	1
	.globl	a1_evt0
	.type	a1_evt0, @object
	.size	a1_evt0, 1
a1_evt0:
	.zero	1
	.globl	_x_a1_evt0
	.type	_x_a1_evt0, @object
	.size	_x_a1_evt0, 1
_x_a1_evt0:
	.zero	1
	.globl	pc1_l0
	.type	pc1_l0, @object
	.size	pc1_l0, 1
pc1_l0:
	.zero	1
	.globl	_x_pc1_l0
	.type	_x_pc1_l0, @object
	.size	_x_pc1_l0, 1
_x_pc1_l0:
	.zero	1
	.globl	a0_evt1
	.type	a0_evt1, @object
	.size	a0_evt1, 1
a0_evt1:
	.zero	1
	.globl	_x_a0_evt1
	.type	_x_a0_evt1, @object
	.size	_x_a0_evt1, 1
_x_a0_evt1:
	.zero	1
	.globl	pc2_l0
	.type	pc2_l0, @object
	.size	pc2_l0, 1
pc2_l0:
	.zero	1
	.globl	_x_pc2_l0
	.type	_x_pc2_l0, @object
	.size	_x_pc2_l0, 1
_x_pc2_l0:
	.zero	1
	.globl	pc2_evt1
	.type	pc2_evt1, @object
	.size	pc2_evt1, 1
pc2_evt1:
	.zero	1
	.globl	_x_pc2_evt1
	.type	_x_pc2_evt1, @object
	.size	_x_pc2_evt1, 1
_x_pc2_evt1:
	.zero	1
	.globl	a0_evt0
	.type	a0_evt0, @object
	.size	a0_evt0, 1
a0_evt0:
	.zero	1
	.globl	_x_a0_evt0
	.type	_x_a0_evt0, @object
	.size	_x_a0_evt0, 1
_x_a0_evt0:
	.zero	1
	.globl	a1_l
	.type	a1_l, @object
	.size	a1_l, 1
a1_l:
	.zero	1
	.globl	_x_a1_l
	.type	_x_a1_l, @object
	.size	_x_a1_l, 1
_x_a1_l:
	.zero	1
	.globl	delta
	.align 4
	.type	delta, @object
	.size	delta, 4
delta:
	.zero	4
	.globl	_x_delta
	.align 4
	.type	_x_delta, @object
	.size	_x_delta, 4
_x_delta:
	.zero	4
	.globl	pc0_l2
	.type	pc0_l2, @object
	.size	pc0_l2, 1
pc0_l2:
	.zero	1
	.globl	_x_pc0_l2
	.type	_x_pc0_l2, @object
	.size	_x_pc0_l2, 1
_x_pc0_l2:
	.zero	1
	.globl	pc2_evt0
	.type	pc2_evt0, @object
	.size	pc2_evt0, 1
pc2_evt0:
	.zero	1
	.globl	_x_pc2_evt0
	.type	_x_pc2_evt0, @object
	.size	_x_pc2_evt0, 1
_x_pc2_evt0:
	.zero	1
	.globl	pc1_x
	.align 4
	.type	pc1_x, @object
	.size	pc1_x, 4
pc1_x:
	.zero	4
	.globl	_x_pc1_x
	.align 4
	.type	_x_pc1_x, @object
	.size	_x_pc1_x, 4
_x_pc1_x:
	.zero	4
	.globl	pc0_x
	.align 4
	.type	pc0_x, @object
	.size	pc0_x, 4
pc0_x:
	.zero	4
	.globl	_x_pc0_x
	.align 4
	.type	_x_pc0_x, @object
	.size	_x_pc0_x, 4
_x_pc0_x:
	.zero	4
	.globl	c_initial
	.type	c_initial, @object
	.size	c_initial, 1
c_initial:
	.zero	1
	.globl	_x_c_initial
	.type	_x_c_initial, @object
	.size	_x_c_initial, 1
_x_c_initial:
	.zero	1
	.globl	pc0_evt0
	.type	pc0_evt0, @object
	.size	pc0_evt0, 1
pc0_evt0:
	.zero	1
	.globl	_x_pc0_evt0
	.type	_x_pc0_evt0, @object
	.size	_x_pc0_evt0, 1
_x_pc0_evt0:
	.zero	1
	.globl	pc0_evt1
	.type	pc0_evt1, @object
	.size	pc0_evt1, 1
pc0_evt1:
	.zero	1
	.globl	_x_pc0_evt1
	.type	_x_pc0_evt1, @object
	.size	_x_pc0_evt1, 1
_x_pc0_evt1:
	.zero	1
	.globl	pc0_l1
	.type	pc0_l1, @object
	.size	pc0_l1, 1
pc0_l1:
	.zero	1
	.globl	_x_pc0_l1
	.type	_x_pc0_l1, @object
	.size	_x_pc0_l1, 1
_x_pc0_l1:
	.zero	1
	.globl	a0_l
	.type	a0_l, @object
	.size	a0_l, 1
a0_l:
	.zero	1
	.globl	_x_a0_l
	.type	_x_a0_l, @object
	.size	_x_a0_l, 1
_x_a0_l:
	.zero	1
	.globl	id
	.align 4
	.type	id, @object
	.size	id, 4
id:
	.zero	4
	.globl	_x_id
	.align 4
	.type	_x_id, @object
	.size	_x_id, 4
_x_id:
	.zero	4
	.globl	pc1_evt0
	.type	pc1_evt0, @object
	.size	pc1_evt0, 1
pc1_evt0:
	.zero	1
	.globl	_x_pc1_evt0
	.type	_x_pc1_evt0, @object
	.size	_x_pc1_evt0, 1
_x_pc1_evt0:
	.zero	1
	.globl	c_move
	.type	c_move, @object
	.size	c_move, 1
c_move:
	.zero	1
	.globl	_x_c_move
	.type	_x_c_move, @object
	.size	_x_c_move, 1
_x_c_move:
	.zero	1
	.globl	pc1_evt1
	.type	pc1_evt1, @object
	.size	pc1_evt1, 1
pc1_evt1:
	.zero	1
	.globl	_x_pc1_evt1
	.type	_x_pc1_evt1, @object
	.size	_x_pc1_evt1, 1
_x_pc1_evt1:
	.zero	1
	.globl	a2_evt0
	.type	a2_evt0, @object
	.size	a2_evt0, 1
a2_evt0:
	.zero	1
	.globl	_x_a2_evt0
	.type	_x_a2_evt0, @object
	.size	_x_a2_evt0, 1
_x_a2_evt0:
	.zero	1
	.globl	pc1_l1
	.type	pc1_l1, @object
	.size	pc1_l1, 1
pc1_l1:
	.zero	1
	.globl	_x_pc1_l1
	.type	_x_pc1_l1, @object
	.size	_x_pc1_l1, 1
_x_pc1_l1:
	.zero	1
	.globl	a2_evt1
	.type	a2_evt1, @object
	.size	a2_evt1, 1
a2_evt1:
	.zero	1
	.globl	_x_a2_evt1
	.type	_x_a2_evt1, @object
	.size	_x_a2_evt1, 1
_x_a2_evt1:
	.zero	1
	.globl	pc0_l0
	.type	pc0_l0, @object
	.size	pc0_l0, 1
pc0_l0:
	.zero	1
	.globl	_x_pc0_l0
	.type	_x_pc0_l0, @object
	.size	_x_pc0_l0, 1
_x_pc0_l0:
	.zero	1
	.globl	pc1_l2
	.type	pc1_l2, @object
	.size	pc1_l2, 1
pc1_l2:
	.zero	1
	.globl	_x_pc1_l2
	.type	_x_pc1_l2, @object
	.size	_x_pc1_l2, 1
_x_pc1_l2:
	.zero	1
	.globl	_diverge_delta
	.align 4
	.type	_diverge_delta, @object
	.size	_diverge_delta, 4
_diverge_delta:
	.zero	4
	.globl	_x__diverge_delta
	.align 4
	.type	_x__diverge_delta, @object
	.size	_x__diverge_delta, 4
_x__diverge_delta:
	.zero	4
	.globl	pc2_x
	.align 4
	.type	pc2_x, @object
	.size	pc2_x, 4
pc2_x:
	.zero	4
	.globl	_x_pc2_x
	.align 4
	.type	_x_pc2_x, @object
	.size	_x_pc2_x, 4
_x_pc2_x:
	.zero	4
	.text
	.globl	main
	.type	main, @function
main:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR pc2_l2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR pc2_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR a1_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR a2_l[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR a1_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR pc1_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR a0_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR pc2_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR pc2_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR a0_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR a1_l[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR pc0_l2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR pc2_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR pc1_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR pc0_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR c_initial[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR pc0_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR pc0_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR pc0_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR a0_l[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR id[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR pc1_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR c_move[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR pc1_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR a2_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR pc1_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR a2_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR pc0_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR pc1_l2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _diverge_delta[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR pc2_x[rip], eax
	movzx	eax, BYTE PTR pc2_l2[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR pc2_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR pc2_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR pc2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR pc2_evt0[rip]
	test	al, al
	jne	.L6
	movzx	eax, BYTE PTR pc2_evt1[rip]
	test	al, al
	je	.L7
.L6:
	movzx	eax, BYTE PTR pc2_evt1[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR pc2_evt0[rip]
	test	al, al
	je	.L7
.L8:
	movzx	eax, BYTE PTR pc2_evt0[rip]
	test	al, al
	je	.L9
	movzx	eax, BYTE PTR pc2_evt1[rip]
	test	al, al
	je	.L7
.L9:
	movzx	eax, BYTE PTR pc2_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR pc2_evt1[rip]
	test	al, al
	je	.L4
.L7:
	movzx	eax, BYTE PTR pc2_l2[rip]
	test	al, al
	jne	.L10
	movzx	eax, BYTE PTR pc2_l0[rip]
	test	al, al
	je	.L10
	movzx	eax, BYTE PTR pc2_l1[rip]
	test	al, al
	jne	.L11
.L10:
	movzx	eax, BYTE PTR pc2_l2[rip]
	test	al, al
	jne	.L12
	movzx	eax, BYTE PTR pc2_l0[rip]
	test	al, al
	jne	.L12
	movzx	eax, BYTE PTR pc2_l1[rip]
	test	al, al
	je	.L11
.L12:
	movzx	eax, BYTE PTR pc2_l2[rip]
	test	al, al
	je	.L13
	movzx	eax, BYTE PTR pc2_l0[rip]
	test	al, al
	jne	.L13
	movzx	eax, BYTE PTR pc2_l1[rip]
	test	al, al
	je	.L11
.L13:
	movzx	eax, BYTE PTR pc2_l2[rip]
	test	al, al
	jne	.L14
	movzx	eax, BYTE PTR pc2_l1[rip]
	test	al, al
	je	.L14
	movzx	eax, BYTE PTR pc2_l0[rip]
	test	al, al
	je	.L11
.L14:
	movzx	eax, BYTE PTR pc2_l2[rip]
	test	al, al
	je	.L15
	movzx	eax, BYTE PTR pc2_l1[rip]
	test	al, al
	je	.L15
	movzx	eax, BYTE PTR pc2_l0[rip]
	test	al, al
	je	.L11
.L15:
	movzx	eax, BYTE PTR pc2_l2[rip]
	test	al, al
	jne	.L16
	movzx	eax, BYTE PTR pc2_l0[rip]
	test	al, al
	je	.L16
	movzx	eax, BYTE PTR pc2_l1[rip]
	test	al, al
	je	.L11
.L16:
	movzx	eax, BYTE PTR pc2_l2[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR pc2_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR pc2_l1[rip]
	test	al, al
	jne	.L4
.L11:
	movzx	eax, BYTE PTR pc1_l2[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR pc1_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR pc1_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR pc1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR pc1_evt0[rip]
	test	al, al
	jne	.L18
	movzx	eax, BYTE PTR pc1_evt1[rip]
	test	al, al
	je	.L19
.L18:
	movzx	eax, BYTE PTR pc1_evt1[rip]
	test	al, al
	je	.L20
	movzx	eax, BYTE PTR pc1_evt0[rip]
	test	al, al
	je	.L19
.L20:
	movzx	eax, BYTE PTR pc1_evt0[rip]
	test	al, al
	je	.L21
	movzx	eax, BYTE PTR pc1_evt1[rip]
	test	al, al
	je	.L19
.L21:
	movzx	eax, BYTE PTR pc1_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR pc1_evt1[rip]
	test	al, al
	je	.L4
.L19:
	movzx	eax, BYTE PTR pc1_l2[rip]
	test	al, al
	jne	.L22
	movzx	eax, BYTE PTR pc1_l0[rip]
	test	al, al
	je	.L22
	movzx	eax, BYTE PTR pc1_l1[rip]
	test	al, al
	jne	.L23
.L22:
	movzx	eax, BYTE PTR pc1_l2[rip]
	test	al, al
	jne	.L24
	movzx	eax, BYTE PTR pc1_l0[rip]
	test	al, al
	jne	.L24
	movzx	eax, BYTE PTR pc1_l1[rip]
	test	al, al
	je	.L23
.L24:
	movzx	eax, BYTE PTR pc1_l2[rip]
	test	al, al
	je	.L25
	movzx	eax, BYTE PTR pc1_l0[rip]
	test	al, al
	jne	.L25
	movzx	eax, BYTE PTR pc1_l1[rip]
	test	al, al
	je	.L23
.L25:
	movzx	eax, BYTE PTR pc1_l2[rip]
	test	al, al
	jne	.L26
	movzx	eax, BYTE PTR pc1_l1[rip]
	test	al, al
	je	.L26
	movzx	eax, BYTE PTR pc1_l0[rip]
	test	al, al
	je	.L23
.L26:
	movzx	eax, BYTE PTR pc1_l2[rip]
	test	al, al
	je	.L27
	movzx	eax, BYTE PTR pc1_l1[rip]
	test	al, al
	je	.L27
	movzx	eax, BYTE PTR pc1_l0[rip]
	test	al, al
	je	.L23
.L27:
	movzx	eax, BYTE PTR pc1_l2[rip]
	test	al, al
	jne	.L28
	movzx	eax, BYTE PTR pc1_l0[rip]
	test	al, al
	je	.L28
	movzx	eax, BYTE PTR pc1_l1[rip]
	test	al, al
	je	.L23
.L28:
	movzx	eax, BYTE PTR pc1_l2[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR pc1_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR pc1_l1[rip]
	test	al, al
	jne	.L4
.L23:
	movzx	eax, BYTE PTR pc0_l2[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR pc0_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR pc0_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR pc0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR pc0_evt0[rip]
	test	al, al
	jne	.L30
	movzx	eax, BYTE PTR pc0_evt1[rip]
	test	al, al
	je	.L31
.L30:
	movzx	eax, BYTE PTR pc0_evt1[rip]
	test	al, al
	je	.L32
	movzx	eax, BYTE PTR pc0_evt0[rip]
	test	al, al
	je	.L31
.L32:
	movzx	eax, BYTE PTR pc0_evt0[rip]
	test	al, al
	je	.L33
	movzx	eax, BYTE PTR pc0_evt1[rip]
	test	al, al
	je	.L31
.L33:
	movzx	eax, BYTE PTR pc0_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR pc0_evt1[rip]
	test	al, al
	je	.L4
.L31:
	movzx	eax, BYTE PTR pc0_l2[rip]
	test	al, al
	jne	.L34
	movzx	eax, BYTE PTR pc0_l0[rip]
	test	al, al
	je	.L34
	movzx	eax, BYTE PTR pc0_l1[rip]
	test	al, al
	jne	.L35
.L34:
	movzx	eax, BYTE PTR pc0_l2[rip]
	test	al, al
	jne	.L36
	movzx	eax, BYTE PTR pc0_l0[rip]
	test	al, al
	jne	.L36
	movzx	eax, BYTE PTR pc0_l1[rip]
	test	al, al
	je	.L35
.L36:
	movzx	eax, BYTE PTR pc0_l2[rip]
	test	al, al
	je	.L37
	movzx	eax, BYTE PTR pc0_l0[rip]
	test	al, al
	jne	.L37
	movzx	eax, BYTE PTR pc0_l1[rip]
	test	al, al
	je	.L35
.L37:
	movzx	eax, BYTE PTR pc0_l2[rip]
	test	al, al
	jne	.L38
	movzx	eax, BYTE PTR pc0_l1[rip]
	test	al, al
	je	.L38
	movzx	eax, BYTE PTR pc0_l0[rip]
	test	al, al
	je	.L35
.L38:
	movzx	eax, BYTE PTR pc0_l2[rip]
	test	al, al
	je	.L39
	movzx	eax, BYTE PTR pc0_l1[rip]
	test	al, al
	je	.L39
	movzx	eax, BYTE PTR pc0_l0[rip]
	test	al, al
	je	.L35
.L39:
	movzx	eax, BYTE PTR pc0_l2[rip]
	test	al, al
	jne	.L40
	movzx	eax, BYTE PTR pc0_l0[rip]
	test	al, al
	je	.L40
	movzx	eax, BYTE PTR pc0_l1[rip]
	test	al, al
	je	.L35
.L40:
	movzx	eax, BYTE PTR pc0_l2[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR pc0_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR pc0_l1[rip]
	test	al, al
	jne	.L4
.L35:
	movzx	eax, BYTE PTR a2_l[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR a2_evt0[rip]
	test	al, al
	jne	.L41
	movzx	eax, BYTE PTR a2_evt1[rip]
	test	al, al
	je	.L42
.L41:
	movzx	eax, BYTE PTR a2_evt1[rip]
	test	al, al
	je	.L43
	movzx	eax, BYTE PTR a2_evt0[rip]
	test	al, al
	je	.L42
.L43:
	movzx	eax, BYTE PTR a2_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR a2_evt1[rip]
	test	al, al
	jne	.L4
.L42:
	movzx	eax, BYTE PTR a1_l[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR a1_evt0[rip]
	test	al, al
	jne	.L44
	movzx	eax, BYTE PTR a1_evt1[rip]
	test	al, al
	je	.L45
.L44:
	movzx	eax, BYTE PTR a1_evt1[rip]
	test	al, al
	je	.L46
	movzx	eax, BYTE PTR a1_evt0[rip]
	test	al, al
	je	.L45
.L46:
	movzx	eax, BYTE PTR a1_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR a1_evt1[rip]
	test	al, al
	jne	.L4
.L45:
	movzx	eax, BYTE PTR a0_l[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR a0_evt0[rip]
	test	al, al
	jne	.L47
	movzx	eax, BYTE PTR a0_evt1[rip]
	test	al, al
	je	.L48
.L47:
	movzx	eax, BYTE PTR a0_evt1[rip]
	test	al, al
	je	.L49
	movzx	eax, BYTE PTR a0_evt0[rip]
	test	al, al
	je	.L48
.L49:
	movzx	eax, BYTE PTR a0_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR a0_evt1[rip]
	test	al, al
	jne	.L4
.L48:
	movzx	eax, BYTE PTR c_initial[rip]
	test	al, al
	je	.L4
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jb	.L4
	mov	eax, DWORD PTR id[rip]
	cmp	eax, 2
	je	.L51
	mov	eax, DWORD PTR id[rip]
	test	eax, eax
	je	.L51
	mov	eax, DWORD PTR id[rip]
	cmp	eax, 1
	jne	.L4
.L51:
	movss	xmm0, DWORD PTR delta[rip]
	movss	xmm1, DWORD PTR _diverge_delta[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	mov	eax, 1
	jmp	.L53
.L4:
	mov	eax, 0
.L53:
	mov	DWORD PTR -4[rbp], eax
	jmp	.L54
.L285:
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_pc2_l2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_pc2_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_a1_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_a2_l[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_a1_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_pc1_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_a0_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_pc2_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_pc2_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_a0_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_a1_l[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_pc0_l2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_pc2_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_pc1_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_pc0_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_c_initial[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_pc0_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_pc0_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_pc0_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_a0_l[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_id[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_pc1_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_c_move[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_pc1_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_a2_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_pc1_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_a2_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_pc0_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_pc1_l2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x__diverge_delta[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_pc2_x[rip], eax
	movzx	eax, BYTE PTR _x_pc2_evt0[rip]
	test	al, al
	jne	.L55
	movzx	eax, BYTE PTR _x_pc2_evt1[rip]
	test	al, al
	je	.L56
.L55:
	movzx	eax, BYTE PTR _x_pc2_evt1[rip]
	test	al, al
	je	.L57
	movzx	eax, BYTE PTR _x_pc2_evt0[rip]
	test	al, al
	je	.L56
.L57:
	movzx	eax, BYTE PTR _x_pc2_evt0[rip]
	test	al, al
	je	.L58
	movzx	eax, BYTE PTR _x_pc2_evt1[rip]
	test	al, al
	je	.L56
.L58:
	movzx	eax, BYTE PTR _x_pc2_evt0[rip]
	test	al, al
	je	.L59
	movzx	eax, BYTE PTR _x_pc2_evt1[rip]
	test	al, al
	je	.L59
.L56:
	movzx	eax, BYTE PTR _x_pc2_l2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR _x_pc2_l0[rip]
	test	al, al
	je	.L60
	movzx	eax, BYTE PTR _x_pc2_l1[rip]
	test	al, al
	jne	.L61
.L60:
	movzx	eax, BYTE PTR _x_pc2_l2[rip]
	test	al, al
	jne	.L62
	movzx	eax, BYTE PTR _x_pc2_l0[rip]
	test	al, al
	jne	.L62
	movzx	eax, BYTE PTR _x_pc2_l1[rip]
	test	al, al
	je	.L61
.L62:
	movzx	eax, BYTE PTR _x_pc2_l2[rip]
	test	al, al
	je	.L63
	movzx	eax, BYTE PTR _x_pc2_l0[rip]
	test	al, al
	jne	.L63
	movzx	eax, BYTE PTR _x_pc2_l1[rip]
	test	al, al
	je	.L61
.L63:
	movzx	eax, BYTE PTR _x_pc2_l2[rip]
	test	al, al
	jne	.L64
	movzx	eax, BYTE PTR _x_pc2_l1[rip]
	test	al, al
	je	.L64
	movzx	eax, BYTE PTR _x_pc2_l0[rip]
	test	al, al
	je	.L61
.L64:
	movzx	eax, BYTE PTR _x_pc2_l2[rip]
	test	al, al
	je	.L65
	movzx	eax, BYTE PTR _x_pc2_l1[rip]
	test	al, al
	je	.L65
	movzx	eax, BYTE PTR _x_pc2_l0[rip]
	test	al, al
	je	.L61
.L65:
	movzx	eax, BYTE PTR _x_pc2_l2[rip]
	test	al, al
	jne	.L66
	movzx	eax, BYTE PTR _x_pc2_l0[rip]
	test	al, al
	je	.L66
	movzx	eax, BYTE PTR _x_pc2_l1[rip]
	test	al, al
	je	.L61
.L66:
	movzx	eax, BYTE PTR _x_pc2_l2[rip]
	test	al, al
	je	.L59
	movzx	eax, BYTE PTR _x_pc2_l0[rip]
	test	al, al
	je	.L59
	movzx	eax, BYTE PTR _x_pc2_l1[rip]
	test	al, al
	jne	.L59
.L61:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L67
	movzx	eax, BYTE PTR pc2_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_pc2_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L59
	movzx	eax, BYTE PTR pc2_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_pc2_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L59
	movzx	eax, BYTE PTR pc2_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_pc2_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L59
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR pc2_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_pc2_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L59
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L59
.L67:
	movzx	eax, BYTE PTR pc2_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_pc2_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L69
	movzx	eax, BYTE PTR pc2_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_pc2_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L69
	movzx	eax, BYTE PTR pc2_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_pc2_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L69
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR pc2_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_pc2_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L69
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L70
.L69:
	movzx	eax, BYTE PTR pc2_evt0[rip]
	test	al, al
	jne	.L70
	movzx	eax, BYTE PTR pc2_evt1[rip]
	test	al, al
	je	.L59
.L70:
	movzx	eax, BYTE PTR pc2_evt0[rip]
	test	al, al
	je	.L72
	movzx	eax, BYTE PTR pc2_evt1[rip]
	test	al, al
	je	.L72
	movss	xmm1, DWORD PTR pc2_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jb	.L72
	movzx	eax, BYTE PTR _x_pc2_l2[rip]
	test	al, al
	je	.L72
	movzx	eax, BYTE PTR _x_pc2_l0[rip]
	test	al, al
	jne	.L72
	movzx	eax, BYTE PTR _x_pc2_l1[rip]
	test	al, al
	jne	.L72
	movss	xmm0, DWORD PTR _x_pc2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L72
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L74
.L72:
	movzx	eax, BYTE PTR pc2_l2[rip]
	test	al, al
	jne	.L74
	movzx	eax, BYTE PTR pc2_l0[rip]
	test	al, al
	jne	.L74
	movzx	eax, BYTE PTR pc2_l1[rip]
	test	al, al
	jne	.L74
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L74
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L74
	movzx	eax, BYTE PTR pc2_evt0[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR pc2_evt1[rip]
	test	al, al
	jne	.L59
.L74:
	movzx	eax, BYTE PTR pc2_evt0[rip]
	test	al, al
	je	.L76
	movzx	eax, BYTE PTR pc2_evt1[rip]
	test	al, al
	je	.L76
	movzx	eax, BYTE PTR _x_pc2_l2[rip]
	test	al, al
	jne	.L77
	movzx	eax, BYTE PTR _x_pc2_l0[rip]
	test	al, al
	jne	.L77
	movzx	eax, BYTE PTR _x_pc2_l1[rip]
	test	al, al
	je	.L78
.L77:
	movzx	eax, BYTE PTR _x_pc2_l2[rip]
	test	al, al
	jne	.L76
	movzx	eax, BYTE PTR _x_pc2_l1[rip]
	test	al, al
	je	.L76
	movzx	eax, BYTE PTR _x_pc2_l0[rip]
	test	al, al
	je	.L78
.L76:
	movzx	eax, BYTE PTR pc2_l2[rip]
	test	al, al
	je	.L78
	movzx	eax, BYTE PTR pc2_l0[rip]
	test	al, al
	jne	.L78
	movzx	eax, BYTE PTR pc2_l1[rip]
	test	al, al
	jne	.L78
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L78
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L78
	movzx	eax, BYTE PTR pc2_evt0[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR pc2_evt1[rip]
	test	al, al
	jne	.L59
.L78:
	movss	xmm0, DWORD PTR _x_pc2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L79
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L79
	movss	xmm0, DWORD PTR pc2_x[rip]
	comiss	xmm0, DWORD PTR .LC3[rip]
	jnb	.L81
.L79:
	movzx	eax, BYTE PTR _x_pc2_l2[rip]
	test	al, al
	jne	.L81
	movzx	eax, BYTE PTR _x_pc2_l0[rip]
	test	al, al
	jne	.L81
	movzx	eax, BYTE PTR _x_pc2_l1[rip]
	test	al, al
	jne	.L81
	movzx	eax, BYTE PTR pc2_l2[rip]
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR pc2_l0[rip]
	test	al, al
	jne	.L81
	movzx	eax, BYTE PTR pc2_l1[rip]
	test	al, al
	je	.L59
.L81:
	movss	xmm1, DWORD PTR pc2_x[rip]
	movss	xmm0, DWORD PTR .LC4[rip]
	comiss	xmm0, xmm1
	jb	.L82
	movss	xmm0, DWORD PTR pc2_x[rip]
	movss	xmm1, DWORD PTR _x_pc2_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L82
	ucomiss	xmm0, xmm1
	je	.L84
.L82:
	movzx	eax, BYTE PTR pc2_l2[rip]
	test	al, al
	je	.L84
	movzx	eax, BYTE PTR pc2_l0[rip]
	test	al, al
	jne	.L84
	movzx	eax, BYTE PTR pc2_l1[rip]
	test	al, al
	jne	.L84
	movzx	eax, BYTE PTR _x_pc2_l2[rip]
	test	al, al
	jne	.L84
	movzx	eax, BYTE PTR _x_pc2_l1[rip]
	test	al, al
	je	.L84
	movzx	eax, BYTE PTR _x_pc2_l0[rip]
	test	al, al
	je	.L59
.L84:
	movss	xmm0, DWORD PTR _x_pc2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L86
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L86
	movzx	eax, BYTE PTR pc2_evt1[rip]
	test	al, al
	je	.L86
	movzx	eax, BYTE PTR pc2_evt0[rip]
	test	al, al
	jne	.L86
	movzx	eax, BYTE PTR _x_pc2_l2[rip]
	test	al, al
	je	.L86
	movzx	eax, BYTE PTR _x_pc2_l1[rip]
	test	al, al
	je	.L86
	movzx	eax, BYTE PTR _x_pc2_l0[rip]
	test	al, al
	je	.L88
.L86:
	movzx	eax, BYTE PTR pc2_l2[rip]
	test	al, al
	jne	.L88
	movzx	eax, BYTE PTR pc2_l1[rip]
	test	al, al
	je	.L88
	movzx	eax, BYTE PTR pc2_l0[rip]
	test	al, al
	jne	.L88
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L88
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L88
	movzx	eax, BYTE PTR pc2_evt0[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR pc2_evt1[rip]
	test	al, al
	jne	.L59
.L88:
	movzx	eax, BYTE PTR _x_pc2_l2[rip]
	test	al, al
	jne	.L89
	movzx	eax, BYTE PTR _x_pc2_l0[rip]
	test	al, al
	je	.L89
	movzx	eax, BYTE PTR _x_pc2_l1[rip]
	test	al, al
	je	.L90
.L89:
	movzx	eax, BYTE PTR _x_pc2_l2[rip]
	test	al, al
	jne	.L91
	movzx	eax, BYTE PTR _x_pc2_l0[rip]
	test	al, al
	je	.L91
	movzx	eax, BYTE PTR _x_pc2_l1[rip]
	test	al, al
	jne	.L90
.L91:
	movzx	eax, BYTE PTR pc2_l2[rip]
	test	al, al
	je	.L90
	movzx	eax, BYTE PTR pc2_l1[rip]
	test	al, al
	je	.L90
	movzx	eax, BYTE PTR pc2_l0[rip]
	test	al, al
	jne	.L90
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L90
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L90
	movzx	eax, BYTE PTR pc2_evt0[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR pc2_evt1[rip]
	test	al, al
	jne	.L59
.L90:
	movss	xmm0, DWORD PTR pc2_x[rip]
	movss	xmm1, DWORD PTR _x_pc2_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L92
	ucomiss	xmm0, xmm1
	jne	.L92
	movzx	eax, BYTE PTR pc2_evt0[rip]
	test	al, al
	je	.L92
	movzx	eax, BYTE PTR pc2_evt1[rip]
	test	al, al
	je	.L92
	movss	xmm0, DWORD PTR pc2_x[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L94
.L92:
	movzx	eax, BYTE PTR pc2_l2[rip]
	test	al, al
	je	.L94
	movzx	eax, BYTE PTR pc2_l1[rip]
	test	al, al
	je	.L94
	movzx	eax, BYTE PTR pc2_l0[rip]
	test	al, al
	jne	.L94
	movzx	eax, BYTE PTR _x_pc2_l2[rip]
	test	al, al
	jne	.L94
	movzx	eax, BYTE PTR _x_pc2_l0[rip]
	test	al, al
	je	.L94
	movzx	eax, BYTE PTR _x_pc2_l1[rip]
	test	al, al
	jne	.L59
.L94:
	movss	xmm0, DWORD PTR _x_pc2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L95
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L95
	movzx	eax, BYTE PTR pc2_evt0[rip]
	test	al, al
	je	.L95
	movzx	eax, BYTE PTR pc2_evt1[rip]
	test	al, al
	jne	.L95
	movss	xmm1, DWORD PTR pc2_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	jnb	.L97
.L95:
	movzx	eax, BYTE PTR pc2_l2[rip]
	test	al, al
	je	.L97
	movzx	eax, BYTE PTR pc2_l1[rip]
	test	al, al
	je	.L97
	movzx	eax, BYTE PTR pc2_l0[rip]
	test	al, al
	jne	.L97
	movzx	eax, BYTE PTR _x_pc2_l2[rip]
	test	al, al
	jne	.L97
	movzx	eax, BYTE PTR _x_pc2_l0[rip]
	test	al, al
	je	.L97
	movzx	eax, BYTE PTR _x_pc2_l1[rip]
	test	al, al
	je	.L59
.L97:
	movzx	eax, BYTE PTR pc2_evt0[rip]
	test	al, al
	je	.L98
	movzx	eax, BYTE PTR pc2_evt1[rip]
	test	al, al
	je	.L98
	movss	xmm0, DWORD PTR pc2_x[rip]
	movss	xmm1, DWORD PTR _x_pc2_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L98
	ucomiss	xmm0, xmm1
	jne	.L98
	movzx	eax, BYTE PTR _x_pc2_l2[rip]
	test	al, al
	je	.L100
	movzx	eax, BYTE PTR _x_pc2_l0[rip]
	test	al, al
	je	.L100
	movzx	eax, BYTE PTR _x_pc2_l1[rip]
	test	al, al
	je	.L101
.L100:
	movzx	eax, BYTE PTR _x_pc2_l2[rip]
	test	al, al
	jne	.L98
	movzx	eax, BYTE PTR _x_pc2_l0[rip]
	test	al, al
	je	.L98
	movzx	eax, BYTE PTR _x_pc2_l1[rip]
	test	al, al
	jne	.L101
.L98:
	movzx	eax, BYTE PTR pc2_l2[rip]
	test	al, al
	jne	.L101
	movzx	eax, BYTE PTR pc2_l0[rip]
	test	al, al
	je	.L101
	movzx	eax, BYTE PTR pc2_l1[rip]
	test	al, al
	jne	.L101
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L101
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L101
	movzx	eax, BYTE PTR pc2_evt0[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR pc2_evt1[rip]
	test	al, al
	jne	.L59
.L101:
	movss	xmm0, DWORD PTR pc2_x[rip]
	comiss	xmm0, DWORD PTR .LC3[rip]
	jnb	.L102
	movzx	eax, BYTE PTR pc2_l2[rip]
	test	al, al
	jne	.L102
	movzx	eax, BYTE PTR pc2_l0[rip]
	test	al, al
	je	.L102
	movzx	eax, BYTE PTR pc2_l1[rip]
	test	al, al
	jne	.L102
	movzx	eax, BYTE PTR _x_pc2_l2[rip]
	test	al, al
	jne	.L102
	movzx	eax, BYTE PTR _x_pc2_l0[rip]
	test	al, al
	je	.L102
	movzx	eax, BYTE PTR _x_pc2_l1[rip]
	test	al, al
	jne	.L59
.L102:
	movss	xmm1, DWORD PTR pc2_x[rip]
	movss	xmm0, DWORD PTR .LC4[rip]
	comiss	xmm0, xmm1
	jnb	.L103
	movzx	eax, BYTE PTR pc2_l2[rip]
	test	al, al
	jne	.L103
	movzx	eax, BYTE PTR pc2_l0[rip]
	test	al, al
	je	.L103
	movzx	eax, BYTE PTR pc2_l1[rip]
	test	al, al
	jne	.L103
	movzx	eax, BYTE PTR _x_pc2_l2[rip]
	test	al, al
	je	.L103
	movzx	eax, BYTE PTR _x_pc2_l0[rip]
	test	al, al
	je	.L103
	movzx	eax, BYTE PTR _x_pc2_l1[rip]
	test	al, al
	je	.L59
.L103:
	movzx	eax, BYTE PTR _x_pc2_l2[rip]
	test	al, al
	jne	.L104
	movzx	eax, BYTE PTR _x_pc2_l0[rip]
	test	al, al
	je	.L104
	movzx	eax, BYTE PTR _x_pc2_l1[rip]
	test	al, al
	jne	.L105
.L104:
	movzx	eax, BYTE PTR pc2_l2[rip]
	test	al, al
	jne	.L105
	movzx	eax, BYTE PTR pc2_l0[rip]
	test	al, al
	je	.L105
	movzx	eax, BYTE PTR pc2_l1[rip]
	test	al, al
	je	.L105
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L105
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L105
	movzx	eax, BYTE PTR pc2_evt0[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR pc2_evt1[rip]
	test	al, al
	jne	.L59
.L105:
	movzx	eax, BYTE PTR _x_pc2_l2[rip]
	test	al, al
	jne	.L106
	movzx	eax, BYTE PTR _x_pc2_l0[rip]
	test	al, al
	jne	.L106
	movzx	eax, BYTE PTR _x_pc2_l1[rip]
	test	al, al
	je	.L107
.L106:
	movzx	eax, BYTE PTR pc2_l2[rip]
	test	al, al
	je	.L107
	movzx	eax, BYTE PTR pc2_l0[rip]
	test	al, al
	je	.L107
	movzx	eax, BYTE PTR pc2_l1[rip]
	test	al, al
	jne	.L107
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L107
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L107
	movzx	eax, BYTE PTR pc2_evt0[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR pc2_evt1[rip]
	test	al, al
	jne	.L59
.L107:
	movzx	eax, BYTE PTR _x_pc1_evt0[rip]
	test	al, al
	jne	.L108
	movzx	eax, BYTE PTR _x_pc1_evt1[rip]
	test	al, al
	je	.L109
.L108:
	movzx	eax, BYTE PTR _x_pc1_evt1[rip]
	test	al, al
	je	.L110
	movzx	eax, BYTE PTR _x_pc1_evt0[rip]
	test	al, al
	je	.L109
.L110:
	movzx	eax, BYTE PTR _x_pc1_evt0[rip]
	test	al, al
	je	.L111
	movzx	eax, BYTE PTR _x_pc1_evt1[rip]
	test	al, al
	je	.L109
.L111:
	movzx	eax, BYTE PTR _x_pc1_evt0[rip]
	test	al, al
	je	.L59
	movzx	eax, BYTE PTR _x_pc1_evt1[rip]
	test	al, al
	je	.L59
.L109:
	movzx	eax, BYTE PTR _x_pc1_l2[rip]
	test	al, al
	jne	.L112
	movzx	eax, BYTE PTR _x_pc1_l0[rip]
	test	al, al
	je	.L112
	movzx	eax, BYTE PTR _x_pc1_l1[rip]
	test	al, al
	jne	.L113
.L112:
	movzx	eax, BYTE PTR _x_pc1_l2[rip]
	test	al, al
	jne	.L114
	movzx	eax, BYTE PTR _x_pc1_l0[rip]
	test	al, al
	jne	.L114
	movzx	eax, BYTE PTR _x_pc1_l1[rip]
	test	al, al
	je	.L113
.L114:
	movzx	eax, BYTE PTR _x_pc1_l2[rip]
	test	al, al
	je	.L115
	movzx	eax, BYTE PTR _x_pc1_l0[rip]
	test	al, al
	jne	.L115
	movzx	eax, BYTE PTR _x_pc1_l1[rip]
	test	al, al
	je	.L113
.L115:
	movzx	eax, BYTE PTR _x_pc1_l2[rip]
	test	al, al
	jne	.L116
	movzx	eax, BYTE PTR _x_pc1_l1[rip]
	test	al, al
	je	.L116
	movzx	eax, BYTE PTR _x_pc1_l0[rip]
	test	al, al
	je	.L113
.L116:
	movzx	eax, BYTE PTR _x_pc1_l2[rip]
	test	al, al
	je	.L117
	movzx	eax, BYTE PTR _x_pc1_l1[rip]
	test	al, al
	je	.L117
	movzx	eax, BYTE PTR _x_pc1_l0[rip]
	test	al, al
	je	.L113
.L117:
	movzx	eax, BYTE PTR _x_pc1_l2[rip]
	test	al, al
	jne	.L118
	movzx	eax, BYTE PTR _x_pc1_l0[rip]
	test	al, al
	je	.L118
	movzx	eax, BYTE PTR _x_pc1_l1[rip]
	test	al, al
	je	.L113
.L118:
	movzx	eax, BYTE PTR _x_pc1_l2[rip]
	test	al, al
	je	.L59
	movzx	eax, BYTE PTR _x_pc1_l0[rip]
	test	al, al
	je	.L59
	movzx	eax, BYTE PTR _x_pc1_l1[rip]
	test	al, al
	jne	.L59
.L113:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L119
	movzx	eax, BYTE PTR pc1_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_pc1_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L59
	movzx	eax, BYTE PTR pc1_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_pc1_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L59
	movzx	eax, BYTE PTR pc1_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_pc1_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L59
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR pc1_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_pc1_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L59
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L59
.L119:
	movzx	eax, BYTE PTR pc1_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_pc1_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L121
	movzx	eax, BYTE PTR pc1_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_pc1_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L121
	movzx	eax, BYTE PTR pc1_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_pc1_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L121
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR pc1_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_pc1_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L121
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L122
.L121:
	movzx	eax, BYTE PTR pc1_evt0[rip]
	test	al, al
	jne	.L122
	movzx	eax, BYTE PTR pc1_evt1[rip]
	test	al, al
	je	.L59
.L122:
	movzx	eax, BYTE PTR pc1_evt0[rip]
	test	al, al
	je	.L124
	movzx	eax, BYTE PTR pc1_evt1[rip]
	test	al, al
	je	.L124
	movss	xmm1, DWORD PTR pc1_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jb	.L124
	movzx	eax, BYTE PTR _x_pc1_l2[rip]
	test	al, al
	je	.L124
	movzx	eax, BYTE PTR _x_pc1_l0[rip]
	test	al, al
	jne	.L124
	movzx	eax, BYTE PTR _x_pc1_l1[rip]
	test	al, al
	jne	.L124
	movss	xmm0, DWORD PTR _x_pc1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L124
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L126
.L124:
	movzx	eax, BYTE PTR pc1_l2[rip]
	test	al, al
	jne	.L126
	movzx	eax, BYTE PTR pc1_l0[rip]
	test	al, al
	jne	.L126
	movzx	eax, BYTE PTR pc1_l1[rip]
	test	al, al
	jne	.L126
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L126
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L126
	movzx	eax, BYTE PTR pc1_evt0[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR pc1_evt1[rip]
	test	al, al
	jne	.L59
.L126:
	movzx	eax, BYTE PTR pc1_evt0[rip]
	test	al, al
	je	.L128
	movzx	eax, BYTE PTR pc1_evt1[rip]
	test	al, al
	je	.L128
	movzx	eax, BYTE PTR _x_pc1_l2[rip]
	test	al, al
	jne	.L129
	movzx	eax, BYTE PTR _x_pc1_l0[rip]
	test	al, al
	jne	.L129
	movzx	eax, BYTE PTR _x_pc1_l1[rip]
	test	al, al
	je	.L130
.L129:
	movzx	eax, BYTE PTR _x_pc1_l2[rip]
	test	al, al
	jne	.L128
	movzx	eax, BYTE PTR _x_pc1_l1[rip]
	test	al, al
	je	.L128
	movzx	eax, BYTE PTR _x_pc1_l0[rip]
	test	al, al
	je	.L130
.L128:
	movzx	eax, BYTE PTR pc1_l2[rip]
	test	al, al
	je	.L130
	movzx	eax, BYTE PTR pc1_l0[rip]
	test	al, al
	jne	.L130
	movzx	eax, BYTE PTR pc1_l1[rip]
	test	al, al
	jne	.L130
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L130
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L130
	movzx	eax, BYTE PTR pc1_evt0[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR pc1_evt1[rip]
	test	al, al
	jne	.L59
.L130:
	movss	xmm0, DWORD PTR _x_pc1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L131
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L131
	movss	xmm0, DWORD PTR pc1_x[rip]
	comiss	xmm0, DWORD PTR .LC3[rip]
	jnb	.L133
.L131:
	movzx	eax, BYTE PTR _x_pc1_l2[rip]
	test	al, al
	jne	.L133
	movzx	eax, BYTE PTR _x_pc1_l0[rip]
	test	al, al
	jne	.L133
	movzx	eax, BYTE PTR _x_pc1_l1[rip]
	test	al, al
	jne	.L133
	movzx	eax, BYTE PTR pc1_l2[rip]
	test	al, al
	je	.L133
	movzx	eax, BYTE PTR pc1_l0[rip]
	test	al, al
	jne	.L133
	movzx	eax, BYTE PTR pc1_l1[rip]
	test	al, al
	je	.L59
.L133:
	movss	xmm1, DWORD PTR pc1_x[rip]
	movss	xmm0, DWORD PTR .LC4[rip]
	comiss	xmm0, xmm1
	jb	.L134
	movss	xmm0, DWORD PTR pc1_x[rip]
	movss	xmm1, DWORD PTR _x_pc1_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L134
	ucomiss	xmm0, xmm1
	je	.L136
.L134:
	movzx	eax, BYTE PTR pc1_l2[rip]
	test	al, al
	je	.L136
	movzx	eax, BYTE PTR pc1_l0[rip]
	test	al, al
	jne	.L136
	movzx	eax, BYTE PTR pc1_l1[rip]
	test	al, al
	jne	.L136
	movzx	eax, BYTE PTR _x_pc1_l2[rip]
	test	al, al
	jne	.L136
	movzx	eax, BYTE PTR _x_pc1_l1[rip]
	test	al, al
	je	.L136
	movzx	eax, BYTE PTR _x_pc1_l0[rip]
	test	al, al
	je	.L59
.L136:
	movss	xmm0, DWORD PTR _x_pc1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L138
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L138
	movzx	eax, BYTE PTR pc1_evt1[rip]
	test	al, al
	je	.L138
	movzx	eax, BYTE PTR pc1_evt0[rip]
	test	al, al
	jne	.L138
	movzx	eax, BYTE PTR _x_pc1_l2[rip]
	test	al, al
	je	.L138
	movzx	eax, BYTE PTR _x_pc1_l1[rip]
	test	al, al
	je	.L138
	movzx	eax, BYTE PTR _x_pc1_l0[rip]
	test	al, al
	je	.L140
.L138:
	movzx	eax, BYTE PTR pc1_l2[rip]
	test	al, al
	jne	.L140
	movzx	eax, BYTE PTR pc1_l1[rip]
	test	al, al
	je	.L140
	movzx	eax, BYTE PTR pc1_l0[rip]
	test	al, al
	jne	.L140
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L140
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L140
	movzx	eax, BYTE PTR pc1_evt0[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR pc1_evt1[rip]
	test	al, al
	jne	.L59
.L140:
	movzx	eax, BYTE PTR _x_pc1_l2[rip]
	test	al, al
	jne	.L141
	movzx	eax, BYTE PTR _x_pc1_l0[rip]
	test	al, al
	je	.L141
	movzx	eax, BYTE PTR _x_pc1_l1[rip]
	test	al, al
	je	.L142
.L141:
	movzx	eax, BYTE PTR _x_pc1_l2[rip]
	test	al, al
	jne	.L143
	movzx	eax, BYTE PTR _x_pc1_l0[rip]
	test	al, al
	je	.L143
	movzx	eax, BYTE PTR _x_pc1_l1[rip]
	test	al, al
	jne	.L142
.L143:
	movzx	eax, BYTE PTR pc1_l2[rip]
	test	al, al
	je	.L142
	movzx	eax, BYTE PTR pc1_l1[rip]
	test	al, al
	je	.L142
	movzx	eax, BYTE PTR pc1_l0[rip]
	test	al, al
	jne	.L142
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L142
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L142
	movzx	eax, BYTE PTR pc1_evt0[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR pc1_evt1[rip]
	test	al, al
	jne	.L59
.L142:
	movss	xmm0, DWORD PTR pc1_x[rip]
	movss	xmm1, DWORD PTR _x_pc1_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L144
	ucomiss	xmm0, xmm1
	jne	.L144
	movzx	eax, BYTE PTR pc1_evt0[rip]
	test	al, al
	je	.L144
	movzx	eax, BYTE PTR pc1_evt1[rip]
	test	al, al
	je	.L144
	movss	xmm0, DWORD PTR pc1_x[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L146
.L144:
	movzx	eax, BYTE PTR pc1_l2[rip]
	test	al, al
	je	.L146
	movzx	eax, BYTE PTR pc1_l1[rip]
	test	al, al
	je	.L146
	movzx	eax, BYTE PTR pc1_l0[rip]
	test	al, al
	jne	.L146
	movzx	eax, BYTE PTR _x_pc1_l2[rip]
	test	al, al
	jne	.L146
	movzx	eax, BYTE PTR _x_pc1_l0[rip]
	test	al, al
	je	.L146
	movzx	eax, BYTE PTR _x_pc1_l1[rip]
	test	al, al
	jne	.L59
.L146:
	movss	xmm0, DWORD PTR _x_pc1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L147
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L147
	movzx	eax, BYTE PTR pc1_evt0[rip]
	test	al, al
	je	.L147
	movzx	eax, BYTE PTR pc1_evt1[rip]
	test	al, al
	jne	.L147
	movss	xmm1, DWORD PTR pc1_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	jnb	.L149
.L147:
	movzx	eax, BYTE PTR pc1_l2[rip]
	test	al, al
	je	.L149
	movzx	eax, BYTE PTR pc1_l1[rip]
	test	al, al
	je	.L149
	movzx	eax, BYTE PTR pc1_l0[rip]
	test	al, al
	jne	.L149
	movzx	eax, BYTE PTR _x_pc1_l2[rip]
	test	al, al
	jne	.L149
	movzx	eax, BYTE PTR _x_pc1_l0[rip]
	test	al, al
	je	.L149
	movzx	eax, BYTE PTR _x_pc1_l1[rip]
	test	al, al
	je	.L59
.L149:
	movzx	eax, BYTE PTR pc1_evt0[rip]
	test	al, al
	je	.L150
	movzx	eax, BYTE PTR pc1_evt1[rip]
	test	al, al
	je	.L150
	movss	xmm0, DWORD PTR pc1_x[rip]
	movss	xmm1, DWORD PTR _x_pc1_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L150
	ucomiss	xmm0, xmm1
	jne	.L150
	movzx	eax, BYTE PTR _x_pc1_l2[rip]
	test	al, al
	je	.L152
	movzx	eax, BYTE PTR _x_pc1_l0[rip]
	test	al, al
	je	.L152
	movzx	eax, BYTE PTR _x_pc1_l1[rip]
	test	al, al
	je	.L153
.L152:
	movzx	eax, BYTE PTR _x_pc1_l2[rip]
	test	al, al
	jne	.L150
	movzx	eax, BYTE PTR _x_pc1_l0[rip]
	test	al, al
	je	.L150
	movzx	eax, BYTE PTR _x_pc1_l1[rip]
	test	al, al
	jne	.L153
.L150:
	movzx	eax, BYTE PTR pc1_l2[rip]
	test	al, al
	jne	.L153
	movzx	eax, BYTE PTR pc1_l0[rip]
	test	al, al
	je	.L153
	movzx	eax, BYTE PTR pc1_l1[rip]
	test	al, al
	jne	.L153
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L153
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L153
	movzx	eax, BYTE PTR pc1_evt0[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR pc1_evt1[rip]
	test	al, al
	jne	.L59
.L153:
	movss	xmm0, DWORD PTR pc1_x[rip]
	comiss	xmm0, DWORD PTR .LC3[rip]
	jnb	.L154
	movzx	eax, BYTE PTR pc1_l2[rip]
	test	al, al
	jne	.L154
	movzx	eax, BYTE PTR pc1_l0[rip]
	test	al, al
	je	.L154
	movzx	eax, BYTE PTR pc1_l1[rip]
	test	al, al
	jne	.L154
	movzx	eax, BYTE PTR _x_pc1_l2[rip]
	test	al, al
	jne	.L154
	movzx	eax, BYTE PTR _x_pc1_l0[rip]
	test	al, al
	je	.L154
	movzx	eax, BYTE PTR _x_pc1_l1[rip]
	test	al, al
	jne	.L59
.L154:
	movss	xmm1, DWORD PTR pc1_x[rip]
	movss	xmm0, DWORD PTR .LC4[rip]
	comiss	xmm0, xmm1
	jnb	.L155
	movzx	eax, BYTE PTR pc1_l2[rip]
	test	al, al
	jne	.L155
	movzx	eax, BYTE PTR pc1_l0[rip]
	test	al, al
	je	.L155
	movzx	eax, BYTE PTR pc1_l1[rip]
	test	al, al
	jne	.L155
	movzx	eax, BYTE PTR _x_pc1_l2[rip]
	test	al, al
	je	.L155
	movzx	eax, BYTE PTR _x_pc1_l0[rip]
	test	al, al
	je	.L155
	movzx	eax, BYTE PTR _x_pc1_l1[rip]
	test	al, al
	je	.L59
.L155:
	movzx	eax, BYTE PTR _x_pc1_l2[rip]
	test	al, al
	jne	.L156
	movzx	eax, BYTE PTR _x_pc1_l0[rip]
	test	al, al
	je	.L156
	movzx	eax, BYTE PTR _x_pc1_l1[rip]
	test	al, al
	jne	.L157
.L156:
	movzx	eax, BYTE PTR pc1_l2[rip]
	test	al, al
	jne	.L157
	movzx	eax, BYTE PTR pc1_l0[rip]
	test	al, al
	je	.L157
	movzx	eax, BYTE PTR pc1_l1[rip]
	test	al, al
	je	.L157
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L157
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L157
	movzx	eax, BYTE PTR pc1_evt0[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR pc1_evt1[rip]
	test	al, al
	jne	.L59
.L157:
	movzx	eax, BYTE PTR _x_pc1_l2[rip]
	test	al, al
	jne	.L158
	movzx	eax, BYTE PTR _x_pc1_l0[rip]
	test	al, al
	jne	.L158
	movzx	eax, BYTE PTR _x_pc1_l1[rip]
	test	al, al
	je	.L159
.L158:
	movzx	eax, BYTE PTR pc1_l2[rip]
	test	al, al
	je	.L159
	movzx	eax, BYTE PTR pc1_l0[rip]
	test	al, al
	je	.L159
	movzx	eax, BYTE PTR pc1_l1[rip]
	test	al, al
	jne	.L159
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L159
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L159
	movzx	eax, BYTE PTR pc1_evt0[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR pc1_evt1[rip]
	test	al, al
	jne	.L59
.L159:
	movzx	eax, BYTE PTR _x_pc0_evt0[rip]
	test	al, al
	jne	.L160
	movzx	eax, BYTE PTR _x_pc0_evt1[rip]
	test	al, al
	je	.L161
.L160:
	movzx	eax, BYTE PTR _x_pc0_evt1[rip]
	test	al, al
	je	.L162
	movzx	eax, BYTE PTR _x_pc0_evt0[rip]
	test	al, al
	je	.L161
.L162:
	movzx	eax, BYTE PTR _x_pc0_evt0[rip]
	test	al, al
	je	.L163
	movzx	eax, BYTE PTR _x_pc0_evt1[rip]
	test	al, al
	je	.L161
.L163:
	movzx	eax, BYTE PTR _x_pc0_evt0[rip]
	test	al, al
	je	.L59
	movzx	eax, BYTE PTR _x_pc0_evt1[rip]
	test	al, al
	je	.L59
.L161:
	movzx	eax, BYTE PTR _x_pc0_l2[rip]
	test	al, al
	jne	.L164
	movzx	eax, BYTE PTR _x_pc0_l0[rip]
	test	al, al
	je	.L164
	movzx	eax, BYTE PTR _x_pc0_l1[rip]
	test	al, al
	jne	.L165
.L164:
	movzx	eax, BYTE PTR _x_pc0_l2[rip]
	test	al, al
	jne	.L166
	movzx	eax, BYTE PTR _x_pc0_l0[rip]
	test	al, al
	jne	.L166
	movzx	eax, BYTE PTR _x_pc0_l1[rip]
	test	al, al
	je	.L165
.L166:
	movzx	eax, BYTE PTR _x_pc0_l2[rip]
	test	al, al
	je	.L167
	movzx	eax, BYTE PTR _x_pc0_l0[rip]
	test	al, al
	jne	.L167
	movzx	eax, BYTE PTR _x_pc0_l1[rip]
	test	al, al
	je	.L165
.L167:
	movzx	eax, BYTE PTR _x_pc0_l2[rip]
	test	al, al
	jne	.L168
	movzx	eax, BYTE PTR _x_pc0_l1[rip]
	test	al, al
	je	.L168
	movzx	eax, BYTE PTR _x_pc0_l0[rip]
	test	al, al
	je	.L165
.L168:
	movzx	eax, BYTE PTR _x_pc0_l2[rip]
	test	al, al
	je	.L169
	movzx	eax, BYTE PTR _x_pc0_l1[rip]
	test	al, al
	je	.L169
	movzx	eax, BYTE PTR _x_pc0_l0[rip]
	test	al, al
	je	.L165
.L169:
	movzx	eax, BYTE PTR _x_pc0_l2[rip]
	test	al, al
	jne	.L170
	movzx	eax, BYTE PTR _x_pc0_l0[rip]
	test	al, al
	je	.L170
	movzx	eax, BYTE PTR _x_pc0_l1[rip]
	test	al, al
	je	.L165
.L170:
	movzx	eax, BYTE PTR _x_pc0_l2[rip]
	test	al, al
	je	.L59
	movzx	eax, BYTE PTR _x_pc0_l0[rip]
	test	al, al
	je	.L59
	movzx	eax, BYTE PTR _x_pc0_l1[rip]
	test	al, al
	jne	.L59
.L165:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L171
	movzx	eax, BYTE PTR pc0_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_pc0_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L59
	movzx	eax, BYTE PTR pc0_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_pc0_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L59
	movzx	eax, BYTE PTR pc0_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_pc0_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L59
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR pc0_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_pc0_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L59
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L59
.L171:
	movzx	eax, BYTE PTR pc0_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_pc0_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L173
	movzx	eax, BYTE PTR pc0_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_pc0_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L173
	movzx	eax, BYTE PTR pc0_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_pc0_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L173
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR pc0_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_pc0_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L173
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L174
.L173:
	movzx	eax, BYTE PTR pc0_evt0[rip]
	test	al, al
	jne	.L174
	movzx	eax, BYTE PTR pc0_evt1[rip]
	test	al, al
	je	.L59
.L174:
	movzx	eax, BYTE PTR pc0_evt0[rip]
	test	al, al
	je	.L176
	movzx	eax, BYTE PTR pc0_evt1[rip]
	test	al, al
	je	.L176
	movss	xmm1, DWORD PTR pc0_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jb	.L176
	movzx	eax, BYTE PTR _x_pc0_l2[rip]
	test	al, al
	je	.L176
	movzx	eax, BYTE PTR _x_pc0_l0[rip]
	test	al, al
	jne	.L176
	movzx	eax, BYTE PTR _x_pc0_l1[rip]
	test	al, al
	jne	.L176
	movss	xmm0, DWORD PTR _x_pc0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L176
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L178
.L176:
	movzx	eax, BYTE PTR pc0_l2[rip]
	test	al, al
	jne	.L178
	movzx	eax, BYTE PTR pc0_l0[rip]
	test	al, al
	jne	.L178
	movzx	eax, BYTE PTR pc0_l1[rip]
	test	al, al
	jne	.L178
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L178
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L178
	movzx	eax, BYTE PTR pc0_evt0[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR pc0_evt1[rip]
	test	al, al
	jne	.L59
.L178:
	movzx	eax, BYTE PTR pc0_evt0[rip]
	test	al, al
	je	.L180
	movzx	eax, BYTE PTR pc0_evt1[rip]
	test	al, al
	je	.L180
	movzx	eax, BYTE PTR _x_pc0_l2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR _x_pc0_l0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR _x_pc0_l1[rip]
	test	al, al
	je	.L182
.L181:
	movzx	eax, BYTE PTR _x_pc0_l2[rip]
	test	al, al
	jne	.L180
	movzx	eax, BYTE PTR _x_pc0_l1[rip]
	test	al, al
	je	.L180
	movzx	eax, BYTE PTR _x_pc0_l0[rip]
	test	al, al
	je	.L182
.L180:
	movzx	eax, BYTE PTR pc0_l2[rip]
	test	al, al
	je	.L182
	movzx	eax, BYTE PTR pc0_l0[rip]
	test	al, al
	jne	.L182
	movzx	eax, BYTE PTR pc0_l1[rip]
	test	al, al
	jne	.L182
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L182
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L182
	movzx	eax, BYTE PTR pc0_evt0[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR pc0_evt1[rip]
	test	al, al
	jne	.L59
.L182:
	movss	xmm0, DWORD PTR _x_pc0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L183
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L183
	movss	xmm0, DWORD PTR pc0_x[rip]
	comiss	xmm0, DWORD PTR .LC3[rip]
	jnb	.L185
.L183:
	movzx	eax, BYTE PTR _x_pc0_l2[rip]
	test	al, al
	jne	.L185
	movzx	eax, BYTE PTR _x_pc0_l0[rip]
	test	al, al
	jne	.L185
	movzx	eax, BYTE PTR _x_pc0_l1[rip]
	test	al, al
	jne	.L185
	movzx	eax, BYTE PTR pc0_l2[rip]
	test	al, al
	je	.L185
	movzx	eax, BYTE PTR pc0_l0[rip]
	test	al, al
	jne	.L185
	movzx	eax, BYTE PTR pc0_l1[rip]
	test	al, al
	je	.L59
.L185:
	movss	xmm1, DWORD PTR pc0_x[rip]
	movss	xmm0, DWORD PTR .LC4[rip]
	comiss	xmm0, xmm1
	jb	.L186
	movss	xmm0, DWORD PTR pc0_x[rip]
	movss	xmm1, DWORD PTR _x_pc0_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L186
	ucomiss	xmm0, xmm1
	je	.L188
.L186:
	movzx	eax, BYTE PTR pc0_l2[rip]
	test	al, al
	je	.L188
	movzx	eax, BYTE PTR pc0_l0[rip]
	test	al, al
	jne	.L188
	movzx	eax, BYTE PTR pc0_l1[rip]
	test	al, al
	jne	.L188
	movzx	eax, BYTE PTR _x_pc0_l2[rip]
	test	al, al
	jne	.L188
	movzx	eax, BYTE PTR _x_pc0_l1[rip]
	test	al, al
	je	.L188
	movzx	eax, BYTE PTR _x_pc0_l0[rip]
	test	al, al
	je	.L59
.L188:
	movss	xmm0, DWORD PTR _x_pc0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L190
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L190
	movzx	eax, BYTE PTR pc0_evt1[rip]
	test	al, al
	je	.L190
	movzx	eax, BYTE PTR pc0_evt0[rip]
	test	al, al
	jne	.L190
	movzx	eax, BYTE PTR _x_pc0_l2[rip]
	test	al, al
	je	.L190
	movzx	eax, BYTE PTR _x_pc0_l1[rip]
	test	al, al
	je	.L190
	movzx	eax, BYTE PTR _x_pc0_l0[rip]
	test	al, al
	je	.L192
.L190:
	movzx	eax, BYTE PTR pc0_l2[rip]
	test	al, al
	jne	.L192
	movzx	eax, BYTE PTR pc0_l1[rip]
	test	al, al
	je	.L192
	movzx	eax, BYTE PTR pc0_l0[rip]
	test	al, al
	jne	.L192
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L192
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L192
	movzx	eax, BYTE PTR pc0_evt0[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR pc0_evt1[rip]
	test	al, al
	jne	.L59
.L192:
	movzx	eax, BYTE PTR _x_pc0_l2[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR _x_pc0_l0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_pc0_l1[rip]
	test	al, al
	je	.L194
.L193:
	movzx	eax, BYTE PTR _x_pc0_l2[rip]
	test	al, al
	jne	.L195
	movzx	eax, BYTE PTR _x_pc0_l0[rip]
	test	al, al
	je	.L195
	movzx	eax, BYTE PTR _x_pc0_l1[rip]
	test	al, al
	jne	.L194
.L195:
	movzx	eax, BYTE PTR pc0_l2[rip]
	test	al, al
	je	.L194
	movzx	eax, BYTE PTR pc0_l1[rip]
	test	al, al
	je	.L194
	movzx	eax, BYTE PTR pc0_l0[rip]
	test	al, al
	jne	.L194
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L194
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L194
	movzx	eax, BYTE PTR pc0_evt0[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR pc0_evt1[rip]
	test	al, al
	jne	.L59
.L194:
	movss	xmm0, DWORD PTR pc0_x[rip]
	movss	xmm1, DWORD PTR _x_pc0_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L196
	ucomiss	xmm0, xmm1
	jne	.L196
	movzx	eax, BYTE PTR pc0_evt0[rip]
	test	al, al
	je	.L196
	movzx	eax, BYTE PTR pc0_evt1[rip]
	test	al, al
	je	.L196
	movss	xmm0, DWORD PTR pc0_x[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L198
.L196:
	movzx	eax, BYTE PTR pc0_l2[rip]
	test	al, al
	je	.L198
	movzx	eax, BYTE PTR pc0_l1[rip]
	test	al, al
	je	.L198
	movzx	eax, BYTE PTR pc0_l0[rip]
	test	al, al
	jne	.L198
	movzx	eax, BYTE PTR _x_pc0_l2[rip]
	test	al, al
	jne	.L198
	movzx	eax, BYTE PTR _x_pc0_l0[rip]
	test	al, al
	je	.L198
	movzx	eax, BYTE PTR _x_pc0_l1[rip]
	test	al, al
	jne	.L59
.L198:
	movss	xmm0, DWORD PTR _x_pc0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L199
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L199
	movzx	eax, BYTE PTR pc0_evt0[rip]
	test	al, al
	je	.L199
	movzx	eax, BYTE PTR pc0_evt1[rip]
	test	al, al
	jne	.L199
	movss	xmm1, DWORD PTR pc0_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	jnb	.L201
.L199:
	movzx	eax, BYTE PTR pc0_l2[rip]
	test	al, al
	je	.L201
	movzx	eax, BYTE PTR pc0_l1[rip]
	test	al, al
	je	.L201
	movzx	eax, BYTE PTR pc0_l0[rip]
	test	al, al
	jne	.L201
	movzx	eax, BYTE PTR _x_pc0_l2[rip]
	test	al, al
	jne	.L201
	movzx	eax, BYTE PTR _x_pc0_l0[rip]
	test	al, al
	je	.L201
	movzx	eax, BYTE PTR _x_pc0_l1[rip]
	test	al, al
	je	.L59
.L201:
	movzx	eax, BYTE PTR pc0_evt0[rip]
	test	al, al
	je	.L202
	movzx	eax, BYTE PTR pc0_evt1[rip]
	test	al, al
	je	.L202
	movss	xmm0, DWORD PTR pc0_x[rip]
	movss	xmm1, DWORD PTR _x_pc0_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L202
	ucomiss	xmm0, xmm1
	jne	.L202
	movzx	eax, BYTE PTR _x_pc0_l2[rip]
	test	al, al
	je	.L204
	movzx	eax, BYTE PTR _x_pc0_l0[rip]
	test	al, al
	je	.L204
	movzx	eax, BYTE PTR _x_pc0_l1[rip]
	test	al, al
	je	.L205
.L204:
	movzx	eax, BYTE PTR _x_pc0_l2[rip]
	test	al, al
	jne	.L202
	movzx	eax, BYTE PTR _x_pc0_l0[rip]
	test	al, al
	je	.L202
	movzx	eax, BYTE PTR _x_pc0_l1[rip]
	test	al, al
	jne	.L205
.L202:
	movzx	eax, BYTE PTR pc0_l2[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR pc0_l0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR pc0_l1[rip]
	test	al, al
	jne	.L205
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L205
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L205
	movzx	eax, BYTE PTR pc0_evt0[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR pc0_evt1[rip]
	test	al, al
	jne	.L59
.L205:
	movss	xmm0, DWORD PTR pc0_x[rip]
	comiss	xmm0, DWORD PTR .LC3[rip]
	jnb	.L206
	movzx	eax, BYTE PTR pc0_l2[rip]
	test	al, al
	jne	.L206
	movzx	eax, BYTE PTR pc0_l0[rip]
	test	al, al
	je	.L206
	movzx	eax, BYTE PTR pc0_l1[rip]
	test	al, al
	jne	.L206
	movzx	eax, BYTE PTR _x_pc0_l2[rip]
	test	al, al
	jne	.L206
	movzx	eax, BYTE PTR _x_pc0_l0[rip]
	test	al, al
	je	.L206
	movzx	eax, BYTE PTR _x_pc0_l1[rip]
	test	al, al
	jne	.L59
.L206:
	movss	xmm1, DWORD PTR pc0_x[rip]
	movss	xmm0, DWORD PTR .LC4[rip]
	comiss	xmm0, xmm1
	jnb	.L207
	movzx	eax, BYTE PTR pc0_l2[rip]
	test	al, al
	jne	.L207
	movzx	eax, BYTE PTR pc0_l0[rip]
	test	al, al
	je	.L207
	movzx	eax, BYTE PTR pc0_l1[rip]
	test	al, al
	jne	.L207
	movzx	eax, BYTE PTR _x_pc0_l2[rip]
	test	al, al
	je	.L207
	movzx	eax, BYTE PTR _x_pc0_l0[rip]
	test	al, al
	je	.L207
	movzx	eax, BYTE PTR _x_pc0_l1[rip]
	test	al, al
	je	.L59
.L207:
	movzx	eax, BYTE PTR _x_pc0_l2[rip]
	test	al, al
	jne	.L208
	movzx	eax, BYTE PTR _x_pc0_l0[rip]
	test	al, al
	je	.L208
	movzx	eax, BYTE PTR _x_pc0_l1[rip]
	test	al, al
	jne	.L209
.L208:
	movzx	eax, BYTE PTR pc0_l2[rip]
	test	al, al
	jne	.L209
	movzx	eax, BYTE PTR pc0_l0[rip]
	test	al, al
	je	.L209
	movzx	eax, BYTE PTR pc0_l1[rip]
	test	al, al
	je	.L209
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L209
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L209
	movzx	eax, BYTE PTR pc0_evt0[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR pc0_evt1[rip]
	test	al, al
	jne	.L59
.L209:
	movzx	eax, BYTE PTR _x_pc0_l2[rip]
	test	al, al
	jne	.L210
	movzx	eax, BYTE PTR _x_pc0_l0[rip]
	test	al, al
	jne	.L210
	movzx	eax, BYTE PTR _x_pc0_l1[rip]
	test	al, al
	je	.L211
.L210:
	movzx	eax, BYTE PTR pc0_l2[rip]
	test	al, al
	je	.L211
	movzx	eax, BYTE PTR pc0_l0[rip]
	test	al, al
	je	.L211
	movzx	eax, BYTE PTR pc0_l1[rip]
	test	al, al
	jne	.L211
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L211
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L211
	movzx	eax, BYTE PTR pc0_evt0[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR pc0_evt1[rip]
	test	al, al
	jne	.L59
.L211:
	movzx	eax, BYTE PTR _x_a2_evt0[rip]
	test	al, al
	jne	.L212
	movzx	eax, BYTE PTR _x_a2_evt1[rip]
	test	al, al
	je	.L213
.L212:
	movzx	eax, BYTE PTR _x_a2_evt1[rip]
	test	al, al
	je	.L214
	movzx	eax, BYTE PTR _x_a2_evt0[rip]
	test	al, al
	je	.L213
.L214:
	movzx	eax, BYTE PTR _x_a2_evt0[rip]
	test	al, al
	je	.L59
	movzx	eax, BYTE PTR _x_a2_evt1[rip]
	test	al, al
	jne	.L59
.L213:
	movzx	eax, BYTE PTR a2_l[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_a2_l[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	jne	.L215
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L59
	movzx	eax, BYTE PTR a2_evt0[rip]
	test	al, al
	jne	.L215
	movzx	eax, BYTE PTR a2_evt1[rip]
	test	al, al
	je	.L59
.L215:
	mov	eax, DWORD PTR _x_id[rip]
	test	eax, eax
	jne	.L217
	movzx	eax, BYTE PTR a2_evt1[rip]
	test	al, al
	je	.L217
	movzx	eax, BYTE PTR a2_evt0[rip]
	test	al, al
	jne	.L217
	movzx	eax, BYTE PTR _x_a2_l[rip]
	test	al, al
	je	.L217
	mov	eax, DWORD PTR id[rip]
	cmp	eax, 3
	je	.L218
.L217:
	movzx	eax, BYTE PTR a2_l[rip]
	test	al, al
	jne	.L218
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L218
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L218
	movzx	eax, BYTE PTR a2_evt0[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR a2_evt1[rip]
	test	al, al
	jne	.L59
.L218:
	movzx	eax, BYTE PTR a2_evt0[rip]
	test	al, al
	je	.L219
	movzx	eax, BYTE PTR a2_evt1[rip]
	test	al, al
	jne	.L219
	movzx	eax, BYTE PTR _x_a2_l[rip]
	test	al, al
	jne	.L219
	mov	eax, DWORD PTR _x_id[rip]
	cmp	eax, 3
	je	.L220
.L219:
	movzx	eax, BYTE PTR a2_l[rip]
	test	al, al
	je	.L220
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L220
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L220
	movzx	eax, BYTE PTR a2_evt0[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR a2_evt1[rip]
	test	al, al
	jne	.L59
.L220:
	movzx	eax, BYTE PTR _x_a1_evt0[rip]
	test	al, al
	jne	.L221
	movzx	eax, BYTE PTR _x_a1_evt1[rip]
	test	al, al
	je	.L222
.L221:
	movzx	eax, BYTE PTR _x_a1_evt1[rip]
	test	al, al
	je	.L223
	movzx	eax, BYTE PTR _x_a1_evt0[rip]
	test	al, al
	je	.L222
.L223:
	movzx	eax, BYTE PTR _x_a1_evt0[rip]
	test	al, al
	je	.L59
	movzx	eax, BYTE PTR _x_a1_evt1[rip]
	test	al, al
	jne	.L59
.L222:
	movzx	eax, BYTE PTR a1_l[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_a1_l[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	jne	.L224
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L59
	movzx	eax, BYTE PTR a1_evt0[rip]
	test	al, al
	jne	.L224
	movzx	eax, BYTE PTR a1_evt1[rip]
	test	al, al
	je	.L59
.L224:
	mov	eax, DWORD PTR _x_id[rip]
	test	eax, eax
	jne	.L226
	movzx	eax, BYTE PTR a1_evt1[rip]
	test	al, al
	je	.L226
	movzx	eax, BYTE PTR a1_evt0[rip]
	test	al, al
	jne	.L226
	movzx	eax, BYTE PTR _x_a1_l[rip]
	test	al, al
	je	.L226
	mov	eax, DWORD PTR id[rip]
	cmp	eax, 2
	je	.L227
.L226:
	movzx	eax, BYTE PTR a1_l[rip]
	test	al, al
	jne	.L227
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L227
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L227
	movzx	eax, BYTE PTR a1_evt0[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR a1_evt1[rip]
	test	al, al
	jne	.L59
.L227:
	movzx	eax, BYTE PTR a1_evt0[rip]
	test	al, al
	je	.L228
	movzx	eax, BYTE PTR a1_evt1[rip]
	test	al, al
	jne	.L228
	movzx	eax, BYTE PTR _x_a1_l[rip]
	test	al, al
	jne	.L228
	mov	eax, DWORD PTR _x_id[rip]
	cmp	eax, 2
	je	.L229
.L228:
	movzx	eax, BYTE PTR a1_l[rip]
	test	al, al
	je	.L229
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L229
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L229
	movzx	eax, BYTE PTR a1_evt0[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR a1_evt1[rip]
	test	al, al
	jne	.L59
.L229:
	movzx	eax, BYTE PTR _x_a0_evt0[rip]
	test	al, al
	jne	.L230
	movzx	eax, BYTE PTR _x_a0_evt1[rip]
	test	al, al
	je	.L231
.L230:
	movzx	eax, BYTE PTR _x_a0_evt1[rip]
	test	al, al
	je	.L232
	movzx	eax, BYTE PTR _x_a0_evt0[rip]
	test	al, al
	je	.L231
.L232:
	movzx	eax, BYTE PTR _x_a0_evt0[rip]
	test	al, al
	je	.L59
	movzx	eax, BYTE PTR _x_a0_evt1[rip]
	test	al, al
	jne	.L59
.L231:
	movzx	eax, BYTE PTR a0_l[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_a0_l[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	jne	.L233
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L59
	movzx	eax, BYTE PTR a0_evt0[rip]
	test	al, al
	jne	.L233
	movzx	eax, BYTE PTR a0_evt1[rip]
	test	al, al
	je	.L59
.L233:
	movzx	eax, BYTE PTR a0_evt1[rip]
	test	al, al
	je	.L235
	movzx	eax, BYTE PTR a0_evt0[rip]
	test	al, al
	jne	.L235
	movzx	eax, BYTE PTR _x_a0_l[rip]
	test	al, al
	je	.L235
	mov	eax, DWORD PTR id[rip]
	cmp	eax, 1
	jne	.L235
	mov	eax, DWORD PTR _x_id[rip]
	test	eax, eax
	je	.L236
.L235:
	movzx	eax, BYTE PTR a0_l[rip]
	test	al, al
	jne	.L236
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L236
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L236
	movzx	eax, BYTE PTR a0_evt0[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR a0_evt1[rip]
	test	al, al
	jne	.L59
.L236:
	mov	eax, DWORD PTR _x_id[rip]
	cmp	eax, 1
	jne	.L237
	movzx	eax, BYTE PTR a0_evt0[rip]
	test	al, al
	je	.L237
	movzx	eax, BYTE PTR a0_evt1[rip]
	test	al, al
	jne	.L237
	movzx	eax, BYTE PTR _x_a0_l[rip]
	test	al, al
	je	.L238
.L237:
	movzx	eax, BYTE PTR a0_l[rip]
	test	al, al
	je	.L238
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L238
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L238
	movzx	eax, BYTE PTR a0_evt0[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR a0_evt1[rip]
	test	al, al
	jne	.L59
.L238:
	movzx	eax, BYTE PTR c_initial[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_c_initial[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	jne	.L239
	movzx	eax, BYTE PTR c_move[rip]
	test	al, al
	je	.L59
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L59
.L239:
	mov	eax, DWORD PTR id[rip]
	test	eax, eax
	jne	.L241
	mov	eax, DWORD PTR _x_id[rip]
	cmp	eax, 1
	jne	.L241
	movzx	eax, BYTE PTR _x_c_initial[rip]
	test	al, al
	je	.L242
.L241:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L242
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L242
	movzx	eax, BYTE PTR c_move[rip]
	test	al, al
	je	.L242
	movzx	eax, BYTE PTR c_initial[rip]
	test	al, al
	jne	.L59
.L242:
	movzx	eax, BYTE PTR _x_c_initial[rip]
	test	al, al
	je	.L243
	movzx	eax, BYTE PTR c_move[rip]
	test	al, al
	je	.L243
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L243
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L243
	movzx	eax, BYTE PTR c_initial[rip]
	test	al, al
	je	.L59
.L243:
	mov	eax, DWORD PTR _x_id[rip]
	cmp	eax, 1
	je	.L244
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L244
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L244
	mov	eax, DWORD PTR id[rip]
	cmp	eax, 2
	jle	.L244
	movzx	eax, BYTE PTR _x_c_initial[rip]
	test	al, al
	jne	.L244
	movzx	eax, BYTE PTR c_initial[rip]
	test	al, al
	je	.L59
.L244:
	mov	eax, DWORD PTR _x_id[rip]
	cmp	eax, 1
	je	.L245
	movzx	eax, BYTE PTR _x_c_initial[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR c_initial[rip]
	test	al, al
	jne	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L245
	mov	eax, DWORD PTR id[rip]
	cmp	eax, 2
	jle	.L59
.L245:
	movss	xmm0, DWORD PTR _x_delta[rip]
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jb	.L59
	mov	eax, DWORD PTR _x_id[rip]
	cmp	eax, 2
	je	.L247
	mov	eax, DWORD PTR _x_id[rip]
	cmp	eax, 1
	je	.L247
	mov	eax, DWORD PTR _x_id[rip]
	test	eax, eax
	jne	.L59
.L247:
	mov	edx, DWORD PTR id[rip]
	mov	eax, DWORD PTR _x_id[rip]
	cmp	edx, eax
	je	.L248
	movzx	eax, BYTE PTR pc2_evt0[rip]
	test	al, al
	jne	.L248
	movzx	eax, BYTE PTR pc2_evt1[rip]
	test	al, al
	jne	.L248
	movzx	eax, BYTE PTR pc1_evt0[rip]
	test	al, al
	jne	.L248
	movzx	eax, BYTE PTR pc1_evt1[rip]
	test	al, al
	jne	.L248
	movzx	eax, BYTE PTR pc0_evt0[rip]
	test	al, al
	jne	.L248
	movzx	eax, BYTE PTR pc0_evt1[rip]
	test	al, al
	jne	.L248
	movzx	eax, BYTE PTR a2_evt0[rip]
	test	al, al
	jne	.L248
	movzx	eax, BYTE PTR a2_evt1[rip]
	test	al, al
	jne	.L248
	movzx	eax, BYTE PTR a1_evt0[rip]
	test	al, al
	jne	.L248
	movzx	eax, BYTE PTR a1_evt1[rip]
	test	al, al
	jne	.L248
	movzx	eax, BYTE PTR c_move[rip]
	test	al, al
	jne	.L248
	movzx	eax, BYTE PTR a0_evt0[rip]
	test	al, al
	jne	.L248
	movzx	eax, BYTE PTR a0_evt1[rip]
	test	al, al
	je	.L59
.L248:
	movzx	eax, BYTE PTR a0_evt1[rip]
	test	al, al
	je	.L249
	movzx	eax, BYTE PTR a0_evt0[rip]
	test	al, al
	jne	.L249
	mov	eax, 1
	jmp	.L250
.L249:
	mov	eax, 0
.L250:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR pc0_evt1[rip]
	test	al, al
	je	.L251
	movzx	eax, BYTE PTR pc0_evt0[rip]
	test	al, al
	jne	.L251
	mov	eax, 1
	jmp	.L252
.L251:
	mov	eax, 0
.L252:
	and	eax, 1
	xor	eax, edx
	test	al, al
	jne	.L253
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L253
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L59
.L253:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L255
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L255
	movzx	eax, BYTE PTR a0_evt0[rip]
	test	al, al
	je	.L256
	movzx	eax, BYTE PTR a0_evt1[rip]
	test	al, al
	jne	.L256
	mov	eax, 1
	jmp	.L257
.L256:
	mov	eax, 0
.L257:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR pc0_evt0[rip]
	test	al, al
	je	.L258
	movzx	eax, BYTE PTR pc0_evt1[rip]
	test	al, al
	jne	.L258
	mov	eax, 1
	jmp	.L259
.L258:
	mov	eax, 0
.L259:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L59
.L255:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L260
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L260
	movzx	eax, BYTE PTR a1_evt1[rip]
	test	al, al
	je	.L261
	movzx	eax, BYTE PTR a1_evt0[rip]
	test	al, al
	jne	.L261
	mov	eax, 1
	jmp	.L262
.L261:
	mov	eax, 0
.L262:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR pc1_evt1[rip]
	test	al, al
	je	.L263
	movzx	eax, BYTE PTR pc1_evt0[rip]
	test	al, al
	jne	.L263
	mov	eax, 1
	jmp	.L264
.L263:
	mov	eax, 0
.L264:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L59
.L260:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L265
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L265
	movzx	eax, BYTE PTR a1_evt0[rip]
	test	al, al
	je	.L266
	movzx	eax, BYTE PTR a1_evt1[rip]
	test	al, al
	jne	.L266
	mov	eax, 1
	jmp	.L267
.L266:
	mov	eax, 0
.L267:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR pc1_evt0[rip]
	test	al, al
	je	.L268
	movzx	eax, BYTE PTR pc1_evt1[rip]
	test	al, al
	jne	.L268
	mov	eax, 1
	jmp	.L269
.L268:
	mov	eax, 0
.L269:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L59
.L265:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L270
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L270
	movzx	eax, BYTE PTR a2_evt1[rip]
	test	al, al
	je	.L271
	movzx	eax, BYTE PTR a2_evt0[rip]
	test	al, al
	jne	.L271
	mov	eax, 1
	jmp	.L272
.L271:
	mov	eax, 0
.L272:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR pc2_evt1[rip]
	test	al, al
	je	.L273
	movzx	eax, BYTE PTR pc2_evt0[rip]
	test	al, al
	jne	.L273
	mov	eax, 1
	jmp	.L274
.L273:
	mov	eax, 0
.L274:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L59
.L270:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L275
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L275
	movzx	eax, BYTE PTR a2_evt0[rip]
	test	al, al
	je	.L276
	movzx	eax, BYTE PTR a2_evt1[rip]
	test	al, al
	jne	.L276
	mov	eax, 1
	jmp	.L277
.L276:
	mov	eax, 0
.L277:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR pc2_evt0[rip]
	test	al, al
	je	.L278
	movzx	eax, BYTE PTR pc2_evt1[rip]
	test	al, al
	jne	.L278
	mov	eax, 1
	jmp	.L279
.L278:
	mov	eax, 0
.L279:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L59
.L275:
	movss	xmm0, DWORD PTR delta[rip]
	movss	xmm1, DWORD PTR _x__diverge_delta[rip]
	ucomiss	xmm0, xmm1
	jp	.L317
	ucomiss	xmm0, xmm1
	je	.L280
.L317:
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	movss	xmm1, DWORD PTR .LC5[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L59
.L280:
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	movss	xmm1, DWORD PTR .LC5[rip]
	comiss	xmm0, xmm1
	jnb	.L282
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x__diverge_delta[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L59
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L59
.L282:
	mov	eax, 1
	jmp	.L284
.L59:
	mov	eax, 0
.L284:
	mov	DWORD PTR -4[rbp], eax
	movzx	eax, BYTE PTR _x_pc2_l2[rip]
	mov	BYTE PTR pc2_l2[rip], al
	movzx	eax, BYTE PTR _x_pc2_l1[rip]
	mov	BYTE PTR pc2_l1[rip], al
	movzx	eax, BYTE PTR _x_a1_evt1[rip]
	mov	BYTE PTR a1_evt1[rip], al
	movzx	eax, BYTE PTR _x_a2_l[rip]
	mov	BYTE PTR a2_l[rip], al
	movzx	eax, BYTE PTR _x_a1_evt0[rip]
	mov	BYTE PTR a1_evt0[rip], al
	movzx	eax, BYTE PTR _x_pc1_l0[rip]
	mov	BYTE PTR pc1_l0[rip], al
	movzx	eax, BYTE PTR _x_a0_evt1[rip]
	mov	BYTE PTR a0_evt1[rip], al
	movzx	eax, BYTE PTR _x_pc2_l0[rip]
	mov	BYTE PTR pc2_l0[rip], al
	movzx	eax, BYTE PTR _x_pc2_evt1[rip]
	mov	BYTE PTR pc2_evt1[rip], al
	movzx	eax, BYTE PTR _x_a0_evt0[rip]
	mov	BYTE PTR a0_evt0[rip], al
	movzx	eax, BYTE PTR _x_a1_l[rip]
	mov	BYTE PTR a1_l[rip], al
	movss	xmm0, DWORD PTR _x_delta[rip]
	movss	DWORD PTR delta[rip], xmm0
	movzx	eax, BYTE PTR _x_pc0_l2[rip]
	mov	BYTE PTR pc0_l2[rip], al
	movzx	eax, BYTE PTR _x_pc2_evt0[rip]
	mov	BYTE PTR pc2_evt0[rip], al
	movss	xmm0, DWORD PTR _x_pc1_x[rip]
	movss	DWORD PTR pc1_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_pc0_x[rip]
	movss	DWORD PTR pc0_x[rip], xmm0
	movzx	eax, BYTE PTR _x_c_initial[rip]
	mov	BYTE PTR c_initial[rip], al
	movzx	eax, BYTE PTR _x_pc0_evt0[rip]
	mov	BYTE PTR pc0_evt0[rip], al
	movzx	eax, BYTE PTR _x_pc0_evt1[rip]
	mov	BYTE PTR pc0_evt1[rip], al
	movzx	eax, BYTE PTR _x_pc0_l1[rip]
	mov	BYTE PTR pc0_l1[rip], al
	movzx	eax, BYTE PTR _x_a0_l[rip]
	mov	BYTE PTR a0_l[rip], al
	mov	eax, DWORD PTR _x_id[rip]
	mov	DWORD PTR id[rip], eax
	movzx	eax, BYTE PTR _x_pc1_evt0[rip]
	mov	BYTE PTR pc1_evt0[rip], al
	movzx	eax, BYTE PTR _x_c_move[rip]
	mov	BYTE PTR c_move[rip], al
	movzx	eax, BYTE PTR _x_pc1_evt1[rip]
	mov	BYTE PTR pc1_evt1[rip], al
	movzx	eax, BYTE PTR _x_a2_evt0[rip]
	mov	BYTE PTR a2_evt0[rip], al
	movzx	eax, BYTE PTR _x_pc1_l1[rip]
	mov	BYTE PTR pc1_l1[rip], al
	movzx	eax, BYTE PTR _x_a2_evt1[rip]
	mov	BYTE PTR a2_evt1[rip], al
	movzx	eax, BYTE PTR _x_pc0_l0[rip]
	mov	BYTE PTR pc0_l0[rip], al
	movzx	eax, BYTE PTR _x_pc1_l2[rip]
	mov	BYTE PTR pc1_l2[rip], al
	movss	xmm0, DWORD PTR _x__diverge_delta[rip]
	movss	DWORD PTR _diverge_delta[rip], xmm0
	movss	xmm0, DWORD PTR _x_pc2_x[rip]
	movss	DWORD PTR pc2_x[rip], xmm0
.L54:
	cmp	DWORD PTR -4[rbp], 0
	jne	.L285
	mov	eax, 0
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	main, .-main
	.section	.rodata
	.align 4
.LC2:
	.long	1112014848
	.align 4
.LC3:
	.long	1103626240
	.align 4
.LC4:
	.long	1103101952
	.align 4
.LC5:
	.long	1065353216
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"208490.c"
	.text
	.align	2
	.global	__VERIFIER_nondet_bool
	.syntax unified
	.arm
	.fpu softvfp
	.type	__VERIFIER_nondet_bool, %function
__VERIFIER_nondet_bool:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	mov	r0, r3
	pop	{fp, pc}
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.comm	pc2_l2,1,1
	.comm	_x_pc2_l2,1,1
	.comm	pc2_l1,1,1
	.comm	_x_pc2_l1,1,1
	.comm	a1_evt1,1,1
	.comm	_x_a1_evt1,1,1
	.comm	a2_l,1,1
	.comm	_x_a2_l,1,1
	.comm	a1_evt0,1,1
	.comm	_x_a1_evt0,1,1
	.comm	pc1_l0,1,1
	.comm	_x_pc1_l0,1,1
	.comm	a0_evt1,1,1
	.comm	_x_a0_evt1,1,1
	.comm	pc2_l0,1,1
	.comm	_x_pc2_l0,1,1
	.comm	pc2_evt1,1,1
	.comm	_x_pc2_evt1,1,1
	.comm	a0_evt0,1,1
	.comm	_x_a0_evt0,1,1
	.comm	a1_l,1,1
	.comm	_x_a1_l,1,1
	.comm	delta,4,4
	.comm	_x_delta,4,4
	.comm	pc0_l2,1,1
	.comm	_x_pc0_l2,1,1
	.comm	pc2_evt0,1,1
	.comm	_x_pc2_evt0,1,1
	.comm	pc1_x,4,4
	.comm	_x_pc1_x,4,4
	.comm	pc0_x,4,4
	.comm	_x_pc0_x,4,4
	.comm	c_initial,1,1
	.comm	_x_c_initial,1,1
	.comm	pc0_evt0,1,1
	.comm	_x_pc0_evt0,1,1
	.comm	pc0_evt1,1,1
	.comm	_x_pc0_evt1,1,1
	.comm	pc0_l1,1,1
	.comm	_x_pc0_l1,1,1
	.comm	a0_l,1,1
	.comm	_x_a0_l,1,1
	.comm	id,4,4
	.comm	_x_id,4,4
	.comm	pc1_evt0,1,1
	.comm	_x_pc1_evt0,1,1
	.comm	c_move,1,1
	.comm	_x_c_move,1,1
	.comm	pc1_evt1,1,1
	.comm	_x_pc1_evt1,1,1
	.comm	a2_evt0,1,1
	.comm	_x_a2_evt0,1,1
	.comm	pc1_l1,1,1
	.comm	_x_pc1_l1,1,1
	.comm	a2_evt1,1,1
	.comm	_x_a2_evt1,1,1
	.comm	pc0_l0,1,1
	.comm	_x_pc0_l0,1,1
	.comm	pc1_l2,1,1
	.comm	_x_pc1_l2,1,1
	.comm	_diverge_delta,4,4
	.comm	_x__diverge_delta,4,4
	.comm	pc2_x,4,4
	.comm	_x_pc2_x,4,4
	.global	__aeabi_fcmpeq
	.global	__aeabi_fcmpge
	.global	__aeabi_fcmple
	.global	__aeabi_f2d
	.global	__aeabi_dsub
	.global	__aeabi_dadd
	.global	__aeabi_dcmpeq
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, fp, lr}
	add	fp, sp, #20
	sub	sp, sp, #8
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+256
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+264
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+4
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+8
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+12
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+16
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+260
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+228
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+20
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+24
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L308+220
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+28
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+224
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L308+32
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L308+36
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+40
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+44
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+48
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+52
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+56
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L308+60
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+64
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+68
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+72
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+76
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+80
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+84
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+88
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+92
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L308+96
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L308+236
	str	r3, [r2]	@ float
	ldr	r3, .L308+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L308+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L308+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L308+236
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L308+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L6
	ldr	r3, .L308+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L6:
	ldr	r3, .L308+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L308+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L8:
	ldr	r3, .L308+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L9
	ldr	r3, .L308+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L9:
	ldr	r3, .L308+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L308+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L7:
	ldr	r3, .L308+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L10
	ldr	r3, .L308+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L10
	ldr	r3, .L308+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L11
.L10:
	ldr	r3, .L308+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L12
	ldr	r3, .L308+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L12
	ldr	r3, .L308+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L11
.L12:
	ldr	r3, .L308+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L13
	ldr	r3, .L308+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L13
	ldr	r3, .L308+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L11
.L13:
	ldr	r3, .L308+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L14
	ldr	r3, .L308+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L14
	ldr	r3, .L308+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L11
.L14:
	ldr	r3, .L308+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L15
	ldr	r3, .L308+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L15
	ldr	r3, .L308+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L11
.L15:
	ldr	r3, .L308+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L16
	ldr	r3, .L308+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L16
	ldr	r3, .L308+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L11
.L16:
	ldr	r3, .L308+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L308+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L308+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L11:
	ldr	r3, .L308+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L308+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L308+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L308+32
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L308+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L18
	ldr	r3, .L308+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L19
.L18:
	ldr	r3, .L308+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L20
	ldr	r3, .L308+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L19
.L20:
	ldr	r3, .L308+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L21
	ldr	r3, .L308+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L19
.L21:
	ldr	r3, .L308+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L308+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L19:
	ldr	r3, .L308+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L22
	ldr	r3, .L308+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L22
	ldr	r3, .L308+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L23
.L22:
	ldr	r3, .L308+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L24
	ldr	r3, .L308+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L24
	ldr	r3, .L308+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L23
.L24:
	ldr	r3, .L308+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L25
	ldr	r3, .L308+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L25
	ldr	r3, .L308+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L23
.L25:
	ldr	r3, .L308+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L26
	ldr	r3, .L308+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L26
	ldr	r3, .L308+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L23
.L26:
	ldr	r3, .L308+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L27
	ldr	r3, .L308+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L27
	ldr	r3, .L308+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L23
.L27:
	ldr	r3, .L308+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L28
	ldr	r3, .L308+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L28
	ldr	r3, .L308+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L23
.L28:
	ldr	r3, .L308+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L308+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L308+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L23:
	ldr	r3, .L308+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L308+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L308+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L308+36
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L308+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L30
	ldr	r3, .L308+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
.L30:
	ldr	r3, .L308+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L32
	ldr	r3, .L308+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
.L32:
	ldr	r3, .L308+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L33
	ldr	r3, .L308+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
.L33:
	ldr	r3, .L308+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L308+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L31:
	ldr	r3, .L308+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L34
	ldr	r3, .L308+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L34
	ldr	r3, .L308+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L35
.L34:
	ldr	r3, .L308+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L36
	ldr	r3, .L308+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L36
	ldr	r3, .L308+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
.L36:
	ldr	r3, .L308+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L37
	ldr	r3, .L308+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L37
	ldr	r3, .L308+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
.L37:
	ldr	r3, .L308+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L38
	ldr	r3, .L308+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L38
	ldr	r3, .L308+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
.L38:
	ldr	r3, .L308+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L39
	ldr	r3, .L308+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L39
	ldr	r3, .L308+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
.L39:
	ldr	r3, .L308+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L40
	ldr	r3, .L308+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L40
	ldr	r3, .L308+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
.L40:
	ldr	r3, .L308+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L308+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L308+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L35:
	ldr	r3, .L308+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L308+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L41
	ldr	r3, .L308+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L42
.L41:
	ldr	r3, .L308+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L43
	ldr	r3, .L308+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L42
.L43:
	ldr	r3, .L308+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L308+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L42:
	ldr	r3, .L308+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L308+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L44
	ldr	r3, .L308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L45
.L44:
	ldr	r3, .L308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L46
	ldr	r3, .L308+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L45
.L46:
	ldr	r3, .L308+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L45:
	ldr	r3, .L308+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L308+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L47
	ldr	r3, .L308+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L48
.L47:
	ldr	r3, .L308+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L49
	ldr	r3, .L308+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L48
.L49:
	ldr	r3, .L308+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L308+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L48:
	ldr	r3, .L308+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L308+220
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L308+60
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L51
	ldr	r3, .L308+60
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L51
	ldr	r3, .L308+60
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L4
.L51:
	ldr	r3, .L308+220
	ldr	r3, [r3]	@ float
	ldr	r2, .L308+96
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	mov	r3, #1
	b	.L53
.L4:
	mov	r3, #0
.L53:
	str	r3, [fp, #-24]
	b	.L54
.L309:
	.align	2
.L308:
	.word	a1_evt1
	.word	a2_l
	.word	a1_evt0
	.word	pc1_l0
	.word	a0_evt1
	.word	a0_evt0
	.word	a1_l
	.word	pc0_l2
	.word	pc1_x
	.word	pc0_x
	.word	c_initial
	.word	pc0_evt0
	.word	pc0_evt1
	.word	pc0_l1
	.word	a0_l
	.word	id
	.word	pc1_evt0
	.word	c_move
	.word	pc1_evt1
	.word	a2_evt0
	.word	pc1_l1
	.word	a2_evt1
	.word	pc0_l0
	.word	pc1_l2
	.word	_diverge_delta
	.word	_x_a1_evt1
	.word	_x_a2_l
	.word	_x_a1_evt0
	.word	_x_pc1_l0
	.word	_x_a0_evt1
	.word	_x_a0_evt0
	.word	_x_a1_l
	.word	_x_delta
	.word	_x_pc0_l2
	.word	_x_pc1_x
	.word	_x_pc0_x
	.word	_x_c_initial
	.word	_x_pc0_evt0
	.word	_x_pc0_evt1
	.word	_x_pc0_l1
	.word	_x_a0_l
	.word	_x_id
	.word	_x_pc1_evt0
	.word	_x_c_move
	.word	_x_pc1_evt1
	.word	_x_a2_evt0
	.word	_x_pc1_l1
	.word	_x_a2_evt1
	.word	_x_pc0_l0
	.word	_x_pc1_l2
	.word	_x__diverge_delta
	.word	_x_pc2_evt0
	.word	_x_pc2_evt1
	.word	1112014848
	.word	_x_pc2_x
	.word	delta
	.word	pc2_evt0
	.word	pc2_evt1
	.word	1103626240
	.word	pc2_x
	.word	1103101952
	.word	_x_pc2_l2
	.word	_x_pc2_l0
	.word	_x_pc2_l1
	.word	pc2_l2
	.word	pc2_l0
	.word	pc2_l1
.L276:
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+244
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+252
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+100
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+104
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+108
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+112
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+116
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+248
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+208
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+120
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+124
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L308+128
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+132
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+204
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L308+136
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L308+140
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+144
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+148
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+152
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+156
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+160
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L308+164
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+168
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+172
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+176
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+180
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+184
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+188
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+192
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L308+196
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L308+200
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L308+216
	str	r3, [r2]	@ float
	ldr	r3, .L308+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L55
	ldr	r3, .L308+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L56
.L55:
	ldr	r3, .L308+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L57
	ldr	r3, .L308+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L56
.L57:
	ldr	r3, .L308+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L58
	ldr	r3, .L308+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L56
.L58:
	ldr	r3, .L308+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L308+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L56:
	ldr	r3, .L308+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L60
	ldr	r3, .L308+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L60
	ldr	r3, .L308+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L60:
	ldr	r3, .L308+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L62
	ldr	r3, .L308+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L62
	ldr	r3, .L308+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L62:
	ldr	r3, .L308+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L308+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L308+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L63:
	ldr	r3, .L308+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L64
	ldr	r3, .L308+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L64
	ldr	r3, .L308+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L64:
	ldr	r3, .L308+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L65
	ldr	r3, .L308+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L65
	ldr	r3, .L308+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L65:
	ldr	r3, .L308+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L66
	ldr	r3, .L308+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L66
	ldr	r3, .L308+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L66:
	ldr	r3, .L308+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L308+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L308+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L61:
	ldr	r3, .L308+220
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L67
	ldr	r3, .L308+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L308+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L308+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L308+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L308+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L308+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L308+220
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L308+236
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L308+216
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L59
.L67:
	ldr	r3, .L308+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L308+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L69
	ldr	r3, .L308+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L308+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L69
	ldr	r3, .L308+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L308+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L69
	ldr	r3, .L308+220
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L308+236
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L308+216
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L70
.L69:
	ldr	r3, .L308+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L70
	ldr	r3, .L308+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L70:
	ldr	r3, .L308+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L71
	ldr	r3, .L308+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L71
	ldr	r3, .L308+236
	ldr	r3, [r3]	@ float
	ldr	r1, .L308+212
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L71
	ldr	r3, .L308+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L71
	ldr	r3, .L308+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L71
	ldr	r3, .L308+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L71
	ldr	r3, .L308+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L73
.L71:
	ldr	r3, .L308+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L73
	ldr	r3, .L308+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L73
	ldr	r3, .L308+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L73
	ldr	r3, .L308+220
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L73
	ldr	r3, .L308+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L308+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L73:
	ldr	r3, .L308+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L74
	ldr	r3, .L308+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L74
	ldr	r3, .L308+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L75
	ldr	r3, .L308+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L75
	ldr	r3, .L308+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L76
.L75:
	ldr	r3, .L308+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L74
	ldr	r3, .L308+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L74
	ldr	r3, .L308+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L76
.L74:
	ldr	r3, .L308+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L76
	ldr	r3, .L308+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L76
	ldr	r3, .L308+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L76
	ldr	r3, .L308+220
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L76
	ldr	r3, .L308+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L308+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L76:
	ldr	r3, .L308+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L77
	ldr	r3, .L308+236
	ldr	r3, [r3]	@ float
	ldr	r1, .L308+232
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L79
.L77:
	ldr	r3, .L308+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L79
	ldr	r3, .L308+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L79
	ldr	r3, .L308+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L79
	ldr	r3, .L308+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L79
	ldr	r3, .L308+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L79
	ldr	r3, .L308+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L79:
	ldr	r3, .L308+236
	ldr	r3, [r3]	@ float
	ldr	r1, .L308+240
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L80
	ldr	r3, .L308+236
	ldr	r3, [r3]	@ float
	ldr	r2, .L308+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L82
.L80:
	ldr	r3, .L308+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L82
	ldr	r3, .L308+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L82
	ldr	r3, .L308+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L82
	ldr	r3, .L308+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L82
	ldr	r3, .L308+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L82
	ldr	r3, .L308+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L82:
	ldr	r3, .L308+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L83
	ldr	r3, .L308+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L83
	ldr	r3, .L308+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L83
	ldr	r3, .L308+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L83
	ldr	r3, .L308+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L83
	ldr	r3, .L308+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L85
.L83:
	ldr	r3, .L308+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L85
	ldr	r3, .L308+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L85
	ldr	r3, .L308+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L85
	ldr	r3, .L308+220
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L85
	ldr	r3, .L308+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L308+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L85:
	ldr	r3, .L308+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L86
	ldr	r3, .L308+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L86
	ldr	r3, .L308+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L87
.L86:
	ldr	r3, .L308+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L88
	ldr	r3, .L308+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L88
	ldr	r3, .L308+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L87
.L88:
	ldr	r3, .L308+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L87
	ldr	r3, .L308+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L87
	ldr	r3, .L308+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L87
	ldr	r3, .L308+220
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L87
	ldr	r3, .L308+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L308+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L87:
	ldr	r3, .L308+236
	ldr	r3, [r3]	@ float
	ldr	r2, .L308+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L89
	ldr	r3, .L308+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L89
	ldr	r3, .L308+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L89
	ldr	r3, .L308+236
	ldr	r3, [r3]	@ float
	ldr	r1, .L308+212
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L91
.L89:
	ldr	r3, .L308+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L91
	ldr	r3, .L308+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L91
	ldr	r3, .L308+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L91
	ldr	r3, .L308+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L91
	ldr	r3, .L308+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L91
	ldr	r3, .L308+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L91:
	ldr	r3, .L308+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L92
	ldr	r3, .L308+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L92
	ldr	r3, .L308+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L92
	ldr	r3, .L308+236
	ldr	r3, [r3]	@ float
	ldr	r1, .L308+232
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L94
.L92:
	ldr	r3, .L308+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L94
	ldr	r3, .L308+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L94
	ldr	r3, .L308+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L94
	ldr	r3, .L308+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L94
	ldr	r3, .L308+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L94
	ldr	r3, .L308+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L94:
	ldr	r3, .L308+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L95
	ldr	r3, .L308+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L95
	ldr	r3, .L308+236
	ldr	r3, [r3]	@ float
	ldr	r2, .L308+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L95
	ldr	r3, .L308+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L97
	ldr	r3, .L308+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L97
	ldr	r3, .L308+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L98
.L97:
	ldr	r3, .L308+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L95
	ldr	r3, .L308+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L95
	ldr	r3, .L308+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L98
.L95:
	ldr	r3, .L308+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L98
	ldr	r3, .L308+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L98
	ldr	r3, .L308+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L98
	ldr	r3, .L308+220
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L98
	ldr	r3, .L308+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L308+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L98:
	ldr	r3, .L308+236
	ldr	r3, [r3]	@ float
	ldr	r1, .L308+232
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L99
	ldr	r3, .L308+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L99
	ldr	r3, .L308+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L99
	ldr	r3, .L308+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L99
	ldr	r3, .L308+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L99
	ldr	r3, .L308+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L99
	ldr	r3, .L308+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L99:
	ldr	r3, .L308+236
	ldr	r3, [r3]	@ float
	ldr	r1, .L308+240
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L100
	ldr	r3, .L308+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L100
	ldr	r3, .L308+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L100
	ldr	r3, .L308+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L100
	ldr	r3, .L308+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L100
	ldr	r3, .L308+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L100
	ldr	r3, .L308+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L100:
	ldr	r3, .L308+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L101
	ldr	r3, .L308+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L101
	ldr	r3, .L308+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L102
.L101:
	ldr	r3, .L308+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L102
	ldr	r3, .L308+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L102
	ldr	r3, .L308+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L102
	ldr	r3, .L310
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L102
	ldr	r3, .L310+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L310+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L102:
	ldr	r3, .L310+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L103
	ldr	r3, .L310+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L103
	ldr	r3, .L310+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L104
.L103:
	ldr	r3, .L310+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L104
	ldr	r3, .L310+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L104
	ldr	r3, .L310+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L104
	ldr	r3, .L310
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L104
	ldr	r3, .L310+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L310+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L104:
	ldr	r3, .L310+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L105
	ldr	r3, .L310+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L106
.L105:
	ldr	r3, .L310+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L107
	ldr	r3, .L310+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L106
.L107:
	ldr	r3, .L310+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L108
	ldr	r3, .L310+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L106
.L108:
	ldr	r3, .L310+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L310+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L106:
	ldr	r3, .L310+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L109
	ldr	r3, .L310+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L109
	ldr	r3, .L310+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L110
.L109:
	ldr	r3, .L310+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L111
	ldr	r3, .L310+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L111
	ldr	r3, .L310+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L110
.L111:
	ldr	r3, .L310+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L112
	ldr	r3, .L310+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L112
	ldr	r3, .L310+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L110
.L112:
	ldr	r3, .L310+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L113
	ldr	r3, .L310+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L113
	ldr	r3, .L310+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L110
.L113:
	ldr	r3, .L310+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L114
	ldr	r3, .L310+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L114
	ldr	r3, .L310+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L110
.L114:
	ldr	r3, .L310+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L115
	ldr	r3, .L310+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L115
	ldr	r3, .L310+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L110
.L115:
	ldr	r3, .L310+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L310+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L310+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L110:
	ldr	r3, .L310
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L116
	ldr	r3, .L310+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L310+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L310+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L310+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L310+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L310+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L310
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L310+68
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L310+72
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L59
.L116:
	ldr	r3, .L310+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L310+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L118
	ldr	r3, .L310+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L310+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L118
	ldr	r3, .L310+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L310+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L118
	ldr	r3, .L310
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L310+68
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L310+72
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L119
.L118:
	ldr	r3, .L310+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L119
	ldr	r3, .L310+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L119:
	ldr	r3, .L310+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L120
	ldr	r3, .L310+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L120
	ldr	r3, .L310+68
	ldr	r3, [r3]	@ float
	ldr	r1, .L310+92
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L120
	ldr	r3, .L310+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L120
	ldr	r3, .L310+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L120
	ldr	r3, .L310+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L120
	ldr	r3, .L310+72
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L122
.L120:
	ldr	r3, .L310+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L122
	ldr	r3, .L310+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L122
	ldr	r3, .L310+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L122
	ldr	r3, .L310
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L122
	ldr	r3, .L310+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L310+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L122:
	ldr	r3, .L310+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L123
	ldr	r3, .L310+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L123
	ldr	r3, .L310+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L124
	ldr	r3, .L310+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L124
	ldr	r3, .L310+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L125
.L124:
	ldr	r3, .L310+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L123
	ldr	r3, .L310+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L123
	ldr	r3, .L310+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L125
.L123:
	ldr	r3, .L310+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L125
	ldr	r3, .L310+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L125
	ldr	r3, .L310+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L125
	ldr	r3, .L310
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L125
	ldr	r3, .L310+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L310+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L125:
	ldr	r3, .L310+72
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L126
	ldr	r3, .L310+68
	ldr	r3, [r3]	@ float
	ldr	r1, .L310+100
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L128
.L126:
	ldr	r3, .L310+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L128
	ldr	r3, .L310+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L128
	ldr	r3, .L310+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L128
	ldr	r3, .L310+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L128
	ldr	r3, .L310+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L128
	ldr	r3, .L310+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L128:
	ldr	r3, .L310+68
	ldr	r3, [r3]	@ float
	ldr	r1, .L310+108
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L129
	ldr	r3, .L310+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L310+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L131
.L129:
	ldr	r3, .L310+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L131
	ldr	r3, .L310+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L131
	ldr	r3, .L310+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L131
	ldr	r3, .L310+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L131
	ldr	r3, .L310+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L131
	ldr	r3, .L310+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L131:
	ldr	r3, .L310+72
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L132
	ldr	r3, .L310+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L132
	ldr	r3, .L310+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L132
	ldr	r3, .L310+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L132
	ldr	r3, .L310+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L132
	ldr	r3, .L310+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L134
.L132:
	ldr	r3, .L310+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L134
	ldr	r3, .L310+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L134
	ldr	r3, .L310+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L134
	ldr	r3, .L310
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L134
	ldr	r3, .L310+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L310+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L134:
	ldr	r3, .L310+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L135
	ldr	r3, .L310+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L135
	ldr	r3, .L310+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L136
.L135:
	ldr	r3, .L310+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L137
	ldr	r3, .L310+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L137
	ldr	r3, .L310+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L136
.L137:
	ldr	r3, .L310+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L136
	ldr	r3, .L310+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L136
	ldr	r3, .L310+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L136
	ldr	r3, .L310
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L136
	ldr	r3, .L310+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L310+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L136:
	ldr	r3, .L310+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L310+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L138
	ldr	r3, .L310+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L138
	ldr	r3, .L310+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L138
	ldr	r3, .L310+68
	ldr	r3, [r3]	@ float
	ldr	r1, .L310+92
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L140
.L138:
	ldr	r3, .L310+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L140
	ldr	r3, .L310+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L140
	ldr	r3, .L310+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L140
	ldr	r3, .L310+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L140
	ldr	r3, .L310+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L140
	ldr	r3, .L310+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L140:
	ldr	r3, .L310+72
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L141
	ldr	r3, .L310+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L141
	ldr	r3, .L310+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L141
	ldr	r3, .L310+68
	ldr	r3, [r3]	@ float
	ldr	r1, .L310+100
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L143
.L141:
	ldr	r3, .L310+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L143
	ldr	r3, .L310+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L143
	ldr	r3, .L310+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L143
	ldr	r3, .L310+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L143
	ldr	r3, .L310+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L143
	ldr	r3, .L310+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L143:
	ldr	r3, .L310+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L144
	ldr	r3, .L310+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L144
	ldr	r3, .L310+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L310+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L144
	ldr	r3, .L310+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L146
	ldr	r3, .L310+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L146
	ldr	r3, .L310+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L147
.L146:
	ldr	r3, .L310+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L144
	ldr	r3, .L310+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L144
	ldr	r3, .L310+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L147
.L144:
	ldr	r3, .L310+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L147
	ldr	r3, .L310+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L147
	ldr	r3, .L310+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L147
	ldr	r3, .L310
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L147
	ldr	r3, .L310+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L310+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L147:
	ldr	r3, .L310+68
	ldr	r3, [r3]	@ float
	ldr	r1, .L310+100
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L148
	ldr	r3, .L310+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L148
	ldr	r3, .L310+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L148
	ldr	r3, .L310+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L148
	ldr	r3, .L310+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L148
	ldr	r3, .L310+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L148
	ldr	r3, .L310+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L148:
	ldr	r3, .L310+68
	ldr	r3, [r3]	@ float
	ldr	r1, .L310+108
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L149
	ldr	r3, .L310+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L149
	ldr	r3, .L310+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L149
	ldr	r3, .L310+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L149
	ldr	r3, .L310+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L149
	ldr	r3, .L310+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L149
	ldr	r3, .L310+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L149:
	ldr	r3, .L310+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L150
	ldr	r3, .L310+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L150
	ldr	r3, .L310+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L151
.L150:
	ldr	r3, .L310+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L151
	ldr	r3, .L310+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
	ldr	r3, .L310+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
	ldr	r3, .L310
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L151
	ldr	r3, .L310+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L310+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L151:
	ldr	r3, .L310+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L152
	ldr	r3, .L310+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L152
	ldr	r3, .L310+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L153
.L152:
	ldr	r3, .L310+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L153
	ldr	r3, .L310+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L153
	ldr	r3, .L310+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L153
	ldr	r3, .L310
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L153
	ldr	r3, .L310+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L310+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L153:
	ldr	r3, .L310+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L154
	ldr	r3, .L310+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L155
.L154:
	ldr	r3, .L310+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L156
	ldr	r3, .L310+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L155
.L156:
	ldr	r3, .L310+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L157
	ldr	r3, .L310+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L155
.L157:
	ldr	r3, .L310+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L310+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L155:
	ldr	r3, .L310+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L158
	ldr	r3, .L310+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L158
	b	.L311
.L312:
	.align	2
.L310:
	.word	delta
	.word	pc2_evt0
	.word	pc2_evt1
	.word	_x_pc2_l2
	.word	_x_pc2_l0
	.word	_x_pc2_l1
	.word	pc2_l2
	.word	pc2_l0
	.word	pc2_l1
	.word	_x_pc1_evt0
	.word	_x_pc1_evt1
	.word	_x_pc1_l2
	.word	_x_pc1_l0
	.word	_x_pc1_l1
	.word	pc1_l0
	.word	pc1_l1
	.word	pc1_l2
	.word	pc1_x
	.word	_x_pc1_x
	.word	pc1_evt0
	.word	pc1_evt1
	.word	_x_pc0_evt0
	.word	_x_pc0_evt1
	.word	1112014848
	.word	_x_pc0_x
	.word	1103626240
	.word	pc0_x
	.word	1103101952
	.word	_x_pc0_l2
	.word	_x_pc0_l0
	.word	_x_pc0_l1
	.word	pc0_l2
	.word	pc0_l0
	.word	pc0_l1
	.word	pc0_evt0
	.word	pc0_evt1
	.word	_x_a2_evt0
	.word	_x_a2_evt1
	.word	id
	.word	_x_a2_l
	.word	_x_id
	.word	a2_l
	.word	delta
	.word	a2_evt0
	.word	a2_evt1
	.word	_x_a1_evt0
.L311:
	ldr	r3, .L310+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L159
.L158:
	ldr	r3, .L310+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L160
	ldr	r3, .L310+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L160
	ldr	r3, .L310+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L159
.L160:
	ldr	r3, .L310+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L161
	ldr	r3, .L310+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L161
	ldr	r3, .L310+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L159
.L161:
	ldr	r3, .L310+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L162
	ldr	r3, .L310+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L162
	ldr	r3, .L310+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L159
.L162:
	ldr	r3, .L310+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L163
	ldr	r3, .L310+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L163
	ldr	r3, .L310+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L159
.L163:
	ldr	r3, .L310+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L164
	ldr	r3, .L310+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L164
	ldr	r3, .L310+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L159
.L164:
	ldr	r3, .L310+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L310+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L310+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L159:
	ldr	r3, .L310+168
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L165
	ldr	r3, .L310+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L310+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L310+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L310+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L310+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L310+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L310+168
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L310+104
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L310+96
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L59
.L165:
	ldr	r3, .L310+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L310+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L167
	ldr	r3, .L310+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L310+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L167
	ldr	r3, .L310+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L310+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L167
	ldr	r3, .L310+168
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L310+104
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L310+96
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L168
.L167:
	ldr	r3, .L310+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L168
	ldr	r3, .L310+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L168:
	ldr	r3, .L310+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L169
	ldr	r3, .L310+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L169
	ldr	r3, .L310+104
	ldr	r3, [r3]	@ float
	ldr	r1, .L310+92
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L169
	ldr	r3, .L310+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L169
	ldr	r3, .L310+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L169
	ldr	r3, .L310+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L169
	ldr	r3, .L310+96
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L171
.L169:
	ldr	r3, .L310+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L171
	ldr	r3, .L310+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L171
	ldr	r3, .L310+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L171
	ldr	r3, .L310+168
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L171
	ldr	r3, .L310+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L310+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L171:
	ldr	r3, .L310+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L172
	ldr	r3, .L310+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L172
	ldr	r3, .L310+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L173
	ldr	r3, .L310+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L173
	ldr	r3, .L310+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
.L173:
	ldr	r3, .L310+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L172
	ldr	r3, .L310+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L172
	ldr	r3, .L310+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
.L172:
	ldr	r3, .L310+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
	ldr	r3, .L310+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L174
	ldr	r3, .L310+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L174
	ldr	r3, .L310+168
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L174
	ldr	r3, .L310+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L310+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L174:
	ldr	r3, .L310+96
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L175
	ldr	r3, .L310+104
	ldr	r3, [r3]	@ float
	ldr	r1, .L310+100
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L177
.L175:
	ldr	r3, .L310+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L177
	ldr	r3, .L310+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L177
	ldr	r3, .L310+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L177
	ldr	r3, .L310+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L177
	ldr	r3, .L310+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L177
	ldr	r3, .L310+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L177:
	ldr	r3, .L310+104
	ldr	r3, [r3]	@ float
	ldr	r1, .L310+108
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L178
	ldr	r3, .L310+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L310+96
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L180
.L178:
	ldr	r3, .L310+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L180
	ldr	r3, .L310+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L180
	ldr	r3, .L310+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L180
	ldr	r3, .L310+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L180
	ldr	r3, .L310+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L180
	ldr	r3, .L310+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L180:
	ldr	r3, .L310+96
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L181
	ldr	r3, .L310+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L181
	ldr	r3, .L310+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L181
	ldr	r3, .L310+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L181
	ldr	r3, .L310+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L181
	ldr	r3, .L310+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L183
.L181:
	ldr	r3, .L310+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L183
	ldr	r3, .L310+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L183
	ldr	r3, .L310+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L183
	ldr	r3, .L310+168
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L183
	ldr	r3, .L310+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L310+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L183:
	ldr	r3, .L310+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L184
	ldr	r3, .L310+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L184
	ldr	r3, .L310+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L185
.L184:
	ldr	r3, .L310+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L186
	ldr	r3, .L310+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L186
	ldr	r3, .L310+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L185
.L186:
	ldr	r3, .L310+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L185
	ldr	r3, .L310+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L185
	ldr	r3, .L310+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L185
	ldr	r3, .L310+168
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L185
	ldr	r3, .L310+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L310+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L185:
	ldr	r3, .L310+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L310+96
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L187
	ldr	r3, .L310+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L187
	ldr	r3, .L310+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L187
	ldr	r3, .L310+104
	ldr	r3, [r3]	@ float
	ldr	r1, .L310+92
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L189
.L187:
	ldr	r3, .L310+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L189
	ldr	r3, .L310+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L189
	ldr	r3, .L310+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L189
	ldr	r3, .L310+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L189
	ldr	r3, .L310+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L189
	ldr	r3, .L310+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L189:
	ldr	r3, .L310+96
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L190
	ldr	r3, .L310+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L190
	ldr	r3, .L310+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L190
	ldr	r3, .L310+104
	ldr	r3, [r3]	@ float
	ldr	r1, .L310+100
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L192
.L190:
	ldr	r3, .L310+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L192
	ldr	r3, .L310+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L192
	ldr	r3, .L310+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L192
	ldr	r3, .L310+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L192
	ldr	r3, .L310+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L192
	ldr	r3, .L310+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L192:
	ldr	r3, .L310+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L310+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L310+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L310+96
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L310+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L310+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L310+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L196
.L195:
	ldr	r3, .L310+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L310+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L310+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L196
.L193:
	ldr	r3, .L310+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L196
	ldr	r3, .L310+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L196
	ldr	r3, .L310+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L196
	ldr	r3, .L310+168
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L196
	ldr	r3, .L310+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L310+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L196:
	ldr	r3, .L310+104
	ldr	r3, [r3]	@ float
	ldr	r1, .L310+100
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L197
	ldr	r3, .L310+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L197
	ldr	r3, .L310+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L197
	ldr	r3, .L310+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L197
	ldr	r3, .L310+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L197
	ldr	r3, .L310+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L197
	ldr	r3, .L310+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L197:
	ldr	r3, .L310+104
	ldr	r3, [r3]	@ float
	ldr	r1, .L310+108
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L198
	ldr	r3, .L310+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L198
	ldr	r3, .L310+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L198
	ldr	r3, .L310+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L198
	ldr	r3, .L310+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L198
	ldr	r3, .L310+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L198
	ldr	r3, .L310+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L198:
	ldr	r3, .L310+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L199
	ldr	r3, .L310+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L199
	ldr	r3, .L310+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L200
.L199:
	ldr	r3, .L310+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L200
	ldr	r3, .L310+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L200
	ldr	r3, .L310+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L200
	ldr	r3, .L310+168
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L200
	ldr	r3, .L310+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L310+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L200:
	ldr	r3, .L310+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L201
	ldr	r3, .L310+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L201
	ldr	r3, .L310+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L202
.L201:
	ldr	r3, .L310+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L202
	ldr	r3, .L310+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L202
	ldr	r3, .L310+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L202
	ldr	r3, .L310+168
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L202
	ldr	r3, .L310+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L310+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L202:
	ldr	r3, .L310+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L203
	ldr	r3, .L310+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L204
.L203:
	ldr	r3, .L310+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L310+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L204
.L205:
	ldr	r3, .L310+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L310+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L204:
	ldr	r3, .L310+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L310+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L206
	ldr	r3, .L310+168
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L310+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L206
	ldr	r3, .L310+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L206:
	ldr	r3, .L310+160
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L208
	ldr	r3, .L310+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L208
	ldr	r3, .L310+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L208
	ldr	r3, .L310+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L208
	ldr	r3, .L310+152
	ldr	r3, [r3]
	cmp	r3, #3
	beq	.L209
.L208:
	ldr	r3, .L310+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L209
	ldr	r3, .L310+168
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L209
	ldr	r3, .L310+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L310+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L209:
	ldr	r3, .L310+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L210
	ldr	r3, .L310+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L210
	ldr	r3, .L310+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L210
	ldr	r3, .L310+160
	ldr	r3, [r3]
	cmp	r3, #3
	beq	.L211
.L210:
	ldr	r3, .L310+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L211
	ldr	r3, .L310+168
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L211
	ldr	r3, .L310+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L310+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L211:
	ldr	r3, .L310+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L212
	ldr	r3, .L313
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L213
.L212:
	ldr	r3, .L313
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
	ldr	r3, .L313+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L213
.L214:
	ldr	r3, .L313+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L313
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L213:
	ldr	r3, .L313+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L313+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L215
	ldr	r3, .L313+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L313+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L215
	ldr	r3, .L313+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L215:
	ldr	r3, .L313+28
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L217
	ldr	r3, .L313+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L217
	ldr	r3, .L313+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L217
	ldr	r3, .L313+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L217
	ldr	r3, .L313+32
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L218
.L217:
	ldr	r3, .L313+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L218
	ldr	r3, .L313+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L218
	ldr	r3, .L313+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L313+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L218:
	ldr	r3, .L313+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L219
	ldr	r3, .L313+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L219
	ldr	r3, .L313+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L219
	ldr	r3, .L313+28
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L220
.L219:
	ldr	r3, .L313+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L220
	ldr	r3, .L313+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L220
	ldr	r3, .L313+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L313+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L220:
	ldr	r3, .L313+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L221
	ldr	r3, .L313+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L222
.L221:
	ldr	r3, .L313+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L223
	ldr	r3, .L313+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L222
.L223:
	ldr	r3, .L313+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L313+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L222:
	ldr	r3, .L313+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L313+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L224
	ldr	r3, .L313+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L313+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L224
	ldr	r3, .L313+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L224:
	ldr	r3, .L313+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L226
	ldr	r3, .L313+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L226
	ldr	r3, .L313+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L226
	ldr	r3, .L313+32
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L226
	ldr	r3, .L313+28
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L227
.L226:
	ldr	r3, .L313+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L227
	ldr	r3, .L313+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L227
	ldr	r3, .L313+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L313+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L227:
	ldr	r3, .L313+28
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L228
	ldr	r3, .L313+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L228
	ldr	r3, .L313+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L228
	ldr	r3, .L313+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L229
.L228:
	ldr	r3, .L313+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L229
	ldr	r3, .L313+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L229
	ldr	r3, .L313+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L313+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L229:
	ldr	r3, .L313+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L313+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L230
	ldr	r3, .L313+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L313+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L59
.L230:
	ldr	r3, .L313+32
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L232
	ldr	r3, .L313+28
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L232
	ldr	r3, .L313+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L233
.L232:
	ldr	r3, .L313+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L233
	ldr	r3, .L313+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L233
	ldr	r3, .L313+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
.L233:
	ldr	r3, .L313+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L234
	ldr	r3, .L313+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L234
	ldr	r3, .L313+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L234
	ldr	r3, .L313+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L234:
	ldr	r3, .L313+28
	ldr	r3, [r3]
	cmp	r3, #1
	beq	.L235
	ldr	r3, .L313+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L235
	ldr	r3, .L313+32
	ldr	r3, [r3]
	cmp	r3, #2
	ble	.L235
	ldr	r3, .L313+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L235
	ldr	r3, .L313+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L235:
	ldr	r3, .L313+28
	ldr	r3, [r3]
	cmp	r3, #1
	beq	.L236
	ldr	r3, .L313+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L236
	ldr	r3, .L313+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L236
	ldr	r3, .L313+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L236
	ldr	r3, .L313+32
	ldr	r3, [r3]
	cmp	r3, #2
	ble	.L59
.L236:
	ldr	r3, .L313+72
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L313+28
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L238
	ldr	r3, .L313+28
	ldr	r3, [r3]
	cmp	r3, #1
	beq	.L238
	ldr	r3, .L313+28
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L59
.L238:
	ldr	r3, .L313+32
	ldr	r2, [r3]
	ldr	r3, .L313+28
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L239
	ldr	r3, .L313+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L239
	ldr	r3, .L313+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L239
	ldr	r3, .L313+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L239
	ldr	r3, .L313+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L239
	ldr	r3, .L313+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L239
	ldr	r3, .L313+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L239
	ldr	r3, .L313+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L239
	ldr	r3, .L313+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L239
	ldr	r3, .L313+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L239
	ldr	r3, .L313+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L239
	ldr	r3, .L313+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L239
	ldr	r3, .L313+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L239
	ldr	r3, .L313+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L239:
	ldr	r3, .L313+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L240
	ldr	r3, .L313+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L240
	mov	r3, #1
	b	.L241
.L240:
	mov	r3, #0
.L241:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L313+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L242
	ldr	r3, .L313+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L242
	mov	r3, #1
	b	.L243
.L242:
	mov	r3, #0
.L243:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L244
	ldr	r3, .L313+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L59
.L244:
	ldr	r3, .L313+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L246
	ldr	r3, .L313+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L313+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	mov	r3, #1
	b	.L248
.L247:
	mov	r3, #0
.L248:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L313+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L249
	ldr	r3, .L313+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L249
	mov	r3, #1
	b	.L250
.L249:
	mov	r3, #0
.L250:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L59
.L246:
	ldr	r3, .L313+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L251
	ldr	r3, .L313+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L252
	ldr	r3, .L313+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L252
	mov	r3, #1
	b	.L253
.L252:
	mov	r3, #0
.L253:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L313+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L254
	ldr	r3, .L313+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L254
	mov	r3, #1
	b	.L255
.L254:
	mov	r3, #0
.L255:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L59
.L251:
	ldr	r3, .L313+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L256
	ldr	r3, .L313+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L257
	ldr	r3, .L313+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L257
	mov	r3, #1
	b	.L258
.L257:
	mov	r3, #0
.L258:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L313+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L259
	ldr	r3, .L313+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L259
	mov	r3, #1
	b	.L260
.L259:
	mov	r3, #0
.L260:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L59
.L256:
	ldr	r3, .L313+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L261
	ldr	r3, .L313+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L262
	ldr	r3, .L313+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L262
	mov	r3, #1
	b	.L263
.L262:
	mov	r3, #0
.L263:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L313+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L264
	ldr	r3, .L313+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L264
	mov	r3, #1
	b	.L265
.L264:
	mov	r3, #0
.L265:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L59
.L261:
	ldr	r3, .L313+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L266
	ldr	r3, .L313+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L267
	ldr	r3, .L313+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L267
	mov	r3, #1
	b	.L268
.L267:
	mov	r3, #0
.L268:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L313+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L269
	ldr	r3, .L313+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L269
	mov	r3, #1
	b	.L270
.L269:
	mov	r3, #0
.L270:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L59
.L266:
	ldr	r3, .L313+16
	ldr	r3, [r3]	@ float
	ldr	r2, .L313+108
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L271
	ldr	r3, .L313+112
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L272
	mov	r3, #0
	mov	r4, r3
.L272:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L59
.L271:
	ldr	r3, .L313+112
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L273
	ldr	r3, .L313+16
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L313+112
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L313+108
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L59
.L273:
	mov	r3, #1
	b	.L275
.L59:
	mov	r3, #0
.L275:
	str	r3, [fp, #-24]
	ldr	r3, .L313+116
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L313+120
	strb	r2, [r3]
	ldr	r3, .L313+124
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L313+128
	strb	r2, [r3]
	ldr	r3, .L313
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L313+24
	strb	r2, [r3]
	ldr	r3, .L313+132
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L313+136
	strb	r2, [r3]
	ldr	r3, .L313+4
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L313+20
	strb	r2, [r3]
	ldr	r3, .L313+140
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L313+144
	strb	r2, [r3]
	ldr	r3, .L313+40
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L313+56
	strb	r2, [r3]
	ldr	r3, .L313+148
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L313+152
	strb	r2, [r3]
	ldr	r3, .L313+156
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L313+80
	strb	r2, [r3]
	ldr	r3, .L313+36
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L313+52
	strb	r2, [r3]
	ldr	r3, .L313+12
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L313+8
	strb	r2, [r3]
	ldr	r3, .L313+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L313+16
	str	r3, [r2]	@ float
	ldr	r3, .L313+160
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L313+164
	strb	r2, [r3]
	ldr	r3, .L313+168
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L313+76
	strb	r2, [r3]
	ldr	r3, .L313+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L313+176
	str	r3, [r2]	@ float
	ldr	r3, .L313+180
	ldr	r3, [r3]	@ float
	ldr	r2, .L313+184
	str	r3, [r2]	@ float
	ldr	r3, .L313+64
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L313+60
	strb	r2, [r3]
	ldr	r3, .L313+188
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L313+92
	strb	r2, [r3]
	ldr	r3, .L313+192
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L313+96
	strb	r2, [r3]
	ldr	r3, .L313+196
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L313+200
	strb	r2, [r3]
	ldr	r3, .L313+48
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L313+44
	strb	r2, [r3]
	ldr	r3, .L313+28
	ldr	r3, [r3]
	ldr	r2, .L313+32
	str	r3, [r2]
	ldr	r3, .L313+204
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L313+84
	strb	r2, [r3]
	ldr	r3, .L313+208
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L313+68
	strb	r2, [r3]
	ldr	r3, .L313+212
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L313+88
	strb	r2, [r3]
	ldr	r3, .L313+216
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L313+100
	strb	r2, [r3]
	ldr	r3, .L313+220
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L313+224
	strb	r2, [r3]
	ldr	r3, .L313+228
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L313+104
	strb	r2, [r3]
	ldr	r3, .L313+232
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L313+236
	strb	r2, [r3]
	ldr	r3, .L313+240
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L313+244
	strb	r2, [r3]
	ldr	r3, .L313+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L313+112
	str	r3, [r2]	@ float
	ldr	r3, .L313+248
	ldr	r3, [r3]	@ float
	ldr	r2, .L313+252
	str	r3, [r2]	@ float
.L54:
	ldr	r3, [fp, #-24]
	cmp	r3, #0
	bne	.L276
	mov	r3, #0
	mov	r0, r3
	sub	sp, fp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, fp, pc}
.L314:
	.align	2
.L313:
	.word	_x_a1_evt1
	.word	_x_a1_evt0
	.word	a1_l
	.word	_x_a1_l
	.word	delta
	.word	a1_evt0
	.word	a1_evt1
	.word	_x_id
	.word	id
	.word	_x_a0_evt0
	.word	_x_a0_evt1
	.word	a0_l
	.word	_x_a0_l
	.word	a0_evt0
	.word	a0_evt1
	.word	c_initial
	.word	_x_c_initial
	.word	c_move
	.word	_x_delta
	.word	pc2_evt0
	.word	pc2_evt1
	.word	pc1_evt0
	.word	pc1_evt1
	.word	pc0_evt0
	.word	pc0_evt1
	.word	a2_evt0
	.word	a2_evt1
	.word	_x__diverge_delta
	.word	_diverge_delta
	.word	_x_pc2_l2
	.word	pc2_l2
	.word	_x_pc2_l1
	.word	pc2_l1
	.word	_x_a2_l
	.word	a2_l
	.word	_x_pc1_l0
	.word	pc1_l0
	.word	_x_pc2_l0
	.word	pc2_l0
	.word	_x_pc2_evt1
	.word	_x_pc0_l2
	.word	pc0_l2
	.word	_x_pc2_evt0
	.word	_x_pc1_x
	.word	pc1_x
	.word	_x_pc0_x
	.word	pc0_x
	.word	_x_pc0_evt0
	.word	_x_pc0_evt1
	.word	_x_pc0_l1
	.word	pc0_l1
	.word	_x_pc1_evt0
	.word	_x_c_move
	.word	_x_pc1_evt1
	.word	_x_a2_evt0
	.word	_x_pc1_l1
	.word	pc1_l1
	.word	_x_a2_evt1
	.word	_x_pc0_l0
	.word	pc0_l0
	.word	_x_pc1_l2
	.word	pc1_l2
	.word	_x_pc2_x
	.word	pc2_x
	.size	main, .-main
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
