	.file	"881557.c"
	.intel_syntax noprefix
	.text
	.globl	__VERIFIER_nondet_bool
	.type	__VERIFIER_nondet_bool, @function
__VERIFIER_nondet_bool:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	call	__VERIFIER_nondet_int@PLT
	test	eax, eax
	setne	al
	movzx	eax, al
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.globl	main
	.type	main, @function
main:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 112
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR -60[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -112[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -108[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -104[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -100[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -96[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -92[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -88[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -84[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -80[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -76[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -72[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -68[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -64[rbp], eax
	cmp	DWORD PTR -72[rbp], 0
	jne	.L4
	cmp	DWORD PTR -76[rbp], 0
	je	.L5
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -88[rbp]
	subsd	xmm0, xmm1
	comisd	xmm0, QWORD PTR .LC0[rip]
	jnb	.L4
	cmp	DWORD PTR -92[rbp], 0
	je	.L5
.L4:
	cmp	DWORD PTR -100[rbp], 0
	jne	.L5
	cmp	DWORD PTR -108[rbp], 0
	jne	.L5
	mov	eax, 1
	jmp	.L6
.L5:
	mov	eax, 0
.L6:
	mov	DWORD PTR -56[rbp], eax
	jmp	.L7
.L105:
	cmp	DWORD PTR -100[rbp], 0
	je	.L8
	cmp	DWORD PTR -108[rbp], 0
	je	.L8
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR -60[rbp], eax
	jmp	.L9
.L8:
	sub	DWORD PTR -60[rbp], 1
.L9:
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -52[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -48[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -44[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -40[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -36[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -32[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -28[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -24[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -20[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -16[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -12[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -8[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -4[rbp], eax
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -88[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -36[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC0[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -36[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC1[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -36[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC2[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -68[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -36[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -88[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -36[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC0[rip]
	jp	.L111
	ucomisd	xmm0, QWORD PTR .LC0[rip]
	je	.L15
.L111:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -36[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	jp	.L112
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	je	.L15
.L112:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -36[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jp	.L113
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	je	.L15
.L113:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -68[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -36[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jp	.L10
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jne	.L10
.L15:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -88[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -20[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC2[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -104[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -20[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC2[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -96[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -20[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC4[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -20[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC4[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -88[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -20[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jp	.L118
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	je	.L24
.L118:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -104[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -20[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jp	.L119
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	je	.L24
.L119:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -96[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -20[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jp	.L120
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	je	.L24
.L120:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -20[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jp	.L10
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jne	.L10
.L24:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -88[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -52[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC5[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -64[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -52[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC6[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -96[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -52[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC7[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -52[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC8[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -88[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -52[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	jp	.L125
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	je	.L33
.L125:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -64[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -52[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	jp	.L126
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	je	.L33
.L126:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -96[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -52[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC7[rip]
	jp	.L127
	ucomisd	xmm0, QWORD PTR .LC7[rip]
	je	.L33
.L127:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -52[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	jp	.L10
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	jne	.L10
.L33:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -88[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -8[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC4[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -8[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC1[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -8[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -68[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -8[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC0[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -88[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jp	.L132
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	je	.L42
.L132:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	jp	.L133
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	je	.L42
.L133:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jp	.L134
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	je	.L42
.L134:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -68[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC0[rip]
	jp	.L10
	ucomisd	xmm0, QWORD PTR .LC0[rip]
	jne	.L10
.L42:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -88[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -24[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC9[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -24[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -24[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC2[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -68[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -24[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC6[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -88[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -24[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jp	.L139
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	je	.L51
.L139:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -24[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jp	.L140
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	je	.L51
.L140:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -24[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jp	.L141
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	je	.L51
.L141:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -68[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -24[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	jp	.L10
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	jne	.L10
.L51:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -104[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -4[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC10[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -64[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -4[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC4[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -4[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC11[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -4[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC2[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -104[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -4[rbp]
	subsd	xmm0, xmm1
	movsd	xmm1, QWORD PTR .LC10[rip]
	ucomisd	xmm0, xmm1
	jp	.L146
	movsd	xmm1, QWORD PTR .LC10[rip]
	ucomisd	xmm0, xmm1
	je	.L60
.L146:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -64[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -4[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jp	.L147
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	je	.L60
.L147:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -4[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	jp	.L148
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	je	.L60
.L148:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -4[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jp	.L10
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jne	.L10
.L60:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -44[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC10[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -68[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -44[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC0[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -44[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC12[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -44[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC13[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -44[rbp]
	subsd	xmm0, xmm1
	movsd	xmm1, QWORD PTR .LC10[rip]
	ucomisd	xmm0, xmm1
	jp	.L153
	movsd	xmm1, QWORD PTR .LC10[rip]
	ucomisd	xmm0, xmm1
	je	.L69
.L153:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -68[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -44[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC0[rip]
	jp	.L154
	ucomisd	xmm0, QWORD PTR .LC0[rip]
	je	.L69
.L154:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -44[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC12[rip]
	jp	.L155
	ucomisd	xmm0, QWORD PTR .LC12[rip]
	je	.L69
.L155:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -44[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	jp	.L10
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	jne	.L10
.L69:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -88[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -28[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC9[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -28[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC14[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -28[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC7[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -68[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -28[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC15[rip]
	comisd	xmm0, xmm1
	jb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -88[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jp	.L160
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	je	.L78
.L160:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC14[rip]
	jp	.L161
	ucomisd	xmm0, QWORD PTR .LC14[rip]
	je	.L78
.L161:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC7[rip]
	jp	.L162
	ucomisd	xmm0, QWORD PTR .LC7[rip]
	je	.L78
.L162:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -68[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	jp	.L10
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	jne	.L10
.L78:
	cmp	DWORD PTR -12[rbp], 0
	jne	.L83
	cmp	DWORD PTR -16[rbp], 0
	je	.L84
	cmp	DWORD PTR -32[rbp], 0
	jne	.L83
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -20[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	comisd	xmm0, QWORD PTR .LC0[rip]
	jb	.L84
.L83:
	mov	edx, 1
	jmp	.L86
.L84:
	mov	edx, 0
.L86:
	mov	eax, DWORD PTR -76[rbp]
	cmp	edx, eax
	jne	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -44[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	comisd	xmm0, QWORD PTR .LC7[rip]
	setnb	al
	movzx	eax, al
	cmp	DWORD PTR -72[rbp], eax
	jne	.L10
	cmp	DWORD PTR -32[rbp], 0
	jne	.L87
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -20[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	comisd	xmm0, QWORD PTR .LC0[rip]
	jb	.L163
.L87:
	mov	edx, 1
	jmp	.L90
.L163:
	mov	edx, 0
.L90:
	mov	eax, DWORD PTR -92[rbp]
	cmp	edx, eax
	jne	.L10
	cmp	DWORD PTR -100[rbp], 0
	je	.L91
	cmp	DWORD PTR -108[rbp], 0
	jne	.L92
.L91:
	cmp	DWORD PTR -100[rbp], 0
	je	.L93
	cmp	DWORD PTR -108[rbp], 0
	jne	.L94
.L93:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -88[rbp]
	subsd	xmm0, xmm1
	comisd	xmm0, QWORD PTR .LC0[rip]
	jnb	.L94
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -88[rbp]
	subsd	xmm0, xmm1
	comisd	xmm0, QWORD PTR .LC0[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L95
	cmp	DWORD PTR -92[rbp], 0
	je	.L94
.L95:
	cmp	DWORD PTR -100[rbp], 0
	je	.L92
.L94:
	mov	edx, 1
	jmp	.L96
.L92:
	mov	edx, 0
.L96:
	mov	eax, DWORD PTR -40[rbp]
	cmp	edx, eax
	jne	.L10
	cmp	DWORD PTR -100[rbp], 0
	je	.L97
	cmp	DWORD PTR -108[rbp], 0
	jne	.L98
.L97:
	cmp	DWORD PTR -100[rbp], 0
	je	.L99
	cmp	DWORD PTR -108[rbp], 0
	jne	.L100
.L99:
	cmp	DWORD PTR -72[rbp], 0
	jne	.L100
	cmp	DWORD PTR -72[rbp], 0
	jne	.L101
	cmp	DWORD PTR -76[rbp], 0
	je	.L100
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -88[rbp]
	subsd	xmm0, xmm1
	comisd	xmm0, QWORD PTR .LC0[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L101
	cmp	DWORD PTR -92[rbp], 0
	je	.L100
.L101:
	cmp	DWORD PTR -108[rbp], 0
	je	.L98
.L100:
	mov	edx, 1
	jmp	.L102
.L98:
	mov	edx, 0
.L102:
	mov	eax, DWORD PTR -48[rbp]
	cmp	edx, eax
	jne	.L10
	mov	eax, 1
	jmp	.L103
.L10:
	mov	eax, 0
.L103:
	mov	DWORD PTR -56[rbp], eax
	movss	xmm0, DWORD PTR -52[rbp]
	movss	DWORD PTR -112[rbp], xmm0
	mov	eax, DWORD PTR -48[rbp]
	mov	DWORD PTR -108[rbp], eax
	movss	xmm0, DWORD PTR -44[rbp]
	movss	DWORD PTR -104[rbp], xmm0
	mov	eax, DWORD PTR -40[rbp]
	mov	DWORD PTR -100[rbp], eax
	movss	xmm0, DWORD PTR -36[rbp]
	movss	DWORD PTR -96[rbp], xmm0
	mov	eax, DWORD PTR -32[rbp]
	mov	DWORD PTR -92[rbp], eax
	movss	xmm0, DWORD PTR -28[rbp]
	movss	DWORD PTR -88[rbp], xmm0
	movss	xmm0, DWORD PTR -24[rbp]
	movss	DWORD PTR -84[rbp], xmm0
	movss	xmm0, DWORD PTR -20[rbp]
	movss	DWORD PTR -80[rbp], xmm0
	mov	eax, DWORD PTR -16[rbp]
	mov	DWORD PTR -76[rbp], eax
	mov	eax, DWORD PTR -12[rbp]
	mov	DWORD PTR -72[rbp], eax
	movss	xmm0, DWORD PTR -8[rbp]
	movss	DWORD PTR -68[rbp], xmm0
	movss	xmm0, DWORD PTR -4[rbp]
	movss	DWORD PTR -64[rbp], xmm0
.L7:
	cmp	DWORD PTR -60[rbp], 0
	js	.L104
	cmp	DWORD PTR -56[rbp], 0
	jne	.L105
.L104:
	mov	eax, 0
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	main, .-main
	.section	.rodata
	.align 8
.LC0:
	.long	0
	.long	-1070333952
	.align 8
.LC1:
	.long	0
	.long	-1071906816
	.align 8
.LC2:
	.long	0
	.long	-1070596096
	.align 8
.LC3:
	.long	0
	.long	-1071644672
	.align 8
.LC4:
	.long	0
	.long	-1070465024
	.align 8
.LC5:
	.long	0
	.long	-1071251456
	.align 8
.LC6:
	.long	0
	.long	-1070399488
	.align 8
.LC7:
	.long	0
	.long	-1073741824
	.align 8
.LC8:
	.long	0
	.long	-1071382528
	.align 8
.LC9:
	.long	0
	.long	-1070727168
	.align 8
.LC10:
	.long	0
	.long	-1074790400
	.align 8
.LC11:
	.long	0
	.long	-1072431104
	.align 8
.LC12:
	.long	0
	.long	-1070989312
	.align 8
.LC13:
	.long	0
	.long	-1072693248
	.align 8
.LC14:
	.long	0
	.long	-1071513600
	.align 8
.LC15:
	.long	0
	.long	-1071120384
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"881557.c"
	.text
	.align	2
	.global	__VERIFIER_nondet_bool
	.syntax unified
	.arm
	.fpu softvfp
	.type	__VERIFIER_nondet_bool, %function
__VERIFIER_nondet_bool:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	mov	r0, r3
	pop	{fp, pc}
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.global	__aeabi_f2d
	.global	__aeabi_dsub
	.global	__aeabi_dcmpge
	.global	__aeabi_dcmple
	.global	__aeabi_dcmpeq
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 112
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, fp, lr}
	add	fp, sp, #12
	sub	sp, sp, #112
	bl	__VERIFIER_nondet_int
	str	r0, [fp, #-72]
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-124]	@ float
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-120]
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-116]	@ float
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-112]
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-108]	@ float
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-104]
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-100]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-96]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-92]	@ float
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-88]
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-84]
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-80]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-76]	@ float
	ldr	r3, [fp, #-84]
	cmp	r3, #0
	bne	.L4
	ldr	r3, [fp, #-88]
	cmp	r3, #0
	beq	.L5
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+12
	bl	__aeabi_dcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L4
	ldr	r3, [fp, #-104]
	cmp	r3, #0
	beq	.L5
.L4:
	ldr	r3, [fp, #-112]
	cmp	r3, #0
	bne	.L5
	ldr	r3, [fp, #-120]
	cmp	r3, #0
	bne	.L5
	mov	r3, #1
	b	.L6
.L5:
	mov	r3, #0
.L6:
	str	r3, [fp, #-68]
	b	.L7
.L84:
	ldr	r3, [fp, #-112]
	cmp	r3, #0
	beq	.L8
	ldr	r3, [fp, #-120]
	cmp	r3, #0
	beq	.L8
	bl	__VERIFIER_nondet_int
	str	r0, [fp, #-72]
	b	.L9
.L120:
	.align	2
.L119:
	.word	-1071251456
	.word	-1071382528
	.word	-1071906816
	.word	-1070333952
	.word	-1070727168
	.word	-1071644672
	.word	-1070399488
	.word	-1070596096
	.word	-1074790400
	.word	-1070465024
	.word	-1072431104
.L8:
	ldr	r3, [fp, #-72]
	sub	r3, r3, #1
	str	r3, [fp, #-72]
.L9:
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-64]	@ float
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-60]
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-56]	@ float
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-52]
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-48]	@ float
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-44]
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-40]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-36]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-32]	@ float
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-28]
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-24]
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-20]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-16]	@ float
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+12
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+8
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+28
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+20
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+12
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L15
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+8
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L15
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+28
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L15
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+20
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
.L15:
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+28
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-116]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+28
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+36
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+36
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+28
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L21
	ldr	r0, [fp, #-116]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+28
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L21
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+36
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L21
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+36
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
.L21:
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-76]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+24
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+4
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L27
	ldr	r0, [fp, #-76]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+24
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L27
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L27
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+4
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
.L27:
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+36
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+8
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+20
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+12
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+36
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L33
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+8
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L33
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+20
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L33
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+12
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
.L33:
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+16
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+20
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+28
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+24
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+16
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L39
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+20
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L39
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+28
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L39
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+24
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
.L39:
	ldr	r0, [fp, #-116]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+32
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-76]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+36
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+40
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+28
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-116]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+32
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L45
	ldr	r0, [fp, #-76]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+36
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L45
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L119+40
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L45
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L121
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
.L45:
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L121+4
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L121+8
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L121+12
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L121+16
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L121+4
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L51
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L121+8
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L51
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L121+12
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L51
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L121+16
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
.L51:
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L121+20
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L121+24
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L121+28
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L121+20
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L57
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L121+24
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L57
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L57
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L121+28
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L10
.L57:
	ldr	r3, [fp, #-24]
	cmp	r3, #0
	bne	.L59
	ldr	r3, [fp, #-28]
	cmp	r3, #0
	beq	.L60
	ldr	r3, [fp, #-44]
	cmp	r3, #0
	bne	.L59
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L121+8
	bl	__aeabi_dcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L60
.L59:
	mov	r2, #1
	b	.L62
.L60:
	mov	r2, #0
.L62:
	ldr	r3, [fp, #-88]
	cmp	r2, r3
	bne	.L10
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r3, #1
	mov	r4, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L63
	mov	r3, #0
	mov	r4, r3
.L63:
	and	r3, r4, #255
	mov	r2, r3
	ldr	r3, [fp, #-84]
	cmp	r3, r2
	bne	.L10
	ldr	r3, [fp, #-44]
	cmp	r3, #0
	bne	.L64
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L121+8
	bl	__aeabi_dcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L118
.L64:
	mov	r2, #1
	b	.L67
.L118:
	mov	r2, #0
.L67:
	ldr	r3, [fp, #-104]
	cmp	r2, r3
	bne	.L10
	ldr	r3, [fp, #-112]
	cmp	r3, #0
	beq	.L68
	ldr	r3, [fp, #-120]
	cmp	r3, #0
	bne	.L69
.L68:
	ldr	r3, [fp, #-112]
	cmp	r3, #0
	beq	.L70
	ldr	r3, [fp, #-120]
	cmp	r3, #0
	bne	.L71
.L70:
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L121+8
	bl	__aeabi_dcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L71
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r3, #1
	mov	r4, r3
	mov	r2, #0
	ldr	r3, .L121+8
	bl	__aeabi_dcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L72
	mov	r3, #0
	mov	r4, r3
.L72:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L73
	ldr	r3, [fp, #-104]
	cmp	r3, #0
	beq	.L71
.L73:
	ldr	r3, [fp, #-112]
	cmp	r3, #0
	beq	.L69
.L71:
	mov	r2, #1
	b	.L74
.L69:
	mov	r2, #0
.L74:
	ldr	r3, [fp, #-52]
	cmp	r2, r3
	bne	.L10
	ldr	r3, [fp, #-112]
	cmp	r3, #0
	beq	.L75
	ldr	r3, [fp, #-120]
	cmp	r3, #0
	bne	.L76
.L75:
	ldr	r3, [fp, #-112]
	cmp	r3, #0
	beq	.L77
	ldr	r3, [fp, #-120]
	cmp	r3, #0
	bne	.L78
.L77:
	ldr	r3, [fp, #-84]
	cmp	r3, #0
	bne	.L78
	ldr	r3, [fp, #-84]
	cmp	r3, #0
	bne	.L79
	ldr	r3, [fp, #-88]
	cmp	r3, #0
	beq	.L78
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r3, #1
	mov	r4, r3
	mov	r2, #0
	ldr	r3, .L121+8
	bl	__aeabi_dcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L80
	mov	r3, #0
	mov	r4, r3
.L80:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L79
	ldr	r3, [fp, #-104]
	cmp	r3, #0
	beq	.L78
.L79:
	ldr	r3, [fp, #-120]
	cmp	r3, #0
	beq	.L76
.L78:
	mov	r2, #1
	b	.L81
.L76:
	mov	r2, #0
.L81:
	ldr	r3, [fp, #-60]
	cmp	r2, r3
	bne	.L10
	mov	r3, #1
	b	.L82
.L10:
	mov	r3, #0
.L82:
	str	r3, [fp, #-68]
	ldr	r3, [fp, #-64]	@ float
	str	r3, [fp, #-124]	@ float
	ldr	r3, [fp, #-60]
	str	r3, [fp, #-120]
	ldr	r3, [fp, #-56]	@ float
	str	r3, [fp, #-116]	@ float
	ldr	r3, [fp, #-52]
	str	r3, [fp, #-112]
	ldr	r3, [fp, #-48]	@ float
	str	r3, [fp, #-108]	@ float
	ldr	r3, [fp, #-44]
	str	r3, [fp, #-104]
	ldr	r3, [fp, #-40]	@ float
	str	r3, [fp, #-100]	@ float
	ldr	r3, [fp, #-36]	@ float
	str	r3, [fp, #-96]	@ float
	ldr	r3, [fp, #-32]	@ float
	str	r3, [fp, #-92]	@ float
	ldr	r3, [fp, #-28]
	str	r3, [fp, #-88]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-84]
	ldr	r3, [fp, #-20]	@ float
	str	r3, [fp, #-80]	@ float
	ldr	r3, [fp, #-16]	@ float
	str	r3, [fp, #-76]	@ float
.L7:
	ldr	r3, [fp, #-72]
	cmp	r3, #0
	blt	.L83
	ldr	r3, [fp, #-68]
	cmp	r3, #0
	bne	.L84
.L83:
	mov	r3, #0
	mov	r0, r3
	sub	sp, fp, #12
	@ sp needed
	pop	{r4, r5, fp, pc}
.L122:
	.align	2
.L121:
	.word	-1070596096
	.word	-1074790400
	.word	-1070333952
	.word	-1070989312
	.word	-1072693248
	.word	-1070727168
	.word	-1071513600
	.word	-1071120384
	.size	main, .-main
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
