	.file	"75582.c"
	.intel_syntax noprefix
	.text
	.globl	__VERIFIER_nondet_bool
	.type	__VERIFIER_nondet_bool, @function
__VERIFIER_nondet_bool:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	call	__VERIFIER_nondet_int@PLT
	test	eax, eax
	setne	al
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.globl	_diverge_delta
	.bss
	.align 4
	.type	_diverge_delta, @object
	.size	_diverge_delta, 4
_diverge_delta:
	.zero	4
	.globl	_x__diverge_delta
	.align 4
	.type	_x__diverge_delta, @object
	.size	_x__diverge_delta, 4
_x__diverge_delta:
	.zero	4
	.globl	p2_l3
	.type	p2_l3, @object
	.size	p2_l3, 1
p2_l3:
	.zero	1
	.globl	_x_p2_l3
	.type	_x_p2_l3, @object
	.size	_x_p2_l3, 1
_x_p2_l3:
	.zero	1
	.globl	p2_l2
	.type	p2_l2, @object
	.size	p2_l2, 1
p2_l2:
	.zero	1
	.globl	_x_p2_l2
	.type	_x_p2_l2, @object
	.size	_x_p2_l2, 1
_x_p2_l2:
	.zero	1
	.globl	p2_l1
	.type	p2_l1, @object
	.size	p2_l1, 1
p2_l1:
	.zero	1
	.globl	_x_p2_l1
	.type	_x_p2_l1, @object
	.size	_x_p2_l1, 1
_x_p2_l1:
	.zero	1
	.globl	p2_evt
	.type	p2_evt, @object
	.size	p2_evt, 1
p2_evt:
	.zero	1
	.globl	_x_p2_evt
	.type	_x_p2_evt, @object
	.size	_x_p2_evt, 1
_x_p2_evt:
	.zero	1
	.globl	delta
	.align 4
	.type	delta, @object
	.size	delta, 4
delta:
	.zero	4
	.globl	_x_delta
	.align 4
	.type	_x_delta, @object
	.size	_x_delta, 4
_x_delta:
	.zero	4
	.globl	v1
	.align 4
	.type	v1, @object
	.size	v1, 4
v1:
	.zero	4
	.globl	_x_v1
	.align 4
	.type	_x_v1, @object
	.size	_x_v1, 4
_x_v1:
	.zero	4
	.globl	v2
	.type	v2, @object
	.size	v2, 1
v2:
	.zero	1
	.globl	_x_v2
	.type	_x_v2, @object
	.size	_x_v2, 1
_x_v2:
	.zero	1
	.globl	p2_l0
	.type	p2_l0, @object
	.size	p2_l0, 1
p2_l0:
	.zero	1
	.globl	_x_p2_l0
	.type	_x_p2_l0, @object
	.size	_x_p2_l0, 1
_x_p2_l0:
	.zero	1
	.globl	p2_c
	.align 4
	.type	p2_c, @object
	.size	p2_c, 4
p2_c:
	.zero	4
	.globl	_x_p2_c
	.align 4
	.type	_x_p2_c, @object
	.size	_x_p2_c, 4
_x_p2_c:
	.zero	4
	.globl	p0_l3
	.type	p0_l3, @object
	.size	p0_l3, 1
p0_l3:
	.zero	1
	.globl	_x_p0_l3
	.type	_x_p0_l3, @object
	.size	_x_p0_l3, 1
_x_p0_l3:
	.zero	1
	.globl	p1_l2
	.type	p1_l2, @object
	.size	p1_l2, 1
p1_l2:
	.zero	1
	.globl	_x_p1_l2
	.type	_x_p1_l2, @object
	.size	_x_p1_l2, 1
_x_p1_l2:
	.zero	1
	.globl	p0_evt
	.type	p0_evt, @object
	.size	p0_evt, 1
p0_evt:
	.zero	1
	.globl	_x_p0_evt
	.type	_x_p0_evt, @object
	.size	_x_p0_evt, 1
_x_p0_evt:
	.zero	1
	.globl	p0_l1
	.type	p0_l1, @object
	.size	p0_l1, 1
p0_l1:
	.zero	1
	.globl	_x_p0_l1
	.type	_x_p0_l1, @object
	.size	_x_p0_l1, 1
_x_p0_l1:
	.zero	1
	.globl	p1_l0
	.type	p1_l0, @object
	.size	p1_l0, 1
p1_l0:
	.zero	1
	.globl	_x_p1_l0
	.type	_x_p1_l0, @object
	.size	_x_p1_l0, 1
_x_p1_l0:
	.zero	1
	.globl	p1_c
	.align 4
	.type	p1_c, @object
	.size	p1_c, 4
p1_c:
	.zero	4
	.globl	_x_p1_c
	.align 4
	.type	_x_p1_c, @object
	.size	_x_p1_c, 4
_x_p1_c:
	.zero	4
	.globl	p1_l3
	.type	p1_l3, @object
	.size	p1_l3, 1
p1_l3:
	.zero	1
	.globl	_x_p1_l3
	.type	_x_p1_l3, @object
	.size	_x_p1_l3, 1
_x_p1_l3:
	.zero	1
	.globl	p0_l2
	.type	p0_l2, @object
	.size	p0_l2, 1
p0_l2:
	.zero	1
	.globl	_x_p0_l2
	.type	_x_p0_l2, @object
	.size	_x_p0_l2, 1
_x_p0_l2:
	.zero	1
	.globl	p0_c
	.align 4
	.type	p0_c, @object
	.size	p0_c, 4
p0_c:
	.zero	4
	.globl	_x_p0_c
	.align 4
	.type	_x_p0_c, @object
	.size	_x_p0_c, 4
_x_p0_c:
	.zero	4
	.globl	p0_l0
	.type	p0_l0, @object
	.size	p0_l0, 1
p0_l0:
	.zero	1
	.globl	_x_p0_l0
	.type	_x_p0_l0, @object
	.size	_x_p0_l0, 1
_x_p0_l0:
	.zero	1
	.globl	p1_evt
	.type	p1_evt, @object
	.size	p1_evt, 1
p1_evt:
	.zero	1
	.globl	_x_p1_evt
	.type	_x_p1_evt, @object
	.size	_x_p1_evt, 1
_x_p1_evt:
	.zero	1
	.globl	p1_l1
	.type	p1_l1, @object
	.size	p1_l1, 1
p1_l1:
	.zero	1
	.globl	_x_p1_l1
	.type	_x_p1_l1, @object
	.size	_x_p1_l1, 1
_x_p1_l1:
	.zero	1
	.text
	.globl	main
	.type	main, @function
main:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _diverge_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p2_l3[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p2_l2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p2_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p2_evt[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR delta[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR v1[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR v2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p2_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p2_c[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p0_l3[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p1_l2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p0_evt[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p0_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p1_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p1_c[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p1_l3[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p0_l2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p0_c[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p0_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p1_evt[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p1_l1[rip], al
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR p2_c[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	je	.L6
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	jne	.L6
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	jne	.L6
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L7
.L6:
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	jne	.L7
.L8:
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	jne	.L9
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	je	.L9
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L9
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L7
.L9:
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	jne	.L10
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	je	.L10
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L10
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L7
.L10:
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	jne	.L11
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	je	.L11
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	jne	.L11
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L7
.L11:
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	jne	.L12
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	jne	.L12
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L12
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	jne	.L7
.L12:
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	jne	.L13
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	jne	.L13
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L13
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L7
.L13:
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	jne	.L14
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	jne	.L14
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	jne	.L14
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L7
.L14:
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	jne	.L4
.L7:
	movss	xmm1, DWORD PTR p2_c[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L15
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	jne	.L16
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	jne	.L16
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L16
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L4
.L16:
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	jne	.L17
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	je	.L17
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	jne	.L17
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L4
.L17:
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	jne	.L18
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	je	.L18
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L18
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	jne	.L4
.L18:
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	je	.L15
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	jne	.L15
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	jne	.L15
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L4
.L15:
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR p1_c[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	je	.L20
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	jne	.L20
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	jne	.L20
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L21
.L20:
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	jne	.L22
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	je	.L22
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L22
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	jne	.L21
.L22:
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	jne	.L23
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	je	.L23
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L23
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L21
.L23:
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	jne	.L24
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	je	.L24
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L24
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L21
.L24:
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	jne	.L25
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	je	.L25
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	jne	.L25
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L21
.L25:
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	jne	.L26
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	jne	.L26
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L26
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	jne	.L21
.L26:
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	jne	.L27
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	jne	.L27
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L27
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L21
.L27:
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	jne	.L28
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	jne	.L28
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	jne	.L28
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L21
.L28:
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	jne	.L4
.L21:
	movss	xmm1, DWORD PTR p1_c[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L29
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	jne	.L30
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	jne	.L30
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L30
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L4
.L30:
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	jne	.L31
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	je	.L31
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	jne	.L31
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L4
.L31:
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	jne	.L32
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	je	.L32
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L32
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	jne	.L4
.L32:
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	je	.L29
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	jne	.L29
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	jne	.L29
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L4
.L29:
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR p0_c[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	je	.L34
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	jne	.L34
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	jne	.L34
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L35
.L34:
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	jne	.L36
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	je	.L36
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L36
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	jne	.L35
.L36:
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	jne	.L37
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	je	.L37
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L37
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L35
.L37:
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	jne	.L38
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	je	.L38
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L38
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L35
.L38:
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	jne	.L39
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	je	.L39
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	jne	.L39
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L35
.L39:
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	jne	.L40
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	jne	.L40
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L40
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	jne	.L35
.L40:
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	jne	.L41
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	jne	.L41
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L41
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L35
.L41:
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	jne	.L42
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	jne	.L42
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	jne	.L42
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L35
.L42:
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	jne	.L4
.L35:
	movss	xmm1, DWORD PTR p0_c[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L43
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	jne	.L44
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	jne	.L44
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L44
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L4
.L44:
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	jne	.L45
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	je	.L45
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	jne	.L45
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L4
.L45:
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	jne	.L46
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	je	.L46
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L46
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	jne	.L4
.L46:
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	je	.L43
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	jne	.L43
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	jne	.L43
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L4
.L43:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jb	.L4
	mov	eax, DWORD PTR v1[rip]
	cmp	eax, 3
	je	.L48
	mov	eax, DWORD PTR v1[rip]
	cmp	eax, 2
	je	.L48
	mov	eax, DWORD PTR v1[rip]
	test	eax, eax
	je	.L48
	mov	eax, DWORD PTR v1[rip]
	cmp	eax, 1
	jne	.L4
.L48:
	movss	xmm0, DWORD PTR delta[rip]
	movss	xmm1, DWORD PTR _diverge_delta[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	mov	eax, 1
	jmp	.L50
.L4:
	mov	eax, 0
.L50:
	mov	DWORD PTR -4[rbp], eax
	jmp	.L51
.L248:
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x__diverge_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p2_l3[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p2_l2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p2_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p2_evt[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_delta[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_v1[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_v2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p2_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p2_c[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p0_l3[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p1_l2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p0_evt[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p0_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p1_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p1_c[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p1_l3[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p0_l2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p0_c[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p0_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p1_evt[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p1_l1[rip], al
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	je	.L52
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	jne	.L52
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	jne	.L52
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L53
.L52:
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	jne	.L54
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	je	.L54
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L54
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	jne	.L53
.L54:
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	jne	.L55
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	je	.L55
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L55
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L53
.L55:
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	jne	.L56
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	je	.L56
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L56
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L53
.L56:
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	jne	.L57
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	je	.L57
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	jne	.L57
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L53
.L57:
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	jne	.L58
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	jne	.L58
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L58
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	jne	.L53
.L58:
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L59
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L53
.L59:
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L53
.L60:
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	jne	.L61
.L53:
	movss	xmm1, DWORD PTR _x_p2_c[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L62
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	jne	.L63
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	jne	.L63
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L63
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L61
.L63:
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	jne	.L64
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	je	.L64
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	jne	.L64
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L61
.L64:
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	jne	.L65
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	je	.L65
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L65
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	jne	.L61
.L65:
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	je	.L62
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	jne	.L62
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	jne	.L62
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L61
.L62:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L66
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L61
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p2_c[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p2_c[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L61
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L61
.L66:
	movzx	eax, BYTE PTR p2_evt[rip]
	test	al, al
	jne	.L68
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L61
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p2_c[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p2_c[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L61
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L61
.L68:
	mov	edx, DWORD PTR v1[rip]
	mov	eax, DWORD PTR _x_v1[rip]
	cmp	edx, eax
	jne	.L70
	mov	eax, DWORD PTR v1[rip]
	test	eax, eax
	jne	.L70
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	jne	.L70
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	jne	.L70
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L70
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	jne	.L70
	movzx	eax, BYTE PTR v2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_v2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L70
	movss	xmm0, DWORD PTR _x_p2_c[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L70
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L71
.L70:
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	jne	.L71
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	jne	.L71
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	jne	.L71
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	jne	.L71
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L71
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L71
	movzx	eax, BYTE PTR p2_evt[rip]
	test	al, al
	jne	.L61
.L71:
	movzx	eax, BYTE PTR v2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_v2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L73
	movss	xmm0, DWORD PTR _x_p2_c[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L73
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L73
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	jne	.L73
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	jne	.L73
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L73
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	jne	.L73
	mov	eax, DWORD PTR _x_v1[rip]
	cmp	eax, 3
	je	.L75
.L73:
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	jne	.L75
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	jne	.L75
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L75
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	jne	.L75
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L75
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L75
	movzx	eax, BYTE PTR p2_evt[rip]
	test	al, al
	jne	.L61
.L75:
	movzx	eax, BYTE PTR v2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_v2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L76
	mov	edx, DWORD PTR v1[rip]
	mov	eax, DWORD PTR _x_v1[rip]
	cmp	edx, eax
	jne	.L76
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	jne	.L77
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	jne	.L77
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	jne	.L77
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L78
.L77:
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	jne	.L76
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	jne	.L76
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L76
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L76
.L78:
	movss	xmm0, DWORD PTR p2_c[rip]
	movss	xmm1, DWORD PTR _x_p2_c[rip]
	ucomiss	xmm0, xmm1
	jp	.L76
	ucomiss	xmm0, xmm1
	je	.L79
.L76:
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	jne	.L79
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	jne	.L79
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L79
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	jne	.L79
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L79
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L79
	movzx	eax, BYTE PTR p2_evt[rip]
	test	al, al
	jne	.L61
.L79:
	mov	eax, DWORD PTR v1[rip]
	cmp	eax, 3
	jne	.L81
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	jne	.L81
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	jne	.L81
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	jne	.L81
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	jne	.L81
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	jne	.L81
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	jne	.L81
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	jne	.L81
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L81
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L81
	movzx	eax, BYTE PTR p2_evt[rip]
	test	al, al
	jne	.L61
.L81:
	mov	eax, DWORD PTR v1[rip]
	cmp	eax, 3
	jne	.L82
	movss	xmm1, DWORD PTR p2_c[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L83
.L82:
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	jne	.L83
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	jne	.L83
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L83
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L83
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	jne	.L83
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	jne	.L83
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L83
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	jne	.L83
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L83
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L83
	movzx	eax, BYTE PTR p2_evt[rip]
	test	al, al
	jne	.L61
.L83:
	movzx	eax, BYTE PTR v2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_v2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L84
	mov	edx, DWORD PTR v1[rip]
	mov	eax, DWORD PTR _x_v1[rip]
	cmp	edx, eax
	jne	.L84
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	jne	.L85
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	jne	.L85
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	jne	.L85
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L86
.L85:
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	jne	.L84
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	je	.L84
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	jne	.L84
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L86
.L84:
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	jne	.L86
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	jne	.L86
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L86
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L86
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L86
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L86
	movzx	eax, BYTE PTR p2_evt[rip]
	test	al, al
	jne	.L61
.L86:
	movzx	eax, BYTE PTR v2[rip]
	test	al, al
	je	.L87
	movss	xmm0, DWORD PTR p2_c[rip]
	movss	xmm1, DWORD PTR _x_p2_c[rip]
	ucomiss	xmm0, xmm1
	jp	.L87
	ucomiss	xmm0, xmm1
	je	.L88
.L87:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L88
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L88
	movzx	eax, BYTE PTR p2_evt[rip]
	test	al, al
	je	.L88
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	jne	.L88
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	jne	.L88
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	jne	.L88
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	jne	.L88
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	jne	.L88
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	jne	.L88
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L88
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	jne	.L61
.L88:
	movzx	eax, BYTE PTR v2[rip]
	test	al, al
	jne	.L90
	movss	xmm0, DWORD PTR _x_p2_c[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L90
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L91
.L90:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L91
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L91
	movzx	eax, BYTE PTR p2_evt[rip]
	test	al, al
	je	.L91
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	jne	.L91
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	jne	.L91
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L91
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L91
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	jne	.L91
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	je	.L91
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	jne	.L91
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L61
.L91:
	movzx	eax, BYTE PTR _x_v2[rip]
	test	al, al
	je	.L93
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	jne	.L93
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	je	.L93
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L93
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	jne	.L93
	mov	edx, DWORD PTR v1[rip]
	mov	eax, DWORD PTR _x_v1[rip]
	cmp	edx, eax
	jne	.L93
	movss	xmm0, DWORD PTR _x_p2_c[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L93
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L94
.L93:
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	jne	.L94
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	je	.L94
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	jne	.L94
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	jne	.L94
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L94
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L94
	movzx	eax, BYTE PTR p2_evt[rip]
	test	al, al
	jne	.L61
.L94:
	movzx	eax, BYTE PTR v2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_v2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L96
	mov	edx, DWORD PTR v1[rip]
	mov	eax, DWORD PTR _x_v1[rip]
	cmp	edx, eax
	jne	.L96
	movss	xmm0, DWORD PTR p2_c[rip]
	movss	xmm1, DWORD PTR _x_p2_c[rip]
	ucomiss	xmm0, xmm1
	jp	.L96
	ucomiss	xmm0, xmm1
	jne	.L96
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	jne	.L98
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	jne	.L98
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	jne	.L98
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L99
.L98:
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	jne	.L96
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	je	.L96
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L96
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L99
.L96:
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	jne	.L99
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	je	.L99
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L99
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	jne	.L99
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L99
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L99
	movzx	eax, BYTE PTR p2_evt[rip]
	test	al, al
	jne	.L61
.L99:
	mov	eax, DWORD PTR v1[rip]
	cmp	eax, 3
	jne	.L100
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L100
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L100
	movzx	eax, BYTE PTR p2_evt[rip]
	test	al, al
	je	.L100
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	jne	.L100
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	jne	.L100
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	jne	.L100
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	jne	.L100
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	jne	.L100
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	je	.L100
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L100
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L61
.L100:
	mov	eax, DWORD PTR v1[rip]
	cmp	eax, 3
	je	.L101
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L101
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L101
	movzx	eax, BYTE PTR p2_evt[rip]
	test	al, al
	je	.L101
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	jne	.L101
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	je	.L101
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L101
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	jne	.L101
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	jne	.L101
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	je	.L101
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L101
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L61
.L101:
	movzx	eax, BYTE PTR v2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_v2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L102
	mov	edx, DWORD PTR v1[rip]
	mov	eax, DWORD PTR _x_v1[rip]
	cmp	edx, eax
	jne	.L102
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	jne	.L102
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	je	.L102
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L102
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L102
	movss	xmm0, DWORD PTR _x_p2_c[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L102
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L103
.L102:
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	jne	.L103
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	je	.L103
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L103
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	jne	.L103
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L103
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L103
	movzx	eax, BYTE PTR p2_evt[rip]
	test	al, al
	jne	.L61
.L103:
	mov	edx, DWORD PTR v1[rip]
	mov	eax, DWORD PTR _x_v1[rip]
	cmp	edx, eax
	jne	.L105
	movss	xmm0, DWORD PTR _x_p2_c[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L105
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L105
	movzx	eax, BYTE PTR _x_v2[rip]
	test	al, al
	jne	.L105
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	je	.L105
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	jne	.L105
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	jne	.L105
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L107
.L105:
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	jne	.L107
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	je	.L107
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L107
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L107
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L107
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L107
	movzx	eax, BYTE PTR p2_evt[rip]
	test	al, al
	jne	.L61
.L107:
	mov	eax, DWORD PTR _x_v1[rip]
	test	eax, eax
	jne	.L108
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	test	al, al
	jne	.L108
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	test	al, al
	jne	.L108
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	jne	.L108
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	jne	.L108
	movzx	eax, BYTE PTR v2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_v2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L108
	movss	xmm0, DWORD PTR p2_c[rip]
	movss	xmm1, DWORD PTR _x_p2_c[rip]
	ucomiss	xmm0, xmm1
	jp	.L108
	ucomiss	xmm0, xmm1
	je	.L109
.L108:
	movzx	eax, BYTE PTR p2_l3[rip]
	test	al, al
	je	.L109
	movzx	eax, BYTE PTR p2_l2[rip]
	test	al, al
	jne	.L109
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	jne	.L109
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	jne	.L109
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L109
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L109
	movzx	eax, BYTE PTR p2_evt[rip]
	test	al, al
	jne	.L61
.L109:
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	je	.L111
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	jne	.L111
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L111
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L112
.L111:
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	jne	.L113
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	je	.L113
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L113
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	jne	.L112
.L113:
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	jne	.L114
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	je	.L114
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L114
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L112
.L114:
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	jne	.L115
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	je	.L115
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L115
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L112
.L115:
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	jne	.L116
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	je	.L116
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L116
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L112
.L116:
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	jne	.L117
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	jne	.L117
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L117
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	jne	.L112
.L117:
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	jne	.L118
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	jne	.L118
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L118
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L112
.L118:
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	jne	.L119
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	jne	.L119
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L119
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L112
.L119:
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	jne	.L61
.L112:
	movss	xmm1, DWORD PTR _x_p1_c[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L120
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	jne	.L121
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	jne	.L121
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L121
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L61
.L121:
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	jne	.L122
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	je	.L122
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L122
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L61
.L122:
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	jne	.L123
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	je	.L123
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L123
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	jne	.L61
.L123:
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	je	.L120
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	jne	.L120
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L120
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L61
.L120:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L124
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L61
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p1_c[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p1_c[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L61
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L61
.L124:
	movzx	eax, BYTE PTR p1_evt[rip]
	test	al, al
	jne	.L126
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L61
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p1_c[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p1_c[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L61
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L61
.L126:
	mov	edx, DWORD PTR v1[rip]
	mov	eax, DWORD PTR _x_v1[rip]
	cmp	edx, eax
	jne	.L128
	mov	eax, DWORD PTR v1[rip]
	test	eax, eax
	jne	.L128
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	jne	.L128
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	jne	.L128
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L128
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	jne	.L128
	movzx	eax, BYTE PTR v2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_v2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L128
	movss	xmm0, DWORD PTR _x_p1_c[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L128
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L129
.L128:
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	jne	.L129
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	jne	.L129
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	jne	.L129
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	jne	.L129
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L129
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L129
	movzx	eax, BYTE PTR p1_evt[rip]
	test	al, al
	jne	.L61
.L129:
	movzx	eax, BYTE PTR v2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_v2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L131
	movss	xmm0, DWORD PTR _x_p1_c[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L131
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L131
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	jne	.L131
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	jne	.L131
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L131
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L131
	mov	eax, DWORD PTR _x_v1[rip]
	cmp	eax, 2
	je	.L133
.L131:
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	jne	.L133
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	jne	.L133
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L133
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	jne	.L133
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L133
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L133
	movzx	eax, BYTE PTR p1_evt[rip]
	test	al, al
	jne	.L61
.L133:
	movzx	eax, BYTE PTR v2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_v2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L134
	mov	edx, DWORD PTR v1[rip]
	mov	eax, DWORD PTR _x_v1[rip]
	cmp	edx, eax
	jne	.L134
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	jne	.L135
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	jne	.L135
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L135
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L136
.L135:
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	jne	.L134
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	jne	.L134
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L134
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L134
.L136:
	movss	xmm0, DWORD PTR p1_c[rip]
	movss	xmm1, DWORD PTR _x_p1_c[rip]
	ucomiss	xmm0, xmm1
	jp	.L134
	ucomiss	xmm0, xmm1
	je	.L137
.L134:
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	jne	.L137
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	jne	.L137
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L137
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	jne	.L137
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L137
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L137
	movzx	eax, BYTE PTR p1_evt[rip]
	test	al, al
	jne	.L61
.L137:
	mov	eax, DWORD PTR v1[rip]
	cmp	eax, 2
	jne	.L139
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	jne	.L139
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	jne	.L139
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L139
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	jne	.L139
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	jne	.L139
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	jne	.L139
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L139
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	jne	.L139
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L139
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L139
	movzx	eax, BYTE PTR p1_evt[rip]
	test	al, al
	jne	.L61
.L139:
	mov	eax, DWORD PTR v1[rip]
	cmp	eax, 2
	jne	.L140
	movss	xmm1, DWORD PTR p1_c[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L141
.L140:
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	jne	.L141
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	jne	.L141
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L141
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L141
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	jne	.L141
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	jne	.L141
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L141
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	jne	.L141
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L141
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L141
	movzx	eax, BYTE PTR p1_evt[rip]
	test	al, al
	jne	.L61
.L141:
	movzx	eax, BYTE PTR v2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_v2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L142
	mov	edx, DWORD PTR v1[rip]
	mov	eax, DWORD PTR _x_v1[rip]
	cmp	edx, eax
	jne	.L142
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	jne	.L143
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	jne	.L143
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L143
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L144
.L143:
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	jne	.L142
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	je	.L142
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L142
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L144
.L142:
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	jne	.L144
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	jne	.L144
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L144
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L144
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L144
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L144
	movzx	eax, BYTE PTR p1_evt[rip]
	test	al, al
	jne	.L61
.L144:
	movzx	eax, BYTE PTR v2[rip]
	test	al, al
	je	.L145
	movss	xmm0, DWORD PTR p1_c[rip]
	movss	xmm1, DWORD PTR _x_p1_c[rip]
	ucomiss	xmm0, xmm1
	jp	.L145
	ucomiss	xmm0, xmm1
	je	.L146
.L145:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L146
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L146
	movzx	eax, BYTE PTR p1_evt[rip]
	test	al, al
	je	.L146
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	jne	.L146
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	jne	.L146
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L146
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	jne	.L146
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	jne	.L146
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	jne	.L146
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L146
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	jne	.L61
.L146:
	movzx	eax, BYTE PTR v2[rip]
	test	al, al
	jne	.L148
	movss	xmm0, DWORD PTR _x_p1_c[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L148
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L149
.L148:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L149
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L149
	movzx	eax, BYTE PTR p1_evt[rip]
	test	al, al
	je	.L149
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	jne	.L149
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	jne	.L149
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L149
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L149
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	jne	.L149
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	je	.L149
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L149
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L61
.L149:
	movzx	eax, BYTE PTR _x_v2[rip]
	test	al, al
	je	.L151
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	jne	.L151
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	je	.L151
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L151
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	jne	.L151
	mov	edx, DWORD PTR v1[rip]
	mov	eax, DWORD PTR _x_v1[rip]
	cmp	edx, eax
	jne	.L151
	movss	xmm0, DWORD PTR _x_p1_c[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L151
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L152
.L151:
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	jne	.L152
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	je	.L152
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	jne	.L152
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	jne	.L152
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L152
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L152
	movzx	eax, BYTE PTR p1_evt[rip]
	test	al, al
	jne	.L61
.L152:
	movzx	eax, BYTE PTR v2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_v2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L154
	mov	edx, DWORD PTR v1[rip]
	mov	eax, DWORD PTR _x_v1[rip]
	cmp	edx, eax
	jne	.L154
	movss	xmm0, DWORD PTR p1_c[rip]
	movss	xmm1, DWORD PTR _x_p1_c[rip]
	ucomiss	xmm0, xmm1
	jp	.L154
	ucomiss	xmm0, xmm1
	jne	.L154
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	jne	.L156
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	jne	.L156
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L156
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L157
.L156:
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	jne	.L154
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	je	.L154
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L154
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L157
.L154:
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	jne	.L157
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	je	.L157
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L157
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	jne	.L157
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L157
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L157
	movzx	eax, BYTE PTR p1_evt[rip]
	test	al, al
	jne	.L61
.L157:
	mov	eax, DWORD PTR v1[rip]
	cmp	eax, 2
	jne	.L158
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L158
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L158
	movzx	eax, BYTE PTR p1_evt[rip]
	test	al, al
	je	.L158
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	jne	.L158
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	jne	.L158
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L158
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	jne	.L158
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	jne	.L158
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	je	.L158
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L158
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L61
.L158:
	mov	eax, DWORD PTR v1[rip]
	cmp	eax, 2
	je	.L159
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L159
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L159
	movzx	eax, BYTE PTR p1_evt[rip]
	test	al, al
	je	.L159
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	jne	.L159
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	je	.L159
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L159
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	jne	.L159
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	jne	.L159
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	je	.L159
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L159
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L61
.L159:
	movzx	eax, BYTE PTR v2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_v2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L160
	mov	edx, DWORD PTR v1[rip]
	mov	eax, DWORD PTR _x_v1[rip]
	cmp	edx, eax
	jne	.L160
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	jne	.L160
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	je	.L160
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L160
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L160
	movss	xmm0, DWORD PTR _x_p1_c[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L160
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L161
.L160:
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	jne	.L161
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	je	.L161
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L161
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	jne	.L161
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L161
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L161
	movzx	eax, BYTE PTR p1_evt[rip]
	test	al, al
	jne	.L61
.L161:
	mov	edx, DWORD PTR v1[rip]
	mov	eax, DWORD PTR _x_v1[rip]
	cmp	edx, eax
	jne	.L163
	movss	xmm0, DWORD PTR _x_p1_c[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L163
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L163
	movzx	eax, BYTE PTR _x_v2[rip]
	test	al, al
	jne	.L163
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	je	.L163
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	jne	.L163
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L163
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L165
.L163:
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	jne	.L165
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	je	.L165
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L165
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L165
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L165
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L165
	movzx	eax, BYTE PTR p1_evt[rip]
	test	al, al
	jne	.L61
.L165:
	mov	eax, DWORD PTR _x_v1[rip]
	test	eax, eax
	jne	.L166
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	test	al, al
	jne	.L166
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	test	al, al
	jne	.L166
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L166
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	jne	.L166
	movzx	eax, BYTE PTR v2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_v2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L166
	movss	xmm0, DWORD PTR p1_c[rip]
	movss	xmm1, DWORD PTR _x_p1_c[rip]
	ucomiss	xmm0, xmm1
	jp	.L166
	ucomiss	xmm0, xmm1
	je	.L167
.L166:
	movzx	eax, BYTE PTR p1_l3[rip]
	test	al, al
	je	.L167
	movzx	eax, BYTE PTR p1_l2[rip]
	test	al, al
	jne	.L167
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	jne	.L167
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	jne	.L167
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L167
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L167
	movzx	eax, BYTE PTR p1_evt[rip]
	test	al, al
	jne	.L61
.L167:
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	je	.L169
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	jne	.L169
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L169
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L170
.L169:
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	jne	.L171
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	je	.L171
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L171
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	jne	.L170
.L171:
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	jne	.L172
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	je	.L172
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L172
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L170
.L172:
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	jne	.L173
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	je	.L173
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L173
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L170
.L173:
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	jne	.L174
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	je	.L174
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L174
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L170
.L174:
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	jne	.L175
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	jne	.L175
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L175
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	jne	.L170
.L175:
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	jne	.L176
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	jne	.L176
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L176
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L170
.L176:
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	jne	.L177
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	jne	.L177
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L177
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L170
.L177:
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	jne	.L61
.L170:
	movss	xmm1, DWORD PTR _x_p0_c[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L178
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	jne	.L179
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	jne	.L179
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L179
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L61
.L179:
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	jne	.L180
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	je	.L180
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L180
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L61
.L180:
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	jne	.L61
.L181:
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	je	.L178
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	jne	.L178
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L178
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L61
.L178:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L182
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L61
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p0_c[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p0_c[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L61
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L61
.L182:
	movzx	eax, BYTE PTR p0_evt[rip]
	test	al, al
	jne	.L184
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L61
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p0_c[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p0_c[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L61
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L61
.L184:
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	jne	.L186
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	jne	.L186
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L186
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	jne	.L186
	mov	eax, DWORD PTR v1[rip]
	test	eax, eax
	jne	.L186
	movss	xmm0, DWORD PTR _x_p0_c[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L186
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L186
	movzx	eax, BYTE PTR v2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_v2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L186
	mov	edx, DWORD PTR v1[rip]
	mov	eax, DWORD PTR _x_v1[rip]
	cmp	edx, eax
	je	.L188
.L186:
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	jne	.L188
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	jne	.L188
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	jne	.L188
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	jne	.L188
	movzx	eax, BYTE PTR p0_evt[rip]
	test	al, al
	je	.L188
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L188
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L61
.L188:
	movss	xmm0, DWORD PTR _x_p0_c[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L190
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L190
	movzx	eax, BYTE PTR v2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_v2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L190
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	jne	.L190
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	jne	.L190
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L190
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L190
	mov	eax, DWORD PTR _x_v1[rip]
	cmp	eax, 1
	je	.L192
.L190:
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	jne	.L192
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	jne	.L192
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L192
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	jne	.L192
	movzx	eax, BYTE PTR p0_evt[rip]
	test	al, al
	je	.L192
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L192
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L61
.L192:
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	jne	.L194
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	jne	.L194
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L194
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L195
.L194:
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	jne	.L196
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	jne	.L196
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L196
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L196
.L195:
	movss	xmm0, DWORD PTR p0_c[rip]
	movss	xmm1, DWORD PTR _x_p0_c[rip]
	ucomiss	xmm0, xmm1
	jp	.L196
	ucomiss	xmm0, xmm1
	jne	.L196
	movzx	eax, BYTE PTR v2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_v2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L196
	mov	edx, DWORD PTR v1[rip]
	mov	eax, DWORD PTR _x_v1[rip]
	cmp	edx, eax
	je	.L198
.L196:
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	jne	.L198
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	jne	.L198
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L198
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	jne	.L198
	movzx	eax, BYTE PTR p0_evt[rip]
	test	al, al
	je	.L198
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L198
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L61
.L198:
	mov	eax, DWORD PTR v1[rip]
	cmp	eax, 1
	jne	.L200
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	jne	.L200
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	jne	.L200
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L200
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	jne	.L200
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	jne	.L200
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	jne	.L200
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L200
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	jne	.L200
	movzx	eax, BYTE PTR p0_evt[rip]
	test	al, al
	je	.L200
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L200
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L61
.L200:
	mov	eax, DWORD PTR v1[rip]
	cmp	eax, 1
	jne	.L202
	movss	xmm1, DWORD PTR p0_c[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L203
.L202:
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	jne	.L203
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	jne	.L203
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L203
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L203
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	jne	.L203
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	jne	.L203
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L203
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	jne	.L203
	movzx	eax, BYTE PTR p0_evt[rip]
	test	al, al
	je	.L203
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L203
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L61
.L203:
	movzx	eax, BYTE PTR v2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_v2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L205
	mov	edx, DWORD PTR v1[rip]
	mov	eax, DWORD PTR _x_v1[rip]
	cmp	edx, eax
	jne	.L205
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	jne	.L206
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	jne	.L206
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L206
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L207
.L206:
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L207
.L205:
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	jne	.L207
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	jne	.L207
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L207
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L207
	movzx	eax, BYTE PTR p0_evt[rip]
	test	al, al
	je	.L207
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L207
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L61
.L207:
	movzx	eax, BYTE PTR v2[rip]
	test	al, al
	je	.L209
	movss	xmm0, DWORD PTR p0_c[rip]
	movss	xmm1, DWORD PTR _x_p0_c[rip]
	ucomiss	xmm0, xmm1
	jp	.L209
	ucomiss	xmm0, xmm1
	je	.L210
.L209:
	movzx	eax, BYTE PTR p0_evt[rip]
	test	al, al
	je	.L210
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L210
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L210
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	jne	.L210
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	jne	.L210
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L210
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	jne	.L210
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	jne	.L210
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	jne	.L210
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L210
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	jne	.L61
.L210:
	movss	xmm0, DWORD PTR _x_p0_c[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L212
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L212
	movzx	eax, BYTE PTR v2[rip]
	test	al, al
	je	.L214
.L212:
	movzx	eax, BYTE PTR p0_evt[rip]
	test	al, al
	je	.L214
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L214
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L214
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	jne	.L214
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	jne	.L214
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L214
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L214
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	jne	.L214
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	je	.L214
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L214
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L61
.L214:
	movzx	eax, BYTE PTR _x_v2[rip]
	test	al, al
	je	.L215
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	jne	.L215
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	je	.L215
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L215
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	jne	.L215
	movss	xmm0, DWORD PTR _x_p0_c[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L215
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L215
	mov	edx, DWORD PTR v1[rip]
	mov	eax, DWORD PTR _x_v1[rip]
	cmp	edx, eax
	je	.L217
.L215:
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	jne	.L217
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	je	.L217
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	jne	.L217
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	jne	.L217
	movzx	eax, BYTE PTR p0_evt[rip]
	test	al, al
	je	.L217
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L217
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L61
.L217:
	movzx	eax, BYTE PTR v2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_v2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L219
	mov	edx, DWORD PTR v1[rip]
	mov	eax, DWORD PTR _x_v1[rip]
	cmp	edx, eax
	jne	.L219
	movss	xmm0, DWORD PTR p0_c[rip]
	movss	xmm1, DWORD PTR _x_p0_c[rip]
	ucomiss	xmm0, xmm1
	jp	.L219
	ucomiss	xmm0, xmm1
	jne	.L219
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	jne	.L221
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	jne	.L221
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L221
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L222
.L221:
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	jne	.L219
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	je	.L219
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L219
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L222
.L219:
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	jne	.L222
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	je	.L222
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L222
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	jne	.L222
	movzx	eax, BYTE PTR p0_evt[rip]
	test	al, al
	je	.L222
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L222
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L61
.L222:
	mov	eax, DWORD PTR v1[rip]
	cmp	eax, 1
	jne	.L224
	movzx	eax, BYTE PTR p0_evt[rip]
	test	al, al
	je	.L224
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L224
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L224
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	jne	.L224
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	jne	.L224
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L224
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	jne	.L224
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	jne	.L224
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	je	.L224
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L224
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L61
.L224:
	mov	eax, DWORD PTR v1[rip]
	cmp	eax, 1
	je	.L225
	movzx	eax, BYTE PTR p0_evt[rip]
	test	al, al
	je	.L225
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L225
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L225
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	jne	.L225
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	je	.L225
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L225
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	jne	.L225
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	jne	.L225
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	je	.L225
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L225
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L61
.L225:
	movzx	eax, BYTE PTR v2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_v2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L226
	mov	edx, DWORD PTR v1[rip]
	mov	eax, DWORD PTR _x_v1[rip]
	cmp	edx, eax
	jne	.L226
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	jne	.L226
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	je	.L226
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L226
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L226
	movss	xmm0, DWORD PTR _x_p0_c[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L226
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L227
.L226:
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	jne	.L227
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	je	.L227
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L227
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	jne	.L227
	movzx	eax, BYTE PTR p0_evt[rip]
	test	al, al
	je	.L227
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L227
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L61
.L227:
	movss	xmm0, DWORD PTR _x_p0_c[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L230
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L230
	mov	edx, DWORD PTR v1[rip]
	mov	eax, DWORD PTR _x_v1[rip]
	cmp	edx, eax
	jne	.L230
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	je	.L230
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	jne	.L230
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L230
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	jne	.L230
	movzx	eax, BYTE PTR _x_v2[rip]
	test	al, al
	je	.L232
.L230:
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	jne	.L232
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	je	.L232
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L232
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L232
	movzx	eax, BYTE PTR p0_evt[rip]
	test	al, al
	je	.L232
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L232
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L61
.L232:
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	test	al, al
	jne	.L234
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	test	al, al
	jne	.L234
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L234
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	jne	.L234
	mov	eax, DWORD PTR _x_v1[rip]
	test	eax, eax
	jne	.L234
	movzx	eax, BYTE PTR v2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_v2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L234
	movss	xmm0, DWORD PTR p0_c[rip]
	movss	xmm1, DWORD PTR _x_p0_c[rip]
	ucomiss	xmm0, xmm1
	jp	.L234
	ucomiss	xmm0, xmm1
	je	.L235
.L234:
	movzx	eax, BYTE PTR p0_l3[rip]
	test	al, al
	je	.L235
	movzx	eax, BYTE PTR p0_l2[rip]
	test	al, al
	jne	.L235
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	jne	.L235
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	jne	.L235
	movzx	eax, BYTE PTR p0_evt[rip]
	test	al, al
	je	.L235
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L235
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L61
.L235:
	mov	eax, DWORD PTR _x_v1[rip]
	cmp	eax, 3
	je	.L238
	mov	eax, DWORD PTR _x_v1[rip]
	cmp	eax, 2
	je	.L238
	mov	eax, DWORD PTR _x_v1[rip]
	cmp	eax, 1
	je	.L238
	mov	eax, DWORD PTR _x_v1[rip]
	test	eax, eax
	jne	.L61
.L238:
	movss	xmm0, DWORD PTR _x_delta[rip]
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jb	.L61
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L240
	movzx	eax, BYTE PTR v2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_v2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L61
	mov	edx, DWORD PTR v1[rip]
	mov	eax, DWORD PTR _x_v1[rip]
	cmp	edx, eax
	jne	.L61
.L240:
	movzx	eax, BYTE PTR p2_evt[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR p0_evt[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR p1_evt[rip]
	test	al, al
	jne	.L241
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L241
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L61
.L241:
	movss	xmm0, DWORD PTR delta[rip]
	movss	xmm1, DWORD PTR _x__diverge_delta[rip]
	ucomiss	xmm0, xmm1
	jp	.L269
	ucomiss	xmm0, xmm1
	je	.L243
.L269:
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	movss	xmm1, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L61
.L243:
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	movss	xmm1, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	jnb	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x__diverge_delta[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L61
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L61
.L245:
	mov	eax, 1
	jmp	.L247
.L61:
	mov	eax, 0
.L247:
	mov	DWORD PTR -4[rbp], eax
	movss	xmm0, DWORD PTR _x__diverge_delta[rip]
	movss	DWORD PTR _diverge_delta[rip], xmm0
	movzx	eax, BYTE PTR _x_p2_l3[rip]
	mov	BYTE PTR p2_l3[rip], al
	movzx	eax, BYTE PTR _x_p2_l2[rip]
	mov	BYTE PTR p2_l2[rip], al
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	mov	BYTE PTR p2_l1[rip], al
	movzx	eax, BYTE PTR _x_p2_evt[rip]
	mov	BYTE PTR p2_evt[rip], al
	movss	xmm0, DWORD PTR _x_delta[rip]
	movss	DWORD PTR delta[rip], xmm0
	mov	eax, DWORD PTR _x_v1[rip]
	mov	DWORD PTR v1[rip], eax
	movzx	eax, BYTE PTR _x_v2[rip]
	mov	BYTE PTR v2[rip], al
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	mov	BYTE PTR p2_l0[rip], al
	movss	xmm0, DWORD PTR _x_p2_c[rip]
	movss	DWORD PTR p2_c[rip], xmm0
	movzx	eax, BYTE PTR _x_p0_l3[rip]
	mov	BYTE PTR p0_l3[rip], al
	movzx	eax, BYTE PTR _x_p1_l2[rip]
	mov	BYTE PTR p1_l2[rip], al
	movzx	eax, BYTE PTR _x_p0_evt[rip]
	mov	BYTE PTR p0_evt[rip], al
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	mov	BYTE PTR p0_l1[rip], al
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	mov	BYTE PTR p1_l0[rip], al
	movss	xmm0, DWORD PTR _x_p1_c[rip]
	movss	DWORD PTR p1_c[rip], xmm0
	movzx	eax, BYTE PTR _x_p1_l3[rip]
	mov	BYTE PTR p1_l3[rip], al
	movzx	eax, BYTE PTR _x_p0_l2[rip]
	mov	BYTE PTR p0_l2[rip], al
	movss	xmm0, DWORD PTR _x_p0_c[rip]
	movss	DWORD PTR p0_c[rip], xmm0
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	mov	BYTE PTR p0_l0[rip], al
	movzx	eax, BYTE PTR _x_p1_evt[rip]
	mov	BYTE PTR p1_evt[rip], al
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	mov	BYTE PTR p1_l1[rip], al
.L51:
	cmp	DWORD PTR -4[rbp], 0
	jne	.L248
	mov	eax, 0
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	main, .-main
	.section	.rodata
	.align 4
.LC1:
	.long	1098907648
	.align 4
.LC3:
	.long	1065353216
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"75582.c"
	.text
	.align	2
	.global	__VERIFIER_nondet_bool
	.syntax unified
	.arm
	.fpu softvfp
	.type	__VERIFIER_nondet_bool, %function
__VERIFIER_nondet_bool:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	mov	r0, r3
	pop	{fp, pc}
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.comm	_diverge_delta,4,4
	.comm	_x__diverge_delta,4,4
	.comm	p2_l3,1,1
	.comm	_x_p2_l3,1,1
	.comm	p2_l2,1,1
	.comm	_x_p2_l2,1,1
	.comm	p2_l1,1,1
	.comm	_x_p2_l1,1,1
	.comm	p2_evt,1,1
	.comm	_x_p2_evt,1,1
	.comm	delta,4,4
	.comm	_x_delta,4,4
	.comm	v1,4,4
	.comm	_x_v1,4,4
	.comm	v2,1,1
	.comm	_x_v2,1,1
	.comm	p2_l0,1,1
	.comm	_x_p2_l0,1,1
	.comm	p2_c,4,4
	.comm	_x_p2_c,4,4
	.comm	p0_l3,1,1
	.comm	_x_p0_l3,1,1
	.comm	p1_l2,1,1
	.comm	_x_p1_l2,1,1
	.comm	p0_evt,1,1
	.comm	_x_p0_evt,1,1
	.comm	p0_l1,1,1
	.comm	_x_p0_l1,1,1
	.comm	p1_l0,1,1
	.comm	_x_p1_l0,1,1
	.comm	p1_c,4,4
	.comm	_x_p1_c,4,4
	.comm	p1_l3,1,1
	.comm	_x_p1_l3,1,1
	.comm	p0_l2,1,1
	.comm	_x_p0_l2,1,1
	.comm	p0_c,4,4
	.comm	_x_p0_c,4,4
	.comm	p0_l0,1,1
	.comm	_x_p0_l0,1,1
	.comm	p1_evt,1,1
	.comm	_x_p1_evt,1,1
	.comm	p1_l1,1,1
	.comm	_x_p1_l1,1,1
	.global	__aeabi_fcmpeq
	.global	__aeabi_fcmple
	.global	__aeabi_fcmpge
	.global	__aeabi_f2d
	.global	__aeabi_dsub
	.global	__aeabi_dadd
	.global	__aeabi_dcmpeq
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, fp, lr}
	add	fp, sp, #20
	sub	sp, sp, #8
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L255
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+168
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+172
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+128
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+148
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L255+144
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L255+120
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+132
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+176
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L255+136
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+4
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+8
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+12
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+16
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+20
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L255+24
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+28
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+32
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L255+36
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+40
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+44
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+48
	strb	r2, [r3]
	ldr	r3, .L255+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L255+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L255+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L255+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L255+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L255+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L6
	ldr	r3, .L255+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L6
	ldr	r3, .L255+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L6
	ldr	r3, .L255+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L6:
	ldr	r3, .L255+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L255+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L255+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L255+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L7
.L8:
	ldr	r3, .L255+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L9
	ldr	r3, .L255+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L9
	ldr	r3, .L255+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L9
	ldr	r3, .L255+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L9:
	ldr	r3, .L255+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L10
	ldr	r3, .L255+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L10
	ldr	r3, .L255+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L10
	ldr	r3, .L255+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L10:
	ldr	r3, .L255+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L11
	ldr	r3, .L255+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L11
	ldr	r3, .L255+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L11
	ldr	r3, .L255+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L11:
	ldr	r3, .L255+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L12
	ldr	r3, .L255+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L12
	ldr	r3, .L255+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L12
	ldr	r3, .L255+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L7
.L12:
	ldr	r3, .L255+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L13
	ldr	r3, .L255+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L13
	ldr	r3, .L255+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L13
	ldr	r3, .L255+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L13:
	ldr	r3, .L255+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L14
	ldr	r3, .L255+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L14
	ldr	r3, .L255+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L14
	ldr	r3, .L255+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L14:
	ldr	r3, .L255+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L255+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L255+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L255+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L7:
	ldr	r3, .L255+136
	ldr	r3, [r3]	@ float
	ldr	r1, .L255+112
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L15
	ldr	r3, .L255+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L16
	ldr	r3, .L255+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L16
	ldr	r3, .L255+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L16
	ldr	r3, .L255+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L16:
	ldr	r3, .L255+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L17
	ldr	r3, .L255+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L17
	ldr	r3, .L255+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L17
	ldr	r3, .L255+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L17:
	ldr	r3, .L255+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L18
	ldr	r3, .L255+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L18
	ldr	r3, .L255+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L18
	ldr	r3, .L255+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L18:
	ldr	r3, .L255+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L15
	ldr	r3, .L255+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L15
	ldr	r3, .L255+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L15
	ldr	r3, .L255+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L15:
	ldr	r3, .L255+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L255+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L255+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L255+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L255+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L255+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L20
	ldr	r3, .L255+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L20
	ldr	r3, .L255+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L20
	ldr	r3, .L255+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L21
.L20:
	ldr	r3, .L255+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L22
	ldr	r3, .L255+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L22
	ldr	r3, .L255+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L22
	ldr	r3, .L255+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L21
.L22:
	ldr	r3, .L255+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L23
	ldr	r3, .L255+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L23
	ldr	r3, .L255+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L23
	ldr	r3, .L255+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L21
.L23:
	ldr	r3, .L255+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L24
	ldr	r3, .L255+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L24
	ldr	r3, .L255+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L24
	ldr	r3, .L255+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L21
.L24:
	ldr	r3, .L255+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L25
	ldr	r3, .L255+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L25
	ldr	r3, .L255+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L25
	ldr	r3, .L255+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L21
.L25:
	ldr	r3, .L255+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L26
	ldr	r3, .L255+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L26
	ldr	r3, .L255+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L26
	ldr	r3, .L255+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L21
.L26:
	ldr	r3, .L255+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L27
	ldr	r3, .L255+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L27
	ldr	r3, .L255+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L27
	ldr	r3, .L255+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L21
.L27:
	ldr	r3, .L255+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L28
	ldr	r3, .L255+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L28
	ldr	r3, .L255+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L28
	ldr	r3, .L255+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L21
.L28:
	ldr	r3, .L255+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L255+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L255+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L255+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L21:
	ldr	r3, .L255+24
	ldr	r3, [r3]	@ float
	ldr	r1, .L255+112
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L29
	ldr	r3, .L255+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L30
	ldr	r3, .L255+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L30
	ldr	r3, .L255+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L30
	ldr	r3, .L255+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L30:
	ldr	r3, .L255+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L31
	ldr	r3, .L255+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
	ldr	r3, .L255+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L31
	ldr	r3, .L255+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L31:
	ldr	r3, .L255+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L32
	ldr	r3, .L255+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L32
	ldr	r3, .L255+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L32
	ldr	r3, .L255+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L32:
	ldr	r3, .L255+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L29
	ldr	r3, .L255+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L29
	ldr	r3, .L255+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L29
	ldr	r3, .L255+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L29:
	ldr	r3, .L255+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L255+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L255+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L255+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L255+36
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L255+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L34
	ldr	r3, .L255+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L34
	ldr	r3, .L255+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L34
	ldr	r3, .L255+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
.L34:
	ldr	r3, .L255+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L36
	ldr	r3, .L255+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L36
	ldr	r3, .L255+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L36
	ldr	r3, .L255+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L35
.L36:
	ldr	r3, .L255+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L37
	ldr	r3, .L255+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L37
	ldr	r3, .L255+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L37
	ldr	r3, .L255+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
.L37:
	ldr	r3, .L255+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L38
	ldr	r3, .L255+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L38
	ldr	r3, .L255+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L38
	ldr	r3, .L255+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
.L38:
	ldr	r3, .L255+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L39
	ldr	r3, .L255+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L39
	ldr	r3, .L255+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L39
	ldr	r3, .L255+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
.L39:
	ldr	r3, .L255+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L40
	ldr	r3, .L255+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L40
	ldr	r3, .L255+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L40
	ldr	r3, .L255+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L35
.L40:
	ldr	r3, .L255+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L41
	ldr	r3, .L255+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L41
	ldr	r3, .L255+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L41
	ldr	r3, .L255+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
.L41:
	ldr	r3, .L255+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L42
	ldr	r3, .L255+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L42
	ldr	r3, .L255+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L42
	ldr	r3, .L255+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
.L42:
	ldr	r3, .L255+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L255+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L255+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L255+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L35:
	ldr	r3, .L255+36
	ldr	r3, [r3]	@ float
	ldr	r1, .L255+112
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L43
	ldr	r3, .L255+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L44
	ldr	r3, .L255+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L44
	ldr	r3, .L255+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L44
	ldr	r3, .L255+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L44:
	ldr	r3, .L255+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L45
	ldr	r3, .L255+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L45
	ldr	r3, .L255+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L45
	ldr	r3, .L255+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L45:
	ldr	r3, .L255+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L46
	ldr	r3, .L255+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L46
	ldr	r3, .L255+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L46
	ldr	r3, .L255+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L46:
	ldr	r3, .L255+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L43
	ldr	r3, .L255+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L43
	ldr	r3, .L255+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L43
	ldr	r3, .L255+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L43:
	ldr	r3, .L255+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L255+120
	ldr	r3, [r3]
	cmp	r3, #3
	beq	.L48
	ldr	r3, .L255+120
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L48
	ldr	r3, .L255+120
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L48
	ldr	r3, .L255+120
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L4
.L48:
	ldr	r3, .L255+144
	ldr	r3, [r3]	@ float
	ldr	r2, .L255
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	mov	r3, #1
	b	.L50
.L4:
	mov	r3, #0
.L50:
	str	r3, [fp, #-24]
	b	.L51
.L256:
	.align	2
.L255:
	.word	_diverge_delta
	.word	p0_l3
	.word	p1_l2
	.word	p0_evt
	.word	p0_l1
	.word	p1_l0
	.word	p1_c
	.word	p1_l3
	.word	p0_l2
	.word	p0_c
	.word	p0_l0
	.word	p1_evt
	.word	p1_l1
	.word	_x__diverge_delta
	.word	_x_p2_evt
	.word	_x_delta
	.word	_x_p0_l3
	.word	_x_p1_l2
	.word	_x_p0_evt
	.word	_x_p0_l1
	.word	_x_p1_l0
	.word	_x_p1_c
	.word	_x_p1_l3
	.word	_x_p0_l2
	.word	_x_p0_c
	.word	_x_p0_l0
	.word	_x_p1_evt
	.word	_x_p1_l1
	.word	1098907648
	.word	_x_v2
	.word	v1
	.word	_x_v1
	.word	p2_l1
	.word	v2
	.word	p2_c
	.word	_x_p2_c
	.word	delta
	.word	p2_evt
	.word	_x_p2_l3
	.word	_x_p2_l2
	.word	_x_p2_l0
	.word	_x_p2_l1
	.word	p2_l3
	.word	p2_l2
	.word	p2_l0
.L234:
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L255+52
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+152
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+156
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+164
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+56
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L255+60
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L255+124
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+116
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+160
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L255+140
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+64
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+68
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+72
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+76
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+80
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L255+84
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+88
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+92
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L255+96
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+100
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+104
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L255+108
	strb	r2, [r3]
	ldr	r3, .L255+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L52
	ldr	r3, .L255+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L52
	ldr	r3, .L255+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L52
	ldr	r3, .L255+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L53
.L52:
	ldr	r3, .L255+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L54
	ldr	r3, .L255+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L54
	ldr	r3, .L255+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L54
	ldr	r3, .L255+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L53
.L54:
	ldr	r3, .L255+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L55
	ldr	r3, .L255+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L55
	ldr	r3, .L255+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L55
	ldr	r3, .L255+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L53
.L55:
	ldr	r3, .L255+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L56
	ldr	r3, .L255+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L56
	ldr	r3, .L255+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L56
	ldr	r3, .L255+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L53
.L56:
	ldr	r3, .L255+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L57
	ldr	r3, .L255+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L57
	ldr	r3, .L255+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L57
	ldr	r3, .L255+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L53
.L57:
	ldr	r3, .L255+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L58
	ldr	r3, .L255+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L58
	ldr	r3, .L255+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L58
	ldr	r3, .L255+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L53
.L58:
	ldr	r3, .L255+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L255+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L255+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L255+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L53
.L59:
	ldr	r3, .L255+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L60
	ldr	r3, .L255+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L60
	ldr	r3, .L255+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L60
	ldr	r3, .L255+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L53
.L60:
	ldr	r3, .L255+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L255+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L255+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L255+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L53:
	ldr	r3, .L255+140
	ldr	r3, [r3]	@ float
	ldr	r1, .L255+112
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L62
	ldr	r3, .L255+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L255+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L255+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L255+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L63:
	ldr	r3, .L255+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L64
	ldr	r3, .L255+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L64
	ldr	r3, .L255+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L64
	ldr	r3, .L255+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L64:
	ldr	r3, .L255+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L65
	ldr	r3, .L255+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L65
	ldr	r3, .L255+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L65
	ldr	r3, .L255+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L65:
	ldr	r3, .L255+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L62
	ldr	r3, .L255+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L62
	ldr	r3, .L255+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L62
	ldr	r3, .L255+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L62:
	ldr	r3, .L255+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L66
	ldr	r3, .L255+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L255+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L255+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L255+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L255+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L255+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L255+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L255+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L255+144
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L255+136
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L255+140
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L61
.L66:
	ldr	r3, .L255+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L68
	ldr	r3, .L255+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L255+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L255+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L255+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L255+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L255+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L255+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L255+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L255+144
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L255+136
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L255+140
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L61
.L68:
	ldr	r3, .L255+120
	ldr	r2, [r3]
	ldr	r3, .L255+124
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L70
	ldr	r3, .L255+120
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L70
	ldr	r3, .L255+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L70
	ldr	r3, .L255+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L70
	ldr	r3, .L255+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L70
	ldr	r3, .L255+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L70
	ldr	r3, .L255+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L255+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L70
	ldr	r3, .L255+140
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L71
.L70:
	ldr	r3, .L255+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L71
	ldr	r3, .L255+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L71
	ldr	r3, .L255+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L71
	ldr	r3, .L255+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L71
	ldr	r3, .L255+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L71
	ldr	r3, .L255+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L71:
	ldr	r3, .L255+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L255+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L72
	ldr	r3, .L255+140
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L72
	ldr	r3, .L255+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L72
	ldr	r3, .L255+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L72
	ldr	r3, .L255+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L72
	ldr	r3, .L255+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L72
	ldr	r3, .L255+124
	ldr	r3, [r3]
	cmp	r3, #3
	beq	.L74
.L72:
	ldr	r3, .L255+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L74
	ldr	r3, .L255+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L74
	ldr	r3, .L255+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L74
	ldr	r3, .L255+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L74
	ldr	r3, .L255+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L74
	ldr	r3, .L255+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L74:
	ldr	r3, .L255+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L255+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L75
	ldr	r3, .L255+120
	ldr	r2, [r3]
	ldr	r3, .L255+124
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L75
	ldr	r3, .L255+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L76
	ldr	r3, .L255+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L76
	ldr	r3, .L255+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L76
	ldr	r3, .L255+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L77
.L76:
	ldr	r3, .L255+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L75
	ldr	r3, .L255+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L75
	ldr	r3, .L255+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L75
	ldr	r3, .L255+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L75
.L77:
	ldr	r3, .L255+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L255+140
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L78
.L75:
	ldr	r3, .L255+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L78
	ldr	r3, .L255+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L78
	ldr	r3, .L255+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L78
	ldr	r3, .L255+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L78
	ldr	r3, .L255+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L78
	ldr	r3, .L255+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L78:
	ldr	r3, .L255+120
	ldr	r3, [r3]
	cmp	r3, #3
	bne	.L79
	ldr	r3, .L255+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L79
	ldr	r3, .L255+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L79
	ldr	r3, .L255+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L79
	ldr	r3, .L255+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L79
	ldr	r3, .L255+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L79
	ldr	r3, .L255+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L79
	ldr	r3, .L255+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L79
	ldr	r3, .L255+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L79
	ldr	r3, .L255+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L79
	ldr	r3, .L255+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L79:
	ldr	r3, .L255+120
	ldr	r3, [r3]
	cmp	r3, #3
	bne	.L80
	ldr	r3, .L255+136
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L255+112
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L81
	mov	r3, #0
	mov	r4, r3
.L81:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L82
.L80:
	ldr	r3, .L255+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L82
	ldr	r3, .L255+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L82
	ldr	r3, .L255+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L82
	ldr	r3, .L255+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L82
	ldr	r3, .L255+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L82
	ldr	r3, .L255+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L82
	ldr	r3, .L255+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L82
	ldr	r3, .L255+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L82
	ldr	r3, .L255+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L82
	ldr	r3, .L255+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L82:
	ldr	r3, .L255+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L255+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L83
	ldr	r3, .L255+120
	ldr	r2, [r3]
	ldr	r3, .L255+124
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L83
	ldr	r3, .L255+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L84
	ldr	r3, .L255+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L84
	ldr	r3, .L255+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L84
	ldr	r3, .L255+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L85
.L84:
	ldr	r3, .L255+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L83
	ldr	r3, .L255+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L83
	ldr	r3, .L255+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L83
	ldr	r3, .L255+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L85
.L83:
	ldr	r3, .L255+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L85
	ldr	r3, .L255+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L85
	ldr	r3, .L255+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L85
	ldr	r3, .L255+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L85
	ldr	r3, .L255+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L85
	ldr	r3, .L255+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L85:
	ldr	r3, .L255+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L86
	ldr	r3, .L255+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L255+140
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L87
.L86:
	ldr	r3, .L255+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L87
	ldr	r3, .L255+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L87
	ldr	r3, .L255+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L87
	ldr	r3, .L255+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L87
	ldr	r3, .L255+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L87
	ldr	r3, .L255+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L87
	ldr	r3, .L255+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L87
	ldr	r3, .L255+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L87
	ldr	r3, .L255+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L87
	ldr	r3, .L257
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L87:
	ldr	r3, .L257+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L88
	ldr	r3, .L257+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L89
.L88:
	ldr	r3, .L257+12
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L89
	ldr	r3, .L257+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L89
	ldr	r3, .L257+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L89
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L89
	ldr	r3, .L257+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L89
	ldr	r3, .L257
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L89
	ldr	r3, .L257+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L89
	ldr	r3, .L257+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L89
	ldr	r3, .L257+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L89
	ldr	r3, .L257+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L89:
	ldr	r3, .L257+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L90
	ldr	r3, .L257+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L90
	ldr	r3, .L257+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L90
	ldr	r3, .L257+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L90
	ldr	r3, .L257+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L90
	ldr	r3, .L257+56
	ldr	r2, [r3]
	ldr	r3, .L257+60
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L90
	ldr	r3, .L257+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L91
.L90:
	ldr	r3, .L257+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L91
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L91
	ldr	r3, .L257+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L91
	ldr	r3, .L257
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L91
	ldr	r3, .L257+12
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L91
	ldr	r3, .L257+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L91:
	ldr	r3, .L257+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L257+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L92
	ldr	r3, .L257+56
	ldr	r2, [r3]
	ldr	r3, .L257+60
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L92
	ldr	r3, .L257+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L257+8
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L92
	ldr	r3, .L257+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L94
	ldr	r3, .L257+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L94
	ldr	r3, .L257+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L94
	ldr	r3, .L257+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L95
.L94:
	ldr	r3, .L257+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L92
	ldr	r3, .L257+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L92
	ldr	r3, .L257+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L92
	ldr	r3, .L257+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L95
.L92:
	ldr	r3, .L257+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L95
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L95
	ldr	r3, .L257+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L95
	ldr	r3, .L257
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L95
	ldr	r3, .L257+12
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L95
	ldr	r3, .L257+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L95:
	ldr	r3, .L257+56
	ldr	r3, [r3]
	cmp	r3, #3
	bne	.L96
	ldr	r3, .L257+12
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L96
	ldr	r3, .L257+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L96
	ldr	r3, .L257+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L96
	ldr	r3, .L257+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L96
	ldr	r3, .L257+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L96
	ldr	r3, .L257+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L96
	ldr	r3, .L257+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L96
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L96
	ldr	r3, .L257+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L96
	ldr	r3, .L257
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L96:
	ldr	r3, .L257+56
	ldr	r3, [r3]
	cmp	r3, #3
	beq	.L97
	ldr	r3, .L257+12
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L97
	ldr	r3, .L257+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L97
	ldr	r3, .L257+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L97
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L97
	ldr	r3, .L257+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L97
	ldr	r3, .L257
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L97
	ldr	r3, .L257+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L97
	ldr	r3, .L257+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L97
	ldr	r3, .L257+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L97
	ldr	r3, .L257+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L97:
	ldr	r3, .L257+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L257+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L98
	ldr	r3, .L257+56
	ldr	r2, [r3]
	ldr	r3, .L257+60
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L98
	ldr	r3, .L257+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L98
	ldr	r3, .L257+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L98
	ldr	r3, .L257+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L98
	ldr	r3, .L257+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L98
	ldr	r3, .L257+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L99
.L98:
	ldr	r3, .L257+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L99
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L99
	ldr	r3, .L257
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L99
	ldr	r3, .L257+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L99
	ldr	r3, .L257+12
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L99
	ldr	r3, .L257+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L99:
	ldr	r3, .L257+56
	ldr	r2, [r3]
	ldr	r3, .L257+60
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L100
	ldr	r3, .L257+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L100
	ldr	r3, .L257+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L100
	ldr	r3, .L257+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L100
	ldr	r3, .L257+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L100
	ldr	r3, .L257+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L100
	ldr	r3, .L257+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L102
.L100:
	ldr	r3, .L257+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L102
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L102
	ldr	r3, .L257+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L102
	ldr	r3, .L257
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L102
	ldr	r3, .L257+12
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L102
	ldr	r3, .L257+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L102:
	ldr	r3, .L257+60
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L103
	ldr	r3, .L257+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L103
	ldr	r3, .L257+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L103
	ldr	r3, .L257+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L103
	ldr	r3, .L257+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L103
	ldr	r3, .L257+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L257+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L103
	ldr	r3, .L257+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L257+8
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L104
.L103:
	ldr	r3, .L257+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L104
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L104
	ldr	r3, .L257+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L104
	ldr	r3, .L257
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L104
	ldr	r3, .L257+12
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L104
	ldr	r3, .L257+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L104:
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L105
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L105
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L105
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L106
.L105:
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L107
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L107
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L107
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L106
.L107:
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L108
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L108
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L108
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L106
.L108:
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L109
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L109
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L109
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L106
.L109:
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L110
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L110
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L110
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L106
.L110:
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L111
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L111
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L111
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L106
.L111:
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L112
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L112
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L112
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L106
.L112:
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L113
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L113
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L113
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L106
.L113:
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L106:
	ldr	r3, .L257+92
	ldr	r3, [r3]	@ float
	ldr	r1, .L257+52
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L114
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L115
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L115
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L115
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L115:
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L116
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L116
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L116
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L116:
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L117
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L117
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L117
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L117:
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L114
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L114
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L114
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L114:
	ldr	r3, .L257+12
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L118
	ldr	r3, .L257+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L257+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L257+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L257+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L257+12
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L257+88
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L257+92
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L61
.L118:
	ldr	r3, .L257+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L120
	ldr	r3, .L257+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L257+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L257+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L257+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L257+12
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L257+88
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L257+92
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L61
.L120:
	ldr	r3, .L257+56
	ldr	r2, [r3]
	ldr	r3, .L257+60
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L122
	ldr	r3, .L257+56
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L122
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L122
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L122
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L122
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L122
	ldr	r3, .L257+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L257+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L122
	ldr	r3, .L257+92
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L123
.L122:
	ldr	r3, .L257+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L123
	ldr	r3, .L257+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L123
	ldr	r3, .L257+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L123
	ldr	r3, .L257+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L123
	ldr	r3, .L257+12
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L123
	b	.L258
.L259:
	.align	2
.L257:
	.word	p2_l1
	.word	v2
	.word	_x_p2_c
	.word	delta
	.word	p2_evt
	.word	p2_l3
	.word	p2_l2
	.word	p2_l0
	.word	_x_p2_l3
	.word	_x_p2_l2
	.word	_x_p2_l0
	.word	_x_p2_l1
	.word	p2_c
	.word	1098907648
	.word	v1
	.word	_x_v1
	.word	_x_p1_l3
	.word	_x_p1_l2
	.word	_x_p1_l0
	.word	_x_p1_l1
	.word	v2
	.word	_x_v2
	.word	p1_c
	.word	_x_p1_c
	.word	p1_l3
	.word	p1_l2
	.word	p1_l0
	.word	p1_l1
	.word	delta
	.word	p1_evt
	.word	_x_p0_l2
	.word	_x_p0_l0
	.word	_x_p0_l1
	.word	_x_p0_l3
.L258:
	ldr	r3, .L257+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L123:
	ldr	r3, .L257+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L257+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L124
	ldr	r3, .L257+92
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L124
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L124
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L124
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L124
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L124
	ldr	r3, .L257+60
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L126
.L124:
	ldr	r3, .L257+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L126
	ldr	r3, .L257+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L126
	ldr	r3, .L257+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L126
	ldr	r3, .L257+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L126
	ldr	r3, .L257+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L126
	ldr	r3, .L257+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L126:
	ldr	r3, .L257+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L257+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L127
	ldr	r3, .L257+56
	ldr	r2, [r3]
	ldr	r3, .L257+60
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L127
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L128
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L128
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L128
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L129
.L128:
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L127
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L127
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L127
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L127
.L129:
	ldr	r3, .L257+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L257+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L130
.L127:
	ldr	r3, .L257+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L130
	ldr	r3, .L257+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L130
	ldr	r3, .L257+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L130
	ldr	r3, .L257+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L130
	ldr	r3, .L257+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L130
	ldr	r3, .L257+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L130:
	ldr	r3, .L257+56
	ldr	r3, [r3]
	cmp	r3, #2
	bne	.L131
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L131
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L131
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L131
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L131
	ldr	r3, .L257+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L131
	ldr	r3, .L257+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L131
	ldr	r3, .L257+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L131
	ldr	r3, .L257+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L131
	ldr	r3, .L257+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L131
	ldr	r3, .L257+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L131:
	ldr	r3, .L257+56
	ldr	r3, [r3]
	cmp	r3, #2
	bne	.L132
	ldr	r3, .L257+88
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L257+52
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L133
	mov	r3, #0
	mov	r4, r3
.L133:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L134
.L132:
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L134
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L134
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L134
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L134
	ldr	r3, .L257+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L134
	ldr	r3, .L257+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L134
	ldr	r3, .L257+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L134
	ldr	r3, .L257+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L134
	ldr	r3, .L257+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L134
	ldr	r3, .L257+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L134:
	ldr	r3, .L257+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L257+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L135
	ldr	r3, .L257+56
	ldr	r2, [r3]
	ldr	r3, .L257+60
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L135
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L136
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L136
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L136
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L137
.L136:
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L135
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L135
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L135
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L137
.L135:
	ldr	r3, .L257+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L137
	ldr	r3, .L257+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L137
	ldr	r3, .L257+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L137
	ldr	r3, .L257+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L137
	ldr	r3, .L257+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L137
	ldr	r3, .L257+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L137:
	ldr	r3, .L257+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L138
	ldr	r3, .L257+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L257+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L139
.L138:
	ldr	r3, .L257+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L139
	ldr	r3, .L257+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L139
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L139
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L139
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L139
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L139
	ldr	r3, .L257+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L139
	ldr	r3, .L257+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L139
	ldr	r3, .L257+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L139
	ldr	r3, .L257+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L139:
	ldr	r3, .L257+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L140
	ldr	r3, .L257+92
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L141
.L140:
	ldr	r3, .L257+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L141
	ldr	r3, .L257+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L141
	ldr	r3, .L257+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L141
	ldr	r3, .L257+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L141
	ldr	r3, .L257+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L141
	ldr	r3, .L257+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L141
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L141
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L141
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L141
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L141:
	ldr	r3, .L257+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L142
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L142
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L142
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L142
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L142
	ldr	r3, .L257+56
	ldr	r2, [r3]
	ldr	r3, .L257+60
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L142
	ldr	r3, .L257+92
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L143
.L142:
	ldr	r3, .L257+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L143
	ldr	r3, .L257+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L143
	ldr	r3, .L257+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L143
	ldr	r3, .L257+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L143
	ldr	r3, .L257+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L143
	ldr	r3, .L257+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L143:
	ldr	r3, .L257+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L257+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L144
	ldr	r3, .L257+56
	ldr	r2, [r3]
	ldr	r3, .L257+60
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L144
	ldr	r3, .L257+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L257+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L144
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L146
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L146
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L146
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L147
.L146:
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L144
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L144
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L144
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L147
.L144:
	ldr	r3, .L257+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L147
	ldr	r3, .L257+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L147
	ldr	r3, .L257+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L147
	ldr	r3, .L257+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L147
	ldr	r3, .L257+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L147
	ldr	r3, .L257+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L147:
	ldr	r3, .L257+56
	ldr	r3, [r3]
	cmp	r3, #2
	bne	.L148
	ldr	r3, .L257+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L148
	ldr	r3, .L257+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L148
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L148
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L148
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L148
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L148
	ldr	r3, .L257+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L148
	ldr	r3, .L257+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L148
	ldr	r3, .L257+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L148
	ldr	r3, .L257+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L148:
	ldr	r3, .L257+56
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L149
	ldr	r3, .L257+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L149
	ldr	r3, .L257+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L149
	ldr	r3, .L257+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L149
	ldr	r3, .L257+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L149
	ldr	r3, .L257+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L149
	ldr	r3, .L257+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L149
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L149
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L149
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L149
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L149:
	ldr	r3, .L257+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L257+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L150
	ldr	r3, .L257+56
	ldr	r2, [r3]
	ldr	r3, .L257+60
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L150
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L150
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L150
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L150
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L150
	ldr	r3, .L257+92
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L151
.L150:
	ldr	r3, .L257+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L151
	ldr	r3, .L257+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
	ldr	r3, .L257+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
	ldr	r3, .L257+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L151
	ldr	r3, .L257+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L151
	ldr	r3, .L257+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L151:
	ldr	r3, .L257+56
	ldr	r2, [r3]
	ldr	r3, .L257+60
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L152
	ldr	r3, .L257+92
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L152
	ldr	r3, .L257+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L152
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L152
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L152
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L152
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L154
.L152:
	ldr	r3, .L257+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L154
	ldr	r3, .L257+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L154
	ldr	r3, .L257+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L154
	ldr	r3, .L257+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L154
	ldr	r3, .L257+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L154
	ldr	r3, .L257+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L154:
	ldr	r3, .L257+60
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L155
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L155
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L155
	ldr	r3, .L257+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L155
	ldr	r3, .L257+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L155
	ldr	r3, .L257+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L257+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L155
	ldr	r3, .L257+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L257+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L156
.L155:
	ldr	r3, .L257+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L156
	ldr	r3, .L257+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L156
	ldr	r3, .L257+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L156
	ldr	r3, .L257+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L156
	ldr	r3, .L257+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L156
	ldr	r3, .L257+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L156:
	ldr	r3, .L257+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L157
	ldr	r3, .L257+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L157
	ldr	r3, .L257+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L157
	ldr	r3, .L257+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L158
.L157:
	ldr	r3, .L257+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L159
	ldr	r3, .L257+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L159
	ldr	r3, .L257+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L159
	ldr	r3, .L257+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L158
.L159:
	ldr	r3, .L257+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L160
	ldr	r3, .L257+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L160
	ldr	r3, .L257+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L160
	ldr	r3, .L257+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L158
.L160:
	ldr	r3, .L257+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L161
	ldr	r3, .L257+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L161
	ldr	r3, .L257+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L161
	ldr	r3, .L257+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L158
.L161:
	ldr	r3, .L257+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L162
	ldr	r3, .L257+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L162
	ldr	r3, .L257+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L162
	ldr	r3, .L257+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L158
.L162:
	ldr	r3, .L257+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L163
	ldr	r3, .L260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L163
	ldr	r3, .L260+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L163
	ldr	r3, .L260+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L158
.L163:
	ldr	r3, .L260+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L164
	ldr	r3, .L260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L164
	ldr	r3, .L260+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L164
	ldr	r3, .L260+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L158
.L164:
	ldr	r3, .L260+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L165
	ldr	r3, .L260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L165
	ldr	r3, .L260+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L165
	ldr	r3, .L260+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L158
.L165:
	ldr	r3, .L260+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L260+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L260+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L158:
	ldr	r3, .L260+164
	ldr	r3, [r3]	@ float
	ldr	r1, .L260+16
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L166
	ldr	r3, .L260+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L167
	ldr	r3, .L260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L167
	ldr	r3, .L260+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L167
	ldr	r3, .L260+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L167:
	ldr	r3, .L260+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L168
	ldr	r3, .L260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L168
	ldr	r3, .L260+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L168
	ldr	r3, .L260+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L168:
	ldr	r3, .L260+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L169
	ldr	r3, .L260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L169
	ldr	r3, .L260+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L169
	ldr	r3, .L260+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L169:
	ldr	r3, .L260+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L166
	ldr	r3, .L260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L166
	ldr	r3, .L260+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L166
	ldr	r3, .L260+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L166:
	ldr	r3, .L260+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L170
	ldr	r3, .L260+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L260+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L260+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L260+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L260+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L260+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L260+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L260+64
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L260+168
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L260+164
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L61
.L170:
	ldr	r3, .L260+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L172
	ldr	r3, .L260+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L260+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L260+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L260+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L260+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L260+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L260+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L260+64
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L260+168
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L260+164
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L61
.L172:
	ldr	r3, .L260+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L174
	ldr	r3, .L260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L174
	ldr	r3, .L260+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
	ldr	r3, .L260+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L174
	ldr	r3, .L260+72
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L174
	ldr	r3, .L260+164
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L174
	ldr	r3, .L260+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L260+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L174
	ldr	r3, .L260+72
	ldr	r2, [r3]
	ldr	r3, .L260+68
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L176
.L174:
	ldr	r3, .L260+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L176
	ldr	r3, .L260+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L176
	ldr	r3, .L260+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L176
	ldr	r3, .L260+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L176
	ldr	r3, .L260+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L176
	ldr	r3, .L260+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L61
.L176:
	ldr	r3, .L260+164
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L178
	ldr	r3, .L260+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L260+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L178
	ldr	r3, .L260+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L178
	ldr	r3, .L260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L178
	ldr	r3, .L260+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L178
	ldr	r3, .L260+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L178
	ldr	r3, .L260+68
	ldr	r3, [r3]
	cmp	r3, #1
	beq	.L180
.L178:
	ldr	r3, .L260+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L180
	ldr	r3, .L260+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L180
	ldr	r3, .L260+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L180
	ldr	r3, .L260+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L180
	ldr	r3, .L260+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L180
	ldr	r3, .L260+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L61
.L180:
	ldr	r3, .L260+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L182
	ldr	r3, .L260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L182
	ldr	r3, .L260+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L182
	ldr	r3, .L260+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L183
.L182:
	ldr	r3, .L260+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L184
	ldr	r3, .L260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L184
	ldr	r3, .L260+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L184
	ldr	r3, .L260+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L184
.L183:
	ldr	r3, .L260+168
	ldr	r3, [r3]	@ float
	ldr	r2, .L260+164
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L184
	ldr	r3, .L260+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L260+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L184
	ldr	r3, .L260+72
	ldr	r2, [r3]
	ldr	r3, .L260+68
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L186
.L184:
	ldr	r3, .L260+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L186
	ldr	r3, .L260+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L186
	ldr	r3, .L260+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L186
	ldr	r3, .L260+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L186
	ldr	r3, .L260+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L186
	ldr	r3, .L260+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L61
.L186:
	ldr	r3, .L260+72
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L188
	ldr	r3, .L260+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L188
	ldr	r3, .L260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L188
	ldr	r3, .L260+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L188
	ldr	r3, .L260+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L188
	ldr	r3, .L260+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L188
	ldr	r3, .L260+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L188
	ldr	r3, .L260+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L188
	ldr	r3, .L260+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L188
	ldr	r3, .L260+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L188
	ldr	r3, .L260+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L61
.L188:
	ldr	r3, .L260+72
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L190
	ldr	r3, .L260+168
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L260+16
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L191
	mov	r3, #0
	mov	r4, r3
.L191:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L192
.L190:
	ldr	r3, .L260+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L192
	ldr	r3, .L260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L192
	ldr	r3, .L260+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L192
	ldr	r3, .L260+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L192
	ldr	r3, .L260+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L192
	ldr	r3, .L260+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L192
	ldr	r3, .L260+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L192
	ldr	r3, .L260+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L192
	ldr	r3, .L260+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L192
	ldr	r3, .L260+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L61
.L192:
	ldr	r3, .L260+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L260+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L194
	ldr	r3, .L260+72
	ldr	r2, [r3]
	ldr	r3, .L260+68
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L194
	ldr	r3, .L260+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L260+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L260+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L196
.L195:
	ldr	r3, .L260+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L194
	ldr	r3, .L260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L194
	ldr	r3, .L260+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L194
	ldr	r3, .L260+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L196
.L194:
	ldr	r3, .L260+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L196
	ldr	r3, .L260+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L196
	ldr	r3, .L260+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L196
	ldr	r3, .L260+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L196
	ldr	r3, .L260+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L196
	ldr	r3, .L260+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L61
.L196:
	ldr	r3, .L260+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L198
	ldr	r3, .L260+168
	ldr	r3, [r3]	@ float
	ldr	r2, .L260+164
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L199
.L198:
	ldr	r3, .L260+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L199
	ldr	r3, .L260+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L199
	ldr	r3, .L260+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L199
	ldr	r3, .L260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L199
	ldr	r3, .L260+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L199
	ldr	r3, .L260+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L199
	ldr	r3, .L260+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L199
	ldr	r3, .L260+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L199
	ldr	r3, .L260+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L199
	ldr	r3, .L260+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L199:
	ldr	r3, .L260+164
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L200
	ldr	r3, .L260+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L202
.L200:
	ldr	r3, .L260+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L202
	ldr	r3, .L260+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L202
	ldr	r3, .L260+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L202
	ldr	r3, .L260+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L202
	ldr	r3, .L260+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L202
	ldr	r3, .L260+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L202
	ldr	r3, .L260+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L202
	ldr	r3, .L260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L202
	ldr	r3, .L260+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L202
	ldr	r3, .L260+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L202:
	ldr	r3, .L260+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L203
	ldr	r3, .L260+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L203
	ldr	r3, .L260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L203
	ldr	r3, .L260+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L203
	ldr	r3, .L260+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L203
	ldr	r3, .L260+164
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L203
	ldr	r3, .L260+72
	ldr	r2, [r3]
	ldr	r3, .L260+68
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L205
.L203:
	ldr	r3, .L260+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L260+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L260+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L260+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L260+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L260+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L61
.L205:
	ldr	r3, .L260+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L260+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L207
	ldr	r3, .L260+72
	ldr	r2, [r3]
	ldr	r3, .L260+68
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L207
	ldr	r3, .L260+168
	ldr	r3, [r3]	@ float
	ldr	r2, .L260+164
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L207
	ldr	r3, .L260+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L209
	ldr	r3, .L260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L209
	ldr	r3, .L260+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L209
	ldr	r3, .L260+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L210
.L209:
	ldr	r3, .L260+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L207
	ldr	r3, .L260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L207
	ldr	r3, .L260+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L207
	ldr	r3, .L260+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L210
.L207:
	ldr	r3, .L260+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	b	.L261
.L262:
	.align	2
.L260:
	.word	_x_p0_l2
	.word	_x_p0_l0
	.word	_x_p0_l1
	.word	_x_p0_l3
	.word	1098907648
	.word	_x__diverge_delta
	.word	_diverge_delta
	.word	_x_p2_l3
	.word	p2_l3
	.word	_x_p2_l2
	.word	p2_l2
	.word	_x_p2_l1
	.word	p2_l1
	.word	_x_p2_evt
	.word	p2_evt
	.word	_x_delta
	.word	delta
	.word	_x_v1
	.word	v1
	.word	_x_v2
	.word	v2
	.word	_x_p2_l0
	.word	p2_l0
	.word	_x_p2_c
	.word	p2_c
	.word	_x_p0_l3
	.word	p0_l3
	.word	_x_p1_l2
	.word	p1_l2
	.word	_x_p0_evt
	.word	p0_evt
	.word	_x_p0_l1
	.word	p0_l1
	.word	_x_p1_l0
	.word	p1_l0
	.word	_x_p1_c
	.word	p1_c
	.word	_x_p1_l3
	.word	p1_l3
	.word	_x_p0_l2
	.word	p0_l2
	.word	_x_p0_c
	.word	p0_c
	.word	_x_p0_l0
	.word	p0_l0
	.word	_x_p1_evt
	.word	p1_evt
	.word	_x_p1_l1
	.word	p1_l1
.L261:
	cmp	r3, #0
	bne	.L210
	ldr	r3, .L260+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L210
	ldr	r3, .L260+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L210
	ldr	r3, .L260+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L210
	ldr	r3, .L260+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L210
	ldr	r3, .L260+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L61
.L210:
	ldr	r3, .L260+72
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L212
	ldr	r3, .L260+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L212
	ldr	r3, .L260+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L212
	ldr	r3, .L260+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L212
	ldr	r3, .L260+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L212
	ldr	r3, .L260+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L212
	ldr	r3, .L260+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L212
	ldr	r3, .L260+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L212
	ldr	r3, .L260+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L212
	ldr	r3, .L260+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L212
	ldr	r3, .L260+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L212:
	ldr	r3, .L260+72
	ldr	r3, [r3]
	cmp	r3, #1
	beq	.L213
	ldr	r3, .L260+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L213
	ldr	r3, .L260+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L213
	ldr	r3, .L260+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L213
	ldr	r3, .L260+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L213
	ldr	r3, .L260+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L213
	ldr	r3, .L260+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L213
	ldr	r3, .L260+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L213
	ldr	r3, .L260+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L213
	ldr	r3, .L260+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L213
	ldr	r3, .L260+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L213:
	ldr	r3, .L260+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L260+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L214
	ldr	r3, .L260+72
	ldr	r2, [r3]
	ldr	r3, .L260+68
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L214
	ldr	r3, .L260+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L214
	ldr	r3, .L260+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
	ldr	r3, .L260+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
	ldr	r3, .L260+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
	ldr	r3, .L260+164
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L215
.L214:
	ldr	r3, .L260+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L215
	ldr	r3, .L260+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L215
	ldr	r3, .L260+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L215
	ldr	r3, .L260+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L215
	ldr	r3, .L260+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L215
	ldr	r3, .L260+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L61
.L215:
	ldr	r3, .L260+164
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L217
	ldr	r3, .L260+72
	ldr	r2, [r3]
	ldr	r3, .L260+68
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L217
	ldr	r3, .L260+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L217
	ldr	r3, .L260+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L217
	ldr	r3, .L260+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L217
	ldr	r3, .L260+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L217
	ldr	r3, .L260+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L219
.L217:
	ldr	r3, .L260+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L219
	ldr	r3, .L260+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L219
	ldr	r3, .L260+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L219
	ldr	r3, .L260+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L219
	ldr	r3, .L260+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L219
	ldr	r3, .L260+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L61
.L219:
	ldr	r3, .L260+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L221
	ldr	r3, .L260+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L221
	ldr	r3, .L260+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L221
	ldr	r3, .L260+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L221
	ldr	r3, .L260+68
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L221
	ldr	r3, .L260+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L260+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L221
	ldr	r3, .L260+168
	ldr	r3, [r3]	@ float
	ldr	r2, .L260+164
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L222
.L221:
	ldr	r3, .L260+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L222
	ldr	r3, .L260+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L222
	ldr	r3, .L260+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L222
	ldr	r3, .L260+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L222
	ldr	r3, .L260+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L222
	ldr	r3, .L260+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L61
.L222:
	ldr	r3, .L260+68
	ldr	r3, [r3]
	cmp	r3, #3
	beq	.L224
	ldr	r3, .L260+68
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L224
	ldr	r3, .L260+68
	ldr	r3, [r3]
	cmp	r3, #1
	beq	.L224
	ldr	r3, .L260+68
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L61
.L224:
	ldr	r3, .L260+60
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L260+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L226
	ldr	r3, .L260+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L260+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L260+72
	ldr	r2, [r3]
	ldr	r3, .L260+68
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L61
.L226:
	ldr	r3, .L260+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L227
	ldr	r3, .L260+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L227
	ldr	r3, .L260+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L227
	ldr	r3, .L260+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L61
.L227:
	ldr	r3, .L260+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L260+20
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L229
	ldr	r3, .L260+24
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L230
	mov	r3, #0
	mov	r4, r3
.L230:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
.L229:
	ldr	r3, .L260+24
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L231
	ldr	r3, .L260+64
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L260+24
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L260+20
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L61
.L231:
	mov	r3, #1
	b	.L233
.L61:
	mov	r3, #0
.L233:
	str	r3, [fp, #-24]
	ldr	r3, .L260+20
	ldr	r3, [r3]	@ float
	ldr	r2, .L260+24
	str	r3, [r2]	@ float
	ldr	r3, .L260+28
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L260+32
	strb	r2, [r3]
	ldr	r3, .L260+36
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L260+40
	strb	r2, [r3]
	ldr	r3, .L260+44
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L260+48
	strb	r2, [r3]
	ldr	r3, .L260+52
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L260+56
	strb	r2, [r3]
	ldr	r3, .L260+60
	ldr	r3, [r3]	@ float
	ldr	r2, .L260+64
	str	r3, [r2]	@ float
	ldr	r3, .L260+68
	ldr	r3, [r3]
	ldr	r2, .L260+72
	str	r3, [r2]
	ldr	r3, .L260+76
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L260+80
	strb	r2, [r3]
	ldr	r3, .L260+84
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L260+88
	strb	r2, [r3]
	ldr	r3, .L260+92
	ldr	r3, [r3]	@ float
	ldr	r2, .L260+96
	str	r3, [r2]	@ float
	ldr	r3, .L260+100
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L260+104
	strb	r2, [r3]
	ldr	r3, .L260+108
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L260+112
	strb	r2, [r3]
	ldr	r3, .L260+116
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L260+120
	strb	r2, [r3]
	ldr	r3, .L260+124
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L260+128
	strb	r2, [r3]
	ldr	r3, .L260+132
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L260+136
	strb	r2, [r3]
	ldr	r3, .L260+140
	ldr	r3, [r3]	@ float
	ldr	r2, .L260+144
	str	r3, [r2]	@ float
	ldr	r3, .L260+148
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L260+152
	strb	r2, [r3]
	ldr	r3, .L260+156
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L260+160
	strb	r2, [r3]
	ldr	r3, .L260+164
	ldr	r3, [r3]	@ float
	ldr	r2, .L260+168
	str	r3, [r2]	@ float
	ldr	r3, .L260+172
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L260+176
	strb	r2, [r3]
	ldr	r3, .L260+180
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L260+184
	strb	r2, [r3]
	ldr	r3, .L260+188
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L260+192
	strb	r2, [r3]
.L51:
	ldr	r3, [fp, #-24]
	cmp	r3, #0
	bne	.L234
	mov	r3, #0
	mov	r0, r3
	sub	sp, fp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, fp, pc}
	.size	main, .-main
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
