	.file	"517753.c"
	.intel_syntax noprefix
	.text
	.globl	RB_BLKSZ
	.bss
	.align 4
	.type	RB_BLKSZ, @object
	.size	RB_BLKSZ, 4
RB_BLKSZ:
	.zero	4
	.globl	RB_BUFSZ
	.align 4
	.type	RB_BUFSZ, @object
	.size	RB_BUFSZ, 4
RB_BUFSZ:
	.zero	4
	.globl	RB_NO_FETCH
	.align 4
	.type	RB_NO_FETCH, @object
	.size	RB_NO_FETCH, 4
RB_NO_FETCH:
	.zero	4
	.globl	RB_NO_UPDATE
	.align 4
	.type	RB_NO_UPDATE, @object
	.size	RB_NO_UPDATE, 4
RB_NO_UPDATE:
	.zero	4
	.globl	RB_RPTR_WR_EN
	.align 4
	.type	RB_RPTR_WR_EN, @object
	.size	RB_RPTR_WR_EN, 4
RB_RPTR_WR_EN:
	.zero	4
	.globl	UVD
	.align 4
	.type	UVD, @object
	.size	UVD, 4
UVD:
	.zero	4
	.globl	UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT
	.align 4
	.type	UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, @object
	.size	UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 4
UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT:
	.zero	4
	.globl	UVD_LMI_CTRL__CRC_RESET_MASK
	.align 4
	.type	UVD_LMI_CTRL__CRC_RESET_MASK, @object
	.size	UVD_LMI_CTRL__CRC_RESET_MASK, 4
UVD_LMI_CTRL__CRC_RESET_MASK:
	.zero	4
	.globl	UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK
	.align 4
	.type	UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK, @object
	.size	UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK, 4
UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK:
	.zero	4
	.globl	UVD_LMI_CTRL__MASK_MC_URGENT_MASK
	.align 4
	.type	UVD_LMI_CTRL__MASK_MC_URGENT_MASK, @object
	.size	UVD_LMI_CTRL__MASK_MC_URGENT_MASK, 4
UVD_LMI_CTRL__MASK_MC_URGENT_MASK:
	.zero	4
	.globl	UVD_LMI_CTRL__REQ_MODE_MASK
	.align 4
	.type	UVD_LMI_CTRL__REQ_MODE_MASK, @object
	.size	UVD_LMI_CTRL__REQ_MODE_MASK, 4
UVD_LMI_CTRL__REQ_MODE_MASK:
	.zero	4
	.globl	UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK
	.align 4
	.type	UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK, @object
	.size	UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK, 4
UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK:
	.zero	4
	.globl	UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK
	.align 4
	.type	UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK, @object
	.size	UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK, 4
UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK:
	.zero	4
	.globl	UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT
	.align 4
	.type	UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT, @object
	.size	UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT, 4
UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT:
	.zero	4
	.globl	UVD_MASTINT_EN__VCPU_EN_MASK
	.align 4
	.type	UVD_MASTINT_EN__VCPU_EN_MASK, @object
	.size	UVD_MASTINT_EN__VCPU_EN_MASK, 4
UVD_MASTINT_EN__VCPU_EN_MASK:
	.zero	4
	.globl	UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT
	.align 4
	.type	UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, @object
	.size	UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 4
UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT:
	.zero	4
	.globl	UVD_MPC_SET_MUXA0__VARA_1__SHIFT
	.align 4
	.type	UVD_MPC_SET_MUXA0__VARA_1__SHIFT, @object
	.size	UVD_MPC_SET_MUXA0__VARA_1__SHIFT, 4
UVD_MPC_SET_MUXA0__VARA_1__SHIFT:
	.zero	4
	.globl	UVD_MPC_SET_MUXA0__VARA_2__SHIFT
	.align 4
	.type	UVD_MPC_SET_MUXA0__VARA_2__SHIFT, @object
	.size	UVD_MPC_SET_MUXA0__VARA_2__SHIFT, 4
UVD_MPC_SET_MUXA0__VARA_2__SHIFT:
	.zero	4
	.globl	UVD_MPC_SET_MUXA0__VARA_3__SHIFT
	.align 4
	.type	UVD_MPC_SET_MUXA0__VARA_3__SHIFT, @object
	.size	UVD_MPC_SET_MUXA0__VARA_3__SHIFT, 4
UVD_MPC_SET_MUXA0__VARA_3__SHIFT:
	.zero	4
	.globl	UVD_MPC_SET_MUXA0__VARA_4__SHIFT
	.align 4
	.type	UVD_MPC_SET_MUXA0__VARA_4__SHIFT, @object
	.size	UVD_MPC_SET_MUXA0__VARA_4__SHIFT, 4
UVD_MPC_SET_MUXA0__VARA_4__SHIFT:
	.zero	4
	.globl	UVD_MPC_SET_MUXB0__VARB_1__SHIFT
	.align 4
	.type	UVD_MPC_SET_MUXB0__VARB_1__SHIFT, @object
	.size	UVD_MPC_SET_MUXB0__VARB_1__SHIFT, 4
UVD_MPC_SET_MUXB0__VARB_1__SHIFT:
	.zero	4
	.globl	UVD_MPC_SET_MUXB0__VARB_2__SHIFT
	.align 4
	.type	UVD_MPC_SET_MUXB0__VARB_2__SHIFT, @object
	.size	UVD_MPC_SET_MUXB0__VARB_2__SHIFT, 4
UVD_MPC_SET_MUXB0__VARB_2__SHIFT:
	.zero	4
	.globl	UVD_MPC_SET_MUXB0__VARB_3__SHIFT
	.align 4
	.type	UVD_MPC_SET_MUXB0__VARB_3__SHIFT, @object
	.size	UVD_MPC_SET_MUXB0__VARB_3__SHIFT, 4
UVD_MPC_SET_MUXB0__VARB_3__SHIFT:
	.zero	4
	.globl	UVD_MPC_SET_MUXB0__VARB_4__SHIFT
	.align 4
	.type	UVD_MPC_SET_MUXB0__VARB_4__SHIFT, @object
	.size	UVD_MPC_SET_MUXB0__VARB_4__SHIFT, 4
UVD_MPC_SET_MUXB0__VARB_4__SHIFT:
	.zero	4
	.globl	UVD_MPC_SET_MUX__SET_0__SHIFT
	.align 4
	.type	UVD_MPC_SET_MUX__SET_0__SHIFT, @object
	.size	UVD_MPC_SET_MUX__SET_0__SHIFT, 4
UVD_MPC_SET_MUX__SET_0__SHIFT:
	.zero	4
	.globl	UVD_MPC_SET_MUX__SET_1__SHIFT
	.align 4
	.type	UVD_MPC_SET_MUX__SET_1__SHIFT, @object
	.size	UVD_MPC_SET_MUX__SET_1__SHIFT, 4
UVD_MPC_SET_MUX__SET_1__SHIFT:
	.zero	4
	.globl	UVD_MPC_SET_MUX__SET_2__SHIFT
	.align 4
	.type	UVD_MPC_SET_MUX__SET_2__SHIFT, @object
	.size	UVD_MPC_SET_MUX__SET_2__SHIFT, 4
UVD_MPC_SET_MUX__SET_2__SHIFT:
	.zero	4
	.globl	UVD_POWER_STATUS__UVD_PG_EN_MASK
	.align 4
	.type	UVD_POWER_STATUS__UVD_PG_EN_MASK, @object
	.size	UVD_POWER_STATUS__UVD_PG_EN_MASK, 4
UVD_POWER_STATUS__UVD_PG_EN_MASK:
	.zero	4
	.globl	UVD_POWER_STATUS__UVD_PG_MODE_MASK
	.align 4
	.type	UVD_POWER_STATUS__UVD_PG_MODE_MASK, @object
	.size	UVD_POWER_STATUS__UVD_PG_MODE_MASK, 4
UVD_POWER_STATUS__UVD_PG_MODE_MASK:
	.zero	4
	.globl	UVD_RBC_RB_CNTL
	.align 4
	.type	UVD_RBC_RB_CNTL, @object
	.size	UVD_RBC_RB_CNTL, 4
UVD_RBC_RB_CNTL:
	.zero	4
	.globl	UVD_VCPU_CNTL__CLK_EN_MASK
	.align 4
	.type	UVD_VCPU_CNTL__CLK_EN_MASK, @object
	.size	UVD_VCPU_CNTL__CLK_EN_MASK, 4
UVD_VCPU_CNTL__CLK_EN_MASK:
	.zero	4
	.globl	UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK
	.align 4
	.type	UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK, @object
	.size	UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK, 4
UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK:
	.zero	4
	.globl	UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT
	.align 4
	.type	UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT, @object
	.size	UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT, 4
UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT:
	.zero	4
	.globl	mmUVD_LMI_CTRL
	.align 4
	.type	mmUVD_LMI_CTRL, @object
	.size	mmUVD_LMI_CTRL, 4
mmUVD_LMI_CTRL:
	.zero	4
	.globl	mmUVD_LMI_CTRL2
	.align 4
	.type	mmUVD_LMI_CTRL2, @object
	.size	mmUVD_LMI_CTRL2, 4
mmUVD_LMI_CTRL2:
	.zero	4
	.globl	mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH
	.align 4
	.type	mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, @object
	.size	mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, 4
mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH:
	.zero	4
	.globl	mmUVD_LMI_RBC_RB_64BIT_BAR_LOW
	.align 4
	.type	mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, @object
	.size	mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, 4
mmUVD_LMI_RBC_RB_64BIT_BAR_LOW:
	.zero	4
	.globl	mmUVD_MASTINT_EN
	.align 4
	.type	mmUVD_MASTINT_EN, @object
	.size	mmUVD_MASTINT_EN, 4
mmUVD_MASTINT_EN:
	.zero	4
	.globl	mmUVD_MPC_CNTL
	.align 4
	.type	mmUVD_MPC_CNTL, @object
	.size	mmUVD_MPC_CNTL, 4
mmUVD_MPC_CNTL:
	.zero	4
	.globl	mmUVD_MPC_SET_MUX
	.align 4
	.type	mmUVD_MPC_SET_MUX, @object
	.size	mmUVD_MPC_SET_MUX, 4
mmUVD_MPC_SET_MUX:
	.zero	4
	.globl	mmUVD_MPC_SET_MUXA0
	.align 4
	.type	mmUVD_MPC_SET_MUXA0, @object
	.size	mmUVD_MPC_SET_MUXA0, 4
mmUVD_MPC_SET_MUXA0:
	.zero	4
	.globl	mmUVD_MPC_SET_MUXB0
	.align 4
	.type	mmUVD_MPC_SET_MUXB0, @object
	.size	mmUVD_MPC_SET_MUXB0, 4
mmUVD_MPC_SET_MUXB0:
	.zero	4
	.globl	mmUVD_POWER_STATUS
	.align 4
	.type	mmUVD_POWER_STATUS, @object
	.size	mmUVD_POWER_STATUS, 4
mmUVD_POWER_STATUS:
	.zero	4
	.globl	mmUVD_RBC_RB_CNTL
	.align 4
	.type	mmUVD_RBC_RB_CNTL, @object
	.size	mmUVD_RBC_RB_CNTL, 4
mmUVD_RBC_RB_CNTL:
	.zero	4
	.globl	mmUVD_RBC_RB_RPTR
	.align 4
	.type	mmUVD_RBC_RB_RPTR, @object
	.size	mmUVD_RBC_RB_RPTR, 4
mmUVD_RBC_RB_RPTR:
	.zero	4
	.globl	mmUVD_RBC_RB_RPTR_ADDR
	.align 4
	.type	mmUVD_RBC_RB_RPTR_ADDR, @object
	.size	mmUVD_RBC_RB_RPTR_ADDR, 4
mmUVD_RBC_RB_RPTR_ADDR:
	.zero	4
	.globl	mmUVD_RBC_RB_WPTR
	.align 4
	.type	mmUVD_RBC_RB_WPTR, @object
	.size	mmUVD_RBC_RB_WPTR, 4
mmUVD_RBC_RB_WPTR:
	.zero	4
	.globl	mmUVD_RBC_RB_WPTR_CNTL
	.align 4
	.type	mmUVD_RBC_RB_WPTR_CNTL, @object
	.size	mmUVD_RBC_RB_WPTR_CNTL, 4
mmUVD_RBC_RB_WPTR_CNTL:
	.zero	4
	.globl	mmUVD_RBC_XX_IB_REG_CHECK
	.align 4
	.type	mmUVD_RBC_XX_IB_REG_CHECK, @object
	.size	mmUVD_RBC_XX_IB_REG_CHECK, 4
mmUVD_RBC_XX_IB_REG_CHECK:
	.zero	4
	.globl	mmUVD_REG_XX_MASK
	.align 4
	.type	mmUVD_REG_XX_MASK, @object
	.size	mmUVD_REG_XX_MASK, 4
mmUVD_REG_XX_MASK:
	.zero	4
	.globl	mmUVD_SCRATCH2
	.align 4
	.type	mmUVD_SCRATCH2, @object
	.size	mmUVD_SCRATCH2, 4
mmUVD_SCRATCH2:
	.zero	4
	.globl	mmUVD_SOFT_RESET
	.align 4
	.type	mmUVD_SOFT_RESET, @object
	.size	mmUVD_SOFT_RESET, 4
mmUVD_SOFT_RESET:
	.zero	4
	.globl	mmUVD_VCPU_CNTL
	.align 4
	.type	mmUVD_VCPU_CNTL, @object
	.size	mmUVD_VCPU_CNTL, 4
mmUVD_VCPU_CNTL:
	.zero	4
	.text
	.type	vcn_v2_0_start_dpg_mode, @function
vcn_v2_0_start_dpg_mode:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	push	rbx
	sub	rsp, 40
	.cfi_offset 3, -24
	mov	QWORD PTR -40[rbp], rdi
	mov	DWORD PTR -44[rbp], esi
	mov	rax, QWORD PTR -40[rbp]
	mov	rax, QWORD PTR 24[rax]
	mov	QWORD PTR -24[rbp], rax
	mov	rax, QWORD PTR -40[rbp]
	mov	rdi, rax
	call	vcn_v2_0_enable_static_power_gating@PLT
	mov	edx, DWORD PTR mmUVD_POWER_STATUS[rip]
	mov	eax, DWORD PTR UVD[rip]
	mov	esi, 0
	mov	edi, eax
	call	RREG32_SOC15@PLT
	mov	DWORD PTR -32[rbp], eax
	mov	eax, DWORD PTR UVD_POWER_STATUS__UVD_PG_MODE_MASK[rip]
	or	DWORD PTR -32[rbp], eax
	mov	eax, DWORD PTR UVD_POWER_STATUS__UVD_PG_EN_MASK[rip]
	or	DWORD PTR -32[rbp], eax
	mov	edx, DWORD PTR mmUVD_POWER_STATUS[rip]
	mov	eax, DWORD PTR UVD[rip]
	mov	ecx, DWORD PTR -32[rbp]
	mov	esi, 0
	mov	edi, eax
	call	WREG32_SOC15@PLT
	cmp	DWORD PTR -44[rbp], 0
	je	.L2
	mov	rax, QWORD PTR -40[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	rdx, rax
	mov	rax, QWORD PTR -40[rbp]
	mov	QWORD PTR [rax], rdx
.L2:
	mov	edx, DWORD PTR -44[rbp]
	mov	rax, QWORD PTR -40[rbp]
	mov	esi, 0
	mov	rdi, rax
	call	vcn_v2_0_clock_gating_dpg_mode@PLT
	mov	eax, DWORD PTR UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT[rip]
	mov	edx, 255
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	DWORD PTR -32[rbp], eax
	mov	eax, DWORD PTR UVD_VCPU_CNTL__CLK_EN_MASK[rip]
	or	DWORD PTR -32[rbp], eax
	mov	eax, DWORD PTR UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK[rip]
	or	DWORD PTR -32[rbp], eax
	mov	edx, DWORD PTR mmUVD_VCPU_CNTL[rip]
	mov	eax, DWORD PTR UVD[rip]
	mov	esi, 0
	mov	edi, eax
	call	SOC15_DPG_MODE_OFFSET_2_0@PLT
	mov	edi, eax
	mov	edx, DWORD PTR -44[rbp]
	mov	eax, DWORD PTR -32[rbp]
	mov	ecx, edx
	mov	edx, 0
	mov	esi, eax
	call	WREG32_SOC15_DPG_MODE_2_0@PLT
	mov	edx, DWORD PTR mmUVD_MASTINT_EN[rip]
	mov	eax, DWORD PTR UVD[rip]
	mov	esi, 0
	mov	edi, eax
	call	SOC15_DPG_MODE_OFFSET_2_0@PLT
	mov	edi, eax
	mov	eax, DWORD PTR -44[rbp]
	mov	ecx, eax
	mov	edx, 0
	mov	esi, 0
	call	WREG32_SOC15_DPG_MODE_2_0@PLT
	mov	edx, DWORD PTR UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK[rip]
	mov	eax, DWORD PTR UVD_LMI_CTRL__REQ_MODE_MASK[rip]
	or	edx, eax
	mov	eax, DWORD PTR UVD_LMI_CTRL__CRC_RESET_MASK[rip]
	or	edx, eax
	mov	eax, DWORD PTR UVD_LMI_CTRL__MASK_MC_URGENT_MASK[rip]
	or	edx, eax
	mov	eax, DWORD PTR UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK[rip]
	or	edx, eax
	mov	eax, DWORD PTR UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK[rip]
	or	edx, eax
	mov	eax, DWORD PTR UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT[rip]
	mov	esi, 8
	mov	ecx, eax
	sal	esi, cl
	mov	eax, esi
	or	eax, edx
	or	eax, 1048576
	mov	DWORD PTR -32[rbp], eax
	mov	edx, DWORD PTR mmUVD_LMI_CTRL[rip]
	mov	eax, DWORD PTR UVD[rip]
	mov	esi, 0
	mov	edi, eax
	call	SOC15_DPG_MODE_OFFSET_2_0@PLT
	mov	edi, eax
	mov	edx, DWORD PTR -44[rbp]
	mov	eax, DWORD PTR -32[rbp]
	mov	ecx, edx
	mov	edx, 0
	mov	esi, eax
	call	WREG32_SOC15_DPG_MODE_2_0@PLT
	mov	eax, DWORD PTR UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT[rip]
	mov	edx, 2
	mov	ebx, edx
	mov	ecx, eax
	sal	ebx, cl
	mov	edx, DWORD PTR mmUVD_MPC_CNTL[rip]
	mov	eax, DWORD PTR UVD[rip]
	mov	esi, 0
	mov	edi, eax
	call	SOC15_DPG_MODE_OFFSET_2_0@PLT
	mov	edi, eax
	mov	eax, DWORD PTR -44[rbp]
	mov	ecx, eax
	mov	edx, 0
	mov	esi, ebx
	call	WREG32_SOC15_DPG_MODE_2_0@PLT
	mov	eax, DWORD PTR UVD_MPC_SET_MUXA0__VARA_1__SHIFT[rip]
	mov	edx, 1
	mov	ecx, eax
	sal	edx, cl
	mov	eax, DWORD PTR UVD_MPC_SET_MUXA0__VARA_2__SHIFT[rip]
	mov	esi, 2
	mov	ecx, eax
	sal	esi, cl
	mov	eax, esi
	or	edx, eax
	mov	eax, DWORD PTR UVD_MPC_SET_MUXA0__VARA_3__SHIFT[rip]
	mov	esi, 3
	mov	ecx, eax
	sal	esi, cl
	mov	eax, esi
	or	edx, eax
	mov	eax, DWORD PTR UVD_MPC_SET_MUXA0__VARA_4__SHIFT[rip]
	mov	esi, 4
	mov	ecx, eax
	sal	esi, cl
	mov	eax, esi
	mov	ebx, edx
	or	ebx, eax
	mov	edx, DWORD PTR mmUVD_MPC_SET_MUXA0[rip]
	mov	eax, DWORD PTR UVD[rip]
	mov	esi, 0
	mov	edi, eax
	call	SOC15_DPG_MODE_OFFSET_2_0@PLT
	mov	edi, eax
	mov	eax, DWORD PTR -44[rbp]
	mov	ecx, eax
	mov	edx, 0
	mov	esi, ebx
	call	WREG32_SOC15_DPG_MODE_2_0@PLT
	mov	eax, DWORD PTR UVD_MPC_SET_MUXB0__VARB_1__SHIFT[rip]
	mov	edx, 1
	mov	ecx, eax
	sal	edx, cl
	mov	eax, DWORD PTR UVD_MPC_SET_MUXB0__VARB_2__SHIFT[rip]
	mov	esi, 2
	mov	ecx, eax
	sal	esi, cl
	mov	eax, esi
	or	edx, eax
	mov	eax, DWORD PTR UVD_MPC_SET_MUXB0__VARB_3__SHIFT[rip]
	mov	esi, 3
	mov	ecx, eax
	sal	esi, cl
	mov	eax, esi
	or	edx, eax
	mov	eax, DWORD PTR UVD_MPC_SET_MUXB0__VARB_4__SHIFT[rip]
	mov	esi, 4
	mov	ecx, eax
	sal	esi, cl
	mov	eax, esi
	mov	ebx, edx
	or	ebx, eax
	mov	edx, DWORD PTR mmUVD_MPC_SET_MUXB0[rip]
	mov	eax, DWORD PTR UVD[rip]
	mov	esi, 0
	mov	edi, eax
	call	SOC15_DPG_MODE_OFFSET_2_0@PLT
	mov	edi, eax
	mov	eax, DWORD PTR -44[rbp]
	mov	ecx, eax
	mov	edx, 0
	mov	esi, ebx
	call	WREG32_SOC15_DPG_MODE_2_0@PLT
	mov	eax, DWORD PTR UVD_MPC_SET_MUX__SET_1__SHIFT[rip]
	mov	edx, 1
	mov	ecx, eax
	sal	edx, cl
	mov	eax, DWORD PTR UVD_MPC_SET_MUX__SET_2__SHIFT[rip]
	mov	esi, 2
	mov	ecx, eax
	sal	esi, cl
	mov	eax, esi
	mov	ebx, edx
	or	ebx, eax
	mov	edx, DWORD PTR mmUVD_MPC_SET_MUX[rip]
	mov	eax, DWORD PTR UVD[rip]
	mov	esi, 0
	mov	edi, eax
	call	SOC15_DPG_MODE_OFFSET_2_0@PLT
	mov	edi, eax
	mov	eax, DWORD PTR -44[rbp]
	mov	ecx, eax
	mov	edx, 0
	mov	esi, ebx
	call	WREG32_SOC15_DPG_MODE_2_0@PLT
	mov	edx, DWORD PTR -44[rbp]
	mov	rax, QWORD PTR -40[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	vcn_v2_0_mc_resume_dpg_mode@PLT
	mov	edx, DWORD PTR mmUVD_REG_XX_MASK[rip]
	mov	eax, DWORD PTR UVD[rip]
	mov	esi, 0
	mov	edi, eax
	call	SOC15_DPG_MODE_OFFSET_2_0@PLT
	mov	edi, eax
	mov	eax, DWORD PTR -44[rbp]
	mov	ecx, eax
	mov	edx, 0
	mov	esi, 16
	call	WREG32_SOC15_DPG_MODE_2_0@PLT
	mov	edx, DWORD PTR mmUVD_RBC_XX_IB_REG_CHECK[rip]
	mov	eax, DWORD PTR UVD[rip]
	mov	esi, 0
	mov	edi, eax
	call	SOC15_DPG_MODE_OFFSET_2_0@PLT
	mov	edi, eax
	mov	eax, DWORD PTR -44[rbp]
	mov	ecx, eax
	mov	edx, 0
	mov	esi, 3
	call	WREG32_SOC15_DPG_MODE_2_0@PLT
	mov	edx, DWORD PTR mmUVD_SOFT_RESET[rip]
	mov	eax, DWORD PTR UVD[rip]
	mov	esi, 0
	mov	edi, eax
	call	SOC15_DPG_MODE_OFFSET_2_0@PLT
	mov	edi, eax
	mov	eax, DWORD PTR -44[rbp]
	mov	ecx, eax
	mov	edx, 0
	mov	esi, 0
	call	WREG32_SOC15_DPG_MODE_2_0@PLT
	mov	eax, DWORD PTR UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT[rip]
	mov	edx, 31
	mov	ebx, edx
	mov	ecx, eax
	sal	ebx, cl
	mov	edx, DWORD PTR mmUVD_LMI_CTRL2[rip]
	mov	eax, DWORD PTR UVD[rip]
	mov	esi, 0
	mov	edi, eax
	call	SOC15_DPG_MODE_OFFSET_2_0@PLT
	mov	edi, eax
	mov	eax, DWORD PTR -44[rbp]
	mov	ecx, eax
	mov	edx, 0
	mov	esi, ebx
	call	WREG32_SOC15_DPG_MODE_2_0@PLT
	mov	ebx, DWORD PTR UVD_MASTINT_EN__VCPU_EN_MASK[rip]
	mov	edx, DWORD PTR mmUVD_MASTINT_EN[rip]
	mov	eax, DWORD PTR UVD[rip]
	mov	esi, 0
	mov	edi, eax
	call	SOC15_DPG_MODE_OFFSET_2_0@PLT
	mov	edi, eax
	mov	eax, DWORD PTR -44[rbp]
	mov	ecx, eax
	mov	edx, 0
	mov	esi, ebx
	call	WREG32_SOC15_DPG_MODE_2_0@PLT
	cmp	DWORD PTR -44[rbp], 0
	je	.L3
	mov	rax, QWORD PTR -40[rbp]
	mov	rax, QWORD PTR [rax]
	mov	edx, eax
	mov	rax, QWORD PTR -40[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	ecx, eax
	mov	eax, edx
	sub	eax, ecx
	mov	ecx, eax
	mov	rax, QWORD PTR -40[rbp]
	mov	edx, DWORD PTR 16[rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	esi, 0
	mov	rdi, rax
	call	psp_update_vcn_sram@PLT
.L3:
	mov	rax, QWORD PTR -24[rbp]
	mov	eax, DWORD PTR 16[rax]
	mov	edi, eax
	call	order_base_2@PLT
	mov	DWORD PTR -28[rbp], eax
	mov	edx, DWORD PTR RB_BUFSZ[rip]
	mov	eax, DWORD PTR UVD_RBC_RB_CNTL[rip]
	mov	ecx, DWORD PTR -28[rbp]
	mov	esi, eax
	mov	edi, 0
	call	REG_SET_FIELD@PLT
	mov	DWORD PTR -32[rbp], eax
	mov	edx, DWORD PTR RB_BLKSZ[rip]
	mov	esi, DWORD PTR UVD_RBC_RB_CNTL[rip]
	mov	eax, DWORD PTR -32[rbp]
	mov	ecx, 1
	mov	edi, eax
	call	REG_SET_FIELD@PLT
	mov	DWORD PTR -32[rbp], eax
	mov	edx, DWORD PTR RB_NO_FETCH[rip]
	mov	esi, DWORD PTR UVD_RBC_RB_CNTL[rip]
	mov	eax, DWORD PTR -32[rbp]
	mov	ecx, 1
	mov	edi, eax
	call	REG_SET_FIELD@PLT
	mov	DWORD PTR -32[rbp], eax
	mov	edx, DWORD PTR RB_NO_UPDATE[rip]
	mov	esi, DWORD PTR UVD_RBC_RB_CNTL[rip]
	mov	eax, DWORD PTR -32[rbp]
	mov	ecx, 1
	mov	edi, eax
	call	REG_SET_FIELD@PLT
	mov	DWORD PTR -32[rbp], eax
	mov	edx, DWORD PTR RB_RPTR_WR_EN[rip]
	mov	esi, DWORD PTR UVD_RBC_RB_CNTL[rip]
	mov	eax, DWORD PTR -32[rbp]
	mov	ecx, 1
	mov	edi, eax
	call	REG_SET_FIELD@PLT
	mov	DWORD PTR -32[rbp], eax
	mov	edx, DWORD PTR mmUVD_RBC_RB_CNTL[rip]
	mov	eax, DWORD PTR UVD[rip]
	mov	ecx, DWORD PTR -32[rbp]
	mov	esi, 0
	mov	edi, eax
	call	WREG32_SOC15@PLT
	mov	edx, DWORD PTR mmUVD_RBC_RB_WPTR_CNTL[rip]
	mov	eax, DWORD PTR UVD[rip]
	mov	ecx, 0
	mov	esi, 0
	mov	edi, eax
	call	WREG32_SOC15@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	rdi, rax
	call	upper_32_bits@PLT
	sar	eax, 2
	mov	ecx, eax
	mov	edx, DWORD PTR mmUVD_RBC_RB_RPTR_ADDR[rip]
	mov	eax, DWORD PTR UVD[rip]
	mov	esi, 0
	mov	edi, eax
	call	WREG32_SOC15@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	rdi, rax
	call	lower_32_bits@PLT
	mov	ecx, eax
	mov	edx, DWORD PTR mmUVD_LMI_RBC_RB_64BIT_BAR_LOW[rip]
	mov	eax, DWORD PTR UVD[rip]
	mov	esi, 0
	mov	edi, eax
	call	WREG32_SOC15@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	rdi, rax
	call	upper_32_bits@PLT
	mov	ecx, eax
	mov	edx, DWORD PTR mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH[rip]
	mov	eax, DWORD PTR UVD[rip]
	mov	esi, 0
	mov	edi, eax
	call	WREG32_SOC15@PLT
	mov	edx, DWORD PTR mmUVD_RBC_RB_RPTR[rip]
	mov	eax, DWORD PTR UVD[rip]
	mov	ecx, 0
	mov	esi, 0
	mov	edi, eax
	call	WREG32_SOC15@PLT
	mov	edx, DWORD PTR mmUVD_SCRATCH2[rip]
	mov	eax, DWORD PTR UVD[rip]
	mov	ecx, 0
	mov	esi, 0
	mov	edi, eax
	call	WREG32_SOC15@PLT
	mov	edx, DWORD PTR mmUVD_RBC_RB_RPTR[rip]
	mov	eax, DWORD PTR UVD[rip]
	mov	esi, 0
	mov	edi, eax
	call	RREG32_SOC15@PLT
	mov	rdx, QWORD PTR -24[rbp]
	mov	QWORD PTR [rdx], rax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR [rax]
	mov	rdi, rax
	call	lower_32_bits@PLT
	mov	ecx, eax
	mov	edx, DWORD PTR mmUVD_RBC_RB_WPTR[rip]
	mov	eax, DWORD PTR UVD[rip]
	mov	esi, 0
	mov	edi, eax
	call	WREG32_SOC15@PLT
	mov	eax, 0
	mov	rbx, QWORD PTR -8[rbp]
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	vcn_v2_0_start_dpg_mode, .-vcn_v2_0_start_dpg_mode
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"517753.c"
	.text
	.comm	RB_BLKSZ,4,4
	.comm	RB_BUFSZ,4,4
	.comm	RB_NO_FETCH,4,4
	.comm	RB_NO_UPDATE,4,4
	.comm	RB_RPTR_WR_EN,4,4
	.comm	UVD,4,4
	.comm	UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT,4,4
	.comm	UVD_LMI_CTRL__CRC_RESET_MASK,4,4
	.comm	UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK,4,4
	.comm	UVD_LMI_CTRL__MASK_MC_URGENT_MASK,4,4
	.comm	UVD_LMI_CTRL__REQ_MODE_MASK,4,4
	.comm	UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK,4,4
	.comm	UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK,4,4
	.comm	UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT,4,4
	.comm	UVD_MASTINT_EN__VCPU_EN_MASK,4,4
	.comm	UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT,4,4
	.comm	UVD_MPC_SET_MUXA0__VARA_1__SHIFT,4,4
	.comm	UVD_MPC_SET_MUXA0__VARA_2__SHIFT,4,4
	.comm	UVD_MPC_SET_MUXA0__VARA_3__SHIFT,4,4
	.comm	UVD_MPC_SET_MUXA0__VARA_4__SHIFT,4,4
	.comm	UVD_MPC_SET_MUXB0__VARB_1__SHIFT,4,4
	.comm	UVD_MPC_SET_MUXB0__VARB_2__SHIFT,4,4
	.comm	UVD_MPC_SET_MUXB0__VARB_3__SHIFT,4,4
	.comm	UVD_MPC_SET_MUXB0__VARB_4__SHIFT,4,4
	.comm	UVD_MPC_SET_MUX__SET_0__SHIFT,4,4
	.comm	UVD_MPC_SET_MUX__SET_1__SHIFT,4,4
	.comm	UVD_MPC_SET_MUX__SET_2__SHIFT,4,4
	.comm	UVD_POWER_STATUS__UVD_PG_EN_MASK,4,4
	.comm	UVD_POWER_STATUS__UVD_PG_MODE_MASK,4,4
	.comm	UVD_RBC_RB_CNTL,4,4
	.comm	UVD_VCPU_CNTL__CLK_EN_MASK,4,4
	.comm	UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK,4,4
	.comm	UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT,4,4
	.comm	mmUVD_LMI_CTRL,4,4
	.comm	mmUVD_LMI_CTRL2,4,4
	.comm	mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,4,4
	.comm	mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,4,4
	.comm	mmUVD_MASTINT_EN,4,4
	.comm	mmUVD_MPC_CNTL,4,4
	.comm	mmUVD_MPC_SET_MUX,4,4
	.comm	mmUVD_MPC_SET_MUXA0,4,4
	.comm	mmUVD_MPC_SET_MUXB0,4,4
	.comm	mmUVD_POWER_STATUS,4,4
	.comm	mmUVD_RBC_RB_CNTL,4,4
	.comm	mmUVD_RBC_RB_RPTR,4,4
	.comm	mmUVD_RBC_RB_RPTR_ADDR,4,4
	.comm	mmUVD_RBC_RB_WPTR,4,4
	.comm	mmUVD_RBC_RB_WPTR_CNTL,4,4
	.comm	mmUVD_RBC_XX_IB_REG_CHECK,4,4
	.comm	mmUVD_REG_XX_MASK,4,4
	.comm	mmUVD_SCRATCH2,4,4
	.comm	mmUVD_SOFT_RESET,4,4
	.comm	mmUVD_VCPU_CNTL,4,4
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	vcn_v2_0_start_dpg_mode, %function
vcn_v2_0_start_dpg_mode:
	@ args = 0, pretend = 0, frame = 24
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, fp, lr}
	add	fp, sp, #12
	sub	sp, sp, #24
	str	r0, [fp, #-32]
	str	r1, [fp, #-36]
	ldr	r3, [fp, #-32]
	ldr	r3, [r3, #12]
	str	r3, [fp, #-24]
	ldr	r0, [fp, #-32]
	bl	vcn_v2_0_enable_static_power_gating
	ldr	r3, .L5
	ldr	r3, [r3]
	ldr	r2, .L5+4
	ldr	r2, [r2]
	mov	r1, #0
	mov	r0, r3
	bl	RREG32_SOC15
	mov	r3, r0
	str	r3, [fp, #-20]
	ldr	r3, .L5+8
	ldr	r3, [r3]
	ldr	r2, [fp, #-20]
	orr	r3, r2, r3
	str	r3, [fp, #-20]
	ldr	r3, .L5+12
	ldr	r3, [r3]
	ldr	r2, [fp, #-20]
	orr	r3, r2, r3
	str	r3, [fp, #-20]
	ldr	r3, .L5
	ldr	r0, [r3]
	ldr	r3, .L5+4
	ldr	r2, [r3]
	ldr	r3, [fp, #-20]
	mov	r1, #0
	bl	WREG32_SOC15
	ldr	r3, [fp, #-36]
	cmp	r3, #0
	beq	.L2
	ldr	r3, [fp, #-32]
	ldr	r3, [r3, #4]
	mov	r2, r3
	ldr	r3, [fp, #-32]
	str	r2, [r3]
.L2:
	ldr	r2, [fp, #-36]
	mov	r1, #0
	ldr	r0, [fp, #-32]
	bl	vcn_v2_0_clock_gating_dpg_mode
	ldr	r3, .L5+16
	ldr	r3, [r3]
	mov	r2, #255
	lsl	r3, r2, r3
	str	r3, [fp, #-20]
	ldr	r3, .L5+20
	ldr	r3, [r3]
	ldr	r2, [fp, #-20]
	orr	r3, r2, r3
	str	r3, [fp, #-20]
	ldr	r3, .L5+24
	ldr	r3, [r3]
	ldr	r2, [fp, #-20]
	orr	r3, r2, r3
	str	r3, [fp, #-20]
	ldr	r3, .L5
	ldr	r3, [r3]
	ldr	r2, .L5+28
	ldr	r2, [r2]
	mov	r1, #0
	mov	r0, r3
	bl	SOC15_DPG_MODE_OFFSET_2_0
	ldr	r3, [fp, #-36]
	mov	r2, #0
	ldr	r1, [fp, #-20]
	bl	WREG32_SOC15_DPG_MODE_2_0
	ldr	r3, .L5
	ldr	r3, [r3]
	ldr	r2, .L5+32
	ldr	r2, [r2]
	mov	r1, #0
	mov	r0, r3
	bl	SOC15_DPG_MODE_OFFSET_2_0
	ldr	r3, [fp, #-36]
	mov	r2, #0
	mov	r1, #0
	bl	WREG32_SOC15_DPG_MODE_2_0
	ldr	r3, .L5+36
	ldr	r2, [r3]
	ldr	r3, .L5+40
	ldr	r3, [r3]
	orr	r2, r2, r3
	ldr	r3, .L5+44
	ldr	r3, [r3]
	orr	r2, r2, r3
	ldr	r3, .L5+48
	ldr	r3, [r3]
	orr	r2, r2, r3
	ldr	r3, .L5+52
	ldr	r3, [r3]
	orr	r2, r2, r3
	ldr	r3, .L5+56
	ldr	r3, [r3]
	orr	r2, r2, r3
	ldr	r3, .L5+60
	ldr	r3, [r3]
	mov	r1, #8
	lsl	r3, r1, r3
	orr	r3, r2, r3
	orr	r3, r3, #1048576
	str	r3, [fp, #-20]
	ldr	r3, .L5
	ldr	r3, [r3]
	ldr	r2, .L5+64
	ldr	r2, [r2]
	mov	r1, #0
	mov	r0, r3
	bl	SOC15_DPG_MODE_OFFSET_2_0
	ldr	r3, [fp, #-36]
	mov	r2, #0
	ldr	r1, [fp, #-20]
	bl	WREG32_SOC15_DPG_MODE_2_0
	ldr	r3, .L5
	ldr	r3, [r3]
	ldr	r2, .L5+68
	ldr	r2, [r2]
	mov	r1, #0
	mov	r0, r3
	bl	SOC15_DPG_MODE_OFFSET_2_0
	ldr	r3, .L5+72
	ldr	r3, [r3]
	mov	r2, #2
	lsl	r1, r2, r3
	ldr	r3, [fp, #-36]
	mov	r2, #0
	bl	WREG32_SOC15_DPG_MODE_2_0
	ldr	r3, .L5
	ldr	r3, [r3]
	ldr	r2, .L5+76
	ldr	r2, [r2]
	mov	r1, #0
	mov	r0, r3
	bl	SOC15_DPG_MODE_OFFSET_2_0
	ldr	r3, .L5+80
	ldr	r3, [r3]
	mov	r2, #1
	lsl	r2, r2, r3
	ldr	r3, .L5+84
	ldr	r3, [r3]
	mov	r1, #2
	lsl	r3, r1, r3
	orr	r2, r2, r3
	ldr	r3, .L5+88
	ldr	r3, [r3]
	mov	r1, #3
	lsl	r3, r1, r3
	orr	r2, r2, r3
	ldr	r3, .L5+92
	ldr	r3, [r3]
	mov	r1, #4
	lsl	r3, r1, r3
	orr	r1, r2, r3
	ldr	r3, [fp, #-36]
	mov	r2, #0
	bl	WREG32_SOC15_DPG_MODE_2_0
	ldr	r3, .L5
	ldr	r3, [r3]
	ldr	r2, .L5+96
	ldr	r2, [r2]
	mov	r1, #0
	mov	r0, r3
	bl	SOC15_DPG_MODE_OFFSET_2_0
	ldr	r3, .L5+100
	ldr	r3, [r3]
	mov	r2, #1
	lsl	r2, r2, r3
	ldr	r3, .L5+104
	ldr	r3, [r3]
	mov	r1, #2
	lsl	r3, r1, r3
	orr	r2, r2, r3
	ldr	r3, .L5+108
	ldr	r3, [r3]
	mov	r1, #3
	lsl	r3, r1, r3
	orr	r2, r2, r3
	ldr	r3, .L5+112
	ldr	r3, [r3]
	mov	r1, #4
	lsl	r3, r1, r3
	orr	r1, r2, r3
	ldr	r3, [fp, #-36]
	mov	r2, #0
	bl	WREG32_SOC15_DPG_MODE_2_0
	ldr	r3, .L5
	ldr	r3, [r3]
	ldr	r2, .L5+116
	ldr	r2, [r2]
	mov	r1, #0
	mov	r0, r3
	bl	SOC15_DPG_MODE_OFFSET_2_0
	ldr	r3, .L5+120
	ldr	r3, [r3]
	mov	r2, #1
	lsl	r2, r2, r3
	ldr	r3, .L5+124
	ldr	r3, [r3]
	mov	r1, #2
	lsl	r3, r1, r3
	orr	r1, r2, r3
	ldr	r3, [fp, #-36]
	mov	r2, #0
	bl	WREG32_SOC15_DPG_MODE_2_0
	ldr	r1, [fp, #-36]
	ldr	r0, [fp, #-32]
	bl	vcn_v2_0_mc_resume_dpg_mode
	ldr	r3, .L5
	ldr	r3, [r3]
	ldr	r2, .L5+128
	ldr	r2, [r2]
	mov	r1, #0
	mov	r0, r3
	bl	SOC15_DPG_MODE_OFFSET_2_0
	ldr	r3, [fp, #-36]
	mov	r2, #0
	mov	r1, #16
	bl	WREG32_SOC15_DPG_MODE_2_0
	ldr	r3, .L5
	ldr	r3, [r3]
	ldr	r2, .L5+132
	ldr	r2, [r2]
	mov	r1, #0
	mov	r0, r3
	bl	SOC15_DPG_MODE_OFFSET_2_0
	ldr	r3, [fp, #-36]
	mov	r2, #0
	mov	r1, #3
	bl	WREG32_SOC15_DPG_MODE_2_0
	ldr	r3, .L5
	ldr	r3, [r3]
	ldr	r2, .L5+136
	ldr	r2, [r2]
	mov	r1, #0
	mov	r0, r3
	bl	SOC15_DPG_MODE_OFFSET_2_0
	ldr	r3, [fp, #-36]
	mov	r2, #0
	mov	r1, #0
	bl	WREG32_SOC15_DPG_MODE_2_0
	ldr	r3, .L5
	ldr	r3, [r3]
	ldr	r2, .L5+140
	ldr	r2, [r2]
	mov	r1, #0
	mov	r0, r3
	bl	SOC15_DPG_MODE_OFFSET_2_0
	ldr	r3, .L5+144
	ldr	r3, [r3]
	mov	r2, #31
	lsl	r1, r2, r3
	ldr	r3, [fp, #-36]
	mov	r2, #0
	bl	WREG32_SOC15_DPG_MODE_2_0
	ldr	r3, .L5
	ldr	r3, [r3]
	ldr	r2, .L5+32
	ldr	r2, [r2]
	mov	r1, #0
	mov	r0, r3
	bl	SOC15_DPG_MODE_OFFSET_2_0
	ldr	r3, .L5+148
	ldr	r1, [r3]
	ldr	r3, [fp, #-36]
	mov	r2, #0
	bl	WREG32_SOC15_DPG_MODE_2_0
	ldr	r3, [fp, #-36]
	cmp	r3, #0
	beq	.L3
	ldr	r3, [fp, #-32]
	ldr	r2, [r3, #8]
	ldr	r3, [fp, #-32]
	ldr	r3, [r3]
	mov	r1, r3
	ldr	r3, [fp, #-32]
	ldr	r3, [r3, #4]
	sub	r3, r1, r3
	mov	r1, #0
	ldr	r0, [fp, #-32]
	bl	psp_update_vcn_sram
.L3:
	ldr	r3, [fp, #-24]
	ldr	r3, [r3, #8]
	mov	r0, r3
	bl	order_base_2
	str	r0, [fp, #-16]
	ldr	r3, .L5+152
	ldr	r1, [r3]
	ldr	r3, .L5+156
	ldr	r2, [r3]
	ldr	r3, [fp, #-16]
	mov	r0, #0
	bl	REG_SET_FIELD
	str	r0, [fp, #-20]
	ldr	r3, .L5+152
	ldr	r1, [r3]
	ldr	r3, .L5+160
	ldr	r2, [r3]
	mov	r3, #1
	ldr	r0, [fp, #-20]
	bl	REG_SET_FIELD
	str	r0, [fp, #-20]
	ldr	r3, .L5+152
	ldr	r1, [r3]
	ldr	r3, .L5+164
	ldr	r2, [r3]
	mov	r3, #1
	ldr	r0, [fp, #-20]
	bl	REG_SET_FIELD
	str	r0, [fp, #-20]
	ldr	r3, .L5+152
	ldr	r1, [r3]
	ldr	r3, .L5+168
	ldr	r2, [r3]
	mov	r3, #1
	ldr	r0, [fp, #-20]
	bl	REG_SET_FIELD
	str	r0, [fp, #-20]
	ldr	r3, .L5+152
	ldr	r1, [r3]
	ldr	r3, .L5+172
	ldr	r2, [r3]
	mov	r3, #1
	ldr	r0, [fp, #-20]
	bl	REG_SET_FIELD
	str	r0, [fp, #-20]
	ldr	r3, .L5
	ldr	r0, [r3]
	ldr	r3, .L5+176
	ldr	r2, [r3]
	ldr	r3, [fp, #-20]
	mov	r1, #0
	bl	WREG32_SOC15
	ldr	r3, .L5
	ldr	r0, [r3]
	ldr	r3, .L5+180
	ldr	r2, [r3]
	mov	r3, #0
	mov	r1, #0
	bl	WREG32_SOC15
	ldr	r3, .L5
	ldr	r4, [r3]
	ldr	r3, .L5+184
	ldr	r5, [r3]
	ldr	r3, [fp, #-24]
	ldr	r3, [r3, #4]
	mov	r0, r3
	bl	upper_32_bits
	mov	r3, r0
	asr	r3, r3, #2
	mov	r2, r5
	mov	r1, #0
	mov	r0, r4
	bl	WREG32_SOC15
	ldr	r3, .L5
	ldr	r4, [r3]
	ldr	r3, .L5+188
	ldr	r5, [r3]
	ldr	r3, [fp, #-24]
	ldr	r3, [r3, #4]
	mov	r0, r3
	bl	lower_32_bits
	mov	r3, r0
	mov	r2, r5
	mov	r1, #0
	mov	r0, r4
	bl	WREG32_SOC15
	ldr	r3, .L5
	ldr	r4, [r3]
	ldr	r3, .L5+192
	ldr	r5, [r3]
	ldr	r3, [fp, #-24]
	ldr	r3, [r3, #4]
	mov	r0, r3
	bl	upper_32_bits
	mov	r3, r0
	mov	r2, r5
	mov	r1, #0
	mov	r0, r4
	bl	WREG32_SOC15
	ldr	r3, .L5
	ldr	r0, [r3]
	ldr	r3, .L5+196
	ldr	r2, [r3]
	mov	r3, #0
	mov	r1, #0
	bl	WREG32_SOC15
	ldr	r3, .L5
	ldr	r0, [r3]
	ldr	r3, .L5+200
	ldr	r2, [r3]
	mov	r3, #0
	mov	r1, #0
	bl	WREG32_SOC15
	ldr	r3, .L5
	ldr	r3, [r3]
	ldr	r2, .L5+196
	ldr	r2, [r2]
	mov	r1, #0
	mov	r0, r3
	bl	RREG32_SOC15
	mov	r2, r0
	ldr	r3, [fp, #-24]
	str	r2, [r3]
	ldr	r3, .L5
	ldr	r4, [r3]
	ldr	r3, .L5+204
	ldr	r5, [r3]
	ldr	r3, [fp, #-24]
	ldr	r3, [r3]
	mov	r0, r3
	bl	lower_32_bits
	mov	r3, r0
	mov	r2, r5
	mov	r1, #0
	mov	r0, r4
	bl	WREG32_SOC15
	mov	r3, #0
	mov	r0, r3
	sub	sp, fp, #12
	@ sp needed
	pop	{r4, r5, fp, pc}
.L6:
	.align	2
.L5:
	.word	UVD
	.word	mmUVD_POWER_STATUS
	.word	UVD_POWER_STATUS__UVD_PG_MODE_MASK
	.word	UVD_POWER_STATUS__UVD_PG_EN_MASK
	.word	UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT
	.word	UVD_VCPU_CNTL__CLK_EN_MASK
	.word	UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK
	.word	mmUVD_VCPU_CNTL
	.word	mmUVD_MASTINT_EN
	.word	UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK
	.word	UVD_LMI_CTRL__REQ_MODE_MASK
	.word	UVD_LMI_CTRL__CRC_RESET_MASK
	.word	UVD_LMI_CTRL__MASK_MC_URGENT_MASK
	.word	UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK
	.word	UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK
	.word	UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT
	.word	mmUVD_LMI_CTRL
	.word	mmUVD_MPC_CNTL
	.word	UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT
	.word	mmUVD_MPC_SET_MUXA0
	.word	UVD_MPC_SET_MUXA0__VARA_1__SHIFT
	.word	UVD_MPC_SET_MUXA0__VARA_2__SHIFT
	.word	UVD_MPC_SET_MUXA0__VARA_3__SHIFT
	.word	UVD_MPC_SET_MUXA0__VARA_4__SHIFT
	.word	mmUVD_MPC_SET_MUXB0
	.word	UVD_MPC_SET_MUXB0__VARB_1__SHIFT
	.word	UVD_MPC_SET_MUXB0__VARB_2__SHIFT
	.word	UVD_MPC_SET_MUXB0__VARB_3__SHIFT
	.word	UVD_MPC_SET_MUXB0__VARB_4__SHIFT
	.word	mmUVD_MPC_SET_MUX
	.word	UVD_MPC_SET_MUX__SET_1__SHIFT
	.word	UVD_MPC_SET_MUX__SET_2__SHIFT
	.word	mmUVD_REG_XX_MASK
	.word	mmUVD_RBC_XX_IB_REG_CHECK
	.word	mmUVD_SOFT_RESET
	.word	mmUVD_LMI_CTRL2
	.word	UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT
	.word	UVD_MASTINT_EN__VCPU_EN_MASK
	.word	UVD_RBC_RB_CNTL
	.word	RB_BUFSZ
	.word	RB_BLKSZ
	.word	RB_NO_FETCH
	.word	RB_NO_UPDATE
	.word	RB_RPTR_WR_EN
	.word	mmUVD_RBC_RB_CNTL
	.word	mmUVD_RBC_RB_WPTR_CNTL
	.word	mmUVD_RBC_RB_RPTR_ADDR
	.word	mmUVD_LMI_RBC_RB_64BIT_BAR_LOW
	.word	mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH
	.word	mmUVD_RBC_RB_RPTR
	.word	mmUVD_SCRATCH2
	.word	mmUVD_RBC_RB_WPTR
	.size	vcn_v2_0_start_dpg_mode, .-vcn_v2_0_start_dpg_mode
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
