	.file	"552212.c"
	.intel_syntax noprefix
	.text
	.globl	__VERIFIER_nondet_bool
	.type	__VERIFIER_nondet_bool, @function
__VERIFIER_nondet_bool:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	call	__VERIFIER_nondet_int@PLT
	test	eax, eax
	setne	al
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.globl	_diverge_delta
	.bss
	.align 4
	.type	_diverge_delta, @object
	.size	_diverge_delta, 4
_diverge_delta:
	.zero	4
	.globl	_x__diverge_delta
	.align 4
	.type	_x__diverge_delta, @object
	.size	_x__diverge_delta, 4
_x__diverge_delta:
	.zero	4
	.globl	p1_l1
	.type	p1_l1, @object
	.size	p1_l1, 1
p1_l1:
	.zero	1
	.globl	_x_p1_l1
	.type	_x_p1_l1, @object
	.size	_x_p1_l1, 1
_x_p1_l1:
	.zero	1
	.globl	p0_l1
	.type	p0_l1, @object
	.size	p0_l1, 1
p0_l1:
	.zero	1
	.globl	_x_p0_l1
	.type	_x_p0_l1, @object
	.size	_x_p0_l1, 1
_x_p0_l1:
	.zero	1
	.globl	p0_l0
	.type	p0_l0, @object
	.size	p0_l0, 1
p0_l0:
	.zero	1
	.globl	_x_p0_l0
	.type	_x_p0_l0, @object
	.size	_x_p0_l0, 1
_x_p0_l0:
	.zero	1
	.globl	p1_l0
	.type	p1_l0, @object
	.size	p1_l0, 1
p1_l0:
	.zero	1
	.globl	_x_p1_l0
	.type	_x_p1_l0, @object
	.size	_x_p1_l0, 1
_x_p1_l0:
	.zero	1
	.globl	p0_x
	.align 4
	.type	p0_x, @object
	.size	p0_x, 4
p0_x:
	.zero	4
	.globl	_x_p0_x
	.align 4
	.type	_x_p0_x, @object
	.size	_x_p0_x, 4
_x_p0_x:
	.zero	4
	.globl	turn
	.align 4
	.type	turn, @object
	.size	turn, 4
turn:
	.zero	4
	.globl	_x_turn
	.align 4
	.type	_x_turn, @object
	.size	_x_turn, 4
_x_turn:
	.zero	4
	.globl	id
	.align 4
	.type	id, @object
	.size	id, 4
id:
	.zero	4
	.globl	_x_id
	.align 4
	.type	_x_id, @object
	.size	_x_id, 4
_x_id:
	.zero	4
	.globl	p1_x
	.align 4
	.type	p1_x, @object
	.size	p1_x, 4
p1_x:
	.zero	4
	.globl	_x_p1_x
	.align 4
	.type	_x_p1_x, @object
	.size	_x_p1_x, 4
_x_p1_x:
	.zero	4
	.globl	delta
	.align 4
	.type	delta, @object
	.size	delta, 4
delta:
	.zero	4
	.globl	_x_delta
	.align 4
	.type	_x_delta, @object
	.size	_x_delta, 4
_x_delta:
	.zero	4
	.text
	.globl	main
	.type	main, @function
main:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _diverge_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p1_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p0_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p0_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p1_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p0_x[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR turn[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR id[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p1_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR delta[rip], eax
	mov	eax, DWORD PTR id[rip]
	test	eax, eax
	jne	.L4
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR p1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	jne	.L6
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L7
.L6:
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L7
.L8:
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L9
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L7
.L9:
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L4
.L7:
	movss	xmm1, DWORD PTR p1_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L10
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L10
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L4
.L10:
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR p0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	jne	.L12
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L13
.L12:
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L14
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L13
.L14:
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L15
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L13
.L15:
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L4
.L13:
	movss	xmm1, DWORD PTR p0_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L16
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L16
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L4
.L16:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jb	.L4
	mov	eax, DWORD PTR id[rip]
	cmp	eax, 2
	je	.L18
	mov	eax, DWORD PTR id[rip]
	test	eax, eax
	je	.L18
	mov	eax, DWORD PTR id[rip]
	cmp	eax, 1
	jne	.L4
.L18:
	mov	eax, DWORD PTR turn[rip]
	cmp	eax, 1
	je	.L19
	mov	eax, DWORD PTR turn[rip]
	cmp	eax, 2
	jne	.L4
.L19:
	movss	xmm0, DWORD PTR delta[rip]
	movss	xmm1, DWORD PTR _diverge_delta[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	mov	eax, 1
	jmp	.L21
.L4:
	mov	eax, 0
.L21:
	mov	DWORD PTR -4[rbp], eax
	jmp	.L22
.L93:
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x__diverge_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p1_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p0_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p0_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p1_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p0_x[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_turn[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_id[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p1_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_delta[rip], eax
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L23
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L24
.L23:
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L25
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L24
.L25:
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L26
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L24
.L26:
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L27
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L27
.L24:
	movss	xmm1, DWORD PTR _x_p1_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L28
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L28
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L27
.L28:
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L29
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L29
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p1_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p1_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L29
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L30
.L29:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L27
	mov	eax, DWORD PTR turn[rip]
	cmp	eax, 2
	jne	.L27
.L30:
	mov	eax, DWORD PTR id[rip]
	test	eax, eax
	jne	.L33
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L33
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L33
	mov	edx, DWORD PTR id[rip]
	mov	eax, DWORD PTR _x_id[rip]
	cmp	edx, eax
	jne	.L33
	movss	xmm0, DWORD PTR _x_p1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L33
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L34
.L33:
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	jne	.L34
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	jne	.L34
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L34
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L34
	mov	eax, DWORD PTR turn[rip]
	cmp	eax, 2
	je	.L27
.L34:
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L36
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	jne	.L36
	movss	xmm1, DWORD PTR p1_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L36
	movss	xmm0, DWORD PTR _x_p1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L36
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L36
	mov	eax, DWORD PTR _x_id[rip]
	cmp	eax, 2
	je	.L39
.L36:
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L39
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	jne	.L39
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L39
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L39
	mov	eax, DWORD PTR turn[rip]
	cmp	eax, 2
	je	.L27
.L39:
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L40
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L41
.L40:
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L42
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	jne	.L41
.L42:
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L41
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	jne	.L41
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L41
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L41
	mov	eax, DWORD PTR turn[rip]
	cmp	eax, 2
	je	.L27
.L41:
	mov	edx, DWORD PTR id[rip]
	mov	eax, DWORD PTR _x_id[rip]
	cmp	edx, eax
	jne	.L43
	movss	xmm0, DWORD PTR _x_p1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L43
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L43
	movss	xmm1, DWORD PTR p1_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L43
	mov	eax, DWORD PTR id[rip]
	cmp	eax, 2
	jne	.L45
.L43:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L45
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L45
	mov	eax, DWORD PTR turn[rip]
	cmp	eax, 2
	jne	.L45
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L45
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	jne	.L45
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L45
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L27
.L45:
	mov	edx, DWORD PTR id[rip]
	mov	eax, DWORD PTR _x_id[rip]
	cmp	edx, eax
	jne	.L46
	movss	xmm0, DWORD PTR p1_x[rip]
	movss	xmm1, DWORD PTR _x_p1_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L46
	ucomiss	xmm0, xmm1
	jne	.L46
	movss	xmm1, DWORD PTR p1_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L46
	mov	eax, DWORD PTR id[rip]
	cmp	eax, 2
	je	.L48
.L46:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L48
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L48
	mov	eax, DWORD PTR turn[rip]
	cmp	eax, 2
	jne	.L48
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L48
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	jne	.L48
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L48
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	jne	.L27
.L48:
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L49
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	jne	.L49
	mov	eax, DWORD PTR _x_id[rip]
	test	eax, eax
	jne	.L49
	movss	xmm0, DWORD PTR p1_x[rip]
	movss	xmm1, DWORD PTR _x_p1_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L49
	ucomiss	xmm0, xmm1
	je	.L50
.L49:
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L50
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L50
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L50
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L50
	mov	eax, DWORD PTR turn[rip]
	cmp	eax, 2
	je	.L27
.L50:
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L52
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L53
.L52:
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L54
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L53
.L54:
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L55
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L53
.L55:
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L27
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L27
.L53:
	movss	xmm1, DWORD PTR _x_p0_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L56
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L56
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L27
.L56:
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L57
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L57
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p0_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p0_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L57
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L58
.L57:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L27
	mov	eax, DWORD PTR turn[rip]
	cmp	eax, 1
	jne	.L27
.L58:
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L61
	mov	eax, DWORD PTR id[rip]
	test	eax, eax
	jne	.L61
	movss	xmm0, DWORD PTR _x_p0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L61
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L61
	mov	edx, DWORD PTR id[rip]
	mov	eax, DWORD PTR _x_id[rip]
	cmp	edx, eax
	je	.L63
.L61:
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	jne	.L63
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	jne	.L63
	mov	eax, DWORD PTR turn[rip]
	cmp	eax, 1
	jne	.L63
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L63
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L27
.L63:
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L65
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	jne	.L65
	movss	xmm1, DWORD PTR p0_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L65
	movss	xmm0, DWORD PTR _x_p0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L65
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L65
	mov	eax, DWORD PTR _x_id[rip]
	cmp	eax, 1
	je	.L68
.L65:
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L68
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	jne	.L68
	mov	eax, DWORD PTR turn[rip]
	cmp	eax, 1
	jne	.L68
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L68
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L27
.L68:
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L70
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L71
.L70:
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L72
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	jne	.L71
.L72:
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L71
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	jne	.L71
	mov	eax, DWORD PTR turn[rip]
	cmp	eax, 1
	jne	.L71
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L71
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L27
.L71:
	movss	xmm0, DWORD PTR _x_p0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L74
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L74
	mov	edx, DWORD PTR id[rip]
	mov	eax, DWORD PTR _x_id[rip]
	cmp	edx, eax
	jne	.L74
	movss	xmm1, DWORD PTR p0_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L74
	mov	eax, DWORD PTR id[rip]
	cmp	eax, 1
	jne	.L76
.L74:
	mov	eax, DWORD PTR turn[rip]
	cmp	eax, 1
	jne	.L76
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L76
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L76
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L76
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	jne	.L76
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L76
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L27
.L76:
	mov	edx, DWORD PTR id[rip]
	mov	eax, DWORD PTR _x_id[rip]
	cmp	edx, eax
	jne	.L77
	movss	xmm0, DWORD PTR p0_x[rip]
	movss	xmm1, DWORD PTR _x_p0_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L77
	ucomiss	xmm0, xmm1
	jne	.L77
	movss	xmm1, DWORD PTR p0_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L77
	mov	eax, DWORD PTR id[rip]
	cmp	eax, 1
	je	.L79
.L77:
	mov	eax, DWORD PTR turn[rip]
	cmp	eax, 1
	jne	.L79
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L79
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L79
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L79
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	jne	.L79
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L79
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	jne	.L27
.L79:
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L80
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	jne	.L80
	movss	xmm0, DWORD PTR p0_x[rip]
	movss	xmm1, DWORD PTR _x_p0_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L80
	ucomiss	xmm0, xmm1
	jne	.L80
	mov	eax, DWORD PTR _x_id[rip]
	test	eax, eax
	je	.L82
.L80:
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L82
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L82
	mov	eax, DWORD PTR turn[rip]
	cmp	eax, 1
	jne	.L82
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L82
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L27
.L82:
	mov	eax, DWORD PTR id[rip]
	cmp	eax, 2
	je	.L84
	mov	eax, DWORD PTR id[rip]
	test	eax, eax
	je	.L84
	mov	eax, DWORD PTR id[rip]
	cmp	eax, 1
	jne	.L27
.L84:
	mov	eax, DWORD PTR _x_turn[rip]
	cmp	eax, 1
	je	.L85
	mov	eax, DWORD PTR _x_turn[rip]
	cmp	eax, 2
	jne	.L27
.L85:
	movss	xmm0, DWORD PTR _x_delta[rip]
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jb	.L27
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L87
	mov	edx, DWORD PTR id[rip]
	mov	eax, DWORD PTR _x_id[rip]
	cmp	edx, eax
	jne	.L27
	mov	edx, DWORD PTR turn[rip]
	mov	eax, DWORD PTR _x_turn[rip]
	cmp	edx, eax
	jne	.L27
.L87:
	movss	xmm0, DWORD PTR delta[rip]
	movss	xmm1, DWORD PTR _x__diverge_delta[rip]
	ucomiss	xmm0, xmm1
	jp	.L112
	ucomiss	xmm0, xmm1
	je	.L88
.L112:
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	movss	xmm1, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L27
.L88:
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	movss	xmm1, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	jnb	.L90
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x__diverge_delta[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L27
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L27
.L90:
	mov	eax, 1
	jmp	.L92
.L27:
	mov	eax, 0
.L92:
	mov	DWORD PTR -4[rbp], eax
	movss	xmm0, DWORD PTR _x__diverge_delta[rip]
	movss	DWORD PTR _diverge_delta[rip], xmm0
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	mov	BYTE PTR p1_l1[rip], al
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	mov	BYTE PTR p0_l1[rip], al
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	mov	BYTE PTR p0_l0[rip], al
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	mov	BYTE PTR p1_l0[rip], al
	movss	xmm0, DWORD PTR _x_p0_x[rip]
	movss	DWORD PTR p0_x[rip], xmm0
	mov	eax, DWORD PTR _x_turn[rip]
	mov	DWORD PTR turn[rip], eax
	mov	eax, DWORD PTR _x_id[rip]
	mov	DWORD PTR id[rip], eax
	movss	xmm0, DWORD PTR _x_p1_x[rip]
	movss	DWORD PTR p1_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_delta[rip]
	movss	DWORD PTR delta[rip], xmm0
.L22:
	cmp	DWORD PTR -4[rbp], 0
	jne	.L93
	mov	eax, 0
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	main, .-main
	.section	.rodata
	.align 4
.LC1:
	.long	1073741824
	.align 4
.LC3:
	.long	1065353216
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"552212.c"
	.text
	.align	2
	.global	__VERIFIER_nondet_bool
	.syntax unified
	.arm
	.fpu softvfp
	.type	__VERIFIER_nondet_bool, %function
__VERIFIER_nondet_bool:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	mov	r0, r3
	pop	{fp, pc}
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.comm	_diverge_delta,4,4
	.comm	_x__diverge_delta,4,4
	.comm	p1_l1,1,1
	.comm	_x_p1_l1,1,1
	.comm	p0_l1,1,1
	.comm	_x_p0_l1,1,1
	.comm	p0_l0,1,1
	.comm	_x_p0_l0,1,1
	.comm	p1_l0,1,1
	.comm	_x_p1_l0,1,1
	.comm	p0_x,4,4
	.comm	_x_p0_x,4,4
	.comm	turn,4,4
	.comm	_x_turn,4,4
	.comm	id,4,4
	.comm	_x_id,4,4
	.comm	p1_x,4,4
	.comm	_x_p1_x,4,4
	.comm	delta,4,4
	.comm	_x_delta,4,4
	.global	__aeabi_fcmpeq
	.global	__aeabi_fcmple
	.global	__aeabi_fcmpge
	.global	__aeabi_f2d
	.global	__aeabi_dsub
	.global	__aeabi_dadd
	.global	__aeabi_dcmpeq
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, fp, lr}
	add	fp, sp, #20
	sub	sp, sp, #8
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L112+72
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L112+20
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L112+44
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L112+40
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L112+16
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L112+32
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L112+60
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L112+52
	str	r3, [r2]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L112+8
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L112+68
	str	r3, [r2]	@ float
	ldr	r3, .L112+52
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L112+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L112+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L112+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L112+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L6
	ldr	r3, .L112+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L6:
	ldr	r3, .L112+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L112+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L8:
	ldr	r3, .L112+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L9
	ldr	r3, .L112+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L9:
	ldr	r3, .L112+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L112+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L7:
	ldr	r3, .L112+8
	ldr	r3, [r3]	@ float
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L10
	ldr	r3, .L112+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L10
	ldr	r3, .L112+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L10:
	ldr	r3, .L112+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L112+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L112+32
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L112+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L12
	ldr	r3, .L112+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L13
.L12:
	ldr	r3, .L112+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L14
	ldr	r3, .L112+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L13
.L14:
	ldr	r3, .L112+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L15
	ldr	r3, .L112+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L13
.L15:
	ldr	r3, .L112+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L112+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L13:
	ldr	r3, .L112+32
	ldr	r3, [r3]	@ float
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L16
	ldr	r3, .L112+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L16
	ldr	r3, .L112+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L16:
	ldr	r3, .L112+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L112+52
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L18
	ldr	r3, .L112+52
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L18
	ldr	r3, .L112+52
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L4
.L18:
	ldr	r3, .L112+60
	ldr	r3, [r3]
	cmp	r3, #1
	beq	.L19
	ldr	r3, .L112+60
	ldr	r3, [r3]
	cmp	r3, #2
	bne	.L4
.L19:
	ldr	r3, .L112+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L112+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	mov	r3, #1
	b	.L21
.L4:
	mov	r3, #0
.L21:
	str	r3, [fp, #-24]
	b	.L22
.L113:
	.align	2
.L112:
	.word	_x_p1_l0
	.word	_x_p1_l1
	.word	p1_x
	.word	_x_p1_x
	.word	p1_l0
	.word	p1_l1
	.word	_x_p0_l0
	.word	_x_p0_l1
	.word	p0_x
	.word	_x_p0_x
	.word	p0_l0
	.word	p0_l1
	.word	_x_delta
	.word	id
	.word	_x_id
	.word	turn
	.word	_x_turn
	.word	delta
	.word	_diverge_delta
	.word	_x__diverge_delta
.L93:
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L112+76
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L112+4
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L112+28
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L112+24
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L112
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L112+36
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L112+64
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L112+56
	str	r3, [r2]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L112+12
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L112+48
	str	r3, [r2]	@ float
	ldr	r3, .L112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L23
	ldr	r3, .L112+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L24
.L23:
	ldr	r3, .L112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L25
	ldr	r3, .L112+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L24
.L25:
	ldr	r3, .L112+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L26
	ldr	r3, .L112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L24
.L26:
	ldr	r3, .L112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L27
	ldr	r3, .L112+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L27
.L24:
	ldr	r3, .L112+12
	ldr	r3, [r3]	@ float
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L28
	ldr	r3, .L112+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L28
	ldr	r3, .L112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L27
.L28:
	ldr	r3, .L112+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L29
	ldr	r3, .L112+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L112+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L29
	ldr	r3, .L112+68
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L112+8
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L112+12
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L30
.L29:
	ldr	r3, .L112+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L27
	ldr	r3, .L112+60
	ldr	r3, [r3]
	cmp	r3, #2
	bne	.L27
.L30:
	ldr	r3, .L112+52
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L32
	ldr	r3, .L112+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L32
	ldr	r3, .L112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L32
	ldr	r3, .L112+52
	ldr	r2, [r3]
	ldr	r3, .L112+56
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L32
	ldr	r3, .L112+12
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L33
.L32:
	ldr	r3, .L112+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L33
	ldr	r3, .L112+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L33
	ldr	r3, .L112+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L33
	ldr	r3, .L112+60
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L27
.L33:
	ldr	r3, .L112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L34
	ldr	r3, .L112+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L34
	ldr	r3, .L112+8
	ldr	r3, [r3]	@ float
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L34
	ldr	r3, .L112+12
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L34
	ldr	r3, .L112+56
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L37
.L34:
	ldr	r3, .L112+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L37
	ldr	r3, .L112+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L37
	ldr	r3, .L112+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L37
	ldr	r3, .L112+60
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L27
.L37:
	ldr	r3, .L112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L38
	ldr	r3, .L112+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L39
.L38:
	ldr	r3, .L112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L40
	ldr	r3, .L112+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L39
.L40:
	ldr	r3, .L112+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L39
	ldr	r3, .L112+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L39
	ldr	r3, .L112+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L39
	ldr	r3, .L112+60
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L27
.L39:
	ldr	r3, .L112+52
	ldr	r2, [r3]
	ldr	r3, .L112+56
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L41
	ldr	r3, .L112+12
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L41
	ldr	r3, .L112+8
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L43
	mov	r3, #0
	mov	r4, r3
.L43:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L41
	ldr	r3, .L112+52
	ldr	r3, [r3]
	cmp	r3, #2
	bne	.L44
.L41:
	ldr	r3, .L112+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L44
	ldr	r3, .L112+60
	ldr	r3, [r3]
	cmp	r3, #2
	bne	.L44
	ldr	r3, .L112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L44
	ldr	r3, .L112+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L44
	ldr	r3, .L112+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L44
	ldr	r3, .L112+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L27
.L44:
	ldr	r3, .L112+52
	ldr	r2, [r3]
	ldr	r3, .L112+56
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L45
	ldr	r3, .L112+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L112+12
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L45
	ldr	r3, .L112+8
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L47
	mov	r3, #0
	mov	r4, r3
.L47:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L45
	ldr	r3, .L112+52
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L48
.L45:
	ldr	r3, .L112+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L48
	ldr	r3, .L112+60
	ldr	r3, [r3]
	cmp	r3, #2
	bne	.L48
	ldr	r3, .L112+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L48
	ldr	r3, .L112+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L48
	ldr	r3, .L112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L48
	ldr	r3, .L112+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L27
.L48:
	ldr	r3, .L112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L49
	ldr	r3, .L112+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L49
	ldr	r3, .L112+56
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L49
	ldr	r3, .L112+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L112+12
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L50
.L49:
	ldr	r3, .L112+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L50
	ldr	r3, .L112+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L50
	ldr	r3, .L112+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L50
	ldr	r3, .L112+60
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L27
.L50:
	ldr	r3, .L112+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L51
	ldr	r3, .L112+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L52
.L51:
	ldr	r3, .L112+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L53
	ldr	r3, .L112+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L52
.L53:
	ldr	r3, .L112+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L54
	ldr	r3, .L112+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L52
.L54:
	ldr	r3, .L112+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L27
	ldr	r3, .L112+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L27
.L52:
	ldr	r3, .L112+36
	ldr	r3, [r3]	@ float
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L55
	ldr	r3, .L112+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L55
	ldr	r3, .L112+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L27
.L55:
	ldr	r3, .L112+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L112+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L56
	ldr	r3, .L112+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L112+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L56
	ldr	r3, .L112+68
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L112+32
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L112+36
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L57
.L56:
	ldr	r3, .L112+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L27
	ldr	r3, .L112+60
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L27
.L57:
	ldr	r3, .L112+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L112+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L112+52
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L112+36
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L112+52
	ldr	r2, [r3]
	ldr	r3, .L112+56
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L61
.L59:
	ldr	r3, .L112+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L112+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L112+60
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L61
	ldr	r3, .L112+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L27
.L61:
	ldr	r3, .L112+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L112+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L112+32
	ldr	r3, [r3]	@ float
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L112+36
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L112+56
	ldr	r3, [r3]
	cmp	r3, #1
	beq	.L66
.L63:
	ldr	r3, .L112+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L66
	ldr	r3, .L112+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L66
	ldr	r3, .L112+60
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L66
	ldr	r3, .L112+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L27
.L66:
	ldr	r3, .L112+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L68
	ldr	r3, .L112+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L69
.L68:
	ldr	r3, .L112+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L70
	ldr	r3, .L112+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L69
.L70:
	ldr	r3, .L112+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L69
	ldr	r3, .L112+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L69
	ldr	r3, .L112+60
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L69
	ldr	r3, .L112+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L27
.L69:
	ldr	r3, .L112+36
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L72
	ldr	r3, .L112+52
	ldr	r2, [r3]
	ldr	r3, .L112+56
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L72
	ldr	r3, .L112+32
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L74
	mov	r3, #0
	mov	r4, r3
.L74:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L72
	ldr	r3, .L112+52
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L75
.L72:
	ldr	r3, .L112+60
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L75
	ldr	r3, .L112+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L75
	ldr	r3, .L112+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L75
	ldr	r3, .L112+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L75
	ldr	r3, .L112+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L75
	ldr	r3, .L112+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L27
.L75:
	ldr	r3, .L112+52
	ldr	r2, [r3]
	ldr	r3, .L112+56
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L76
	ldr	r3, .L112+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L112+36
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L76
	ldr	r3, .L112+32
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L78
	mov	r3, #0
	mov	r4, r3
.L78:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L76
	ldr	r3, .L112+52
	ldr	r3, [r3]
	cmp	r3, #1
	beq	.L79
.L76:
	ldr	r3, .L112+60
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L79
	ldr	r3, .L112+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L79
	ldr	r3, .L112+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L79
	ldr	r3, .L112+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L79
	ldr	r3, .L112+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L79
	ldr	r3, .L112+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L27
.L79:
	ldr	r3, .L112+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L80
	ldr	r3, .L112+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L80
	ldr	r3, .L112+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L112+36
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L80
	ldr	r3, .L112+56
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L82
.L80:
	ldr	r3, .L112+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L82
	ldr	r3, .L112+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L82
	ldr	r3, .L112+60
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L82
	ldr	r3, .L112+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L27
.L82:
	ldr	r3, .L112+52
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L84
	ldr	r3, .L112+52
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L84
	ldr	r3, .L112+52
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L27
.L84:
	ldr	r3, .L112+64
	ldr	r3, [r3]
	cmp	r3, #1
	beq	.L85
	ldr	r3, .L112+64
	ldr	r3, [r3]
	cmp	r3, #2
	bne	.L27
.L85:
	ldr	r3, .L112+48
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L27
	ldr	r3, .L112+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L87
	ldr	r3, .L112+52
	ldr	r2, [r3]
	ldr	r3, .L112+56
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L27
	ldr	r3, .L112+60
	ldr	r2, [r3]
	ldr	r3, .L112+64
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L27
.L87:
	ldr	r3, .L112+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L112+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L88
	ldr	r3, .L112+72
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L89
	mov	r3, #0
	mov	r4, r3
.L89:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L27
.L88:
	ldr	r3, .L112+72
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L90
	ldr	r3, .L112+68
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L112+72
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L112+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L27
.L90:
	mov	r3, #1
	b	.L92
.L27:
	mov	r3, #0
.L92:
	str	r3, [fp, #-24]
	ldr	r3, .L114
	ldr	r3, [r3]	@ float
	ldr	r2, .L114+4
	str	r3, [r2]	@ float
	ldr	r3, .L114+8
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L114+12
	strb	r2, [r3]
	ldr	r3, .L114+16
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L114+20
	strb	r2, [r3]
	ldr	r3, .L114+24
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L114+28
	strb	r2, [r3]
	ldr	r3, .L114+32
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L114+36
	strb	r2, [r3]
	ldr	r3, .L114+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L114+44
	str	r3, [r2]	@ float
	ldr	r3, .L114+48
	ldr	r3, [r3]
	ldr	r2, .L114+52
	str	r3, [r2]
	ldr	r3, .L114+56
	ldr	r3, [r3]
	ldr	r2, .L114+60
	str	r3, [r2]
	ldr	r3, .L114+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L114+68
	str	r3, [r2]	@ float
	ldr	r3, .L114+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L114+76
	str	r3, [r2]	@ float
.L22:
	ldr	r3, [fp, #-24]
	cmp	r3, #0
	bne	.L93
	mov	r3, #0
	mov	r0, r3
	sub	sp, fp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, fp, pc}
.L115:
	.align	2
.L114:
	.word	_x__diverge_delta
	.word	_diverge_delta
	.word	_x_p1_l1
	.word	p1_l1
	.word	_x_p0_l1
	.word	p0_l1
	.word	_x_p0_l0
	.word	p0_l0
	.word	_x_p1_l0
	.word	p1_l0
	.word	_x_p0_x
	.word	p0_x
	.word	_x_turn
	.word	turn
	.word	_x_id
	.word	id
	.word	_x_p1_x
	.word	p1_x
	.word	_x_delta
	.word	delta
	.size	main, .-main
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
