	.file	"799185.c"
	.intel_syntax noprefix
	.text
	.globl	SIMD_LOAD_CONSTANT_V4SI
	.type	SIMD_LOAD_CONSTANT_V4SI, @function
SIMD_LOAD_CONSTANT_V4SI:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	DWORD PTR -12[rbp], esi
	mov	DWORD PTR -16[rbp], edx
	mov	DWORD PTR -20[rbp], ecx
	mov	DWORD PTR -24[rbp], r8d
	mov	rax, QWORD PTR -8[rbp]
	mov	edx, DWORD PTR -12[rbp]
	mov	DWORD PTR [rax], edx
	mov	rax, QWORD PTR -8[rbp]
	lea	rdx, 4[rax]
	mov	eax, DWORD PTR -16[rbp]
	mov	DWORD PTR [rdx], eax
	mov	rax, QWORD PTR -8[rbp]
	lea	rdx, 8[rax]
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR [rdx], eax
	mov	rax, QWORD PTR -8[rbp]
	lea	rdx, 12[rax]
	mov	eax, DWORD PTR -24[rbp]
	mov	DWORD PTR [rdx], eax
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	SIMD_LOAD_CONSTANT_V4SI, .-SIMD_LOAD_CONSTANT_V4SI
	.globl	SIMD_LOAD_V4SI
	.type	SIMD_LOAD_V4SI, @function
SIMD_LOAD_V4SI:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	QWORD PTR -16[rbp], rsi
	mov	rax, QWORD PTR -16[rbp]
	movzx	edx, WORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	mov	WORD PTR [rax], dx
	mov	rax, QWORD PTR -8[rbp]
	lea	rdx, 2[rax]
	mov	rax, QWORD PTR -16[rbp]
	movzx	eax, WORD PTR 2[rax]
	mov	WORD PTR [rdx], ax
	mov	rax, QWORD PTR -8[rbp]
	lea	rdx, 4[rax]
	mov	rax, QWORD PTR -16[rbp]
	movzx	eax, WORD PTR 4[rax]
	mov	WORD PTR [rdx], ax
	mov	rax, QWORD PTR -8[rbp]
	lea	rdx, 6[rax]
	mov	rax, QWORD PTR -16[rbp]
	movzx	eax, WORD PTR 6[rax]
	mov	WORD PTR [rdx], ax
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	SIMD_LOAD_V4SI, .-SIMD_LOAD_V4SI
	.globl	SIMD_STORE_GENERIC_V4SI
	.type	SIMD_STORE_GENERIC_V4SI, @function
SIMD_STORE_GENERIC_V4SI:
.LFB2:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	QWORD PTR -16[rbp], rsi
	mov	QWORD PTR -24[rbp], rdx
	mov	QWORD PTR -32[rbp], rcx
	mov	QWORD PTR -40[rbp], r8
	mov	rax, QWORD PTR -8[rbp]
	mov	edx, DWORD PTR [rax]
	mov	rax, QWORD PTR -16[rbp]
	mov	DWORD PTR [rax], edx
	mov	rax, QWORD PTR -8[rbp]
	mov	edx, DWORD PTR 4[rax]
	mov	rax, QWORD PTR -24[rbp]
	mov	DWORD PTR [rax], edx
	mov	rax, QWORD PTR -8[rbp]
	mov	edx, DWORD PTR 8[rax]
	mov	rax, QWORD PTR -32[rbp]
	mov	DWORD PTR [rax], edx
	mov	rax, QWORD PTR -8[rbp]
	mov	edx, DWORD PTR 12[rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR [rax], edx
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE2:
	.size	SIMD_STORE_GENERIC_V4SI, .-SIMD_STORE_GENERIC_V4SI
	.globl	SIMD_LOAD_GENERIC_V4SI
	.type	SIMD_LOAD_GENERIC_V4SI, @function
SIMD_LOAD_GENERIC_V4SI:
.LFB3:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	eax, ecx
	mov	ecx, r8d
	mov	WORD PTR -12[rbp], si
	mov	WORD PTR -16[rbp], dx
	mov	WORD PTR -20[rbp], ax
	mov	eax, ecx
	mov	WORD PTR -24[rbp], ax
	mov	rax, QWORD PTR -8[rbp]
	movzx	edx, WORD PTR -12[rbp]
	mov	WORD PTR [rax], dx
	mov	rax, QWORD PTR -8[rbp]
	lea	rdx, 2[rax]
	movzx	eax, WORD PTR -16[rbp]
	mov	WORD PTR [rdx], ax
	mov	rax, QWORD PTR -8[rbp]
	lea	rdx, 4[rax]
	movzx	eax, WORD PTR -20[rbp]
	mov	WORD PTR [rdx], ax
	mov	rax, QWORD PTR -8[rbp]
	lea	rdx, 6[rax]
	movzx	eax, WORD PTR -24[rbp]
	mov	WORD PTR [rdx], ax
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE3:
	.size	SIMD_LOAD_GENERIC_V4SI, .-SIMD_LOAD_GENERIC_V4SI
	.globl	SIMD_STORE_V4SI
	.type	SIMD_STORE_V4SI, @function
SIMD_STORE_V4SI:
.LFB4:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	QWORD PTR -16[rbp], rsi
	mov	rax, QWORD PTR -8[rbp]
	movzx	edx, WORD PTR [rax]
	mov	rax, QWORD PTR -16[rbp]
	mov	WORD PTR [rax], dx
	mov	rax, QWORD PTR -16[rbp]
	lea	rdx, 2[rax]
	mov	rax, QWORD PTR -8[rbp]
	movzx	eax, WORD PTR 2[rax]
	mov	WORD PTR [rdx], ax
	mov	rax, QWORD PTR -16[rbp]
	lea	rdx, 4[rax]
	mov	rax, QWORD PTR -8[rbp]
	movzx	eax, WORD PTR 4[rax]
	mov	WORD PTR [rdx], ax
	mov	rax, QWORD PTR -16[rbp]
	lea	rdx, 6[rax]
	mov	rax, QWORD PTR -8[rbp]
	movzx	eax, WORD PTR 6[rax]
	mov	WORD PTR [rdx], ax
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE4:
	.size	SIMD_STORE_V4SI, .-SIMD_STORE_V4SI
	.globl	SIMD_ADDW
	.type	SIMD_ADDW, @function
SIMD_ADDW:
.LFB5:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	QWORD PTR -16[rbp], rsi
	mov	QWORD PTR -24[rbp], rdx
	mov	rax, QWORD PTR -16[rbp]
	movzx	eax, WORD PTR [rax]
	mov	edx, eax
	mov	rax, QWORD PTR -24[rbp]
	movzx	eax, WORD PTR [rax]
	add	eax, edx
	mov	edx, eax
	mov	rax, QWORD PTR -8[rbp]
	mov	WORD PTR [rax], dx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 2
	movzx	eax, WORD PTR [rax]
	mov	edx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 2
	movzx	eax, WORD PTR [rax]
	add	edx, eax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 2
	mov	WORD PTR [rax], dx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 4
	movzx	eax, WORD PTR [rax]
	mov	edx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 4
	movzx	eax, WORD PTR [rax]
	add	edx, eax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 4
	mov	WORD PTR [rax], dx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 6
	movzx	eax, WORD PTR [rax]
	mov	edx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 6
	movzx	eax, WORD PTR [rax]
	add	edx, eax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 6
	mov	WORD PTR [rax], dx
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE5:
	.size	SIMD_ADDW, .-SIMD_ADDW
	.globl	SIMD_SUBW
	.type	SIMD_SUBW, @function
SIMD_SUBW:
.LFB6:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	QWORD PTR -16[rbp], rsi
	mov	QWORD PTR -24[rbp], rdx
	mov	rax, QWORD PTR -16[rbp]
	movzx	eax, WORD PTR [rax]
	mov	edx, eax
	mov	rax, QWORD PTR -24[rbp]
	movzx	eax, WORD PTR [rax]
	mov	ecx, eax
	mov	eax, edx
	sub	eax, ecx
	mov	edx, eax
	mov	rax, QWORD PTR -8[rbp]
	mov	WORD PTR [rax], dx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 2
	movzx	eax, WORD PTR [rax]
	mov	edx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 2
	movzx	eax, WORD PTR [rax]
	sub	edx, eax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 2
	mov	WORD PTR [rax], dx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 4
	movzx	eax, WORD PTR [rax]
	mov	edx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 4
	movzx	eax, WORD PTR [rax]
	sub	edx, eax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 4
	mov	WORD PTR [rax], dx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 6
	movzx	eax, WORD PTR [rax]
	mov	edx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 6
	movzx	eax, WORD PTR [rax]
	sub	edx, eax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 6
	mov	WORD PTR [rax], dx
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE6:
	.size	SIMD_SUBW, .-SIMD_SUBW
	.globl	SIMD_MULW
	.type	SIMD_MULW, @function
SIMD_MULW:
.LFB7:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	QWORD PTR -16[rbp], rsi
	mov	QWORD PTR -24[rbp], rdx
	mov	rax, QWORD PTR -16[rbp]
	movzx	eax, WORD PTR [rax]
	mov	edx, eax
	mov	rax, QWORD PTR -24[rbp]
	movzx	eax, WORD PTR [rax]
	imul	eax, edx
	mov	edx, eax
	mov	rax, QWORD PTR -8[rbp]
	mov	WORD PTR [rax], dx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 2
	movzx	eax, WORD PTR [rax]
	mov	edx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 2
	movzx	eax, WORD PTR [rax]
	imul	edx, eax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 2
	mov	WORD PTR [rax], dx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 4
	movzx	eax, WORD PTR [rax]
	mov	edx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 4
	movzx	eax, WORD PTR [rax]
	imul	edx, eax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 4
	mov	WORD PTR [rax], dx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 6
	movzx	eax, WORD PTR [rax]
	mov	edx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 6
	movzx	eax, WORD PTR [rax]
	imul	edx, eax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 6
	mov	WORD PTR [rax], dx
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE7:
	.size	SIMD_MULW, .-SIMD_MULW
	.globl	SIMD_GTW
	.type	SIMD_GTW, @function
SIMD_GTW:
.LFB8:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	QWORD PTR -16[rbp], rsi
	mov	QWORD PTR -24[rbp], rdx
	mov	rax, QWORD PTR -16[rbp]
	movzx	edx, WORD PTR [rax]
	mov	rax, QWORD PTR -24[rbp]
	movzx	eax, WORD PTR [rax]
	cmp	dx, ax
	setg	al
	movzx	edx, al
	mov	rax, QWORD PTR -8[rbp]
	mov	DWORD PTR [rax], edx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 2
	movzx	edx, WORD PTR [rax]
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 2
	movzx	eax, WORD PTR [rax]
	cmp	dx, ax
	setg	cl
	mov	rax, QWORD PTR -8[rbp]
	lea	rdx, 4[rax]
	movzx	eax, cl
	mov	DWORD PTR [rdx], eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 4
	movzx	edx, WORD PTR [rax]
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 4
	movzx	eax, WORD PTR [rax]
	cmp	dx, ax
	setg	cl
	mov	rax, QWORD PTR -8[rbp]
	lea	rdx, 8[rax]
	movzx	eax, cl
	mov	DWORD PTR [rdx], eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 6
	movzx	edx, WORD PTR [rax]
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 6
	movzx	eax, WORD PTR [rax]
	cmp	dx, ax
	setg	cl
	mov	rax, QWORD PTR -8[rbp]
	lea	rdx, 12[rax]
	movzx	eax, cl
	mov	DWORD PTR [rdx], eax
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE8:
	.size	SIMD_GTW, .-SIMD_GTW
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"799185.c"
	.text
	.align	2
	.global	SIMD_LOAD_CONSTANT_V4SI
	.syntax unified
	.arm
	.fpu softvfp
	.type	SIMD_LOAD_CONSTANT_V4SI, %function
SIMD_LOAD_CONSTANT_V4SI:
	@ args = 4, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	str	r2, [fp, #-16]
	str	r3, [fp, #-20]
	ldr	r3, [fp, #-8]
	ldr	r2, [fp, #-12]
	str	r2, [r3]
	ldr	r3, [fp, #-8]
	add	r3, r3, #4
	ldr	r2, [fp, #-16]
	str	r2, [r3]
	ldr	r3, [fp, #-8]
	add	r3, r3, #8
	ldr	r2, [fp, #-20]
	str	r2, [r3]
	ldr	r3, [fp, #-8]
	add	r3, r3, #12
	ldr	r2, [fp, #4]
	str	r2, [r3]
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	SIMD_LOAD_CONSTANT_V4SI, .-SIMD_LOAD_CONSTANT_V4SI
	.align	2
	.global	SIMD_LOAD_V4SI
	.syntax unified
	.arm
	.fpu softvfp
	.type	SIMD_LOAD_V4SI, %function
SIMD_LOAD_V4SI:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-12]
	ldrsh	r2, [r3]
	ldr	r3, [fp, #-8]
	strh	r2, [r3]	@ movhi
	ldr	r3, [fp, #-8]
	add	r3, r3, #2
	ldr	r2, [fp, #-12]
	ldrsh	r2, [r2, #2]
	strh	r2, [r3]	@ movhi
	ldr	r3, [fp, #-8]
	add	r3, r3, #4
	ldr	r2, [fp, #-12]
	ldrsh	r2, [r2, #4]
	strh	r2, [r3]	@ movhi
	ldr	r3, [fp, #-8]
	add	r3, r3, #6
	ldr	r2, [fp, #-12]
	ldrsh	r2, [r2, #6]
	strh	r2, [r3]	@ movhi
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	SIMD_LOAD_V4SI, .-SIMD_LOAD_V4SI
	.align	2
	.global	SIMD_STORE_GENERIC_V4SI
	.syntax unified
	.arm
	.fpu softvfp
	.type	SIMD_STORE_GENERIC_V4SI, %function
SIMD_STORE_GENERIC_V4SI:
	@ args = 4, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	str	r2, [fp, #-16]
	str	r3, [fp, #-20]
	ldr	r3, [fp, #-8]
	ldr	r2, [r3]
	ldr	r3, [fp, #-12]
	str	r2, [r3]
	ldr	r3, [fp, #-8]
	ldr	r2, [r3, #4]
	ldr	r3, [fp, #-16]
	str	r2, [r3]
	ldr	r3, [fp, #-8]
	ldr	r2, [r3, #8]
	ldr	r3, [fp, #-20]
	str	r2, [r3]
	ldr	r3, [fp, #-8]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #4]
	str	r2, [r3]
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	SIMD_STORE_GENERIC_V4SI, .-SIMD_STORE_GENERIC_V4SI
	.align	2
	.global	SIMD_LOAD_GENERIC_V4SI
	.syntax unified
	.arm
	.fpu softvfp
	.type	SIMD_LOAD_GENERIC_V4SI, %function
SIMD_LOAD_GENERIC_V4SI:
	@ args = 4, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-8]
	mov	r0, r1
	mov	r1, r2
	mov	r2, r3
	mov	r3, r0	@ movhi
	strh	r3, [fp, #-10]	@ movhi
	mov	r3, r1	@ movhi
	strh	r3, [fp, #-12]	@ movhi
	mov	r3, r2	@ movhi
	strh	r3, [fp, #-14]	@ movhi
	ldr	r3, [fp, #-8]
	ldrh	r2, [fp, #-10]	@ movhi
	strh	r2, [r3]	@ movhi
	ldr	r3, [fp, #-8]
	add	r3, r3, #2
	ldrh	r2, [fp, #-12]	@ movhi
	strh	r2, [r3]	@ movhi
	ldr	r3, [fp, #-8]
	add	r3, r3, #4
	ldrh	r2, [fp, #-14]	@ movhi
	strh	r2, [r3]	@ movhi
	ldr	r3, [fp, #-8]
	add	r3, r3, #6
	ldrh	r2, [fp, #4]	@ movhi
	strh	r2, [r3]	@ movhi
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	SIMD_LOAD_GENERIC_V4SI, .-SIMD_LOAD_GENERIC_V4SI
	.align	2
	.global	SIMD_STORE_V4SI
	.syntax unified
	.arm
	.fpu softvfp
	.type	SIMD_STORE_V4SI, %function
SIMD_STORE_V4SI:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-8]
	ldrsh	r2, [r3]
	ldr	r3, [fp, #-12]
	strh	r2, [r3]	@ movhi
	ldr	r3, [fp, #-12]
	add	r3, r3, #2
	ldr	r2, [fp, #-8]
	ldrsh	r2, [r2, #2]
	strh	r2, [r3]	@ movhi
	ldr	r3, [fp, #-12]
	add	r3, r3, #4
	ldr	r2, [fp, #-8]
	ldrsh	r2, [r2, #4]
	strh	r2, [r3]	@ movhi
	ldr	r3, [fp, #-12]
	add	r3, r3, #6
	ldr	r2, [fp, #-8]
	ldrsh	r2, [r2, #6]
	strh	r2, [r3]	@ movhi
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	SIMD_STORE_V4SI, .-SIMD_STORE_V4SI
	.align	2
	.global	SIMD_ADDW
	.syntax unified
	.arm
	.fpu softvfp
	.type	SIMD_ADDW, %function
SIMD_ADDW:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	str	r2, [fp, #-16]
	ldr	r3, [fp, #-12]
	ldrsh	r3, [r3]
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldr	r3, [fp, #-16]
	ldrsh	r3, [r3]
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	add	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldr	r3, [fp, #-8]
	strh	r2, [r3]	@ movhi
	ldr	r3, [fp, #-12]
	add	r3, r3, #2
	ldrsh	r3, [r3]
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldr	r3, [fp, #-16]
	add	r3, r3, #2
	ldrsh	r3, [r3]
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	add	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldr	r3, [fp, #-8]
	add	r3, r3, #2
	lsl	r2, r2, #16
	asr	r2, r2, #16
	strh	r2, [r3]	@ movhi
	ldr	r3, [fp, #-12]
	add	r3, r3, #4
	ldrsh	r3, [r3]
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldr	r3, [fp, #-16]
	add	r3, r3, #4
	ldrsh	r3, [r3]
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	add	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldr	r3, [fp, #-8]
	add	r3, r3, #4
	lsl	r2, r2, #16
	asr	r2, r2, #16
	strh	r2, [r3]	@ movhi
	ldr	r3, [fp, #-12]
	add	r3, r3, #6
	ldrsh	r3, [r3]
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldr	r3, [fp, #-16]
	add	r3, r3, #6
	ldrsh	r3, [r3]
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	add	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldr	r3, [fp, #-8]
	add	r3, r3, #6
	lsl	r2, r2, #16
	asr	r2, r2, #16
	strh	r2, [r3]	@ movhi
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	SIMD_ADDW, .-SIMD_ADDW
	.align	2
	.global	SIMD_SUBW
	.syntax unified
	.arm
	.fpu softvfp
	.type	SIMD_SUBW, %function
SIMD_SUBW:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	str	r2, [fp, #-16]
	ldr	r3, [fp, #-12]
	ldrsh	r3, [r3]
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldr	r3, [fp, #-16]
	ldrsh	r3, [r3]
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	sub	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldr	r3, [fp, #-8]
	strh	r2, [r3]	@ movhi
	ldr	r3, [fp, #-12]
	add	r3, r3, #2
	ldrsh	r3, [r3]
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldr	r3, [fp, #-16]
	add	r3, r3, #2
	ldrsh	r3, [r3]
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	sub	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldr	r3, [fp, #-8]
	add	r3, r3, #2
	lsl	r2, r2, #16
	asr	r2, r2, #16
	strh	r2, [r3]	@ movhi
	ldr	r3, [fp, #-12]
	add	r3, r3, #4
	ldrsh	r3, [r3]
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldr	r3, [fp, #-16]
	add	r3, r3, #4
	ldrsh	r3, [r3]
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	sub	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldr	r3, [fp, #-8]
	add	r3, r3, #4
	lsl	r2, r2, #16
	asr	r2, r2, #16
	strh	r2, [r3]	@ movhi
	ldr	r3, [fp, #-12]
	add	r3, r3, #6
	ldrsh	r3, [r3]
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldr	r3, [fp, #-16]
	add	r3, r3, #6
	ldrsh	r3, [r3]
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	sub	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldr	r3, [fp, #-8]
	add	r3, r3, #6
	lsl	r2, r2, #16
	asr	r2, r2, #16
	strh	r2, [r3]	@ movhi
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	SIMD_SUBW, .-SIMD_SUBW
	.align	2
	.global	SIMD_MULW
	.syntax unified
	.arm
	.fpu softvfp
	.type	SIMD_MULW, %function
SIMD_MULW:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	str	r2, [fp, #-16]
	ldr	r3, [fp, #-12]
	ldrsh	r3, [r3]
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	ldr	r2, [fp, #-16]
	ldrsh	r2, [r2]
	lsl	r2, r2, #16
	lsr	r2, r2, #16
	mul	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldr	r3, [fp, #-8]
	strh	r2, [r3]	@ movhi
	ldr	r3, [fp, #-12]
	add	r3, r3, #2
	ldrsh	r3, [r3]
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	ldr	r2, [fp, #-16]
	add	r2, r2, #2
	ldrsh	r2, [r2]
	lsl	r2, r2, #16
	lsr	r2, r2, #16
	mul	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldr	r3, [fp, #-8]
	add	r3, r3, #2
	lsl	r2, r2, #16
	asr	r2, r2, #16
	strh	r2, [r3]	@ movhi
	ldr	r3, [fp, #-12]
	add	r3, r3, #4
	ldrsh	r3, [r3]
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	ldr	r2, [fp, #-16]
	add	r2, r2, #4
	ldrsh	r2, [r2]
	lsl	r2, r2, #16
	lsr	r2, r2, #16
	mul	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldr	r3, [fp, #-8]
	add	r3, r3, #4
	lsl	r2, r2, #16
	asr	r2, r2, #16
	strh	r2, [r3]	@ movhi
	ldr	r3, [fp, #-12]
	add	r3, r3, #6
	ldrsh	r3, [r3]
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	ldr	r2, [fp, #-16]
	add	r2, r2, #6
	ldrsh	r2, [r2]
	lsl	r2, r2, #16
	lsr	r2, r2, #16
	mul	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldr	r3, [fp, #-8]
	add	r3, r3, #6
	lsl	r2, r2, #16
	asr	r2, r2, #16
	strh	r2, [r3]	@ movhi
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	SIMD_MULW, .-SIMD_MULW
	.align	2
	.global	SIMD_GTW
	.syntax unified
	.arm
	.fpu softvfp
	.type	SIMD_GTW, %function
SIMD_GTW:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	str	r2, [fp, #-16]
	ldr	r3, [fp, #-12]
	ldrsh	r2, [r3]
	ldr	r3, [fp, #-16]
	ldrsh	r3, [r3]
	cmp	r2, r3
	movgt	r3, #1
	movle	r3, #0
	and	r3, r3, #255
	mov	r2, r3
	ldr	r3, [fp, #-8]
	str	r2, [r3]
	ldr	r3, [fp, #-12]
	add	r3, r3, #2
	ldrsh	r2, [r3]
	ldr	r3, [fp, #-16]
	add	r3, r3, #2
	ldrsh	r3, [r3]
	cmp	r2, r3
	movgt	r3, #1
	movle	r3, #0
	and	r2, r3, #255
	ldr	r3, [fp, #-8]
	add	r3, r3, #4
	str	r2, [r3]
	ldr	r3, [fp, #-12]
	add	r3, r3, #4
	ldrsh	r2, [r3]
	ldr	r3, [fp, #-16]
	add	r3, r3, #4
	ldrsh	r3, [r3]
	cmp	r2, r3
	movgt	r3, #1
	movle	r3, #0
	and	r2, r3, #255
	ldr	r3, [fp, #-8]
	add	r3, r3, #8
	str	r2, [r3]
	ldr	r3, [fp, #-12]
	add	r3, r3, #6
	ldrsh	r2, [r3]
	ldr	r3, [fp, #-16]
	add	r3, r3, #6
	ldrsh	r3, [r3]
	cmp	r2, r3
	movgt	r3, #1
	movle	r3, #0
	and	r2, r3, #255
	ldr	r3, [fp, #-8]
	add	r3, r3, #12
	str	r2, [r3]
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	SIMD_GTW, .-SIMD_GTW
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
