<p>Just as @Dmitri Budnikov memtioned, cache information is not public available.</p>

<p>Some researchers are working on this problem, and <a href="http://arxiv.org/pdf/1509.02308.pdf" rel="nofollow">This Paper</a> give us some insights on the memory hierarchy of GPU architecture.</p>

<p>Their findings on L2 cache can be summarized as below:</p>

<ol>
<li>The replacement policy of the L2 cache is not LRU;</li>
<li>The L2 cache line size is 32 bytes;</li>
<li>The data mapping is sophisticated and not conventional bits-defined;</li>
<li>A hardware-level pre-fetching mechanism from the DRAM to the L2 data cache is found on fermi, Kepler and Maxwell architecture.</li>
</ol>

<p>The benchmarks they developed can be found <a href="http://www.comp.hkbu.edu.hk/~chxw/gpu_benchmark.html#l2_cache" rel="nofollow">here</a>.</p>
Does anyone knows about details of L2 cache structure of NVIDIA Kepler GPUs(Mapping function, Replacement policy, Associativity)?
<p>I need the detail information about L2 caches of NVIDIA Kepler GPUs. I know the size (e.g. 512KB on GT740M GPU) and block size (32B) of the cache. I tried to capture the associativity, replacement policy, and more importantly, the mapping function (from global address to cache line), by a sample kernel and profiling the read hit ratio by nvprof profiler. I realized that mapping is not modulo operation. Is there any trick to find out what cache line a given global address is mapped to? can anyone help me?</p>