<p><strong>The bottleneck in all of your examples is the predecoder.</strong></p>
<p>I analyzed your examples with my simulator uiCA (<a href="https://uica.uops.info/" rel="nofollow noreferrer">https://uica.uops.info/</a>, <a href="https://github.com/andreas-abel/uiCA" rel="nofollow noreferrer">https://github.com/andreas-abel/uiCA</a>). It predicts the following throughputs, which closely match your measurements:</p>
<div class="s-table-container">
<table class="s-table">
<thead>
<tr>
<th></th>
<th>TP</th>
<th>Link</th>
</tr>
</thead>
<tbody>
<tr>
<td>g1a</td>
<td>13.00</td>
<td><a href="https://uica.uops.info/?code=.test7:%0D%0A%09times%2032%20nop%0D%0A%09mov%20eax,-1%0D%0A%09mov%20ebx,-1%0D%0A%09%3Bmov%20ecx,-1%0D%0A%09mov%20edx,-1%0D%0A%09mov%20edi,-1%0D%0A%09mov%20esi,-1%0D%0A%09mov%20r8d,-1%0D%0A%09mov%20r9d,-1%0D%0A%09mov%20r10d,-1%0D%0A%09mov%20r11d,-1%0D%0A%09mov%20r12d,-1%0D%0A%09mov%20r13d,-1%0D%0A%09mov%20r14d,-1%0D%0A%09mov%20r15d,-1%0D%0A%0D%0A%09dec%20ecx%0D%0A%09jge%20.test7%0D%0A&amp;syntax=NASM&amp;uArchs=SKL&amp;tools=uiCA&amp;alignment=0&amp;uiCAHtmlOptions=traceTable&amp;uiCAHtmlOptions=graph" rel="nofollow noreferrer">https://uica.uops.info/?code=...</a></td>
</tr>
<tr>
<td>g1b</td>
<td>14.00</td>
<td><a href="https://uica.uops.info/?code=.test3:%0D%0A%09times%2032%20nop%0D%0A%09mov%20rax,-1%0D%0A%09mov%20rbx,-1%0D%0A%09%3Bmov%20ecx,-1%0D%0A%09mov%20rdx,-1%0D%0A%09mov%20rdi,-1%0D%0A%09mov%20rsi,-1%0D%0A%09mov%20r8,-1%0D%0A%09mov%20r9,-1%0D%0A%09mov%20r10,-1%0D%0A%09mov%20r11,-1%0D%0A%09mov%20r12,-1%0D%0A%09mov%20r13,-1%0D%0A%09mov%20r14,-1%0D%0A%09mov%20r15,-1%0D%0A%0D%0A%09dec%20ecx%0D%0A%09jge%20.test3&amp;syntax=NASM&amp;uArchs=SKL&amp;tools=uiCA&amp;alignment=0&amp;uiCAHtmlOptions=traceTable&amp;uiCAHtmlOptions=graph" rel="nofollow noreferrer">https://uica.uops.info/?code=...</a></td>
</tr>
<tr>
<td>g2a</td>
<td>16.00</td>
<td><a href="https://uica.uops.info/?code=.test6:%0D%0A%09times%2032%20nop%0D%0A%09xor%20eax,%20eax%0D%0A%09dec%20eax%09%0D%0A%09xor%20ebx,%20ebx%0D%0A%09dec%20ebx%0D%0A%09xor%20edx,%20edx%0D%0A%09dec%20edx%0D%0A%09xor%20edi,%20edi%0D%0A%09dec%20edi%0D%0A%09xor%20esi,%20esi%0D%0A%09dec%20esi%0D%0A%09xor%20r8d,%20r8d%0D%0A%09dec%20r8d%0D%0A%09xor%20r9d,%20r9d%0D%0A%09dec%20r9d%0D%0A%09xor%20r10d,%20r10d%0D%0A%09dec%20r10d%0D%0A%09xor%20r11d,%20r11d%0D%0A%09dec%20r11d%0D%0A%09xor%20r12d,%20r12d%0D%0A%09dec%20r12d%0D%0A%09xor%20r13d,%20r13d%0D%0A%09dec%20r13d%0D%0A%09xor%20r14d,%20r14d%0D%0A%09dec%20r14d%0D%0A%09xor%20r15d,%20r15d%0D%0A%09dec%20r15d%0D%0A%09dec%20ecx%0D%0A%09jge%20.test6&amp;syntax=NASM&amp;uArchs=SKL&amp;tools=uiCA&amp;alignment=0&amp;uiCAHtmlOptions=traceTable&amp;uiCAHtmlOptions=graph" rel="nofollow noreferrer">https://uica.uops.info/?code=...</a></td>
</tr>
<tr>
<td>g2b</td>
<td>17.00</td>
<td><a href="https://uica.uops.info/?code=.test2:%0D%0A%09times%2032%20nop%0D%0A%09xor%20eax,%20eax%0D%0A%09dec%20rax%09%0D%0A%09xor%20ebx,%20ebx%0D%0A%09dec%20rbx%0D%0A%09xor%20edx,%20edx%0D%0A%09dec%20rdx%0D%0A%09xor%20edi,%20edi%0D%0A%09dec%20rdi%0D%0A%09xor%20esi,%20esi%0D%0A%09dec%20rsi%0D%0A%09xor%20r8d,%20r8d%0D%0A%09dec%20r8%0D%0A%09xor%20r9d,%20r9d%0D%0A%09dec%20r9%0D%0A%09xor%20r10d,%20r10d%0D%0A%09dec%20r10%0D%0A%09xor%20r11d,%20r11d%0D%0A%09dec%20r11%0D%0A%09xor%20r12d,%20r12d%0D%0A%09dec%20r12%0D%0A%09xor%20r13d,%20r13d%0D%0A%09dec%20r13%0D%0A%09xor%20r14d,%20r14d%0D%0A%09dec%20r14%0D%0A%09xor%20r15d,%20r15d%0D%0A%09dec%20r15%0D%0A%09dec%20ecx%0D%0A%09jge%20.test2&amp;syntax=NASM&amp;uArchs=SKL&amp;tools=uiCA&amp;alignment=0&amp;uiCAHtmlOptions=traceTable&amp;uiCAHtmlOptions=graph" rel="nofollow noreferrer">https://uica.uops.info/?code=...</a></td>
</tr>
<tr>
<td>g3a</td>
<td>17.00</td>
<td><a href="https://uica.uops.info/?code=.test0:%0D%0A%09times%2032%20nop%0D%0A%09xor%20ebx,ebx%0D%0A%09lea%20eax,%5Brbx-1%5D%0D%0A%09xor%20ebx,ebx%0D%0A%09lea%20edx,%5Brbx-1%5D%0D%0A%09xor%20ebx,ebx%0D%0A%09lea%20edi,%5Brbx-1%5D%0D%0A%09xor%20ebx,ebx%0D%0A%09lea%20esi,%5Brbx-1%5D%0D%0A%09xor%20ebx,ebx%0D%0A%09lea%20eax,%5Brbx-1%5D%0D%0A%09xor%20ebx,ebx%0D%0A%09lea%20r8d,%5Brbx-1%5D%0D%0A%09xor%20ebx,ebx%0D%0A%09lea%20r9d,%5Brbx-1%5D%0D%0A%09xor%20ebx,ebx%0D%0A%09lea%20r10d,%5Brbx-1%5D%0D%0A%09xor%20ebx,ebx%0D%0A%09lea%20r11d,%5Brbx-1%5D%0D%0A%09xor%20ebx,ebx%0D%0A%09lea%20r12d,%5Brbx-1%5D%0D%0A%09xor%20ebx,ebx%0D%0A%09lea%20r13d,%5Brbx-1%5D%0D%0A%09xor%20ebx,ebx%0D%0A%09lea%20r14d,%5Brbx-1%5D%0D%0A%09xor%20ebx,ebx%0D%0A%09lea%20r15d,%5Brbx-1%5D%0D%0A%0D%0A%09dec%20ecx%0D%0A%09jge%20.test0&amp;syntax=NASM&amp;uArchs=SKL&amp;tools=uiCA&amp;alignment=0&amp;uiCAHtmlOptions=traceTable&amp;uiCAHtmlOptions=graph" rel="nofollow noreferrer">https://uica.uops.info/?code=...</a></td>
</tr>
<tr>
<td>g3b</td>
<td>18.00</td>
<td><a href="https://uica.uops.info/?code=.test00:%0D%0A%09times%2032%20nop%0D%0A%09xor%20ebx,ebx%0D%0A%09lea%20rax,%5Brbx-1%5D%0D%0A%09xor%20ebx,ebx%0D%0A%09lea%20rdx,%5Brbx-1%5D%0D%0A%09xor%20ebx,ebx%0D%0A%09lea%20rdi,%5Brbx-1%5D%0D%0A%09xor%20ebx,ebx%0D%0A%09lea%20rsi,%5Brbx-1%5D%0D%0A%09xor%20ebx,ebx%0D%0A%09lea%20rax,%5Brbx-1%5D%0D%0A%09xor%20ebx,ebx%0D%0A%09lea%20r8,%5Brbx-1%5D%0D%0A%09xor%20ebx,ebx%0D%0A%09lea%20r9,%5Brbx-1%5D%0D%0A%09xor%20ebx,ebx%0D%0A%09lea%20r10,%5Brbx-1%5D%0D%0A%09xor%20ebx,ebx%0D%0A%09lea%20r11,%5Brbx-1%5D%0D%0A%09xor%20ebx,ebx%0D%0A%09lea%20r12,%5Brbx-1%5D%0D%0A%09xor%20ebx,ebx%0D%0A%09lea%20r13,%5Brbx-1%5D%0D%0A%09xor%20ebx,ebx%0D%0A%09lea%20r14,%5Brbx-1%5D%0D%0A%09xor%20ebx,ebx%0D%0A%09lea%20r15,%5Brbx-1%5D%0D%0A%0D%0A%09dec%20ecx%0D%0A%09jge%20.test00&amp;syntax=NASM&amp;uArchs=SKL&amp;tools=uiCA&amp;alignment=0&amp;uiCAHtmlOptions=traceTable&amp;uiCAHtmlOptions=graph" rel="nofollow noreferrer">https://uica.uops.info/?code=...</a></td>
</tr>
<tr>
<td>g4a</td>
<td>12.00</td>
<td><a href="https://uica.uops.info/?code=.test5:%0D%0A%09times%2032%20nop%0D%0A%09or%20eax,-1%0D%0A%09or%20ebx,-1%0D%0A%09%3Bmov%20ecx,-1%0D%0A%09or%20edx,-1%0D%0A%09or%20edi,-1%0D%0A%09or%20esi,-1%0D%0A%09or%20r8d,-1%0D%0A%09or%20r9d,-1%0D%0A%09or%20r10d,-1%0D%0A%09or%20r11d,-1%0D%0A%09or%20r12d,-1%0D%0A%09or%20r13d,-1%0D%0A%09or%20r14d,-1%0D%0A%09or%20r15d,-1%0D%0A%0D%0A%09dec%20ecx%0D%0A%09jge%20.test5&amp;syntax=NASM&amp;uArchs=SKL&amp;tools=uiCA&amp;alignment=0&amp;uiCAHtmlOptions=traceTable&amp;uiCAHtmlOptions=graph" rel="nofollow noreferrer">https://uica.uops.info/?code=...</a></td>
</tr>
<tr>
<td>g4b</td>
<td>12.00</td>
<td><a href="https://uica.uops.info/?code=.test1:%0D%0A%09times%2032%20nop%0D%0A%09or%20rax,-1%0D%0A%09or%20rbx,-1%0D%0A%09%3Bmov%20ecx,-1%0D%0A%09or%20rdx,-1%0D%0A%09or%20rdi,-1%0D%0A%09or%20rsi,-1%0D%0A%09or%20r8,-1%0D%0A%09or%20r9,-1%0D%0A%09or%20r10,-1%0D%0A%09or%20r11,-1%0D%0A%09or%20r12,-1%0D%0A%09or%20r13,-1%0D%0A%09or%20r14,-1%0D%0A%09or%20r15,-1%0D%0A%0D%0A%09dec%20ecx%0D%0A%09jge%20.test1&amp;syntax=NASM&amp;uArchs=SKL&amp;tools=uiCA&amp;alignment=0&amp;uiCAHtmlOptions=traceTable&amp;uiCAHtmlOptions=graph" rel="nofollow noreferrer">https://uica.uops.info/?code=...</a></td>
</tr>
</tbody>
</table>
</div>
<p>The trace table that uiCA generates provides some insights into how the code is executed. For g1a, for example, it generates the following trace:
<a href="https://i.stack.imgur.com/GI1K2.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/GI1K2.png" alt="Trace for g1a" /></a></p>
<p>You can see that for the 32 nops, the predecoder requires 8 cycles, and for the remaining instructions, it requires 5 cycles, which together corresponds to the 13 cycles that you measured.</p>
<p>You may notice that in some cycles, only a small number of instructions is predecoded; for example, in the fourth cycle, only one instruction is predecoded. This is because the predecoder works on aligned 16-byte blocks, and it can handle at most five instructions per cycle (note that some sources incorrectly claim that it can handle 6 instructions per cycle). You can find more details on the predecoder, for example how it handles instructions that cross a 16-byte boundary, in <a href="https://arxiv.org/pdf/2107.14210.pdf" rel="nofollow noreferrer">this paper</a>.</p>
<p>If you compare this trace with the trace for g1b,
<a href="https://i.stack.imgur.com/NFcW0.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/NFcW0.png" alt="enter image description here" /></a>
you can see that the instructions after the nops now require 6 instead of 5 cycles to be predecoded, which is because several of the instructions in g1b are longer than the corresponding ones in g1a.</p>
Do 32-bit and 64-bit registers cause differences in CPU micro architecture?
<p>I am trying to compare the methods mentioned by Peter Cordes in <a href="https://stackoverflow.com/a/45113467/17187836">his answer</a> to the question that 'set all bits in CPU register to 1'.</p>
<p>Therefore, I write a benchmark to set all 13 registers to all bits 1 except <code>e/rsp</code>, <code>e/rbp</code>, and <code>e/rcx</code>.</p>
<p>The code is like below. <code>times 32 nop</code> is used to avoid DSB and LSD influence.</p>
<pre><code>mov ecx, 100000000
Align 32
.test3:
    times 32 nop
    mov rax,-1
    mov rbx,-1
    ;mov ecx,-1
    mov rdx,-1
    mov rdi,-1
    mov rsi,-1
    mov r8,-1
    mov r9,-1
    mov r10,-1
    mov r11,-1
    mov r12,-1
    mov r13,-1
    mov r14,-1
    mov r15,-1

    dec ecx
    jge .test3
    jmp .out
</code></pre>
<p>I test below methods he mentioned, and <a href="https://github.com/moep0/relativeCode/tree/main/2021/1126" rel="nofollow noreferrer">Full code in here</a></p>
<pre><code>mov e/rax, -1                   

xor eax, eax        
dec e/rax               

xor ecx, ecx        
lea e/rax, [rcx-1]  

or e/rax, -1            
</code></pre>
<p>To make this question more concise, I will use <code>group1 a (g1a)</code> to replace <code>mov eax,-1</code> in the below tables.</p>
<div class="s-table-container">
<table class="s-table">
<thead>
<tr>
<th>number</th>
<th>pattern</th>
<th>test number</th>
</tr>
</thead>
<tbody>
<tr>
<td>group1 a</td>
<td>mov eax,-1</td>
<td>test 7</td>
</tr>
<tr>
<td>group1 b</td>
<td>mov rax,-1</td>
<td>test3</td>
</tr>
<tr>
<td>group2 a</td>
<td>xor eax, eax / dec eax</td>
<td>test6</td>
</tr>
<tr>
<td>group2 b</td>
<td>xor eax, eax / dec rax</td>
<td>test2</td>
</tr>
<tr>
<td>group3 a</td>
<td>xor ecx, ecx / lea eax, [rcx-1]</td>
<td>test0</td>
</tr>
<tr>
<td>group3 b</td>
<td>xor ecx, ecx / lea rax, [rcx-1]</td>
<td>test-1(test00)</td>
</tr>
<tr>
<td>group4 a</td>
<td>or eax,-1</td>
<td>test5</td>
</tr>
<tr>
<td>group4 b</td>
<td>or rax,-1</td>
<td>test1</td>
</tr>
</tbody>
</table>
</div>
<p>The table below shows that from group 1 to group 3, when using 64 bit registers, there is 1 more cycle per loop.</p>
<p>The IDQ_UOPS_NOT_DELIVERED also increases, which may explain the growing number of cycles. <strong>But can this explain the exact 1 more cycle per loop?</strong></p>
<div class="s-table-container">
<table class="s-table">
<thead>
<tr>
<th></th>
<th>cycles</th>
<th>MITE cycles(r1002479)</th>
<th>MITE 4uops cycles (r4002479)</th>
<th>IDQ UOPS NOT DELIVERED(r19c)</th>
</tr>
</thead>
<tbody>
<tr>
<td>g1a</td>
<td>1,300,903,705</td>
<td>1,300,104,496</td>
<td>800,055,137</td>
<td>601,487,115</td>
</tr>
<tr>
<td>g1b</td>
<td>1,400,852,931</td>
<td>1,400,092,325</td>
<td>800,049,313</td>
<td>1,001,524,712</td>
</tr>
<tr>
<td>g2a</td>
<td>1,600,920,156</td>
<td>1,600,113,480</td>
<td>1,300,061,359</td>
<td>501,522,554</td>
</tr>
<tr>
<td>g2b</td>
<td>1,700,834,769</td>
<td>1,700,108,688</td>
<td>1,300,057,576</td>
<td>901,467,008</td>
</tr>
<tr>
<td>g3a</td>
<td>1,701,971,425</td>
<td>1,700,093,298</td>
<td>1,300,111,482</td>
<td>902,327,493</td>
</tr>
<tr>
<td>g3b</td>
<td>1,800,891,861</td>
<td>1,800,110,096</td>
<td>1,300,059,338</td>
<td>1,301,497,001</td>
</tr>
<tr>
<td>g4a</td>
<td>1,201,164,208</td>
<td>1,200,122,275</td>
<td>1,100,049,081</td>
<td>201,592,292</td>
</tr>
<tr>
<td>g4b</td>
<td>1,200,553,577</td>
<td>1,200,074,422</td>
<td>1,100,031,729</td>
<td>200,772,985</td>
</tr>
</tbody>
</table>
</div>
<p>Besides, the port distribution of g2a and g2b is different, unlike g1a and g1b (g1a is the same as g1b in port distribution), or g3a and g3b.</p>
<p><strong>And if I comment <code>times 32 nop</code>, this phenomenon disappears. Is it related to MITE?</strong></p>
<div class="s-table-container">
<table class="s-table">
<thead>
<tr>
<th></th>
<th>p0</th>
<th>p1</th>
<th>p2</th>
<th>p3</th>
<th>p4</th>
<th>p5</th>
<th>p6</th>
<th>p7</th>
</tr>
</thead>
<tbody>
<tr>
<td>g1a</td>
<td>299,868,019</td>
<td>300,014,657</td>
<td>5,925</td>
<td>7,794</td>
<td>16,589</td>
<td>300,279,232</td>
<td>499,885,294</td>
<td>7,242</td>
</tr>
<tr>
<td>g1b</td>
<td>299,935,968</td>
<td>300,085,089</td>
<td>6,622</td>
<td>8,758</td>
<td>18,842</td>
<td>299,935,445</td>
<td>500,426,436</td>
<td>7,336</td>
</tr>
<tr>
<td>g2a</td>
<td>299,800,192</td>
<td>299,758,460</td>
<td>7,461</td>
<td>9,635</td>
<td>20,622</td>
<td>399,836,486</td>
<td>400,312,354</td>
<td>8,446</td>
</tr>
<tr>
<td>g2b</td>
<td>200,047,079</td>
<td>200,203,026</td>
<td>7,899</td>
<td>9,967</td>
<td>21,539</td>
<td>500,542,313</td>
<td>500,296,034</td>
<td>9,635</td>
</tr>
<tr>
<td>g3a</td>
<td>36,568</td>
<td>550,860,773</td>
<td>7,784</td>
<td>10,147</td>
<td>22,538</td>
<td>749,063,082</td>
<td>99,856,623</td>
<td>9,767</td>
</tr>
<tr>
<td>g3b</td>
<td>36,858</td>
<td>599,960,197</td>
<td>8,232</td>
<td>10,763</td>
<td>23,086</td>
<td>700,499,893</td>
<td>100,078,368</td>
<td>9,513</td>
</tr>
<tr>
<td>g4a</td>
<td>200,142,036</td>
<td>300,600,535</td>
<td>5,383</td>
<td>6,705</td>
<td>15,344</td>
<td>400,045,302</td>
<td>500,364,377</td>
<td>6,802</td>
</tr>
<tr>
<td>g4b</td>
<td>200,224,703</td>
<td>300,284,609</td>
<td>5,464</td>
<td>7,031</td>
<td>15,817</td>
<td>400,047,050</td>
<td>499,467,546</td>
<td>6,746</td>
</tr>
</tbody>
</table>
</div>
<p>Environment: intel i7-10700, ubuntu 20.04, and NASM 2.14.02.</p>
<p><em>It is a little bit hard for me to explain this in English. Please comment if the description is unclear.</em></p>