<p>There is single (sliced) L3 cache in single-socket chip, and several L2 caches (one per real physical core).
L3 cache caches data in segments of size of 64 bytes (cache lines), and there is special <a href="https://en.wikipedia.org/wiki/Cache_coherence" rel="noreferrer">Cache coherence protocol</a> between L3 and different L2/L1 (and between several chips in the NUMA/ccNUMA multi-socket systems too); it tracks which cache line is actual, which is shared between several caches, which is just modified (and should be invalidated from other caches). Some of protocols (cache line possible states and state translation): <a href="https://en.wikipedia.org/wiki/MESI_protocol" rel="noreferrer">https://en.wikipedia.org/wiki/MESI_protocol</a>, <a href="https://en.wikipedia.org/wiki/MESIF_protocol" rel="noreferrer">https://en.wikipedia.org/wiki/MESIF_protocol</a>,  <a href="https://en.wikipedia.org/wiki/MOESI_protocol" rel="noreferrer">https://en.wikipedia.org/wiki/MOESI_protocol</a></p>

<p>In older chips (epoch of Core 2) cache coherence was <a href="https://en.wikipedia.org/wiki/Bus_snooping" rel="noreferrer">snooped</a> on shared bus, now it is checked with help of <a href="https://en.wikipedia.org/wiki/Directory-based_cache_coherence" rel="noreferrer">directory</a>.</p>

<p>In real life L3 is not just "single" but sliced into several slices, each of them having high-speed access ports. There is some method of selecting the slice based on physical address, which allow multicore system to do many accesses at every moment (each access will be directed by <a href="https://software.intel.com/en-us/forums/software-tuning-performance-optimization-platform-monitoring/topic/673649" rel="noreferrer">undocumented method</a> to some slice; when two cores uses same physical address, their accesses will be served by same slice or by slices which will do cache coherence protocol checks).
Information about L3 cache slices was reversed in several papers: </p>

<ul>
<li><a href="https://cmaurice.fr/pdf/raid15_maurice.pdf" rel="noreferrer">https://cmaurice.fr/pdf/raid15_maurice.pdf</a> Reverse Engineering Intel Last-Level Cache Complex Addressing Using Performance Counters</li>
<li><a href="https://eprint.iacr.org/2015/690.pdf" rel="noreferrer">https://eprint.iacr.org/2015/690.pdf</a> Systematic Reverse Engineering of Cache Slice Selection in Intel Processors</li>
<li><a href="https://arxiv.org/pdf/1508.03767.pdf" rel="noreferrer">https://arxiv.org/pdf/1508.03767.pdf</a> Cracking Intel Sandy Bridge’s Cache Hash Function</li>
</ul>

<p>With recent chips programmer has ability to partition the L3 cache between applications "Cache Allocation Technology" (v4 Family): <a href="https://software.intel.com/en-us/articles/introduction-to-cache-allocation-technology" rel="noreferrer">https://software.intel.com/en-us/articles/introduction-to-cache-allocation-technology</a>  <a href="https://software.intel.com/en-us/articles/introduction-to-code-and-data-prioritization-with-usage-models" rel="noreferrer">https://software.intel.com/en-us/articles/introduction-to-code-and-data-prioritization-with-usage-models</a> <a href="https://danluu.com/intel-cat/" rel="noreferrer">https://danluu.com/intel-cat/</a> <a href="https://lwn.net/Articles/659161/" rel="noreferrer">https://lwn.net/Articles/659161/</a></p>
How are the modern Intel CPU L3 caches organized?
<p>Given that CPUs are now multi-core and have their own L1/L2 caches, I was curious as to how the L3 cache is organized given that its shared by multiple cores. I would imagine that if we had, say, 4 cores, then the L3 cache would contain 4 pages worth of data, each page corresponding to the region of memory that a particular core is referencing. Assuming I'm somewhat correct, is that as far as it goes? It could, for example, divide each of these pages into sub-pages. This way when multiple threads run on the same core each thread may find their data in one of the sub-pages. I'm just coming up with this off the top of my head so I'm very interested in educating myself on what is really going on underneath the scenes. Can anyone share their insights or provide me with a link that will cure me of my ignorance? </p>

<p>Many thanks in advance.</p>