Latency and latch count minimization in wave steered circuits

TitleLatency and latch count minimization in wave steered circuits
Publication TypeConference Paper
Year of Publication2001
AuthorsSingh, A, Mukherjee, A, Marek-Sadowska, M
Conference NameDesign Automation Conference, 2001. Proceedings
Keywords0.25 micron, 500 MHz, binary decision diagrams, circuit layout CAD, CMOS logic circuits, CMOS technology, design methodology, flip-flops, high throughput circuits, integer linear programming, integer programming, integrated circuit layout, latch count minimization, layout friendly synthesized structures, linear programming, logic CAD, minimisation of switching nets, retiming, scheduling, signal arrival times, timing, wave steered circuits
AbstractWave steering is a new design methodology that realizes high throughput circuits by embedding layout friendly synthesized structures in silicon. Wave steered circuits inherently utilize latches in order to guarantee the correct signal arrival times at the inputs of these synthesized structures and maintain the high throughput of operation. In this paper, we show a method of reordering signals to achieve minimum circuit latency for wave steered circuits and propose an integer linear programming (ILP) formulation for scheduling and retiming these circuits to minimize the number of latches for minimum latency. Experimental results show that in 0.25 mu;m CMOS technology, as much as 33.2% reduction in latch count, at minimum latency, can be achieved over unoptimized wave steered circuits operating at 500 MHz.