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  3. FIssiki

    Can't Write to SPI Flash

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  6. Vector22

    Can't Write to SPI Flash

  11. Oskar STEPIEÑ

    Place:1108 in a XC6SLX16-CSG324

  12. mkarlsson

    Place:1108 in a XC6SLX16-CSG324

    Here is the problem - you take the signal from the button connected to pin C4 and use that as a clock for the ledst0 flip-flop. This is not how you use an FPGA. Pin C4 is not a clock input pin, which cause the error 1108 you see, and logic signals like btnl should not be used as a clock. FPGAs are intended to be used for synchronous logic designs where a large number of flip-flops are clocked with a common clock. In order to make this possible the clock is distributed to all the flip-flops in this clock domain using special clock buffers and clock networks. The source of the clock is typically coming from an input pin on the FPGA and only a select few pins can be used as clock input. The input clock can be used as is or can be feed to a clock management tile that has resources like PLLs and DCMs that allow you to create a clock with different clock frequency. The Nexys3 board has a 100 MHz clock input signal connected to pin V10 that can be used as system clock. This is what the Nexys3 manual states: Try this code instead: .ucf file: BTW, your switch might "bounce", so you might have to de-bounce the signal from the switch. See What is debouncing? Magnus
  13. Hello everyone,, I was wondering if anyone had any input, pro or con, on the Papilio FPGA dev boards. They look like good learning tools, with a decent hobbyist community. My goals: Learn the basics mobdro lucky patcher kodi about FPGAs - I'm starting from scratch (experience with PIC16/18 and ARM9, basic electronics, PC programming). Primary application: FPGA based ADS-B receiver/decoder. Other applications: DSP of other RF signals, maybe playing with graphics generation.
  14. Hello everyone,, This question has already been asked but not for a very long time. Given the long time since the last discussion, I would hazard a guess that both have had major improvements. To which I ask which is the best out of the two? I will be using the board as an introduction to FPGAs as I have developed a keen interest in them as of late. As a theoretical physicist I never really encountered any electronics but an FPGA programmer at work gave me a CPLD to play around with after spending a few months of learning electronics. As such I already know a little about VHDL and could probably shift to Verilog without much fuss. The project I am thinking of doing first is to make the FPGA into a logic analyser for other project testing. I know the Papilio has this feature as standard but given I want to make the project myself that doesn't really matter. What I want to know is, is the I/O routing on the Mojo good enough to allow the 100/200 MHz speeds the Papilio can reach? The Mojo is much easier to get hold of here in the UK whereas the Papilio would have to be imported. That being said the Papilio does have a bundle for everything to make it into a logic analyser (5V buffer boards and test clips) and I guess code which already works out of the box. PS: I would also appreciate any tips for getting a job in FPGA programming as a physicist given that the usual path would be for an electronics engineer. I am only a hobbyist yet but wouldn't mind having the option of my hobby becoming a career. I have already messed around with PICs and CPLDs with reasonable success.
  15. F6EEQ

    Driving small TFTs

    Seems nice, but I've been unable to open the link.... Which soft could open it?? Thanks Gerard.
  16. mistery

    FPGArduino - where FPGA meets Arduino - FER

    Great, than you ... We did lots of new stuff with FPGArduino, and recently we developed new version of our FPGA board that is supported by new opensource tools you can check few tutorials/presentation/samples here: Odysseus.pdf
  17. vhdlspain

    FPGArduino - where FPGA meets Arduino - FER

    Hello, Talking about FPGA and Arduino, here you can find a tutorial about connecting a FPGA to Arduino using I2C.
  18. F6EEQ

    HD44780 interface

    Hi, I'm back on Papilio and I would like ti interface with a LCD to be able to follow what is going on. Easy to do with PIC or ARDUINO, but not so much with FPGA. I browsed the web (FPGA4fun for instance or Hamsterworks) but did not find any usable tutorial. I do not wish to go with ZPuino or the like, but pure FPGA things. Playground did not provide any help on this matter either, although there is a LCD on the retro wing. Could some one help me? I'm not looking for a ready-to-go project ( butit could help) but rather some educated hints on how to proceed. Thanks in advance. Gerard.
  19. Oskar STEPIEÑ

    Place:1108 in a XC6SLX16-CSG324

    Hi, I´m making a emulatorfor an FPGA Spartan6 XC6SLX16-CSG324C (Its a Nexys 3 board). When I tried make something more complex than light an LED, I though the problem was mine. But, I tried make a simple program to know the issue. This program, a simple botton-led, I use the C4 pin and U16 pin. The problem is the C4, a button, does the next error. Alright, some good being, told me to use the solution of: 1- Change the button to other that works (Works fine, but... there only works 3 buttons from 6, and one is the RESET button) 2- Use the "NET "btnl" CLOCK_DEDICATED_ROUTE = FALSE;", this, doesn´t work fine in the board. I looking for any new solution that might work. I also have the original proyect that don´t have any of this issues, but it´s a bit strange. The code is the next: And the .ucf file: Any help would be apreciated.
  20. benediktsch

    DUO as SPI Slave

    Hello together, On my Duo Board I am using the Softcore on the FPGA as my Microcontroller. In the Design Lab there are several libaries available, also the SPI libarie. I need the DUO Board to work as a slave but in the libaries nothing like this seems to be implemented. Did someone already do this and can show me how it is done?
  21. Hello. I'm just starting to learn ISE with the Papilio Duo. My first step was to create a circuit to read & write 1 bit from the onboard SRAM. However, I've hit a wall that I can't understand how to work around and was hoping someome could helpme figure it out. Here is the circuit I have thus far (attached) - basically connected an 8bit IBUF and OBUF to the sram data lines and just all 0 to the address lines. However, it won't synthesize: It gives this error: ERROR:Xst:1850 - Unable to insert IOBUF on port <sram_data<0>> in unit <SRAMOutput> having KEEP_HIERARCHY constraint. There are feedbacks in other units. Searching the Xst forums suggests turning off the KEEP_HEIRARCHY constraint, but it is already off in the settings and I don't understand why it is an issue since I have no other components / levels. Any ideas greatly appreciated. Thanks.
  22. Hi all, just wanted to share this with the whole community: regards
  23. Ricky Yuu

    Could not load into board for both xilinx and zap

    Its okay I have found the solution, the USB itself holds an important role. Now, I want to test out where to upload for the ZAP IDE. I will update the progress here. Thank you.
  24. Ricky Yuu

    Computer doesn't recognize FPGA

    Hey, LambdaPi I have found the solution with the issue perhaps you should using the USB power jack that has cylindrical around the USB. I hope it will help you a little bit
  25. Ricky Yuu

    Computer doesn't recognize FPGA

    I also have similar problem.
  26. Hi, As the link of the video below, i have followed each steps as on the final steps on loading the ZAP i could not upload it, as first what is the board it is used as there's variety of papilio one 500k ( how can i differentiate it?) and the port of the COM of the ZAP IDE does not show up. i could not upload into the board has been installed and un-installed papilio loader and ZAP IDE. I could not find the solution and been running this for two weeks. I am using papilo one 500k. Currently my papilio loader could not open. Could you please pointed out my mistakes in this case, such as if i don't download any necessary software beside Xilinx ISE, ZAP IDE and papilio loader. I am current;y using window 7 for this project. ( thank you very much. Ricky
  27. RErik

    DesignLab Malware?

    Hi, I downloaded the latest version of DesignLab (version 1.0.8) but my AV (Avast) reports it as containing FileRepMalware. I'm pretty sure this is a false positive but can anyone confirm either way? Thanks.
  28. Gregg

    Newbie Programming 3 Questions

    Bnusbick, Many thanks for the pointer. I was wondering HOW I flash the SPI and you've answered that question. I want to move to the 2.8 loader as soon as I can.
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