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  3. please help me to go through the operation of ddr in zybo z7 clg400 , meanwhile also explain me the process for operation of audio codec in and out.
  4. Szia @attila, You never fail to amaze me what WaveForms and Analog Discovery can do! Thank you again!
  5. Floorplanning is where you start before designing a new board. Once you've assigned pins and created a PCB your options for meeting timing for a particularly complex, dense, and high clock rate design are limited. Of course you will need to have a reasonably 'close to final version' of your FPGA design to start with so that the tools can select the best pin locations. For a general purpose development board like the one you are using only a few interfaces need to be 'optimized' for speed; and of course the speed grade of the parts on the board have a large impact on limiting the performance of any design. It is not always possible to select an arbitrary clock rate for any application for a particular board and always meet timing. On the other hand it's easy to create a design that doesn't have a chance to operate at a desired clock rate when a better conceived design might. Providing the tools with good guidance in the form of constraints is often the key to achieving a particular performance goal, though don't expect Vivado to turn a poor design into a greate design.
  6. Szia @Andras The UART is not suitable for RGB LED control. You can use a custom Patterns signal and script like this to build the data sequence for WS2812 RGB LEDs. Here you have the project: WS2812.dwf3work The default Analog Discovery configuration allocates 1k samples for each Patterns channel with this you can control 14 LED array (1024/24/3). With the 4th AD device configuration you will have 16k samples and can control 227 LEDs. With Digital Discovery 32k 455 LEDs... The supported frequencies are positive integer divisions of 100MHz base frequency: 100MHz, 50M, 33.3M, ... ~3.226M, 3.125M ...
  7. revathi


    Hi @jpeyron, I have noticed one thing today, If I reduce the frequency , the ADC code gets increases like this. But its really look no meaning how it happens, why there is a indirect proportional to frequency and voltage. It may be due to any anti aliasing filter effects. I don,t know exactly. and still am not clear in Vn offset, I would like you to notice what I realized from the manual UG480. Kindly refer the figure below.
  8. Hi, I'm trying to implement a custom protocol for NeoPixel LED arrays using a script. I need to represent the 0 and 1 data bits as signals of 0.4us high + 0.85us low and 0.8us high + 0.45us low respectively. I implemented the custom protocol with a script already, the data pulse widths look alright and I thought I could use UART and its Protocol.UART.Send(uartMessage,true) method, but I had to realize that I can't disable UART's Start bit so the receiver will misunderstand my data. Is there a way to disable the Start bit in the Digital Protocol? Also, when I was investigating the bus, I used the Logic Analyzer and I found something interesting: when I tried to set the rate to 3.2 MHz it always jumped back to 3.125 MHz. Is this normal? Thanks, Andras
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  10. Hello! @jpeyron Dir "jpeyron" there is a picture in your answer of block design for Zynq ("hello world" generate example). But you wrote, that you used vivado 2018.3. I use vivado 2017.4, when i connect block like in your picture and start "implementation" - all be ok. When start "generate bit stream" - i get error. Could you give more pictures that explain how to edit properties of each blocks of that (Zynq core, AXI interconnect, GPIO, proc reset) ???
  11. Hi, reading between the lines of your post, you're just "stepping up" one level in FPGA design. I don't do long answers but here's my pick on the "important stuff" - Before, take one step back from the timing report and fix asynchronous inputs and outputs (e.g. LEDs and switches). Throw in a bunch of extra registers, or even "false-path" them. The problem (assuming this "beginner mistake") is that the design tries to sample them at the high clock rate. Which creates a near-impossible problem. Don't move further before this is understood, fixed and verified. - speaking of "verified": Read the detailed timing analysis and understand it. It'll take a few working hours to make sense of it but this is where a large part of "serious" design work happens. - Once the obvious problems are fixed, I need to understand what is the so-called "critical path" in the design and improve it. For a feedforward-style design (no feedback loops) this can be systematically done by inserting delay registers. The output is generated e.g. one clock cycle later but the design is able to run at a higher clock so overall performance improves. - Don't worry about floorplanning yet (if ever) - this comes in when the "automatic" intelligence of the tools fails. But, they are very good. - Do not optimize on a P&R result that fails timing catastrophically (as in your example - there are almost 2000 paths that fail). It can lead into a "rabbit's hole" where you optimize non-critical paths (which is usually a bad idea for long-term maintenance) - You may adjust your coding style based on the observations, e.g. throw in extra registers where they will "probably" make sense (even if those paths don't show up in the timing analysis, the extra registers allow the tools to essentially disregard them in optimization to focus on what is important) - There are a few tricks like forcing redundant registers to remain separate. Example, I have a dozen identical blocks that run on a common, fast 32-bit system clock and are critical to timing. Step 1, I sample the clock into a 32-bit register at each block's input to relax timing, and step 2) I declare these register as DONT_TOUCH because the tools would otherwise notice they are logically equivalent and try to use one shared instance. This as an example. - For BRAMs and DSP blocks, check the documentation where extra registers are needed (that get absorbed into the BRAM or DSP using a dedicated hardware register). This is the only way to reach the device's specified memory or DSP performance. - Read the warnings. Many relate to timing, e.g. when the design forces a BRAM or DSP to bypass a hardware register. - Finally, 260 MHz on Artix is already much harder than 130 MHz (very generally speaking). Usually feasible but you need to pay attention to what you're doing and design for it (e.g. a Microblaze with the wrong settings will most likely not make it through timing). - You might also have a look at the options ("strategy") but don't expect any miracles on a bad design. Ooops, this almost qualifies as "long" answer ...
  12. Hi , I am using Arty 7 kit to implement my design. At first I used a clock frequency of 130 MHz, and the timing was "met" . Then I increased the clock the clock frequency to 260 MHz , but the timing constraints were "not met" . Pls, see the attached picture. I read about the issue and I found myself I have to do some floorplanning for my design. How to do floorplanning? What is the first step that I have to do with floorplanning ? Thanks.
  13. revathi


    Hi @jpeyron, I have attached my unipolar xadc output signal. Kindly check it off, the same deformation of voltage is there. Vp sinput signal is 0 to 1V, with offset of 500mV. Vn is from DAC B, default value is 0V. Freq from generator is 10Khz I don't understand why there is only 0.93V max and 0.3V minimum.
  14. revathi


    Hi @jpeyron, The sampling rate is 961.54 Kbps I have attached my SDK code, for bipolar mode. Kindly go through it. Recently i got the waveform with proper shape and smoothing, the only thing is there is some deformation of voltage in output. Fig 3: TEST SIGNAL FOR BIPOLAR MODE _NO OFFSET FIG 4: INPUT SIGNAL (VP) CONNECTION FROM AWG TO FPGA KIT FIG 5 : TEST SIGNAL TO UNIPOLAR MODE 1. Weather configuring the bipolar / unipolar mode in XADC WIZARD is enough? 2. Or I need to make some changes in sdk code 3. My assumption is am doing some error in SDK code I will attach my SDK code , I followed the Adam taylor and this attached link for coding and referred the xsysmon .h lab 3 4. The boxed thing in sdk code was added myself for bipolar and unipolar 5. Is it necessary to give the coding which i have given inside the text box? 6. Is it am doing any error in code ? sdk code.docx
  15. Hi @Carlos Posse, Based on the output from dmesg I can tell you that this is not an issue with drivers or software configurations. It's a hardware issue of some sort. I don't see any issues with your schematic. Have you tried using a different USB cable or connecting the cable to a different port on your PC? What are you loading for L8 and L9? Perhaps try loading shunts (0 ohm resistors) instead of ferrites or inductors and see if that makes any difference. Thanks, Michael
  16. mishu

    DDR3 input clock source

    Hi, I am wondering why is a 100 MHz clock present on the ARTY-S7 to be used for the DDR3 clocking, but not present in the ARTY-7. Why not use only a single 100 MHz clock source for ARTY-S7 as main clocking source? Or this was the idea from the beginning? I suppose in both cases with a SE 100 MHz clock source placed on a MRCC FPGA pin can be used to clock also the FPGA resources and the external DDR3 device. Cheers, Mishu
  17. Dear all, I'm looking to purchase a Labview license for personal/non-commercial use. Apparently, Labview 2014 Home edition should be the thing I need but I have some additional questions. Is 'Labview 2014 Home Edition' based on 'Labview 2014'? I know this question almost answers itself, but nevertheless... NI is currently at Labview 2019, so Labview 2014 is getting old and there are some nice-to-have/upgrades that LV19 offers. If you are a student, the 'Labview student edition' is maybe something to look at because it offers more addons. But, since you can not be a student for the rest of your life, I presume this is a yearly license. Is 'Labview student Edition' a one year license and is 'Labview 2014 Home Edition' a life-long license? Regards
  18. I need QSPI flash IP for my soft processor in my Genesys 2 FPGA. AXI Quad SPI IP provided by xilinx seems to support only Spansion S70FL01G command set. Is there a IP for Digilent Genesys 2 FPGAs spansion s25fl256xxxxxx0 flash memory?
  19. Hello, None of us here at Digilent have any experience porting material to risc-v material, but the Xilinx materials that we have on the Digilent GitHub for the PmodSF3 is based off of the Arduino styled material for the SF3 (link to PmodSF3 Resource Center), so you might look there for easier to interpret material. I'm sorry we couldn't be of more help. Thanks, JColvin
  20. Hi @Schuette, Please attach screen shot of your block design along with your project settings. Did you run block automation prior to trying to add the additional clock? best regards, Jon
  21. jpeyron


    Hi @revathi, What is the Sample rate of the XADC. Please attach your SDK Code. best regards, Jon
  22. Hi @Tim S., It is good to hear that you you were able to over come this issue. Thank you for sharing what you found about the AXI4 and the AXI Stream. best regards, Jon
  23. @herve, There's an option for Vivado to create a ".bin" file. Copy this directly to your flash device, starting with the first byte (unless you use warmboot, etc.), and you should be there. Don't forget that you might also need to adjust the configuration load options as well. Dan
  24. Tim S.

    Zybo Z7-20 audio interrupt

    Hi @jpeyron, I have examined some of the d_axi_i2s_audio Digilent IP Core sources. It appears that the control of the fifo_4 and fifo_32 fifo instances might be dependent on the AXI4 Stream and AXI4 Lite all running on the same clock. I had attempted to run the AXI4 Lite at 50 MHz and the AXI4 Stream run at a matching-phase 100 MHz. Best I can tell from the STATUS register is that the FIFOs fill with data and then are not dequeued. If I utilize a second M_GP (M_GP1) on the Zynq 7 Processing System and execute it at 100 MHz instead of 50 MHz; and interconnect the Audio DMA cores all at the same 100 MHz; then the audio I2S functions according to the Audio DMA example. Best regards, Tim
  25. I am trying to use my Zybo Z7-20 board with the Pmod CAN. With the help of Getting Started with Digilent Pmod IPs I added the Pmod CAN IP to my Zybo Z7-20 base design. When I try to add a 100MHz clock to ths PS configuration, I always got an error: How can I make a 100MHz clock available for the Pmod CAN with a Zybo Z7-20 PS?
  26. Hi, you might look at the open-source xc3sprog utility, it shows how it's done. Nevermind the name, it works also with 7 series with minor modifications (such as IDCODE and flash ID). I remember there is some header in the .bit file that is quite obviously for documentation purposes (open in text editor). But then, AFAIK it does no harm since the FPGA looks for some "magic" 32-bit word to recognize the start of the binary block. That is at least for JTAG-based upload (not sure about flash, I guess it's the same but I don't know). You might have a quick look into the configuration guide if it says anything about preparing a bitstream for flash.
  27. Is it possible to write a VERILOG / VHDL code to download the programming file (fpga bitstream) to the hardware device (for example an SPI flash memory)? I'm asking this, because I would like to transfer a bit stream into a spi flash memory, which will then be mounted on an fpga card for boot and configuration. I have already written a few lines of code to write, read, and erase the contents of the 32 MB NOR flash memory (PMODSF3). I tested my code and it works without problems! However, how to read the bitstream, before writing it to the flash memory? Do I only need to transfer the bitstream into flash memory or do I have to add a header and a footer in the memory before and after the transfer of the bitstream file? Have you ever worked on a similar project? N.B: I am using a Xilinx FPGA (Artix-7) on a customized board. I would like to find an alternative solution to the Xilinx hardware manager to program the SPI flash. Any ideas, feedbacks and suggestions are welcomed! Thank you Hervé
  28. Hello, I want to use Digilent PMODSF3 with self-designed risc-v core & SoC, therefore I need a version of PMODSF3 driver & tests that can be runned on gnu toolchain but not on Xilinx SDK. Could you please provide me some instruction on how to port the api? Thank you very much! Yun-Chen Lo, Tsing Hua University, Taiwan
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