What makes an embedded design low power?

Wednesday, March 2nd, 2011 by Robert Cravotta







9 Responses to “What makes an embedded design low power?”

  1. Jon Titus says:

    I don’t mean to seem flippant, but if a product meets the buyer’s expectation for low power, then it’s low power. Some people will want micro-watt-power devices and others will be satisfied with milliwatt-power devices. A lot depends on the end use and the requirements.

  2. T.Z. @ LI says:

    This is a very interesting discussion. Few years ago i have been working for a known company developing DSP’s to support Wi-Fi functionality in cell phones, and I remember this gloomy day when the company lost a bid for supplying a potential customer with ten of millions of chips because of … power consumption. If my memory does not mislead me, it was all about few mW that made the difference with competitors.
    I am not a hardware guy, however I can tell you that software will likely make the big difference: choice of relevant OS, programming language, design of efficient algorithms, hardware management, these are few factors that have direct impact on your smartphone power consumption or your terabytes router. High power consumption means high direct and indirect operation costs ( cooling down your network/telecom platforms costs a lot of money ), shorter life cycle, higher probability of failures etc…

  3. T.Z. @ LI says:

    Processors tend to consume in the watt range when running, but microwatts when idle or sleeping (depends on how fine control you have over clocks and peripherals).

    There is no free lunch as far as CPU time – there are better or worse, but you will need a certain number of joules per operation.

    So I would define it as conservation. Some thoughts:

    Use as close to nothing as possible when not doing anything.

    Sleep and Wake will require special attention. Maybe even hibernate (save state to lower powered NV and shut that part off).

    Refactor or design to avoid power-hungry forms, e.g. divides might take a lot more than a repeated subtract, fixed point over floating point, a targeted parser instead of sscanf.

    High-performance/efficiency. IIRC, the power consumption goes up with the SQUARE of the clock speed. So if you can run at 1Mhz at 50% instead of 2Mhz at 25%, drop the clock speed.

    • Dan says:

      @T.Z. — “IIRC, the power consumption goes up with the SQUARE of the clock speed”

      I think you’re crossing a couple of concepts here. Actually, power goes up with the square of the VOLTAGE.

      You’re probably coupling this to the fact that in reality, as the clock speed rises, the voltage usually needs to as well. But the increased power consumption is mostly due to the voltage increase.

      The main reason for this is that these digital circuits really have quite a bit of “analog” to them if you dig deeper. There is capacitance lurking in all those gates & transistors. The capacitance affects how long it takes to “switch” the transistors on & off. In order to switch faster, you need a higher voltage. Thus as you increase your clock rate, you generally need to increase your voltage.

      Back in the day, processors ran at 5V. Then they dropped down to 3.3V. Then 1.8V. Then 1.5V, then 1.2V… now I believe there are processors running at 0.9V.

      You’ll notice in a lot of processor data books, there is a graph which shows a graph of required core voltage vs. clock rate.

      I’ve worked on quite a few systems where the power supply was more-or-less fixed, and that in turn dictated the maximum processor clock speed – without more voltage, you just can’t switch the transistors fast enough.

  4. I agree that the term “low-power”, applied seemingly to all kinds of devices with different energy consumption specs, can be confusing. And unfortunately, with all the different ways that power numbers are measured and reported, it becomes all the more difficult to compare them with each other.
    The best way is to consider these platforms from the point of view of a particular application or class of applications. This will determine the required hardware and software feature-set and the approximate performance and specific interfacing needs that the embedded design has to meet.

    I suppose there could be two main criteria to consider when comparing low-power embedded designs – Capability and Practicability.

    Capability asks the question: What can this embedded platform do? What does the application running on this platform do and what features can it support? How effective is this solution for solving the problems of a particular application or application space?

    We may find that a μW device-based design might not be the best solution for a particular application as it may not completely address the application requirements due to performance limitations or may not support as many features as a mW-based design. In this case the mW device-based design may actually be the best low-power solution (compared to designs based on higher-power devices) for that application space. Alternatively we may find that we have two designs – both valid low-power designs for different classes of the same application space.

    Practicability ask the question: Is this a viable solution? Is it low-cost enough to be practical? Does it provide scope for future revisions/improvements? Is it flexible enough to be customized?

    Sometimes a design could be just ahead of its time in terms of cost of the technology and sometimes in the practicality of the solution. A μW device-based design might just be too expensive because the technology is yet not mature or because it needs too many extra components to match a mW device-based design – driving up cost and possibly total system power considerably. ASICs or devices with fixed data-path accelerators, by-far, can get you the lowest power consumption, but may not the most favored solution due to high costs for any changes to application feature-set or for customization of application for product differentiation. So, the lowest-power design may not be the best solution in these cases.

  5. S.B. @ LI says:

    Hi Robert,

    Personally, I am not at all involved in the domain of low-power. However, I would be very curious to see what people think, so I am very much surprised by the almost complete absence of comments here!

    If I were to answer the question of what is “low power” myself, I would intuitively suggest that a device be considered as low power if its average (alternatively maximum) consumption per operation is lower than a certain threshold compared to its nominal power supply. Taking the ratio here moves you from the domain of absolute consumption values to relative ones and, potentially, allows to fix a unique threshold.


  6. T.Z. @ LI says:

    S., right, not too much comments. I have by myself a limited experience in that field. From software perspective interacting with chips, the less inquiries you send to a FPGA, the less interrupts you get from it to SW, the less power you consume.
    From a software perspective running on a CPU, it is up to the software engineer to design efficient algorithms, avoid overheads etc…
    At the end your competitors and customers will “tell” you if you are enough low power. I do not think there is an absolute number that can be defined for that.

  7. H.A. @ LI says:

    As per my understanding, low power can be achieved with the clever use of hardware and software.

    In hardware, each microcontroller have a lot of peripherals, and if the peripheral are not in use then also, some current leakage is there, that also consume power, so this leakage should be minimum. In Some Microcontroller, peripheral will go in sleep mode, if it is not in use, and after finishing the job, and try to save more power. And DSP processor also can be use only when required, else let it be in sleep mode

    And in software, programmers have to take care about the algorithms and the uses of the hardware.

  8. J.G. @ LI says:

    Low power is a relative term. There are processors that consume in the micro-watt or even nano-watt range. However these processors typically have very low horsepower and are really only suitable for very simple applications. As processors are required to perform more complex tasks and the number of peripherals climbs, the power requirement typically increase as well. Depending on the application(s), frequency and voltage scaling may offer a way to reduce average power consumption.

    While frequency scaling reduces the power consumption by spreading the power used over a longer period of time, voltage scaling offers a way to really save power when doing tasks that are not time critical. With a processor that offers voltage scaling, you can reduce the core voltage as you reduce the operating frequency. Being able to selectively power down peripherals when they are not in use is also an excellent way of conserving power.

    As I said at the start, low power is a relative term. That is, if a system typically requires say 5 watts and a competitor comes up with a similar system that only requires 4 watts, the new system is comparatively low power.

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