0. NSL outline


HDL(Hardware Description Language)
Computer language for hardware design that is used when ASIC and FPGA, etc. are designed
NSL(Next Synthesis Language)
Hardware Description Language based on the message driven.
Syntax that is described in accordance with syntax of NSL language
Bundle of minimum units that are described by NSL
Part that operates with one clock
Action statement
Element in a module, which represents action
Common action description
Part that always operates with every clock among the action descriptions except “procedure” and “function”
Atomic action
Minimum unit of action that is described in the action description part of a module
Proc (Procedure)
Processing that consolidates actions that are used repeatedly many times
Func (Function)
Bundle of processes that can be called from outside and inside of a module via a control terminal by consolidating action descriptions in a unit
In a submodule syntax, “substance” when a module to be lower is declared in a higher module
I/O structure element
Element that combines the signal to be input into module and the signal to be output from module
Data terminal
Signal line that inputs and outputs numerical value
Memory element that is used in an electronic circuit and HDL, etc. It is used to assist the operation, and store the value, etc.
It is made to save multiple data by arranging the registers.
Control terminal
Signal line to activate “function” that resides in a module
Internal structure element
Element that configures module itself such as “register” and “procedure”, etc.
Part that is put in {} in action description. It includes the kinds of “par”, “any”, “alt”, “if”, “seq”, etc., and each block operates separately.
Hierarchic structure
Structure that overlaps in stratified like the floor in a building. Achieving a hierarchic structure makes it easy to structure a large-scale system. Submodule syntax is used for NSL to achieve a hierarchic structure.
Block top level
Independent block that is not nested by any block
MSB/LSB (Most Significant Bit/Least Significant Bit)
As for NSL language, it assumes that the leftmost is MSB (Most Significant Bit), and the rightmost is LSB (Lest Significant Bit).
Compile, Compiling operation
It is indicated to generate a lower language source from NSL language source using NSL conversion engine. Or, its operation is indicated.

0-2.Basic structure

In this section, explains the basic system of NSL is explained.
Basic structure in the description of NSL consists of the system in Example 0.
(Hereafter, the syntax enclosed with <> in Reference may be omitted.)

<<Example 0. Basic structure of NSL>>
declare Module_name <interface> {
    <Parameter declaration list>
    <Declaration of I/O structure element list>
module Module_name {
    <Declaration of internal structure element list>
    <Action description list>
        - <Common action description part>
        - <Function description part>
        - <Procedure description part>

NSL consists of the “declare” syntax and the “module” syntax.


Though operator of NSL is basically compatible with Verilog HDL, a part and conditional operation of relational operations, and division are excluded.
The unique NSL operation includes sign extended arithmetic. Operator usable for NSL is listed in Table 0-1.
(Hereafter, the semicolon used in the table is used as a sign to delimit the syntax used in NSL from its meaning.)

<<Table 0-1.Operator>>
Bit Operation meaning Arithmetic operation meaning
Bit operation AND
Bit operation OR
Bit operation NOT
Bit operation EX-OR
Arithmetic addition
Arithmetic subtraction
Arithmetic multiplication
Relational operation meaning
Reduction operation meaning ==
Not equal
Greater than
Less than
Greater than or equal to
Less than or equal to
Reduction AND
Reduction OR
Reduction EX-OR
Logical operation meaning Other operations meaning
Logical NOT
Logical AND
Logical OR
if(condition) sigA else sigB
Signed extension
Unsigned extension
Bit clipping operation
Bit clipping operation
Bit connecting
Repeated operation
Conditional operation
Shift operation meaning
Right shift
Left shift

0-4.Priority of operator

The priority in Table 0-2 exists in the NSL operator.
When multiple operators are described in an expression of a sentence,
the operation is sequentially executed from the operator with higher priority.
“( )” is used to raise the priority of expression in an expression.

<<Table 0-2.Priority of operator>>
Priority Operator Meaning
Bit connecting
Repeated operation
Sign extension
Unsign extension
Reduction AND
Reduction OR
Reduction EX-OR
Bit operation NOT
Logical NOT
2 * Arithmetic multiplication
3 +
Arithmetic addition
Arithmetic subtraction
4 <<
Left shift
Right shift
5 <=
Less than or Equal to
Greater than or Equal to
Less than
Greater than
6 ==
Not Equal
7 &
Bit operation AND
Bit operation EX-OR
8 | Bit operation OR
9 && Logical AND
10 || Logical OR
if() … else … Conditional operation

0-5. “transfer” of value

The operation called “transfer” of a value and a signal is most frequently seen on designing a circuit.
“transfer” indicates it to pass a certain value and a certain signal to another signal wire.
“transfer” is executed by using the sign “=” in the following procedure.

Signal A = Value B

The “transfer” indicates an action that “value B is passed to signal A”.
In the above, value B is passed to signal A in the same clock as the transfer of the value.
As stated above, “transfer” is an action in which the right-hand side is passed to the left-hand side.

Next, it explains the case when a value is passed to a register.
The register is a memory element that is used in an electronic circuit, and HDL, etc.
When a value and a signal are transferred to a register,
the register memorizes the transferred value and signal one clock after the transfer.

To transfer a value and a signal to a register, it is executed by using “:=” as follows.

Register_A := Value_B

This transfer indicates that “value B is passed to register A”.
In this case, register A memorizes value B at the next clock of having transferred value B.

The transfer command is shown in the following Table 0-3.

<<Table 0-3.List of transfer command>>
Transfer command Meaning
transfer to signal
transfer to register

0-6.Notation of numerical value

Notation of numerical value in NSL has two kinds of Verilog HDL type and C language type.
Notation of Verilog HDL type describes as follows :


For example, 12 in decimal numbers is expressed by the binary numbers in 4-bit width as


Binary is abbreviated as “b”.
4-bit, 5 in decimal numbers is expressed as follows :


In this way,
it describes Binary number: b, Octal number: o,
Decimal number: d, and Hexadecimal number: h respectively in Verilog HDL type.

<<Table 0-4.Notation of numerical value in Verilog HDL type>>
Radix_Character Meaning
Binary number
Octal number
Decimal number
Hexadecimal number

And, it describes in C language type notation as follows :


For example, 8 in decimal number is expressed in binary number of 4-bit width as follows:


In this notation of C language type,
it describes Binary number: b, and Hexadecimal number:x respectively.

<<Table 0-5.Notation of numerical value in C language type>>
Radix_Character Meaning
Binary number
Hexadecimal number

Though “value” need not be matched to the bit width in Verilog HDL type, in C language
type, the bit width is decided by the width in “value” described.
For example, it is decided to 8 bits for 0×00, and 4 bits for 0b0000.
In addition, “_” (Underscore) can be used to represent Value. Underscore is disregarded when compiling. It can be used to raise the readability of numerical representation in multiple digits.

Example :
8′b01011010 -> 8′b0101_1010
32′hA9876543 -> 32′hA987_6543
0×12345678 -> 0x1234_5678

0-7.Comment out

Comment out in NSL is compatible with C language,
and two kinds of representations are permitted.

Single line comment describes as follows:

// Comment

Area comment:


Notes: Though single line comment can be described in an area comment,
the area comment cannot be nested.

0-8.Multiple declarations

In NSL, it can declare the multiple signal line, and internal structural element, etc. in a syntax.
The declaration indicates the multiple declarations by delimiting the declaration names
with “,”. The following description method is used to execute multiple declarations.

Declaration_command Declaration_name_A, declaration_name_B, declaration_name_C. … declaration_name_X

The elements possible for multiple declarations are shown in the following Table 6.

<<Table 0-6.The elements possible for multiple declarations>>
I/O structure element Declaration command
Data input terminal
Data output terminal
Data input and output terminal
Control input terminal
Control output terminal
Internal structure element Declaration command
Internal terminal
Control Internal terminal

0-9.About clock signal and reset signal

Verilog HDL and VHDL are a signal-oriented language that varies the behavior with a certain signal.
NSL, on the other hand is a language based on the message driven that
decides the operation by describing the behavior of a module first.
NSL automatically provides a synchronization signal for module,
and creates a module that operates with a single-phase or a multi-phase clock.
It also provides a reset signal for the circuit as well as the synchronization signal at the same time.
When it is not specified at all, the clock signal is automatically synthesized with the name of “m_clock”, and the reset signal with “p_reset”.
Both of the clock name and the signal name can be changed by a compilation option.

0-10.End of syntax

In NSL, an end of syntax is represented by semicolon “;”.
When a syntax that is a minimum unit of the description such as declaration of element, and description of operation, etc. is ended, the end is determined using the semicolon as follows.

Declaration of structure element ;
Description of atomic action ;

It is also possible to do multiple descriptions by separating with a semicolon,
however it is not recommended because the readability falls remarkably.