Network-on-Chip and Special Function Units (ongoing)

Network-on-Chip and Special Function Units

Contemporary computer architectures are increasingly using multiple computing cores. This decision is primarily driven by the fact that the total power consumption of the chip has a hard constraint. It is envisioned that in the future, we will have a very large number of heterogeneous cores on the same die.

This leads to two key problems. The first problem is to design a fast, power-efficient Network on Chip (NoC) to interconnect these cores. The second problem arises from an opportunity. With the large number of available cores, there is the opportunity to design special function units tuned for specific computational tasks. Our work addresses the first problem by using a source-synchronous ring-based NoC. The data in the rings is transmitted in a source-synchronous fashion, strobed off of an extreme high speed, low power ring-based standing-wave resonant clocking paradigm. Our results indicate a 4.5X improvement in bandwidth and about 7.5X improved contention free latency using this approach, compared to the best existing approach. Ongoing work includes exploring network topologies, and benchmarking the NoC against real and synthetic traffic.

To address the second problem, my group has developed special purpose units for computational tasks such as sorting, comparison of two numbers, logarithm and antilogarithm computation, cryptographic key generation and Boolean Satisfiability.

Publications, patents and artefacts: