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IEEE 802.11 WLAN - HDL Optimized Beacon Frame Receiver with Captured Data

This example shows a hardware friendly model that receives beacon frames in an 802.11 wireless local area network (WLAN) as described in [ 1 ]. For more information refer to the IEEE 802.11 WLAN - Beacon Frame Receiver with Captured Data example.


The IEEE 802.11 WLAN - Beacon Frame Receiver with Captured Data example shows the reception of beacon frames in an 802.11 based wireless local area network (WLAN). Three major modifications have been made to this example so that it generates efficient HDL code.

  • Streaming: The HDL optimized beacon frame receiver processes data in streaming mode. The captured framed-based real-world signal is streamed into the receiver front-end. The output of the receiver controller is then buffered and passed to the detector.

  • Fixed-point: The receiver front-end and the controller logic operate in fixed-point mode.

  • HDL optimized architecture: Several blocks have been redesigned using hardware efficient algorithms and architectures.

The beacon frame example consists of three main components: front end, receiver controller, and detector. The front end and the controller operate at a high rate in the receiver, so they have been optimized for HDL code generation in this example. The following sections describe the details of the modifications.

Receiver Front-End

The receiver front-end is composed of a matched-filter, AGC, and coarse frequency compensation. Modifications have been made to the frequency estimation algorithm [ 2 ] implemented in MATLAB Function block in the original beacon receiver model:

  • The auto correlation operation has been replaced by a simple smooth filter.

  • Then the angle function has been implemented using CORDIC [ 3 ] algorithm.

  • The detected phase offset is sent to NCO HDL Optimized block to generate a complex exponential signal that is used to correct the phase offset in the original signal.

The NCO HDL Optimized block provides hardware friendly options, maps the lookup table into a ROM, and provides a lookup table compression option to significantly reduce the lookup table size. To learn more about HDL support for HDL Optimized NCO block, refer to the documentationdocumentation.

Receiver Controller

The receiver controller finds the correlation between the phase offset corrected signal and synchronization signal. When the peak of the correlation is detected, the signal is delayed based on the peak position before despreading. Because of the large beacon frame size (2816 samples), implementing the correlator using either an FFT or a matched filter is not efficient in hardware. In addition, finding the maximum of a 2816-element vector is not hardware friendly. The correlation and despreading algorithm has been redesigned in this example. Despreading is performed before the correlation, aiming to reduce the filter size from 2816 to 128. Because the start of the beacon signal is unknown when performing the despreading early, 22 channels have been designed in the Despread_Matched Filter module, with each channel offsetting the adjacent channel by one sample. The maximum of the outputs of 22 filters is computed and the despread results from the channel that produces the maximum are selected to send to the Detector.

The downsample operation before the 22-channel matched filter allows the possibility of sharing resources across the FIR matched filters, as a way to balance the hardware speed and resource usage.

The despreaded signal is buffered in 128 symbol frames in the frame buffer before processed in the detector. The PLCP information was fed back to the receiver controller in the original beacon frame receiver to decide the length of payload to be collected. The maximal length of payload has been collected in this example to simplify the interface between the hardware and software components.

Results and Displays

When you run the simulation, it displays several scopes. The synchronization scope and the MPDU GUI are displayed in this section. You can refer to the IEEE 802.11 WLAN - Beacon Frame Receiver with Captured Data example for more information about the scopes.

HDL Code Generation

Pipeline registers (shown in green) have been added throughout the model to make sure the receiver front-end and the controller run at the expected speed. The HDL code generated from the receiver front-end and the controller were synthesized using Xilinx ISE on a Virtex6 (xc6vlx75t) FPGA, and the circuit ran at about 150 MHZ, which is sufficient to process the data in real time.


You can use the commands makehdl(subsystemname) and makehdltb(subsystemname) to generate HDL code and testbench for subsystems in HDLRx.




  2. M. Luise and R. Reggiannini, "Carrier frequency recovery in all-digital modems for burst-mode transmissions," IEEE Trans. Communications, pp. 1169-1178, Feb.-March-Apr. 1995.

  3. Ray Andraka, "A Survey of CORDIC Algorithms for FPGA Based Computers", 1998,ACM 0-89791-978-5/98/01

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