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Publication numberUS3644784 A
Publication typeGrant
Publication dateFeb 22, 1972
Filing dateApr 16, 1970
Priority dateApr 16, 1970
Also published asCA932051A1, DE2118222A1
Publication numberUS 3644784 A, US 3644784A, US-A-3644784, US3644784 A, US3644784A
InventorsDickey Marcus P, Mcintyre Donald C
Original AssigneeHoneywell Inc
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Solid-state indicator displays
US 3644784 A
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Description  (OCR text may contain errors)

0 llmted States Patent {151 3,644,784 Dickey et al. 1 Feb. 22, 1972 [54] SOLID-STATE INDICATOR DISPLAYS 3,343,155 9/1967 Pahlavan ..340/324 [72] Inventors: Marcus y, g p Donald C. 3,496,410 2/l970 Maclntyre ..3l5/ 169 McIntyre, Roseville, both of Minn. OTHER PUBLICATIONS Assigneei Honeywell -1 Minneapolis, Minn- Konnerth, Electroluminescent Display IBM Technical Disclo- [22] Filed: Apt 16 1970 1 sure Bulletin Vol. 8, No. l 1, April 1966 [21] Appl.N0.: 29,093 Primary Examiner.lohn Kominski AttorneyCharles J. Ungemach, Ronald T. Reiling and James A. Phillips [52] 0.8. Cl ..3l5/169, 315/132, 340/325 [51] It. Cl. ..I'I05b 33/00 [57 CT [58] Field of Search ..315/84.5,130132,

' 313/108 D; 340/324 325 378, 379 A display having blocks of display contrasting elements and 1 individual elements electrically connected in a matrix such [56] References Cited that two input signals to the matrix energize a number of elements in the form of a pointer which moves in accordance UNITED STATES PATENTS with the input Signals- 3,327,l63 6/1967 Blank ..315/169 5 Claims, 5 Drawing Figures YA: YAZ YAI YAO l l l l i I PATENIEBFEB22|912 3,644.784


SHEET M []F 4 sea TQ DEC MAL c NVERT R TENS O E s (ecu) AND DRIVERS BCD TO DECIMAL UNITS CONVERTERS uacm AND DISPLAY omvsns so Z-INPUT OR GATES INVENTORS MARCUS I? DICKEY DONALD C. MCINTYRE wm w ATTORNEY SOLID-STATE INDICATOR DISPLAYS BACKGROUND OF THE INVENTION Displays up to now have usually used electromechanical servomechanisms to position a pointer'to indicate a quantity upon the scale range displayed. This invention is a display using solid state display media, commanded to indicate quantity by means of digital words from a central computer. This display simulates the visual appearance of the conventional servomechanism displays.

SUMMARY A moving pointer which indicates quantity upon a scale is mechanized such that groups of three, or more, display media segments are activated to provide a contrasted pointer in response to a digital input signal, or signals, representing a quantity to be displayed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is the face of a display made up of two columns of display media segments;

FIG. 2 is an enlarged portion of the display of FIG. 1;

FIG. 3 is an electrical schematic showing how the solid state display media segments are interconnected in a matrix;

FIG. 4 is a schematic diagram illustrating a kind of logic which can be used to select the proper input signals to the matrix of FIG. 3; and,

FIG. 5 is a block diagram of the display.

DETAILED DESCRIPTION FIG. I is a display made up of two columns, A and B, of contrasting display media segments, such as LEDs (light-emitting diodes). FIG. 2 shows an enlarged portion of the display of FIG. I alongside some scale marks. A group of three segments, I0, 12, and 14 are activated (shown as crosshatched) to provide a contrasted pointer indicating the quantity represented by a scale mark 16.

In FIG. 2 the segments of column B are offset from those of column A such that a horizontal line, e.g., dashed line 18, drawn through the center of a segment in column B bisects the spacing between two adjacent segments in column A.

In FIG. 1 the columns A and B are electrically segregated into n blocks, referenced as XO through X(nl), and n+1 individual segments, referenced as ZO though Zn. Each block contains m segments in column A, referenced as YAO through YA(m-l), and ml segments in column B, referenced as YBI through YB(ml The n+1 individual segments Z0 through Zn are also referenced as YBO segments in column B. This particular display contains 2mn+l segments.

The segments of FIG. 1 are electrically connected in a matrix as shown in FIG. 3. By energizing one of m lines ref e enced as Y0 through Y(m1), one of n lines referenced as X0 through X(n-I), and, sometimes, one of the n+1 lines referenced as T0 through T a specific group of three segments (in this case the segments are shown as LEDs) can be activated to provide a contrasted pointer. For example, referring to block X2 in FIG. 1, to activate segments YA2, YB2, and YB3 a first positive voltage is applied to line Y2 and a second voltage, negative with respect to the first voltage, is applied to line X2. The voltage present on line Y2 is applied to the anodes of the YA2, YB2, and YB3 LEDs in each block X0 through X(nl) and the voltage present on line X2 is applied to the cathode of each LED in block X2. Consequently only the YAZ, YB2, and YB3 LED's in block X2 (labeled with the reference numerals 30, 32 and 34 respectively in FIG. 3) are activated an d will remain in that state until either one of the lines Y2, X2 is opened or if the differential voltage between lines Y2 and X2 is small enough to not cause display contrast or if the voltage on line X2 becomes more positive than that on line Y2 (back biasing the corresponding LED's).

Two additional examples will illustrate one of the particular advantages of the invention. To activate segments YA(m-l) another X(k+l), e.g., from block X0 to block X1, one of the individual segments Z(k+l), in this case Z1, must be addressed. The following Partial Truth Table illustrates this further.

Partial Truth Table I Line X Line Z Line Addressed Addressed Addressed W's- 5 Y(rri l) Z 2 required Y0 & required Y1 19 i Y X 2 Y(m2) E 2* I Y(m- I) X2 2 required Y0 & Z2 required Yl X3 Z3 required, optional This table indicates, for example, that if lines Y( m2) and XI are addressed (energized) line Z l need not necessarily be addressed, that is, the addressing of line Z1 in this case is not required but is optional. However if lines Y(ml) and m are addressed, line Z2 must necessarily be addressed, that is, the addressing of line Z2 in this case is required and is not optional. X-lines and Z-lines of the same number can be addressed with the same voltage in all cases except when the Y(m-l) line is addressed. When a Y(ml) line is addressed the number of the Z-line addressed is one unit higher than the corresponding X-line addressed. This is shown in the second row of entries in the above table and also in the eighth row of entries. This particular function can be accomplished with a number of conventional OR gates and logic, reducing the number of input lines tg the display to m lines, Y0 through Y(ml), and n lines, X0 through X(n-l). This is shown in detail in FIG. 4.

In FIG. 4 information representing a units digit and a tens digit to be displayed is present on line sets 50 and 52 rcspectively. The information is in a form called BCD (binary-coded decimal). Line sets 50 and 52 are connected to converters 54 and 56 respectively. These converters convert the incoming BCD information to straight decimal information. The outgoing decimal information from the converters is developed on one of 10 output lines (referenced 0-9) in each converter. FIG. 4 also includes a set of 10 transistor drivers 58, one driver for each output line of converter 54, and nine pairs of OR- gates 60. One of the OR gate pairs comprises OR-gates 62 and 64. OR-gates 62 and 64 are of the type that provide a low output signal if either one or both of the input signals are low. The output terminals of each pair of OR gates are connected to the input terminals of an AND gate. For example, the output leads of OR-gates 62 and 64 are connected to the input terminals of AND-gate 66. AND-gate 66 is of a type that provides a high output signal only if both of the input signals are low. The output of AND-gate 66 is inverted and amplified by amplifier 68 the output of which is applied to the Z2 line of the matrix of FIG. 3.

The operation of the circuits of FIG. 4 will be explained with a specific example. Assume the units digit to be displayed is a 9 and the tens digit to be displayed is a 1. Referring to the matrix of FIG. 3 this means that a positive voltage must be applied to line Y(m-l)=Y9 and relatively negative voltages must be applied to lines XT and Z2. Note that this represents g ne of the special cases where the number associated with the Z line is one unit greater than that associated with the X line. Lines A and D of line set 50, representing a numeral 9, are activated and line A of line set 52, representing a numeral 1, is activated. In converter 54, a transistor (not shown) becomes conductive and essentially grounds an output line 70 (the 9 output line). Grounding line 70 causes a transistor 74 in driver 58 to be turned ON which causes a voltage +V to be applied to line Y9 through transistor 74. When line 70 is grounded (low) the output of an inverting amplifier 72 is high. Therefore the left input terminal of OR-gate 62, connected to the output of amplifier 72 is high.

In converter 56 a transistor, not shown, becomes conductive, essentially grounding output line 76 (the 1 output line). Line 76 is connected to the Y1 terminal of the matrix of FIG. 3 and right hand input terminal of OR-gate 62. Since at least one of the input terminals of OR-gate 62 is low the output is low. OR-gate 64 has one input tied 'to an output line 78 (the 2 output line) of converter 56, which is high, and a second input tied to the output of an inverting amplifier 80, the input of which is connected to an output line 82 (the output line) of converter 54. Since line 82 is high the output of amplifier 80 is low and the second input to OR-gate 64 is low. Thus the output of OR-gate 64 is also low. The outputs of OR-gates 62 and 64 form the inputs to AND-gate 66 and since both inputs are low the output of AND-gate 66 is high. Amplifier 68 inverts the output of AND-gate 66, providing a low output signal on the Z 2 line ofthe matrix of H6. 3.

FIG. 5 is a block diagram showing the application and usefulness of the invention. This diagram includes a display 90, of the configuration of FIG. 1, having a total of 201 display media segments, 100 segments in a first column and 101 segments in a second column. The number of display media segments is computed from the formula 2nzn+l=20l where m=n=This display will provide a contrasted pointer for a 100 unit scale, that is, a scale with digits O0 to 99. Such a scale has a resolution of 1 percent.

The display command, received from a computer (not shown), is received on two four-line sets 50 and 52. The information received on the lines is in BCD form. The information on line set 52 relates to the 's digit to be displayed and the information of line set 50 relates to the is digit to be displayed. The information is converted from BCD form to straight decimal form in decoders 54 and 56 which include drivers that provide power to display 90 as commanded. The output lines of decoder 56 are connected to lines Y6 through of the matrix of display 90 and to lines Z 0 through 216 through a set of 18 two-input OR-gates 60. The output lines of decoder 54 are connected to lines Y0 through Y9 of the matrix.

The display segments are not limited to light emitting diodes, other devices having unilateral diode characteristics or that can have a series diode added to provide the unilateral diode characteristic and produce display contrast can be used. Liquid crystals e.g., can provide display contrast. They operate on a light scattering rather than a light emitting principle. The shape of the contrasted pointer is not limited to the triangular shape described. Any geometric or irregular shape can be used. Furthermore the shape of the individual display segments is a matter of choice. The number of columns used in the display is also a matter of choice. A display configuration need not be a straight column, for example, the configuration may be curved or irregular and also the scale quantities need not be linear. The display command need not be BCD, but can be any digital code that, when utilized with an appropriate decoder, selects one of m Y-lines and one of n X- lines to drive the matrix.

Many modifications and variations of the present invention are possible and the embodiment described herein should not be considered a limitation of the present invention which is to be limited only by the following claims.

What is claimed is:

1. A display comprising first and second columns of display media segments, the

segments of the second column offset from those in the first column, the columns formed with n blocks of segments and n+l individual segments, each block containing m segments in the first column and ml segments in the second column, the individual segments being in the second column; and, means for selectively energizing a predetermined pattern of segments in the first column and in the second column.

2. The display of claim 1 wherein the display media segments provide display contrast.

3. The display of claim 2 wherein the display media segments are liquid crystals.

4. The display of claim 1 wherein the display media segments are light emitting diodes.

5. The display of claim 1 wherein the selectively energized predetermined pattern of segments comprises three mutually adjacent segments, one segment in the first column and two segments in the second column.

Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US4253096 *Apr 12, 1978Feb 24, 1981Bbc Brown, Boveri & Company, LimitedMethod for addressing an electro-optical device, and an addressing circuit and a display device for carrying out the method
US4680580 *Feb 18, 1983Jul 14, 1987Kabushiki Kaisha Daini SeikoshaActive matrix-addressed liquid-crystal display device
US4739319 *Aug 9, 1985Apr 19, 1988Isuzu Motors LimitedBar graph display apparatus
US4903596 *Sep 14, 1987Feb 27, 1990Heidelberger Druckmaschinen AgSystem for indicating settings of ink feed for printing
U.S. Classification345/39, 345/204, 315/132
International ClassificationG11C15/00, G01R13/40, G01R13/00
Cooperative ClassificationG11C15/00, G01R13/408
European ClassificationG01R13/40C4, G11C15/00
Legal Events
Sep 23, 1994ASAssignment
Effective date: 19940113
Sep 23, 1994AS01Change of name
Effective date: 19940113
Apr 20, 1994ASAssignment
Effective date: 19940113
Apr 20, 1994AS02Assignment of assignor's interest
Owner name: ALFA LAVAL AB
Effective date: 19940113