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After reading how processors use pipelines (from various articles: wikipedia, SU, and other places), I'm a bit confused on certain parts of what I've read, so I would just like to share what I've come to understand and if someone can just clarify that the following is correct (please let me know if any of it's wrong),


cycle = clock cycle
ICR = Instruction Completion Rate
IT = Instruction Throughput
IL = Instruction Latency

  1. IL is the number of nanoseconds taken for a single instruction to pass through the whole pipeline (so the lower the IL, the higher the ICR).

  2. Each stage of a pipeline takes one cycle to complete.

  3. Assuming that: a pipeline doesn't experience any "bubbles", cache misses, etc; the pipeline is 5 stages deep, the processor is running at a clock speed of 2 GHz (that's 0.5 nanoseconds per cycle).

    The processor will be able to process 800'000'000 instructions in one second (ignoring the fact that the pipeline needs to first fill with instructions, in order to reach it's maximum IT).

  4. If a pipeline is 10 stages deep, an instruction will have an IL of 10 cycles.

  5. The maximum IT a single core, non-superscalar architect processor can achieve is, 1 instruction per cycle.

  6. A processor's cycle period is determined by the slowest stage of its pipeline.

  7. The shorter the period of time each stage of a pipeline takes the higher the IT & ICR.

  8. The perfect pipeline has a: low IL, high pipeline depth (but prevents "bubbles", cache misses, etc), high clock speed, high IT & high ICR.

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closed as off-topic by Breakthrough, Excellll, Tog, Dave M, allquixotic Sep 11 '13 at 19:24


  • "This question is not about computer hardware or software, within the scope defined in the help center." – Excellll, Tog, Dave M, allquixotic

1 Answer

up vote 2 down vote accepted


1) Its really has more to do with how long the pipeline is. To compare, a high latency internet connection is not necessarily one with low bandwidth.

2) Yes, though sometimes an instruction can't leave a particular stage of the pipeline when we want it to (cache miss, etc.).

3) No, it will process 2,000,000,000 instructions. A different instruction will be in each stage of the pipeline at any time, so having 5 stages won't slow it down in the perfect universe where nothing bubbles or cache misses.

4) Sounds right. With some processors, how many stages an instruction goes through depends on the instruction.

5) Sounds right.

6) They all have to run on the same clock, but when you are engineering one, yes, which ever one fails to clock the highest becomes the limiting factor.

7) Yes, and the shorter the instruction latency is too, though achieving these higher clock speeds often requires lengthening the pipeline.

8) A long pipeline may let you achieve higher clock speeds but leaves you more vulnerable to bubbles or mispredicted branches, so this is really more of a trade off. Ultimately all you care about is throughput.

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Thanks, just to clarify IT is the measurement of how many instructuctions are processed in a given amount of time, right? If so, then wouldn't IL affect ICR, then ICR wouldn't equal IT. –  Sam Sep 3 '13 at 12:33
I'm not really sure what you mean, but IT and ICR really are synonyms. As far as the relation between IL and ICR, ICR (or IT) = pipeline depth / IL. For example, a 1 GHz CPU with a pipeline depth of 10 has an IL of 10 ns, 10 / 10 ns = 1 billion instructions per second. –  wingedsubmariner Sep 3 '13 at 21:54
Oh ok, the example cleared things up, thanks. So I suppose the trick to getting higher IT is, to shorten the period of the slowest stage in the pipeline without increasing its depth? –  Sam Sep 4 '13 at 8:59
Maybe. Or maybe you want to split that stage in two, and accept the increased pipeline depth. There are no easy answers in engineering. –  wingedsubmariner Sep 4 '13 at 12:28
Ok, thanks for your help. –  Sam Sep 4 '13 at 13:46
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