Experienced GPU Cache RTL Design Engineer - 74290

Location: Santa Clara, US

Company: Advanced Micro Devices

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What you do at AMD changes everything 



AMD's GPU design team is seeking an experienced ASIC Design Engineer to design the cache system control for our GPUs with a focus on low power. This position is for a design engineer in AMD's graphics group working on next generation graphics architectures. Our focus is on design of the high performance GPUs that support advanced graphics rendering and highly parallelized scientific computing.


We are looking for candidates with:
Strong technical skills
Good communication skills
Ability to develop complex system designs that meet stringent power goals

Experience in the following areas is valuable:
High performance processor designs, particularly highly parallel compute systems; GPUs, DSPs or other novel systems
Cache systems, particularly multiple level caches and multiprocessor cache schemes
High performance graphics hardware architecture

The successful candidate will:
Be responsible for a block's hardware design.
Collaborate with architects to translate the block's functional requirements into the block micro architectural specification.
Be responsible for implementing the block Register Transfer Level (RTL) in hardware description language.
Be responsible for synthesizing the RTL to generate the logic gate result.
Assist physical design teams in timing closure.

Collaborate with the block verification team on the block test plan.
Add functional coverage visibility to the design and provide coverage analysis.

Debug block test failures.
Support post-silicon debug efforts.


Master's degree and 1 or more years' experience; or Bachelor's degree and 3 or more years' experience. Degree in Electrical or Computer Engineering preferred.


Relevant Experience:
Knowledge of computer architecture, including memory sub-systems, cache hierarchies, and pipelined design.
Experience with hardware description languages like Verilog or VHDL.
Experience with synthesis tools (e.g. Synopsys Design Compiler, Cadence RTL compiler, etc.).
Experience with Static Timing Analysis tools (e.g., Synopsys PrimeTime, Cadence Encounter, etc.).
Experience with RTL Linting tools (e.g., Cadence Conformal Lint, Synopsys LEDA, Atrenta Spyglass, etc.).
Experience with RTL logical equivalency checking tools (e.g. Synopsys Formality, Cadence Conformal LEC, etc.).



Requisition Number: 74290 
Country: United States State: California City: Santa Clara 
Job Function: Design 



Nearest Major Market: San Jose
Nearest Secondary Market: Palo Alto

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