When sampling a signal, it is standard practice to use a sampling rate that is greater than two times the bandwidth of the signal in order to avoid aliasing. The result is then low-pass filtered (and sometimes upsampled prior to this) in order to get rid of the harmonics.

Unfortunately, in control systems applications preventing aliasing in not enough. The system also needs to respond quickly enough to the input (as determined by a spec), and a low sampling rate will limit this performance. Specifically, if the system samples a signal at time t, then any event that occurs immediately afterwards will be ignored until one sampling period later. Thus, there are clear performance advantages to having a sampling rate much greater than two times the signal bandwidth. I'm looking to quantify this performance improvement.

Consider an open-loop control system that attempts to cancel out an incoming signal by outputting an inverted version of this same signal. In other words, active compensation through destructive interference. If the system has infinite magnitude resolution (both the ADC and DAC have infinite bits) and an infinite sampling time, then the inverted output signal will be a perfect inverse of the original and the signals will cancel out completely. But if the system has a finite sampling rate, then the output signal will not be a perfect inverse of the original and the two will not cancel completely. The lower the sampling rate, the worse the cancellation will be (even if no aliasing occurs).

Q: Assuming the following:

  • The input signal is a sinusoid of frequency $f_0$ and magnitude $A$

  • The system has an ADC with a sampling rate of $f_s$ where $f_s > 2 f_0$

  • The system uses sample-and-hold (ZOH) interpolation to output an inverted sinusoid and add it to the original signal

  • The system has zero time delay between an ADC sample and the corresponding DAC output (ADC settling time, DSP calculations, etc. are instantaneous)

How do I calculate the frequency and magnitude of the resulting frequency components?

  • $\begingroup$ Seems you could model the sampling rate effect by changing your zero time delay assumption. As a worst-case analysis, you could assume that your system instead has a time delay of some value just a bit less than one sampling period. In this case, you won't achieve perfect cancellation, as you pointed out. Instead, your "canceller" is really just a comb filter, which might not give you the desired performance at all. $\endgroup$ – Jason R Sep 23 '15 at 19:24
  • $\begingroup$ I don't have much experience with active cancellation, but this may be why linear prediction is a common tool for this task. If you're simply feeding back without any prediction, you're always going to be "behind" the input, limiting your ability to cancel it effectively. If you can stochastically model the signal such that you can predict what it should be shortly in the future, then your canceller could be more effective. $\endgroup$ – Jason R Sep 23 '15 at 19:26
  • $\begingroup$ I used a sinusoid in the example to simplify the math, but in reality the input signal would be white noise over a specified frequency range. I don't believe that can be predicted, can it? $\endgroup$ – SharpHawk Sep 23 '15 at 20:27

The system has zero time delay (sampling, calculations, etc. are instantaneous)

This is an invalid assumption. Almost every digital system has at least one sample delay. DAC and ADC or clocked off the same master clock. So at sample time n, the ADC is acquiring sample n while at the same time the DAC is outputting sample n-1. The only way around this is using a much higher master clock, donwsampling that clock and clocking the A/D and D/A on different phases. However that's equivalent to running at a higher sample rate in the first place.

So your ability to cancel is given by how much the amplitude of the sine wave changes during 1 sample. The residual signal is simply given by $$e(t) = \sin(f_0 \cdot t) - \sin(f_0 \cdot (t-T_s)) = 2 \cdot \cos(f_0 \cdot (t- T_s/2)) \cdot \sin(f_0 \cdot T_s/2)$$ where $T_s = 1/f_s$ is the sample time. The error is simply a function of the ratio of signal frequency and sample rate. For $f_0 << f_s$ the error is very small.

The only way to get around this is to crank up the sample rate or use some a priori knowledge of the signal to do some prediction and speculative cancellation.

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  • $\begingroup$ Not quite correct: the second term is held constant between sampling instants, so it's really not $\sin(f_0 \cdot (t-T_s))$. More like $\sin(f_0 \cdot (\lceil t/T_s \rceil*T_s -T_s))$. $\endgroup$ – Peter K. Sep 23 '15 at 19:50
  • $\begingroup$ It's true that a real ADC exhibits some amount of delay $t_d$, but frequently $t_d << 1/f_s$ and therefore it can be ignored. This is certainly true for my application, which is why I provided the zero delay assumption. Additionally, you may be saying (I'm not sure) that a sample and hold scheme is a form of pure delay, which I believe is incorrect. $\endgroup$ – SharpHawk Sep 23 '15 at 20:38
  • $\begingroup$ I've reworded that assumption to remove any ambiguity between ADC settling time and sampling period. I meant to say that the former is zero, not the latter, in case that wasn't clear. $\endgroup$ – SharpHawk Sep 23 '15 at 20:42
  • $\begingroup$ One last comment, since I'm no longer allowed to edit the previous ones: you claim that "every digital system has at least on sample delay." This is true only if you define one sample as one cycle of the MCU/DSP. Since the MCU/DSP (and the DAC) can run at frequencies orders of magnitude greater than the sampling frequency, this delay is insignificant relative to the time between ADC samples. $\endgroup$ – SharpHawk Sep 23 '15 at 20:56
  • $\begingroup$ A real ADC with an anti-alias filter will not have a settling time much faster than 1/Fs. If it does, it will produce lots of alias spectra. Therefore delays on the order of 1/Fs can not be ignored. $\endgroup$ – hotpaw2 Sep 23 '15 at 21:11

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