@misc{10695, author = {Horstmann, Jens}, publisher = {Paderborn University}, title = {{Beschleunigte Simulation elektrischer Stromnetze mit GPUs}}, year = {2016}, } @book{10758, author = {Squillero, Giovanni and Burelli, Paolo and M. Mora, Antonio and Agapitos, Alexandros and S. Bush, William and Cagnoni, Stefano and Cotta, Carlos and De Falco, Ivanoe and Della Cioppa, Antonio and Divina, Federico and Eiben, A.E. and I. Esparcia-Alc{\'a}zar, Anna and Fern{\'a}ndez de Vega, Francisco and Glette, Kyrre and Haasdijk, Evert and Ignacio Hidalgo, J. and Kampouridis, Michael and Kaufmann, Paul and Mavrovouniotis, Michalis and Thanh Nguyen, Trung and Schaefer, Robert and Sim, Kevin and Tarantino, Ernesto and Urquhart, Neil and Zhang (editors), Mengjie}, publisher = {Springer}, title = {{Applications of Evolutionary Computation - 19th European Conference, EvoApplications}}, volume = {9597}, year = {2016}, } @inproceedings{13151, author = {Graf, Tobias and Platzner, Marco}, booktitle = {Computer and Games}, title = {{Using Deep Convolutional Neural Networks in Monte Carlo Tree Search}}, year = {2016}, } @inproceedings{15873, author = {Boschmann, Alexander and Agne, Andreas and Witschen, Linus Matthias and Thombansen, Georg and Kraus, Florian and Platzner, Marco}, booktitle = {2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, isbn = {9781467394062}, keyword = {Electromyography, Feature extraction, Delays, Hardware Pattern recognition, Prosthetics, High definition video}, location = {Mexiko City, Mexiko}, publisher = {IEEE}, title = {{FPGA-based acceleration of high density myoelectric signal processing}}, doi = {10.1109/reconfig.2015.7393312}, year = {2016}, } @misc{10615, author = {Ahmed, Abdullah Fathi}, publisher = {Paderborn University}, title = {{Self-Optimizing Organic Cache}}, year = {2015}, } @inproceedings{10711, author = {Meisner, Sebastian and Platzner, Marco}, booktitle = {Field Programmable Technology (FPT), 2015 International Conference on}, pages = {212--215}, title = {{Comparison of thread signatures for error detection in hybrid multi-cores}}, doi = {10.1109/FPT.2015.7393153}, year = {2015}, } @misc{3364, author = {Knorr, Christoph}, title = {{Evaluation von Bildverarbeitungsalgorithmen in heterogenen Rechenknoten}}, year = {2015}, } @inproceedings{10767, author = {Ghribi, Ines and Ben Abdallah, Riadh and Khalgui, Mohamed and Platzner, Marco}, booktitle = {Proceedings of the 29th European Simulation and Modelling Conference (ESM)}, title = {{New Codesign Solutions for Modelling and Partitioning of Probabilistic Reconfigurable Embedded Software}}, year = {2015}, } @inproceedings{10779, author = {Guettatfi, Zakarya and Kermia, Omar and Khouas, Abdelhakim}, booktitle = {25th International Conference on Field Programmable Logic and Applications (FPL)}, issn = {1946-147X}, keyword = {embedded systems, field programmable gate arrays, operating systems (computers), scheduling, μC/OS-II, FPGAs, OS foundation, SafeRTOS, Xenomai, chip utilization ration, complex time constraints, embedded systems, hard real-time hardware task allocation, hard real-time hardware task scheduling, hardware-software real-time operating systems, partially reconfigurable field-programmable gate arrays, resource constraints, safety-critical RTOS, Field programmable gate arrays, Hardware, Job shop scheduling, Real-time systems, Shape, Software}, publisher = {Imperial College}, title = {{Over effective hard real-time hardware tasks scheduling and allocation}}, doi = {10.1109/FPL.2015.7293994}, year = {2015}, } @inproceedings{10673, author = {Ho, Nam and Ahmed, Abdullah Fathi and Kaufmann, Paul and Platzner, Marco}, booktitle = {Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)}, keyword = {cache storage, field programmable gate arrays, multiprocessing systems, parallel architectures, reconfigurable architectures, FPGA, dynamic reconfiguration, evolvable cache mapping, many-core architecture, memory-to-cache address mapping function, microarchitectural optimization, multicore architecture, nature-inspired optimization, parallelization degrees, processor, reconfigurable cache mapping, reconfigurable computing, Field programmable gate arrays, Software, Tuning}, pages = {1--7}, title = {{Microarchitectural optimization by means of reconfigurable and evolvable cache mappings}}, doi = {10.1109/AHS.2015.7231178}, year = {2015}, } @inproceedings{13153, author = {Graf, Tobias and Platzner, Marco}, booktitle = {Advances in Computer Games: 14th International Conference, ACG 2015, Leiden, The Netherlands, July 1-3, 2015, Revised Selected Papers}, pages = {1--11}, publisher = {Springer International Publishing}, title = {{Adaptive Playouts in Monte-Carlo Tree Search with Policy-Gradient Reinforcement Learning}}, doi = {10.1007/978-3-319-27992-3_1}, year = {2015}, } @article{1768, author = {Plessl, Christian and Platzner, Marco and Schreier, Peter J.}, journal = {Informatik Spektrum}, keyword = {approximate computing, survey}, number = {5}, pages = {396--399}, publisher = {Springer}, title = {{Aktuelles Schlagwort: Approximate Computing}}, doi = {10.1007/s00287-015-0911-z}, year = {2015}, } @inproceedings{238, abstract = {In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator.}, author = {Damschen, Marvin and Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian}, booktitle = {Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)}, pages = {1078--1083}, publisher = {EDA Consortium / IEEE}, title = {{Transparent offloading of computational hotspots from binary code to Xeon Phi}}, doi = {10.7873/DATE.2015.1124}, year = {2015}, } @inproceedings{303, abstract = {This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement.}, author = {Damschen, Marvin and Plessl, Christian}, booktitle = {Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)}, title = {{Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores}}, year = {2015}, } @inproceedings{269, abstract = {Proof-carrying hardware is an approach that has recently been proposed for the efficient verification of reconfigurable modules. We present an application of proof-carrying hardware to guarantee the correct functionality of dynamically reconfigured image processing modules. Our prototype comprises a reconfigurable-system-on-chip with an embedded virtual FPGA fabric. This setup allows us to leverage open source FPGA synthesis and backend tools to produce FPGA configuration bitstreams with an open format and, thus, to demonstrate and experimentally evaluate proof-carrying hardware at the bitstream level.}, author = {Wiersema, Tobias and Wu, Sen and Platzner, Marco}, booktitle = {Proceedings of the International Symposium in Reconfigurable Computing (ARC)}, pages = {365----372}, title = {{On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach}}, doi = {10.1007/978-3-319-16214-0_32}, year = {2015}, } @article{10770, author = {Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}, journal = {IEEE Transactions on Nanotechnology}, number = {6}, pages = {1117--1126}, publisher = {IEEE}, title = {{From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires}}, doi = {10.1109/TNANO.2015.2482359}, volume = {14}, year = {2015}, } @phdthesis{10624, abstract = {The use of heterogeneous computing resources, such as graphics processing units or other specialized co-processors, has become widespread in recent years because of their performance and energy efficiency advantages. Operating system approaches that are limited to optimizing CPU usage are no longer sufficient for the efficient utilization of systems that comprise diverse resource types. Enabling task preemption on these architectures and migration of tasks between different resource types at run-time is not only key to improving the performance and energy consumption but also to enabling automatic scheduling methods for heterogeneous compute nodes. This thesis proposes novel techniques for run-time management of heterogeneous resources and enabling tasks to migrate between diverse hardware. It provides fundamental work towards future operating systems by discussing implications, limitations, and chances of the heterogeneity and introducing solutions for energy- and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous systems by the use of a centralized scheduler are presented that show benefits over existing approaches in varying case studies.}, author = {Beisel, Tobias}, isbn = {978-3-8325-4155-2}, pages = {183}, publisher = {Logos Verlag Berlin GmbH}, title = {{Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing}}, year = {2015}, } @inproceedings{10693, author = {Kaufmann, Paul and Shen, Cong}, booktitle = {Genetic and Evolutionary Computation (GECCO)}, pages = {409--416}, publisher = {ACM}, title = {{Generator Start-up Sequences Optimization for Network Restoration Using Genetic Algorithm and Simulated Annealing}}, year = {2015}, } @article{296, abstract = {FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x.}, author = {Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, journal = {International Journal of Reconfigurable Computing (IJRC)}, publisher = {Hindawi}, title = {{Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study}}, doi = {10.1155/2015/859425}, volume = {2015}, year = {2015}, } @inproceedings{10771, author = {Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and Zhang, Jian and De Micheli, Giovanni and Sanchez, Eduardo and Reorda, Matteo Sonza}, booktitle = {2015 IEEE Computer Society Annual Symposium on VLSI}, pages = {491--496}, publisher = {IEEE}, title = {{On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors}}, doi = {10.1109/ISVLSI.2015.13}, year = {2015}, } @misc{10668, author = {Hangmann, Hendrik}, publisher = {Paderborn University}, title = {{Evolution of Heat Flow Prediction Models for FPGA Devices}}, year = {2015}, } @misc{10714, author = {Meißner, Roland}, publisher = {Paderborn University}, title = {{Konzept und Implementation einer Benutzeroberfläche zur Generierung virtueller FPGAs}}, year = {2015}, } @misc{10726, author = {Posewsky, Thorbjörn}, publisher = {Paderborn University}, title = {{Acceleration of Artificial Neural Networks on a Zynq Platform}}, year = {2015}, } @book{10757, author = {M. Mora, Antonio and Squillero, Giovanni and Agapitos, Alexandros and Burelli, Paolo and S. Bush, William and Cagnoni, Stefano and Cotta, Carlos and De Falco, Ivanoe and Della Cioppa, Antonio and Divina, Federico and Eiben, A.E. and I. Esparcia-Alc{\'a}zar, Anna and Fern{\'a}ndez de Vega, Francisco and Glette, Kyrre and Haasdijk, Evert and Ignacio Hidalgo, J. and Kampouridis, Michael and Kaufmann, Paul and Mavrovouniotis, Michalis and Thanh Nguyen, Trung and Schaefer, Robert and Sim, Kevin and Tarantino, Ernesto and Urquhart, Neil and Zhang (editors), Mengjie}, publisher = {Springer}, title = {{Applications of Evolutionary Computation - 18th European Conference, EvoApplications}}, volume = {9028}, year = {2015}, } @article{1772, author = {Torresen, Jim and Plessl, Christian and Yao, Xin}, journal = {IEEE Computer}, keyword = {self-awareness, self-expression}, number = {7}, pages = {18--20}, publisher = {IEEE Computer Society}, title = {{Self-Aware and Self-Expressive Systems – Guest Editor's Introduction}}, doi = {10.1109/MC.2015.205}, volume = {48}, year = {2015}, } @inproceedings{10772, author = {Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}, booktitle = {Proceedings of the 2015 Design, Automation & Test in Europe Conference \& Exhibition}, pages = {453--458}, publisher = {EDA Consortium}, title = {{Fault modeling in controllable polarity silicon nanowire circuits}}, doi = {10.7873/DATE.2015.0428}, year = {2015}, } @inproceedings{10765, author = {H.W. Leong, Philip and Amano, Hideharu and Anderson, Jason and Bertels, Koen and M.P. Cardoso, Jo\~ao and Diessel, Oliver and Gogniat, Guy and Hutton, Mike and Lee, JunKyu and Luk, Wayne and Lysaght, Patrick and Platzner, Marco and K. Prasanna, Viktor and Rissa, Tero and Silvano, Cristina and So, Hayden and Wang, Yu}, booktitle = {Proceedings of the 25th International Conference on Field Programmable Logic and Applications (FPL)}, pages = {1--3}, publisher = {Imperial College}, title = {{Significant papers from the first 25 years of the FPL conference}}, doi = {10.1109/FPL.2015.7293747}, year = {2015}, } @misc{10671, author = {Haupt, Christian}, publisher = {Paderborn University}, title = {{Computer Vision basierte Klassifikation von HD EMG Signalen}}, year = {2015}, } @inproceedings{1773, author = {Schumacher, Jörn and T. Anderson, J. and Borga, A. and Boterenbrood, H. and Chen, H. and Chen, K. and Drake, G. and Francis, D. and Gorini, B. and Lanni, F. and Lehmann-Miotto, Giovanna and Levinson, L. and Narevicius, J. and Plessl, Christian and Roich, A. and Ryu, S. and P. Schreuder, F. and Vandelli, Wainer and Vermeulen, J. and Zhang, J.}, booktitle = {Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)}, publisher = {ACM}, title = {{Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm}}, doi = {10.1145/2675743.2771824}, year = {2015}, } @inproceedings{10773, author = {Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and Yazdani, Majid and De Micheli, Giovanni}, booktitle = {2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)}, pages = {163--168}, publisher = {IEEE}, title = {{Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection}}, doi = {10.1109/NANOARCH.2014.6880479}, year = {2014}, } @article{10603, author = {Giefers, Heiner and Platzner, Marco}, journal = {IEEE Transactions on Computers}, number = {12}, pages = {2919 -- 2932}, title = {{An FPGA-based Reconfigurable Mesh Many-Core}}, doi = {10.1109/TC.2013.174}, volume = {63}, year = {2014}, } @misc{10627, author = {Bockhorn, Arne}, publisher = {Paderborn University}, title = {{Echtzeit Klassifikation von sEMG Signalen mit einem low-cost DSP Evaluation Board}}, year = {2014}, } @misc{10665, author = {Hagedorn, Christoph}, publisher = {Paderborn University}, title = {{Entwicklung einer codegrößenoptimierten Softwarebibliothek für 8-Bit Mikrocontroller in netzunabhängigen Notleuchten}}, year = {2014}, } @inproceedings{10677, author = {Ho, Nam and Kaufmann, Paul and Platzner, Marco}, booktitle = {2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)}, keyword = {Linux, cache storage, embedded systems, granular computing, multiprocessing systems, reconfigurable architectures, Leon3 SPARe processor, custom logic events, evolvable-self-adaptable processor cache, fine granular profiling, integer unit events, measurement infrastructure, microarchitectural events, multicore embedded system, perf_event standard Linux performance measurement interface, processor properties, run-time reconfigurable memory-to-cache address mapping engine, run-time reconfigurable multicore infrastructure, split-level caching, Field programmable gate arrays, Frequency locked loops, Irrigation, Phasor measurement units, Registers, Weaving}, pages = {31--37}, title = {{Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure}}, doi = {10.1109/ICES.2014.7008719}, year = {2014}, } @article{1779, author = {Giefers, Heiner and Plessl, Christian and Förstner, Jens}, issn = {0163-5964}, journal = {ACM SIGARCH Computer Architecture News}, keyword = {funding-maxup, tet_topic_hpc}, number = {5}, pages = {65--70}, publisher = {ACM}, title = {{Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers}}, doi = {10.1145/2641361.2641372}, volume = {41}, year = {2014}, } @inproceedings{388, abstract = {In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties.}, author = {Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian}, booktitle = {Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)}, pages = {144--155}, publisher = {Springer International Publishing}, title = {{Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer}}, doi = {10.1007/978-3-319-05960-0_13}, volume = {8405}, year = {2014}, } @inproceedings{408, abstract = {Verification of hardware and software usually proceeds separately, software analysis relying on the correctness of processors executing instructions. This assumption is valid as long as the software runs on standard CPUs that have been extensively validated and are in wide use. However, for processors exploiting custom instruction set extensions to meet performance and energy constraints the validation might be less extensive, challenging the correctness assumption.In this paper we present an approach for integrating software analyses with hardware verification, specifically targeting custom instruction set extensions. We propose three different techniques for deriving the properties to be proven for the hardware implementation of a custom instruction in order to support software analyses. The techniques are designed to explore the trade-off between generality and efficiency and span from proving functional equivalence over checking the rules of a particular analysis domain to verifying actual pre and post conditions resulting from program analysis. We demonstrate and compare the three techniques on example programs with custom instructions, using stateof-the-art software and hardware verification techniques.}, author = {Jakobs, Marie-Christine and Platzner, Marco and Wiersema, Tobias and Wehrheim, Heike}, booktitle = {Proceedings of the 11th International Conference on Integrated Formal Methods (iFM)}, editor = {Albert, Elvira and Sekerinski, Emil}, pages = {307--322}, title = {{Integrating Software and Hardware Verification}}, doi = {10.1007/978-3-319-10181-1_19}, year = {2014}, } @inproceedings{439, abstract = {Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes.}, author = {Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, booktitle = {Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, pages = {1--8}, publisher = {IEEE}, title = {{Deferring Accelerator Offloading Decisions to Application Runtime}}, doi = {10.1109/ReConFig.2014.7032509}, year = {2014}, } @inproceedings{10654, author = {Glette, Kyrre and Kaufmann, Paul}, booktitle = {IEEE Congress on Evolutionary Computation (CEC)}, title = {{Lookup Table Partial Reconfiguration for an Evolvable Hardware Classifier System}}, year = {2014}, } @inproceedings{1782, author = {Graf, Tobias and Schaefers, Lars and Platzner, Marco}, booktitle = {Proc. Conf. on Computers and Games (CG)}, number = {8427}, pages = {14--25}, publisher = {Springer}, title = {{On Semeai Detection in Monte-Carlo Go}}, doi = {10.1007/978-3-319-09165-5_2}, year = {2014}, } @inproceedings{377, abstract = {In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates.}, author = {Riebler, Heinrich and Kenter, Tobias and Plessl, Christian and Sorge, Christoph}, booktitle = {Proceedings of Field-Programmable Custom Computing Machines (FCCM)}, keyword = {coldboot}, pages = {222--229}, publisher = {IEEE}, title = {{Reconstructing AES Key Schedules from Decayed Memory with FPGAs}}, doi = {10.1109/FCCM.2014.67}, year = {2014}, } @article{365, abstract = {Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems.}, author = {Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, journal = {ACM Transactions on Reconfigurable Technology and Systems (TRETS)}, number = {2}, publisher = {ACM}, title = {{Self-awareness as a Model for Designing and Operating Heterogeneous Multicores}}, doi = {10.1145/2617596}, volume = {7}, year = {2014}, } @inproceedings{10674, author = {Ho, Nam and Kaufmann, Paul and Platzner, Marco}, booktitle = {24th Intl. Conf. on Field Programmable Logic and Applications (FPL)}, keyword = {Linux, hardware-software codesign, multiprocessing systems, parallel processing, LEON3 multicore platform, Linux kernel, PMU, hardware counters, hardware-software infrastructure, high performance embedded computing, perf_event, performance monitoring unit, Computer architecture, Hardware, Monitoring, Phasor measurement units, Radiation detectors, Registers, Software}, pages = {1--4}, title = {{A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms}}, doi = {10.1109/FPL.2014.6927437}, year = {2014}, } @misc{10679, author = {König, Fabian}, publisher = {Paderborn University}, title = {{EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen Prothese}}, year = {2014}, } @misc{10701, author = {Koch, Benjamin}, publisher = {Paderborn University}, title = {{Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA}}, year = {2014}, } @misc{10732, author = {Rüthing, Christoph}, publisher = {Paderborn University}, title = {{The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores}}, year = {2014}, } @misc{10744, author = {Surmund, Sebastian}, publisher = {Paderborn University}, title = {{Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA}}, year = {2014}, } @book{10756, author = {I. Esparcia-Alc{\'a}zar, Anna and Eiben, A.E. and Agapitos, Alexandros and Sim{\~o}es, Anabela and G.B. Tettamanzi, Andrea and Della Cioppa, Antonio and M. Mora, Antonio and Cotta, Carlos and Tarantino, Ernesto and Haasdijk, Evert and Divina, Federico and Fern{\'a}ndez de Vega, Francisco and Squillero, Giovanni and De Falco, Ivanoe and Ignacio Hidalgo, J. and Sim, Kevin and Glette, Kyrre and Zhang, Mengjie and Urquhart, Neil and Burelli, Paolo and Kaufmann, Paul and Po{\v s}{\'\i}k, Petr and Schaefer, Robert and Drechsler, Rolf and Antipolis, Sophia and Cagnoni, Stefano and Thanh Nguyen, Trung and S. Bush (editors), William}, publisher = {Springer}, title = {{Applications of Evolutionary Computation - 17th European Conference, EvoApplications}}, volume = {8602}, year = {2014}, } @inproceedings{13154, author = {Graf, Tobias and Platzner, Marco}, booktitle = {2014 IEEE Conference on Computational Intelligence and Games}, pages = {1--8}, title = {{Common Fate Graph Patterns in Monte Carlo Tree Search for Computer Go}}, doi = {10.1109/CIG.2014.6932863}, year = {2014}, } @article{328, abstract = {The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications}, author = {Agne, Andreas and Happe, Markus and Keller, Ariane and Lübbers, Enno and Plattner, Bernhard and Platzner, Marco and Plessl, Christian}, journal = {IEEE Micro}, number = {1}, pages = {60--71}, publisher = {IEEE}, title = {{ReconOS - An Operating System Approach for Reconfigurable Computing}}, doi = {10.1109/MM.2013.110}, volume = {34}, year = {2014}, }