Assuming the stored value of the RHBD 10T proposal
the memory cell is 1 in digital logic, that is, Q = 1, QN = 0, S1 = 1,
and S0 = 0, as shown in Fig. We can easily imagine that
The proposed RHBD 10T memory cell continuously maintains storage
value when the WL is driven by a low voltage (WL = 0). Before normal
read the operation, due to the preload circuits, the voltages of the bit lines
BL and BLN will be raised to 1 in digital logic. In the reading operation,
WL is in high mode (WL = 1), then two access transistors
N3 and N4 are on immediately. Nodes Q, QN, S1 and
S0 saves the stored value, and the voltage of the bit line BL is
nor changed However, the bitline voltage BLN is reduced
due to the discharge operation through the ON N1 and N3 transistors.


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