J1a SwapForth built with IceStorm

Project IceStorm aims to reverse engineer some Lattice FPGAs, and provides a working tool chain for synthesizing designs and downloading them into the hardware.

The J1a CPU is a minimal 16-bit Verilog CPU, fits easily on the Lattice HX20-1K on the Lattice iCEstick evaluation board. After some help from the people at project IceStorm, it is now buildable using the IceStorm tools. The J1a is a simplified variant of the original J1. The modifications from the original J1 are:

The board has 8K of RAM, and runs SwapForth, a small but complete interactive Forth development environment. SwapForth takes about 5K of the available RAM, and includes a full native compiler, the ANS standard CORE words, and several more modern extensions.

The whole system is:

There is a 20-page manual covering board setup and usage of SwapForth.

Source code is at https://github.com/jamesbowman/swapforth/tree/master/j1a