QuickLogic Collaborates with ETH Zurich to Integrate eFPGA into PULP Platform

-- Integrating eFPGA into the Parallel Ultra Low Power (PULP) platform enables significant power reduction for researchers and developers using the platform

-- Developing SoC which integrates ArcticPro™ eFPGA technology with RISC-V cores

-- First licensee of eFPGA technology on GLOBALFOUNDRIES new 22FDX® process node

SUNNYVALE, Calif., Aug. 8, 2018 /PRNewswire/ -- QuickLogic Corporation (NASDAQ: QUIK), a developer of ultra-low power embedded FPGA IP and programmable logic solutions, today announced that the ETH Zurich, [in German: Eidgenössische Technische Hochschule Zürich (ETH)], a renowned technical university located in Zurich, Switzerland, will collaborate to integrate QuickLogic's ArcticPro embedded FPGA (eFPGA) technology onto the university's PULP platform. ETH chose QuickLogic's technology for its ultra-low power operation and its ability to create new options for extremely power efficient hardware/software implementations.

QuickLogic logo (PRNewsfoto/QuickLogic Corporation)

ETH is a science, technology, engineering and mathematics STEM university in the city of Zürich, Switzerland. It will become the first licensee of eFPGA technology from QuickLogic on the 22FDX process node. They will develop an SoC integrating ETHZ's open-source RISC-V cores and eFPGA technology, enabling users to offload critical functions from the processor(s) and implement them in eFPGA fabric. This approach creates multiple hardware co-processors that increase system efficiency and performance while decreasing power consumption. A common use case is utilizing the eFPGA to enable hardware acceleration of feature extraction, which significantly improves performance and lowers power consumption by offloading those functions from the RISC-V processor while still maintaining the ability to adopt updated algorithms.

PULP is a silicon-proven open-source parallel platform for ultra-low power computing created with the objective of delivering high compute bandwidth combined with high-energy efficiency. The platform is organized in clusters of RISC-V cores that share a common and tightly-coupled data memory subsystem. The platform also includes a set of System Verilog-described IP blocks, their related synthesis and simulation scripts, and the runtime software (written in C and RISC-V assembly) necessary to provide a complete system. All of the architecture, IP, scripts and software are open sourced to encourage global collaboration and development.

Integrating QuickLogic's eFPGA technology onto PULP opens a new dimension of power reduction possibilities for researchers and developers using the platform. Now, users will be able to explore hardware/software tradeoffs for different classes of designs and move certain functions from software running on a processor or processors to hardware in the eFPGA fabric, thus achieving dramatic reductions in total system power consumption.

"The high degree of implementation flexibility and ultra-low power consumption of QuickLogic's eFPGA technology make it a perfect complement to the extreme power efficiency objectives we have for the PULP platform," said Dr. Luca Benini, director of the project and one of its originators. "We are excited to integrate this technology to evaluate hardware/software implementation trade-offs, and we are particularly interested in exploring feature extraction functions for AI at the edge and security applications."

"The main goal of the PULP program is to use a multi-disciplinary approach to achieve extremely high-power efficiency for computing applications," said Dr. Timothy Saxe, QuickLogic's chief technology officer. "QuickLogic has a tremendous depth of experience in achieving low power consumption across a broad range of applications, including AI and IoT at the edge and security, and we look forward to contributing what we've learned along with our eFPGA technology to this groundbreaking initiative in low power computing."


QuickLogic's eFPGA technology is available now, as is ETH's PULP platform.  The fully integrated system with eFPGA is expected to be available Q1' 2019.

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SOURCE QuickLogic Corporation