Article thumbnail
Location of Repository


By Dong Wu, Bashir M. Al-Hashimi and Marcus T. Schmitz


The performance of Network-on-Chip (NoC) largely depends on the underlying routing techniques, which have two constituencies: output selection and input selection. Previous research on routing techniques for NoC has focused on the improvement of output selection. This paper investigates the impact of input selection, and presents a novel contention-aware input selection (CAIS) technique for NoC that improves the routing efficiency. When there are contentions of multiple input channels competing for the same output channel, CAIS decides which input channel obtains the access depending on the contention level of the upstream switches, which in turn removes possible network congestion. Simulation results with different synthetic and real-life traffic patterns show that, when combined with either deterministic or adaptive output selection, CAIS achieves significant better performance than the traditional first-come-first-served (FCFS) input selection, with low hardware overhead (&lt;3%)

Year: 2006
DOI identifier: 10.1145/1118299.1118310
OAI identifier:
Provided by: e-Prints Soton

Suggested articles


  1. (2002). A network on chip architecture and design methodology,&quot; ISVLSI, doi
  2. (1993). A survey of wormhole routing techniques in direct networks,&quot; doi
  3. (1992). Adaptive routing in meshconnected networks,&quot;
  4. (2004). DyAD - Smart routing for networks-on-chip,&quot; DAC, doi
  5. (2004). K a v a l d j i e v , doi
  6. (2003). Load distribution with the proximity congestion awareness in a network on chip,&quot; DATE, doi
  7. (2002). Networks on chips: A new SoC paradigm,&quot; doi
  8. (2004). On-chip networks: A scalable, communication-centric embedded system design paradigm,&quot; doi
  9. (2004). Packetization and routing analysis of on-chip multiprocessor networks,&quot; doi
  10. (2004). RASoC: A router soft-core for Networks-on-Chip,&quot; Designers Forum - DATE, doi
  11. (2001). Route packets, not wires: On-chip interconnection networks,&quot; DAC, doi
  12. (2004). Systemlevel design techniques for energy-efficient embedded systems,&quot; doi
  13. (2000). The odd-even turn model for adaptive routing,&quot; doi
  14. (2003). Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip,&quot; doi
  15. (2004). Xpipes: A network-on-chip architecture for gigascale systems-on-chip,&quot; doi
