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Subject: Re: IBM Nanotech news Date: 11/6/2012 4:56 PM
Recommendations: 3

Decimal point error. You get about 100x100=10,000 silicon atoms in a square surface 22x22 nm. Actually in litho, you get circles at minimum feature size, so 7855 +/- a few atoms. Fortunately for semi manufacturers, transistors are designed so that the process width only determines the width of the channel. Note that the channel consists of an oxide layer (now often containing halfnium, and less than 2 nm thick), with the gate electrode on top.


Three tricks. First, the masks are normally 4 times (in linear measure) the size of the chip being exposed. Second, you would need a mask to produce a mask, and in the early days masks were drawn by hand and photographically reduced. Today, electron beam writing is typically used to create the original masks (with normal resist processing and development). This pushes the cost of a mask set for a CPU up above a million dollars. (One mistake and throw that set away, or at least some masks in it. Worse, it will take months you don't have to get parts made with the next mask set. If the error is in one of the top layers you will save weeks.)

Third, see from my explanation of half-pitch that with (clever) biasing you can make lines one half the half-pitch, in between you will have gaps of 3/2 the half pitch. Use another mask, and put a second set of lines in there. This is called double patterning and is the way (AFAIK) everyone working at 22 nm is doing it. (Some are developing and etching between exposures, others are doing two exposures with one development and etch. Both have advantages and disadvantages.)

Way back at 0.13 microns (130 nm), some processes used AAPS (alternate aperture phase shift). Different parts of the masks caused different phase shifts in the light, and by making the mask the "right" thickness this could be used to create gaps between lines at the junction between two lines in the actual mask. AFAIK this is not used at all in the most recent processes. The problem with e-beam created masks is not creating lines fine enough, it is in eventually using ArF (193 nm) light to make fine enough lines on the wafer. There are lots of tricks in the OPC (optical proximity correction) book. Most of them require drawing patterns on the mask that have much smaller features than the eventual product. (Think of the serifs on small fonts that make them easier to read.) Fortunately e-beam technology can do this, but it is expensive. Doing multiple exposures to create an AAPS mask would push the cost way up.

Since we are now trying to create features at 22 nm, this means that, at the mask, the finest dimension we are trying to create is 88 nm, or about 1/3 the light wave length. So you get interference fringes all over the place. The mask makers do put in corrections in the mask set to create the finest possible mask, taking into account the interference between every piece of the final pattern. This used to be an expensive computation. It is getting cheaper all the time, even as process dimensions shrink. Each process comes with a set of design rules so that the designers of chips* create designs which the mask creation software can use to make designs with reasonable yields.

* Actually EDA software, this is way to much work for a single designer to do in a lifetime. However, a lot of engineers spend a lot of hours taking the list of problems spit back by the EDA software and changing the routing lists to fix them. The time schedule advantage is that you can split the error lists up among multiple engineers. What if two changes conflict? Repeat the process again, When you have a design with no conflicts this is called tape out. You still may have design errors and places that cause yield problems. So you typically go through (today) about three sets of masks between tape out and full production.
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