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OpenTLM: Tools for Virtual Systems-on-Chip


Project type


Project holder

STMicroelectronics Grenoble


INRIA Grenoble - Rhône-Alpes, Leti

Non-members Partners

Safetronix, Silicomp, VERIMAG, Thomson, TIMA - Techniques de l'Informatique et de la Microélectronique pour l'Architecture d'ordinateurs


Today, Systems-on-Chip (SoC) demand significant hardware and software development work. Software developers are highly dependent on hardware and are forced to wait until a functional prototype (e.g. on-chip circuit) is available before they can begin testing; in other words, they must wait until the circuit has been completed. Reducing lead times and allowing developers to begin work on virtual platforms (simulators) as quickly as possible are thus critical factors in boosting competitiveness.


Using SystemC and its extension TLM (two global standards developed by STMicroelectronics) it is possible to describe SoC and electronic systems at a higher level of abstraction than with languages such as VHDL/Verilog RTL. OpenTLM aims to make TLM (Transaction Level Modeling) accessible to software developers (embedded in SoC circuits and/or electronic systems) who are not hardware modeling experts. Used to perform rapid simulations of hardware platforms, these high-level descriptions can also be used to assess the effectiveness of an architecture, to test hardware functionalities, and, in some cases, generate circuit subassemblies (RTL).

Projet infos page d'un projet


11,821 K€


48 month

Human resources allocated

90 men/year