What number is it correct to divide by your ADC counts as a first step in converting counts to voltage? For example, in a 10 bit ADC, is it correct to divide by 1024 or 1023?

I have always divided by 1024, which means that a full count would yield less than full scale voltage reading. I think this is a more accurate representation of the hardware, though, since there is usually an LSB of error. This is also what I've read in every datasheet, as well as various DSP literature and white papers from ADI and TI. Please prove me right (or wrong) with the detailed reasoning why!

Links to lit: http://www.ti.com/general/docs/litabsmultiplefilelist.tsp?literatureNumber=slyw038b



  • $\begingroup$ please link the the literature you have read. $\endgroup$ – spet Oct 17 '18 at 15:13
  • $\begingroup$ Can you give an example where both may be correct and why? $\endgroup$ – montserrat Oct 17 '18 at 15:23
  • $\begingroup$ I am more of asking what is theoretically correct for an ideal ADC, with as much precision as you need, so you can assume FP. Also, I've always thought of it being your ADC's returned counts divided by the possible number of "steps"...hence 1024, instead of 1023 possible "values" that can be returned. $\endgroup$ – montserrat Oct 17 '18 at 15:30
  • $\begingroup$ stackoverflow.com/questions/892723/… $\endgroup$ – spet Oct 17 '18 at 15:36
  • $\begingroup$ @spet Yea, that thread references the literature I cited above. It's basically what I've always done, always read (in theoretical and datasheets), and what makes sense to ME. I just feel that I don't have as strong of a theoretical explanation to anyone on the 2^n-1 side of the debate. $\endgroup$ – montserrat Oct 17 '18 at 15:43

The correct answer depends on implementation and what you decide to call Full Scale; if the end points are included in the conversion mapping used, then the answer would be $2^n-1$ as I depict in the graphic below.

The easy way to see this is to consider a simple 3 bit converter which has 8 levels, for the conversion of a unipolar signal from 0 to 1V, where we specifically have mapped (in the design of the converter) 0V (+/- 1/2 lsb) to 000 and 1V (+/- 1/2 lsb) to 111:

3 bit mapping

Here we see clearly how with 8 levels the resulting mapping is given as

$$V_{out} = 1V\frac{b}{2^3-1}$$

where b is the digitized value of interest, in this case ranging from 0 to 7.

Because our digital range is inclusive of the end points of our voltage range, it would always be 1 less than the number of levels in this case.

Although not an ADC, but a counter example I could find showing the implementation dependence is A DAC implemented with an R-2R ladder (https://en.wikipedia.org/wiki/Resistor_ladder). This shows a mapping where a division of $2^n$ is used, and the full scale voltage IF based on the reference voltage used is never actually reached as an output of the DAC (but why not simply call "Full Scale" the voltage corresponding to the maximum digital value? - Here you see that it is simply a matter of how you decide to scale it).

  • $\begingroup$ is this unipolar or bipolar? and are we to assume that we want our scaled signal to be between -1 and +1? $\endgroup$ – robert bristow-johnson Oct 18 '18 at 1:33
  • $\begingroup$ no, we need to figger out what the issues are. then fix any misleading part. $\endgroup$ – robert bristow-johnson Oct 18 '18 at 1:38
  • $\begingroup$ even if it's not only a DAC or ADC context, this scaling is also an issue with MIDI control values that are either 0x00 to 0x7F (or if 14 bit, they go 0x0000 to 0x3FFF). what to do with that 0? some people make the 0x7F be the max (like +1), 0x40 is zero, and 0x01 is the min (like -1) and 0x00 maps to the same control value as 0x01. $\endgroup$ – robert bristow-johnson Oct 18 '18 at 1:41
  • $\begingroup$ Let us continue this discussion in chat. $\endgroup$ – Dan Boschen Oct 18 '18 at 1:46

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