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EDPIDR2, External Debug Peripheral Identification Register 2

The EDPIDR2 characteristics are:


Provides information to identify an external debug component.

For more information, see 'About the Peripheral identification scheme'.


Implementation of this register is OPTIONAL.

If FEAT_DoPD is implemented, this register is in the Core power domain. If FEAT_DoPD is not implemented, this register is in the Debug power domain.

This register is required for CoreSight compliance.


EDPIDR2 is a 32-bit register.

Field descriptions

The EDPIDR2 bit assignments are:


Bits [31:8]

Reserved, RES0.

REVISION, bits [7:4]

Part major revision. Parts can also use this field to extend Part number to 16-bits.

JEDEC, bit [3]

RAO. Indicates a JEP106 identity code is used.

DES_1, bits [2:0]

Designer, most significant bits of JEP106 ID code. For Arm Limited, this field is 0b011.

Accessing the EDPIDR2

EDPIDR2 can be accessed through the external debug interface:


This interface is accessible as follows:

  • When FEAT_DoPD is not implemented or IsCorePowered() accesses to this register are RO.
  • Otherwise accesses to this register generate an error response.