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Advancements in Nanoscale Manufacturing

Advancements in Nanoscale Manufacturing
by Paul McLellan on 04-10-2014 at 1:40 pm

 I’m at the GSA Silicon Summit today, at the computer history museum. The first panel session this morning was about future process technology. It was moderated by Joe Sawicki of Mentor with a panel consisting of Rob Aitken from ARM, Paul Farrar of G450C, Peter Huang of TSMC, John Kibarian of PDF Solutions and someone from Applied Materials whose name I didn’t note down but doesn’t appear in the program.

There have been two constants in semiconductor manufacturing. #1 is Moore’s Law and #2 is that two nodes out we run into a wall and it can’t be done. For instance, in 1986 “optical litho is dead”. How did that work out? But things are accelerating. Planar lasted for decades. Hi-K metal gate lasted for 2 nodes. FinFET just a few, maybe to 7nm, maybe not.

Since I am talking about it at EDPS next week, I was intrigued that the first topic was whether FD-SOI has any room to make a play. The general opinion is that it will have a place since it is already in production (at ST) but that FinFET has sucked up all the expertise. It takes too much effort to do a process generation and the large system companies have insisted that the foundry industry chase Intel in FinFET so the entire foundry industry (except ST) have consolidated on FinFET and that is what the whole ecosystem is focused on. If you do a new technology and your competitors do not, then you are vulnerable.

EUV: closer than in 2002 (which is not saying that much!). Most issues relate to manufacturing and being cost-effective, rather than technical. The economic challenge cannot be overcome. We are already looking at double patterning if it comes in for the 7nm or 5nm node.

There was a lot of discussion about whether 20nm and 16nm are cost reduction nodes. Everyone has seen the graphs showing that cost per transistor goes up but those charts assume parametric yields go down every process generation but they don’t. Everyone has learned and the customers work with the foundry for years now. Foundries have learned a lot about design. The IP and fabless companies have learned a lot about transistors. 3 years of work and then a 1-2 year product cycle and then on to the next node. Test vehicles are run much earlier, everyone is investing in the nodes earlier. The general opinion was that each of these nodes would, in fact, be a cost reduction.

What about 10nm? 7nm? FinFETs are probably running out of steam by then and we will need gate all-round for 7nm. Industry will look collectively and decide if we want horizontal nanowires and if we do they will happen.

What about the decline in the number of manufacturers? Is that a benefit or a liability? Even if the number of fabs is limited due to the cost of entry the ecosystem will exist around them. There are some advantages from focus (like everyone agreeing to FinFET) but also fewer things are being explored in R&D so some choices will turn out to be wrong or suboptimal. There is some variation such as gate-first vs gate-last, FinFET vs FD-SOI, Intel introducing FinFET at 22nm and everyone else at 14/16nm. But not as much as there used to be. And a cynic would say that 16nm is actually a variant of 20nm with different transistors. Node names for sure do not make sense.

The then chairman of PDF solutions 12 years ago said “it will eventually come down to a competition of countries” and it is clear that we are close to that stage now. TSMC in Taiwan (with all sorts of tax breaks from the government), GF in US (with tax breaks from NY state), Samsung in Korea (probably with all sorts of government support too). Of course there are fabs in other places (GF in Singapore and Germany, Samsung in Texas etc).

 What about 450mm wafers? Low power is the driver of process today whereas 450mm is purely about cost reduction. So it depends on if and when the industry decides that there is an acute need for cost reduction. There need to be a lot of fully loaded fabs ready to replace all the equipment. But one big issue I’ve commented on before is that lithography scaling with wafer size does not work. Twice the area takes twice the time and about 80% of the cost is in tools that process die by die not wafer-at-a-time. So as long as Moore’s law is scaling every couple of years 450mm is not needed. If it slows to 4 years and demand for transistors continues to increase then it will not be economical not to switch to 450mm. But decisions need to be made soon to intercept the future.

But, like in Hollywood, nobody knows anything. 15 years ago if you said we would all be using double patterning, FinFETs, gating every power domain and so on then you’d have been laughed out of the room. But that is where we are.

The challenges we face are maybe easier than other parts of the electronic ecosystem. Will batteries improve in capacity by 10X? Probably not. Will transistors consume 10 times less power? Maybe.

It has been estimated that 40% of GDP growth is due to Moore’s Law. That is maybe $500B a year. So the leverage is huge to increase the spend to keep things on track.

More articles by Paul McLellan…


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