Why are so many pins of 8086 active-low? Does it have to do something with the fact that more circuits are able to sink current than to source current, or is there another reason for it?

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    \$\begingroup\$ putting all the great answers here aside, active low is IMO easier to implement in physical design of an application - you only have to supply a connection to GND, instead of a voltage line; in many situations, it's actually easier and safer to pull the line down instead of up (see switches etc.). \$\endgroup\$
    – user20088
    Dec 10 '16 at 18:57
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    \$\begingroup\$ It was a secret plot to sell inverter ICs... ;-) \$\endgroup\$
    – Ecnerwal
    Dec 11 '16 at 3:54
  • \$\begingroup\$ So many? The 8086 has 37 signal pins, of which only 4 are dedicated active low. \$\endgroup\$ Dec 11 '16 at 18:54

In the TTL era, active low was the standard.

The old NMOS parts like the 8086 were designed in that time period- note that the input levels are TTL-compatible Vih=2.0V and Vil=0.8V.

Active-low allows wired-OR with open collector/drain outputs (you may have noticed that calling it 'wired-OR' implies negative logic).

Also, the NMOS parts were almost like RTL except the pull-up resistors (loads) were depletion mode n-channel MOSFETs so the negative edges would tend to be sharper with capacitive load. There are no p-channel parts in this technology (which made it simpler and thus higher yield)

CMOS parts (originally 4000 series) were not designed to be TTL compatible and generally have active-high inputs. The 74C/74HC etc CMOS parts derived from similar TTL functions tend to have active-low inputs. Remembering this difference can serve you even today- if you need a flip-flip with active high clear input you are more likely to find it in a 4xxx or 74HC4xxx part than in a 74HCxx part such as 74HC74.

  • \$\begingroup\$ You missed the meat and potatoes: power draw. RTL, TTL and NMOS all had this quirk: a line pulled low draws a lot of power but a line left high draws no power. CMOS, on the other hand, only draw power when switching, allowing for symmetric design and thus a split across active-low and active-high. \$\endgroup\$ Dec 10 '16 at 23:42
  • \$\begingroup\$ @MaxthonChan True, of course, but I'm not sure how that's relevant to the question. The inputs are high impedance. The chip draws about 1/3 of an ampere just sitting there so I don't think a few uA from input high or low matters much. \$\endgroup\$ Dec 10 '16 at 23:51
  • \$\begingroup\$ It is the output stages drawing power when low. \$\endgroup\$ Dec 10 '16 at 23:52
  • \$\begingroup\$ @MaxthonChan Output current is 400uA at 2.4V, not very much compared to 340-360mA. I doubt they gave that aspect much thought. \$\endgroup\$ Dec 11 '16 at 0:01
  • \$\begingroup\$ It adds up with a lot of transistors in the chip. Multiply that current draw by the transistor count and you get a toasty chip. \$\endgroup\$ Dec 29 '16 at 11:19

In some technologies, it's easier to make a N channel FET with more current capability than a P channel FET.


The 8086 pre-dates (fast, low voltage) CMOS logic. It's built in NMOS technology, with NMOS transistors (which, like NPN transistors, make good pull-downs) and ... I'm not sure what it used as pull-ups, possibly more NMOS transistors which, in that role, make slow, low current pull-ups.

So, analogous to contemporary TTL logic - which was used for much of the support logic, it was designed to the limitations of the available transistors, which meant critical signals were pulled down, and active low logic was easier to use for them.


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