Stratix FPGA discontinued June 1st, 2017

Volume 1 (ver 3.4, Jan 2006, 3 MB)

Section I. Stratix Device Family Data Sheet

Volume 2 (ver 3.5, Jun 2006, 6 MB)

Section I. Clock Management

Section II. Memory

Section III. I/O Standards

Section IV. Digital Signal Processing (DSP)

Section V. IP & Design Considerations

Section VI. Configuration & Remote System Upgrades

Section VII. PCB Layout Guidelines

Application Notes

Following are the most frequently asked questions about Stratix devices.




Digital Signal Processing Blocks

System Clock Management

I/O Standards & Termination

Device Configuration

Nios® II Embedded Processors

Software & Intellectual Property


What is the Stratix device family?

The Stratix device family offers a 50% average push-button performance increase over previous architectures. In concert with the Logic Lock Region design methodology available in the Quartus® II software, Stratix devices simplify the difficult design integration process, providing the basis upon which block-based designs can be developed and optimized for maximum performance. Stratix devices offer features such as up to 7 Mbits of embedded TriMatrix memory, DSP blocks, and Terminator technology. Based on a 1.5-V, 0.13-µm, all-layer-copper process technology, Stratix devices give designers the capability to develop flexible solutions in high-bandwidth applications while minimizing precious time to market.

What densities, packages, and speed grades will be available?

Stratix devices are offered in seven densities from 10,570 to 79,040 logic elements (LEs) and various packages and speed grades as outlined on the Stratix device overview page.

When will Stratix devices be available?

All seven members of the Stratix FPGA family are production qualified and available today. For more information on device availability, refer to Table 1 of the Stratix device overview page.

How many system gates are available in Stratix devices?

Stratix devices, when enumerated using historical gate-counting methodologies, range in system gate density from 4 to 43 million gates. However, as FPGAs become more and more complex, it becomes increasingly difficult to represent logic density, advanced features, and memory blocks using system gates as a single unit of measure because they do not follow a defined, FPGA industry standard. Disproportionate growth in embedded memory and LEs leads to unbalanced weighting in gate enumeration and ultimately to misleading density representations. An LE-based nomenclature facilitates better device selection and avoids confusion. Therefore, Stratix device densities are represented using an LE-based nomenclature that more accurately communicates the logic capacity of FPGAs.

How do Stratix device ordering codes relate to their respective densities?

Stratix device ordering codes are an approximation derived from the number of available LEs in the device. For example, the second smallest Stratix device, which has 18,460 LEs, is named the EP1S20 device.

Are Stratix devices drop-in compatible with any other device families?

Stratix devices are not drop-in compatible with older device families. Because the Stratix device family is an entirely new architecture built from the ground up with exciting new features, capabilities, and package offerings, new pin-outs were developed to support these enhancements. Customers can easily re-target their designs for Stratix devices using third-party EDA development tools and the Quartus II software.


What is the difference between push-button and optimized performance?

Push-button performance refers to the maximum system frequency that designers achieve with an existing design, when they use only the performance-enhancing options that are available in the Quartus II software. In contrast, optimized performance involves the combination of the performance-enhancing options in the Quartus II software and manual design optimization techniques that are applied before and after the initial place-and-route. The original design may also be altered to more closely match the targeted architecture to take full advantage of any device family-specific features that are available in the device.

What is the MultiTrack interconnect?

The MultiTrack interconnect is a continuous routing structure that provides high-speed connectivity between logic resources, TriMatrix memory, DSP blocks, and I/O structures using column- and row-based routing lines of varying lengths. These lines ensure fast, consistent signal propagation and predictable timing results within and between design blocks. The Quartus II software intelligently prioritizes signals so that design-critical paths are routed on faster lines to accelerate performance.

What is DirectDrive technology?

DirectDrive technology is a proprietary, deterministic routing technology that ensures identical routing resource usage for any function regardless of its placement within the device. This greatly simplifies the system integration stage of block-based designs by eliminating the often time-consuming system re-optimization process that typically follows design changes and additions. Signals within each region propagate at the same rate, regardless of the degree of logic resource usage in surrounding areas. For this reason, designers can freely add, modify, and move various portions of their design without negatively affecting design performance, fittability, or functionality.


What is TriMatrix memory and what features does it support?

The TriMatrix memory is a revolutionary memory structure that offers up to 7 megabits of storage capacity and 8 terabits per second of total memory bandwidth and consists of an array of three sizes of memory blocks, each optimized to target a different class of applications. The integration of the 512-Kbit M-RAM blocks with several smaller M512 and M4K blocks provides a unique solution to applications requiring either large amounts of memory bits or high memory bandwidth. For example, M512 blocks can be used for small functions such as first-in first-out (FIFO) applications, M4K blocks can be used to store incoming data from multi-channel I/O protocols, and 512-Kbit M-RAM blocks can be used to store Nios microprocessor code or other storage-intensive applications such as IP packet buffering. All memory blocks include extra parity bits for error control, mixed-width mode, and mixed-clock mode support. Additionally, the M4K and M-RAM blocks support true dual-port mode and byte masking for advanced write operations.

Why have Stratix devices been designed with so much memory in non-uniform block sizes?

Next-generation system speeds have been steadily outpacing internal processing power, resulting in a growing need for buffering and on-chip storage. To address this, Stratix devices were designed with a 4x increase in the logic-to-memory ratio over previous-generation architectures, an increase that was achieved by integrating area-efficient M-RAM blocks. The total number of data ports is as important as the total number of memory bits, as this parameter determines the maximum memory bandwidth in the device (an increasingly important measure of performance as systems continue to accelerate). By adding a large number of M512 and M4K blocks, the effective number of ports is increased in the device, allowing greater movement of data in and out of the memory blocks for processing.

Digital Signal Processing Blocks

What are DSP blocks and what are they capable of?

The DSP blocks in Stratix devices are high-performance embedded processing units that are optimized for applications such as rake receivers, voice over Internet protocol (VoIP) gateways, orthogonal frequency division multiplexing (OFDM) transceivers, image processing applications, and multimedia entertainment systems. The DSP blocks eliminate performance bottlenecks in DSP applications, provide predictable and reliable performance, and result in resource savings without compromising performance. Input, output, and optional intermediate pipelining registers are available in each block for pushing performance levels to over 300 MHz and bandwidth capabilities to 2.4-GMAC operations per second.

What benefits are associated with this type of DSP block architecture?

The Stratix device family's DSP blocks provide customers with many benefits in both performance and resource usage. The processing capabilities of FPGAs outperform industry-standard DSP processors in computation-intensive applications that require parallel operations or time-domain multiplexing (TDM). Since both the multiplication and subsequent accumulation/addition/subtraction stages are completely isolated within the DSP block, performance is determined independently of the remainder of the chip's usage. Resources for the various stages of the DSP block are not shared with the general-purpose portion of the device; therefore, whether the device is 99% or 10% consumed, block performance will remain the same.

System Clock Management

How many PLLs are embedded in Stratix devices?


How many types of PLLs are available in Stratix devices?

Stratix devices support two types of PLLs: enhanced PLLs and fast PLLs, both of which provide advanced frequency synthesis capabilities.

What PLL features are available?

Enhanced PLLs are feature-rich and can be used for general-purpose applications, supporting advanced capabilities such as external feedback, clock switchover, phase and delay control, PLL reconfiguration, spread-spectrum clocking, and programmable bandwidth. Fast PLLs offer high-speed outputs to manage high-speed differential I/O interfaces, as well as other general-purpose clocking management capabilities such as clock multiplication and phase shifting.

I/O Standards & Termination

What high-speed differential I/O electrical standards are supported in Stratix devices?

With proven expertise in high-speed differential I/O design, we continue support for LVDS, PCML, HyperTransport, and LVPECL in Stratix devices. Our differential I/O solution, unlike any other in the programmable logic industry, uses dedicated, high-speed circuitry to maximize device throughput. This includes optimized transmitter and receiver I/O buffers, serialization/deserialization circuitry, high-performance fast PLLs, and enhanced byte alignment capabilities. Up to 152 channels are available on each device, 80 of which are optimized for 840-Mbps performance.

What high-speed I/O interfaces are supported in Stratix devices?

Stratix devices support many of the latest high-bandwidth bus protocols, including the SPI-4 Phase 2 (POS-PHY Level 4), SFI-4, 10 Gigabit Ethernet XSBI interface (16 bit), HyperTransport, RapidIO, common switch interface (CSIX), and UTOPIA Level IV protocols. A single Stratix device can simultaneously support up to four distinct high-speed I/O interfaces for applications such as interface bridging, backplanes, chip-to-chip communications, and other subsystems.

Which external memory interfaces do Stratix devices support?

The Stratix device family external memory interface solution meets the performance requirements of the latest synchronous random access memory (SRAM) and synchronous, dynamic random access memory (SDRAM) devices, as shown in Table 1. External memory devices can be easily connected to Stratix devices without causing performance bottlenecks, and provide additional storage capacity outside of abundant on-chip TriMatrix memory resources. Designers can purchase IP memory controller cores from us or our partners, download royalty-free reference designs from our web site, or develop their own customized cores for their specific applications.

Memory Device Type Supported Clock Speed Maximum Data Transfer Rate
Single Data Rate (SDR) SDRAM 200 MHz 200 MHz
Double Data Rate (DDR) SDRAM 200 MHz 400 Mbps
DDR Fast Cycle (DDR FCRAM) 200 MHz 400 Mbps
Zero Bus Turnaround (ZBT) SRAM 200 MHz 200 Mbps
Quad Data Rate (QDR) SRAM 167 MHz 668 Mbps
QDRII SRAM 167 MHz 668 Mbps

Device Configuration

What is the remote system upgrade feature?

The remote system upgrade feature allows designers to reconfigure Stratix devices from a remote source, saving time and costs while extending the product's lifespan. New application data can be sent to a system from a remote source, saved to an external memory device such as an advanced configuration device, and subsequently used to reconfigure the Stratix device. The Stratix device includes dedicated circuitry that ensures successful configuration using the new application data. If an error were to occur, the Stratix device automatically initiates re-configuration from the external memory device using safe, bug-free factory-configuration data. With Stratix devices, designers can now safely deploy system upgrades or bug fixes without the time-consuming process of visiting all locations to perform a manual re-configuration.


Nios II Embedded Processors

Do Stratix devices support the Nios II embedded processor?

Stratix devices support the Nios II embedded processor, offering significant performance improvements over previous architectures. Stratix devices feature continued support for current Nios features such as the simultaneous multi-master Avalon™ bus, custom instruction capabilities, and advanced debugging solutions.

Software & Intellectual Property

What version of software will support Stratix devices?

The Quartus II software, version 2.2 service pack 1 supports all Stratix devices. With new enhancements such as the SignalProbe™ feature, Linux support, and the fast fit compiler option, designers have a truly integrated, single platform development tool that minimizes overall development time. The advanced PowerFit™ technology optimally places and routes designs resulting in efficient resource usage and maximized performance.

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