This work presents two low-power Secure Hash Algorithm-3 (SHA-3) designs on Field Programmable Gate Array (FPGA) using embedded Digital Signal Processing (DSP48E) slice, one for area constrained environments and the other for high-speed applications. The seven equations of SHA-3 are logically optimized to three and four stage pipelined organizations for our compact and high-speed designs, respectively. The maximum parallelism between all the bitwise operations of different stages of SHA-3 is explored with respect to the 48-bit structure of DSP slice. Further Logical Cascade Structure (LCS) design strategy is proposed in accordance with the DSP slice organization. These optimizations result in saving of resources and at the same time achieve low-power with high performance. Our compact design results in saving of 79.10% DSP slices and consumes only 1/7 th of power while 1600-bit DSP design provides 23.57 Gbps throughput and consumes only 1/5 th of power as compared to the conventional SHA-3 designs. 
A low-power SHA-3 designs using embedded digital signal processing slice on FPGA