Three dimensional integrated circuits (3D ICs) can alleviate the problem of interconnection, a critical problem in the nanoscale era, and are also promising for heterogeneous integration. This paper proposes a two-phase method combining the ant system algorithm (AS) and simulated annealing (SA) to handle 3D IC floorplanning with fixed-outline constraints. In the first AS phase, the floorplans are constructed by sequentially packing the block one by one, and the AS is used to explore the appropriate packing order and device layer assignment for the blocks. When packing a block, a proper position including the coordinates and the appropriate layer in the partially constructed floorplan should be chosen from all possible positions. While packing the blocks, a probability layer assignment strategy is proposed to determine the device layer assignment of unpacked blocks. After the AS phase, the SA phase is used to perform further optimization. The proposed method can also be easily applied to 2D floorplanning problems. Compared with the state of the art 3D/2D fixed-outline floorplanner, the experimental results demonstrate the effectiveness of the proposed method. 
Combining the ant system algorithm and simulated annealing for 3D/2D fixed-outline floorplanning