This work studies a digital hardware implementation of a radial basis function neural network (RBF NN) Firstly, the architecture of the RBF NN, which consists of an input layer, a hidden layer of nonlinear processing neurons with Gaussian function, an output layer and a learning mechanism, is presented. The supervising learning mechanism based on the stochastic gradient descent (SGD) method is applied to update the parameters of RBF NN. Secondly, a very high-speed IC hardware description language (VHDL) is adopted to describe the behavior of the RBF NN. The finite state machine (FSM) is applied for reducing the hardware resource usage. Thirdly, based on the electronic design automation (EDA) simulator link, a co-simulation work by Simulink and ModelSim is applied to verify the VHDL code of RBF NN. Finally, some simulation cases are tested to validate the effectiveness of the proposed digital hardware implementation of the RBF NN. 
Digital hardware implementation of a radial basis function neural network