the research center Q develop new multicore processor the processor consist n core k cell cache memory consider work processorAt cycle core processor get instruction number memory cell core write information cell after receive command core execute immediately sometimes happen cycle multiple core try write information single cell unfortunately developer foresee possibility resolve conflict core case deadlock core correspond memory cell lock forever each lock core ignore command core future able record information lock cell if core tries write information lock cell immediately lockedThe development team want explore deadlock situation therefore need program simulate processor give set instruction core m cycle you re lucky interesting work entrust accord instruction m cycle define core number cycle lock it believe initially core memory cell lock