METHOD AND APPARATUS FOR COMPENSATING FOR TIMING VARIANCES IN DIGITAL DATA TRANSMISSION CHANNELS
A high-speed digital interface circuit for use with an N bit digital data signal is disclosed. The circuit comprises a source device (12) that initially receives the N bit digital data signal, and a sink device (14) that receives the N bit digital data signal from the source device (12). The N bit digital date signal has a skew when received by the sink device (14). A detection circuit in the sink device (14) detects the skew in the N bit digital data signal and generates a skew detection signal. A line (28) supplies the skew detection signal to the source device (12). A compensation circuit in the source device (12) receives the skew detection signal and compensates for the skew in the N bit digital data signal.