VHDL implementation of two-state multiple turbo codes
With increasing demand for different data rates and services for communication systems, reconfigurability is of utmost importance. Field Programmable Gate Arrays (FPGAs) provide the flexibility in operation and function by a simple change in the configuration bit stream. Low complexity turbo-like codes based on simple two-state trellis or simple graph structure results in decoder with low complexity. Two-state multiple turbo code is one such example. In this paper, we present the VHDL implementation of a 2-state multiple turbo code architecture targeted towards the Xilinx Vertex-5 FPGAs and compared its implementation with 8-state 3GPP turbo code in terms of hardware complexity and speed.