Ultra-Low power and highly-scalable interfaces for the internet of things
The era of the Internet of Things (IoT), in which every physical entity includes power-autonomous embedded electronics, capturing relevant information by sensors and interacting with objects and humans in a globally interconnected network, is bringing about new challenges in Integrated Circuit (IC) design. The performance of ICs in terms of integration density, power consumption and cost, in fact, is the only limiting factor to the feasibility and/or to the widespread diffusion of IoT-based solutions.
Digital ICs in the most recent nanoscale CMOS technologies are keeping the pace of IoT requirements. On the contrary, the implementation of analog functions, which are however essential to acquire data from sensors, thus enabling the interactions of IoT nodes with the surrounding environment, is nowadays the real bottleneck and the most serious concern and limiting factor for the further development of IoT applications.
In the foreseeable future, the planned device scaling and voltage reduction down to near threshold (e.g. 0.4-0.5V) makes the design of analog circuits extremely hard, in view of the degradation of signal-to-noise ratio, matching and linearity. Despite of device shrinking, traditional low-voltages analog circuits do not really scale down in size, and occupy a more and more relevant percentage (i.e., cost) of the die area.
In this scenario, the proposed research activity is intended to substantially enhance the scalability of analog blocks with technology and voltage by re-thinking analog functions in ICs in digital terms. In a new cross-domain approach, design and testing methodologies from the digital world will be extended and frontier design concepts like near-threshold operation further exploited.
The effectiveness of the proposed approach will be verified and validated on IC demonstrators and with reference to a full SoC for wearable electronics applications in the development of novel IoT solutions.