Flip flop supporting glitchless operation on a one-hot bus and method
A flip flop includes a master portion operable to latch at least one of an input signal and an inverted input signal. The flip flop also includes a slave portion operable to latch at least one of the signal latched by the master portion and an inverted signal latched by the master portion in response to a first phase of a clock signal. The slave portion is also operable to be reset in response to a second phase of the clock signal.