A CMOS pixel sensor with 4-bit column-parallel self-triggered ADC for the ILC vertex detector
This paper presents a CMOS Pixel Sensor (CPS) prototype for the outer layers of the future International Linear Collider (ILC) vertex detector. It is composed of a matrix of 48 × 64 pixels with a 4-bit column-parallel analog-to-digital converter (ADC). The pixel concept combines in-pixel amplification with a correlated double sampling (CDS) operation in order to reduce the temporal and fixed pattern noise (FPN). The self-triggered ADC accommodating the pixel readout in a rolling shutter mode completes the conversion by performing a multi-bit/step approximation. The ADC design was optimized for power saving at sampling frequency. Accounting the fact that in the outer layers of the ILC vertex detector the hit density is in the order of a few per thousand, this ADC works in two modes: active mode and inactive mode. The average energy and total capacitance are significantly reduced by a power-gating control and a switching network, respectively. The prototype sensor was fabricated in a 0.35 μm CMOS process with a pixel pitch of 35 μm. The designed 4-bit ADC dissipates, at a 3-V supply and 6.25-MS/s sampling rate, 486 μW in its inactive mode, which is by far the most frequent. This value rises to 714 μW in case of the active mode. Its footprint amounts to 35 × 545 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .