LEVEL-SHIFTER FOR EXTREMELY LOW POWER SUPPLY
An improved level shifter circuit is provided which is designed for use with an extremely low power supply voltage. The level shifter circuit includes a fourth NMOS transistor (N102), a third PMOS transistor (P103), and a fifth NMOS transistor (N103) connected in series and interconnected between the high voltage and the output terminal. As a result, the high voltage will still be passed to the output terminal when the high voltage is lowered to be equal to the low power supply voltage.