HIGH LEVEL SYNTHESIS FOR DESIGN SPACE EXPLORATION
In VLSI, design space exploration considering various constraints complex using conventional RTL design flow. The techniques of high level synthesis are useful in abstracting the design to a higher level than in the regular RTL design flow. The various hardware architectures possible need to be explored to bring out the design trade-offs in terms of parameters namely latency, critical path delay and resource utilization. The focus of the work presented here is to explore systolic array mapping methods with and without HLS transformations. Unfolding and pipelining are the HLS transformations applied on the DSP benchmark –FIR filter. Unfolding enhances the possibilities of concurrency in loops and pipeline architecture makes concurrency possible. Vivado HLS tool is used to explore the design space for random subspace mapping and computational subspace mapping and analyze their merits and demerits in terms of the design tradeoff performance parameters when the design is mapped to Zynq architecture.