Evaluation of novel ultra-fast selective iii-v epitaxy
As the worldwide photonics market is increasing and optical and electronic devices based on III-V semiconductors are gaining market segment, the production of III-V semiconductor wafers including GaN has increased in volume  and sizes have increased from 2” to 6”. However, this is still short of the 8”-12” common in Silicon CMOS technology. Furthermore, the integration of III-Vs on silicon or on-insulator, has been a long-standing goal for the past 50 years, in order to combine electronic and photonic applications, and to allow photonic technologies to take advantage of the highly developed silicon CMOS technology, thereby opening up for vast new application opportunities. The aim of ENUF is for the first time to attempt to combine two different growth methods to achieve a low-cost integration of large-area III-V on insulator on a silicon platform, and to establish this as a replacement technology for existing III-V wafer production or to enable low-cost integration of optically active material as enabling technology for silicon photonic applications. The method can also be adapted to GaN on Si or on insulator for low-cost high-volume production of high power electronics and light emitting devices.