INTEGRATED CIRCUIT WITH REDUCED POWER CONSUMPTION HAVING A ONE WIRE COMMUNICATION INTERFACE
The invention relates to an integrated circuit (20) comprising a binding post (11) for receiving a data-carrying electrical signal (DT) and means (CEC1) for delivering a first clock signal (CK1) consisting of clock pulses emitted after each falling edge of the data-carrying electrical signal inside a data sampling window. According to the invention, the integrated circuit comprises means (CEC2) for delivering a second clock signal (CK2) consisting of clock pulses emitted only when the data-carrying electrical signal (DT) is at the high level and data-processing means (PCC, REGB, MEM), which are synchronised by the second clock signal (CK2). Thanks to the invention, it is possible to power the integrated circuit using an electric voltage present at the binding post.