Software-managed Cache Coherence for fast One-Sided Communication
The ongoing many-core design aims at core counts where cache coherence becomes a serious challenge. Therefore, this paper discusses how one-sided communication can be implemented on a non-cache coherent many-core CPU. The Intel SCC serves as an exemplary hardware architecture. The presented approach is based on software-managed cache coherence for MPI one-sided communication. The prototype implementation delivers a PUT performance of up to five times faster than the default message-based approach and reveals a reduction of the communication costs for the NPB 3D FFT by a factor of five. Further, the paper identifies drawbacks of the SCC's architecture and derives conclusions for future architectures.