Design of a 32-bit, dual pipeline superscalar RISC-V processor on FPGA
A 40 MHz, 32-bit, 5-stage dual-pipeline superscalar processor based on RISC-V Instruction Set Architecture is presented. It supports integer, multiply-divide and atomic readmodify-write operations. The proposed system implements inorder issuing of instructions. The design incorporates a dynamic branch prediction unit, memory subsystem with virtual memory, separate instruction cache and data cache, integer and floating point execution units, interrupt controller, error control module, and a UART peripheral. The interrupt controller supports four levels of preemptive priority, which is programmable for individual interrupts. Error control module provides single error correction and double error detection for the main memory. Wishbone B.3 bus standard is adopted for on-chip communication. The processor is implemented on Virtex-7 XC7VX485TFFG1761-2 FPGA based board. CoreMark and Dhrystone benchmark values for the design are 3.84/MHz and 1.0603 DMIPS/MHz respectively.