A study of surface condensation defect improvement after cryogenic implantation
For USJ engineering, cryogenic implantation is proposed for the reduction of dopant TED effect (i.e., Xj reduction) and the reduction of EOR defect formation. (i.e., less dopant deactivation)1 However, condensation defects are formed during the wafer warm up period due to the temperature of the cold wafer surface, and this impacts the device electrical performance. In this study, we use a heater lamp and post N 2 purge function to improve the lower wafer temperature issue after the cryogenic implantation process. In order to minimize the wafer to wafer temperature difference, we can adjust the wafer cassette elevator position and post N 2 purge time. Turn-on heater lamp 8min with elevator position at slot14 and post N 2 purge 40min, we can improve the wafer surface temperature to ∼23°C with wafer to wafer temperature range ∼0.6°C. The wafer surface temperature after the heater lamp function is close to room temperature implantation and it would be benefit to suppress the surface condensation defects formation.