Reliability of TSV interconnects: Thermal shock and mechanical properties
With the trend of electronic products towards miniaturization and multi-function, integrated circuit (IC) is facing severer challenges in reducing package size, expediting responses and providing additional functionalities. 3-dimensions (3D) IC based on Through-Silicon Vias (TSVs) has nowadays become the most promising technology to overcome the obstacles, as the vertical stack of chips using TSV can satisfy the need of higher bandwidths and smaller footprints. Continuous development of TSVs leads to a persisting demand for their reliability investigations, which of course include the thermal shock test. It is commonly accepted that the coefficient of thermal expansion (CTE) mismatch between Cu-TSV and Si-chip can result in residual stresses in each material and interfacial shear stresses near the extremities of the via during a thermal excursion, therefore, it is necessary to study the effects of thermal shock on TSVs. In this paper, TSV samples are exposed to thermal shock for different cycles. After thermal shock, microstructure of TSV is analyzed. The intrusion of Cu under low cycle, which is distinct from results of other studies, has been found. In addition, hardness of TSV is tested.