Analysis of Reconfigurable Multipliers for Integer and Galois Field Multiplication based on High Speed Adders
Abstract Multiplication is indeed the most crucial operation in digital signal processing (DSP). Its implementation requires large hardware resources and significantly affects the size, performance, and power consumption of a DSP system. Several DSP algorithms require different types of multiplications, specifically integer or Galois field (GF) multiplication. Since both functions share similarities in their structures, it is better to combine both circuits in a single circuit. In this paper, various reconfigurable multipliers for integer and Galois field multiplication will be analyzed and discussed in detail. A comparative study of these architectures with the proposed architectures based on high speed Shannon adder is made. Such study shows area savings of up to 10% at a marginal reduction in delay and power around 3% compare to the conventional adder based reconfigurable structures. From this perspective, function-specific reconfigurable circuits based on high speed Shannon adder can be considered feasible alternatives to standard ASIC solutions.