HDL model simulation-based verification in a VHDLVisualizer visualization environment
Throughout the world, many VHDL (Very-high-speed integrated circuit Hardware Description Language) simulators exist, but only a few of them support the visualization of VHDL model simulation. The simulation is most commonly displayed as a waveform. This representation of the visualization is sufficient for the verification of the model, however it is hard-to-read for novice designers and it is difficult to identify the potential errors. In this paper, we present our progress in developing a visualization environment, which is able to display the simulation in the structural sphere of the model. During the simulation visualization, the designer is able to switch between hierarchic levels of the structure and watch how the signal changes directly in the component that he/she wishes to verify. Keywords: Vhdl, visualization, simulation, model, environment;