MEMORY DEVICE
A first DRAM device (11) comprises a first input connected to a first trace line (21) to receive an address signal and a second input is connected to receive an operating voltage, such as Vdd. A second DRAM device comprises a first input connected to the first trace line (21) to receive the address signal and a second input to receive the operating voltage. A first signal termination structure (20) is connected to the first trace line, wherein the first signal termination structure is to terminate the first trace line to the operating voltage.