STUB MINIMIZATION FOR MULTI-DIE WIREBOND ASSEMBLIES WITH PARALLEL WINDOWS
A microelectronic package 10 can include a substrate 20 having first and second surfaces 21, 22 and first and second apertures 26a, 26b extending therebetween, first and second microelectronic elements 30a, 30b each having a surface 31 facing the first surface, terminals 25a exposed at the second surface in a central region 23 thereof, and leads 40 electrically connected between contacts 35 exposed at the surface of each microelectronic element and the terminals. The apertures 26a, 26b can have first and second parallel axes 29a, 29b extending in directions of the lengths of the respective apertures. The central region 23 of the second surface 22 can be disposed between the first and second axes 29a, 29b. The terminals 25a can be configured to carry address information usable by circuitry within the microelectronic package 10 to determine an addressable memory location from among all the available addressable memory locations of a memory storage array of at least one of the microelectronic elements 30a, 30b.