Technology advances for pilotline of enhanced semiconductors for 3nm
In line with industry needs, Moore’s law, scaling in ITRS 2013, and ECSEL JU MASP 2017, the main objective of the
TAPES3 project is to discover, develop and demonstrate lithographic, metrology, EUV mask technology, devices and process modules enabling 3nm node technology. This is planned with available EUV/NA 0.33 scanners, and with system design and integration of a new hyper NA EUV lithography tool to enable more single exposure patterning at 3nm to create complex integrated circuits. Process steps for 3D devices as alternative to the conventional FINFet will be explored for application in the 3nm node. The impact of the application of these so called 3D devices  on circuit topology and logic design will be explored. During the development, specific challenges in metrology for the characterization of 3D devices will be assessed and metrology tools will be newly developed. The result will be demonstrated in the imec pilot line.
The TAPES3 project relates to the ECSEL work program topic Equipment, Material and Manufacturing. It addresses and targets, as set out in MASP, the grand Challange of ""More Moore Equipment and Materials for sub 10nm technologies"" by exploring the requirements and solutions for the 3nm node. The project touches the core of the continuation of Moore’s law. Moreover, the cost aware development process will support the involved companies, and will place them in a preferred position over their worldwide competition. Through their worldwide affiliations, the impact of the TAPES3  project will be felt outside Europe in America and Asia Pacific semiconductor centers and is expected to benefit the European economy a lot by supporting its semiconductor equipment and metrology sectors with innovations, exports and employment.