Forward slice core
There are two major flavors of processor core microarchitectures, namely the in-order core and the out-of-order core. Out-of-order processors deliver high performance while incurring high design complexity, large chip area and high power consumption. In-order processors on the other hand feature low complexity, small chip area and low power consumption, but deliver limited performance. There is a clear need for a novel core microarchitecture that delivers high performance at low hardware complexity, low cost and low power consumption. This is of particular interest for mobile and edge devices (e.g., tablets, smartphones, smartwatches, etc.) where increasingly high performance is needed at low cost and low power consumption. The mobile and edge device market is a huge market which continues to grow. High-performance out-of-order processors are too costly and too power-hungry, while in-order processors deliver insufficient performance for the increasingly high-performance demands of emerging mobile and edge workloads and use cases.

We propose a novel core microarchitecture, called the Forward Slice Core (FSC) microarchitecture, which provides high performance at low cost and low power consumption. FSC achieves a dramatic improvement in efficiency by replacing the expensive and high-complexity out-of-order hardware with much simpler in-order hardware queues into which instructions are intelligently steered for high performance using the notion of a load's forward slice. FSC has the potential to improve performance per Watt per euro by at least an order of magnitude. 

The overall objective of this PoC project is to build a strong benchmarking and IPR portfolio to convince potential processor manufacturers to license the Forward Slice Core microarchitecture. The project will strengthen the evaluation of the FSC proposal through simulation and real-hardware implementation, and develop a licensing strategy for commercialization.