PLL circuit and optical communication reception apparatus
The invention provides a PLL circuit (10) wherein, even if the duty ratio of an input signal varies, the convergence time required for frequency detection of a frequency detection circuit (12) is short and wrong operation of the frequency detection circuit (12) with a control signal is less likely to occur. A clock generator (17) produces, based on an oscillation frequency clock of a VCO (16), a first clock signal (ICLK) of the same phase, a second clock signal (QCLK) having a phase delayed by 90 degrees from that of the first clock signal, and a third clock signal (I'CLK) having a phase delayed by 45 degrees from that of the first clock signal. A phase detection circuit (11) performs phase control based on the phase difference between the third clock signal and an input signal, and a frequency detection circuit (12) fetches the first and second clock signals in synchronism with the input signal and performs frequency control based on the fetched signals. <IMAGE>