Design of an 8x8 Intra Prediction Module
In this thesis, a proposed hardware architecture of an H.264/AVC 8 × 8 luminance intra prediction module is designed and realized in VHDL to be used on an FPGA. The module is a part of a MPEG-2 to H.264/AVC transcoder and its implementation is based on an existing design of a 4 × 4 luminance intra prediction module used in the same transcoder. Intra prediction is characterized by high data dependency between input video frames which makes it hard to achieve a high throughput. This is solved by processing 16 image samples in parallel and by implementing a partial pipeline to increase efficiency. The design is implemented and synthesized on the Kintex-7 XC7K325T board with a maximum clock frequency of 129.34 MHz, which gives a throughput of 456.32 Mpixels/s. This is enough to encode 2160p (4k UHD) video frames at 30 frames per second in real time.