A Low-Power and High-PSNR Unified DCT/IDCT Architecture Based on EARC and Enhanced Scale Factor Approximation
The Discrete cosine transform (DCT) and inverse Discrete cosine transform (IDCT) have been widely used in image and video compression standards, and more and more researchers focus on the method that taking use of the coordinate rotation digital computer (CORDIC) to execute the DCT and IDCT, the reason is that CORDIC can realize the complex transcendental functions only by using shifters and adders, and is easily suitable implemented in a parallel way. However, the conventional CORDIC has some drawbacks, such as low precision, long iteration number, scale factor and so on. In our previous paper, we have implemented an unified DCT/IDCT based on adaptive recoding CORDIC (ARC) to improve the performance. In this paper, compared with our previous work, we propose an enhanced unified architecture for DCT and IDCT based on the cooperation between the enhanced adaptive recoding coordinate rotation digital computer (EARC) and the conventional CORDIC, in which the radix-2 scale factor approximation proposed in our previous paper is also optimized significantly to achieve better performance in power consumption and PSNR. To conduct a fair competition, the proposed architecture is also validated on a Virtex 5 FPGA platform to evaluate the performance. Under DCT only mode, compared with the Huang and Lee architectures, the proposed architecture at least uses 3.3% less area, dissipates 9% less power at the nearly 2% cost of the critical path delay. Under DCT/IDCT mode, the proposed architecture also saves over 2% hardware resources, reduces more than 5.9% power dissipation when compared to the latest unified DCT/IDCT architectures. Meanwhile, the proposed architecture exceeds the state-of-the-art unified architectures over 0.98 dB in PSNR. Compared with 2S-8P-DCT and 3S-8P-DCT, the proposed unified DCT/IDCT architecture also achieves the best performance in accuracy, processing time and throughput.