High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees
For high-performance chip designs, a clock network with high tolerance towards process-variation is essential for chip synchronization. Clock mesh structure are widely used in these designs because of its resistant to variations. However, traditional mesh structures suffer from several drawbacks such as difficulty in timing estimation, inability to handle obstacles, and high power consumption. This paper proposes a new obstacle-avoiding clock mesh synthesis method which applies a two-stage approach of mesh construction followed by driving-tree synthesis. The method achieves very low skew through structural optimization, thus eliminating the need of direct timing estimation and/or SPICE simulation during clock network synthesis. In addition, our approach handles obstacles with the structural consideration, and reduces power consumption by removing non-critical mesh components and optimizing the driving-tree structure. Based on the benchmarks of the ISPD'10 Clock Network Synthesis Contest, the top contest performers result in 1.32X skew over our approach by using mesh structure, and more than 2.0X skew over our approach by using tree structure. Our approach runs 8326X/11421X faster than teams that used simulation, and 67X/90X times faster than teams that did not use simulation.