Two priority dimension order routing algorithm for virtualization of a network on chip design
A two priority dimension order routing(TPDOR) algorithm was developed foris communications in irregular topologies formed by virtualization of network on chip(NoC) designs.The TPDOR needs two bits per router to configurate two prior routing directions.The TPDOR can be used in two categories of topologies with three meshes connected in any way or with all the end-nodes communicating with the rest of the nodes through a minimal path defined in the original mesh topology.The algorithm connectivity is proven and the algorithm is shown to be free of dead locks.Simulations of the TPDOR in the field-programmable gate arrays(FPGA) of the EP2S180F1020C3 show that the area penalty is just 1.2% higher than the dimension order routing module,with negligible added cost.