Remote FPGA lab applications, interactive timing diagrams and assessment
The Remote FPGA Lab (RFL) provides interactive web-based visual control and probing of reconfigurable logic hardware in the Cloud in real time, and supports a learn-bydoing approach to digital system education. The authors have previously reported the RFL architecture, and RFL usage and survey data which highlights its effectiveness for enhanced learning, achievement and engagement. This paper illustrates an RFL counter example use case. A range of animated interactive web page console views are presented, from top level block diagram to FPGA Lookup Table and D Flip Flop hardware implementation views, and Finite State Machine animation. The paper illustrates the additional interactive real-time timing diagram functionality and proposes an automatic online assessment strategy using the RFL.