def pportD2(state):
 global dataReg
 if (state == 0):
  dataReg = (dataReg & (~ 4))
 else:
  dataReg = (dataReg | 4)
 port.DlPortWritePortUchar(baseAddress, dataReg)

def pportD2 ( state ) : global dataReg if ( state == 0 ) : dataReg = ( dataReg & ( ~ 4 ) ) else : dataReg = ( dataReg | 4 ) port . DlPortWritePortUchar ( baseAddress , dataReg )
toggle data register d2 bit .