def __getitem__(self, key):
        """
        [] operator

        :attention: Table below is for litle endian bit order (MSB:LSB)
            which is default.
            This is **reversed** as it is in pure python
            where it is [0, len(self)].

        :attention: slice on slice f signal is automatically reduced
            to single slice

        +-----------------------------+----------------------------------------------------------------------------------+
        | a[up:low]                   | items low through up; a[16:8] selects upper byte from 16b vector a               |
        +-----------------------------+----------------------------------------------------------------------------------+
        | a[up:]                      | low is automatically substituted with 0; a[8:] will select lower 8 bits          |
        +-----------------------------+----------------------------------------------------------------------------------+
        | a[:end]                     | up is automatically substituted; a[:8] will select upper byte from 16b vector a  |
        +-----------------------------+----------------------------------------------------------------------------------+
        | a[:], a[-1], a[-2:], a[:-2] | raises NotImplementedError   (not implemented due to complicated support in hdl) |
        +-----------+----------------------------------------------------------------------------------------------------+
        """
        iamVal = isinstance(self, Value)
        st = self._dtype
        length = st.bit_length()
        if length == 1 and not st.forceVector:
            # assert not indexing on single bit
            raise TypeError("indexing on single bit")

        if isinstance(key, slice):
            key = slice_to_SLICE(key, length)
            isSLICE = True
        else:
            isSLICE = isinstance(key, Slice.getValueCls())

        if isSLICE:
            # :note: downto notation
            start = key.val[0]
            stop = key.val[1]
            startIsVal = isinstance(start, Value)
            stopIsVal = isinstance(stop, Value)
            indexesAreValues = startIsVal and stopIsVal
        else:
            key = toHVal(key)

        iAmResultOfIndexing = (not iamVal and
                               hasattr(self, "origin") and
                               len(self.drivers) == 1 and
                               isinstance(self.origin, Operator) and
                               self.origin.operator == AllOps.INDEX)
        if isSLICE:
            if indexesAreValues and start.val == length and stop.val == 0:
                # selecting all bits no conversion needed
                return self

            if iAmResultOfIndexing:
                # try reduce self and parent slice to one
                original, parentIndex = self.origin.operands
                if isinstance(parentIndex._dtype, Slice):
                    parentLower = parentIndex.val[1]
                    start = start + parentLower
                    stop = stop + parentLower
                    return original[start:stop]

            # check start boundaries
            if startIsVal:
                _start = int(start)
                if _start < 0 or _start > length:
                    raise IndexError(_start, length)

            # check end boundaries
            if stopIsVal:
                _stop = int(stop)
                if _stop < 0 or _stop > length:
                    raise IndexError(_stop, length)

            # check width of selected range
            if startIsVal and stopIsVal and _start - _stop <= 0:
                raise IndexError(_start, _stop)

            if iamVal:
                return self._getitem__val(key)
            else:
                key = start._downto(stop)
                _resWidth = start - stop
                resT = Bits(width=_resWidth, forceVector=True,
                            signed=st.signed)

        elif isinstance(key, IntegerVal):
            # check index range
            _v = int(key)
            if _v < 0 or _v > length - 1:
                raise IndexError(_v)

            resT = BIT
            if iamVal:
                return self._getitem__val(key)

        elif isinstance(key, RtlSignalBase):
            t = key._dtype
            if isinstance(t, Integer):
                resT = BIT
            elif isinstance(t, Slice):
                resT = Bits(width=key.staticEval()._size(),
                            forceVector=st.forceVector, signed=st.signed)
            elif isinstance(t, Bits):
                resT = BIT
                key = key._auto_cast(INT)
            else:
                raise TypeError(
                    "Index operation not implemented"
                    " for index of type %r" % (t))

        else:
            raise TypeError(
                "Index operation not implemented for index %r" % (key))

        return Operator.withRes(AllOps.INDEX, [self, key], resT)
def __getitem__ ( self , key ) : iamVal = isinstance ( self , Value ) st = self . _dtype length = st . bit_length ( ) if length == 1 and not st . forceVector : raise TypeError ( "indexing on single bit" ) if isinstance ( key , slice ) : key = slice_to_SLICE ( key , length ) isSLICE = True else : isSLICE = isinstance ( key , Slice . getValueCls ( ) ) if isSLICE : start = key . val [ 0 ] stop = key . val [ 1 ] startIsVal = isinstance ( start , Value ) stopIsVal = isinstance ( stop , Value ) indexesAreValues = startIsVal and stopIsVal else : key = toHVal ( key ) iAmResultOfIndexing = ( not iamVal and hasattr ( self , "origin" ) and len ( self . drivers ) == 1 and isinstance ( self . origin , Operator ) and self . origin . operator == AllOps . INDEX ) if isSLICE : if indexesAreValues and start . val == length and stop . val == 0 : return self if iAmResultOfIndexing : original , parentIndex = self . origin . operands if isinstance ( parentIndex . _dtype , Slice ) : parentLower = parentIndex . val [ 1 ] start = start + parentLower stop = stop + parentLower return original [ start : stop ] if startIsVal : _start = int ( start ) if _start < 0 or _start > length : raise IndexError ( _start , length ) if stopIsVal : _stop = int ( stop ) if _stop < 0 or _stop > length : raise IndexError ( _stop , length ) if startIsVal and stopIsVal and _start - _stop <= 0 : raise IndexError ( _start , _stop ) if iamVal : return self . _getitem__val ( key ) else : key = start . _downto ( stop ) _resWidth = start - stop resT = Bits ( width = _resWidth , forceVector = True , signed = st . signed ) elif isinstance ( key , IntegerVal ) : _v = int ( key ) if _v < 0 or _v > length - 1 : raise IndexError ( _v ) resT = BIT if iamVal : return self . _getitem__val ( key ) elif isinstance ( key , RtlSignalBase ) : t = key . _dtype if isinstance ( t , Integer ) : resT = BIT elif isinstance ( t , Slice ) : resT = Bits ( width = key . staticEval ( ) . _size ( ) , forceVector = st . forceVector , signed = st . signed ) elif isinstance ( t , Bits ) : resT = BIT key = key . _auto_cast ( INT ) else : raise TypeError ( "Index operation not implemented" " for index of type %r" % ( t ) ) else : raise TypeError ( "Index operation not implemented for index %r" % ( key ) ) return Operator . withRes ( AllOps . INDEX , [ self , key ] , resT )
[] operator

        :attention: Table below is for litle endian bit order (MSB:LSB)
            which is default.
            This is **reversed** as it is in pure python
            where it is [0, len(self)].

        :attention: slice on slice f signal is automatically reduced
            to single slice

        +-----------------------------+----------------------------------------------------------------------------------+
        | a[up:low]                   | items low through up; a[16:8] selects upper byte from 16b vector a               |
        +-----------------------------+----------------------------------------------------------------------------------+
        | a[up:]                      | low is automatically substituted with 0; a[8:] will select lower 8 bits          |
        +-----------------------------+----------------------------------------------------------------------------------+
        | a[:end]                     | up is automatically substituted; a[:8] will select upper byte from 16b vector a  |
        +-----------------------------+----------------------------------------------------------------------------------+
        | a[:], a[-1], a[-2:], a[:-2] | raises NotImplementedError   (not implemented due to complicated support in hdl) |
        +-----------+----------------------------------------------------------------------------------------------------+