def write_efuses(self):
        """ Write the values in the efuse write registers to
        the efuse hardware, then refresh the efuse read registers.
        """

        # Configure clock
        apb_freq = self._esp.get_crystal_freq()
        clk_sel0, clk_sel1, dac_clk_div = EFUSE_CLK_SETTINGS[apb_freq]

        self.update_reg(EFUSE_DAC_CONF_REG, EFUSE_DAC_CLK_DIV_MASK, dac_clk_div)
        self.update_reg(EFUSE_CLK_REG, EFUSE_CLK_SEL0_MASK, clk_sel0)
        self.update_reg(EFUSE_CLK_REG, EFUSE_CLK_SEL1_MASK, clk_sel1)

        self.write_reg(EFUSE_REG_CONF, EFUSE_CONF_WRITE)
        self.write_reg(EFUSE_REG_CMD, EFUSE_CMD_WRITE)

        def wait_idle():
            deadline = time.time() + EFUSE_BURN_TIMEOUT
            while time.time() < deadline:
                if self._esp.read_reg(EFUSE_REG_CMD) == 0:
                    return
            raise esptool.FatalError("Timed out waiting for Efuse controller command to complete")
        wait_idle()
        self.write_reg(EFUSE_REG_CONF, EFUSE_CONF_READ)
        self.write_reg(EFUSE_REG_CMD, EFUSE_CMD_READ)
        wait_idle()
def write_efuses ( self ) : apb_freq = self . _esp . get_crystal_freq ( ) clk_sel0 , clk_sel1 , dac_clk_div = EFUSE_CLK_SETTINGS [ apb_freq ] self . update_reg ( EFUSE_DAC_CONF_REG , EFUSE_DAC_CLK_DIV_MASK , dac_clk_div ) self . update_reg ( EFUSE_CLK_REG , EFUSE_CLK_SEL0_MASK , clk_sel0 ) self . update_reg ( EFUSE_CLK_REG , EFUSE_CLK_SEL1_MASK , clk_sel1 ) self . write_reg ( EFUSE_REG_CONF , EFUSE_CONF_WRITE ) self . write_reg ( EFUSE_REG_CMD , EFUSE_CMD_WRITE ) def wait_idle ( ) : deadline = time . time ( ) + EFUSE_BURN_TIMEOUT while time . time ( ) < deadline : if self . _esp . read_reg ( EFUSE_REG_CMD ) == 0 : return raise esptool . FatalError ( "Timed out waiting for Efuse controller command to complete" ) wait_idle ( ) self . write_reg ( EFUSE_REG_CONF , EFUSE_CONF_READ ) self . write_reg ( EFUSE_REG_CMD , EFUSE_CMD_READ ) wait_idle ( )
Write the values in the efuse write registers to
        the efuse hardware, then refresh the efuse read registers.