def step(self, provided_inputs):
        """ Take the simulation forward one cycle

        :param provided_inputs: a dictionary mapping wirevectors to their values for this step

        All input wires must be in the provided_inputs in order for the simulation
        to accept these values

        Example: if we have inputs named 'a' and 'x', we can call:
        sim.step({'a': 1, 'x': 23}) to simulate a cycle with values 1 and 23
        respectively
        """

        # Check that all Input have a corresponding provided_input
        input_set = self.block.wirevector_subset(Input)
        supplied_inputs = set()
        for i in provided_inputs:
            if isinstance(i, WireVector):
                name = i.name
            else:
                name = i
            sim_wire = self.block.wirevector_by_name[name]
            if sim_wire not in input_set:
                raise PyrtlError(
                    'step provided a value for input for "%s" which is '
                    'not a known input ' % name)
            if not isinstance(provided_inputs[i], numbers.Integral) or provided_inputs[i] < 0:
                raise PyrtlError(
                    'step provided an input "%s" which is not a valid '
                    'positive integer' % provided_inputs[i])
            if len(bin(provided_inputs[i]))-2 > sim_wire.bitwidth:
                raise PyrtlError(
                    'the bitwidth for "%s" is %d, but the provided input '
                    '%d requires %d bits to represent'
                    % (name, sim_wire.bitwidth,
                       provided_inputs[i], len(bin(provided_inputs[i]))-2))

            self.value[sim_wire] = provided_inputs[i]
            supplied_inputs.add(sim_wire)

        # Check that only inputs are specified, and set the values
        if input_set != supplied_inputs:
            for i in input_set.difference(supplied_inputs):
                raise PyrtlError('Input "%s" has no input value specified' % i.name)

        self.value.update(self.regvalue)  # apply register updates from previous step

        for net in self.ordered_nets:
            self._execute(net)

        # Do all of the mem operations based off the new values changed in _execute()
        for net in self.mem_update_nets:
            self._mem_update(net)

        # at the end of the step, record the values to the trace
        # print self.value # Helpful Debug Print
        if self.tracer is not None:
            self.tracer.add_step(self.value)

        # Do all of the reg updates based off of the new values
        for net in self.reg_update_nets:
            argval = self.value[net.args[0]]
            self.regvalue[net.dests[0]] = self._sanitize(argval, net.dests[0])

        # finally, if any of the rtl_assert assertions are failing then we should
        # raise the appropriate exceptions
        check_rtl_assertions(self)
def step ( self , provided_inputs ) : input_set = self . block . wirevector_subset ( Input ) supplied_inputs = set ( ) for i in provided_inputs : if isinstance ( i , WireVector ) : name = i . name else : name = i sim_wire = self . block . wirevector_by_name [ name ] if sim_wire not in input_set : raise PyrtlError ( 'step provided a value for input for "%s" which is ' 'not a known input ' % name ) if not isinstance ( provided_inputs [ i ] , numbers . Integral ) or provided_inputs [ i ] < 0 : raise PyrtlError ( 'step provided an input "%s" which is not a valid ' 'positive integer' % provided_inputs [ i ] ) if len ( bin ( provided_inputs [ i ] ) ) - 2 > sim_wire . bitwidth : raise PyrtlError ( 'the bitwidth for "%s" is %d, but the provided input ' '%d requires %d bits to represent' % ( name , sim_wire . bitwidth , provided_inputs [ i ] , len ( bin ( provided_inputs [ i ] ) ) - 2 ) ) self . value [ sim_wire ] = provided_inputs [ i ] supplied_inputs . add ( sim_wire ) if input_set != supplied_inputs : for i in input_set . difference ( supplied_inputs ) : raise PyrtlError ( 'Input "%s" has no input value specified' % i . name ) self . value . update ( self . regvalue ) for net in self . ordered_nets : self . _execute ( net ) for net in self . mem_update_nets : self . _mem_update ( net ) if self . tracer is not None : self . tracer . add_step ( self . value ) for net in self . reg_update_nets : argval = self . value [ net . args [ 0 ] ] self . regvalue [ net . dests [ 0 ] ] = self . _sanitize ( argval , net . dests [ 0 ] ) check_rtl_assertions ( self )
Take the simulation forward one cycle

        :param provided_inputs: a dictionary mapping wirevectors to their values for this step

        All input wires must be in the provided_inputs in order for the simulation
        to accept these values

        Example: if we have inputs named 'a' and 'x', we can call:
        sim.step({'a': 1, 'x': 23}) to simulate a cycle with values 1 and 23
        respectively