Systems and methods are provided for determining an order of execution of a neural network. For instance, data indicative of a neural network and data indicative of an amount of available memory in a constrained memory space can be obtained. The neural network can include a plurality of operators. An order of execution associated with the neural network can then be determined. The order of execution specifies an order in which to execute each of the plurality of operators. The order of execution is determined based at least in part on the available memory in the constrained memory space. In particular, one or more graph search algorithms can be performed on a graph that is representative of the neural network to obtain the order of execution.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A computer-implemented method of determining an order of execution of a neural network, the method comprising: obtaining, by one or more computing devices, data that describes a graph of a neural network, the neural network comprising a plurality of operators; obtaining, by the one or more computing devices, data indicative of an amount of available memory in a constrained memory space; and performing, by the one or more computing devices, at least one graph search algorithm on the graph to determine an order of execution associated with the neural network, the order of execution specifying an order in which to execute each of the plurality of operators, wherein the order of execution results in a memory usage that does not exceed the amount of available memory in the constrained memory space. 2. The computer-implemented method of claim 1, further comprising: determining, by the one or more computing devices, a first memory address for each operator of the plurality of operators, each first memory address specifying a location in the constrained memory space in which to store output data of the corresponding operator; and determining, by the one or more computing devices, a second memory address for at least one operator of the plurality of operators, each second memory address specifying a location in in the constrained memory space in which to store temporary data associated with execution of the corresponding operator. 3. The computer-implemented method of claim 2, wherein the first memory address and the second memory address are determined based at least in part on the determined order of execution of the neural network. 4. The computer-method of claim 1, wherein performing, by the one or more computing devices, the at least one graph search algorithm comprises: identifying, by the one or more computing devices, one or more forced transitions indicative of a transition between a first operator and a second operator, such that when the second operator is executed, the peak memory consumption associated with execution of the neural network does not increase; and adding, by the one or more computing devices, at least one of the forced transitions to the order of execution. 5. The computer-implemented method of claim 1, wherein performing, by the one or more computing devices, the at least one graph search algorithm comprises: identifying, by the one or more computing devices, one or more candidate orders of execution of the neural network; determining, by the one or more computing devices, a memory requirement associated with execution of the neural network in accordance with each candidate order of execution; and selecting, by the one or more computing devices, an order of execution based at least in part on the determined memory requirements. 6. The computer-implemented method of claim 1, wherein the order of execution of the neural network is determined at least in part using a shortest path algorithm that uses an all time peak memory usage as its key metric. 7. The computer-implemented method of claim 1, wherein performing, by the one or more computing devices, the at least one graph search algorithm comprises adding, by the one or more computing devices, one or more additional operators to the neural network. 8. The computer-implemented method of claim 7, wherein adding, by the one or more computing devices, the one or more additional operators comprise adding, by the one or more computing devices, at least one of a defragment operator, a move operator, or a reorder operator associated with the constrained memory space. 9. The computer-implemented method of claim 1, wherein the constrained memory space comprises a scratch buffer that is on-chip with a processor configured to execute the neural network. 10. The computer-implemented method of claim 1, further comprising determining, by the one or more computing devices, an error when an amount of data required for execution of one or more operators exceeds the amount of available memory in the constrained memory space. 11. The computer-implemented method of claim 1, further comprising storing, by the one or more computing devices, the determined order of execution, such that a future execution of the neural network occurs in accordance with the stored order of execution. 12. The computer-implemented method of claim 1, further comprising providing, by the one or more computing devices, the determined order of execution to a wearable image capture device configured to execute the neural network. 13. A computing system determine a static allocation of a neural network, the computing system comprising at least one processor and at least one non-transitory computer-readable medium storing instructions executable by the at least one processor to cause the computing system to: obtain data that describes a graph of a neural network, wherein the neural network comprises a plurality of operators; obtain data that describes an amount of available memory in a constrained memory space; perform at least one graph search algorithm on the graph to determine an execution order for the plurality of operators of the neural network that results in memory usage that does not exceed the amount of available memory in the constrained memory space; and store the determined execution order, wherein future execution of the neural network occurs according to the stored execution order. 14. The computing system of claim 13, wherein to perform the graph search algorithm, the computing system: identifies one or more forced transitions within the graph that necessarily decrease one or more memory requirements of the execution order; and prunes a search of a portion of the graph based at least in part on the identified one or more forced transitions. 15. The computing system of claim 13, wherein: the graph comprises a plurality of nodes and a plurality of arcs respectively that respectively connect the plurality of nodes; the plurality of nodes respectively represent a plurality of search states, each search state comprising a first set of operators and a second set of operators, the first set of operators comprising operators that have been completed and that have at least one output that is required to be maintained, the second set of operators comprising operators that have not been completed but for which all required inputs are available; and the plurality of arcs respectively represent candidate transitions between the plurality of search states. 16. The computing system of claim 15, wherein to perform the at least one graph search algorithm, the computing system: analyzes, for a given node, at least one of a plurality of available arcs for such node to determine whether such arc represents a forced transition, wherein a forced transition does not increase a peak memory used, and wherein a forced transition does not increase a current memory used; and in response to a determination that one of the available arcs represents a forced transition: selects such available arc as the transition for the given node; and prunes the other available arcs from a search space of the graph. 17. The computing system of claim 15, wherein to perform the at least one graph search algorithm, the computing system: determines a fingerprint for each of a plurality of explored search states of the plurality of search states, wherein the fingerprint for each explored search state comprises a result of an application of a hash function to one or more fields of the explored search state that uniquely identify a third set of operators that have been completed; detects when two or more explored search states have equivalent fingerprints; and in response to detection of two or more explored search states with equivalent fingerprints, selects one of the two or more explored search states with equivalent fingerprints based on a comparison of the respective memory requirements of the two or more explored search states with equivalent fingerprints. 18. The computing system of claim 13, wherein execution of the instructions further causes the computing system to: provide at least one annotation for each of the plurality of operators of the neural network, wherein the at least one annotation for each of the plurality of operators comprises a first memory address and a second memory address, the first memory address describing a first memory location at which output data of the operator should be stored, the second memory address describing a second location at which a temporary buffer of the operator should be stored. 19. A non-transitory computer-readable medium storing instructions that, when executed by at least one processor, cause the at least one processor to perform operations, the operations comprising: obtaining data indicative of a neural network, the neural network comprising a plurality of operators; obtaining data indicative of an amount of available memory in a constrained memory space; building a graph that describes a plurality of dependencies respectively between the plurality of operators of the neural network; and performing at least one graph search algorithm to determine an order of execution for the neural network, the order of execution specifying an order in which to execute each of the plurality of operators, the order of execution being determined based at least in part on the available memory in the constrained memory space; wherein performing at least one graph search algorithm comprises: identifying one or more forced transitions within the graph that necessarily decrease one or more memory requirements of the order of execution; and pruning a search of a portion of the graph based at least in part on the identified one or more forced transitions. 20. The non-transitory computer-readable medium of claim 19, wherein the instructions which cause the at least one processor to perform the at least one graph search algorithm cause the at least one processor to perform at least one shortest path algorithm that uses a peak memory usage as a key metric.