A synapse circuit to perform spike timing dependent plasticity (STDP) operation is provided. The synapse circuit includes a memristor having a resistance value, a transistor connected to the memristor, and the transistor configured to receive at least two input signals. The resistance value of the memristor is changed based on a time difference between the at least two input signals received by the transistor.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A synapse circuit to perform spike timing dependent plasticity (STDP) operation, the synapse circuit comprising: a memristor having a resistance value; and a transistor connected to the memristor, the transistor configured to receive at least two input signals, wherein the resistance value of the memristor is changed based on a time difference between the at least two input signals received by the transistor. 2. The synapse circuit of claim 1, wherein the resistance value of the memristor is changed based on a voltage change caused by the time difference between the at least two input signals. 3. The synapse circuit of claim 1, wherein the resistance value of the memristor is changed based on a time difference between a first input signal applied to a gate terminal of the transistor and a second input signal based on a membrane voltage applied to a source terminal of the transistor. 4. The synapse circuit of claim 3, wherein a direction of a current flowing on the memristor is determined by a voltage difference caused by the time difference between the first input signal and the second input signal. 5. The synapse circuit of claim 3, wherein an amount of a current flowing on the memristor is determined by a voltage difference caused by the time difference between the first input signal and the second input signal. 6. The synapse circuit of claim 3, wherein the synapse circuit further comprises: a first terminal connected to the gate terminal of the transistor and configured to provide the first input signal, and a second terminal connected to the source terminal of the transistor and configured to provide the second input signal, and the synapse circuit is connected to a pre-synaptic neuron circuit through the first terminal and to a post-synaptic neuron circuit through the second terminal. 7. The synapse circuit of claim 6, wherein the post-synaptic neuron circuit is configured to generate a spike fired with reference to a resting voltage. 8. The synapse circuit of claim 7, wherein the post-synaptic neuron circuit comprises an N-metal oxide semiconductor (MOS) and a P-MOS transistor, the N-MOS transistor and the P-MOS transistor being serially connected; a resting voltage source to supply the resting voltage is connected to a source terminal of the N-MOS transistor; and a capacitor is connected to a source terminal of the P-MOS transistor. 9. The synapse circuit of claim 1, wherein different voltages are applied to the memristor and the source terminal of the transistor. 10. The synapse circuit of claim 1, wherein the memristor is connected to a drain terminal of the transistor. 11. The synapse circuit of claim 1, wherein a channel of the memristor is serially connected to a channel of the transistor. 12. The synapse circuit of claim 1, wherein the transistor comprises an N-MOS transistor. 13. A neuromorphic system comprising: a synapse circuit configured to perform spike timing dependent plasticity (STDP) operation, the synapse circuit comprising a first terminal, a second terminal, a memristor having a resistance value, and a transistor connected to the memristor; a pre-synaptic neuron circuit connected to the memristor through the first terminal of the synapse circuit; and a post-synaptic neuron circuit connected to the memristor through the second terminal of the synapse circuit, wherein the resistance value of the memristor is changed based on a time difference between at least two input signals received by the synapse circuit. 14. The neuromorphic system of claim 13, wherein the first terminal of the synapse circuit is connected to a gate terminal of the transistor to provide a first input signal, and the second terminal of the synapse circuit is connected to a source terminal of the transistor to provide a second input signal. 15. The neuromorphic system of claim 14, wherein the resistance value of the memristor is changed based on a time difference between the first input signal applied to the gate terminal of the transistor and the second input signal based on a membrane voltage applied to the source terminal of the transistor. 16. The neuromorphic system of claim 15, wherein a direction of a current flowing on the memristor is determined by a voltage difference caused by the time difference between the first input signal and the second input signal. 17. The neuromorphic system of claim 15, wherein an amount of a current flowing on the memristor is determined by a voltage difference caused by the time difference between the first input signal and the second input signal. 18. The neuromorphic system of claim 14, wherein the post-synaptic neuron circuit is configured to generate a spike fired with reference to a resting voltage. 19. The neuromorphic system of claim 18, wherein the post-synaptic neuron circuit comprises an N-metal oxide semiconductor (MOS) and a P-MOS transistor, wherein the N-MOS transistor and the P-MOS transistor are serially connected, a resting voltage source to supply the resting voltage is connected to a source terminal of the N-MOS transistor, and a capacitor is connected to a source terminal of the P-MOS transistor. 20. A method of performing spike timing dependent plasticity (STDP) operation between a pre-synaptic neuron circuit and a post-synaptic neuron circuit, the method comprising: receiving a pre-synaptic input signal from the pre-synaptic neuron circuit; receiving a post-synaptic input signal from the post-syantic neuron circuit; and adjusting a resistance value of a memristor based on a time difference between the pre-synaptic input signal and the post-synaptic input signal.