In a general aspect, randomized compiling techniques for quantum computing are described. In some aspects, an initial quantum-logic gate sequence is received. A modified quantum-logic gate sequence is generated by applying virtual random gates to the initial quantum-logic gate sequence, such that the initial quantum-logic gate sequence is logically equivalent to the modified quantum-logic gate sequence. The modified quantum-logic gate sequence can be provided to a quantum information processor for execution.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A compiler method comprising: receiving an initial quantum-logic gate sequence; generating, by operation of data processing apparatus, a modified quantum-logic gate sequence by applying virtual random gates to the initial quantum-logic gate sequence, wherein the initial quantum-logic gate sequence is logically equivalent to the modified quantum-logic gate sequence; and providing the modified quantum-logic gate sequence to be executed by a quantum information processor. 2. The method of claim 1, wherein the initial quantum-logic gate sequence comprises a series of cycles, and the modified quantum-logic gate sequence is generated by applying virtual random gates in each cycle of the initial quantum-logic gate sequence. 3. The method of claim 2, wherein, after an initial cycle in the series, a portion of the virtual random gates applied in each cycle are configured to invert one or more of the virtual random gates applied in a preceding cycle. 4. The method of claim 1, wherein the virtual random gates comprise virtual random Pauli gates or dihedral gates. 5. The method of claim 1, wherein providing the modified quantum-logic gate to be executed by a quantum information processor comprises converting the modified quantum-logic gate into machine code that is executable by the quantum information processor. 6. The method of claim 1, wherein the virtual random gates are configured to convert coherent errors in the quantum information processor into stochastic errors in the quantum information processor. 7. The method of claim 1, further comprising executing the modified quantum-logic gate sequence on the quantum information processor. 8. A system comprising: a quantum device comprising a quantum information processor; and one or more data processors configured to perform operations comprising: receiving an initial quantum-logic gate sequence; generating a modified quantum-logic gate sequence by applying virtual random gates to the initial quantum-logic gate sequence, wherein the initial quantum-logic gate sequence is logically equivalent to the modified quantum-logic gate sequence; and providing the modified quantum-logic gate to be executed by the quantum information processor. 9. The system of claim 8, wherein the initial quantum-logic gate sequence comprises a series of cycles, and the modified quantum-logic gate sequence is generated by applying virtual random gates in each cycle of the initial quantum-logic gate sequence. 10. The system of claim 9, wherein, after an initial cycle in the series, a portion of the virtual random gates applied in each cycle are configured to invert one or more of the virtual random gates applied in a preceding cycle. 11. The system of claim 8, wherein the virtual random gates comprise virtual random Pauli gates or dihedral gates. 12. The system of claim 8, wherein providing the modified quantum-logic gate to be executed by a quantum information processor comprises converting the modified quantum-logic gate into machine code that is executable by the quantum information processor. 13. The system of claim 8, wherein the virtual random gates are configured to convert coherent errors in the quantum information processor into stochastic errors in the quantum information processor. 14. A noise-tailoring method comprising: receiving a bare quantum-logic circuit; generating, by operation of data processing apparatus, a set of modified quantum-logic circuits by applying virtual twirling gates and virtual correction gates to the bare quantum-logic circuit, wherein the bare quantum-logic circuit is logically equivalent to each of the modified quantum-logic circuits; executing the set of modified quantum-logic circuits on a quantum information processor to obtain a set of outcomes; and averaging the set of outcomes to obtain a noise-tailored outcome. 15. The noise-tailoring method of claim 14, wherein the bare quantum-logic circuit comprises a plurality of dock cycles, and virtual twirling gates and virtual correction gates are applied to individual clock cycles. 16. The noise-tailoring method of claim 15, wherein, after an initial dock cycle, the virtual correction gates applied in each dock cycle are configured to invert corresponding virtual twirling gates applied in a preceding clock cycle. 17. The noise-tailoring method of claim 14, wherein the virtual random gates comprise virtual random Pauli gates or dihedral gates. 18. The noise-tailoring method of claim 14, wherein the virtual twirling gates and virtual correction gates cause the quantum information processor to execute the modified quantum-logic circuit with a lower worst-case error rate compared to executing the bare quantum-logic circuit on the quantum information processor. 19. The noise-tailoring method of claim 14, wherein the virtual twirling gates and virtual correction gates cause the quantum information processor to execute the modified quantum-logic circuit with a lower average error rate compared to executing the bare quantum-logic circuit on the quantum information processor.