Computer-readable storage memory may include a) input memory having addressable blocks of random access memory storing an input data pattern, b) pattern input address memory having addressable blocks of random access memory, each of the addressable blocks storing a predetermined address of the input memory, c) current state address memory comprising a block of random access memory storing a current state address, and d) at least one next state memory having addressable blocks of random access memory, each of the addressable blocks storing predetermined data determining a next state address. The pattern input address memory and the at least one next state memory may each be sized with at least a number of addressable blocks as a maximum state address storable in the current state address memory. The current state address may index an addressable block of the pattern input address memory and the at least one next state memory.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A computer-readable storage memory comprising: input memory comprising addressable blocks of random access memory, the input memory storing an input data pattern; pattern input address memory comprising addressable blocks of random access memory, each of the addressable blocks storing a predetermined address of the input memory; current state address memory comprising a block of random access memory storing a current state address; and at least one next state memory comprising addressable blocks of random access memory, each of the addressable blocks storing predetermined data for determining a next state address to store in the current state address memory; wherein the pattern input address memory and the at least one next state memory are each sized with at least a number of addressable blocks as a maximum state address storable in the current state address memory; and wherein the current state address indexes an addressable block of the pattern input address memory and the at least one next state memory. 2. The computer-readable storage memory of claim 1, wherein the at least one next state memory comprises at least two next state memories, each comprising addressable blocks of random access memory, each of the addressable blocks storing predetermined data for determining a next state address to store in the current state address memory; and wherein data in an addressable block of the input memory indexed by the predetermined address in an addressable block of the pattern input address memory indexed by the current state address determines which of the at least two next state memories to index for determining a next state address to store in the current state address memory. 3. The computer-readable storage memory of claim 2, further comprising: magnitude comparison memory comprising addressable blocks of random access memory, each of the addressable blocks storing a predetermined magnitude value; wherein data in an addressable block of the input memory indexed by the predetermined address in an addressable block of the pattern input address memory indexed by the current state address is compared with a magnitude value in an addressable block of the magnitude comparison memory indexed by the current state address, and the result of the comparison determines which of the at least two next state memories to index for determining a next state address to store in the current state address memory. 4. The computer-readable storage memory of claim 1, wherein the predetermined data in each of the addressable blocks of the at least one next state memory comprises a random number between a predetermined range of numbers. 5. The computer-readable storage memory of claim 1, wherein the predetermined data in each of the addressable blocks of the at least one next state memory comprises a next state address value, the next state address value being a summation of an index of the respective addressable block of the at least one next state memory and a random number between a predetermined range of numbers. 6. The computer-readable storage memory of claim 2, further comprising ID memory comprising addressable blocks of random access memory, each of the addressable blocks storing an ID hash of predetermined bits, and addressable by an ID hash index. 7. The computer-readable storage memory of claim 6, further comprising vertical sensory memory comprising addressable blocks of random access memory, each of the addressable blocks storing predetermined data from which a hash index and bit number can be determined, the bit number identifying which bit in the ID hash indexed in the ID memory by the hash index to set. 8. The computer-readable storage memory of claim 1, further comprising: pattern map memory comprising addressable blocks of random access memory, data in an addressable block of the pattern map memory indexed by the predetermined address in an addressable block of the pattern input address memory indexed by the current state address; wherein each addressable block of the pattern map memory stores data identifying the type of data stored in an addressable block of the input memory indexed by the predetermined address in an addressable block of the pattern input address memory indexed by the current state address. 9. The computer-readable storage memory of claim 8, wherein the type of data stored in an addressable block of the input memory comprises one of binary data, magnitude data, or category data. 10. The computer-readable storage memory of claim 9, wherein category data comprises data from a dataset having a predetermined number of data choices. 11. The computer-readable storage memory of claim 10, wherein the at least one next state memory comprises a next state memory corresponding to each data choice, each comprising addressable blocks of random access memory, each of the addressable blocks storing predetermined data for determining a next state address to store in the current state address memory; and wherein, if an addressable block of the pattern map memory indexed by the predetermined address in an addressable block of the pattern input address memory indexed by the current state address identifies the type of data stored in an addressable block of the input memory indexed by the predetermined address in an addressable block of the pattern input address memory indexed by the current state address as a category type, then a next state address to store in the current state address memory is determined from data in the next state memory corresponding to the data in an addressable block of the input memory indexed by the predetermined address in an addressable block of the pattern input address memory indexed by the current state address. 12. The computer-readable storage memory of claim 6, wherein the ID hashes of ID memory are determined from a sequence of selections of the at least two next state memories. 13. A parallel pattern memory engine comprising at least two of the computer-readable storage memories of claim 1 operating in parallel. 14. The parallel pattern memory engine of claim 13, wherein the addressable blocks of the pattern input address memory of one of the at least two of the computer-readable storage memories comprises a different set of predetermined addresses than the addressable blocks of the pattern input address memory of another of the at least two of the computer-readable storage memories; and wherein the addressable blocks of the at least one next state memory of one of the at least two of the computer-readable storage memories comprises a different set of predetermined data than the addressable blocks of the at least one next state memory of another of the at least two of the computer-readable storage memories. 15. The parallel pattern memory engine of claim 13, wherein the input data pattern of one of the at least two of the computer-readable storage memories comprises data from a different source than the input data pattern of another of the at least two of the computer-readable storage memories. 16. The parallel pattern memory engine of claim 15, further comprising: a first sensor generating a first type of data and providing pattern data as the input data pattern to one of the at least two of the computer-readable storage memories; and a second sensor generating a second type of data and providing pattern data as the input data pattern to another of the at least two of the computer-readable storage memories. 17. A serial pattern memory engine comprising at least two of the computer-readable storage memories of claim 1 operating in serial, such that a computer-readable storage memory of the at least two computer-readable storage memories of claim 1 on a lower level provides its output to a computer-readable storage memory of the at least two computer-readable storage memories of claim 1 on a higher level. 18. The serial pattern memory engine of claim 17, further comprising at least two of the computer-readable storage memories of claim 1 operating in parallel. 19. The serial pattern memory engine of claim 17, wherein a computer-readable storage memory of the at least two computer-readable storage memories of claim 1 on a higher level provides its output as feedback to a computer-readable storage memory of the at least two computer-readable storage memories of claim 1 on a lower level.