The present invention discloses an integrated neuro-processor comprising at least a three-dimensional memory (3D-M) array. The 3D-M array stores the synaptic weights, while the neuro-processing circuit performs neural processing. The 3-D integration between the 3D-M array and the neuro-processing circuit not only improves the computational power per die area, but also greatly increases the storage capacity per die area.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. An integrated neuro-processor, comprising: a semiconductor substrate having transistors thereon; an array of neural storage-processing units (NSPU) formed on said semiconductor substrate, each of said NSPUs comprising at least a first three-dimensional memory (3D-M) array and a neuro-processing circuit, wherein said first 3D-M array is stacked above said neuro-processing circuit, said 3D-M array storing at least a synaptic weight; said neuro-processing circuit is formed on said substrate, said neuro-processing circuit performing neural processing with said synaptic weight; said first 3D-M array and said neuro-processing circuit are communicatively coupled by a plurality of contact vias. 2. The integrated neuro-processor according to claim 1, wherein said first 3D-M array at least partially covers said neuro-processing circuit. 3. The integrated neuro-processor according to claim 1, further comprising a second 3D-M array formed on a same memory level as said first 3D-M array, said first and second 3D-M arrays at least partially covering said neuro-processing circuit. 4. The integrated neuro-processor according to claim 1, wherein said first 3D-M array is three-dimensional writable memory (3D-W). 5. The integrated neuro-processor according to claim 4, wherein said 3D-W is 3D-XPoint. 6. The integrated neuro-processor according to claim 1, wherein said first 3D-M array is a three-dimensional printed memory (3D-P). 7. The integrated neuro-processor according to claim 1, further comprising a third 3D-M array formed on a different memory level than said first 3D-M array, wherein said third 3D-M array stores at least a portion of a look-up table (LUT) of an activation function. 8. The integrated neuro-processor according to claim 12, wherein said third 3D-M array is 3D-P. 9. An integrated neuro-processor, comprising: a semiconductor substrate having transistors thereon; an array of neural storage-processing units (NSPU) formed on said semiconductor substrate, each of said NSPUs comprising at least a first three-dimensional memory (3D-M) array and a neuro-processing circuit, wherein said first 3D-M array is stacked above said neuro-processing circuit, said 3D-M array storing at least a synaptic weight; said neuro-processing circuit is formed on said substrate, said neuro-processing circuit comprising a multiplier, wherein one input of said multiplier is said synaptic weight; said first 3D-M array and said neuro-processing circuit are communicatively coupled by a plurality of contact vias. 10. The integrated neuro-processor according to claim 9, wherein said neuro-processing circuit further comprises an adder. 11. The integrated neuro-processor according to claim 9, wherein said first 3D-M array at least partially covers said multiplier. 12. The integrated neuro-processor according to claim 9, further comprising a second 3D-M array formed on a same memory level as said first 3D-M array, said first and second 3D-M arrays at least partially covering said neuro-processing circuit. 13. The integrated neuro-processor according to claim 9, wherein said first 3D-M array is three-dimensional writable memory (3D-W). 14. The integrated neuro-processor according to claim 9, wherein said first 3D-M array is a three-dimensional printed memory (3D-P). 15. The integrated neuro-processor according to claim 9, further comprising a third 3D-M array formed on a different memory level than said first 3D-M array, wherein said third 3D-M array stores at least a portion of a look-up table (LUT) of an activation function. 16. The integrated neuro-processor according to claim 15, wherein said third 3D-M array is 3D-P. 17. A hybrid three-dimensional memory (3D-M) block, comprising: a semiconductor substrate having transistors thereon; a first three-dimensional memory (3D-M) array stacked above said semiconductor substrate and coupling with said semiconductor substrate; a second 3D-M array stacked above said first 3D-M array and coupling with said semiconductor substrate; wherein said first and second 3D-M arrays are of different types of 3D-M. 18. The hybrid 3D-M block according to claim 17, wherein said first 3D-M array is a three-dimensional printed memory (3D-P) array; and, said second 3D-M array is a three-dimensional writable memory (3D-W) array. 19. The hybrid 3D-M block according to claim 17, wherein said first 3D-M array is a 3D-W array; and, said second 3D-M array is a 3D-P array. 20. The hybrid 3D-M block according to claim 17, further comprising a third 3D-M array on a same memory level as said first 3D-M array, wherein said second 3D-M array fully covers said first and third 3D-M arrays, said first and third 3d-M arrays being of a same type.