A neuromorphic memory system including neuromorphic memory arrays. Each neuromorphic memory array includes rows and columns of neuromorphic memory cells. A column of postsynaptic circuits is electrically coupled to postsynaptic spike timing dependent plasticity (STDP) lines. Each postsynaptic STDP line is coupled to a row of neuromorphic memory cells. A column of summing circuits is electrically coupled to postsynaptic leaky integrate and fire (LIF) lines. Each postsynaptic LIF line is coupled to the row of neuromorphic memory cells at a respective memory array. Each summing circuit provides a sum of signals from the postsynaptic LIF lines to a respective postsynaptic circuit.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A neuromorphic memory system comprising: a plurality of neuromorphic memory arrays, each of the neuromorphic memory arrays including rows and columns of neuromorphic memory cells; a column of postsynaptic circuits, each of the postsynaptic circuits electrically coupled to a plurality of postsynaptic spike timing dependent plasticity (STDP) lines, each of the postsynaptic STDP lines coupled to a row of neuromorphic memory cells at a respective memory array of the memory arrays; a column of summing circuits, each of the summing circuits electrically coupled to a plurality of postsynaptic leaky integrate and fire (LIF) lines, each of the postsynaptic LIF lines coupled to the row of neuromorphic memory cells at the respective memory array, each of the summing circuits providing a sum of signals from the postsynaptic LIF lines to a respective postsynaptic circuit of the postsynaptic circuits. 2. The neuromorphic memory system of claim 1, further comprising: wherein the signals from the postsynaptic LIF lines are current signals; and wherein each of the summing circuits includes a plurality of current amplifiers, each of the current amplifiers is coupled to and receives current from a respective postsynaptic LIF line of the postsynaptic LIF lines, each of the current amplifiers is coupled at an output to the postsynaptic circuit. 3. The neuromorphic memory system of claim 2, further comprising: a plurality of presynaptic LIF lines; a plurality of presynaptic STDP lines; a column of neuromorphic memory cells at the respective memory array, the column of neuromorphic memory cells is coupled to a respective presynaptic LIF line of the presynaptic LIF lines and a respective presynaptic STDP line of the presynaptic STDP lines; a plurality of presynaptic driver circuit rows, each of the presynaptic driver circuit rows is coupled to a respective neuromorphic memory array of the neuromorphic memory arrays, each of the presynaptic driver circuit rows including a plurality of presynaptic driver circuits, each of the presynaptic driver circuits is coupled to the respective presynaptic LIF line and the respective presynaptic STDP line. 4. The neuromorphic memory system of claim 3, wherein each of the presynaptic driver circuits: generates a presynaptic LIF pulse on the respective presynaptic LIF line at time t1; and activates an access transistor coupled to the respective presynaptic LIF line in response to the presynaptic LIF pulse, the access transistor enabling LIF current to pass through the neuromorphic memory cells to the respective postsynaptic LIF line. 5. The neuromorphic memory system of claim 4, wherein each of the postsynaptic circuits: integrates the LIF current at an output of a respective summing circuit of the summing circuits over time; compares an LIF voltage at the output of the respective summing circuit to a threshold voltage; and generates a postsynaptic STDP pulse at time t2 min(Δt) on the respective postsynaptic STDP line if the LIF voltage is beyond the threshold voltage, where min(Δt) is a constant time shift. 6. The neuromorphic memory system of claim 5, wherein each of the presynaptic driver circuits transmits a presynaptic STDP pulse at the respective presynaptic STDP line as fVD1 1(h(t+min(Δt) t1)), where t is time, h is a target STDP behavior function describing a desired relative change in synaptic weight of the neuromorphic memory cells based on the time difference between when the postsynaptic neuron fires (t2) to generate the postsynaptic STDP pulse on a respective postsynaptic STDP line at t2−min(Δt) and the presynaptic STDP pulse is generated on the respective presynaptic STDP line (t1), and fVD1 is a memory cell characteristic function describing a relationship between change in an electrical resistance of the neuromorphic memory cells and a voltage of the presynaptic STDP pulse at a voltage of the postsynaptic STDP pulse, the presynaptic STDP pulse controlling a current flow through a respective neuromorphic memory cell when the postsynaptic STDP pulse is generated. 7. The neuromorphic memory system of claim 6, wherein the synaptic weight of the resistive memory cells is inversely proportional to the electrical resistance of the resistive memory cell. 8. The neuromorphic memory system of claim 6, wherein the STDP behavior function h approaches zero as an absolute value of t2−t1 increases. 9. The neuromorphic memory system of claim 5, wherein each of the postsynaptic circuits includes a LIF capacitor electrically coupled to the output of the respective summing circuit, the LIF capacitor configured to integrate the LIF current over time. 10. The neuromorphic memory system of claim 9, wherein each of the postsynaptic circuits includes a LIF discharge line coupled to the output of the respective summing circuit, the LIF discharge line configured to discharge the LIF capacitor over time. 11. The neuromorphic memory system of claim 10, wherein each of the postsynaptic circuits includes a LIF comparator electrically coupled to the output of the respective summing circuit, the LIF comparator configured to compare the LIF voltage to the threshold voltage and generate the postsynaptic STDP pulse if the LIF voltage is beyond the threshold voltage. 12-19. (canceled) 20. A neuromorphic memory system comprising: a resistive memory cell; a presynaptic neuron circuit configured to generate a presynaptic leaky integrate and fire (LIF) pulse on a presynaptic LIF line at time t1; an access transistor coupled to the presynaptic LIF line, the access transistor activated in response to the presynaptic LIF pulse, the access transistor enabling LIF current to pass through the resistive memory cell to a postsynaptic LIF line; and a postsynaptic neuron circuit including: a LIF capacitor electrically coupled to the postsynaptic LIF line, the LIF capacitor configured to integrate the LIF current at the postsynaptic LIF line over time; a LIF discharge line coupled to the postsynaptic LIF line, the LIF discharge line configured to discharge the LIF capacitor over time; and a LIF comparator electrically coupled to the postsynaptic LIF line, the LIF comparator configured to compare a LIF voltage at the LIF capacitor to a threshold voltage and generate the postsynaptic spike timing dependent plasticity (STDP) pulse on a postsynaptic STDP line if the LIF voltage is beyond the threshold voltage.