Embodiments of the invention provide a method comprising creating a structural description for at least one neurosynaptic core circuit. Each core circuit comprises an interconnect network including plural electronic synapses for interconnecting one or more electronic neurons with one or more electronic axons. The structural description defines a desired neuronal activity for the core circuits. The desired neuronal activity is simulated by programming the core circuits with the structural description. The structural description controls routing of neuronal firing events for the core circuits.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A method comprising: generating a plurality of modular, reusable, scalable configurations, wherein each configuration comprises information corresponding to a portion of a neural network circuit; and programming a multi-core circuit chip structure based on at least one of the configurations to simulate a plurality of interconnected neurosynaptic core circuits configured to perform a visual processing task. 2. The method of claim 1, wherein each core circuit comprises a plurality of electronic synapses interconnecting a plurality of electronic neurons with a plurality of electronic axons. 3. The method of claim 1, wherein each configuration comprises information relating to at least one input received, at least output generated, and at least one function performed by a corresponding portion of the neural network circuit. 4. The method of claim 1, wherein each configuration comprises at least one constituent unit, and each constituent unit corresponds to one of the following: a portion of a core circuit, a core circuit, or another configuration. 5. The method of claim 1, wherein each configuration is a static configuration file. 6. The method of claim 1, wherein the visual processing task is one of edge detection, motion history tracking or object classification. 7. A system comprising a computer processor, a computer-readable hardware storage medium, and program code embodied with the computer-readable hardware storage medium for execution by the computer processor to implement a method comprising: generating a plurality of modular, reusable, scalable configurations, wherein each configuration comprises information corresponding to a portion of a neural network circuit; and programming a multi-core circuit chip structure based on at least one of the configurations to simulate a plurality of interconnected neurosynaptic core circuits configured to perform a visual processing task. 8. The system of claim 7, wherein each core circuit comprises a plurality of electronic synapses interconnecting a plurality of electronic neurons with a plurality of electronic axons. 9. The system of claim 7, wherein each configuration comprises information relating to at least one input received, at least output generated, and at least one function performed by a corresponding portion of the neural network circuit. 10. The system of claim 7, wherein each configuration comprises at least one constituent unit, and each constituent unit corresponds to one of the following: a portion of a core circuit, a core circuit, or another configuration. 11. The system of claim 7, wherein each configuration is a static configuration file. 12. The system of claim 7, wherein the visual processing task is one of edge detection, motion history tracking or object classification. 13. A computer program product comprising a computer-readable hardware storage medium having program code embodied therewith, the program code being executable by a computer to implement a method comprising: generating a plurality of modular, reusable, scalable configurations, wherein each configuration comprises information corresponding to a portion of a neural network circuit; and programming a multi-core circuit chip structure based on at least one of the configurations to simulate a plurality of interconnected neurosynaptic core circuits configured to perform a visual processing task. 14. The computer program product of claim 13, wherein each core circuit comprises a plurality of electronic synapses interconnecting a plurality of electronic neurons with a plurality of electronic axons. 15. The computer program product of claim 13, wherein each configuration comprises information relating to at least one input received, at least output generated, and at least one function performed by a corresponding portion of the neural network circuit. 16. The computer program product of claim 13, wherein each configuration comprises at least one constituent unit, and each constituent unit corresponds to one of the following: a portion of a core circuit, a core circuit, or another configuration. 17. The computer program product of claim 13, wherein each configuration is a static configuration file. 18. The computer program product of claim 13, wherein the visual processing task is one of edge detection, motion history tracking or object classification.