A method for creating on chip analog mathematical engines is provided utilizing a neural network with a switched capacitor structure to implement coefficients for weighted connections and error functions for the neural network. The neural networks are capable of any transfer function, learning, doing pattern recognition, clustering, control or many other functions. The switched capacitor charge controls allow for nodal control of charge transfer based switched capacitor circuits. The method reduces reliance on passive component programmable arrays to produce programmable switched capacitor circuit coefficients. The switched capacitor circuits are dynamically scaled without having to rely on switched in unit passives, such as unit capacitors, and the complexities of switching these capacitors into and out of circuit. The current, and thus the charge transferred is controlled at a nodal level, and the current rather than the capacitors are scaled providing a more accurate result in addition to saving silicon area.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A neural network comprising: one or more neurons formed by switched capacitor circuits, said switched capacitor circuits comprising input switched capacitors and output switched capacitors; wherein said one or more neurons have a set of weighted input connections, said weighted input connections created by one or more of said input switched capacitors; and wherein said switched capacitor output capacitors represents the neuron summers. 2. The neural network of claim l wherein said switched capacitor circuit further comprises: a first current source coupled to said output switched capacitor; a second current source coupled to a comparison node coupling the input and output switched capacitors; and a comparison device coupled to said comparison node and coupled to said current sources such that the current sources are turned off once they reach a reference level; wherein the resulting ratio of currents into said input and output switched capacitors may be programmed relative to one another to set the weightings of said weighted input connections. 3. The neural network of claim 1 wherein said weighted input connections further comprise: two or more current sources sealed relative to the other in magnitude, one current source coupled to said output switched capacitor charging a series connection of said switched capacitors and the other modifying the current into the input switched capacitor until the voltage on the node coupling said capacitors reaches a reference potential; wherein the ratio of currents into said input switched capacitor and said output switched capacitor may now be used to control the ratio of charge imparted on said first input switched capacitor relative to said second output switched capacitor such that said scaling of said current magnitudes may be used to produce a programmable gain or weight. 4. The neural network of claim 3 further comprising: a decision function device coupled to said output capacitors; where said decision function outputs a decision in conformance with the voltage on the output capacitor at the end of the charge period. 5. A neural network comprising: an input layer; an output layer; one or more hidden layers; neurons comprising a switched capacitor circuit, wherein said switched capacitor circuit comprises a comparison device and a plurality of switched input capacitors and a single output switched capacitor; wherein for each neuron at least one current source is coupled to a node shared by said plurality of switched input capacitors, said comparator and said output switched capacitor for each of said switched input capacitors; a single current source is coupled to said output capacitor; and wherein said at least one current source coupled to said input capacitor current is programmed in magnitude relative to the output capacitor current source so as to program the weighting coefficients of the weighted inputs. 6. The neural network of claim 5 further comprising a training device where an error propagation minimization function is used to adjust the magnitude of said weighting coefficients in conformance with an input layer and a target output layer. 7. The neural network of claim 6 wherein a floating gate non-volatile memory is used to store the magnitude of said at least one current source, and thus the weighting coefficients, once the error propagation minimization in said neural network is trained. 8. The neural network of claim 6 wherein a digital non-volatile memory is used to store the magnitude of said at least one current source, and thus the weighting coefficients, once error propagation minimization in said neural network is trained. 9. The neural network of claim 5 further comprising a set of bias inputs created with an additional input switched capacitor coupled to a reference and a current source coupled to said shared node to establish the weighting of said bias input. 10. The neural network of claim 5 wherein said plurality of current sources coupled to said plurality of input capacitors which is used to weight said input connections are combined into a reduced number of current sources or a single current source of a magnitude equal to the sum of said plurality of current sources. 11. The neural network of claim 5 further comprising: at least two of said neurons; and a single input switched capacitor in place of said plurality of input capacitors coupled to a reference; wherein current sources whose magnitudes correlate to input values are coupled to one or more current multipliers at each of said neurons to multiply said input currents by desired weight coefficients; wherein said multiplied input currents are coupled to said comparison node. 12. The neural network of claim 11 wherein said neural network learns by adjustment of said weighting coefficients according to an error minimization function which propagates through the neurons until a minimization constraint is reached; 13. The neural network of claim 12 where said multiplier is an analog multiplier. 14. The neural network of claim 4 wherein said decision function is implemented with a comparator. 15. The neural network of claim 4 wherein said decision function is implemented as a linear transconductor. 16. The neural network of claim 4 wherein said decision function is a wavelet. 17. The neural network of claim 3 where the ratio of charge imparted onto said input switched capacitor versus said output switched capacitor of said neurons is controlled by turning one current source on later than another and/or turning off one current source before the other during the charge transfer period; 18. The neural network of claim 4 further comprising: a nuller circuit; wherein errors related to non-idealities of said at least one current source and said comparator are removed with said nuller circuit. 19. The neural network of claim 4, further comprising: a programmable multiplexer configured to couple at least one of said neuron inputs to elements in at least one of said input layers and hidden layers and to couple said output decision to an element of an output layer or hidden layer; and a clocking device wherein unused neurons are not gated. 20. The neural network of claim 4, wherein the neural network is used to identify a pattern.