Systems and methods of implementing a more efficient and less resource-intensive CNN are disclosed herein. In particular, applications of CNN in the analog domain using Sampled Analog Technology (SAT) methods are disclosed. Using a CNN design with SAT results in lower power usage and faster operation as compared to a CNN design with digital logic and memory. The lower power usage of a CNN design with SAT can allow for sensor devices that also detect features at very low power for isolated operation.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A convolutional neural network using sampled analog technology, comprising: an input source including first and second analog input data points, a first set of capacitors for analyzing the first analog input data point and outputting a first analog convolution output, and a second set of capacitors for analyzing the second analog input data point and outputing a second analog convolution output, wherein the first and second analog convolution outputs each include a plurality of features. 2. The convolutional neural network of claim 1, further comprising an array of variable capacitance structures, wherein the first and second outputs are multiplexed through the array of variable capacitance structures to generate a multiplexed convolution output. 3. The convolutional neural network of claim 1, wherein the first and second sets of capacitors comprise fixed capacitors, and wherein the fixed capacitors are analog memory cells. 4. The convolutional neural network of claim 1, wherein the first and second sets of capacitors are variable capacitance cells with fixed weights. 5. The convolutional neural network of claim 4, wherein the fixed weights are implemented using a memory capacitor size, and wherein the memory capacitor size is equal to a weight of the fixed weights. 6. The convolutional neural network of claim 1, wherein the first set of capacitors and the second set of capacitors are driven by the input source. 7. The convolutional neural network of claim 1, further comprising: a first fixed voltage source having a charge, and a first capacitor digital-to-analog converter (capDAC), wherein a charge from the first fixed voltage source is sampled by the first capDAC to generate a first bias value, and wherein the first bias value is added to the first output. 8. The convolutional neural network of claim 1, further comprising a sub-sampler coupled to the first and second analog convolution outputs, wherein the sub-sampler averages the first and second analog convolution outputs to generate a mean convolution output, and wherein the sub-sampler processes the mean convolution output with a nonlinear transfer function. 9. The convolutional neural network of claim 8, wherein the nonlinear transfer function is an analog rectification function. 10. The convolutional neural network of claim 1, further comprising a sub-sampler coupled to the first analog convolution output, wherein the first analog convolution output includes a subwindow of values, and wherein the sub-sampler includes a plurality of analog voltage comparators for determining a maximum value of the subwindow of values of the first analog convolution output. 11. A method for implementing a neural network using sampled analog technology, comprising: receiving analog input data including first and second analog input data points, analyzing the first analog input data point with a first set of capacitors to generate a first analog convolution output, and analyzing the second analog input data point with a second set of capacitors to generate a second analog convolution output, wherein generating the first and second analog convolution outputs includes performing an analog convolution operation on a plurality of features. 12. The method of claim 11, further comprising multiplexing the first and second analog convolution outputs through an array of variable capacitance structures to generate an analog multiplexed convolution output. 13. The method of claim 11, wherein the first and second sets of capacitors are variable capacitance cells, the first set of capacitors have a first fixed weight, and the second set of capacitors have a second fixed weight, and wherein generating the first analog convolution output includes multiplying the first input data point with the first fixed weight, and generating the second analog convolution output includes multiplying the second input data point with the second fixed weight. 14. The method of claim 11, further comprising: generating a first bias value by sampling, using a first capacitor digital-to-analog converter, a scaled charge from a first fixed voltage source, and adding the first bias value to the first output. 15. The method of claim 11, further comprising averaging the first analog convolution output with the second analog convolution output at a sub-sampler. 16. The method of claim 11, wherein the first analog convolution output includes a subwindow of values, and further comprising determining a maximum value of the subwindow of values. 17. A convolutional neural network using sampled analog technology, comprising an input including analog input data, a plurality of sets of capacitors, each set of capacitors configured to analyze a respective subwindow of the analog input data and output an analog convolution output for the respective subwindow, wherein the analog convolution output includes a plurality of features, and an analog sub-sampler coupled to the analog convolution output, wherein the analog sub-sampler is configured to reduce a size of at least one of the plurality of features of the analog convolution output. 18. The convolutional neural network of claim 17, wherein the plurality of sets of capacitors comprise fixed capacitors, and wherein the fixed capacitors are analog memory cells. 19. The convolutional neural network of claim 17, wherein the plurality of sets of capacitors comprise variable capacitance cells with fixed weights. 20. The convolutional neural network of claim 17, further comprising: a fixed voltage source having a charge, and a capacitor digital-to-analog converter (capDAC), wherein a charge from the fixed voltage source is sampled by the capDAC to generate a bias value, and wherein the bias value is added to an output from one of the plurality of sets of capacitors.