The technical disclosure relates to artificial neural network. In particular, the technical disclosure relates to how to implement efficient data access control in the neural network hardware acceleration system. Specifically, it proposes an overall design of a device that can process data receiving, bit-width transformation and data storing. By employing the technical disclosure, neural network hardware acceleration system can avoid the data access process becomes the bottleneck in neural network computation.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A data access control device used for a neural network acceleration system, comprising: a parameter access control circuit, configured to read parameters required by a plurality of processing elements (PEs) from a memory, and perform bit-width transformation operation on said parameters and output the transformed parameters to said PEs; a vector access control circuit, configured to read vectors required by PEs from the memory, perform bit-width transformation operation on said vectors and output the transformed vectors to said PEs; a computation result access control circuit, configured to read computation results from said PEs, perform bit-width transformation operation on said computation results and output the transformed computation results to the memory. 2. The device of claim 1, wherein said parameter access control circuit further comprises: at least one parameter buffer, configured to store received parameters; and at least one bit-width converter, configured to perform bit-width transformation operation on said parameters. 3. The device of claim 1, wherein said vector access control circuit further comprises: at least one vector buffer, configured to store received vectors; and at least one bit-width converter, configured to perform bit-width transformation operation on said vectors. 4. The device of claim 1, wherein said computation result access control circuit further comprises: at least one vector buffer, configured to store received computation results; and at least one bit-width converter, configured to perform bit-width transformation operation on said computation results. 5. The device of any of claims 2-4, wherein the number of bit-width converters is no less than m×n÷d, wherein m is the number of said PEs, n is the number of data to be processed or to be output by one PE per computation cycle, and d is the computation delay. 6. The device of any of claims 2-4, wherein said bit-width converter operation is implemented by two cascaded asynchronous FIFOs, one is a 512 bit-to-64 bit converter and the other is 64 bit-to-16 bit to converter. 7. The device of claim 1, wherein said parameters comprises at least weight, bias, diagnose matrix data of said neural network. 8. A data access control device used for a neural network acceleration system, comprising: first memory configured for storing weight data of the neural network; second memory configured for storing input vectors, bias data of the neural network; first memory controller configured for reading the weight data from the first memory and outputting said weight data to a plurality of processing elements (PEs); second memory controller configured for reading the input vectors and bias data from the second memory, conducting bit-width conversion on the input vectors and bias data, and outputting said converted input vectors and bias data to the processing elements. 9. The data access control device of claim 8, wherein the second memory controller further comprising: at least one bit-width converter, configured to perform bit-width transformation operation. 10. The device of claim 8, wherein the second memory controller further comprising: a computation result access control circuit, configured to read computation results from said PEs, perform bit-width conversion operation on said computation results and output the transformed computation results to the first memory. 11. The device of claim 9, wherein said bit-width converter operation is implemented by two cascaded asynchronous FIFOs, one is a 512 bit-to-64 bit converter and the other is 64 bit-to-l6 bit to converter. 12. The device of claim 9, wherein the number of bit-width converters is no less than m×n÷d, wherein m is the number of said PEs, n is the number of data to be processed or to be output by one PE per computation cycle, and d is the computation delay.