Provided is an operation method of a convolution circuit. The method includes receiving input feature maps, generating output feature maps corresponding to the respective input feature maps through convolution operations for performing parallel processing with a kernel unit, and outputting the output feature maps to an external memory.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. An operation method of a convolution circuit, the method comprising: receiving input feature maps; generating output feature maps corresponding to the respective input feature maps through convolution operations by performing parallel processing with a kernel unit; and outputting the output feature maps to an external memory. 2. The method of claim 1, wherein the kernel unit is K×K window filtering (K is a natural number). 3. The method of claim 2, further comprising storing K lines of each of the input feature maps in an internal memory of a chip. 4. The method of claim 2, wherein the generating the output feature maps comprises storing kernels necessary for generating the output feature maps in the external memory. 5. The method of claim 1, further comprising repeating loading and accumulating a partial sum of the convolution operation from the external memory, or storing the partial sum in the external memory. 6. The method of claim 1, at least one of the parallel processing convolutions may use a physically different memory for its data multiplied by the kernel weights. 7. The method of claim 1, wherein result values of each of the convolution operations are stored in the external memory in a predetermined order. 8. The method of claim 1, wherein at least one of the convolution operations is performed while outputting at least one of the output feature maps to the external memory. 9. The method of claim 1, wherein a plurality of feature map data are output at the same time while receiving the plurality of feature map data from the external memory. 10. A convolution circuit comprising: a direct memory access (DMA) processing unit configured to read data from an external memory or output data to the external memory; a kernel buffer configured to store kernel data for connecting an input feature map being processed and N output feature maps; a bottom buffer configured to store a plurality of input data corresponding to an input feature map; an input data load unit configured to store the N kernel data and M input feature map data from the DMA processing unit into the kernel buffer; a kernel/data supply unit configured to output P (P is a natural number of 2 or more) K×K input data of the bottom buffer and P K×K kernel data of the kernel buffer; a pipeline parallel kernel processing unit configured to perform a convolution operation to the K×K input data by using K×K kernel weight values for each P kernel processing; a result reception unit configured to receive a result value of the pipeline parallel kernel processing unit; a partial top buffer configured to store the intermediate result values; and a control unit configured to control the DMA control unit, the kernel buffer, the bottom buffer, the input data load unit, the kernel/data supply unit, the pipeline parallel kernel processing unit, the result reception unit, and the partial top buffer. 11. The convolution circuit of claim 10, wherein the DMA processing unit comprises: a read first-in, first-out (FIFO) memory configured to store a plurality of input feature map data and kernel data from the external memory; and a write FIFO memory configured to store a plurality of output feature map data to be written in the external memory. 12. The convolution circuit of claim 10, wherein the kernel buffer is implemented as a dual port random access memory (DPRAM) for storing the N kernel data and outputting the P kernel data for parallel processing at the same time. 13. The convolution circuit of claim 11, wherein the kernel buffer further loads kernel data from the external memory in an order of an input feature map, and loads kernel data to a memory in an order of processing output feature maps when processing the input feature map, and wherein a storage order of each kernel data is to store the kernel data with a row unit first and then to store the kernel data with a column unit in each row. 14. The convolution circuit of claim 13, wherein the kernel buffer further allocates a different physical memory for each row of a kernel. 15. The convolution circuit of claim 11, wherein the kernel buffer collects the K weight values from the read FIFO memory and stores the K weight values in a corresponding memory. 16. The convolution circuit of claim 11, wherein the bottom buffer outputs all data in a kernel window at the same time while the kernel window for input data moves in the input feature map. 17. The convolution circuit of claim 16, wherein the kernel/data supply unit further reads input data corresponding to the kernel window from the bottom buffer according to a row and column index of an output feature map and read the P kernel data for processing the data read from the kernel buffer. 18. The convolution circuit of claim 17, wherein the pipeline parallel kernel processing unit outputs the P result values by performing a multiplication operation and an addition operation on the input data and corresponding kernel weight values delivered from the kernel/data supply unit. 19. The convolution circuit of claim 11, further comprising an output data storage unit configured to read the intermediate result values from the partial top buffer and transmit the accumulated intermediate result values to the write FIFO memory of the DMA processing unit. 20. An operation method of an application processor, the method comprising: performing parallel convolution operations on each of input feature maps to extract features; and performing sub-sampling operations on each of result values of the parallel convolution operation to extract the features, wherein the performing of the parallel convolution operations comprises outputting intermediate result values to an external memory at the same time while receiving input data from the external memory.