In one embodiment, the present invention provides a neural network circuit comprising multiple symmetric core circuits. Each symmetric core circuit comprises a first core module and a second core module. Each core module comprises a plurality of electronic neurons, a plurality of electronic axons, and an interconnection network comprising multiple electronic synapses interconnecting the axons to the neurons. Each synapse interconnects an axon to a neuron. The first core module and the second core module are logically overlayed on one another such that neurons in the first core module are proximal to axons in the second core module, and axons in the first core module are proximal to neurons in the second core module. Each neuron in each core module receives axonal firing events via interconnected axons and generates a neuronal firing event according to a neuronal activation function.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A method, comprising: receiving a first firing event generated by a first neural network circuit of a plurality of neural network circuits, wherein the plurality of neural network circuits are interconnected via a plurality of routers, each router corresponds to a neural network circuit of the plurality of neural network circuits, and each router comprises a compact lookup table (LUT) maintaining routing information for each firing event generated by a corresponding neural network circuit; retrieving routing information for the first firing event from a first router of the plurality of routers, wherein the first router corresponds to the first neural network circuit; generating a first packet for the first firing event based on the routing information retrieved; and routing the first packet between the plurality of neural network circuits via the plurality of routers. 2. The method of claim 1, wherein each neural network circuit comprises a plurality of electronics neurons interconnected to a plurality of electronic axons via a plurality of electronic synapses. 3. The method of claim 2, wherein each packet for each firing event is routed to a target axon of a neural network circuit of the plurality of neural network circuits. 4. The method of claim 3, wherein routing information for a firing event comprises at least one of: a distance to a target axon, a direction to the target axon, an address of the target axon, and a delivery time indicative of a time a packet for the firing event is scheduled for delivery to the target axon. 5. The method of claim 4, wherein the plurality of neural network circuits are organized into multiple regions, each region comprising a group of axons representing a fascicle. 6. The method of claim 5, wherein each LUT of each router is compact as the router routes outgoing packets to and receives incoming packets from a same region of the plurality of neural network circuits, such that the outgoing packets traverse an identical route but are delivered to different target axons of the same region. 7. The method of claim 6, wherein a compact LUT allows one or more parametrized chip compiler variants to be generated on the fly. 8. A system comprising a computer processor, a computer-readable hardware storage medium, and program code embodied with the computer-readable hardware storage medium for execution by the computer processor to implement a method comprising: receiving a first firing event generated by a first neural network circuit of a plurality of neural network circuits, wherein the plurality of neural network circuits are interconnected via a plurality of routers, each router corresponds to a neural network circuit of the plurality of neural network circuits, and each router comprises a compact lookup table (LUT) maintaining routing information for each firing event generated by a corresponding neural network circuit; retrieving routing information for the first firing event from a first router of the plurality of routers, wherein the first router corresponds to the first neural network circuit; generating a first packet for the first firing event based on the routing information retrieved; and routing the first packet between the plurality of neural network circuits via the plurality of routers. 9. The system of claim 8, wherein each neural network circuit comprises a plurality of electronics neurons interconnected to a plurality of electronic axons via a plurality of electronic synapses. 10. The system of claim 9, wherein each packet for each firing event is routed to a target axon of a neural network circuit of the plurality of neural network circuits. 11. The system of claim 10, wherein routing information for a firing event comprises at least one of: a distance to a target axon, a direction to the target axon, an address of the target axon, and a delivery time indicative of a time a packet for the firing event is scheduled for delivery to the target axon. 12. The system of claim 11, wherein the plurality of neural network circuits are organized into multiple regions, each region comprising a group of axons representing a fascicle. 13. The system of claim 12, wherein each LUT of each router is compact as the router routes outgoing packets to and receives incoming packets from a same region of the plurality of neural network circuits, such that the outgoing packets traverse an identical route but are delivered to different target axons of the same region. 14. The system of claim 13, wherein a compact LUT allows one or more parametrized chip compiler variants to be generated on the fly. 15. A computer program product comprising a computer-readable hardware storage device having program code embodied therewith, the program code being executable by a computer to implement a method comprising: receiving a first firing event generated by a first neural network circuit of a plurality of neural network circuits, wherein the plurality of neural network circuits are interconnected via a plurality of routers, each router corresponds to a neural network circuit of the plurality of neural network circuits, and each router comprises a compact lookup table (LUT) maintaining routing information for each firing event generated by a corresponding neural network circuit; retrieving routing information for the first firing event from a first router of the plurality of routers, wherein the first router corresponds to the first neural network circuit; generating a first packet for the first firing event based on the routing information retrieved; and routing the first packet between the plurality of neural network circuits via the plurality of routers. 16. The computer program product of claim 15, wherein each neural network circuit comprises a plurality of electronics neurons interconnected to a plurality of electronic axons via a plurality of electronic synapses. 17. The computer program product of claim 16, wherein each packet for each firing event is routed to a target axon of a neural network circuit of the plurality of neural network circuits. 18. The computer program product of claim 17, wherein routing information for a firing event comprises at least one of: a distance to a target axon, a direction to the target axon, an address of the target axon, and a delivery time indicative of a time a packet for the firing event is scheduled for delivery to the target axon. 19. The computer program product of claim 18, wherein the plurality of neural network circuits are organized into multiple regions, each region comprising a group of axons representing a fascicle. 20. The computer program product of claim 19, wherein each LUT of each router is compact as the router routes outgoing packets to and receives incoming packets from a same region of the plurality of neural network circuits, such that the outgoing packets traverse an identical route but are delivered to different target axons of the same region.