A memory controlled circuit includes a configurable circuit element electrically coupled to a first terminal and to a second terminal. The circuit may further include a transconductor. A first input of the transconductor may be electrically coupled to the first terminal and a second input of the transconductor may be electrically coupled to the second terminal. The circuit may also include a switch coupled to an output of the transconductor. The circuit may include a dynamic analog memory electrically coupled to the configurable circuit element and to the switch.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A memory controlled circuit comprising: a configurable circuit element electrically coupled to a first terminal and to a second terminal; a transconductor, wherein a first input of the transconductor is electrically coupled to the first terminal and a second input of the transconductor is electrically coupled to the second terminal; a switch coupled to an output of the transconductor; and a dynamic analog memory electrically coupled to the configurable circuit element and to the switch. 2. The memory controlled circuit of claim 1, wherein the configurable circuit comprises a transistor configured to operate in a linear region mode or a near-linear region mode. 3. The memory controlled circuit of claim 2, wherein the transistor is a zero threshold voltage transistor. 4. The memory controlled circuit of claim 2, wherein the transistor is an N-channel field effect transistor (FET), a P-channel FET, an NPN bipolar junction transistor (BJT), a PNP BJT, or a junction gate field-effect transistor (JFET). 5. The memory controlled circuit of claim 1, wherein the configurable circuit comprises a variable capacitor. 6. The memory controlled circuit of claim 5, wherein the variable capacitor comprises a three-terminal varactor. 7. The memory controlled circuit of claim 1, wherein the dynamic analog memory comprises a capacitor electrically coupled to a control input of the configurable circuit element and electrically coupled to a common voltage. 8. The memory controlled circuit of claim 7, wherein the capacitor has a capacitance of between about 100 femtofarads and five picofarads. 9. The memory controlled circuit of claim 1, further comprising a bi-stable latch coupled to the configurable circuit element. 10. The memory controlled circuit of claim 1, further comprising a strobe signal source coupled to the switch. 11. The memory controlled circuit of claim 10, wherein the strobe signal source comprises a system clock. 12. The memory controlled circuit of claim 10, wherein the strobe signal source comprises an event detector circuit, wherein a first input of the event detector circuit is electrically coupled to the first terminal and a second input of the event detector circuit is electrically coupled to the second terminal, and wherein an output of event detector circuit is electrically coupled to the switch. 13. The memory controlled circuit of claim 12, wherein the event detector circuit comprises: an absolute difference circuit configured to generate a signal indicating a magnitude of a voltage difference between the first terminal and the second terminal; and an asynchronous comparator configured to set a strobe signal to a logical high in response to the magnitude of the voltage difference exceeding a threshold. 14. The memory controlled circuit of claim 12, wherein the event detector circuit comprises: a first asynchronous comparator configured to set a strobe signal to a logical high in response to a voltage difference between the first terminal and the second terminal exceeding a first threshold; and a second asynchronous comparator configured to set the strobe signal to a logical high in response to the voltage difference between the first terminal and the second terminal being lower than a second threshold. 15. A method of controlling an electrical property of a circuit, the method comprising: sensing a voltage difference between a first terminal and a second terminal of a memory controlled circuit; changing a value of a dynamic analog memory based on the voltage difference; and changing an electrical property of a configurable circuit element positioned between the first terminal and the second terminal based on the value of the dynamic analog memory. 16. The method of claim 15, wherein changing the value of the dynamic analog memory comprises increasing or decreasing the value of the dynamic analog memory based on an integration operation performed on the sensed voltage difference over time. 17. The method of claim 15, wherein changing the electrical property comprises increasing or decreasing a resistance of the configurable circuit element or increasing or decreasing a capacitance of the configurable circuit element. 18. A system of memory controlled circuits comprising: at least one input neuron device; at least one output neuron device; at least one memory controlled circuit, wherein the at least one input neuron device is coupled to the at least one output neuron device via the at least one memory controlled circuit, and wherein the memory controlled circuit comprises: a configurable circuit element electrically coupled to a first terminal and to a second terminal; a transconductor, wherein a first input of the transconductor is electrically coupled to the first terminal and a second input of the transconductor is electrically coupled to the second terminal; a switch coupled to an output of the transconductor; and a dynamic analog memory electrically coupled to the configurable circuit element and to the switch. 19. The system of claim 18, wherein the at least one memory controlled circuit enables bi-directional communication between the at least one input neuron device and the at least one output neuron device. 20. The system of claim 18, wherein the memory controlled circuit is configured to control an electrical property of the configurable circuit element based on a voltage difference between a first voltage spike generated by the at least one input neuron device at the first terminal and a second voltage spike generated by the at least one output neuron device at the second terminal. 21. The system of claim 20, wherein the first voltage spike is generated in response to the second voltage spike or the second voltage spike is generated in response to the first voltage spike. 22. The system of claim 20, wherein the electrical property of the configurable circuit element is changed when a period of time between the first voltage spike and the second voltage spike is less than a threshold. 23. The system of claim 18, further comprising at least one analog-to-digital converter coupled to the dynamic analog memory, the analog-to-digital converter enabling a controller to perform a read operation corresponding to the dynamic analog memory. 24. The system of claim 18, further comprising at least one digital-to-analog converter coupled to the at least one memory controlled circuit, the digital-to-analog converter enabling a controller to perform a write or refresh operation corresponding to the dynamic analog memory. 25. The system of claim 18, further comprising a memory array configured to store a value corresponding to the dynamic analog memory. 26. The system of claim 18, further comprising: a plurality of input neuron devices, the plurality of input neuron devices including the at least one input neuron device; a plurality of output neuron devices, the plurality of output neuron devices including the at least one output neuron device; and a plurality of memory controlled circuits, each of the plurality of memory controlled circuits including the at least one memory controlled circuit, wherein each input neuron device of the plurality of input neuron devices is electrically coupled to each output neuron device of the plurality of output neuron devices via memory controlled circuits. 27. The system of claim 26, wherein the plurality of memory controlled circuits are organized in a cross-point array configuration, wherein the cross point array configuration is a dense neural network layer or a machine learning data structure.