An electronic neuromorphic core processor circuit and related method include a dendrite circuit comprising an input that receives an input spike message having an associated input identifier that identifies a distribution set of dendrite compartments. A synapse map provides a mapping of the received identifier to a synapse configuration in the memory. A synapse configuration circuit associates the identifier with a set of synaptic connections, possibly shared hierarchically over populations of neurons defined implicitly by the mapping structures, that are read from the memory. The synaptic connections determine n-tuple information comprising a dendriteID, a weight, and a network delay time. A dendrite accumulator circuit accumulates weight values scheduled at the appropriate future time as identified by the n-tuple information and maps them to a soma compartment. A soma circuit maintains soma compartment state in response to the accumulated weight values scheduled for servicing and, when sufficiently activated, produces output spikes.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. An electronic neuromorphic core processor circuit comprising: a dendrite circuit comprising: an input circuit configured to receive an input spike message having an associated fan-in-population index (fip index) and a source atom number; a synapse map circuit configured to provide a mapping of the received fip index to a synapse base address in the memory, a routing list size, and a dendrite compartment base index; a synapse configuration circuit, comprising a plurality of type-space routing list connectivity structures stored in the memory representing sets of synaptic connections related to dendrite compartments for different population types; a dendrite accumulator circuit and memory comprising an array indexed by the associated dendrite compartment index and the synaptic connectivity properties; and a dendrite output at which a weighted sum value representing a total accumulated amount for the dendritic compartment at an output time is sent. 2. The circuit of claim 1, wherein: the fip index represents a specific fanin arc to a particular destination population instance in the core and the source atom identifies a particular neuron within the source population type in the core that initiated the spike message; the synapse map circuit is further configured to compute a routing list base address obtained by adding the synapse base address to a product of the routing list size and the source atom number for the synapse configuration; each set of synaptic connections comprises one or more bits of weight and other connectivity properties per dendrite compartment, wherein the synapse configuration circuit is configured to associate the connectivity properties of each connection in the set with a specific dendrite compartment index calculated as a sum of the dendrite compartment base index and an offset corresponding to each synapse connection in the set; and the dendrite accumulator circuit is configured to accumulate weight values within a dendritic compartment identified by the address. 3. The circuit of claim 2, wherein the input circuit is configured to process a series of input spike messages arriving in a time-multiplexed fashion. 4. The circuit of claim 2, wherein weight values within a plurality of dendritic compartments are accumulated based on the set of synaptic connections associated with the fip idx and the atom number. 5. The circuit of claim 4; wherein each dendrite accumulator memory address associated with each dendritic compartment of the plurality of dendritic compartments is calculated as the sum of the dendritic compartment index, a service time T, and a delay time that is derived from the synaptic connectivity properties. 6. The circuit of claim 5, wherein the addresses associated with a dendrite compartment index over all delay time offsets are organized as a circular FIFO buffer. 7. The circuit of claim 2, wherein, at a service time T, a subset of a plurality of dendritic compartments of the dendrite accumulator that are associated with the service time T are processed and a plurality of weighted sum values are sent from the dendrite output. 8. The circuit of claim 7, wherein after the plurality of weighted sum values are sent, the servicing time T is indexed to a next servicing time T+1 such that T+1→T. 9. The circuit of claim 8, wherein the servicing time T is indexed to the next servicing time T+1 after receiving a handshake from neighboring cores that is a barrier synchronization message indication completion of neuron servicing by the neighboring cores. 10. The circuit of claim 2, wherein a first set of dendrite compartments associated with a first input fip index differs in size from a second set of dendrite compartments associated with a second input fip index belonging to a different population type. 11. The circuit of claim 2, further comprising: a soma circuit, comprising: a soma input connected to the dendrite output and at which the dendrite compartment weighted sum value is received comprising an index to a related soma compartment; a soma configuration memory of a soma compartment associated with the dendrite compartment, the soma configuration memory to store configuration parameters for a neuron comprising the soma compartment and that is configured to be updated by the processor based on the received weighted sum value; a soma state memory to store the neuron's present activation state level and that is configured to be updated by the processor based on the received weighted sum value, wherein if an updated present activation state level exceeds a threshold activation level value, the processor is configured to generate an output spike event comprising a spiking neuron index; an axon map memory comprising a mapping of the spiking neuron index to a spike fanout destination list identifier based on the fip index and the atom number; an axon configuration memory comprising a list of one or more destination core-fip index pairs referenced by the spike fanout destination list identifier; and an output circuit configured to route a spike message containing the source atom number and the fip index to each destination core of the list. 12. An electronic neuromorphic core processor circuit comprising: a soma circuit, comprising: a soma input at which a dendrite compartment weighted sum value is received comprising an index to a related soma compartment; a soma configuration memory of a soma compartment associated with the dendrite compartment, the soma configuration memory to store configuration parameters for a neuron comprising the soma compartment and that is configured to be updated by the processor based on the received weighted sum value; a soma state memory to store the neuron's present activation state level and that is configured to be updated by the processor based on the received weighted sum value, wherein if an updated present activation state level exceeds a threshold activation level value, the processor is configured to generate an output spike event comprising a spiking neuron index; an axon map memory to store a mapping of the spiking neuron index to a spike fanout destination list identifier based on the fip index and the atom number; an axon configuration memory to store a list of one or more destination core-fip index pairs referenced by the spike fanout destination list identifier; and an output circuit configured to route a spike message comprising the fip index and source atom number to each destination core of the list. 13. The circuit of claim 12, wherein the output spike event is delayed before being passed to the axon map by a delay amount specified in the soma configuration memory. 14. The circuit of claim 12, wherein the processor is configured to reset the present active state level if an output spike event is generated. 15. The circuit of claim 12, wherein the axon configuration memory is sharable by a plurality of neurons. 16. The circuit of claim 12, wherein the soma input is configured to receive a plurality of weighted sum values arriving in a time-multiplexed fashion. 17. The circuit of claim 12, wherein the output circuit is configured to route a plurality of output spike messages serially. 18. A system for performing neuromorphic computing, comprising: an electronic neuromorphic core processor circuit comprising: a dendrite circuit comprising: an input circuit configured to receive an input spike message having an associated fan-in-population index (fip index) and a source atom number; a synapse map circuit configured to provide a mapping of the received tip index to a synapse base address in the memory, a routing list size, and a dendrite compartment base index; a synapse configuration circuit, comprising a plurality of type-space routing list connectivity structures stored in the memory representing sets of synaptic connections related to dendrite compartments for different population types; a dendrite accumulator circuit and memory comprising an array indexed by the associated dendrite compartment index and the synaptic connectivity properties; and a dendrite output at which a weighted sum value representing a total accumulated amount for the dendritic compartment at an output time is sent. 19. The system of claim 18, wherein the input circuit is configured to process a series of input spike messages arriving in a time-multiplexed fashion. 20. A method of operating an electronic neuromorphic core processor, comprising: by a dendrite circuit: receiving an input spike message having an associated fan-in-population index (fip index) and a source atom number, the fip index representing a specific fanin arc to a particular destination population instance in the core and the source atom identifying the particular neuron within the source population type in the core that initiated the spike message; synapse mapping the fip index to a synapse configuration in a memory comprising a synapse base address, a routing list size, and a dendrite compartment base index; associating the tip index, the atom number, the synapse base address, and the routing list size with a routing list in the memory that is a set of synaptic connections related to a set of dendrite compartments in population type space, each comprising one or more bits of weight and other connectivity properties per dendrite compartment; associating each weight and other properties with a specific dendrite index calculated as the dendrite compartment base address plus an offset incrementing over each synapse connection in the associated set of connections from the memory; accumulating, in a dendrite accumulator comprising an array indexed by the dendrite index, weight values within a dendritic compartment; and sending, from a dendrite output, a weighted sum value representing a total accumulated amount for the dendritic compartment at an output time; and by a soma circuit: receiving, at a soma input connected to the dendrite output the weighted sum value comprising an index to a related soma compartment; updating, with the processor and based on the received weighted sum value: a soma state memory to store the neuron's present activation state level, wherein if an updated present activation state level exceeds a threshold activation level value, then generating an output spike event comprising a spiking neuron index; the method further comprising: routing a spike message to each destination core of list that is one or more destination core-fip index pairs referenced by a spike fanout destination list identifier that was mapped by an axon map memory from the spiking neuron index, wherein each spike message comprises the fip index and the source atom number. 21. The method of claim 20, further comprising: associating each weight with a specific dendrite index calculated as the sum of a multiple of the dendrite compartment base address plus an offset incrementing over each synapse connection, and the current service time T plus a delay time derived from the synaptic connectivity properties, modulo a maximum delay time value. 22. The method of claim 21, further comprising, at a service time T, processing a plurality of dendritic compartments of the dendrite accumulator and sending a plurality of weighted sum values from the dendrite output that are associated with the service time T. 23. The method of claim 20, further comprising, after the plurality of weighted sum values are sent, indexing the servicing time T to a next servicing time T+1 such that T+1→T after receiving a handshake from neighboring cores that is a barrier synchronization message indication completion of neuron servicing by the neighboring cores. 24. At least one machine readable medium including instructions that, when executed by an electronic neuromorphic core processor, cause the electronic neuromorphic core processor to perform operations comprising: by a dendrite circuit: receiving an input spike message having an associated fan-in-population index (fip index) and a source atom number, the fip index representing a specific fanin arc to a particular destination population instance in the core and the source atom identifying the particular neuron within the source population type in the core that initiated the spike message; synapse mapping the fip index to a synapse configuration in a memory comprising a synapse base address, a routing list size, and a dendrite compartment base index; associating the fip index, the atom number, the synapse base address, and the routing list size with a routing list in the memory that is a set of synaptic connections related to a set of dendrite compartments in population type space, each comprising one or more bits of weight and other connectivity properties per dendrite compartment; associating each weight and other properties with a specific dendrite index calculated as the dendrite compartment base address plus an offset incrementing over each synapse connection in the associated set of connections from the memory; accumulating, in a dendrite accumulator comprising an array indexed by the dendrite index, weight values within a dendritic compartment; and sending, from a dendrite output, a weighted sum value representing a total accumulated amount for the dendritic compartment at an output time. 25. The at least one machine readable medium of claim 24, the operations further comprising: by a soma circuit: receiving, at a soma input connected to the dendrite output the weighted sum value comprising an index to a related soma compartment; updating, with the processor and based on the received weighted sum value: a soma state memory to store the neuron's present activation state level, wherein if an updated present activation state level exceeds a threshold activation level value, then generating an output spike event comprising a spiking neuron index; the method further comprising: routing a spike message to each destination core of list that is one or more destination core-fip index pairs referenced by a spike fanout destination list identifier that was mapped by an axon map memory from the spiking neuron index, wherein each spike message comprises the fip index and the source atom number.