A method of reducing computational complexity for a fixed point neural network operating in a system having a limited bit width in a multiplier-accumulator (MAC) includes reducing a number of bit shift operations when computing activations in the fixed point neural network. The method also includes balancing an amount of quantization error and an overflow error when computing activations in the fixed point neural network.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A method of reducing computational complexity for a fixed point neural network operating in a system having a limited bit width in a multiplier-accumulator (MAC), comprising: reducing a number of bit shift operations when computing activations in the fixed point neural network; and balancing an amount of quantization error and an overflow error when computing activations in the fixed point neural network. 2. The method of claim 1, in which the balancing comprises reducing the number of bit shift operations before an intermediate addition step to balance a likelihood of overflow and the amount of quantization error. 3. The method of claim 1, further comprising adding a number (K) of terms while computing activations before performing a bit shift operation. 4. The method of claim 3, in which the number is based at least in part on a balance between decreasing bit shift operations and preventing the overflow error. 5. The method of claim 3, in which the adding occurs in a register of the MAC and the bit shift operation occurs before writing to memory. 6. The method of claim 3, further comprising modifying a number format of input activations and/or a number format of weights before adding the number (K) of terms to reduce a likelihood of overflow. 7. The method of claim 1, further comprising modifying a number format of input activations and/or a number format of weights to reduce the number of bit shift operations to zero. 8. The method of claim 7, in which the modifying further comprises increasing a number of integer bits and/or decreasing a number of fractional bits in a first number format of the input activations and/or a second number format of the weights. 9. An apparatus for reducing computational complexity for a fixed point neural network operating in a system having a limited bit width in a multiplier-accumulator (MAC), the apparatus comprising: means for reducing a number of bit shift operations when computing activations in the fixed point neural network; and means for balancing an amount of quantization error and an overflow error when computing activations in the fixed point neural network. 10. The apparatus of claim 9, in which the means for balancing comprises means for reducing the number of bit shift operations before an intermediate addition step to balance a likelihood of overflow and the amount of quantization error. 11. The apparatus of claim 9, further comprising means for adding a number (K) of terms while computing activations before performing a bit shift operation. 12. The apparatus of claim 11, in which the number is based at least in part on a balance between decreasing bit shift operations and preventing the overflow error. 13. The apparatus of claim 11, in which the adding occurs in a register of the MAC and the bit shift operation occurs before writing to memory. 14. The apparatus of claim 11, further comprising means for modifying a number format of input activations and/or a number format of weights before adding the number (K) of terms to reduce a likelihood of overflow. 15. The apparatus of claim 9, further comprising means for modifying a number format of input activations and/or a number format of weights to reduce the number of bit shift operations to zero. 16. The apparatus of claim 15, further comprising means for increasing a number of integer bits and/or decreasing a number of fractional bits in a first number format of the input activations and/or a second number format of the weights. 17. An apparatus for reducing computational complexity for a fixed point neural network operating in a system having a limited bit width in a multiplier-accumulator (MAC), the apparatus comprising: a memory unit; and at least one processor coupled to the memory unit, the at least one processor configured: to reduce a number of bit shift operations when computing activations in the fixed point neural network; and to balance an amount of quantization error and an overflow error when computing activations in the fixed point neural network. 18. The apparatus of claim 17, in which the at least one processor is further configured to reduce the number of bit shift operations before an intermediate addition step to balance a likelihood of overflow and the amount of quantization error. 19. The apparatus of claim 17, in which the at least one processor is further configured to add a number (K) of terms while computing activations before performing a bit shift operation. 20. The apparatus of claim 19, in which the number is based at least in part on a balance between decreasing bit shift operations and preventing the overflow error. 21. The apparatus of claim 19, in which the adding occurs in a register of the MAC and the bit shift operation occurs before writing to memory. 22. The apparatus of claim 19, in which the at least one processor is further configured to modify a number format of input activations and/or a number format of weights before adding the number (K) of terms to reduce a likelihood of overflow. 23. The apparatus of claim 17, in which the at least one processor is further configured to modify a number format of input activations and/or a number format of weights to reduce the number of bit shift operations to zero. 24. The apparatus of claim 23, in which the at least one processor is further configured to increase a number of integer bits and/or decreasing a number of fractional bits in a first number format of the input activations and/or a second number format of the weights. 25. A non-transitory computer-readable medium for a fixed point neural network operating in a system having a limited bit width in a multiplier-accumulator (MAC), the non-transitory computer-readable medium having program code recorded thereon, the program code being executed by a processor and comprising: program code to reduce a number of bit shift operations when computing activations in the fixed point neural network; and program code to balance an amount of quantization error and an overflow error when computing activations in the fixed point neural network. 26. The non-transitory computer-readable medium of claim 25, further comprising program code to decrease the number of bit shift operations before an intermediate addition step to balance a likelihood of overflow and the amount of quantization error. 27. The non-transitory computer-readable medium of claim 25, further comprising program code to add a number (K) of terms while computing activations before performing a bit shift operation. 28. The non-transitory computer-readable medium of claim 27, in which the number is based at least in part on a balance between decreasing bit shift operations and preventing the overflow error. 29. The non-transitory computer-readable medium of claim 27, in which the adding occurs in a register of the MAC and the bit shift operation occurs before writing to memory. 30. The non-transitory computer-readable medium of claim 27, further comprising program code to modify a number format of input activations and/or a number format of weights before adding the number (K) of terms to reduce a likelihood of overflow.