A tunable resistance device and methods of forming the same include a magnetic fixed layer having a fixed magnetization, a magnetic free layer, and a non-magnetic conductive layer directly between the magnetic fixed layer and the magnetic free layer. The magnetic fixed layer, the magnetic free layer, and the non-magnetic conductive layer are formed in a lattice of wires, with each wire in the lattice being formed from a stack of the magnetic fixed layer, the magnetic free layer, and the non-magnetic conductive layer.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A tunable resistance device, comprising: a magnetic fixed layer having a fixed magnetization; a magnetic free layer; and a non-magnetic conductive layer directly between the magnetic fixed layer and the magnetic free layer, wherein the magnetic fixed layer, the magnetic free layer, and the non-magnetic conductive layer are formed in a lattice of wires, with each wire in the lattice being formed from a stack of the magnetic fixed layer, the magnetic free layer, and the non-magnetic conductive layer. 2. The tunable resistance device of claim 1, further comprising a first via in contact with one of the magnetic fixed layer and the magnetic free layer and a second via in contact with one of the magnetic free layer and the magnetic fixed layer, wherein the first via and the second via are not vertically aligned. 3. The tunable resistance device of claim 2, wherein one of the first via and the second via comprises a symmetric diode. 4. The tunable resistance device of claim 3, wherein the symmetric diode is a mixed ionic-electronic conduction diode. 5. The tunable resistance device of claim 1, wherein the magnetic free layer has a single magnetic domain wall. 6. The tunable resistance device of claim 1, wherein the magnetic free layer has a plurality of magnetic domain walls. 7. The tunable resistance device of claim 1, wherein the neural network synapse has a tunable resistance based on a number and position of domain walls in the magnetic free layer. 8. The tunable resistance device of claim 1, wherein the magnetic free layer comprises one or more notches to pin magnetic domain walls. 9. A neural network, comprising: a plurality of neurons, comprising a layer of input neurons, one or more layers of hidden neurons, and a layer of output neurons; a plurality of arrays of synapses, each array of synapses being configured to accept voltage pulses from a first layer of neurons and to output current to a second layer of neurons during a feed forward operation, each synapse in each array of synapses having a respective settable resistance and comprising: a magnetic fixed layer having a fixed magnetization; a magnetic free layer; and a non-magnetic conductive layer directly between the magnetic fixed layer and the magnetic free layer. 10. The neural network of claim 9, wherein each synapse further comprises a first via in contact with one of the magnetic free layer and the magnetic fixed layer and a second via in contact with one of the magnetic free layer and the magnetic fixed layer. 11. The neural network of claim 10, wherein one of the first via and the second via of each synapse comprises a symmetric diode. 12. The neural network of claim 11, wherein each symmetric diode is a mixed ionic-electronic conduction diode. 13. The neural network of claim 9, wherein the magnetic free layer of each synapse has a single magnetic domain wall that is positioned at one of one or more notches. 14. The neural network of claim 9, wherein the magnetic free layer of each synapse has a plurality of magnetic domain walls, each positioned at one of a plurality of notches. 15. A method of forming a tunable resistance device, comprising: forming a magnetic fixed layer having a fixed magnetization; forming a non-magnetic conductive layer on the magnetic fixed layer; and forming a magnetic free layer on the non-magnetic conductive layer, wherein the magnetic fixed layer, the magnetic free layer, and the non-magnetic conductive layer are formed in a lattice of wires, with each wire in the lattice being formed from a stack of the magnetic fixed layer, the magnetic free layer, and the non-magnetic conductive layer. 16. The method of claim 15, further comprising forming a first via in contact with one of the magnetic free layer and the magnetic fixed layer and a second via in contact with one of the magnetic free layer and the magnetic fixed layer. 17. The method of claim 16, further comprising forming a symmetric diode in one of the first via and the second via. 18. The method of claim 17, wherein the symmetric diode is a mixed ionic-electronic conduction diode. 19. The method of claim 15, further comprising inducing a uniform magnetization in the magnetic free layer and then forming one or more initial domain walls in the magnetic free layer. 20. The method of claim 15, further comprising forming one or more notches in the magnetic free layer to pin magnetic domain walls.