A memory holds D rows of N words and receives an address having log2D bits and an extra bit. Each of N processing units (PU) of index J has first and second registers, an accumulator, an arithmetic unit that performs an operation thereon to accumulate a result, and multiplexing logic receiving memory word J, and for PUs 0 to (N/2)−1 also memory word J+(N/2). In a first mode, the multiplexing logic of PUs 0 to N−1 selects word J to output to the first register. In a second mode: when the extra bit is a zero, the multiplexing logic of PUs 0 to (N/2)−1 selects word J to output to the first register, and when the extra bit is a one, the multiplexing logic of PUs 0 through (N/2)−1 selects word J+(N/2) to output to the first register.
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CLAIM: 1 An apparatus, comprising: a memory that receives an address and that holds D rows of N words indexed as 0 through N−1, wherein N is at least 512, wherein the address has log2D bits and an extra bit; an array of N processing units (PU) indexed as 0 through N−1, each PU of index J having: first and second registers; an accumulator; an arithmetic unit having first, second and third inputs and that performs an operation thereon to generate a result to store in the accumulator, the first input receives an output of the accumulator, the second input receives a word output by the first register, the third input receives a word output by the second register; and multiplexing logic that receives word J output by the memory, and in the case of PUs 0 through (N/2)−1 also receives word J+(N/2) output by the memory, and outputs a selected word to the first register; wherein in a first mode, the multiplexing logic of PUs 0 through N−1 selects word J output by the memory to output to the first register of PU J; and wherein in a second mode: when the address extra bit is a first value, the multiplexing logic of PUs 0 through (N/2)−1 selects word J output by the memory to output to the first register of PU J; and when the address extra bit is a second value, the multiplexing logic of PUs 0 through (N/2)−1 selects word J+(N/2) output by the memory to output to the first register of PU J. 2. The apparatus of claim 1, wherein in the second mode the memory is effectively configured to hold 2*W rows of N/2 words for provision to PUs 0 through (N/2)−1. 3. The apparatus of claim 1, further comprising: for J equal to 0 through (N/2)−1: second multiplexing logic that receives a first result that is a function of the accumulator of PU J and that receives a second result that is a function of the accumulator of PU J+(N/2) and outputs a selected result for the memory to write to word J+(N/2) of a row of the memory; wherein in the first mode, the memory writes words 0 through (N/2)−1 of a row with N/2 results that are a function of the accumulators of respective PUs 0 through (N/2)−1 and, for J equal to 0 through (N/2)−1, the second multiplexing logic selects the second result to output for the memory to write to word J+(N/2) of the row; and wherein in the second mode: when the address extra bit is the first value, the memory writes words 0 through (N/2)−1 of a row with N/2 results that are a function of the accumulators of respective PUs 0 through (N/2)−1, and the memory does not write words N/2 through N−1 of the row; and when the address extra bit is the second value, the memory does not write words 0 through (N/2)−1 of a row and, for J equal to 0 through (N/2)−1, the second multiplexing logic selects the first result to output for the memory to write to word J+(N/2) of the row. 4. The apparatus of claim 3, wherein the function of the accumulator is a neural network activation function. 5. The apparatus of claim 1, wherein in the second mode: when the address extra bit is the first value, the memory outputs words 0 through (N/2)−1 of a row selected by the log2D address bits, but does not output words N/2 through N−1; and when the address extra bit is the second value, the memory outputs words N/2 through N−1 of a row selected by the log2D address bits, but does not output words 0 through (N/2)−1. 6. The apparatus of claim 1, wherein the multiplexing logic further receives the word output by the first register of PU J−1 and outputs a selected word to the first register, wherein PU J−1 is PU N−1 for PU 0; and wherein in a third mode, the multiplexing logic alternatively selects the word output by the first register of PU J−1 to output to the first register. 7. The apparatus of claim 1, wherein the multiplexing logic further receives the word output by the first register of PU J−1 and outputs a selected word to the first register, wherein PU J−1 is PU (N/2)−1 for PU 0; and wherein in a third mode, the multiplexing logic selects the word output by the first register of PU J−1 to output to the first register, and PUs N/2 through N−1 are powered off. 8. The apparatus of claim 1, further comprising: a second memory that holds W rows of N words indexed as 0 through N−1 and that receives a second address, wherein the second address has log2W bits and a second extra bit; and each PU of index J further having: second multiplexing logic that receives word J output by the second memory, and in the case of PUs 0 through (N/2)−1 also receives word J+(N/2) output by the second memory, and outputs a selected word to the second register. 9. The apparatus of claim 8, further comprising: wherein in the first mode, the second multiplexing logic of PUs 0 through N−1 selects word J output by the second memory to output to the second register of PU J; and wherein in the second mode: when the address second extra bit is a first value, the second multiplexing logic of PUs 0 through (N/2)−1 selects word J output by the second memory to output to the second register of PU J; and when the address second extra bit is a second value, the second multiplexing logic of PUs 0 through (N/2)−1 selects word J+(N/2) output by the second memory to output to the second register of PU J. 10. The apparatus of claim 1, wherein the address further includes a second extra bit; wherein in the case of PUs 0 through (N/4)−1, the multiplexing logic further receives word J+(N/4) and word J+(3N/4) output by the memory, and outputs a selected word to the first register; wherein in a third mode: when the address first and second extra bits are a first value, the multiplexing logic of PUs 0 through (N/4)−1 selects word J output by the memory to output to the first register of PU J; when the address first and second extra bits are a second value, the multiplexing logic of PUs 0 through (N/4)−1 selects word J+(N/4) output by the memory to output to the first register of PU J; when the address first and second extra bits are a third value, the multiplexing logic of PUs 0 through (N/4)−1 selects word J+(N/2) output by the memory to output to the first register of PU J; and when the address first and second extra bits are a fourth value, the multiplexing logic of PUs 0 through (N/4)−1 selects word J+(3N/4) output by the memory to output to the first register of PU J. 11. A method for operating an apparatus having a memory that receives an address and that holds D rows of N words indexed as 0 through N−1, wherein N is at least 512, wherein the address has log2D bits and an extra bit, an array of N processing units (PU) indexed as 0 through N−1, each PU of index J having: first and second registers, an accumulator, an arithmetic unit having first, second and third inputs and that performs an operation thereon to generate a result to store in the accumulator, the first input receives an output of the accumulator, the second input receives a word output by the first register, the third input receives a word output by the second register, and multiplexing logic that receives word J output by the memory, and in the case of PUs 0 through (N/2)−1 also receives word J+(N/2) output by the memory, and outputs a selected word to the first register, the method comprising: in a first mode: selecting, by the multiplexing logic of PUs 0 through N−1, word J output by the memory to output to the first register of PU J; and in a second mode: when the address extra bit is a first value: selecting, by the multiplexing logic of PUs 0 through (N/2)−1, word J output by the memory to output to the first register of PU J; and when the address extra bit is a second value: selecting, by the multiplexing logic of PUs 0 through (N/2)−1, word J+(N/2) output by the memory to output to the first register of PU J. 12. The method of claim 11, further comprising: in the second mode: effectively configuring the memory to hold 2*W rows of N/2 words for provision to PUs 0 through (N/2)−1. 13. The method of claim 1, further comprising for J equal to 0 through (N/2)−1, second multiplexing logic that receives a first result that is a function of the accumulator of PU J and that receives a second result that is a function of the accumulator of PU J+(N/2) and outputs a selected result for the memory to write to word J+(N/2) of a row of the memory, the method further comprising: in the first mode: writing, by the memory, words 0 through (N/2)−1 of a row with N/2 results that are a function of the accumulators of respective PUs 0 through (N/2)−1; and for J equal to 0 through (N/2)−1: selecting, by the second multiplexing logic, the second result to output for the memory to write to word J+(N/2) of the row; and in the second mode: when the address extra bit is the first value: writing, by the memory, words 0 through (N/2)−1 of a row with N/2 results that are a function of the accumulators of respective PUs 0 through (N/2)−1; and not writing, by the memory, words N/2 through N−1 of the row; and when the address extra bit is the second value: not writing, by the memory, words 0 through (N/2)−1 of a row; and for J equal to 0 through (N/2)−1: selecting, by the second multiplexing logic, the first result to output for the memory to write to word J+(N/2) of the row. 14. The method of claim 13, wherein the function of the accumulator is a neural network activation function. 15. The method of claim 11, further comprising: in the second mode: when the address extra bit is the first value: outputting, by the memory, words 0 through (N/2)−1 of a row selected by the log2D address bits, but not outputting words N/2 through N−1; and when the address extra bit is the second value: outputting, by the memory, words N/2 through N−1 of a row selected by the log2D address bits, but not outputting words 0 through (N/2)−1. 16. The method of claim 11, wherein the multiplexing logic further receives the word output by the first register of PU J−1 and outputs a selected word to the first register, wherein PU J−1 is PU N−1 for PU 0, the method further comprising: in a third mode: alternatively selecting, by the multiplexing logic, the word output by the first register of PU J−1 to output to the first register. 17. The method of claim 11, wherein the multiplexing logic further receives the word output by the first register of PU J−1 and outputs a selected word to the first register, wherein PU J−1 is PU (N/2)−1 for PU 0, the method further comprising: in a third mode: selecting, by the multiplexing logic, the word output by the first register of PU J−1 to output to the first register; and powering off PUs N/2 through N−1. 18. The method of claim 11, wherein the apparatus further comprises a second memory that holds W rows of N words indexed as 0 through N−1 and that receives a second address, wherein the second address has log2W bits and a second extra bit, and each PU of index J further having second multiplexing logic that receives word J output by the second memory, and in the case of PUs 0 through (N/2)−1 also receives word J+(N/2) output by the second memory, and outputs a selected word to the second register. 19. The method of claim 18, further comprising: in the first mode: selecting, by the second multiplexing logic of PUs 0 through N−1, word J output by the second memory to output to the second register of PU J; and in the second mode: when the address second extra bit is a first value: selecting, by the second multiplexing logic of PUs 0 through (N/2)−1, word J output by the second memory to output to the second register of PU J; and when the address second extra bit is a second value: selecting, by the second multiplexing logic of PUs 0 through (N/2)−1, word J+(N/2) output by the second memory to output to the second register of PU J. 20. The method of claim 11, wherein the address further includes a second extra bit, wherein in the case of PUs 0 through (N/4)−1, the multiplexing logic further receives word J+(N/4) and word J+(3N/4) output by the memory, and outputs a selected word to the first register, the method further comprising: in a third mode: when the address first and second extra bits are a first value: selecting, by the multiplexing logic of PUs 0 through (N/4)−1, word J output by the memory to output to the first register of PU J; when the address first and second extra bits are a second value: selecting, by the multiplexing logic of PUs 0 through (N/4)−1, word J+(N/4) output by the memory to output to the first register of PU J; when the address first and second extra bits are a third value: selecting, by the multiplexing logic of PUs 0 through (N/4)−1, word J+(N/2) output by the memory to output to the first register of PU J; and when the address first and second extra bits are a fourth value: selecting, by the multiplexing logic of PUs 0 through (N/4)−1, word J+(3N/4) output by the memory to output to the first register of PU J. 21. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising: computer usable program code embodied in said medium, for specifying a apparatus, the computer usable program code comprising: first program code for specifying a memory that receives an address and that holds D rows of N words indexed as 0 through N−1, wherein N is at least 512, wherein the address has log2D bits and an extra bit; and second program code for specifying an array of N processing units (PU) indexed as 0 through N−1, each PU of index J having: first and second registers; an accumulator; an arithmetic unit having first, second and third inputs and that performs an operation thereon to generate a result to store in the accumulator, the first input receives an output of the accumulator, the second input receives a word output by the first register, the third input receives a word output by the second register; and multiplexing logic that receives word J output by the memory, and in the case of PUs 0 through (N/2)−1 also receives word J+(N/2) output by the memory, and outputs a selected word to the first register; wherein in a first mode, the multiplexing logic of PUs 0 through N−1 selects word J output by the memory to output to the first register of PU J; and wherein in a second mode: when the address extra bit is a first value, the multiplexing logic of PUs 0 through (N/2)−1 selects word J output by the memory to output to the first register of PU J; and when the address extra bit is a second value, the multiplexing logic of PUs 0 through (N/2)−1 selects word J+(N/2) output by the memory to output to the first register of PU J.