A synaptic circuit performing spike-timing dependent plasticity STDP interposed between a pre-synaptic neuron and a post-synapse neuron includes a memristor having a variable resistance value configured to receive a first signal from the pre-synaptic neuron. The circuit has an intermediate unit connected in series with the memristor for receiving a second signal from the pre-synaptic neuron and provides an output signal to the post-synaptic neuron. The intermediate unit receives a retroaction signal generated from the post-synaptic neuron and the memristor modifies the resistance value based on a delay between two at least partially overlapped input pulses, a spike event of the first signal and a pulse of the retroaction signal, in order to induct a potentiated state STP or a depressed state STD at the memristor. An electronic neuromorphic system having synaptic circuits and a method of performing spike timing dependent plasticity STDP by a synaptic circuit are also provided.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A synaptic circuit (3) performing spike-timing dependent plasticity (STDP) interposed between a pre-synaptic neuron (2) and a post-synapse neuron (4) and comprising: a memristor (10) having a variable resistance value (R) and being configured to receive a first signal (VTE) from the pre-synaptic neuron (2); an intermediate unit (11) connected in series with the memristor (10) and being configured for receiving a second signal (VCG) from the pre-synaptic neuron (2) and being configured for providing an output signal (IBE) to the post-synaptic neuron (4), wherein the intermediate unit (11) is further configured to receive a retroaction signal (VFG) generated from the post-synaptic neuron (4), and the memristor (10) is configured to modify the resistance value (R) based on a delay (Δt) between two at least partially overlapped input pulses, a spike event (FE1) of the first signal (VTE) and a pulse (VFGMAX) of the retroaction signal (VFG), in order to induct a potentiated state (STP) or a depressed state (STD) at the memristor (10). 2. The synaptic circuit of claim 1, wherein the intermediate unit (11) comprises a first transistor (12) and a second transistor (13) that are connected in parallel. 3. The synaptic circuit of claim 2, wherein the first transistor (12) and the second transistor (13) are connected between a first inner node (27) and a second inner node (28), the first transistor (12) having a control terminal coupled to the pre-synaptic neuron (2) for receiving the second signal (VCG) and the second transistor (13) having a control terminal connected to the post-synaptic neuron (4) for receiving the retroaction signal (VFG). 4. The synaptic circuit of claim 2, wherein the first transistor (12) and the second transistor (13) are n-MOS transistors. 5. The synaptic circuit of claim 1, wherein the memristor (10) is a bipolar memristor. 6. The synaptic circuit of claim 1, wherein the resistance value (R) is configured to decrease by inducting the potentiated state (LTP) at the memristor (10) when the pulse (VFGMAX) of the retroaction signal (VFG) is successive to the spike event (FE1) of the first signal (VTE). 7. The synaptic circuit of claim 1, wherein the resistance value (R) is configured to increase by inducting the depressed state (LTD) at the memristor (10) when the pulse (VFGMAX) of the retroaction signal (VFG) precedes the spike event (FE1) of the first signal (VTE). 8. The synaptic circuit of claim 1, wherein the pre-synaptic neuron (2) and the post-synaptic neuron (4) are four-terminal components and are configured to behave both as an integrate and fire module (5). 9. The synaptic circuit of claim 8, wherein the integration and fire module (5) of the post-synaptic neuron (4) comprises an integration unit (6) having an operational amplifier connected in series by an internal terminal (25) with a fire unit (7) comprising a comparator stage, the integration unit (6) being configured to integrate an output signal (IBE) issued from the intermediate unit (11) and to generate an internal voltage (VINT) at the internal terminal (25), the fire unit (7) being configured to generate: a further first signal (VTE) by a first output terminal (30), further second signal (VCG) by a second output terminal (31) and the retroaction signal (VFG) by the retroaction terminal (24). 10. The synaptic circuit of claim 9, wherein the integration and fire module (5) comprises an emptying unit that is configured to provide a reset state by imposing a constant predetermined voltage at the internal terminal (25) when the internal voltage (VINT) reaches a threshold value (VTH). 11. The synaptic circuit of claim 1, wherein the two at least partially overlapped input pulses, the pulse of the first signal (VTE) and the pulse (VFGMAX) of the retroaction signal (VFG), have opposite exponential shapes and the first signal (VTE) further having spike events (FE1) at the end of each pulse. 12. The synaptic circuit of claim 1, wherein the two at least partially overlapped input pulses have square shapes, the pulses of the first signal (VTE) and the pulse (VFGMAX) of the retroaction signal (VFG), the first signal (VTE) further having a spike event (FE1) at the end of each pulse. 13. An electronic neuromorphic system comprising a multi-layer structure wherein an intermediate layer (LX) comprises a first set (N) of pre-synaptic neurons (2) and a subsequent layer (LX+1) comprises a second set (M) of post-synaptic neurons (4), synaptic circuits (3) performing spike-timing dependent plasticity (STDP) being interposed between the pre-synaptic neurons (2) of the first set (N) and the post-synaptic neurons (4) of the second set (M), each synaptic circuit (3) comprising: a memristor (10) having a variable resistance value (R) and being configured to receive a first signal (VTE) from the pre-synaptic neuron (2); an intermediate unit (11) connected in series with the memristor (10) and being configured for receiving a second signal (VCG) from the pre-synaptic neuron (2) and being configured for providing an output signal (IBE) to the post-synaptic neuron (4), wherein the intermediate unit (11) is further configured to receive a retroaction signal (VFG) generated from the post-synaptic neuron (4), and the memristor (10) is configured to modify the resistance value (R) based on a delay (Δt) between two at least partially overlapped input pulses, a spike event (FE1) of the first signal (VTE) and a pulse (VFGMAX) of the retroaction signal (VFG), in order to induct a potentiated state (STP) or a depressed state (STD) at the memristor (10). 14. The electronic neuromorphic system of claim 13, wherein the synaptic circuits (3) are arranged in an array (N×M) comprising N-lines (L1-LN) and M-columns (C1-CM), and wherein each line comprises a pre-synaptic neuron (2) of the first set (N) of the intermediate layer (LX) and each column comprises a post-synaptic neuron (4) of the second set (M) of the subsequent layer (LX+1). 15. The electronic neuromorphic system of claim 14, wherein each pre-synaptic neuron (2) of the intermediate layer (LX) comprises a first output terminal (30) configured to provide the first signal (VTE) to each of the M synaptic circuits (3) arranged at the same line, and configured to provide the second signal (VCG) by a second output terminal (31) of the M synaptic circuits (3) of such line. 16. The electronic neuromorphic system of claim 13, wherein each post-synaptic neuron (4) of the subsequent layer (LX+1) comprises an input terminal (32) configured to receive the output signal (IBE) from each intermediate unit (11) of the N synaptic circuits (3) arranged at the same column, and configured to provide the retroaction signal (VFG) to each retroaction terminal (24) of the N synaptic circuits (3) of such column. 17. A method of performing spike timing dependent plasticity (STDP) by a synaptic circuit (3) comprising a memristor (10) having a variable resistance value (R), the memristor (10) being interposed between a pre-synaptic neuron (2) and a post-synaptic neuron (4), the method comprising: receiving a first signal (VTE) from the pre-synaptic neuron (2); receiving a retroaction signal (VFG) from the post-synaptic neuron (4), and modifying the resistance value (R) based on a delay (Δt) between two at least partially overlapped input pulses, a spike event (FE1) of the first signal (VTE) and a pulse (VFGMAX) of the retroaction signal (VFG), by inducting a potentiated state (STP) or a depressed state (STD) at the memristor (10). 18. The method of claim 17, further comprising: connecting an intermediate unit (11) in series with the memristor (10); receiving at the memristor (10) the first signal (VTE); receiving at the intermediate unit (11) a second signal (VCG) from the pre-synaptic neuron (2); providing an output signal (IBE) to the post-synaptic neuron (4) by the intermediate unit (11); receiving the retroaction signal (VFG) at the intermediate unit (11). 19. The method of claim 18, further comprising: providing the intermediate unit (11) by comprising a first transistor (12) and a second transistor (13), and connecting the second transistor (13) in parallel with the first transistor (12) interposed between a first inner node (27) and a second inner node (28), connecting the memristor (10) to the first inner node (27) and connecting the post-synaptic neuron (4) to the second node (28) by an output terminal (23). 20. The method of claim 17, further comprising: providing the synaptic circuit (3) comprising a bipolar memristor (10). 21. The method of claim 17, further comprising: decreasing the resistance value (R) when the pulse (VFGMAX) of the retroaction signal (VFG) is successive to the spike event (FE1) of the first signal (VTE) issued from the pre-synaptic neuron (2) by providing the potentiated state (LTP) at the memristor (10). 22. The method of claim 17, further comprising: increasing the resistance value (R) when the pulse (VFGMAX) of the retroaction signal (VFG) precedes the spike event (FE1) of the first signal (VTE) issued from the pre-synaptic neuron (2) by providing the depressed state (LTD) at the memristor (10).