A neuristor-based reservoir computing device includes support circuitry formed in a complimentary metal oxide semiconductor (CMOS) layer, input nodes connected to the support circuitry and output nodes connected to the support circuitry. Thin film neuristor nodes are disposed over the CMOS layer with a first portion of the neuristor nodes connected to the input nodes and a second portion of the neuristor nodes connected to the output nodes. Interconnections between the neuristor nodes form a reservoir accepting input signals from the input nodes and outputting signals on the output nodes. A method for forming a neuristor-based reservoir computing device is also provided.
Please help me write a proper abstract based on the patent claims. CLAIM: 1-20. (canceled) 21. A neuristor node for a neuristor-based reservoir computing device, the neuristor node including: an input for receiving an input signal; an output for outputting an output signal; two nominally identical Mott memristors; two capacitors, each associated with one of the Mott memristors and in parallel therewith to form two channels; two DC bias sources with opposite polarity voltages, each providing one of the channels with a voltage, with one channel receiving a positive polarity and the other channel receiving a negative polarity; a load resistor for coupling the two channels to each other; an input resistance connected to the input, the first channel and the load resistor; and an output impedance connected to the load resistor, to the second channel, and to the output. 22. The neuristor node as defined in claim 21, wherein the output impedance comprises an output resistor and an output capacitor in parallel. 23. The neuristor node as defined in claim 21, wherein when the input signal is below a threshold input voltage, then the output signal of the neuristor is relatively small and when the input signal is above the threshold input voltage, then the output signal of the neuristor is relatively large. 24. The neuristor node as defined in claim 21, which exhibits both signal gain and thresholding. 25. The neuristor node as defined in claim 21, wherein charging and discharging of the two capacitors control a time delay from receipt of the input signal to the neuristor node in its initial state to the outputting of the output signal to a return of the neuristor node to the initial state, which mimics a refractory period of biological systems. 26. The neuristor node as defined in claim 21, wherein interaction between the two Mott memristors is mediated by the load resistor. 27. A neuristor-based reservoir computing device, including: a plurality of input nodes; a plurality of output nodes; and a neuristor-based reservoir comprising a collection of recurrently connected neuristor nodes, in which a first portion of each neuristor node is connected to an input node, in which a second portion of each neuristor node is connected to an output node, and in which each neuristor node is connected to other neuristor nodes, wherein each neuristor node includes two Mott memristors. 28. The neuristor-based reservoir computing device as defined in claim 27, further including support circuitry formed in a complementary metal oxide semiconductor (CMOS) layer, to which the plurality of input nodes and plurality of output nodes are connected, with the neuristor nodes disposed over the CMOS layer. 29. The neuristor-based reservoir computing device as defined in claim 27, the neuristor node including: an input for receiving an input signal; an output for outputting an output signal; the two Mott memristors, which are nominally identical; two capacitors, each associated with one of the Mott memristors and in parallel therewith to form two channels; two DC bias sources with opposite polarity voltages, each providing one of the channels with a voltage, with one channel receiving a positive polarity and the other channel receiving a negative polarity; a load resistor for coupling the two channels to each other; an input resistance connected to the input, the first channel and the load resistor; and an output impedance connected to the load resistor, to the second channel, and to the output. 30. The neuristor-based reservoir computing device as defined in claim 29, wherein the output impedance comprises an output resistor and an output capacitor in parallel. 31. The neuristor-based reservoir computing device as defined in claim 29, wherein when the input signal is below a threshold input voltage, then the output signal of the neuristor is relatively small and when the input signal is above the threshold input voltage, then the output signal of the neuristor is relatively large. 32. The neuristor-based reservoir computing device as defined in claim 29, which exhibits both signal gain and thresholding. 33. The neuristor-based reservoir computing device as defined in claim 29, wherein charging and discharging of the two capacitors control a time delay from receipt of the input signal to the neuristor node in its initial state to the outputting of the output signal to a return of the neuristor node to the initial state, which mimics a refractory period of biological systems. 34. The neuristor-based reservoir computing device as defined in claim 29, wherein interaction between the two Mott memristors is mediated by the load resistor. 35. The neuristor-based reservoir computing device as defined in claim 27, in which the interconnections between the neuristor nodes are parametrically random. 36. The neuristor-based reservoir computing device as defined in claim 27, in which the interconnections between the neuristor nodes have parametrically random electrical resistances. 37. A neuristor reservoir, including: a plurality of input/output nodes; and a plurality of neuristor nodes that are highly interconnected to the input/output nodes and to other neuristor nodes and form a number of feedback loops that can resonate in response to specific input signals or time sequences; wherein each neuristor node includes two memristors. 38. The neuristor reservoir as defined in claim 37, wherein interconnections between input nodes, output nodes, and neuristor nodes are parametrically random. 39. The neuristor reservoir as defined in claim 37, wherein the memristors include negative differential resistance switching. 40. The neuristor reservoir as defined in claim 37, wherein the memristors are Mott memristors.