An array of resistive processing units (RPUs) comprises a plurality of rows of RPUs and a plurality of columns of RPUs wherein each RPU comprises an AND gate configured to perform an AND operation of a first stochastic bit stream received from a first stochastic translator translating a number encoded from a neuron in a row and a second stochastic bit stream received from a second stochastic translator translating a number encoded from a neuron in a column. A first storage is configured to store a weight value of the RPU, and a second storage is configured to store an amount of change to the weight value of the RPU. When the first stochastic bit stream and the second stochastic bit stream coincide, the amount of change to the weight value of the RPU is added to the weight value of the RPU.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. An array of resistive processing units comprising: a plurality of rows of resistive processing units; and a plurality of columns of resistive processing units, wherein each resistive processing unit comprises: an AND gate configured to perform an AND operation of a first stochastic bit stream received from a first stochastic translator translating a number encoded from a neuron in a row and a second stochastic bit stream received from a second stochastic translator translating a number encoded from a neuron in a column; a first storage configured to store a weight value of the resistive processing unit; and a second storage configured to store an amount of change to the weight value of the resistive processing unit, wherein when the first stochastic bit stream and the second stochastic bit stream coincide, the amount of change to the weight value of the resistive processing unit is added to the weight value of the resistive processing unit. 2. The array of resistive processing units of claim 1, wherein each of the first stochastic translator and the second stochastic translator comprises a bit length of a stochastic bit stream. 3. The array of resistive processing units of claim 2, wherein the bit length of each of the first stochastic bit stream and the second stochastic bit stream is 10. 4. The array of resistive processing units of claim 1, wherein each of the first stochastic bit stream and the second stochastic bit stream comprises a random variable characterized by a Bernoulli process. 5. The array of resistive processing units of claim 1, wherein the AND gate comprises: a first input terminal electrically coupled to the first stochastic bit stream; a second input terminal electrically coupled to the second stochastic bit stream; and an output terminal configured to provide an output of the AND operation of the first stochastic bit stream and the second stochastic bit stream. 6. The array of resistive processing units of claim 5, wherein the output terminal of the AND gate is true when the first stochastic bit stream and the second stochastic bit stream coincide. 7. The array of resistive processing units of claim 1, wherein the array of resistive processing units further comprises a neuron state controller configured to control a forward propagation, a backward propagation, and a weight update of a neural network training. 8. A neural network comprising: an array of resistive processing units having: a plurality of rows of resistive processing units; and a plurality of columns of resistive processing units, wherein each resistive processing unit comprises: an AND gate configured to perform an AND operation of a first stochastic bit stream received from a first stochastic translator translating a number encoded from a neuron in a row and a second stochastic bit stream received from a second stochastic translator translating a number encoded from a neuron in a column; a first storage configured to store a weight value of the resistive processing unit; and a second storage configured to store an amount of change to the weight value of the resistive processing unit, wherein when the first stochastic bit stream and the second stochastic bit stream coincide, the amount of change to the weight value of the resistive processing unit is added to the weight value of the resistive processing unit. 9. The neural network of claim 8, wherein each of the first stochastic translator and the second stochastic translator comprises a bit length of a stochastic bit stream. 10. The neural network of claim 8, wherein each of the first stochastic bit stream and the second stochastic bit stream comprises a random variable characterized by a Bernoulli process. 11. The neural network of claim 8, wherein the AND gate comprises: a first input terminal electrically coupled to the first stochastic bit stream; a second input terminal electrically coupled to the second stochastic bit stream; and an output terminal configured to provide an output of the AND operation of the first stochastic bit stream and the second stochastic bit stream. 12. The neural network of claim 11, wherein the output terminal of the AND gate is true, when the first stochastic bit stream and the second stochastic bit stream coincide. 13. The neural network of claim 8, wherein the array of resistive processing units further comprises a neuron state controller configured to control a forward propagation, a backward propagation, and a weight update of a neural network training. 14. A method of two step neural network training comprising: providing a first array of resistive processing units; performing a first step neural network training using the first array of resistive processing units; providing a high precision neural network; and performing a second step neural network training using the high precision neural network. 15. The method of claim 14, wherein performing the first step neural network training comprises extracting each of weight values of the first array of the resistive processing units. 16. The method of claim 15, wherein performing the second step neural network training comprises initializing the high precision neural network with corresponding weight values extracted from the first array of the resistive processing units. 17. The method of claim 14, wherein the first array of resistive processing units comprises an array of noisy resistive processing units, and the high precision neural network comprises a floating point conventional neural network. 18. The method of claim 14, wherein each of the first array of resistive processing units and the first array of resistive processing units comprises: a plurality of rows of resistive processing units; and a plurality of columns of resistive processing units, wherein each resistive processing unit comprises: an AND gate configured to perform an AND operation of a first stochastic bit stream received from a first stochastic translator translating a number encoded from a neuron in a row and a second stochastic bit stream received from a second stochastic translator translating a number encoded from a neuron in a column; a first storage configured to store a weight value of the resistive processing unit; and a second storage configured to store an amount of change to the weight value of the resistive processing unit, wherein when the first stochastic bit stream and the second stochastic bit stream coincide, the amount of change to the weight value of the resistive processing unit is added to the weight value of the resistive processing unit. 19. The method of claim 18, wherein each of the first stochastic translator and the second stochastic translator comprises a bit length of a stochastic bit stream, and each of the first stochastic bit stream and the second stochastic bit stream comprises a random variable characterized by a Bernoulli process. 20. The method of claim 18, wherein the AND gate comprises: a first input terminal electrically coupled to the first stochastic bit stream; a second input terminal electrically coupled to the second stochastic bit stream; and an output terminal configured to provide an output of the AND operation of the first stochastic bit stream and the second stochastic bit stream, wherein the output terminal of the AND gate is true, when the first stochastic bit stream and the second stochastic bit stream coincide.