Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A quantum processor comprising: a first qubit having a first characteristic associated with a parameter; a second qubit having a second characteristic associated with the parameter, wherein the first characteristic of the first qubit is different from the second characteristic of the second qubit; a coupling system selectively configurable to provide communicative coupling between the first qubit and the second qubit; and at least one device that is selectively operable to tune the parameter of the first qubit such that the first characteristic of the first qubit matches the second characteristic of the second qubit. 2. The quantum processor of claim 1 wherein the parameter is capacitance. 3. The quantum processor of claim 2 wherein the first qubit is a superconducting qubit and the second qubit is a superconducting qubit, the first and the second qubits each comprising: a qubit loop formed by a first superconducting current path; a first compound Josephson junction structure formed by a first pair of parallel superconducting current paths, wherein the first compound Josephson junction structure interrupts the qubit loop, and wherein each superconducting current path in the first pair of parallel superconducting current paths is interrupted by at least one Josephson junction; and a series LC-circuit coupled in parallel with the first compound Josephson junction structure through a superconducting current path, wherein the series LC-circuit realizes a tunable capacitance. 4. The quantum processor of claim 3 wherein the series LC-circuit includes at least one capacitance and a second Josephson junction structure coupled in series with the at least one capacitance, the second compound Josephson junction structure formed by a second pair of parallel superconducting current paths, wherein each superconducting current path in the second pair of parallel superconducting current paths is interrupted by at least one Josephson junction. 5. The quantum processor of claim 1 wherein the parameter is inductance. 6. The quantum processor of claim 5 wherein the first qubit is a superconducting qubit and the second qubit is a superconducting qubit, the first and the second qubits each comprising a qubit loop formed by a superconducting current path, the qubit loop interrupted by at least one Josephson junction structure, the quantum processor further comprising: at least one L-tuner compound Josephson junction that interrupts the qubit loop of the first qubit; at least one L-tuner compound Josephson junction that interrupts the qubit loop of the second qubit; and a programming interface that is positioned to inductively couple control signals to each of the at least one L-tuner compound Josephson junctions, the programming interface selectively operable to tune the inductance of at least one of the first and the second qubits. 7. The quantum processor of claim 1 wherein the at least one device that is selectively operable to tune the parameter of the first qubit is selectively operable to compensate, at least in part, for Josephson junction asymmetry in the first and the second qubits. 8. The quantum processor of claim 1 wherein the at least one device that is selectively operable to tune the parameter of the first qubit is selectively operable to generate a Josephson junction asymmetry in the first and the second qubits. 9. The quantum process of claim 1 wherein the at least one device that is selectively operable to tune the parameter of the first qubit is selectively operable to tune the parameter to synchronize the behavior of the first and the second qubits before running a quantum computation. 10. A method of operation of a quantum processor that comprises a plurality of qubits and, for each of the qubits, a respective plurality of programming interfaces that are communicatively coupleable to the respective qubits, the method comprising: tuning at least one parameter of at least one of the qubits; matching at least one parameter between a first one of the qubits and at least a second one of the qubits; and executing a quantum computation via the quantum processor after the tuning and the matching. 11. The method of claim 10 wherein tuning at least one parameter of at least one of the qubits comprises selectively operating the respective plurality of programming interfaces for the at least one of the qubits to tune a capacitance. 12. The method of claim 10 wherein tuning at least one parameter of at least one of the qubits comprises selectively operating the respective plurality of programming interfaces for the at least one of the qubits to tune an inductance. 13. The method of claim 10 wherein tuning at least one parameter of at least one of the qubits comprises selectively operating the respective plurality of programming interfaces for the at least one of the qubits to compensate, at least in part, for Josephson junction asymmetry. 14. The method of claim 10 wherein tuning at least one parameter of at least one of the qubits comprises selectively operating the respective plurality of programming interfaces for the at least one of the qubits to generate, at least in part, a Josephson junction asymmetry. 15. The method of claim 10 wherein matching at least one parameter between a first one of the qubits and at least a second one of the qubits comprises selectively operating the respective plurality of programming interfaces for the first one and the second one of the qubits to parameter to synchronize a behavior of the first one and the second one of the qubits before executing the quantum computation. 16. A quantum processor comprising: a plurality of superconducting qubits, each superconducting qubit respectively comprising: a qubit loop formed by: a first current path that is superconductive below a critical temperature; and a primary compound Josephson junction structure that interrupts the qubit loop, the primary compound Josephson junction structure comprising two parallel current paths that are each formed of a material that is superconducting below a critical temperature, wherein each of the two parallel current paths of the primary compound Josephson junction structure includes a respective Josephson junction structure, the Josephson junction structure in each of the two parallel current paths of the primary compound Josephson junction structure includes a first and a second secondary compound Josephson junction structure nested within the primary compound Josephson junction structure, each secondary compound Josephson junction structure comprising two parallel current paths that are superconductive below a critical temperature, and at least two Josephson junctions, each of which interrupts a respective one of the two parallel current paths, the quantum processor further comprising: a first programming interface positioned to couple a control signal to the qubit loop; a second programming interface positioned to couple a control signal to the primary compound Josephson junction structure; a third programming interface positioned to couple a control signal to the first secondary compound Josephson junction structure and thereby tune a characteristic of the first secondary compound Josephson junction structure to match a characteristic of the second secondary compound Josephson junction structure; and a fourth programming interface positioned to couple a control signal to the second secondary compound Josephson junction structure and thereby tune a characteristic of the second secondary compound Josephson junction structure to match a characteristic of the first secondary compound Josephson junction structure, wherein the second, the third and the fourth programming interfaces for each superconducting qubit are selectively operable in combination to at least one of adjust a Josephson junction asymmetry or synchronize a behavior of the plurality of superconducting qubits. 17. The quantum processor of claim 16 wherein the second, the third and the fourth programming interfaces for at least one of the superconducting qubits actively compensate, at least in part, for Josephson junction asymmetry. 18. The quantum processor of claim 16 wherein the second, the third and the fourth programming interfaces for each superconducting qubit for at least one of the superconducting qubits generate a determined degree of Josephson junction asymmetry to adjust Josephson junction asymmetry. 19. A superconducting processor, the superconducting processor comprising: a qubit loop formed by a first current path that is superconductive below a critical temperature; a first programming interface that couples a control signal to the qubit loop; a primary compound Josephson junction structure that interrupts the qubit loop, the primary compound Josephson junction structure comprising two parallel current paths that are each formed of a material that is superconducting below a critical temperature, wherein each of the two parallel current paths of the primary compound Josephson junction structure includes a respective Josephson junction structure, the Josephson junction structure in each of the two parallel current paths of the primary compound Josephson junction structure includes a first and a second secondary compound Josephson junction structure nested within the primary compound Josephson junction structure, each secondary compound Josephson junction structure comprising two parallel current paths that are superconductive below a critical temperature, and at least two Josephson junctions, each of which interrupts a respective one of the two parallel current paths; a second programming interface that couples a control signal to the primary compound Josephson junction structure; a third programming interface that couples a control signal to the first secondary compound Josephson junction structure and thereby tunes a characteristic of the first secondary compound Josephson junction structure to match a characteristic of the second secondary compound Josephson junction structure; and a fourth programming interface that couples a control signal to the second secondary compound Josephson junction structure and thereby tunes a characteristic of the second secondary compound Josephson junction structure to match a characteristic of the first secondary compound Josephson junction structure. 20. The quantum processor of claim 19 wherein the second, the third and the fourth programming interfaces are selectively operable to: i) actively compensate, at least in part, for Josephson junction asymmetry and ii) generate a determined degree of Josephson junction asymmetry to adjust Josephson junction asymmetry.