The present invention generally relates to systems and methods for visual process analysis. The disclosed techniques can include: obtaining a theoretical and an empirical process model, generating a theoretical process layout corresponding to the theoretical process model, where the theoretical process layout is generated using a layout algorithm, generating an empirical process layout corresponding to the empirical process model, where the empirical process layout is generated using the layout algorithm, superposing the empirical process layout onto the theoretical process layout, such that a superposition layout is generated, annotating the superposition layout based on ugliness indicators, such that an annotated superposition layout is generated, and causing the annotated superposition layout to be displayed.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A computer-implemented method for detecting at least one difference between a theoretical process and an empirical process, the method comprising: obtaining a theoretical process model; obtaining, using an electronic processor, an empirical process model corresponding to the theoretical process model; generating, using an electronic processor, a theoretical process layout corresponding to the theoretical process model, wherein the theoretical process layout is generated using a layout algorithm; generating, using an electronic processor, an empirical process layout corresponding to the empirical process model, wherein the empirical process layout is generated using the layout algorithm; superposing, using an electronic processor, the empirical process layout onto the theoretical process layout, whereby a superposition layout is generated; annotating, using an electronic processor, the superposition layout based on ugliness indicators, whereby an annotated superposition layout is generated; and causing, using an electronic processor, the annotated superposition layout to be displayed. 2. The method of claim 1, wherein the theoretical process layout and the empirical process layout comprise a longest path layout format. 3. The method of claim 1, wherein the superposing comprises: maintaining in a same position at least one node representing a same activity in both the empirical process layout and the theoretical process layout; and placing in a different position at least one node from the empirical process layout. 4. The method of claim 1, further comprising conforming an empirical process to the theoretical process model. 5. The method of claim 1, further comprising enhancing the theoretical process model. 6. The method of claim 1, wherein the ugliness indicators comprise an indication that an edge in the superposition layout appears in the empirical process layout but not in the theoretical process layout. 7. The method of claim 1, wherein the ugliness indicators comprise an indication that an edge in the superposition layout appears in the theoretical process layout but not in the empirical process layout. 8. The method of claim 1, wherein the ugliness indicators comprise an indication that a node in the superposition layout appears in the empirical process layout but not in the theoretical process layout. 9. The method of claim 1, wherein the ugliness indicators comprise an indication that a node in the superposition layout appears in the theoretical process layout but not in the empirical process layout. 10. The method of claim 1, wherein the annotating comprises assigning different colors to a plurality of ugliness indicators. 11. A system for detecting at least one difference between a theoretical process and an empirical process, the system comprising: an electronic memory; and at least one electronic processor operatively coupled to the electronic memory and configured to: obtain a theoretical process model; obtain, using an electronic processor, an empirical process model corresponding to the theoretical process model; generate a theoretical process layout corresponding to the theoretical process model, wherein the theoretical process layout is generated using a layout algorithm; generate an empirical process layout corresponding to the empirical process model, wherein the empirical process layout is generated using the layout algorithm; superpose the empirical process layout onto the theoretical process layout, whereby a superposition layout is generated; annotate the superposition layout based on ugliness indicators, whereby an annotated superposition layout is generated; and cause the annotated superposition layout to be displayed. 12. The system of claim 10, wherein the theoretical process layout and the empirical process layout comprise a longest path layout format. 13. The system of claim 10, wherein the at least one processor is further configured to: maintain in a same position at least one node representing a same activity in both the empirical process layout and the theoretical process layout; and place in a different position at least one node from the empirical process layout. 14. The system of claim 10, wherein the at least one processor is further configured to provide a suggestion to conform an empirical process to the theoretical process model. 15. The system of claim 10, wherein the at least one processor is further configured to enhance the theoretical process model. 16. The system of claim 10, wherein the ugliness indicators comprise an indication that an edge in the superposition layout appears in the empirical process layout but not in the theoretical process layout. 17. The system of claim 10, wherein the ugliness indicators comprise an indication that an edge in the superposition layout appears in the theoretical process layout but not in the empirical process layout. 18. The system of claim 10, wherein the ugliness indicators comprise an indication that a node in the superposition layout appears in the empirical process layout but not in the theoretical process layout. 19. The system of claim 10, wherein the ugliness indicators comprise an indication that a node in the superposition layout appears in the theoretical process layout but not in the empirical process layout. 20. The system of claim 10, wherein the at least one processor is further configured to assign different colors to a plurality of ugliness indicators.