Embodiments of the present invention relate to providing fault-tolerant power minimization in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for fault-tolerant power-driven synthesis is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores connected by a plurality of routers. At least one faulty core of the plurality of neurosynaptic cores is located. A placement blockage is modeled at the location of the at least one faulty core. A placement of the neurosynaptic cores is determined by minimizing the wire length.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A method comprising: modeling power consumption of a neurosynaptic network as wire length, the neurosynaptic network comprising a plurality of neurosynaptic cores connected by a plurality of routers; locating at least one faulty core of the plurality of neurosynaptic cores; modeling a placement blockage at the location of the at least one faulty core; determining a placement of the neurosynaptic cores by minimizing the wire length. 2. The method of claim 1, wherein the minimizing the wire length comprises applying a VLSI placement algorithm. 3. The method of claim 2, wherein the VLSI placement algorithm comprises partitioning-based placement. 4. The method of claim 1, further comprising: locating at least one faulty router of the plurality of routers; and modeling a second placement blockage, the second placement blockage including at least a core of the plurality of cores associated with the faulty router. 5. The method of claim 1, wherein the plurality of neurosynaptic cores is divided among a plurality of chips. 6. A method comprising: modeling power consumption of a neurosynaptic network as wire length, the neurosynaptic network comprising a plurality of neurosynaptic cores connected by a plurality of routers; locating at least one faulty router of the plurality of routers; modeling a placement blockage, the placement blocking including at least a core of the plurality of cores associated with the faulty router; determining a placement of the neurosynaptic cores by minimizing the wire length. 7. The method of claim 6, wherein: the placement of the neurosynaptic cores is substantially along rows and columns of a grid; the placement blockage includes at least a column of the grid. 8. The method of claim 6, wherein: the placement of the neurosynaptic cores is substantially along a grid; the placement blockage includes at least a row of the grid. 9. The method of claim 6, wherein: the placement of the neurosynaptic cores is substantially along a grid; the placement blockage includes at least a row and a column of the grid. 10. The method of claim 6, wherein the minimizing the wire length comprises applying a VLSI placement algorithm. 11. The method of claim 10, wherein the VLSI placement algorithm comprises partitioning-based placement. 12. The method of claim 6, wherein the plurality of neurosynaptic cores is divided among a plurality of chips. 13. The method of claim 6, further comprising: locating at least one faulty core of the plurality of neurosynaptic cores; and modeling a second placement blockage at the location of the at least one faulty core. 14. A computer program product for fault-tolerant power-driven synthesis, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising: modeling power consumption of a neurosynaptic network as wire length, the neurosynaptic network comprising a plurality of neurosynaptic cores connected by a plurality of routers; locating at least one faulty core of the plurality of neurosynaptic cores; modeling a placement blockage at the location of the at least one faulty core; and determining a placement of the neurosynaptic cores by minimizing the wire length. 15. The computer program product of claim 10, wherein the minimizing the wire length comprises applying a VLSI placement algorithm. 16. The computer program product of claim 11, wherein the VLSI placement algorithm comprises partitioning-based placement. 17. The method of claim 1, further comprising: locating at least one faulty router of the plurality of routers; and modeling a second placement blockage, the second placement blockage including at least a core of the plurality of cores associated with the faulty router. 18. The method of claim 1, wherein the plurality of neurosynaptic cores is divided among a plurality of chips. 19. A computer program product for fault-tolerant power-driven synthesis, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising: modeling power consumption of a neurosynaptic network as wire length, the neurosynaptic network comprising a plurality of neurosynaptic cores connected by a plurality of routers; locating at least one faulty router of the plurality of routers; modeling a placement blockage, the placement blocking including at least a core of the plurality of cores associated with the faulty router; and determining a placement of the neurosynaptic cores by minimizing the wire length. 20. The computer program product of claim 13, wherein: the placement of the neurosynaptic cores is substantially along rows and columns of a grid; and the placement blockage includes at least a column of the grid.