Embodiments are directed towards a configurable accelerator framework device that includes a stream switch and a plurality of convolution accelerators. The stream switch has a plurality of input ports and a plurality of output ports. Each of the input ports is configurable at run time to unidirectionally pass data to any one or more of the output ports via a stream link. Each one of the plurality of convolution accelerators is configurable at run time to unidirectionally receive input data via at least two of the plurality of stream switch output ports, and each one of the plurality of convolution accelerators is further configurable at run time to unidirectionally communicate output data via an input port of the stream switch.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A configurable accelerator framework device, comprising: a stream switch having a plurality of input ports and a plurality of output ports, each of the input ports configurable at run time to unidirectionally pass data to any one or more of the output ports via a stream link; and a plurality of convolution accelerators, each one of the plurality of convolution accelerators configurable at run time to unidirectionally receive input data via at least two of the plurality of stream switch output ports and each one of the plurality of convolution accelerators configurable at run time to unidirectionally communicate output data via an input port of the stream switch. 2. A configurable accelerator framework device according to claim 1, wherein each one of the plurality of convolution accelerators includes: a kernel buffer; a feature line buffer; and a multiply-accumulate (MAC) unit module having a plurality of MAC units arranged to multiply data passed from the kernel buffer with data passed from and the feature line buffer, the plurality of MAC units further arranged to accumulate products of the multiplication. 3. A configurable accelerator framework device according to claim 2, wherein the kernel buffer is coupled via a first input bus to a first one of the at least two of the plurality of stream switch output ports, and wherein the feature line buffer is coupled via a second input bus to a second one of the at least two of the plurality of stream switch output ports. 4. A configurable accelerator framework device according to claim 3, further comprising: an adder tree module arranged to receive and sum data received from the MAC unit module. 5. A configurable accelerator framework device according to claim 4, wherein the adder tree module is coupled via a third input bus to a third one of the at least two of the plurality of stream switch output ports, and wherein data passed into adder tree module via the third input bus is intermediate data produced by a second convolution accelerator of the plurality of convolution accelerators. 6. A configurable accelerator framework device according to claim 1, further comprising: a plurality of direct memory access (DMA) engines, each of the DMA engines configurable at run time to autonomously communicate data into the stream switch or out from the stream switch. 7. A configurable accelerator framework device according to claim 6, wherein the configurable accelerator framework device is arranged as a coprocessor in a system on chip (SoC). 8. A configurable accelerator framework device according to claim 9, further comprising: a memory device integrated in the SoC and arranged to store kernel data and feature data, the kernel data and the feature data communicated between the memory and at least one of the plurality of convolution accelerators via selected ones of the plurality of DMA engines. 9. A configurable accelerator framework device according to claim 1, further comprising: control registers, first ones of the control registers arranged to control operations of the stream switch at run time, and second ones of the control registers arranged to control operations of the plurality of convolution accelerators at run time. 10. A configurable accelerator framework device according to claim 1, further comprising: a first plurality of IP's arranged to source streaming data into the stream switch; and a second plurality of IP's arranged to sink streaming data out from the stream switch. 11. A configurable accelerator framework method, comprising: configuring at run time a stream switch having a plurality of input ports, a plurality of output ports, and a plurality of stream links available to couple each of the plurality of input ports to any one or more of the plurality of output ports, the configuring including: selecting a first input port of the stream switch; selecting a first output port of the stream switch; communicatively coupling the first input port of the stream switch to the first output port of the stream switch via a first stream link of the stream switch; communicatively coupling a streaming data source to the first input port of the stream switch; and communicatively coupling a convolution accelerator to the first output port of the stream switch; unidirectionally passing streaming data through the first input port of the stream switch to the convolution accelerator; and performing at least one convolution operation with the convolution accelerator. 12. A configurable accelerator framework method according to claim 11, further comprising: further configuring the stream switch at run time, the further configuring including: selecting second, third, and fourth input ports of the stream switch; selecting second, third, and fourth output ports of the stream switch; communicatively coupling, respectively, the second, third, and fourth input ports of the stream switch to the second, third, and fourth output ports of the stream switch via second, third, and fourth stream links of the stream switch; communicatively coupling a kernel data source to the second input port of the stream switch; and communicatively coupling an intermediate data source to the third input port of the stream switch; and communicatively coupling an output of the convolution accelerator to the fourth input port of the stream switch; unidirectionally passing convolution output data through the fourth input port of the stream switch. 13. A configurable accelerator framework method according to claim 12, wherein the intermediate data source is an output of a second convolution accelerator. 14. A configurable accelerator framework method according to claim 12, wherein the streaming data unidirectionally passed through the first input port of the stream switch is provided by an image sensor. 15. A configurable accelerator framework method according to claim 11, wherein the configurable accelerator framework is configured at run time to perform deep convolutional neural network (DCNN) operations. 16. A system, comprising: a system on chip (SoC), the SoC having a configurable accelerator framework, the configurable accelerator framework being configurable at run time to perform deep convolutional neural network (DCNN) operations, the configurable accelerator framework having a stream switch, wherein the stream switch includes: a plurality of input ports, a plurality of output ports, and a plurality of stream link structures, each of the input ports configurable at run time to unidirectionally pass data to any of the output ports via a selected one of the plurality of stream link structures; and wherein the configurable accelerator framework includes: a plurality of convolution accelerators, each one of the plurality of convolution accelerators configurable at run time to unidirectionally receive input data via at least two of the plurality of stream switch output ports and each one of the plurality of convolution accelerators configurable at run time to unidirectionally communicate output data via an input port of the stream switch. 17. A system according to claim 16, wherein a selected one of the plurality of input ports of the stream switch is configurable at run time to concurrently and unidirectionally pass data through the stream switch to at least two output ports. 18. A system according to claim 16, wherein the system is a mobile device. 19. A system according to claim 18, wherein the system is powered by a battery. 20. A system according to claim 16, wherein the DCNN is arranged to process streaming data and adaptively learn by conflating proximally related features within the data, by making predictions about the data, and by refining the predictions based on generated conclusions and new conflations.