A hardware implementation of a temporal memory system is disclosed. One aspect includes at least one array of memory cells logically organized in rows and columns, wherein each of the memory cells is adapted for storing a scalar value and adapted for changing the stored scalar value. The hardware implementation additionally includes an input system adapted for receiving an input frame as input and for creating a representation for the input, where the input comprises information for addressing the memory cells in the at least one array. The hardware implantation additionally includes at least one addressing unit for identifying a memory cell in the at least one array with a row address and a column address. The at least one addressing unit includes a column addressing unit for receiving the representation or a derivative thereof as input and applying the representation or the derivative as a column address to the array of memory cells, and a row addressing unit for receiving a delayed version of the representation at a specified time in the past as input, and applying this representation as a row address to the array of cells. The hardware implementation further includes a reading unit adapted for reading out scalar values from a selected row of memory cells in the array, based on the row address applied, wherein each scalar values read out by the reading unit corresponds to a likelihood of temporal coincidence between the input representation of the row address and the input representation of the column address, the likelihood being adjustable through the scalar value stored in the memory cell.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A hardware implementation of a temporal memory system, comprising: at least one array of memory cells logically organized in rows and columns, wherein each of the memory cells is adapted for storing a scalar value and adapted for changing the stored scalar value; an input system adapted for receiving an input frame as input and creating a representation for the input, wherein the input comprises information for addressing the memory cells in the at least one array; at least one addressing unit for identifying a memory cell in the at least one array with a row address and a column address, the at least one addressing unit comprising: a column addressing unit for receiving the representation or a derivative thereof as input and applying the representation or the derivative as a column address to the array of memory cells, and a row addressing unit for receiving a delayed version of the representation at a specified time in the past as input, and applying the delayed version of the representation as a row address to the array of memory cells; and a reading unit adapted for reading out scalar values from a selected row of memory cells in the array, based on the row address applied, wherein each scalar values read out by the reading unit corresponds to a likelihood of temporal coincidence between the input representation of the row address and the input representation of the column address, the likelihood being adjustable through the scalar value stored in the memory cell. 2. The hardware implementation according to claim 1, wherein the specified time in the past corresponds to a predetermined number of frames before a current input frame, wherein the hardware implementation furthermore comprises a buffering unit for implementing a first-in-first-out (FIFO) queue with a pre-determined depth for storing a given number of derivative representations of previous input frames. 3. The hardware implementation according to claim 2, wherein the first-in-first-out (FIFO) queue furthermore comprises a shifting unit adapted for enqueuing a row address to the FIFO queue. 4. The hardware implementation according to claim 1, wherein the reading unit comprises a selection unit for selecting the scalar value based on a criterion and corresponding addresses of the scalar value. 5. The hardware implementation according to claim 1, wherein the at least one array is a square array comprising equal numbers of rows and columns. 6. The hardware implementation according to claim 1, wherein the memory cells are adapted for supporting three operations including reading the scalar value, incrementing the scalar value and decrementing the scalar value. 7. The hardware implementation according to claim 6, wherein the addressing unit is adapted for identifying one or more memory cells in the at least one array prior to implementing any of the three operations. 8. The hardware implementation according to claim 1, wherein the input system comprises a block-level input unit adapted for receiving a partitioned input from an input unit, and for transforming the partitioned input into a representation fit for memory cell addressing in the at least one array. 9. The hardware implementation according to claim 1, wherein the memory cells include non-volatile memory cells. 10. The hardware implementation according to claim 1, wherein the memory cells include one or more of resistive random-access memory (RRAM) cells, oxide-based random-access memory (OXRAM) cells, conductive bridging random-access memory (CBRAM) cells, vacancy-modulated conductive oxide random-access memory (VMCO) cells, phase-change memory (PCM) cells, programmable metallization (PMC) cells, static random-access memory (SRAM) cells, flash cells, floating gate cells, magnetic random-access memory (MRAM) cells, spin-transfer torque (STT) MRAM cells, and spin orbit torque (SOT) MRAM cells. 11. The hardware implementation according to claim 1, wherein the memory cells include volatile memory cells. 12. The hardware implementation according to claim 11, wherein the memory cells include one or both silicon-oxide-nitride-oxide-silicon (SONOS) cells and dynamic random access memory (DRAM) cells. 13. The hardware implementation according to claim 1, wherein each of the memory cells comprises a single selector and a single storage element. 14. A method of processing a transition of a first frame to a second frame in a system comprising at least one array of memory cells logically organized in rows and columns, each memory cell being adapted for storing a scalar value and adapted for changing the stored scalar value, the method comprising: obtaining a representation of the first frame, and applying the representation of the first frame as a row address to the array of memory cells; obtaining a representation of the second frame, and applying the representation of the second frame as a column address to the array of memory cells; reading the memory cells, addressed by the row and column addresses, and identifying one of the memory cells that satisfies a selection criterion when any of the memory cells satisfies the selection criterion, or choosing an arbitrary addressed memory cell if none of the memory cells satisfies the selection criterion, and incrementing or decrementing the scalar value of the identified or chosen memory cell; and sparsifying the representation of the second frame based on reading the memory cells. 15. The method according to claim 14, further comprising signalling an anomaly event when none of the read memory cells satisfies the selection criterion. 16. The method according to claim 14, wherein reading a memory cell of the at least one array includes reading a scalar value stored in the memory cell, and wherein identifying a memory cell of the at least one array that satisfies the selection criterion includes testing the read scalar value. 17. The method according to claim 16, wherein testing the read scalar values comprises comparing against one or more of a threshold on current, a resistance or a voltage. 18. The method according to claim 17, wherein the representation of the first frame is a sparse data bit string comprising only one logically high bit or only one logically low bit. 19. A method for predicting a representation of a next frame based on a current frame in a system comprising at least one array of memory cells logically organized in rows and columns, each memory cell being adapted for storing a scalar value and adapted for changing the stored scalar value, the method comprising: obtaining a representation of the current frame, and applying the representation of the current frame as a row address to the array of memory cells; and reading the memory cells, addressed by the row address, and identifying one or more memory cells that satisfy a selection criterion when any of the memory cells satisfies the selection criterion, the column address of the memory cells satisfying the selection criterion being the predicted representation of the next frame. 20. The method according to claim 19, further comprising: obtaining an actual representation of the next frame; and comparing the predicted representation of the next frame with the actual representation of the next frame, and signalling a misprediction when a mismatch is identified. 21. A method of hardware-implementing a temporal memory system for processing or predicting a transition of a first frame to a second frame, the method comprising: providing at least one array of memory cells to logically organized in rows and columns, wherein each of the memory cells in the array is adapted for storing a scalar value and adapted for changing the stored scalar value, the scalar value corresponding to a likelihood of temporal coincidence between an input representation of the first frame applied as a row address to the at least one array, and the column address, wherein the likelihood is adjustable through the scalar value stored in the memory cell. 22. The method according to claim 21, further comprising processing or predicting the transition of the first frame to the second frame, an input representation of the second frame being applied as a column address to the array, wherein an increment or decrement operation is applied to the scalar value of a memory cell of the at least one memory array each time the memory cell is addressed by a row address and a column address. 23. The method according to claim 21, wherein row addresses and column addresses are sparse bit strings.