The present disclosure provides a quantum processor realised in a semiconductor material and method to operate the quantum processor to implement error corrected quantum computation. The quantum processor comprises a plurality of qubit elements disposed in a two-dimensional matrix arrangement. The qubits are implemented using the nuclear or electron spin of phosphorus donor atoms. Further, the processor comprises a control structure with a plurality of control members, each arranged to control a plurality of qubits disposed along a line or a column of the matrix. The control structure is controllable to perform topological quantum error corrected computation.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A quantum processor comprising: a plurality of qubit elements disposed in a two-dimensional matrix arrangement; and a control structure comprising a plurality of control members, each control member being arranged to control a plurality of qubits disposed along a line or a column of the two-dimensional matrix, wherein the control structure is controllable to perform topological quantum error corrected computation. 2. The processor of claim 1 wherein the control structure is controllable to simultaneously interact with a plurality of qubit elements disposed in pattern of qubits. 3. The processor of claim 1 wherein a quantum state of the qubit elements is encoded in the nuclear or electron spin of one or more donor atoms embedded in a semiconducting structure. 4. The processor of claim 3 wherein the control structure is controllable to simultaneously load or unload electrons to or from a plurality of donor atoms. 5. The processor of claim 3 wherein a plurality of donor atoms is arranged to facilitate electromagnetic coupling between one or more of the qubit elements. 6. The processor of claim 3 wherein each control member is disposed at intersections or between two rows or columns of donor atoms on a plane above or below a plane comprising the donor atoms. 7. The processor of claim 6 wherein the plurality of control members comprises a first set of elongated control members, disposed in a first plane above the plane comprising the donor atoms, and a second set of elongated control members, disposed in a second plane below the plane comprising the donor atoms. 8. The processor of claim 7 wherein: the control members of the first set are parallel to each other and the control members of the second set are parallel to each other; and the control members of the first set are disposed transversally to the control members of the second set to form a plurality of intersections where control members of different sets overlap in the direction perpendicular to the plane comprising the donor atoms. 9. The processor of claim 8 wherein the control structure further comprises a plurality of control elements disposed on a plane between the first and the second plane about the intersections, each control element forming a single electron transistor with a respective control member of the first set and a second control member of the second set. 10. The processor of claim 9 wherein each control element is arranged to interact with a plurality of neighbouring donor atoms. 11. A method for loading or unloading an electron to or from a donor atom of a quantum processor, the method comprising the step of: switching, for a predetermined number of times, one or more electrostatic signals applied to respective control members from a first configuration to a second configuration, wherein the first configuration of signals is such to prevent quantum tunneling of the electron to or from the donor atom and the second configuration of signals is such to permit quantum tunneling of the electron to or from the donor atom. 12. The method of claim 11 wherein the predetermined number of times is selected such that quantum tunneling of the electron occurs with a predetermined level of confidence. 13. The method of claim 11 wherein a control element is provided in proximity of the donor atom to form a potential well about the donor atom, the potential well providing a plurality of energy levels and the energy spacing of the energy levels being such to allow quantum tunneling of electrons with different spins between the donor atom and the potential well. 14. A method of operating a quantum X gate in a quantum processor comprising a plurality of qubit elements encoded in the nuclear or electron spin of one or more donor atoms embedded in a semiconducting structure, the method comprising the steps of: applying a magnetic field to the donor atoms with a loaded electron, the magnetic field being in resonance with a nuclear spin of the donor atoms; allowing coherent rotation of the nuclear spin by an angle θ; and removing the magnetic field. 15. A method of operating a CNOT quantum gate in a quantum processor comprising a plurality of qubit elements encoded in the nuclear or electron spin of one or more donor atoms embedded in a semiconducting structure, the method comprising the steps of: loading a first electron with a predefined spin orientation onto a first donor atom; performing an X gate operation on the spin of the first electron; applying a Hadamard gate to a nuclear spin of the first donor atom; loading a second electron onto a second donor atom, the second electron having the same spin orientation as the first electron before the X gate is performed on the first electron; swapping the nuclear spin states of the first and second donor atoms with the respective electron spin states; allowing interaction of the electron spin states; swapping the electron spin states of the first and second donor atoms with the respective nuclear spin states; applying a Hadamard gate to the nuclear spins of the first donor atom; and unloading the first and second electrons. 16. The method of claim 15 wherein the method further comprises the step of, during the step of unloading the first and the second electrons, measuring the spins state of the first and the second electrons and verifying the spin orientation of the first and the second electrons to detect possible errors of the CNOT gate. 17. A method of performing readout of a quantum state of a plurality of qubit elements in a quantum processor comprising the plurality of qubit elements encoded in the nuclear or electron spin of one or more donor atoms embedded in a semiconducting structure, the method comprising the steps of: simultaneously controlling a plurality of control members arranged to interact with the donor atoms associated with the plurality of qubit elements; measuring electrical signals propagated on the plurality of control members; and performing one or more time-correlation operations using one or more of the measured electrical signals to determine associate readout information to qubit elements allowing for simultaneous readout. 18. A method for implementing topological quantum error corrected computation in a quantum processor comprising a plurality of qubit elements encoded in the nuclear or electron spin of one or more donor atoms embedded in a semiconducting structure, wherein a plurality of data qubit elements are encoded in a first set of the donor atoms and a plurality of ancilla qubit elements are encoded in a second set of the donor atoms, wherein in each row or column of the matrix data qubits are alternated with ancilla qubits to facilitate quantum correction; and the control method comprises the steps of: loading an electron onto an ancilla donor atom; loading an electron onto a data donor atom disposed north of the ancilla donor atom; performing a CNOT gate between the ancilla and data donor atom to the north; unloading the electron to the north; loading an electron onto a data donor atom disposed west of the ancilla donor atom; performing a CNOT gate between the ancilla and data donor atom to the west; unloading the electron to the west; loading an electron onto a data donor atom disposed east of the ancilla donor atom; performing a CNOT gate between the ancilla and data donor atom to the east; unloading the electron to the east; loading an electron onto a data donor atom disposed south of the ancilla donor atom; performing a CNOT gate between the ancilla and data donor atom to the south; and unloading the electron to the south, and wherein the steps of loading electrons on ancilla/data donor atoms are performed simultaneously on a plurality of donor atoms across the two-dimensional matrix. 19. The method of claim 14 wherein at least one of the steps of loading or unloading electrons is performed using a method comprising switching, for a predetermined number of times, one or more electrostatic signals applied to respective control members from a first configuration to a second configuration, wherein the first configuration of signals is such to prevent quantum tunneling of the electron to or from the donor atom and the second configuration of signals is such to permit quantum tunneling of the electron to or from the donor atom. 20. A semiconductor quantum processor comprising: a plurality of donor atoms arranged in a two-dimensional matrix; a plurality of data qubit elements encoded in a first set of the donor atoms; a plurality of ancilla qubit elements encoded in a second set of the donor atoms; wherein in each row or column of the matrix data qubits are alternated with ancilla qubits to facilitate quantum correction; and a plurality of logical data qubits and logical ancilla qubits are encoded across the matrix, each logical data qubit and logical ancilla qubit being encoded on a plurality of data qubit elements and ancilla qubit elements qubit elements.