A convolutional neural network (CNN) processing method and a CNN processing device are provided. The CNN processing method includes: acquiring an intensity type of a first module in a CNN model; in response of determining that the intensity type of the first module is a computation-intensity type, deploying the first module with an application specific integrated circuit (ASIC), where the first module occupies multiple arithmetic unit resources of the ASIC; acquiring the multiple arithmetic unit resources of the ASIC which are occupied by the first module; obtaining a first resource merging module by merging identical arithmetic unit resources among the multiple arithmetic unit resources of the ASIC which are occupied by the first module; and operating the first resource merging module by the ASIC.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A convolutional neural network (CNN) processing method, comprising: acquiring an intensity type of a first module in a CNN model; in response of determining that the intensity type of the first module is a computation-intensity type, deploying the first module with an application specific integrated circuit (ASIC), wherein the first module occupies a plurality of arithmetic unit resources of the ASIC; acquiring the plurality of arithmetic unit resources of the ASIC which are occupied by the first module; obtaining a first resource merging module by merging identical arithmetic unit resources among the plurality of arithmetic unit resources of the ASIC which are occupied by the first module; and operating the first resource merging module by the ASIC, wherein the method is performed by a processor. 2. The method according to claim 1, further comprising: acquiring an intensity type of a second module in the CNN model; in response of determining that the intensity type of the second module is the computation-intensity type, deploying the second module with the ASIC, and acquiring a plurality of arithmetic unit resources of the ASIC which are occupied by the second module; merging the first module and the second module to obtain a third module, in a case that the arithmetic unit resources occupied by the first module are identical or partially identical to the arithmetic unit resources occupied by the second module, wherein a function of the third module comprises a function of the first module and a function of the second module; and operating the third module by the ASIC. 3. The method according to claim 2, wherein the merging the first module and the second module comprises: merging identical arithmetic unit resources of the ASIC which are occupied by the first module and the second module; and merging an input interface of the first module and an input interface of the second module, and merging an output interface of the first module and an output interface of the second module. 4. The method according to claim 2, wherein the operating the third module by the ASIC comprises: setting a come into effect condition for the function of the third module based on the function of the first module and the function of the second module; and determining whether to implement the function of the first module or the function of the second module by the ASIC based on the come into effect condition. 5. The method according to claim 2, wherein after deploying the second module with the ASIC and acquiring the plurality of arithmetic unit resources of the ASIC which are occupied by the second module, the method further comprises: obtaining a second resource merging module by merging identical arithmetic unit resources among the plurality of arithmetic unit resources of the ASIC which are occupied by the second module; and operating the second resource merging module by the ASIC. 6. The method according to claim 1, further comprising: monitoring an operation state of the first resource merging module on the ASIC during operating the first resource merging module by the ASIC; unloading the first resource merging module from the ASIC after the first resource merging module completes operation on the ASIC; and loading a fourth module in the CNN model to the ASIC. 7. The method according to claim 1, further comprising: deploying a mathematical library of the CNN model on the ASIC, wherein the mathematical library comprises the first module. 8. The method according to claim 1, wherein the ASIC is a field programmable gate array (FPGA). 9. A convolutional neural network (CNN) processing device, comprising a processor and a memory for storing program instructions, wherein the processor is configured to execute the program instructions to: acquire an intensity type of a first module in a CNN model; in response of determining that the intensity type of the first module is a computation-intensity type, deploy the first module with an application specific integrated circuit (ASIC), wherein the first module occupies a plurality of arithmetic unit resources of the ASIC; acquire the plurality of arithmetic unit resources of the ASIC which are occupied by the first module; obtain a first resource merging module by merging identical arithmetic unit resources among the plurality of arithmetic unit resources of the ASIC which are occupied by the first module; and operate the first resource merging module by the ASIC. 10. The device according to claim 9, wherein the processor is further configured to execute the program instructions to: acquire an intensity type of a second module in the CNN model; in response of determining that the intensity type of the second module is the computation-intensity type, deploy the second module with the ASIC, and acquire a plurality of arithmetic unit resources of the ASIC which are occupied by the second module; merge the first module and the second module to obtain a third module, in a case that the arithmetic unit resources occupied by the first module are identical or partially identical to the arithmetic unit resources occupied by the second module, wherein a function of the third module comprises a function of the first module and a function of the second module; and operate the third module by the ASIC. 11. The device according to claim 10, wherein the processor is further configured to execute the program instructions to: merge identical arithmetic unit resources of the ASIC which are occupied by the first module and the second module; and merge an input interface of the first module and an input interface of the second module, and merge an output interface of the first module and an output interface of the second module. 12. The device according to claim 10, wherein the processor is further configured to execute the program instructions to: set a come into effect condition for the function of the third module based on the function of the first module and the function of the second module; and determine whether to implement the function of the first module or the function of the second module by the ASIC based on the come into effect condition. 13. The device according to claim 10, wherein the processor is further configured to execute the program instructions to: obtain a second resource merging module by merging identical arithmetic unit resources among the plurality of arithmetic unit resources of the ASIC which are occupied by the second module; and operate the second resource merging module by the ASIC. 14. The device according to claim 9, wherein the processor is further configured to execute the program instructions to: monitor an operation state of the first resource merging module on the ASIC during operating the first resource merging module by the ASIC; unload the first resource merging module from the ASIC after the first resource merging module completes operation on the ASIC; and load a fourth module in the CNN model to the ASIC. 15. The device according to claim 9, wherein the processor is further configured to execute the program instructions to deploy a mathematical library of the CNN model on the ASIC, wherein the mathematical library comprises the first module. 16. The device according to claim 9, wherein the ASIC is a field programmable gate array (FPGA). 17. A nonvolatile storage medium for storing one or more computer programs, wherein the computer programs comprise instructions executable by a processor comprising one or more memories; and the processor executes the instructions to perform a convolutional neural network (CNN) processing method, wherein the CNN processing method comprises: acquiring an intensity type of a first module in a CNN model; in response of determining that the intensity type of the first module is a computation-intensity type, deploying the first module with an application specific integrated circuit (ASIC), wherein the first module occupies a plurality of arithmetic unit resources of the ASIC; acquiring the plurality of arithmetic unit resources of the ASIC which are occupied by the first module; obtaining a first resource merging module by merging identical arithmetic unit resources among the plurality of arithmetic unit resources of the ASIC which are occupied by the first module; and operating the first resource merging module by the ASIC. 18. The nonvolatile storage medium according to claim 17, wherein the CNN processing method further comprises: acquiring an intensity type of a second module in the CNN model; in response of determining that the intensity type of the second module is the computation-intensity type, deploying the second module with the ASIC, and acquiring a plurality of arithmetic unit resources of the ASIC which are occupied by the second module; merging the first module and the second module to obtain a third module, in a case that the arithmetic unit resources occupied by the first module are identical or partially identical to the arithmetic unit resources occupied by the second module, wherein a function of the third module comprises a function of the first module and a function of the second module; and operating the third module by the ASIC. 19. The nonvolatile storage medium according to claim 18, wherein the merging the first module and the second module comprises: merging identical arithmetic unit resources of the ASIC which are occupied by the first module and the second module; and merging an input interface of the first module and an input interface of the second module, and merging an output interface of the first module and an output interface of the second module. 20. The nonvolatile storage medium according to claim 18, wherein the operating the third module by the ASIC comprises: setting a come into effect condition for the function of the third module based on the function of the first module and the function of the second module; and determining whether to implement the function of the first module or the function of the second module by the ASIC based on the come into effect condition.