Quantum circuits are synthesized based on a projective gate set derived from a set of single-qubit gates, typically a basis set such as the Clifford+T gates or the V-gates. An initial projective gate set is used to determine at least one characteristic of a quaternion algebra, and the quaternion algebra is used to define a new projective gate set. Exactly synthesizable unitaries are identified, and a circuit approximating a target unitary is defined in the single-qubit gate set by mapping from the new projective gate set.
Please help me write a proper abstract based on the patent claims. CLAIM: 1.-15. (canceled) 16. A quantum circuit synthesis method implemented on a classical processor, comprising: storing a computer-readable description of a single-qubit gate set; and processing the computer-readable description of the single-qubit gate set and determining a projective gate set corresponding to the single-qubit gate set. 17. The quantum circuit synthesis method of claim 16, further comprising determining a mapping of the projective gate set to a quaternion algebra. 18. The quantum circuit synthesis method of claim 17, wherein determining the mapping comprises establishing elements of the quaternion algebra. 19. The quantum circuit synthesis method of claim 17, wherein the mapping is associated with a selected nth root of unity. 20. The quantum circuit synthesis method of claim 19, wherein the mapping is associated with an 8th or 10th root of unity. 21. The quantum circuit synthesis method of claim 17, wherein the elements of the quaternion algebra are established based on at least one Pauli matrix. 22. The quantum circuit synthesis method of claim 17, wherein the elements of the quaternion algebra are established so that a first element corresponds to an identity matrix and a second element is associated with at least one of a Pauli X, Y, or Z matrix. 23. The quantum circuit synthesis method of claim 17, further comprising determining a maximal order associated with the quaternion algebra that includes elements corresponding to the single-qubit gate set. 24. The quantum circuit synthesis method of claim 23, further comprising determining a set of ideals corresponding to the single-qubit gate set. 25. The quantum circuit synthesis method of claim 17, wherein the single-qubit gate is associated with the Clifford+T basis or the V-basis. 26. A quantum circuit synthesizer, comprising: a processor; and at least one memory coupled to the processor and having stored thereon processor-executable instructions for a method that includes: based on at least one characteristic of a quaternion algebra, finding a projective gate set corresponding to a set of single-qubit gates; and establishing circuit syntheses for unitary matrices exactly synthesizable over the projective gate set. 27. The quantum circuit synthesizer of claim 26, wherein the at least one characteristic of the quaternion algebra is a maximal order or a set of ideals associated with the maximal order. 28. The quantum circuit synthesizer of claim 26, wherein the quaternion algebra is specified as ( - D , b F + ) , further comprising associating at least one quaternion basis element with a Pauli matrix as √{square root over (−D)}Z or √{square root over (−b)}X, wherein X and Z are Pauli matrices. 29. The quantum circuit synthesizer of claim 26, further comprising computer-executable instructions for: receiving a target unitary; finding a corresponding approximate target unitary that is exactly synthesizable unitary corresponding to the target unitary; and synthesizing the approximate target unitary based on the unitary matrices exactly synthesizable over the projective gate set. 30. The quantum circuit synthesizer of claim 29, wherein the approximate target unitary is synthesized based on mapping the projective gate set to the set of single-qubit gates. 31. The quantum circuit synthesizer of claim 26, wherein the set of single-qubit gates is the set of Clifford+T basis gates, the V-basis gates, or the Fibonacci basis gates. 32. The quantum circuit synthesizer of claim 26, wherein the projective gate set is obtained by rescaling at least one gate of the set of single-qubit gates. 33. The quantum circuit synthesizer of claim 26, wherein the projective gate set is based on a mapping from a CM-field. 34. The quantum circuit synthesizer of claim 26, wherein the at least one characteristic of the quaternion algebra is determined based on an initial projective gate set associated with the single-qubit gate set. 35. A quantum circuit synthesis method, comprising, in a classical processor: receiving a specification of a single-qubit gate set; determining an initial projective gate set (PGS) associated with the single-qubit gate set; identifying a set of elements of a quaternion algebra related to the PGS; based on a maximal order and a set of ideals associated with the quaternion algebra, determining a final projective gate set (PGS*); identifying a set of unitaries that are exactly representable based on PGS*; obtaining a PGS/PGS* mapping; and based on the mapping, synthesizing a target unitary in the single-qubit gate set.