Embodiments of the invention provide a neural network comprising multiple functional neural core circuits, and a dynamically reconfigurable switch interconnect between the functional neural core circuits. The interconnect comprises multiple connectivity neural core circuits. Each functional neural core circuit comprises a first and a second core module. Each core module comprises a plurality of electronic neurons, a plurality of incoming electronic axons, and multiple electronic synapses interconnecting the incoming axons to the neurons. Each neuron has a corresponding outgoing electronic axon. In one embodiment, zero or more sets of connectivity neural core circuits interconnect outgoing axons in a functional neural core circuit to incoming axons in the same functional neural core circuit. In another embodiment, zero or more sets of connectivity neural core circuits interconnect outgoing and incoming axons in a functional neural core circuit to incoming and outgoing axons in a different functional neural core circuit, respectively.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A method comprising: interconnecting multiple board structures in a scalable low power neural network circuit via an event routing system comprising at least one inter-chip router; and routing one or more neuronal firing events via the event routing system. 2. The method of claim 1, wherein: each board structure comprises multiple chip structures. 3. The method of claim 2, wherein: each chip structure comprises multiple functional neuronal core circuits. 4. The method of claim 3, wherein: each functional neural core circuit comprises a first neural core module and a second neural core module, each neural core module comprises a plurality of electronic neurons, a plurality of incoming electronic axons and a plurality of electronic synapses interconnecting the incoming electronic axons to the electronic neurons, and the first neural core module and the second neural core module are logically overlaid on one another such that electronic neurons of the first neural core module are proximal to incoming electronic axons of the second neural core module, and incoming electronic axons of the first neural core module are proximal to electronic neurons of the second neural core module. 5. The method of claim 1, wherein: each electronic synapse interconnects an incoming electronic axon to an electronic neuron such that the electronic neuron receives one or more incoming neuronal firing events from the incoming electronic axon, and generates one or more outgoing neuronal firing events based on the one or more incoming neuronal firing events received and a neuronal activation function. 6. The method of claim 1, further comprising: at each inter-chip router, maintaining compact routing information for routing one or more neuronal firing events within a same region. 7. The method of claim 4, further comprising: generating one or more parametrized chip compiler variants for a chip structure on the fly. 8. The method of claim 7, wherein the one or more parametrized chip compiler variants includes at least one of the following: number of functional neural core circuits per chip structure, number of electronic neurons per neural core module, number of incoming electronic axons per neural core module, and at least one learning rule. 9. A system comprising a computer processor, a computer-readable hardware storage medium, and program code embodied with the computer-readable hardware storage medium for execution by the computer processor to implement a method comprising: interconnecting multiple board structures in a scalable low power neural network circuit via an event routing system comprising at least one inter-chip router; and routing one or more neuronal firing events via the event routing system. 10. The system of claim 9, wherein: each board structure comprises multiple chip structures. 11. The system of claim 10, wherein: each chip structure comprises multiple functional neuronal core circuits. 12. The system of claim 11, wherein: each functional neural core circuit comprises a first neural core module and a second neural core module, each neural core module comprises a plurality of electronic neurons, a plurality of incoming electronic axons and a plurality of electronic synapses interconnecting the incoming electronic axons to the electronic neurons, and the first neural core module and the second neural core module are logically overlaid on one another such that electronic neurons of the first neural core module are proximal to incoming electronic axons of the second neural core module, and incoming electronic axons of the first neural core module are proximal to electronic neurons of the second neural core module. 13. The system of claim 9, wherein: each electronic synapse interconnects an incoming electronic axon to an electronic neuron such that the electronic neuron receives one or more incoming neuronal firing events from the incoming electronic axon, and generates one or more outgoing neuronal firing events based on the one or more incoming neuronal firing events received and a neuronal activation function. 14. The system of claim 9, further comprising: at each inter-chip router, maintaining compact routing information for routing one or more neuronal firing events within a same region. 15. The system of claim 12, further comprising: generating one or more parametrized chip compiler variants for a chip structure on the fly. 16. The system of claim 15, wherein the one or more parametrized chip compiler variants includes at least one of the following: number of functional neural core circuits per chip structure, number of electronic neurons per neural core module, number of incoming electronic axons per neural core module, and at least one learning rule. 17. A computer program product comprising a computer-readable hardware storage device having program code embodied therewith, the program code being executable by a computer to implement a method comprising: interconnecting multiple board structures in a scalable low power neural network circuit via an event routing system comprising at least one inter-chip router; and routing one or more neuronal firing events via the event routing system. 18. The computer program product of claim 17, wherein: each board structure comprises multiple chip structures. 19. The computer program product of claim 18, wherein: each chip structure comprises multiple functional neuronal core circuits. 20. The computer program product of claim 19, wherein: each functional neural core circuit comprises a first neural core module and a second neural core module, each neural core module comprises a plurality of electronic neurons, a plurality of incoming electronic axons and a plurality of electronic synapses interconnecting the incoming electronic axons to the electronic neurons, and the first neural core module and the second neural core module are logically overlaid on one another such that electronic neurons of the first neural core module are proximal to incoming electronic axons of the second neural core module, and incoming electronic axons of the first neural core module are proximal to electronic neurons of the second neural core module.