Embodiments of the present invention relate to providing power minimization in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for power-driven synaptic network synthesis is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores. An arrangement of the synaptic cores is determined by minimizing the wire length.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A method comprising: modeling power consumption of a neurosynaptic network as wire length, the neurosynaptic network comprising a plurality of neurosynaptic cores; determining an arrangement of the plurality of neurosynaptic cores by minimizing the wire length. 2. The method of claim 1, wherein the minimizing the wire length comprises applying a VLSI placement algorithm. 3. The method of claim 2, wherein the VLSI placement algorithm comprises partitioning-based placement. 4. The method of claim 1, further comprising: modeling each of the plurality of neurosynaptic cores as a node in a placement graph, the graph having a plurality of edges. 5. The method of claim 4, further comprising: assigning a weight to one of the plurality of edges based on a spike frequency. 6. The method of claim 4, further comprising assigning a weight to one of the plurality of edges based on a total number of connections between two of the plurality of neurosynaptic cores. 7. The method of claim 4, wherein the neurosynaptic network further comprises a plurality of neuron-axon connections, and wherein each of the plurality of edges correspond to one of the neuron-axon connections. 8. The method of claim 7, wherein each of the plurality of neuron-axon connections has a source core and a destination core, and wherein the plurality of edges does not include edges corresponding to those neuron-axon connections whose source core and destination core are the same. 9. The method of claim 4, wherein the plurality of neurosynaptic cores is divided among a plurality of chips. 10. The method of claim 9, wherein the plurality of chips are on a board, the board having an input port and an output port, the method further comprising: modeling each of the input port and the output port as nodes in the placement graph. 11. A method comprising: modeling power consumption of a neurosynaptic network as wire length, the synaptic network comprising a plurality of neurosynaptic cores divided among a plurality of chips; modeling each of the plurality of chips as a node in a placement graph, the graph having a plurality of edges and each edge having a weight; assigning a weight to at least one of the plurality of edges based on a spike frequency; assigning a weight to at least one of the plurality of edges based on a total number of edges between two of the plurality of neurosynaptic cores. 12. The method of claim 11, further comprising: modeling a pseudo-blockage between two of the plurality of chips, the pseudo-blockage being proportional to an energy cost between the two of the plurality of chips. 13. The method of claim 11, further comprising: determining an arrangement of the neurosynaptic cores by minimizing the wire length. 14. The method of claim 11, further comprising: determining a plurality of arrangements of the chips; for each of the plurality of arrangements, determining the wire length; selecting the arrangement of the plurality of arrangements with the minimum wire length. 15. A computer program product for power-driven synaptic network synthesis, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising: modeling power consumption of a neurosynaptic network as wire length, the neurosynaptic network comprising a plurality of neurosynaptic cores; determining an arrangement of the neurosynaptic cores by minimizing the wire length. 16. The computer program product of claim 15, wherein the minimizing the wire length comprises applying a VLSI placement algorithm. 17. The computer program product of claim 16, wherein the VLSI placement algorithm comprises partitioning-based placement. 18. The computer program product of claim 15, the method further comprising: modeling each of the plurality of neurosynaptic cores as a node in a placement graph, the graph having a plurality of edges. 19. The computer program product of claim 17, the method further comprising: assigning a weight to one of the plurality of edges based on a spike frequency. 20. The computer program product of claim 17, the method further comprising assigning a weight to one of the plurality of edges based on a total number of connections between two of the plurality of neurosynaptic cores.