A simple format is disclosed and referred to as Elementary Network Description (END). The format can fully describe a large-scale neuronal model and embodiments of software or hardware engines to simulate such a model efficiently. The architecture of such neuromorphic engines is optimal for high-performance parallel processing of spiking networks with spike-timing dependent plasticity. The software and hardware engines are optimized to take into account short-term and long-term synaptic plasticity in the form of LTD, LTP, and STDP.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A computerized system comprising: one or more processors; and a nonvolatile medium adapted to store a plurality of instructions, which when executed by the one or more processors provide event-based updates in a network comprising: a first unit and a second unit characterized by first unit memory and second unit memory, respectively; and a doublet configured to connect the first unit to the second unit, the doublet characterized by a doublet memory; wherein: the doublet is configured to deliver to the second unit an event produced by the first unit, the event occurrence being based on a change in the first unit memory; the doublet memory and the second unit memory are configured to be updated in accordance with a doublet event rule, comprising: an event timing portion configured to update the doublet memory based on a first time instance associated with occurrence of the event; and an event delivery portion configured to update the second unit memory; and execution of the doublet event timing portion and of the event delivery portion is caused by the event. 2. The system of claim 1, wherein: the network comprises: a plurality of units characterized by respective unit memory, the plurality of units comprising the first unit; a plurality of doublets configured to connect the first unit to at least a portion of the plurality of units, individual doublets characterized by respective doublet memory and the doublet event rule, the plurality of doublets comprising the doublet; and execution of individual doublet event rules for individual ones of the plurality of doublets is order-independent from one another. 3. The system, of claim 2, wherein: the timing event portion is configured based on at least one other event associated with the first unit and occurring prior to the event; execution of a individual ones of doublet event rules associated with individual ones of the plurality of doublets is configured in parallel with one another; and execution of a individual ones of doublet event rules associated with individual ones of the plurality of doublets is configured in parallel with one another. 4. The system, of claim 3, wherein: the timing event portion is configured based on a difference of time of the one other event and the event; the memory of the first unit comprises event-based memory configured to be modified based on the event; and the doublet event rule is configured based on the content of the event-based memory. 5. The system, of claim 2, further comprising: a timing component configured to provide a notification associated with an expiration of a time period; wherein: the first unit memory and memory of individual ones of the portion of the plurality of units are configured to be updated in accordance with a unit update rule based on the notification; and individual ones of the plurality of doublets are characterized by individual ones of the plurality of doublet event rules; and based on the event, execution of individual ones of a plurality of doublet event rules is configured to be completed prior to the notification occurring subsequent to the event. 6. The system, of claim 5, a memory component in data communication with one or more processors, the memory component comprising the first unit memory and the second unit memory; and wherein the first unit is configured to produce the event based on an evaluation of the unit update rule associated with the first unit. 7. The system, of claim 1, wherein the event timing portion of the doublet event rule comprises pre-post component configured to modify the doublet memory based on an operation comprising the first time and a second time with a second event associated with the second unit and occurring subsequent to the event. 8. The system, of claim 7, wherein the event timing portion of the doublet event rule comprises post-pre component configured to modify the doublet memory based on an operation comprising the first time and a third time associated with a third event associated with the second unit and occurring prior to the event. 9. The system, of claim 1, wherein: the doublet memory is configured to be modified based on a post event rule configured to be executed based on a second event associated with the second unit; and the post event rule is configured based on difference between timing of second event and the timing of at least one other event associated with the first unit and preceding second event. 10. A computerized apparatus for facilitating a parallel network having event-based plasticity rules, the apparatus comprising: a first network node comprising first node memory; a second network node comprising second node memory; an interface configured communicate data from the first node to the second node, the interface comprising an interface memory; and a timing component configured to provide a plurality of notifications associated with an expiration of a time period; wherein the interface is configured to cause modification of the second node memory responsive to a first event produced by the first node, the second node memory modification based on content of the interface memory. 11. The apparatus of claim 10, wherein: the modification of the second node memory and the modification of the interface memory each are configured to be executed within the time period prior to occurrence of a second one of the plurality of notifications subsequent to occurrence the first event; and the interface memory is configured to be modified based on the content of second node memory and an operation configured based of the first event and a second event produced by the second node. 12. The apparatus of claim 11, wherein: the interface memory comprises one or more memory storage cells within an integrated circuit, the storage cells configured to store a parameter; the interface memory modification is configured based on the parameter; and the operation comprises determination of a difference between time of occurrence of the first event and the second event. 13. The apparatus of claim 10, wherein the interface memory is configured to be modified based on the content of second node; the first network node comprises a first computational component and the second network node comprises a second computational component each embodied within a semiconductor integrated circuit; and the first node memory and the second node memory are configured to be updated based on individual ones of the notifications, the first node memory update being effectuated by the first computational component, the second node memory update being effectuated by the second computational component contemporaneously with the first node memory update. 14. The apparatus of claim 10, wherein: the interface memory is configured to be modified based on time of occurrence of the first event; the interface memory comprises one or more memory storage cells within an integrated circuit, the storage cells configured to store a parameter; and the interface memory modification is configured based on the parameter. 15. The apparatus of claim 14, wherein: the interface memory modification is configured based on timing of: (i) the first event and a second event produced by the first node prior to the first event; and (ii) a third event produced by the second node subsequent to the first event. 16. The apparatus of claim 15, wherein: the second network node comprises a second computational component embodied within the semiconductor integrated circuit; and the third event is being produced by the second computational component based on the modification of the second node memory responsive to the first event. 17. The apparatus of claim 15, wherein: the interface memory is configured to store information related to timing of the first event until at least occurrence of a fourth event produced by the first node subsequent to the first event; and the interface is configured to provide at least a portion of data within the interface memory to second node.