ACCEPTED
Please predict whether this patent is acceptable.PATENT ABSTRACT: A logic decoder circuit capable of performing Boolean or fuzzy logic has one or more logic components configured to perform a logic function of an AND-NOT gate, each AND-NOT gate comprising a circuit that performs a conjunction of an excitatory input X and an inhibitory input Y to obtain an output X-AND-NOT-Y substantially linearly for given ranges for X and Y. Certain preferred designs are provided for an X-AND-NOT-Y logic gate and a family of fast fuzzy decoders composed of such gates.