A signal processing module comprises at least one operational unit incorporating computation units, input and output interfaces able to be linked to a bus and a memory storing data destined for the computation units, the memory being organized so that each data word is stored column-wise over several addresses according to an order dependent on the application, a column having a width of one bit, the words being transferred in series to the computation units.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A signal processing module, comprising at least one operational unit incorporating computation units, input and output interfaces able to be linked to a bus and a memory storing data destined for said computation units, wherein said memory is organized in such a way that each data word is stored column-wise over several addresses, a column having a width of one bit, the words being transferred in series to said computation units. 2. The signal processing module as claimed in claim 1, wherein each data word is stored column-wise over several addresses according to an order dependent on the application using said data. 3. The signal processing module as claimed in claim 2, wherein said several addresses comprise address jumps. 4. The signal processing module as claimed in claim 1, wherein the data transfers are performed one column per computation unit. 5. The signal processing module as claimed in claim 1, comprising a routing unit connected between said memory and the operational unit, said routing unit having a number of inputs at least equal to the number of width bits of said memory, each input being linked to a single column only, said routing unit routing the data words from said memory to the computation units, one and the same word being able to be routed to several computation units. 6. The signal processing module as claimed in claim 5, wherein the routing unit comprises at least two other series of inputs/outputs able to be linked to circuits outside said module. 7. The signal processing module as claimed in claim 6, wherein said inputs/outputs are able to be linked as inputs and outputs of the routing unit of another module identical to said module. 8. The signal processing module as claimed in claim 5, wherein the routing unit performs all or part of the following operations: shifting of the bits of the data words; logical operations; expansion of the words. 9. The signal processing module as claimed in claim 1, comprising a memory virtualization unit linked on the one hand in write and read mode to said memory and on the other hand to an external memory via a circuit of DMA type. 10. The signal processing module as claimed in claim 9, wherein the memory virtualization unit performs operations of reorganization of said memory. 11. The signal processing module as claimed in claim 10, wherein the operations of reorganization of said memory are done by duplication or change of order of the data between the columns of said memory. 12. The signal processing module as claimed in claim 1, wherein the input and output interfaces communicate with said bus by a TDMA protocol. 13. The signal processing module as claimed in claim 8, comprising a memory virtualization unit linked on the one hand in write and read mode to said memory and on the other hand to an external memory via a circuit of DMA type, wherein said memory allows independent accesses in read and write mode for the input interfaces, the virtualization unit and the routing unit. 14. The signal processing module as claimed in claim 1, wherein it operates according to several independent synchronous zones, the operational unit operating in a first clock area, the input interface and the output interface operating in a second clock area. 15. The signal processing module as claimed in claim 14, comprising a memory virtualization unit linked on the one hand in write and read mode to said memory and on the other hand to an external memory via a circuit of DMA type, wherein the memory virtualization unit operates in a third independent clock area. 16. The signal processing module as claimed in claim 1, wherein the computation units execute the operations as a function of the value of a guard bit assigned to each of said units. 17. The signal processing module as claimed in claim 1, wherein the operational unit comprises at least 32 computation units, said memory having a width of 32 bits. 18. The signal processing module as claimed in claim 1, wherein being able to implement a set of neurons it performs neuronal computations or signal digital processings, said memory storing at least results of the computations, coefficients of filters or of convolution products and synaptic coefficients. 19. A circuit able to implement a neural network, comprising at least one series of signal processing modules as claimed in claim 18. 20. The circuit as claimed in claim 19, wherein the signal processing modules are grouped together as branches, a branch being formed of a groups of modules and of a dissemination bus, said modules being connected to said bus, a routing block linked to the dissemination buses of said branches performing at least the routing and the dissemination of the input and output data of said circuit to and from said branches.