A neuromorphic device may include: a pre-synaptic neuron; a synapse electrically connected with the pre-synaptic neuron through a row line; and a post-synaptic neuron electrically connected with the synapse through a column line. The post-synaptic neuron may include a first inverter, the first inverter comprising a first pull-up transistor and a first pull-down transistor, a body of the first pull-up transistor and a body of the first pull-down transistor being electrically connected with a first output node of the first inverter.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A neuromorphic device comprising: a pre-synaptic neuron; a synapse electrically connected with the pre-synaptic neuron through a row line; and a post-synaptic neuron electrically connected with the synapse through a column line, wherein the post-synaptic neuron comprises a first inverter, the first inverter comprising a first pull-up transistor and a first pull-down transistor, a body of the first pull-up transistor and a body of the first pull-down transistor being electrically connected with a first output node of the first inverter. 2. The neuromorphic device of claim 1, wherein the first pull-up transistor comprises: a source electrode electrically connected with a supply voltage node; a drain electrode electrically connected with the output node; and a gate electrode electrically connected with the column line. 3. The neuromorphic device of claim 1, wherein the first pull-down transistor comprises: a source electrode electrically connected with a ground voltage node; a drain electrode electrically connected with the output node; and a gate electrode electrically connected with the column line. 4. The neuromorphic device of claim 1, wherein the post-synaptic neuron further comprises a second inverter, the second inverter comprising a second pull-up transistor and a second pull-down transistor, a gate electrode of the second pull-up transistor and a gate electrode of the second pull-down transistor being electrically connected with the output node. 5. The neuromorphic device of claim 4, wherein the second pull-up transistor comprises: a source electrode electrically connected with the supply voltage node; and a drain electrode electrically connected with an output terminal. 6. The neuromorphic device of claim 4, wherein the second pull-down transistor comprises: a source electrode electrically connected with the ground voltage node; and a drain electrode electrically connected with an output terminal. 7. The neuromorphic device of claim 1, wherein the first pull-up transistor comprises a plurality of p-channel metal-oxide semiconductor (PMOS) transistors connected in series. 8. The neuromorphic device of claim 1, wherein the first pull-down transistor comprises a plurality of n-channel metal-oxide semiconductor (NMOS) transistors connected in series. 9. The neuromorphic device of claim 1, wherein the post-synaptic neuron further comprises an integrator having an input terminal and an output terminal, the input terminal being electrically connected with the column line, the output terminal being electrically connected with an input node of the first inverter. 10. The neuromorphic device of claim 9, wherein the post-synaptic neuron further comprises a comparator disposed between the integrator and the first inverter, an input terminal of the comparator being electrically connected with the output terminal of the integrator, an output terminal of the comparator being electrically connected with the input node of the first inverter. 11. A neuromorphic device comprising: a pre-synaptic neuron; a synapse electrically connected with the pre-synaptic neuron through a row line; and a post-synaptic neuron electrically connected with the synapse through a column line, whenever the post-synaptic neuron comprises a first inverter, the first inverter comprising: an output node; a first p-channel metal-oxide semiconductor (PMOS) transistor having a source electrode, a drain electrode, and a body, the source electrode of the PMOS transistor being electrically connected with a supply voltage node, the drain electrode and the body of the first PMOS transistor being electrically connected with the output node; and a first n-channel metal-oxide semiconductor (NMOS) transistor having a source electrode, a drain electrode, and a body, the source electrode of the first NMOS transistor being electrically connected with a ground voltage node, the drain electrode and the body of the first NMOS transistor being electrically connected with the output node. 12. The neuromorphic device of claim 11, wherein the post-synaptic neuron further comprises a second inverter, the second inverter comprising: an output terminal; a second PMOS transistor having a source electrode, a drain electrode, and a body, the source electrode of the second PMOS transistor being electrically connected with the supply voltage node, the drain electrode and the body of the second PMOS transistor being electrically connected with the output terminal; and a second NMOS transistor having a source electrode, a drain electrode, and a body, the source electrode of the second NMOS transistor being electrically connected with the ground voltage node, the drain electrode and the body of the second NMOS transistor being electrically connected with the output terminal. 13. The neuromorphic device of claim 12, wherein the output node of the first inverter is electrically connected with a gate electrode of the second PMOS transistor and a gate electrode of the second NMOS transistor. 14. The neuromorphic device of claim 12, wherein the second PMOS transistor comprises a plurality of PMOS transistors connected in series, the body of each of the plurality of PMOS transistors being electrically connected with the second output node. 15. The neuromorphic device of claim 11, wherein the first inverter comprises a plurality of NMOS transistors connected in series, the first NMOS transistor being one of the plurality of NMOS transistors, a body of each of the plurality of NMOS transistors being electrically connected with the first output node. 16. The neuromorphic device of claim 11, wherein the post-synaptic neuron further comprises an integrator having an input terminal and an output terminal, the input terminal being electrically connected with the column line, the output terminal being electrically connected with an input node of the first inverter. 17. The neuromorphic device of claim 16, wherein the post-synaptic neuron further comprises a comparator disposed between the integrator and the first inverter, an input terminal of the comparator being electrically connected with the output terminal of the integrator, an output terminal of the comparator being electrically connected with the input node of the first inverter. 18. A neuromorphic device comprising: an input device and an output device; a plurality of synapse arrays between the input device and the output device, each of the plurality of synapse arrays including a plurality of synapses, each of the plurality of synapses being electrically connected with a pre-synaptic neuron through a row line; and an inter-synapse circuit between the plurality of synapse arrays, the inter-synapse circuit including a post-synaptic neuron electrically connected with one of the plurality of synapses through a column line, wherein the post-synaptic neuron of the inter-synapse circuit comprises a first inverter. 19. The neuromorphic device of claim 18, wherein the first inverter comprises a first pull-up transistor and a first pull-down transistor, wherein the first pull-up transistor comprises one or more first p-channel metal-oxide semiconductor (PMOS) transistors, a body of each of the one or more first PMOS transistors being electrically connected with an output node of the first inverter, and wherein the first pull-down transistor comprises one or more first n-channel metal-oxide semiconductor (NMOS) transistors, a body of each of the one or more first NMOS transistors being electrically connected with the output node of the first inverter. 20. The neuromorphic device of claim 19, wherein the inter-synapse circuit further comprises a second inverter connected in series to the first inverter, wherein the second inverter comprises a second pull-up transistor and a second pull-down transistor, wherein the second pull-up transistor comprises one or more second PMOS transistors, a body of each of the one or more second PMOS transistors being electrically connected with an output node of the second inverter, and wherein the second pull-down transistor comprises one or more second NMOS transistors, a body of each of the one or more second PMOS transistors being electrically connected with the output node of the second inverter.