A circuit that makes use of chaos or self-organized criticality to generate a matrix of bits for computation and information processing. The example embodiment utilizes CMOS circuitry and can solve optimization problems. A plurality of unit cells includes multiple transistors in a lattice formation that set voltages as state variables to other transistor cells. Adjustable bifurcation parameters are utilized to bring the chaotic circuit in and out of the chaotic regime. A processing unit with software are utilized for implanting a problem of interest into the chaotic circuit, while data latches or analog to digital converters provide for reading out the voltages from the chaotic circuit.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. An apparatus for solving optimization problems, comprising: (a) a circuit lattice having a plurality of unit cells interconnected by a matrix of transmission gates; (b) wherein each unit cell is configured for setting a voltage as a state variable in the circuit lattice for each unit cell position; and (c) wherein the transmissive mode of each transmission gate is configured for being set in response to receiving a control signal to establish the transmissive mode of said transmission gate; (d) a controller configured for outputting bifurcation control signals to change operating characteristics of at least a portion of the unit cells, and for outputting coupling strength control signals for changing transmission characteristics of said transmission gates when implanting an objective function in said circuit lattice; and (e) a voltage registration circuit configured for registering state variable voltages in said circuit matrix and outputting these state variable voltages as digital signals to said controller; (f) wherein said controller is configured for implanting a problem of interest into the circuit matrix, and for controlling bifurcation to drive said matrix circuit between chaos, self-organized critical, or Markovian regimes by modifying bifurcation parameters, until a desired solution is obtained. 2. The apparatus as recited in claim 1, wherein the unit cells can be arranged in many different shapes of lattice formation. 3. The apparatus as recited in claim 1, wherein the unit cells can have any number of connections to their neighboring cells. 4. The apparatus as recited in claim 1, wherein said change in operating characteristics of the unit cells changes between having a stable state output, to that of having an oscillating output signal, depending on the state of the bifurcation control signal received. 5. The apparatus as recited in claim 1: wherein each said unit cell comprises a number of active elements within an oscillator circuit having a forward path through which an oscillator signal propagates and a feedback path from oscillator output to oscillator input; and wherein said oscillator is configured for having one of its stages selectively enabling or disabled through which the oscillator signal propagates in response to receiving said bifurcation signal. 6. The apparatus as recited in claim 1, wherein the unit cells comprise a plurality of inverters connected in series. 7. The apparatus as recited in claim 1, wherein one or more of the inverters can be bypassed or turned off changing the mode of the unit cell from an oscillator mode to circuit having steady states. 8. The apparatus as recited in claim 1, wherein said transmission gate is configured so that the transmissive mode of resistance in said transmission gate changes in response to receiving said coupling strength control signals. 9. The apparatus as recited in claim 8, wherein said transmission gate is further configured with polarity reversal so that opposing voltages are forced at opposing ends of said transmissive gate. 10. The apparatus as recited in claim 1, wherein said controller comprises a digital control circuit configured for outputting control signals to the unit cells and transmission gates and for processing voltage states read from the lattice circuit. 11. The apparatus as recited in claim 10, wherein said controller comprises at least one processing element and at least one memory configured for storing instructions executable on the processing element. 12. The apparatus as recited in claim 1, wherein said voltage registration circuit comprises latch circuits configured for converting voltage signals at the nodes of said lattice circuit to digital signals readable by said controller. 13. The apparatus as recited in claim 12, wherein each said latch circuit upon receiving a clock signal digitizes and records a voltage signal at one node of said lattice circuit. 14. The apparatus as recited in claim 1, wherein said voltage registration circuit comprises analog to digital conversion for converting voltage signals at the nodes of said lattice circuit to digital signals which can be read by said controller. 15. The apparatus as recited in claim 1, wherein the matrix of bits output from the voltage registration circuit represent a solution to the problem of interest, which is interpreted by the controller, which records the lowest objective function value (cost of a solution) and the solution that gives the lowest objective function value. 16. The apparatus as recited in claim 1, further comprising: a plurality of noise sources; wherein said circuit or system operates in a self-organized phase; and wherein width of the self-organized phase is controlled by modifying amplitude of the noise sources. 17. The apparatus as recited in claim 1, wherein the chaotic circuit comprises a plurality of non-linearly coupled oscillators connected through said lattice formation. 18. The apparatus as recited in claim 1, wherein said desired solution is obtained based on an objective function value, called a cost function, of these solutions to the objective function. 19. The apparatus as recited in claim 18, wherein said cost function of the solutions is determined from the circuit lattice, or determined by utilizing a computer processor configured for analyzing cost functions. 20. An apparatus for solving optimization problems, the system comprising: (a) a chaotic circuit comprising: (i) a plurality of unit cells, with each unit cell comprising a plurality of transistors that set voltages as state variables in a lattice formation; (ii) wherein said state variables are coupled electrically to one another through said lattice formation; and (iii) selectable modes in the unit cells, which in response to receiving bifurcation parameters bring the chaotic circuit in and out of the chaotic regime; (b) a processing unit and instructions executable on the processing unit for implanting a problem of interest into the chaotic circuit; and (c) data latches or analog to digital converters to read out the voltages from the chaotic circuit. 21. The apparatus as recited in claim 20, wherein the unit cells can be arranged in many different shapes of lattice formation. 22. The apparatus as recited in claim 20, wherein the unit cells can have any number of connections to their neighboring cells. 23. The apparatus as recited in claim 20, wherein the unit cells comprise a plurality of inverters connected in series. 24. The apparatus as recited in claim 23, wherein one or more of the inverters can be bypassed or turned off which changes unit cell mode from an oscillator mode to circuit having steady states. 25. The apparatus as recited in claim 20, wherein the objective function is implanted in the lattice formation by setting different coupling strengths between the state variables. 26. The apparatus as recited in claim 20, wherein electrical coupling between unit cells in the lattice formation is implemented using a circuit that exhibits nonlinear connections between two adjacent unit cells. 27. The apparatus as recited in claim 20, wherein said processing unit and instructions executable on the processing unit are further configured for identifying self-organized critical (SOCr) regime from output voltages of said chaos circuit which is driven to chaos, self-organized critical, or Markovian regimes by modifying bifurcation parameters sent to the unit cells. 28. The apparatus as recited in claim 20, further comprising: a plurality of noise sources; wherein said circuit or system operates in a self-organized phase; and wherein width of the self-organized phase is controlled by modifying amplitude of the noise sources. 29. The apparatus as recited in claim 20, wherein the chaotic circuit comprises a plurality of non-linearly coupled oscillators. 30. The apparatus as recited in claim 20, wherein said desired solution is obtained based on an objective function value, called a cost function, of these solutions to the objective function. 31. The apparatus as recited in claim 30, wherein said cost function of the solutions is determined from the circuit lattice, or determined by utilizing a computer processor configured for analyzing cost functions. 32. A method for solving optimization problems, comprising: (a) constructing an objective function for a problem of interest; (b) implanting the objective function into a processor configured for controlling a chaos circuit, or the chaos circuit itself; (c) wherein said chaos circuit comprises a plurality of unit cells interconnected in a lattice formation; (d) controlling the bifurcation parameters of the chaos circuit by sending signals from a processor to change the electrical properties of the circuit elements in said chaos circuit; (e) finding values of bifurcation parameters that drive the chaos circuit into chaos or self-organized criticality by modifying bifurcation parameters used for controlling unit cell function between an oscillator mode and a mode which exhibits steady state output; (f) slowly driving the chaos circuit from chaos, through the self-organized critical phase, and into the Markovian regime; and (g) continuously reading out solutions while the circuit is being moved out of chaos and keeping track of the solution that has the lowest cost. 33. A method for solving optimization problems, comprising: (a) constructing an objective function for a problem of interest; (b) implanting the objective function into a chaos circuit having a plurality of unit cells interconnected in a lattice formation; (c) finding values of bifurcation parameters that drive the chaos circuit into chaos or self-organized criticality by modifying bifurcation parameters used for controlling unit cell function between an oscillator mode and a mode which exhibits steady state output; (d) slowly driving the chaos circuit from chaos, through the self-organized critical phase, and into the Markovian regime; and (e) continuously reading out solutions until a solution with a sufficiently low cost is found, or until an allowed time threshold has been reached. 34. A method for solving optimization problems, comprising: (a) constructing an objective function for a problem of interest; (b) implanting the objective function in software executable on a processor in the circuit or system; (c) finding values of bifurcation parameters that drive the system into chaos or self-organized criticality and putting the circuit or system into self-organized criticality by modifying the bifurcation parameters; (d) continuously reading out solutions and calculating their costs using said software; (e) driving the circuit closer to chaos by changing its bifurcation parameters if the cost of the current solution is high, and driving the circuit closer to the Markovian regime if the cost of the current solution is low; and (f) tracking solution cost, and outputting a solution with the lowest cost. 35. A method for solving optimization problems, comprising: (a) constructing an objective function for a problem of interest to be solved in a chaos system; (b) implanting the objective function in software executable on a processor of the chaos system; (c) finding values of bifurcation parameters that drive the chaos system into chaos or self-organized criticality and putting the circuit or system into self-organized criticality by modifying the bifurcation parameters; (d) continuously reading out solutions and calculating their costs using said software; (e) tracking solution cost; and (f) driving the circuit closer to chaos by changing its bifurcation parameters if the said lowest cost is not decreasing, and driving the circuit closer to the Markovian regime if said lowest cost is decreasing, until a sufficiently low cost solution is obtained.