A resistive processing unit (RPU) that includes a pair of transistors connected in series providing an update function for a weight of a training methodology to the RPU, and a read transistor for reading the weight of the training methodology. In some embodiments, the resistive processing unit (RPU) further includes a capacitor connecting a gate of the read transistor to the air of transistors providing the update function for the resistive processing unit (RPU). The capacitor stores said weight of training methodology for the RPU.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A resistive processing unit (RPU) comprising: a pair of transistors connected in series providing an update function for a weight of a training methodology to the RPU; a read transistor for reading said weight of the training methodology; and a capacitor connecting a gate of the read transistor to the air of transistors providing the update function for the RPU, wherein the capacitor stores said weight of training methodology for the RPU. 2. The resistive processing unit of claim 1, wherein at least one of the read transistor and the pair of transistors that are connected in series are metal oxide semiconductor field effect transistors. 3. The resistive processing unit of claim 1, wherein the RPU processing unit operates in a subthreshold regime. 4. The resistive processing unit of claim 1, wherein the RPU unit switch at up to 1000 different incremental states. 5. The resistive processing unit of claim 1, wherein the capacitor comprises a node dielectric separating two electrodes. 6. The resistive processing unit of claim 1, wherein the pair of transistors for providing the update function comprises: a first FET having a first source/drain region connected to a positive supply voltage (Vdd), and a first gate structure connected to a first end of an update line; and a second FET having a first source/drain region for the second transistor connected to a second source/drain region of the first FET, a second gate connected to a second end of the update line, wherein the second source/drain region of the second FET is connected to the capacitor. 7. The resistive processing unit of claim 6, wherein the capacitor is present between the gate structure of the read transistor and a second source/drain region of the second FET of the pair of transistors for providing the update function. 8. A resistive processing unit comprising: a first pair of transistors connected in series providing an update function for a weight of a training methodology to the RPU; a second pair of transistors for reading the weight of the training methodology by differential weight reading; and a capacitor connecting at least one gate of the second pair of read transistor to the first pair of transistors providing the update function for the RPU, wherein the capacitor stores the weight of training methodology for the RPU. 9. The resistive processing unit of claim 8, wherein the RPU processing unit operates in a subthreshold regime. 10. The resistive processing unit of claim 8, wherein the pair of transistors for providing the update function comprises: a first FET having a first source/drain region connected to a positive supply voltage (Vdd), and a first gate structure connected to a first end of an update line; and a second FET having a first source/drain region for the second transistor connected to a second source/drain region of the first FET, a second gate connected to a second end of the update line, wherein the second source/drain region of the second FET is connected to the capacitor. 11. The resistive processing unit of claim 8, wherein the capacitor is present between the gate structure of the second pair of transistors for reading the weight of the training methodology and a second source/drain region of the second FET of the pair of transistors for providing the update function. 12. A method of storing weight of training in a resistive processing unit (RPU) of artificial neural network comprising: providing a capacitor for storing a weight of training for resistive crosspoint circuit elements for an artificial neural network; connecting a first pair of transistors to the capacitor for updating the weight of training stored on the capacitor; and providing at least one read transistor having a gate structure connected to the capacitor for reading the weight of training that is stored on the capacitor. 13. The method of claim 12, wherein updating the weight of training stored on the capacitor comprises charging or discharging the capacitor through the first pair of transistors. 14. The method of claim 12, wherein the at least one read transistor reads weight of training through a channel resistance of the at least one read transistor. 15. The method of claim 14, wherein the channel resistance of the at least one read transistor is modulated by the charge stored on the capacitor consistent with the weight of training being stored. 16. The method of claim 15, wherein the first pair of transistors and the at least one read transistor are operated in a subthreshold regime. 17. The method of claim 15, wherein the at least one read transistor comprises a pair of transistors for reading the weight of the training methodology by differential weight reading. 18. The method of claim 12, wherein the first pair of transistors to the capacitor are metal oxide semiconductor field effect transistors. 19. The method of claim 12, wherein the at least one read transistor is a metal oxide semiconductor field effect transistor. 20. The method of claim 12, wherein the RPU unit switch at up to 1000 different incremental states.