A neuromorphic computing system is provided which comprises: a synapse core; and a pre-synaptic neuron, a first post-synaptic neuron, and a second post-synaptic neuron coupled to the synaptic core, wherein the synapse core is to: receive a request from the pre-synaptic neuron, generate, in response to the request, a first address of the first post-synaptic neuron and a second address of the second post-synaptic neuron, wherein the first address and the second address are not stored in the synapse core prior to receiving the request.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A neuromorphic computing system comprising: a synapse core; and a pre-synaptic neuron, a first post-synaptic neuron, and a second post-synaptic neuron coupled to the synaptic core, wherein the synapse core is to: receive a request from the pre-synaptic neuron, and generate, in response to the request, a first address of the first post-synaptic neuron and a second address of the second post-synaptic neuron, wherein the first address and the second address are not stored in the synapse core prior to receiving the request. 2. The neuromorphic computing system of claim 1, wherein the synapse core is to: transmit (i) a first weighted spike to the first address of the first post-synaptic neuron and (ii) a second weighted spike to the second address of the second post-synaptic neuron. 3. The neuromorphic computing system of claim 1, wherein the synapse core is to generate the first address and the second address by: a finite field mathematical function which is to apply to a first seed number to generate the first address; and the finite field mathematical function which is to apply to a second seed number to generate the second address. 4. The neuromorphic computing system of claim 1, wherein the synapse core is to generate the first address and the second address by: a finite field mathematical function which is to apply to a first seed number to generate the first address and the second address. 5. The neuromorphic computing system of claim 1, wherein the synapse core is to generate the first address by: a finite field mathematical function which is to apply to a seed number to generate least significant bits (LSBs) of the first address; a storage which is to be accessed to retrieve most significant bits (MSBs) of the first address; and the first address which is to generate based on the LSBs of the first address and the MSBs of the first address. 6. The neuromorphic computing system of claim 1, wherein the first post-synaptic neuron is included in a first core of the neuromorphic computing system, and wherein the synapse core is to generate the first address by: a Galois field function which is to apply to a seed number to generate an identification of the first post-synaptic neuron within the first core; a storage which is to be accessed to retrieve an identification of the first core; and the first address which is to be generated based on the identification of the first post-synaptic neuron and the identification of the first core. 7. The neuromorphic computing system of claim 1, wherein the synapse core is to: associate a first weight with a first spike to generate the first weighted spike; and associate a second weight with a second spike to generate the second weighted spike. 8. The neuromorphic computing system of claim 7, further comprising: a memory to store the first weight and the second weight; and one or more registers to store a plurality of seed numbers, wherein the first address and the second address are to be generated based on one or more seed numbers of the plurality of seed numbers. 9. The neuromorphic computing system of claim 8, further comprising: circuitry to update the first weight and the second weight in the memory. 10. A synapse core of a neuromorphic computing system, the synapse core comprising: mapping logic to (i) receive a request, the request comprising an identification of a pre-synaptic neuron that generated the request, (ii) access a seed number based on the identification of the pre-synaptic neuron, and (iii) map the seed number to an identification of a post-synaptic neuron that is included in a first core of the neuromorphic computing system; and a first storage to provide an identification of the first core, wherein the synapse core is to (i) generate an address of the post-synaptic neuron, based at least in part on the identification of the post-synaptic neuron and the identification of the first core, and (ii) transit a spike to the address of the post-synaptic neuron. 11. The synapse core of claim 10, wherein the request is a first request, wherein the seed number is a first seed number, and wherein the mapping logic is to: receive a second request, the second request comprising the identification of the post-synaptic neuron that generated the second request; access a second seed number based on the identification of the post-synaptic neuron; and map the second seed number to the identification of the pre-synaptic neuron. 12. The synapse core of claim 11, wherein: the mapping logic is to (i) map the seed number to the identification of the post-synaptic neuron request using at least in part a first mathematical function, and (ii) map the second seed number to the identification of the pre-synaptic neuron using at least in part a second mathematical function, wherein the second mathematical function is an inverse of the first mathematical function. 13. The synapse core of claim 10, wherein the synapse core is to: associate a weight to the spike, prior to the transmission of the spike to the address of the post-synaptic neuron. 14. The synapse core of claim 11, further comprising: a memory to store the weight. 15. The synapse core of claim 14, further comprising: circuitry to update the weight in the memory, wherein the circuitry comprises: a first circuitry to generate a change in weight; a second circuitry to read an original weight from the memory; a third circuitry to generate an updated weight based on the change in weight and the original weight; and a fourth circuitry to write the updated weight to the memory. 16. The synapse core of claim 10, wherein: the request includes a sparsity number; and the mapping logic is to map the seed number to identifications of a first number of post-synaptic neurons, the first number based on the sparsity number. 17. One or more non-transitory computer-readable storage media to store instructions that, when executed by a processor, cause the processor to: receive a request from a pre-synaptic neuron; generate, in response to the request, an address of a post-synaptic neuron, wherein the address is not stored in an apparatus, which comprises the processor, prior to receiving the request; and transmit a weighted spike to the address of the post-synaptic neuron. 18. The one or more non-transitory computer-readable storage media of claim 17, wherein the instructions, when executed, cause the processor to: apply a finite field mathematical function to a seed number to generate a first section of the address. 19. The one or more non-transitory computer-readable storage media of claim 18, wherein the instructions, when executed, cause the processor to: access a storage to retrieve a second section of the address; and generate the address based on the first section and the second section. 20. The one or more non-transitory computer-readable storage media of claim 17, wherein the instructions, when executed, cause the processor to: apply a Galois field function to a seed number to generate an identification of the post-synaptic neuron, wherein the post-synaptic neuron is included in a core of a neuromorphic computing system; access a storage to retrieve an identification of the core; and generate the address based on the identification of the post-synaptic neuron and the identification of the core. 21. The one or more non-transitory computer-readable storage media of claim 17, wherein the instructions, when executed, cause the processor to: associate a synaptic weight with a spike to generate the weighted spike.