The present invention proposes a highly parallel solution for implementing ANN by sharing both weights matrix of ANN and input activation vectors. It significantly reduces the memory access operations, the on-chip buffers. In addition, the present invention considers how to achieve a load balance among a plurality of on-chip processing units being operated in parallel. It also considers a balance between the I/O bandwidth and calculation capabilities of the processing units.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A device for implementing an artificial neural network, comprising: an receiving unit for receiving a plurality of input vectors a0, a1, . . . ; a sparse matrix reading unit, for reading a sparse weight matrix W of said neural network, said matrix W represents weights of a layer of said neural network; a plurality of processing elements PExy, wherein x=0,1, . . . M-1, y=0,1, . . . N-1, such that said plurality of PE are divided into M groups of PE, and each group has N PE, x represents the xth group of PE, y represents the yth PE of the group PE, a control unit being configured to input a plurality of input vectors ai to said M groups of PE, input a fraction Wp of said matrix W to the jth PE of each group of PE, wherein j=0,1, . . . N-1, each of said PEs perform calculations on the received input vector and the received fraction Wp of the matrix W, an outputting unit for outputting the sum of said calculation results to output a plurality of output vectors b0, b1, . . . . 2. The device of claim 1, said control unit is configured to input M input vectors ai to said M groups of PE, wherein i is chosen as follows: i (MOD M)=0,1, . . . M-1. 3. The device of claim 1, said control unit is configured to input a fraction Wp of said matrix W to the jth PE of each group of PE, wherein j=0,1, . . . N-1, wherein Wp is chosen from pth rows of W in the following manner: p (MOD N)=j, wherein p=0,1, . . . P-1, j=0,1, . . . N-1, said matrix W is of the size P*Q. 4. The device of claim 1, wherein the matrix W is compressed with CCS (compressed column storage) or CRS (compressed row storage) format. 5. The device of claim 1, said matrix W is encoded with an index and codebook. 6. The device of claim 4, said sparse matrix reading unit further comprises: a pointer reading unit for reading address information in order to access non-zero weights of said matrix W. 7. The device of claim 5, said sparse matrix reading unit further comprises: a decoding unit for decoding the encoded matrix W so as to obtain non-zero weights of said matrix W. 8. The device of claim 1, further comprising: a leading zero detecting unit for detecting non-zero values in input vectors and output said non-zero values to the receiving unit. 9. The device of claim 1, wherein said receiving unit further comprising: a plurality of FIFO (first in first out) units, each of which corresponding to a group of PE. 10. The device of claim 1, said output unit further comprising: a first buffer and a second buffer, which are used to receive and output calculation results of said PE in an alternative manner, so that one of the buffers receives the present calculation result while the other of the buffers outputs the previous calculation result. 11. A method for implementing an artificial neural network, comprising: receiving a plurality of input vectors a0, a1, . . . ; reading a sparse weight matrix W of said neural network, said matrix W represents weights of a layer of said neural network; inputting said input vectors and matrix W to a plurality of processing elements PExy, wherein x=0,1, . . . M-1, y=0,1, . . . N-1, such that said plurality of PE are divided into M groups of PE, and each group has N PE, x represents the xth group of PE, y represents the yth PE of the group PE, said inputting step comprising inputting a plurality of input vectors ai to said M groups of PE, inputting a fraction Wp of said matrix W to the jth PE of each group of PE, wherein j=0,1, . . . N-1, performing calculations on the received input vector and the received fraction Wp of the matrix W by each of said PEs, outputting the sum of said calculation results to output a plurality of output vectors b0, b1, . . . . 12. The method of claim 11, the step of inputting M input vectors ai to said M groups of PE comprising: choosing i as follows: i (MOD M)=0,1, . . . M-1. 13. The method of claim 11, the step of inputting a fraction Wp of said matrix W to the jth PE of each group of PE, wherein j=0,1, . . . N-1, further comprising: choosing pth rows of W as Wp in the following manner: p (MOD N)=j, wherein p =0,1, . . . P-1, j=0,1, . . . N-1, said matrix W is of the size P*Q. 14. The method of claim 11, further comprising: compressing the matrix W with CCS (compressed column storage) or CRS (compressed row storage) format. 15. The method of claim 11, further comprising: encoding said matrix W with an index and codebook. 16. The method of claim 14, said sparse matrix reading step further comprising: a pointer reading step of reading address information in order to access non-zero weights of said matrix W. 17. The method of claim 15, said sparse matrix reading step further comprising: a decoding step for decoding the encoded matrix W so as to obtain non-zero weights of said matrix W. 18. The method of claim 11, further comprising: a leading zero detecting step for detecting non-zero values in input vectors and outputting said non-zero values to the receiving step. 19. The method of claim 11, wherein said step of inputting input vectors further comprising: using a plurality of FIFO (first in first out) units to input a plurality of input vectors to said groups of PE. 20. The method of claim 11, said outputting step further comprising: using a first buffer and a second buffer to receive and output calculation results of said PE in an alternative manner, so that one of the buffers receives the present calculation result while the other of the buffers outputs the previous calculation result.