A configurable spiking neural network based accelerator system is provided. The accelerator system may be executed on an expansion card which may be a printed circuit board. The system includes one or more application specific integrated circuits comprising at least one spiking neural processing unit and a programmable logic device mounted on the printed circuit board. The spiking neural processing unit includes digital neuron circuits and digital, dynamic synaptic circuits. The programmable logic device is compatible with a local system bus. The spiking neural processing units contain digital circuits comprises a Spiking Neural Network that handles all of the neural processing. The Spiking Neural Network requires no software programming, but can be configured to perform a specific task via the Signal Coupling device and software executing on the host computer. Configuration parameters include the connections between synapses and neurons, neuron types, neurotransmitter types, and neuromodulation sensitivities of specific neurons.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A Spiking Neural Network accelerator system comprising: an interface to connect the Spiking Neural Network accelerator system to a host computing device; one or more neural processing units configured to have digital hardware logic performing the functions associated with artificial spiking neurons, including dendrites and dynamic synapses; a programmable logic device configured to initialize the spiking neural network and configure it for a specific task. 2. The Spiking Neural Network accelerator system of claim 1, wherein the programmable logic device further comprising a signal coupling device. 3. The Spiking Neural Network accelerator system of claim 1, wherein said one or more neural processing units is a spiking artificial neural processing unit. 4. The Spiking Neural Network accelerator system of claim 1, wherein said one or more neural processing units comprises a first means to convert a data received from the host computing device to a spike and deriving an output result. 5. The Spiking Neural Network accelerator system of claim 4, wherein the first means is a sensory neuron. 6. The Spiking Neural Network accelerator system of claims 1 and 4, wherein said one or more neural processing units comprises a second means to convert the output result into an output value. 7. The Spiking Neural Network accelerator system of claim 6, wherein the output value is communicated to the host computing device. 8. The Spiking Neural Network accelerator system of claim 6, wherein the second means is a motor neuron. 9. The Spiking Neural Network accelerator system of claim 1, wherein the digital hardware logic performed computations in said one or more neural processing units by synchronous or asynchronous combinational digital logic circuits. 10. The Spiking Neural Network accelerator system of claim 1, wherein the artificial neural network comprises a plurality of neuron circuits, each neuron circuit having a unique address; and a plurality of synapse circuits that can be configured to respond to spikes received from any neuron address. 11. The Spiking Neural Network accelerator system of claim 1 further comprising an application programming interface that configures the neuron circuits, including dendrites, and the synapse circuits to perform independent Neural Processing for a running application. 12. The spiking Neural Network accelerator system of claim 1 wherein spike events are transferred over an Address Event Representation (AER) bus. 13. The Spiking Neural Network accelerator system of claim 11, wherein the spike time dependent plasticity learning rule determines efficacy of a connection between the synapse circuit and the neuron circuit. 14. An information processing system intended for use in Artificial Intelligence, the system comprising; one or more Application Specific Integrated Circuits (ASIC) containing a first plurality of digital dynamic synapse circuits that store a synapse efficacy value, said digital dynamic synapse circuits include a means of learning to respond to an input signal by producing or compounding the synapse efficacy value; and a second plurality of artificial spiking neuron circuits each comprising an integrator circuit that integrates and combines each individually produced and compounded over time synapse value to produce a value that is the digital equivalent of a biological neuron membrane potential; and a third plurality of spike shaper circuits that each receive an input value which is the equivalent of a membrane potential and determine the duration and number of output spikes. 15. The information processing system of claim 13, wherein the synapse efficacy value is stored in a digital register of the first plurality of digital synapse circuit. 16. The information processing system of claim 14, wherein digital registers store the address of the connected neuron, the connection efficacy of the synapse also known as the synapse weight, and certain variable levels.