Embodiments of the invention relate to a neural network circuit comprising a memory block for maintaining neuronal data for multiple neurons, a scheduler for maintaining incoming firing events targeting the neurons, and a computational logic unit for updating the neuronal data for the neurons by processing the firing events. The network circuit further comprises at least one permutation logic unit enabling data exchange between the computational logic unit and at least one of the memory block and the scheduler. The network circuit further comprises a controller for controlling the computational logic unit, the memory block, the scheduler, and each permutation logic unit.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A neural network circuit, comprising: a memory block for maintaining neuronal data for multiple neurons; a scheduler for maintaining incoming firing events targeting said multiple neurons; a computational logic unit for updating said neuronal data for said multiple neurons by processing said incoming firing events; at least one permutation logic unit enabling data exchange between said computational logic unit and at least one of said memory block and said scheduler; and a controller for controlling said computational logic unit, said memory block, said scheduler, and each permutation logic unit. 2. The neural network circuit of claim 1, wherein: said neuronal data comprises synaptic connectivity information, neuron parameters, and neuronal states for said multiple neurons. 3. The neural network circuit of claim 2, wherein: said memory block is configurable to maintain said synaptic connectivity information, said neuron parameters, and said neuronal states in different locations of said memory block. 4. The neural network circuit of claim 2, wherein: said controller controls a sequence of execution comprising: for each neuron: copying corresponding synaptic connectivity information, one or more corresponding neuron parameters, and a corresponding neuronal state of said neuron from said memory block to said computational logic unit; copying corresponding synaptic input information from said scheduler to said computational logic unit; instructing said computational logic unit to update said corresponding neuronal state by processing any synaptic event targeting said neuron; generating an outgoing firing event if said updated corresponding neuronal state exceeds a pre-determined threshold; and copying said updated corresponding neuronal state to said memory block. 5. The neural network circuit of claim 4, wherein: said controller interacts with a routing network for routing and delivering each outgoing firing event generated. 6. The neural network circuit of claim 1, wherein said memory block maintains neuronal data for multiple neurons of multiple neurosynaptic core circuits. 7. The neural network circuit of claim 2, wherein the number of bits allocated to at least one of said synaptic connectivity information, said neuron parameters and said neuronal states is variable. 8. The neural network circuit of claim 5, wherein: said neuronal data further comprises spike destination information for said multiple neurons; and said routing network routes and delivers each outgoing firing event generated by each neuron based on corresponding spike destination information for said neuron. 9. A method for consolidating neuronal data for multiple neurons, comprising: maintaining neuronal data for multiple neurons in a memory block; maintaining incoming firing events targeting said multiple neurons in a scheduler; updating said neuronal data for said multiple neurons by processing said incoming firing events via a computational logic unit; and exchanging data between said computational logic unit and at least one of said memory block and said scheduler via at least one permutation logic unit; and controlling said computational logic unit, said memory block, said scheduler, and each permutation logic unit. 10. The method of claim 9, wherein: said neuronal data comprises synaptic connectivity information, neuron parameters, and neuronal states for said multiple neurons. 11. The method of claim 10, further comprising: configuring said memory block to maintain said synaptic connectivity information, said neuron parameters, and said neuronal states in different locations of said memory block. 12. The method of claim 10, further comprising: controlling a sequence of execution comprising: for each neuron: copying corresponding synaptic connectivity information, one or more corresponding neuron parameters, and a corresponding neuronal state of said neuron from said memory block to said computational logic unit; copying corresponding synaptic input information from said scheduler to said computational logic unit; instructing said computational logic unit to update said corresponding neuronal state by processing any synaptic event targeting said neuron; generating an outgoing firing event if said updated corresponding neuronal state exceeds a pre-determined threshold; and copying said updated corresponding neuronal state to said memory block. 13. The method of claim 12, further comprising: routing and delivering each outgoing firing event generated via a routing network. 14. The method of claim 9, wherein said memory block maintains neuronal data for multiple neurons of multiple neurosynaptic core circuits. 15. The method of claim 10, wherein the number of bits allocated to at least one of said synaptic connectivity information, said neuron parameters and said neuronal states is variable. 16. The method of claim 13, wherein: said neuronal data further comprises spike destination information for said multiple neurons; and said routing network routes and delivers each outgoing firing event generated by each neuron based on corresponding spike destination information for said neuron. 17. A computer program product for consolidating neuronal data for multiple neurons, the computer program product comprising a computer-readable storage medium having program code embodied therewith, the program code being executable by a computer to: maintain neuronal data for multiple neurons in a memory block; maintain incoming firing events targeting said multiple neurons in a scheduler; update said neuronal data for said multiple neurons by processing said incoming firing events via a computational logic unit; exchange data between said computational logic unit and at least one of said memory block and said scheduler via at least one permutation logic unit; and control said computational logic unit, said memory block, said scheduler, and each permutation logic unit. 18. The computer program product of claim 17, the program code being further executable by the computer to: configure said memory block to maintain synaptic connectivity information, neuron parameters, and neuronal states for said multiple neurons in different locations of said memory block. 19. The computer program product of claim 18, the program code being further executable by the computer to: control a sequence of execution comprising: for each neuron: copying corresponding synaptic connectivity information, one or more corresponding neuron parameters, and a corresponding neuronal state of said neuron from said memory block to said computational logic unit; copying corresponding synaptic input information from said scheduler to said computational logic unit; instructing said computational logic unit to update said corresponding neuronal state by processing any synaptic event targeting said neuron; generating an outgoing firing event if said updated corresponding neuronal state exceeds a pre-determined threshold; and copying said updated corresponding neuronal state to said memory block. 20. The computer program product of claim 18, wherein: the number of bits allocated to at least one of said synaptic connectivity information, said neuron parameters and said neuronal states is variable.