Quantum processor architectures employ unit cells tiled over an area. A unit cell may include first and second sets of qubits where each qubit in the first set crosses at least one qubit in the second set. Angular deviations between qubits in one set may allow qubits in the same set to cross one another. Each unit cell is positioned proximally adjacent at least one other unit cell. Communicatively coupling between qubits is realized through respective intra-cell and inter-cell coupling devices.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A method of operation of a quantum processor, the quantum processor comprising a plurality of qubits and one or more coupling devices, each coupling device operable to provide controllable communicative coupling between a respective pair of the plurality of qubits, the method comprising: embedding in the quantum processor a problem graph comprising one or more odd cycles, the problem graph comprising a plurality of vertices and one or more edges, wherein embedding in the quantum processor a problem graph comprising one or more odd cycles includes: mapping each vertex to a respective single qubit of the plurality of qubits; mapping each edge to a respective single coupling device of the one or more coupling devices, the respective single coupling device operable to provide direct controllable communicatively coupling between a pair of qubits of the plurality of qubits, each qubit of the pair of qubits mapped to a respective pair of vertices. 2. The method of claim 1 wherein the problem graph comprises one or more sub-graphs, each sub-graph comprising a respective subset of the plurality of qubits and a respective subset of the one or more coupling devices, wherein at least one sub-graph is a bipartite graph. 3. The method of claim 2 wherein the at least one sub-graph is a bipartite Kn,n graph comprising a first partition of n qubits and a second partition of n qubits, the method further comprising: providing controllable communicative coupling between a respective first pair of qubits in the first partition via a first coupling device of the respective subset of the one or more coupling devices; and providing controllable communicative coupling between a respective second pair of qubits via a second coupling device of the respective subset of the one or more coupling devices, a first qubit of the respective second pair of qubits in the first partition, and a second qubit of the respective second pair of qubits in the second partition. 4. The method of claim 1 wherein the plurality of qubits and the one or more coupling devices are arranged in a plurality of unit cells tiled over an area such that each unit cell is positioned adjacent to at least one other unit cell, each unit cell comprising: a first set of qubits and a second set of qubits, each qubit in the first set and the second set of qubits comprising: a respective loop of material that is superconductive at a critical temperature; and at least one respective Josephson Junction that interrupts the loop of material, wherein: a first portion of the loop of material of a first qubit in the first set of qubits is nonparallel to at least a portion of the loop of material of a second qubit in the first set of qubits, the first portion of the first qubit crossing the second qubit in the first set of qubits; and a second portion of the loop of material of the first qubit in the first set of qubits is nonparallel to at least a portion of the loop of material of a third qubit in the second set of qubits, the second portion of the first qubit crossing the third qubit in the second set of qubits; a first coupling device positioned proximate a region at which the first qubit in the first set of qubits crosses the second qubit in the first set of qubits, the first coupling device operable to provide controllable communicative coupling between the first qubit in the first set of qubits and the second qubit in the first set of qubits; and a second coupling device in positioned proximate a region where the first qubit in the first set of qubits crosses the third qubit in the second set of qubits, the second coupling device operable to provide controllable communicative coupling between the first qubit in the first set of qubits and the third qubit in the second set of qubits. 5. The method of claim 4, the quantum processor further comprising an inter-cell coupling device positioned between a pair of qubits of the plurality of qubits, a first member qubit of the pair of qubits in a first unit cell, and a second member qubit of the pair of qubits in a second unit cell, the inter-cell coupling device which is operable to provide controllable communicative coupling between the pair of qubits. 6. The quantum processor of claim 5 wherein the second unit cell is one of horizontally, vertically, or diagonally adjacent to the first unit cell. 7. The method of claim 1 wherein the plurality of qubits comprises a plurality of superconducting qubits, and the one or more coupling devices comprise one or more superconducting coupling devices. 8. The method of claim 1, the method further comprising performing quantum annealing by the quantum processor. 9. A quantum processor comprising: a plurality of qubits; one or more coupling devices, each coupling device operable to provide controllable communicative coupling between a respective pair of the plurality of qubits to form an interconnected topology in which a problem graph comprising one or more odd cycles is embeddable, the problem graph comprising: a plurality of vertices, each vertex mapped to a respective single qubit of the plurality of qubits; and one or more edges, each edge mapped to a respective single coupling device of the one or more coupling devices, the respective single coupling device operable to provide direct controllable communicatively coupling between a pair of qubits of the plurality of qubits, each qubit of the pair of qubits mapped to a respective pair of vertices. 10. The quantum processor of claim 9 wherein the problem graph comprises one or more sub-graphs, each sub-graph comprising a respective subset of the plurality of qubits and a respective subset of the one or more coupling devices, wherein at least one sub-graph is a bipartite graph. 11. The quantum processor of claim 10 wherein the at least one sub-graph is a bipartite K,n graph comprising a first partition of n qubits and a second partition of n qubits, and wherein: a first coupling device of the respective subset of the one or more coupling devices is operable to provide controllable communicative coupling between a respective first pair of qubits in the first partition; and a second coupling device of the respective subset of the one or more coupling devices is operable to provide controllable communicative coupling between a respective second pair of qubits, a first qubit of the respective second pair of qubits in the first partition, and a second qubit of the respective second pair of qubits in the second partition. 12. The quantum processor of claim 11 wherein n=8. 13. The quantum processor of claim 9 wherein the plurality of qubits and the one or more coupling devices are arranged in a plurality of unit cells tiled over an area such that each unit cell is positioned adjacent to at least one other unit cell, each unit cell comprising: a first set of qubits and a second set of qubits, each qubit in the first set and the second set of qubits comprising: a respective loop of material that is superconductive at a critical temperature; and at least one respective Josephson Junction that interrupts the loop of material, wherein: a first portion of the loop of material of a first qubit in the first set of qubits is nonparallel to at least a portion of the loop of material of a second qubit in the first set of qubits, the first portion of the first qubit crossing the second qubit in the first set of qubits; and a second portion of the loop of material of the first qubit in the first set of qubits is nonparallel to at least a portion of the loop of material of a third qubit in the second set of qubits, the second portion of the first qubit crossing the third qubit in the second set of qubits; a first coupling device positioned proximate a region at which the first qubit in the first set of qubits crosses the second qubit in the first set of qubits, the first coupling device operable to provide controllable communicative coupling between the first qubit in the first set of qubits and the second qubit in the first set of qubits; and a second coupling device in positioned proximate a region where the first qubit in the first set of qubits crosses the third qubit in the second set of qubits, the second coupling device operable to provide controllable communicative coupling between the first qubit in the first set of qubits and the third qubit in the second set of qubits. 14. The quantum processor of claim 13, further comprising an inter-cell coupling device positioned between a pair of qubits of the plurality of qubits, a first member qubit of the pair of qubits in a first unit cell, and a second member qubit of the pair of qubits in a second unit cell, the inter-cell coupling device which is operable to provide controllable communicative coupling between the pair of qubits. 15. The quantum processor of claim 14 wherein the second unit cell is one of horizontally, vertically, or diagonally adjacent to the first unit cell. 16. The quantum processor of claim 9 wherein the plurality of qubits comprises a plurality of superconducting qubits, and the one or more coupling devices comprise one or more superconducting coupling devices. 17. The quantum processor of claim 16 wherein the plurality of superconducting qubits comprises a plurality of superconducting flux qubits. 18. The quantum processor of claim 9 wherein the quantum processor is operable to implement quantum annealing. 19. The quantum processor of claim 9 wherein the quantum processor comprises a multi-layered integrated circuit. 20. The quantum processor of claim 19 wherein the quantum processor comprises a superconducting quantum processor and the multi-layered integrated circuit comprises a multi-layered superconducting integrated circuit.