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Please predict whether this patent is acceptable.PATENT ABSTRACT: N processing units (PU) each have an arithmetic unit (AU) that performs an operation on first, second and third inputs to generate a result to store in an accumulator having an output provided to the first input. A weight input is received by the AU second input. A multiplexed register has first, second, third and fourth data inputs and an output received by the third AU input. A first memory provides N weight words to the N weight inputs. A second memory provides N data words to the multiplexed register first data inputs. The multiplexed register output is also received by the second, third, and fourth data input of the multiplexed register one, 2̂J, and 2̂K PUs away, respectively. The N multiplexed registers collectively operate as an N-word rotater that rotates by one, 2̂J, or 2̂K words when the control input specifies the second, third, or fourth data input, respectively.