A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A neuromorphic device, comprising: a substrate, the substrate being substantially planar; a first floating-gate transistor on the substrate, the first floating-gate transistor having: a channel; a floating gate; and a control gate; and a second floating-gate transistor, vertically stacked on the first floating-gate transistor, the second floating-gate transistor having: a channel; a floating gate; and a control gate directly connected to the control gate of the first floating-gate transistor, the neuromorphic device having: a gate contact connected to: the control gate of the first floating-gate transistor; and the control gate of the second floating-gate transistor; a first source-drain contact connected to a first end of the channel of the first floating-gate transistor; a second source-drain contact connected to a second end, opposite the first end, of the channel of the first floating-gate transistor and to a first end of the channel of the second floating-gate transistor; and a third source-drain contact connected to a second end of the channel of the second floating-gate transistor. 2. The neuromorphic device of claim 1, wherein the channel of the first floating-gate transistor and the channel of the second floating-gate transistor are parts of one continuous, vertical structure. 3. The neuromorphic device of claim 1, wherein the neuromorphic device has: a first number of floating-gate transistors, including the first floating-gate transistor and the second floating-gate transistor; and a second number of source-drain contacts, including the first source-drain contact, the second source-drain contact, and the third source-drain contact, the second number being greater than the first number by one. 4. The neuromorphic device of claim 1, comprising sixteen floating-gate transistors including the first floating-gate transistor and the second floating-gate transistor. 5. The neuromorphic device of claim 1, comprising thirty-two floating-gate transistors including the first floating-gate transistor and the second floating-gate transistor. 6. The neuromorphic device of claim 1, wherein: the first source-drain contact includes: a first conductive path; and a second conductive path, the first conductive path being horizontal and having a first length, and the second conductive path being vertical and having a second length, the second source-drain contact includes: a third conductive path; and a fourth conductive path, the third conductive path being horizontal and having a third length less than the first length, and the fourth conductive path being vertical and having a fourth length less than the second length. 7. The neuromorphic device of claim 1, wherein each of the first source-drain contact and the second source-drain contact comprises a horizontal portion, and the gate contact comprises a vertical portion in a gate contact opening penetrating: the horizontal portion of the first source-drain contact; and the horizontal portion of the second source-drain contact, the neuromorphic device further comprising: an internal sidewall spacer in the gate contact opening, to insulate the gate contact from the horizontal portion of the first source-drain contact; and an internal sidewall spacer in the gate contact opening, to insulate the gate contact from the horizontal portion of the second source-drain contact. 8. A method for operating a neural network, the method comprising: erasing a neuromorphic device, the neuromorphic device comprising: a substrate, the substrate being substantially planar; a first floating-gate transistor on the substrate, the first floating-gate transistor having: a channel; a floating gate; and a control gate; and a second floating-gate transistor, vertically stacked on the first floating-gate transistor, the second floating-gate transistor having: a channel; a floating gate; and a control gate directly connected to the control gate of the first floating-gate transistor, the neuromorphic device having: a gate contact connected to: the control gate of the first floating-gate transistor, and the control gate of the second floating-gate transistor; a first source-drain contact connected to a first end of the channel of the first floating-gate transistor, a second source-drain contact connected to a second end of the channel of the first floating-gate transistor and to a first end of the channel of the second floating-gate transistor; and a third source-drain contact connected to a second end of the channel of the second floating-gate transistor, the erasing comprising: applying, during a first time interval, a first voltage to the gate contact; and applying, during the first time interval, a second voltage, higher than the first voltage, to: the first source-drain contact; the second source-drain contact; and the third source-drain contact. 9. The method of claim 8, wherein the first time interval is sufficiently long and the second voltage is sufficiently higher than the first voltage to cause each of a threshold voltage of the first floating-gate transistor, and a threshold voltage of the second floating-gate transistor to be less than 0.5 V. 10. The method of claim 8, wherein the neuromorphic device comprises a plurality of vertically stacked floating-gate transistors including the first floating-gate transistor and the second floating-gate transistor, and has a plurality of source-drain contacts, including the first source-drain contact, the second source-drain contact, and the third source-drain contact, the method further comprising programming the neuromorphic device, the programming comprising: applying a third voltage to: a first set of consecutive source-drain contacts of the plurality of source-drain contacts; and the gate contact; and applying a fourth voltage to a second set of consecutive source-drain contacts of the plurality of source-drain contacts, the first set of consecutive source-drain contacts and the second set of consecutive source-drain contacts: being mutually exclusive subsets of the plurality of source-drain contacts, and together including all of the plurality of source-drain contacts. 11. The method of claim 10, wherein the third voltage is selected from among a set of 256 voltages. 12. The method of claim 10, wherein the third voltage is selected from among a set of four voltages. 13. The method of claim 8, further comprising evaluating the neuromorphic device, the evaluating comprising: applying a third voltage to the gate contact, the third voltage being selected to cause each of the first floating-gate transistor and the second floating-gate transistor to operate in a linear mode; applying a first input voltage to the first source-drain contact; applying a second input voltage to the second source-drain contact; and processing a voltage at the third source-drain contact with a thresholding circuit, the thresholding circuit being a circuit configured to receive, as an input, the voltage at the third source-drain contact and to generate an output voltage, the output voltage being a nonlinear function of the voltage at the third source-drain contact. 14. The method of claim 13, wherein the thresholding circuit is configured to generate, as the output voltage, a voltage selected from among a set of 256 voltages. 15. The method of claim 13, wherein the thresholding circuit is configured to generate, as the output voltage, a voltage selected from among a set of four voltages. 16. A method for fabricating a neuromorphic device, the method comprising: forming, on a substrate, a first floating-gate transistor, the first floating-gate transistor having: a channel; a floating gate; and a control gate; and forming a second floating-gate transistor, vertically stacked on the first floating-gate transistor, the second floating-gate transistor having: a channel; a floating gate; and a control gate directly connected to the control gate of the first floating-gate transistor, the forming of the second floating-gate transistor and of the first floating-gate transistor comprising: forming a gate contact connected to: the control gate of the first floating-gate transistor; and the control gate of the second floating-gate transistor; forming a first source-drain contact connected to a first end of the channel of the first floating-gate transistor; forming a second source-drain contact connected to a second end of the channel of the first floating-gate transistor and to a first end of the channel of the second floating-gate transistor; and forming a third source-drain contact connected to a second end of the channel of the second floating-gate transistor. 17. The method of claim 16, wherein the forming of the gate contact comprises forming a gate contact opening penetrating: a horizontal portion of the first source-drain contact; and a horizontal portion of the second source-drain contact. 18. The method of claim 17, wherein the forming of the gate contact further comprises: forming an internal sidewall spacer in the gate contact opening, to insulate the gate contact from the horizontal portion of the first source-drain contact; and forming an internal sidewall spacer in the gate contact opening, to insulate the gate contact from the horizontal portion of the second source-drain contact. 19. The method of claim 17, wherein the forming of the gate contact further comprises filling the gate contact opening with contact metal. 20. The method of claim 17, wherein the forming of the first source-drain contact and the first source-drain contact comprises: forming a first source-drain contact opening extending to the horizontal portion of the first source-drain contact; forming a second source-drain contact opening extending to the horizontal portion of the second source-drain contact; and filling the first source-drain contact opening and the second source-drain contact opening with contact metal.