A neural array may include an array unit, a first processing unit, and a second processing unit. The array unit may include synaptic devices. The first processing unit may input a row input signal to the array unit, and receive a row output signal from the array unit. The second processing unit may input a column input signal to the array unit, and receive a column output signal from the array unit. The array unit may have a first array value and a second array value. When the first processing unit or the second processing unit receives an output signal based on the first array value from the array unit which has selected the first array value and then the array unit selects the second array value, it may input a signal generated based on the output signal to the array unit which has selected the second array value.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A neural array configured to form a deep neural network, comprising: an array unit including one or more synaptic devices arranged in one or more rows and columns; a first processing unit coupled to the array unit and configured to input a row input signal to the array unit and receive a row output signal from the array unit; and a second processing unit coupled to the array unit and configured to input a column input signal to the array unit and receive a column output signal from the array unit, wherein the array unit has multiple selectable array values including a first array value and a second array value, and when the first processing unit or the second processing unit receives an output signal based on the first array value from the array unit which has selected the first array value and the array unit selects the second array value, the first processing unit or the second processing unit inputs an input signal generated based on the output signal to the array unit that selects the second array value. 2. The neural array of claim 1, wherein each of the one or more synaptic devices is configured to form a NAND flash structure. 3. The neural array of claim 1, wherein the one or more synaptic devices include a floating gate metal oxide silicon field effect transistor (FG MOSFET). 4. The neural array of claim 1, wherein the array unit is configured to output a column output signal to the second processing unit based on the row input signal received from the first processing unit and output a row output signal to the first processing unit based on the column input signal received from the second processing unit. 5. The neural array of claim 1, wherein the array unit is configured to operate in a time-division multiplexing mode, and the array unit uses the first array value in a first time section and uses the second array value in a second time section after the first time section. 6. The neural array of claim 1, wherein the neural array is configured to implement a Restricted Boltzmann Machine. 7. The neural array of claim 6, wherein the neural array is configured to: update the first array value using at least one input signal; generate at least one input signal for the second array value based on the updated first array value; and update the second array value using the at least one input signal for the second array value. 8. The neural array of claim 7, wherein the neural array is configured to, after multiple array values including the first array value and the second array value are updated, performs a Back Propagation Process based on the updated multiple array values to further update the updated multiple array values. 9. A method to be performed in a neural array which is configured to form a deep neural network and implement a Restricted Boltzmann Machine, wherein the neural array has multiple selectable array values including a first array value and a second array value and is configured to cause an output signal for an array value to be an input signal for another array value, the method comprises: updating a first array value; and updating a second array value based on the updated first array value, wherein the updating the first array value includes: selecting the first array value; generating a first output signal based on a first input signal and the first array value; generating a reconstructed first input signal based on the first output signal and the first array value; generating a reconstructed first output signal based on the reconstructed first input signal and the first array value; and updating the first array value based on the first input signal, the first output signal, the reconstructed first input signal, and the reconstructed first output signal, and wherein the updating the second array value includes: generating a second input signal based on the first input signal and the updated first array value; and selecting the second array value. 10. The method of claim 9, wherein the neural array includes one or more synaptic devices arranged in one or more rows and columns, and each of the one or more synaptic devices is configured to form a NAND flash structure. 11. The method of claim 10, wherein the one or more synaptic devices include a floating gate MOSFET. 12. The method of claim 9, wherein the neural array is configured to operate in a time-division multiplexing mode, wherein the updating the first array value is performed in a first time section according to the time-division multiplexing mode, and wherein the updating the second array value is performed in a second time section after the first time section. 13. A method to perform a Back Propagation Process in a neural array forming a deep neural network, the neural array has multiple selectable array values and configured to cause an output signal for an array value to be an input signal for another array value, the method comprises: receiving an input signal; performing forward propagation to generate an output signal based on the received input signal and the multiple array values; obtaining an error value based on the output signal and a target value for the output signal; performing back propagation based on the error value and the multiple array values; and updating the multiple array values based on results of the forward propagation and the back propagation. 14. The method of claim 13, wherein the neural array includes one or more synaptic devices arranged in one or more rows and columns, and each of the one or more synaptic devices is configured to form a NAND flash structure. 15. The method of claim 13, wherein the one or more synaptic devices include a floating gate MOSFET.