A synapse array based on a static random access memory (SRAM), a pulse shaper circuit, and a neuromorphic system are provided. The synapse array includes a plurality of synapse circuits. At least one synapse circuit among the plurality of synapse circuits includes at least one bias transistor and at least two cut-off transistors, and the at least one synapse circuit is configured to charge a membrane node of a neuron circuit connected with the at least one synapse circuit using a sub-threshold leakage current that passed through the at least one bias transistor.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A synapse array based on a static random access memory (SRAM), the synapse array comprising a plurality of synapse circuits, wherein at least one synapse circuit among the plurality of synapse circuits comprises at least one bias transistor and at least two cut-off transistors, and the at least one synapse circuit is configured to charge a membrane node of a neuron circuit connected with the at least one synapse circuit using a sub-threshold leakage current that passed through the at least one bias transistor. 2. The synapse array of claim 1, wherein the at least one synapse circuit is configured to change a value of the SRAM using a leakage current that passed through the at least two cut-off transistors. 3. The synapse array of claim 1, wherein the neuron circuit is configured to fire a spike based on a result of comparing a number of occurrences of oscillation pulses generated based on a voltage of the membrane node to a predetermined reference number. 4. The synapse array of claim 1, wherein the neuron circuit comprises: a pulse generator configured to generate an oscillation pulse based on a voltage of the membrane node; a counter configured to count a number of occurrences of the oscillation pulse; and a comparator configured to compare the number of occurrences to a predetermined reference number. 5. The synapse array of claim 4, wherein the comparator is configured to compare the reference number with the number of occurrences, in synchronization with a clock signal periodically input. 6. The synapse array of claim 4, wherein the neuron circuit further comprises a transistor connected to a ground, and the oscillation pulse is used to reset the membrane node by activating the transistor. 7. The synapse array of claim 1, wherein the at least two cut-off transistors comprise a first cut-off transistor and a second cut-off transistor, the first cut-off transistor is connected to a power voltage for pull-up, the second cut-off transistor is connected to a ground for pull-down, and the at least one bias transistor is connected to the membrane node of the neuron circuit connected with the at least one synapse circuit. 8. A pulse shaper circuit configured to generate a digital pulse indicating whether pulses corresponding to spikes fired by a neuron circuit potentiate or depress a synaptic weight of a synapse circuit. 9. The pulse shaper circuit of claim 8, comprising: a finite impulse response (FIR) filter comprising a 1-bit D flip flop chain configured to store the pulses; a first OR calculator configured to generate the digital pulse by performing OR calculation with respect to at least one pulse corresponding to potentiation of the synaptic weight among the stored pulses; and a second OR calculator is configured to generate the digital pulse by performing OR calculation with respect to at least one pulse corresponding to depression of the synaptic weight among the stored pulses. 10. The pulse shaper circuit of claim 9, wherein the pulse shaper circuit is configured to generate the digital pulse for maintaining the synaptic weight based on a value of the first OR calculator and a value of the second OR calculator. 11. A neuromorphic system comprising: a synapse array based on a static random access memory (SRAM), the synapse array comprising at least one synapse circuit; a neuron circuit connected with the synapse circuit, the synapse circuit being configured to charge a membrane node of the neuron circuit using a sub-threshold leakage current that passed through at least one bias transistor of the synapse array, and the neuron circuit being configured to fire spikes based on a voltage of the membrane node; and a pulse shaper circuit configured to generate a digital pulse corresponding to the fired spikes. 12. The neuromorphic system of claim 11, wherein the synapse array comprises a plurality of synapse circuits, the plurality of synapse circuits including the at least one synapse circuit; the neuromorphic system comprises a plurality of neuron circuits and a plurality of pulse shaper circuits; and the neuromorphic system further comprises a spike-timing dependent plasticity (STDP) logic circuit configured to determine an update state of a synapse circuit among the plurality of synapse circuits and an updated value for the synapse circuit based on a digital pulse; and an encoder configured to access a synapse circuit to be updated according to the digital pulse. 13. The neuromorphic system of claim 11, the neuron circuit is configured to fire spikes based on a result of comparing a number of occurrences of oscillation pulses generated based on the voltage of the membrane node to a predetermined reference number. 14. The neuromorphic system of claim 11, wherein the synapse array further comprises at least two cut-off transistors, and is configured to change a value of the SRAM using a leakage current that passed through the at least two cut-off transistors. 15. The neuromorphic system of claim 11, wherein the neuron circuit comprises: a pulse generation unit configured to generate an oscillation pulse based on the voltage of the membrane node; a counter configured to count a number of occurrences of the oscillation pulse; and a comparator configured to compare the number of occurrences to a predetermined reference number. 16. The neuromorphic system of claim 15, wherein the neuron circuit further comprises a transistor connected to a ground, and the oscillation pulse is used to reset the membrane node by activating the transistor. 17. The neuromorphic system of claim 14, wherein the at least two cut-off transistors comprise a first cut-off transistor and a second cut-off transistor, the first cut-off transistor is connected to a power voltage for pull-up, the second cut-off transistor is connected to a ground for pull-down, and the at least one bias transistor is connected to the membrane node of the neuron circuit connected with the synapse circuit. 18. The neuromorphic system of claim 12, wherein the plurality of pulse shaper circuits are configured to generate a digital pulse indicating whether pulses corresponding to spikes fired by a neuron circuit potentiate or depress a synaptic weight of the synapse circuit. 19. The neuromorphic system of claim 18, wherein the STDP logic circuit is configured to determine an update state of the plurality of synapse circuits and an updated value for the synapse circuits based on whether the digital pulse potentiates or depresses the synaptic weight. 20. The neuromorphic system of claim 19, wherein the STDP logic circuit is configured to determine the update states and the updated values of the synapse circuits, depending on a spike time between digital pulses corresponding to the spikes fired by the plurality of neuron circuits. 21. The neuromorphic system of claim 20, wherein the neuromorphic system is configured to enable a write line (WL) of a synapse circuit corresponding to a first neuron circuit at a falling edge of a first digital pulse corresponding to a spike fired by the first neuron circuit in response to the first neuron circuit among the plurality of neuron circuits firing the spike. 22. The neuromorphic system of claim 21, wherein the STDP logic circuit is configured to determine the updated value of the synapse circuit corresponding to the first neuron circuit based on a value of a second digital pulse of a second neuron seen from the falling edge of the first digital pulse. 23. The neuromorphic system of claim 22, wherein the STDP logic circuit is configured to update a value for potentiating the synaptic weight as the updated value in response to the first digital pulse preceding the second digital pulse. 24. The neuromorphic system of claim 22, wherein the STDP logic circuit is configured to update a value for depressing the synaptic weight as the updated value in response to the second digital pulse preceding the first digital pulse. 25. The neuromorphic system of claim 22, wherein the STDP logic circuit is configured to determine to maintain the value of the synapse circuit corresponding to the first neuron circuit in response to ‘0’ being detected at the falling edge of the first digital pulse. 26. The neuromorphic system of claim 12, wherein the encoder is configured to transmit the updated value to the synapse circuits according to the digital pulse.