A circuit element of a multi-dimensional dynamic adaptive neural network array (DANNA) may comprise a neuron/synapse select input functional to select the circuit element to function as one of a neuron and a synapse. In one embodiment of a DANNA array of such circuit elements, (wherein a circuit element may be digital), a destination neuron may be connected to a first neuron by a first synapse in one dimension a second destination neuron may be connected to the first neuron by a second synapse in a second dimension to form linked columns and rows of neuron/synapse circuit elements. In one embodiment, the rows and columns of circuit elements have read registers that are linked together by signal lines and clocked and controlled so as to output columnar data to an output register when a neuron/synapse data value is stored in the read register.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. Apparatus for a neuromorphic network comprising an artificial neural network, the artificial neural network comprising a multi-dimensional array of interconnected circuit elements, each circuit element having similar components to one another selectively representing, under special purpose program control, one of a neuron and a synapse, at least one circuit element of the array selectively representing an input neuron, at least one circuit element of the array selectively representing an output synapse and under program control one to multiple circuit elements of the array selectively representing a neuron or a synapse connected between the input neuron and the output synapse, the circuit elements formed in an array of rows and columns with signal lines connecting rows and signal lines connecting columns, a given circuit element at a particular row and column number selectively reporting its output to an output register when a value is stored in a read register of the circuit element. 2. The apparatus of claim 1, the selected elements of the array comprising a programmable logic array, ASIC or VLSI component. 3. The apparatus of claim 2, defined by a hardware description language, circuit diagram and/or logic equations. 4. The apparatus of claim 3 wherein said hardware description language is one of VHDL and Verilog. 5. The apparatus of claim 1 wherein at least one circuit element is a digital circuit element. 6. The apparatus of claim 1 wherein at least one circuit element contains an analog electronic device. 7. The apparatus of claim 6 wherein said analog electronic device is a memristor. 8. The apparatus of claim 1, the special purpose program control implemented using one of a microprocessor, a microcontroller, and a processor core. 9. The apparatus of claim 1 wherein a circuit element of the array of interconnected circuit elements comprises an accumulator, a comparator, a refractory period input and a threshold input, the accumulator accumulating charge from a plurality of selectable inputs of the circuit element for comparison at the comparator with the threshold input, and, if the accumulated charge is greater than the threshold and if a refractory period has lapsed, the comparator causing a fire output of the circuit element. 10. The apparatus of claim 1 wherein a circuit element of the array comprises a read register responsive to a global network clock, the read register having an output port to the output register and further having a load read register signal line input for actuating a transmittal of a neuron/synapse event to the read register. 11. The apparatus of claim 1 further comprising a clock circuit for generating a plurality of clock signals and each circuit element comprising an LTD/LTP state machine, the clock signals comprising a network clock signal input to a synapse distance/delay register and to a counter representing an LTD/LTP refractory period signal, an LTD/LTP refractory period signal to the LTD/LTP state machine, the LTD/LTP state machine for respectively outputting an increment/decrement weight signal to an accumulator of a circuit element representing a synapse. 12. The apparatus of claim 11 wherein the circuit element of the array outputs an event to a corresponding read register and to an output register responsive to a load read register signal. 13. The apparatus of claim 1 comprising an array of a plurality of X columns of circuit elements and Y rows of circuit elements, at least one circuit element being selectively enabled, each selectively enabled circuit element performing a selected function of one of a neuron and of a synapse, wherein X and Y are integers, the array having an output register for selectively receiving a value from a circuit element in a column and providing an output signal according to said received value. 14. The apparatus of claim 1 comprising an array of a plurality of X columns of circuit elements and Y rows of circuit elements, one circuit element representing a destination neuron and a plurality of connected circuit elements representing synapse circuit elements selectively connected under special purpose program control to the destination neuron such that LTP/LTD occurs symmetrically on synapses connected to enabled inputs of the destination neuron, the destination neuron's enabled input from the first output of a plurality of synapses being randomly sampled, and, thereafter, the plurality of synapses being sequentially sampled until all connected synapse inputs are sampled, the next input from a synapse to the destination neuron being randomly selected from the plurality of synapses. 15. The apparatus of claim 14 wherein the array comprises the destination neuron connected to a plurality of synapses, one of the synapses emitting a weight signal on at least one of its outputs, the at least one output including an output of the weight signal to be received at an enabled input of the destination neuron, the destination neuron one of 1) having a charge state insufficient to fire upon receiving the weight signal, 2) being not refractory and having a charge state sufficient to fire and 3) being refractory, the connected synapse determining that its outputs caused the neuron to fire or did not cause the neuron to fire during a given clock cycle. 16. The apparatus of claim 1 comprising an artificial neural network having at least one destination neuron and at least one connected synapse, each of the destination neuron and the synapse comprising one circuit element, the array having a network clock having a plurality of k cycles where k is an integer greater than zero network clock cycles, the at least one synapse being configured to implement a delay line of k greater than zero clock cycles and to emit a weight value causing the destination neuron to fire when the firing event is received at an enabled input of the destination neuron and reported to the output register. 17. The apparatus of claim 16 whereas the destination neuron continues to fire at least once every k, being greater than zero, clock cycles, the destination neuron and connected synapse forming an oscillating structure. 18. The apparatus of claim 1 comprising at least one artificial neural network determined using evolutionary optimization of firing parameters of neurons and delay parameters of synapses. 19. The apparatus of claim 1 wherein each circuit element comprises an accumulator, a fire counter for tracking the number of fire states, the read register storing, if a neuron, a charge value and, if a synapse, a weight value. 20. A method of providing real-time monitoring of circuit elements of a neuromorphic network comprising an artificial neural network, the artificial neural network comprising a multi-dimensional array of interconnected circuit elements, each circuit element having similar components to one another selectively representing, under special purpose program control, one of a neuron and a synapse, at least one circuit element of the array selectively representing an input neuron, at least one circuit element of the array selectively representing an output synapse and, under program control, one to multiple circuit elements of the array selectively representing a neuron or a synapse connected between the input neuron and the output synapse, the circuit elements formed in an array of rows and columns with signal lines connecting rows and signal lines connecting columns, the method comprising a given circuit element at a particular row and column number reporting its output to an output register when selectively actuated and having a value stored in a read register. 21. The method of claim 20 wherein a circuit element of the array of interconnected circuit elements comprises an accumulator, a comparator, a refractory period input and a threshold input, the accumulator accumulating charge from a plurality of selectable inputs of the circuit element for comparison at the comparator with the threshold input, and, if the accumulated charge is greater than the threshold and if a refractory period has lapsed, the comparator causing a fire output of the circuit element for storage in the read register. 22. The method of claim 20 wherein a circuit element of the array comprises a synapse distance/delay register having a synapse distance/delay input and a FIFO with sufficient entries to represent the maximum synapse distance/delay to hold input fire events, the synapse distance/delay register, responsive to an input fire multiplexer, outputting a fire signal to an element fire signal line according to the synapse distance/delay input for storage in the read register. 23. The method of claim 20 wherein an array of the network comprises a plurality of X columns of circuit elements and Y rows of circuit elements, at least one circuit element being selectively enabled, each selectively enabled circuit element performing a selected function of one of a neuron and of a synapse, wherein X and Y are integers, the array having the output register for selectively receiving a value from a circuit element in a column and providing an output signal according to said received value. 24. The method of claim 20 wherein an array of the network comprises a plurality of X columns of circuit elements and Y rows of circuit elements, one circuit element representing a destination neuron and a plurality of connected circuit elements representing synapse circuit elements selectively connected under special purpose program control to the destination neuron such that long-term potentiation and depression occur symmetrically on synapses connected to enabled inputs of the destination neuron, the destination neuron's enabled input from the first output of a plurality of synapses being randomly sampled, and, thereafter, the plurality of synapses being sequentially sampled until all connected synapse inputs are sampled, the next input from a synapse to the destination neuron being randomly selected from the plurality of synapses.