Systems, apparatuses, and methods for enabling sensor discovery in autonomous devices herein. An example device to perform system-level verification predictions includes a neural network circuit including a neural network. During a first phase, the neural network circuit to train the neural network using respective assembly-level test data and the system-level verification test data associated with each of a first plurality of semiconductor dice. The first plurality of semiconductor dice is produced from a plurality of training wafers. During a second phase, the neural network circuit to determine, using the neural network, a system-level pass/fail decision for each of second plurality of semiconductor dice based on respective assembly-level test data associated with each of the second plurality of semiconductor dice. The second plurality of semiconductor dice is produced from a plurality of production wafers.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A device to perform system-level verification predictions comprising: a prediction circuit including a neural network, the prediction circuit to: during a first phase: receive respective assembly-level test data and respective system-level verification test data associated with each of a first plurality of end products, the first plurality of end products produced from a plurality of training units; and train the neural network using the respective assembly-level test data and the system-level verification test data associated with each of the first plurality of end products; and during a second phase: receive respective assembly-level test data associated with each of a second plurality of end products, the second plurality of end products produced from a plurality of production units; and determine, using the neural network, a system-level pass/fail decision for each of the second plurality of end products based on the respective assembly-level test data. 2. The device of claim 1, further comprising a transceiver to receive the respective assembly-level test data associated with each of the first plurality of end products and the respective assembly-level test data associated with each of the second plurality of end products. 3. The device of claim 2, wherein the transceiver communicates with a plurality of testers to receive the respective assembly-level test data associated with each of the first plurality of end products and the respective assembly-level test data associated with each of the second plurality of end products. 4. The device of claim 2, wherein the transceiver further to receive the respective system-level test data associated with each of the first plurality of end products. 5. The device of claim 1, wherein the prediction circuit further to receive telemetry data from a tester, wherein training of the neural network further uses the telemetry data. 6. The device of claim 5, wherein the telemetry data includes environmental data or tester health data. 7. The device of claim 1, wherein, during the second phase, the prediction circuit further to: receive respective assembly-level test data and respective system-level verification test data associated with each of a third plurality of end products, the third plurality of end products produced from the plurality of production units; and further train the neural network using the respective assembly-level test data and the system-level verification test data associated with each of the third plurality of end products. 8. The device of claim 1, wherein the plurality of training units and the plurality of production units are divided from a common supply. 9. The device of claim 1, wherein the plurality of production units includes semiconductor wafers and the second plurality of end products includes semiconductor dice. 10. A device to perform system-level verification predictions comprising: a neural network circuit including a neural network, wherein, during a first phase, the neural network circuit to train the neural network using respective assembly-level test data and the system-level verification test data associated with each of a first plurality of semiconductor dice, the first plurality of semiconductor dice produced from a plurality of training wafers, wherein, during a second phase, the neural network circuit to determine, using the neural network, a system-level pass/fail decision for each of second plurality of semiconductor dice based on respective assembly-level test data associated with each of the second plurality of semiconductor dice, the second plurality of semiconductor dice produced from a plurality of production wafers. 11. The device of claim 10, wherein, during the second phase, the neural network circuit further to train the neural network using the respective assembly-level test data and the system-level verification test data associated with each of a third plurality of semiconductor dice, the third plurality of semiconductor dice produced from each of the plurality of production wafers. 12. The device of claim 11, wherein the third plurality of semiconductor dice are produced from specified locations on each of the plurality of production wafers 13. The device of claim 10, wherein the plurality of training wafers and the plurality of production wafers are sliced from a common ingot of semiconductor material. 14. The device of claim 10, wherein assembly-level test data associated with each of a first plurality of semiconductor dice includes wafer-level test data and semiconductor-die level test data. 15. The device of claim 10, wherein assembly-level test data includes leakage current, transistor drive strengths, device capacitances, transistor performance, metal resistance, interconnect capacitance, optical images, or combinations thereof. 16. At least one machine-readable medium including instructions that, when executed on a machine cause the machine to perform operations including: during a first phase: receive respective assembly-level test data and respective system-level verification test data associated with each of a first plurality of end products, the first plurality of end products produced from a plurality of training units; and train a neural network of a prediction circuit using the respective assembly-level test data and the system-level verification test data associated with each of the first plurality of end products; and during a second phase: receive respective assembly-level test data associated with each of a second plurality of end products, the second plurality of end products produced from a plurality of production units; and determine, using the neural network, a system-level pass/fail decision for each of the second plurality of end products based on the respective assembly-level test data. 17. The machine-readable medium of claim 16, including instructions that, when executed on the machine, cause the machine to perform operations including communicating with a plurality of testers to receive the respective assembly-level test data associated with each of the first plurality of end products and the respective assembly-level test data associated with each of the second plurality of end products. 18. The machine-readable medium of claim 17, including instructions that, when executed on the machine, cause the machine to perform operations including receiving telemetry data from a tester, wherein training of the neural network further uses the telemetry data. 19. The machine-readable medium of claim 18 wherein the telemetry data includes environmental data or tester health data. 20. The machine-readable medium of claim 16, including instructions that, when executed on the machine, cause the machine to perform operations including: receiving respective assembly-level test data and respective system-level verification test data associated with each of a third plurality of end products produced from the plurality of production units; and training the neural network using the respective assembly-level test data and the system-level verification test data associated with each of the third plurality of end products. 21. A method to perform system-level verification predictions comprising: during a first phase, training a neural network of a neural network circuit using respective assembly-level test data and the system-level verification test data associated with each of a first plurality of semiconductor dice produced from a plurality of training wafers; and during a second phase, determining, using the neural network, a system-level pass/fail decision for each of second plurality of semiconductor dice based on respective assembly-level test data associated with each of the second plurality of semiconductor dice, the second plurality of semiconductor dice produced from a plurality of production wafers. The method of claim 21, wherein, during the second phase, training the neural network using the respective assembly-level test data and the system-level verification test data associated with each of a third plurality of semiconductor dice produced from each of the plurality of production wafers. 23. The method of claim 22, wherein the third plurality of semiconductor dice are produced from common specified locations on each of the plurality of production wafers. 24. The method of claim 23, wherein training the neural network using the respective assembly-level test data and the system-level verification test data associated with each of the third plurality of semiconductor dice includes determining inter-wafer correlation. 25. The method of claim 21, wherein the assembly-level test data associated with each of a first plurality of semiconductor dice includes wafer-level test data and semiconductor-die level test data.