A neural network unit including a register programmable with a representation of a reciprocal value of a divisor and a plurality of neural processing units (NPU). Each NPU has an ALU, an accumulator, and a reciprocal multiplier unit. The ALU performs arithmetic and logical operations on a sequence of operands to generate a sequence of results and accumulates the sequence of results as an accumulated value into the accumulator. The reciprocal multiplier unit receives the representation of the reciprocal value and the accumulated value and in response generates a result that is the quotient of the accumulated value and the divisor.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A neural network unit, comprising: a register programmable with a representation of a reciprocal value of a divisor; and a plurality of neural processing units (NPU), each comprising: an arithmetic logic unit (ALU) that performs arithmetic and logical operations on a sequence of operands to generate a sequence of results; an accumulator into which the ALU accumulates the sequence of results as an accumulated value; and a reciprocal multiplier unit that receives the representation of the reciprocal value and the accumulated value and in response generates a result that is the quotient of the accumulated value and the divisor. 2. The neural network unit of claim 1, further comprising: the representation of the reciprocal value programmed into the register comprises a first value that is the reciprocal value of the divisor with leading zeros suppressed, and a second value that specifies a number of leading zeros suppressed in the first value. 3. The neural network unit of claim 2, the reciprocal multiplier unit comprising: a multiplier that multiplies the first value and the accumulated value to generate a product; and a shifter that shifts the product right by the second value to generate the quotient. 4. The neural network unit of claim 2, further comprising: the operations performed by the ALU are integer operations and the accumulated value is a fixed-point value; and a second register programmable with a location of a binary point of the accumulated value accumulated in the accumulator. 5. The neural network unit of claim 2, further comprising: the operations performed by the ALU are integer operations and the operands are fixed-point values; and a second register programmable with a location of a binary point of the operands. 6. The neural network unit of claim 2, further comprising: the operations performed by the ALU are integer operations and the accumulated value is a fixed-point value; and a second register programmable with a location of a binary point of the quotient. 7. The neural network unit of claim 1, further comprising: a first memory that holds elements of a data matrix; a second memory that holds elements of a convolution kernel; and for each NPU of the plurality of NPUs, the accumulated value is a convolution of the convolution kernel and a respective sub-matrix of the elements of the data matrix. 8. The neural network unit of claim 7, further comprising: the divisor is the number of the elements of the convolution kernel. 9. The neural network unit of claim 7, further comprising: the divisor is the sum of the values of the elements of the convolution kernel. 10. The neural network unit of claim 1, further comprising: a first memory that holds elements of a data matrix; and for each NPU of the plurality of NPUs, the accumulated value is a sum of values of elements of a respective sub-matrix of the data matrix. 11. The neural network unit of claim 10, further comprising: the divisor is the number of the elements of the sub-matrix. 12. The neural network unit of claim 1, further comprising: a program memory that stores a program that the neural network unit executes to generate the sequence of results and to accumulate the sequence of results as the accumulated value and to generate the result that is the quotient of the accumulated value and the divisor. 13. A method for operating a neural network unit having a plurality of neural processing units (NPU) each having an arithmetic logic unit (ALU), an accumulator, and a reciprocal multiplier unit, the method comprising: programming a register with a representation of a reciprocal value of a divisor; performing, by each of the ALUs, arithmetic and logical operations on a sequence of operands to generate a sequence of results; accumulating, by each of the ALUs, into the an accumulator the sequence of results as an accumulated value; and receiving, by the reciprocal multiplier unit, the representation of the reciprocal value and the accumulated value and in response generating a result that is the quotient of the accumulated value and the divisor. 14. The method of claim 13, further comprising: the representation of the reciprocal value programmed into the register comprises a first value that is the reciprocal value of the divisor with leading zeros suppressed, and a second value that specifies a number of leading zeros suppressed in the first value. 15. The method of claim 14, further comprising: multiplying, by each of the reciprocal multiplier units, the first value and the accumulated value to generate a product; and shifting, by each of the reciprocal multiplier units, the product right by the second value to generate the quotient. 16. The method of claim 14, further comprising: the operations performed by the ALU are integer operations and the accumulated value is a fixed-point value; and programming a second register with a location of a binary point of the accumulated value accumulated in the accumulator. 17. The method of claim 14, further comprising: the operations performed by the ALU are integer operations and the operands are fixed-point values; and programming a second register with a location of a binary point of the operands. 18. The method of claim 14, further comprising: the operations performed by the ALU are integer operations and the accumulated value is a fixed-point value; and programming a second register with a location of a binary point of the quotient. 19. The method of claim 13, further comprising: holding, by a first memory, elements of a data matrix; holding, by a second memory, elements of a convolution kernel; and for each NPU of the plurality of NPUs, the accumulated value is a convolution of the convolution kernel and a respective sub-matrix of the elements of the data matrix. 20. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising: computer usable program code embodied in said medium, for specifying a neural network unit, the computer usable program code comprising: first program code for specifying a register programmable with a representation of a reciprocal value of a divisor; and second program code for specifying a plurality of neural processing units (NPU), each comprising: an arithmetic logic unit (ALU) that performs arithmetic and logical operations on a sequence of operands to generate a sequence of results; an accumulator into which the ALU accumulates the sequence of results as an accumulated value; and a reciprocal multiplier unit that receives the representation of the reciprocal value and the accumulated value and in response generates a result that is the quotient of the accumulated value and the divisor.