A neuromorphic device may include: first to N-th row lines; first to M-th column lines; first to N-th first neuron circuits coupled to the first to N-th row lines, respectively; first to M-th second neuron circuits coupled to the first to M-th column lines, respectively; a plurality of synapses positioned at intersections of the first to N-th row lines and the first to M-th column lines, respectively, each of the plurality of synapses comprising a variable resistance element and a first transistor which are coupled in series, wherein N and M are natural numbers equal to or larger than two; and a t-th gate line to which gates of first transistors coupled to a t-th column line among the first to M-th column lines are coupled, wherein t is a natural number ranging from 1 to M.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A neuromorphic device comprising: first to N-th row lines; first to M-th column lines; first to N-th first neuron circuits coupled to the first to N-th row lines, respectively; first to M-th second neuron circuits coupled to the first to M-th column lines, respectively; a plurality of synapses positioned at intersections of the first to N-th row lines and the first to M-th column lines, respectively, each of the plurality of synapses comprising a variable resistance element and a first transistor which are coupled in series, wherein N and M are natural numbers equal to or larger than two; and a t-th gate line to which gates of first transistors coupled to a t-th column line among the first to M-th column lines are coupled, wherein t is a natural number ranging from 1 to M. 2. The neuromorphic device of claim 1, wherein when the t-th column line is a column line having learned specific data, the t-th gate line is driven to turn off the first transistors coupled to the t-th column line during a learning operation of a u-th column line, wherein u is a natural number ranging from 1 to M and is not equal to t. 3. The neuromorphic device of claim 2, wherein during the learning process of the u-th column line, the t-th column line is in a floating state. 4. The neuromorphic device of claim 2, wherein during the learning process of the u-th column line, a u-th gate line is driven to turn on first transistors coupled to the u-th column line. 5. The neuromorphic device of claim 1, wherein the t-th gate line has the same extension direction as the t-th column line. 6. The neuromorphic device of claim 5, further comprising a gate control circuit coupled to the t-th gate line, wherein a t-th second neuron circuit coupled to the t-th column line and the gate control circuit coupled to the t-th gate line are positioned in opposite sides with respect to the plurality of synapses in the extension direction of the t-th column line. 7. The neuromorphic device of claim 1, wherein the variable resistance element has electrical conductance which gradually changes according to electrical pulses inputted to the first to the N-th row lines, respectively. 8. The neuromorphic device of claim 1, wherein the variable resistance element exhibits an analog behavior according to electrical pulses inputted to the first to N-th row lines, respectively. 9. The neuromorphic device of claim 1, wherein each of the plurality of synapses further comprises a second transistor that is coupled to and disposed between the variable resistance element and the first transistor. 10. The neuromorphic device of claim 9, wherein relative positions of the variable resistance element, the first transistor, and the second transistor are variable. 11. The neuromorphic device of claim 9, further comprising an s-th gate line to which gates of second transistors coupled to an s-th row line among the first to N-th row lines are coupled, wherein s is a natural number ranging from 1 to N. 12. The neuromorphic device of claim 11, wherein the s-th gate line has the same extension direction as the s-th row line. 13. The neuromorphic device of claim 12, further comprising a gate control circuit coupled to the s-th gate line, wherein an s-th first neuron circuit coupled to the s-th row line and the gate control circuit coupled to the s-th gate line are positioned in opposite sides with respect to the plurality of synapses in the extension direction of the s-th row line. 14. A synapse comprising: a first transistor; and a variable resistance element coupled in series to the first transistor, wherein the first transistor is turned on during a learning operation, and turned off when the learning operation ends. 15. The synapse of claim 14, further comprising: a second transistor coupled to and disposed between the first transistor and the variable resistance element, wherein the first transistor is used to control a leakage current on a first set of row and column bases, and the second transistor is used to control a leakage current on a second set of the row and column bases.