A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A method comprising: interconnecting a plurality of neurons via a plurality of synapses; and for a synapse of the plurality of synapses: maintaining a set of bits representing a corresponding multi-bit fine-grain synaptic weight for the synapse; and updating the corresponding multi-bit fine-grain synaptic weight for the synapse based on a learning rule. 2. The method of claim 1, wherein, for a synapse of the plurality of synapses, a corresponding multi-bit fine-grain synaptic weight for the synapse provides noise tolerance. 3. The method of claim 1, further comprising: for a synapse of the plurality of synapses: reading a corresponding multi-bit fine-grain synaptic weight for the synapse; modifying the corresponding multi-bit fine-grain synaptic weight for the synapse based on a decay counter value of an interconnected neuron, wherein the decay counter value decays at a pre-specified decay rate for the neuron during each time step; and writing the modified corresponding multi-bit fine-grain synaptic weight for the synapse. 4. The method of claim 1, wherein, for a synapse of the plurality of synapses, a set of bits maintained by the synapse comprises m bits. 5. The method of claim 4, wherein, for a synapse of the plurality of synapses, a corresponding multi-bit fine-grain synaptic weight for the synapse is a value in a range from 0 to 2m−1. 6. The method of claim 4, wherein, for a synapse of the plurality of synapses, the synapse has m pairs of bit lines, and an updated corresponding multi-bit fine-grain synaptic weight for the synapse is written at once utilizing only one word line. 7. A system comprising a computer processor, a computer-readable hardware storage medium, and program code embodied with the computer-readable hardware storage medium for execution by the computer processor to implement a method comprising: interconnecting a plurality of neurons via a plurality of synapses; and for a synapse of the plurality of synapses: maintaining a set of bits representing a corresponding multi-bit fine-grain synaptic weight for the synapse; and updating the corresponding multi-bit fine-grain synaptic weight for the synapse based on a learning rule. 8. The system of claim 7, wherein, for a synapse of the plurality of synapses, a corresponding multi-bit fine-grain synaptic weight for the synapse provides noise tolerance. 9. The system of claim 7, the method further comprising: for a synapse of the plurality of synapses: reading a corresponding multi-bit fine-grain synaptic weight for the synapse; modifying the corresponding multi-bit fine-grain synaptic weight for the synapse based on a decay counter value of an interconnected neuron, wherein the decay counter value decays at a pre-specified decay rate for the neuron during each time step; and writing the modified corresponding multi-bit fine-grain synaptic weight for the synapse. 10. The system of claim 7, wherein, for a synapse of the plurality of synapses, a set of bits maintained by the synapse comprises m bits. 11. The system of claim 10, wherein, for a synapse of the plurality of synapses, a corresponding multi-bit fine-grain synaptic weight for the synapse is a value in a range from 0 to 2m−1. 12. The system of claim 10, wherein, for a synapse of the plurality of synapses, the synapse has m pairs of bit lines, and an updated corresponding multi-bit fine-grain synaptic weight for the synapse is written at once utilizing only one word line. 13. A computer program product comprising a computer-readable hardware storage medium having program code embodied therewith, the program code being executable by a computer to implement a method comprising: interconnecting a plurality of neurons via a plurality of synapses; and for a synapse of the plurality of synapses: maintaining a set of bits representing a corresponding multi-bit fine-grain synaptic weight for the synapse; and updating the corresponding multi-bit fine-grain synaptic weight for the synapse based on a learning rule. 14. The computer program product of claim 13, wherein, for a synapse of the plurality of synapses, a corresponding multi-bit fine-grain synaptic weight for the synapse provides noise tolerance. 15. The computer program product of claim 13, the method further comprising: for a synapse of the plurality of synapses: reading a corresponding multi-bit fine-grain synaptic weight for the synapse; modifying the corresponding multi-bit fine-grain synaptic weight for the synapse based on a decay counter value of an interconnected neuron, wherein the decay counter value decays at a pre-specified decay rate for the neuron during each time step; and writing the modified corresponding multi-bit fine-grain synaptic weight for the synapse. 16. The computer program product of claim 13, wherein, for a synapse of the plurality of synapses, a set of bits maintained by the synapse comprises m bits. 17. The computer program product of claim 16, wherein, for a synapse of the plurality of synapses, a corresponding multi-bit fine-grain synaptic weight for the synapse is a value in a range from 0 to 2m−1. 18. The computer program product of claim 16, wherein, for a synapse of the plurality of synapses, the synapse has m pairs of bit lines, and an updated corresponding multi-bit fine-grain synaptic weight for the synapse is written at once utilizing only one word line.