The device for processing data comprises a set of processing nodes and connections between the nodes. Each connection is configured to transmit, to a receiver node, events delivered by an emitter node. Each node is arranged to vary a respective potential value according to events that it receives and to deliver an event when the potential value reaches a predefined threshold. At least one input value of the data processing device is represented by a time interval between two events received by at least one node, and at least one output value of the data processing device is represented by a time interval between two events delivered by at least one node.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A data processing device, comprising a set of processing nodes and connections between the nodes, wherein each connection has an emitter node and a receiver node out of the set of processing nodes and is configured to transmit, to the receiver node, events delivered by the emitter node, wherein each node is arranged to vary a respective potential value-M according to events received by said node and to deliver an event when the potential value reaches a predefined threshold, wherein at least one input value of the data processing device is represented by a time interval between two events received by at least one node, and wherein at least one output value of the data processing device is represented by a time interval between two events delivered by at least one node. 2. The device of claim 1, wherein each processing node is arranged to reset its potential value when delivering an event. 3. The device of claim 1, wherein the connections between the nodes comprise potential variation connections, each having a respective weight, and wherein the receiver node of a potential variation connection is arranged to respond to an event received on said potential variation connection by adding, to its potential value, the weight of said potential variation connection. 4. The device of claim 3, wherein the set of processing nodes comprises at least one first node forming the receiver node of a first potential variation connection having a first positive weight at least equal to the predefined threshold for the potential value, and at least one second node forming the receiver node of a second potential variation connection having a weight at least equal to half the predefined threshold for the potential value and less than the predefined threshold for the potential value, wherein the first node further forms the emitter node and the receiver node of a third potential variation connection having a weight equal to the opposite of the first weight, wherein the first node further forms the emitter node of a fourth connection and the second node further forms the emitter node of a fifth connection, and wherein the first and second potential variation connections are configured to each receive two events separated by a first time interval representing an input value, whereby the fourth and fifth connections transport respective events having between them a second time interval related to the first time interval. 5. The device of claim 3, comprising at least one minimum calculation circuit, wherein the minimum calculation circuit comprises: first and second input nodes; an output node; first and second selection nodes; first, second, third, fourth, fifth and sixth potential variation connections each having a first positive weight at least equal to half the predefined threshold for the potential value and less than the predefined threshold for the potential value; seventh and eighth potential variation connections each having a second weight opposite to the first weight; and ninth and tenth potential variation connections each having a third weight double of the second weight, wherein the first input node forms the emitter node of the first and third connections and the receiver node of the tenth connection, wherein the second input node forms the emitter node of the second and fourth connections and the receiver node of the ninth connection, wherein the first selection node forms the emitter node of the fifth, seventh and ninth connections and the receiver node of the first and eighth connections, wherein the second selection node forms the emitter node of the sixth, eighth and tenth connections and the receiver node of the second and seventh connections, and wherein the output node forms the receiver node of the third, fourth, fifth and sixth connections. 6. The device of claim 3, comprising at least one maximum calculation circuit, wherein the maximum calculation circuit comprises: first and second input nodes; an output node; first and second selection nodes; first, second, third and fourth potential variation connections each having a first positive weight at least equal to half the predefined threshold for the potential value and less than the predefined threshold for the potential value; and fifth and sixth potential variation connections each having a second weight equal to double of the opposite of the first weight, wherein the first input node forms the emitter node of the first and third connections, wherein the second input node forms the emitter node of the second and fourth connections, wherein the first selection node forms the emitter node of the fifth connection and the receiver node of the first and sixth connections, wherein the second selection node forms the emitter node of the sixth connection and the receiver node of the second and fifth connections, and wherein the output node forms the receiver node of the third and fourth connections. 7. The device of claim 3, comprising at least one subtractor circuit, wherein the subtractor circuit comprises: first and second synchronisation nodes; first and second inhibition nodes; first and second output nodes; first, second, third, fourth, fifth and sixth potential variation connections each having a first positive weight at least equal to the predefined threshold for the potential value; seventh and eighth potential variation connections each having a second weight equal to half the first weight; ninth and tenth potential variation connections each having a third weight opposite to the first weight; and eleventh and twelfth potential variation connections each having a fourth weight double the third weight, wherein the first synchronisation node forms the emitter node of the first, second, third and ninth connections, wherein the second synchronisation node forms the emitter node of the fourth, fifth, sixth and tenth connections, wherein the first inhibition node forms the emitter node of the eleventh connection and the receiver node of the third, eighth and tenth connections, wherein the second inhibition node forms the emitter node of the twelfth connection and the receiver node of the sixth, seventh and ninth connections, wherein the first output node form the emitter node of the seventh connection and the receiver node of the first, fifth and eleventh connections, wherein the second output node forms the emitter node of the eighth connection and the receiver node of the second, fourth and twelfth connections, and wherein the first synchronisation node is configured to receive, on at least one potential variation connection having the second weight, a first pair of events having between them a first time interval representing a first operand, and the second synchronisation node is configured to receive, on at least one potential variation connection having the second weight, a second pair of events having between them a second time interval representing a second operand, whereby a third pair of events having between them a third time interval is delivered by the first output node if the first time interval is longer than the second time interval and by the second output node if the first time interval is shorter than the second time interval, the third time interval representing the absolute value of the difference between the first and second operand. 8. The device of claim 7, wherein the subtractor circuit further comprises zero detection logic including at least one detection node associated with detection and inhibition connections with the first and second synchronisation node, one of the first and second inhibition node and one of the first and second output node, and wherein the detection and inhibition connections are faster than the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh and twelfth connections, in order to inhibit the production of events by one of the first and second output node when the first and second time intervals are substantially equal. 9. The device of claim 3, wherein the set of processing nodes comprises at least one node arranged to vary a current value according to events received on at least one current adjustment connection, and to vary its potential value over time at a rate proportional to said current value. 10. The device of claim 9, wherein a processing node arranged to vary a current value is arranged to reset said current value to zero when it delivers an event. 11. The device of claim 9, wherein the current value in at least one node has a component that is constant between two events received on at least one constant current component adjustment connection having a respective weight, and wherein the receiver node of a constant current component adjustment connection is arranged to respond to an event received on said connection by adding the weight of said connection to the constant component of its current value. 12. The device of claim 11, comprising at least one inverter memory circuit, wherein the inverter memory circuit comprises: an accumulator node; first, second and third constant current component adjustment connections, the first and third connections having a same positive weight and the second connection having a weight opposite to the weight of the first and third connections; and at least one fourth connection, wherein the accumulator node forms the receiver node of the first, second and third connections and the emitter node of the fourth connection, and wherein the first and second connections are configured to respectively address to the accumulator node first and second events having between them a first time interval related to a time interval representing a value to be memorised, whereby the accumulator node then reacts to a third event received on the third connection by increasing its potential value until delivery of a fourth event on the fourth connection, the third and fourth events having between them a second time interval related to the first time interval. 13. The device of claim 12, comprising at least one memory circuit, wherein the memory circuit comprises: first and second accumulator nodes; first, second, third and fourth constant current component adjustment connections, the first, second and fourth connections each having a first positive weight and the third connection having a weight opposite to the weight of the first, second and fourth connections; and at least one fifth connection, wherein the first accumulator node forms the receiver node of the first connection and the emitter node of the third connection, wherein the second accumulator node forms the receiver node of the second, third and fourth and fifth connections and the emitter node of the fifth connection, and wherein the first and second connections are configured to address, to the first and second accumulator nodes, respectively, first and second events having between them a first time interval related to a time interval representing a value to be memorised, whereby the second accumulator node then responds to a third event received on the fourth connection by increasing its potential value until delivery of a fourth event on the fifth connection, the third and fourth events having between them a second time interval related to the first time interval. 14. The device of claim 13, wherein the memory circuit comprises a sixth connection having the first accumulator node as an emitter node, the sixth connection delivering an event to signal the availability of the memory circuit for reading. 15. The device of claim 14, comprising at least one synchronisation circuit, which includes a number N>1 of memory circuits and a synchronisation node, wherein the synchronisation node is sensitive to each event delivered on the sixth connection of one of the N memory circuits via a respective potential variation connection having a weight equal to the first weight divided by N, and wherein the synchronisation node is arranged to trigger simultaneous reception of the third events via the respective fourth connections of the N memory circuits. 16. The device of claim 11, comprising at least one accumulation circuit, wherein the accumulation circuit comprises: N inputs each having a respective weighting coefficient, N being a integer greater than 1; an accumulator node; a synchronisation node; for each of the N inputs of the accumulation circuit: a first constant current component adjustment connection having a first positive weight proportional to the respective weighting coefficient of said input; and a second constant current component adjustment connection having a second weight opposite to the first weight; and a third constant current component adjustment connection having a third positive weight, wherein the accumulator node forms the receiver node of the first, second and third connections, wherein the synchronization node forms the emitter node of the third connection, wherein, for each of the N inputs, the first and second connections are configured to respectively address, to the accumulator node, first and second events having between them a first time interval representing a respective operand provided on said input, wherein the synchronisation node is configured to deliver a third event once the first and second events have been addressed for each of the N inputs, whereby the accumulator node increases its potential value until delivery of a fourth event, the third and fourth event having between them a second time interval related to a time interval representing a weighted sum of the operands provided on the N inputs. 17. The device of claim 16, wherein the accumulation circuit is part of a weighted addition circuit further comprising: a second accumulator node; a fourth constant current component adjustment connection having the third weight; and a fifth and sixth connection, wherein the synchronisation node of the accumulation circuit forms the emitter node of the fourth connection, wherein the accumulator node of the accumulation circuit forms the emitter node of the fifth connection, wherein the second accumulator node forms the receiver node of the fourth connection and the emitter node of the sixth connection, wherein, in response to delivery of the third event by the synchronisation node, the accumulator node of the accumulation circuit increases its potential value until delivery of a fourth event on the fifth connection, and the second accumulator node increases its potential value until delivery of a fifth event on the sixth connection, the fourth and fifth events having between them a third time interval related to a time interval representing a weighted sum of the operands provided on the N inputs of the accumulation circuit. 18. The device of claim 16, comprising two accumulation circuits assembled in a linear combination circuit, wherein the two accumulation circuits share their synchronisation node, wherein the linear combination circuit further comprises a subtractor circuit configured to react to the third event delivered by the shared synchronisation node and to the fourth events respectively delivered by the accumulator nodes of the two accumulation circuits by delivering a pair of events having between them a third time interval representing the difference between the weighted sum for one of the two accumulation circuits and the weighted sum for the other of the two accumulation circuits. 19. The device of claim 11, wherein the current value in at least one node has a component that decreases exponentially between two events received on at least one exponentially decreasing current component adjustment connection having a respective weight, and wherein the receiver node of an exponentially decreasing current component adjustment connection is arranged to respond to an event received on said connection by adding the weight of said connection to the exponentially decreasing component of its current value. 20. The device of claim 19, comprising at least one logarithm calculation circuit, wherein the logarithm calculation circuit comprises: an accumulator node; a first and a second constant current component adjustment connections, the first connection having a positive weight, and the second connection having a weight opposite to the weight of the first connection; a third exponentially decreasing current component adjustment connection; and at least one fourth connection, wherein the accumulator node forms the receiver node of the first, second and third connections and the emitter node of the fourth connection, wherein the first and second connections are configured to address, to the accumulator node, respective first and second events having between them a first time interval related to a time interval representing an input value of the logarithm calculation circuit, wherein the third connection is configured to address, to the accumulator node, a third event simultaneous or posterior to the second event, whereby the accumulator node increases its potential value until delivery of a fourth event on the fourth connection, the third and fourth events having between them a second time interval related to a time interval representing a logarithm of said input value. 21. The device of claim 19, wherein at least one node taking into account an exponentially decreasing current component is the receiver node of a deactivation connection in order to receive events for deactivation of the exponentially decreasing component. 22. The device of claim 21, comprising at least one exponentiation circuit, wherein the exponentiation circuit comprises: an accumulator node; a first exponentially decreasing current component adjustment connection; a second deactivation connection; a third constant current component adjustment connection; and at least one fourth connection, wherein the accumulator node forms the receiver node of the first, second and third connections and the emitter node of the fourth connection, wherein the first and second connections are configured to address, to the accumulator node, respective first and second event having between them a first time interval related to a time interval representing an input value of the exponentiation circuit, wherein the third connection is configured to address, to the accumulator node, a third event simultaneous or posterior to the second event, whereby the accumulator node increases its potential value until delivery of a fourth event on the fourth connection, the third and fourth events having between them a second time interval related to a time interval representing an exponentiation of said input value. 23. The device of claim 21, comprising at least one multiplier circuit, wherein the multiplier circuit comprises: first, second and third accumulator nodes; a synchronisation node; first, second, third, fourth and fifth constant current component adjustment connections, the first, third and fifth connections having a first positive weight, and the second and fourth connections having a second weight opposite to the first weight; sixth, seventh and eighth exponentially decreasing current component adjustment connections; a ninth deactivation connection; and at least one tenth connection, wherein the first accumulator node forms the receiver node of the first, second and sixth connections and the emitter node of the seventh connection, wherein the second accumulator node forms the receiver node of the third, fourth and seventh connections and the emitter node of the fifth and ninth connections, wherein the third accumulator node forms the receiver node of the fifth, eighth and ninth connections and the emitter node of the tenth connection, wherein the synchronisation node forms the emitter node of the sixth and eighth connections, wherein the first and second connections are configured to address, to the first accumulator node, respective first and second event having between them a first time interval related to a time interval representing a first operand of the multiplier circuit, wherein the third and fourth connections are configured to address, to the second accumulator node, respective third and fourth events having between them a second time interval related to a time interval representing a second operand of the multiplier circuit, wherein the synchronisation node is configured to deliver a fifth event on the sixth and eighth connections once the first, second, third and fourth events have been received, whereby: the first accumulator node increases its potential value until delivery of a sixth event on the seventh connection; in response to the sixth event, the second accumulator node increases its potential value until delivery of a seventh event on the fifth and ninth connections; in response to the seventh event, the third accumulator node increases its potential value until delivery of an eighth event on the tenth connection, the seventh and eighth events having between them a third time interval related to a time interval representing the product of the first and second operands. 24. The device of claim 23, further comprising sign detection logic associated with the multiplier circuit in order to detect respective signs of the first and second operand and cause two events having between them a time interval representing the product of the first and second operands to be delivered on one or the other of two outputs of the multiplier circuit according to the detected signs. 25. The device of claim 1, wherein each connection is associated with a delay parameter, in order to signal the receiver node of said connection to carry out a change of state with a delay, with respect to reception of an event on the connection, indicated by said parameter. 26. The device of claim 1, wherein the time interval Δt between two events representing a value having an absolute value x is in the form Δt=Tmin+x·Tcod, where Tmin and Tcod are predefined time parameters. 27. The device of claim 26, wherein the values represented by time intervals have absolute values x between 0 and 1. 28. The device of claim 1, comprising, for an input value: a first input comprising one node or two nodes out of the set of processing nodes, the first input being arranged to receive two events having between them a time interval representing a positive value of said input value; and a second input comprising one node or two nodes out of the set of processing nodes, the second input being arranged to receive two events having between them a time interval representing a negative value of said input value. 29. The device of claim 1, comprising, for an output value: a first output comprising one node or two nodes out of the set of processing nodes, the first output being arranged to deliver two events having between them a time interval representing a positive value of said output value; and a second output comprising one node or two nodes out of the set of processing nodes, the second output being arranged to deliver two events having between them a time interval representing a negative value of said output value. 30. The device of claim 1, wherein the set of processing nodes is in the form of at least one programmable array, the nodes of the array having a shared behavior model according to the events received, the device further comprising a programming logic in order to adjust weights and delay parameters of the connections between the nodes of the array according to a calculation program, and a control unit in order to provide input values to the array and recover output values calculated according to the program.