A neural network unit includes a register programmable with a control value, a plurality of neural processing units (NPU), and a plurality of activation function units (AFU). Each NPU includes an arithmetic logic unit (ALU) that performs arithmetic and logical operations on a sequence of operands to generate a sequence of results and an accumulator into which the ALU accumulates the sequence of results as an accumulated value. Each AFU includes a first module that performs a first function on the accumulated value to generate a first output, a second module that performs a second function on the accumulated value to generate a second output, the first function is distinct from the second function, and a multiplexer that receives the first and second outputs and selects one of the two outputs based on the control value programmed into the register.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A neural network unit, comprising: a register programmable with a control value; a plurality of neural processing units (NPU), each comprising: an arithmetic logic unit (ALU) that performs arithmetic and logical operations on a sequence of operands to generate a sequence of results; and an accumulator into which the ALU accumulates the sequence of results as an accumulated value; and a plurality of activation function units (AFU), each comprising: a first module that performs a first function on the accumulated value to generate a first output; a second module that performs a second function on the accumulated value to generate a second output, the first function is distinct from the second function; and a multiplexer that receives the first and second outputs and selects one of the two outputs based on the control value programmed into the register. 2. The neural network unit of claim 1, further comprising: the first function operates to non-linearly normalize the accumulated value to generate the first output within a first expected range; and the second function operates to non-linearly normalize the accumulated value to generate the second output within a second expected range. 3. The neural network unit of claim 1, further comprising: the first function operates to non-linearly normalize the accumulated value to generate the first output within a first expected range; and the second function operates to effectively divide the accumulated value by a divisor. 4. The neural network unit of claim 3, further comprising: a second programmable register that holds a reciprocal of the divisor; and the second module comprises a multiplier that multiplies the reciprocal of the divisor by the accumulated value to generate the second output. 5. The neural network unit of claim 3, further comprising: a second programmable register that holds a second control value that specifies a shift amount; and the second module comprises a shifter that shifts the accumulated value by the shift amount to generate the second output. 6. The neural network unit of claim 1, further comprising: the multiplexer also receives the accumulated value and selects one of: the two outputs and multiple portions of the accumulated value. 7. The neural network unit of claim 6, further comprising: a second programmable register that holds a second control value that specifies a size, in bits, of the operands; the specified size of the operands is less than a size, in bits, of the accumulated value; and the multiple portions of the accumulated value are the specified size of the operands. 8. The neural network unit of claim 7, further comprising: a compressor that compresses the accumulated value to a canonical size value that is twice the specified operand size; and the multiple portions of the accumulated value are the two portions of the canonical size value. 9. The neural network unit of claim 1, further comprising: the first and second functions are two functions from the following list: a hyperbolic tangent function, a sigmoid function, a softplus function and a rectify function. 10. The neural network unit of claim 1, further comprising: a first memory for storing a portion of the operands; a second memory for storing a portion of the operands; a second programmable register that holds a second control value that specifies one of the first and second memories; and the neural network unit writes the selected one of the two outputs to the one of the first and second memories specified by the second control value. 11. A method for operating a neural network unit having a plurality of neural processing units (NPU) and a plurality of activation function units (AFU), the method comprising: programming a register with a control value; by each of the plurality of NPUs: performing, by an arithmetic logic unit (ALU), arithmetic and logical operations on a sequence of operands to generate a sequence of results; and accumulating into an accumulator the sequence of results as an accumulated value; and by each of the plurality of AFUs: performing, by a first module, a first function on the accumulated value to generate a first output; performing, by a second module, a second function on the accumulated value to generate a second output, the first function is distinct from the second function; and selecting one of the first and second outputs based on the control value programmed into the register. 12. The method of claim 11, further comprising: the first function operates to non-linearly normalize the accumulated value to generate the first output within a first expected range; and the second function operates to non-linearly normalize the accumulated value to generate the second output within a second expected range. 13. The method of claim 11, further comprising: the first function operates to non-linearly normalize the accumulated value to generate the first output within a first expected range; and the second function operates to effectively divide the accumulated value by a divisor. 14. The method of claim 13, further comprising: programming a second register with a reciprocal of the divisor; and multiplying, by the second module, the reciprocal of the divisor by the accumulated value to generate the second output. 15. The method of claim 13, further comprising: programming a second register with a second control value that specifies a shift amount; and shifting, by the second module, the accumulated value by the shift amount to generate the second output. 16. The method of claim 11, further comprising: receiving the accumulated value and selecting one of: the two outputs and multiple portions of the accumulated value. 17. The method of claim 16, further comprising: programming a second register with a second control value that specifies a size, in bits, of the operands; the specified size of the operands is less than a size, in bits, of the accumulated value; and the multiple portions of the accumulated value are the specified size of the operands. 18. The method of claim 17, further comprising: compressing the accumulated value to a canonical size value that is twice the specified operand size; and the multiple portions of the accumulated value are the two portions of the canonical size value. 19. The method of claim 11, further comprising: the first and second functions are two functions from the following list: a hyperbolic tangent function, a sigmoid function, a softplus function and a rectify function. 20. The method of claim 11, further comprising: storing in a first memory a portion of the operands; storing in a second memory a portion of the operands; programming a second register with a second control value that specifies one of the first and second memories; and writing the selected one of the two outputs to the one of the first and second memories specified by the second control value. 21. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising: computer usable program code embodied in said medium, for specifying a neural network unit, the computer usable program code comprising: first program code for specifying a register programmable with a control value; second program code for specifying a plurality of neural processing units (NPU), each comprising: an arithmetic logic unit (ALU) that performs arithmetic and logical operations on a sequence of operands to generate a sequence of results; and an accumulator into which the ALU accumulates the sequence of results as an accumulated value; and third program code for specifying a plurality of activation function units (AFU), each comprising: a first module that performs a first function on the accumulated value to generate a first output; a second module that performs a second function on the accumulated value to generate a second output, the first function is distinct from the second function; and a multiplexer that receives the first and second outputs and selects one of the two outputs based on the control value programmed into the register.