An architecture and associated techniques of an apparatus for hardware accelerated machine learning are disclosed. The architecture features multiple memory banks storing tensor data. The tensor data may be concurrently fetched by a number of execution units working in parallel. Each operational unit supports an instruction set specific to certain primitive operations for machine learning. An instruction decoder is employed to decode a machine learning instruction and reveal one or more of the primitive operations to be performed by the execution units, as well as the memory addresses of the operands of the primitive operations as stored in the memory banks. The primitive operations, upon performed or executed by the execution units, may generate some output that can be saved into the memory banks. The fetching of the operands and the saving of the output may involve permutation and duplication of the data elements involved.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. An execution unit of hardware acceleration for machine learning, the execution unit running on a clock and configured to execute one instruction of an instruction set per clock cycle of the clock, the execution unit comprising: a clock input receiving the clock; an operation specification input receiving an opcode specifying the one instruction; a first operand input receiving a first operand; a second operand input receiving a second operand; an accumulation register storing a current accumulation value; and an output, wherein: the accumulation register is updated, within the clock cycle, with a new accumulation value based on the opcode and one or more of the first operand, the second operand and the current accumulation value, and the output comprises saturated lower bits of the new value. 2. The execution unit of claim 1, further comprising: a random number register storing a current random number, wherein the one instruction comprises a seed random number generator operation, and wherein the random number register is updated, within the clock cycle, with a new random number based on the first operand, the second operand and the current random number. 3. The execution unit of claim 1, further comprising: a conditional execution input receiving a conditional execution, wherein the one instruction is executed or skipped as determined by the conditional execution. 4. The execution unit of claim 3, further comprising: a conditional set mask receiving a conditional set mask; a conditional reset mask receiving a conditional reset mask; and a status register, wherein, when the one instruction is executed as determined by the conditional execution, bits of the status register are updated, within the clock cycle, based on corresponding bits of the conditional set mask and corresponding bits of the conditional reset mask. 5. The execution unit of claim 4, wherein the one instruction comprises a compare operation, and wherein bits of the status register are updated only when the compare operation returns a true result. 6. An indexing module for looping over a plurality of indexes each corresponding to one of multiple dimensions of a tensor, the indexing module comprising: a counter unit comprising: a plurality of counter registers each storing a respective one of the plurality of indexes; and a plurality of size registers each corresponding to one of the counter registers; and an address unit, wherein: the counter unit updates the plurality of indexes stored in the counter registers by repeating a method to loop over the plurality of indexes, and the address unit generates, for each of the indexes stored in the counter registers, an address that is a polynomial of the respective index. 7. The indexing module of claim 6, wherein the address unit further generates a quotient and a reminder of the address by dividing the address with a fixed modulus. 8. The indexing module of claim 7, wherein the address unit receives, for each of the indexes stored in the counter registers, a delta comprising a quotient delta and a reminder delta with respective to the fixed modulus, and wherein the address unit updates of the address by adding the quotient delta to the quotient of the address and the reminder delta to the reminder of the address. 9. The indexing module of claim 6, wherein: the indexing module is driven by a clock, the counter unit further comprises an OVER register and a NEXT register, and the method comprising: resetting the counter registers and the size registers to 0; setting the OVER register to 1 and the NEXT register to 0; configuring the counter registers with a configuration input; configuring the size registers with the configuration input; setting the OVER register to 0 if any counter register contains a non-zero value; updating the NEXT register based on a counter register of a highest sequence of the counter registers that contains a non-zero value; decrementing the non-zero value of the counter register by 1 and updating counter registers having a higher sequence than specified by the NEXT register with the corresponding size registers; and repeating the updating the NEXT register, the decrementing the non-zero value and the updating the counter registers until each of the counter registers contains 0. 10. A permutation network for transferring data elements between a vector of logical addresses and multiple banks of random access memory (RAM), the permutation network comprising: a first wiring pattern configured to map a logical space to a cyclic space; a first barrel shifter; a second wiring pattern configured to map the cyclic space to the logical space; and a second barrel shifter, wherein: a quantity number of the data elements is less than or equal to a quantity number of the banks of RAM, the vector of logical addresses is represented by an address offset and a multiplier, the multiplier is relatively prime to the quantity number of the banks of RAM, the first barrel shifter rotates the data elements in the cyclic space based on the multiplier, and the second barrel shifter rotates the data elements in the logical space based on the address offset. 11. The permutation network of claim 10, performing on the data elements addressed by the vector of logical addresses a forward modulo permutation suitable for saving the data elements to the banks of RAM, via: mapping, by the first wiring pattern, the vector of logical addresses to the cyclic space; rotating right, by the first barrel shifter, the data elements in the cyclic space based on the multiplier; mapping, by the second wiring pattern, the data elements after the rotating right by the first barrel shifter to the logical space; and rotating right, by the second barrel shifter, the data elements in the logical space based on the address offset. 12. The permutation network of claim 11, further comprising: a reset mechanism for maintaining output bits of the second barrel shifter to be 0 until the permutation network finishes pipelining operations. 13. The permutation network of claim 10, performing on the data elements addressed by the vector of logical addresses a reverse modulo permutation for reordering the data elements read from the banks of RAM, via: rotating left, by the second barrel shifter, the data elements in the logical space based on the address offset; mapping, by the first wiring pattern, the data elements after the rotating left by the second barrel shifter to the cyclic space; rotating left, by the first barrel shifter, the data elements in the cyclic space based on the multiplier; and mapping, by the second wiring pattern, the data elements after the rotating left by the first barrel shifter from the cyclic space to the logical space. 14. The permutation network of claim 13, further comprising: a reset mechanism for maintaining output bits of the second wiring pattern to be 0 until the permutation network finishes pipelining operations. 15. A banked asynchronous memory read unit for reading data from a computer readable memory having a plurality of memory banks, comprising: a modulo address generator configured to generate: a set of per-bank read addresses each addressing respective data to be read from a respective memory bank of the plurality of memory banks; and a set of per-bank enable bits indicating the one or more respective memory banks of the plurality of memory banks; a plurality of memory queues each corresponding to a respective memory bank of the plurality of memory banks, each of the memory queues comprising: an address queue (AQ) configured to receive the read address for the respective memory bank; a memory reader (D) configured to read the data addressed by the read address; and an output data queue (DQ) configured to store the data read by the memory reader; a control queue (CQ) configured to store the set of per-bank enable bits; and a deque logic controller configured to combine the data stored in the data output queues of the plurality of memory queues into complete output data based on the set of per-bank enable bits stored in the control queue. 16. The banked asynchronous memory read unit of claim 15, wherein the data read by the memory reader and subsequently stored in the output data queue is of full bit-width of the respective memory bank. 17. The banked asynchronous memory read unit of claim 15, wherein the deque logic controller combines the data stored in the data output queues that are indicated as enabled by the set of per-bank enable bits and pads bits of 0 in between the data for data output queues that are indicated as disabled by the set of per-bank enable bits. 18. The banked asynchronous memory read unit of claim 15, further comprising: a reverse modulo permutation network, wherein: the control queue is further configured to store a set of per-bank offset moduli, and the reverse modulo permutation network is configured to perform, using the set of per-bank offset moduli, a reverse modulo permutation for the data combined by the deque logic controller to generate the complete output data. 19. A banked asynchronous memory write unit for writing data to a computer readable memory having a plurality of memory banks, comprising: a modulo address generator configured to generate: a set of per-bank write addresses each addressing respective data to be written to a respective memory bank of the plurality of memory banks; and a set of per-bank enable bits indicating the one or more respective memory banks of the plurality of memory banks; a plurality of memory queues each corresponding to a respective memory bank of the plurality of memory banks, each of the memory queues comprising: a write queue (WQ) configured to receive the write address and data to be written according to the write address for the respective memory bank; a memory writer (D) configured to write the data addressed by the write address; and an acknowledgement counter (AC) configured to acknowledge the writing by the memory writer; a control queue (CQ) configured to store the set of per-bank enable bits; and a deque logic controller configured to generate an ACK signal indicating that the data stored in the write queues of the plurality of memory queues have been written to the respective memory banks indicated enable by the set of per-bank enable bits stored in the control queue. 20. The banked asynchronous memory write unit of claim 19, further comprising: a forward modulo permutation network, wherein: the control queue is further configured to store a set of per-bank offset moduli, and the forward modulo permutation network is configured to perform, using the set of per-bank offset moduli, a forward modulo permutation for the data before sending the data to the write queues of the plurality of memory queues.