A multiplexed neural core circuit according to one embodiment comprises, for an integer multiplexing factor T that is greater than zero, T sets of electronic neurons, T sets of electronic axons, where each set of the T sets of electronic axons corresponds to one of the T sets of electronic neurons, and a synaptic interconnection network comprising a plurality of electronic synapses that each interconnect a single electronic axon to a single electronic neuron, where the interconnection network interconnects each set of the T sets of electronic axons to its corresponding set of electronic neurons.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A multiplexed neural core circuit, for an integer multiplexing factor T that is greater than zero, comprising: T sets of electronic neurons; T sets of electronic axons, where each set of the T sets of electronic axons corresponds to one of the T sets of electronic neurons; and a synaptic interconnection network comprising a plurality of electronic synapses that each interconnect a single electronic axon to a single electronic neuron, where the interconnection network interconnects each set of the T sets of electronic axons to its corresponding set of electronic neurons. 2. The multiplexed neural core circuit of claim 1, wherein the synaptic interconnection network is shared across the T sets of electronic neurons. 3. The multiplexed neural core circuit of claim 1, wherein a plurality of neuron parameters is shared across the T sets of electronic neurons. 4. The multiplexed neural core circuit of claim 1, wherein a plurality of neuron destination locations is shared across the T sets of electronic neurons. 5. The multiplexed neural core circuit of claim 1, wherein a neuron state is shared across the T sets of electronic neurons. 6. The multiplexed neural core circuit of claim 1, wherein an operation of the multiplexed neural core circuit is described in terms of a plurality of discrete timesteps, and within a single discrete timestep, each set of the T sets of electronic axons is interconnected with its corresponding set of electronic neurons via the synaptic interconnection network. 7. The multiplexed neural core circuit of claim 6, further comprising: dividing each of the plurality of discrete timesteps into T sub-timesteps, assigning each set of the T sets of electronic axons and its corresponding set of electronic neurons one of the T sub-timesteps, and interconnecting each set of the T sets of electronic axons with its corresponding set of electronic neurons via the synaptic interconnection network within their assigned one of the T sub-timesteps. 8. The multiplexed neural core circuit of claim 1, further comprising two distinct memory banks, the two distinct memory banks including: a first memory bank comprising the synaptic interconnection network, a plurality of neuron parameters, a plurality of neuron destination locations, and a neuron state for all electronic neurons within the T sets of electronic neurons, and a second memory bank comprising an electronic axon buffer memory. 9. The multiplexed neural core circuit of claim 8, further comprising dividing the electronic axon buffer memory into T rows×max(Δ) columns, where max(Δ) is a number of time delays. 10. The multiplexed neural core circuit of claim 8, wherein the first memory bank is implemented utilizing a first memory portion comprising the synaptic interconnection network and a second memory portion comprising the plurality of neuron parameters, the plurality of neuron destination locations, and the neuron state for all electronic neurons within the T sets of electronic neurons, where the first memory portion is different from or the same as the second memory portion. 11. A computer-implemented method for multiplexing a neural core circuit, for an integer multiplexing factor T that is greater than zero, comprising: configuring T sets of electronic neurons; configuring T sets of electronic axons, where each set of the T sets of electronic axons corresponds to one of the T sets of electronic neurons; and configuring an synaptic interconnection network comprising a plurality of electronic synapses that each interconnect a single electronic axon to a single electronic neuron, where the interconnection network interconnects each set of the T sets of electronic axons to its corresponding set of electronic neurons. 12. The computer-implemented method of claim 11, wherein the synaptic interconnection network is shared across the T sets of electronic neurons. 13. The computer-implemented method of claim 11, wherein a plurality of neuron parameters is shared across the T sets of electronic neurons. 14. The computer-implemented method of claim 11, wherein a plurality of neuron destination locations is shared across the T sets of electronic neurons. 15. The computer-implemented method of claim 11, wherein a neuron state is shared across the T sets of electronic neurons. 16. The computer-implemented method of claim 11, wherein an operation of the multiplexed neural core circuit is described in terms of a plurality of discrete timesteps, and within a single discrete timestep, each set of the T sets of electronic axons is interconnected with its corresponding set of electronic neurons via the synaptic interconnection network. 17. The computer-implemented method of claim 16, further comprising: dividing each of the plurality of discrete timesteps into T sub-timesteps, assigning each set of the T sets of electronic axons and its corresponding set of electronic neurons one of the T sub-timesteps, and interconnecting each set of the T sets of electronic axons with its corresponding set of electronic neurons via the synaptic interconnection network within their assigned one of the T sub-timesteps. 18. The computer-implemented method of claim 11, further comprising storing two distinct memory banks, the two distinct memory banks including: a first memory bank comprising the synaptic interconnection network, a plurality of neuron parameters, a plurality of neuron destination locations, and a neuron state for all electronic neurons within the T sets of electronic neurons, and a second memory bank comprising an electronic axon buffer memory. 19. A neurosynaptic system, comprising: a neurosynaptic chip, a single-core neurosynaptic module as a component on a chip, or a multi-core neurosynaptic module as a component on a chip, including a plurality of multiplexed neural core circuits interconnected via an on-chip network, where each of the plurality of multiplexed neural core circuits comprises, for an integer multiplexing factor T that is greater than zero: T sets of electronic neurons, T sets of electronic axons, where each set of the T sets of electronic axons corresponds to one of the T sets of electronic neurons, and a synaptic interconnection network comprising a plurality of electronic synapses that each interconnect a single electronic axon to a single electronic neuron, where the interconnection network interconnects each set of the T sets of electronic axons to its corresponding set of electronic neurons. 20. The neurosynaptic system of claim 19, wherein the neurosynaptic chip, the single-core neurosynaptic module, or the multi-core neurosynaptic module is interconnected via an off-chip network. 21. The neurosynaptic system of claim 19, wherein the on-chip network is event-driven. 22. The neurosynaptic system of claim 19, wherein the off-chip network is event-driven. 23. The neurosynaptic system of claim 19, wherein one or more of the plurality of multiplexed neural core circuits have an integer multiplexing factor different from the other multiplexed neural core circuits of the plurality of multiplexed neural core circuits. 24. The neurosynaptic system of claim 23, wherein a first set of the plurality of multiplexed neural core circuits has a first integer multiplexing factor T1, and the first set connects with a second set of multiplexed neural core circuits that has a second integer multiplexing factor T2 that is different from the first integer multiplexing factor T1. 25. The neurosynaptic system of claim 23, wherein inter-core messages include spike packets that encode a relative address of a destination core, an electronic axon time delay, an address of a set of electronic axons, an axon address, and information that encodes a mapping between the integer multiplexing factor Ts of source cores and the integer multiplexing factor Td of destination cores.