An electronic device includes a memory device storing data and a system-on-a-chip using the memory device as a working memory. The system-on-a-chip performs software training on a second memory area of the memory device by loading a training code to a first memory area of the memory device, and executing the loaded training code.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. An electronic device comprising: a memory device configured to store data; and a system-on-a-chip that uses the memory device as a working memory, wherein the system-on-a-chip loads a training code into a first memory area of the memory device, and performs software training on a second memory area of the memory device by executing the loaded training code. 2. The electronic device of claim 1, wherein the system-on-a-chip loads training data for testing and adjusting an access parameter of the second memory area upon the execution of the training code. 3. The electronic device of claim 1, wherein the system-on-a-chip loads the training code to the first memory area after deactivating a channel interleaving mode associated with the memory device. 4. The electronic device of claim 3, wherein the first memory area is included in a memory unit corresponding to a first channel of the memory device, and the second memory area is included in a memory unit corresponding to a second channel thereof. 5. The electronic device of claim 1, wherein the system-on-a-chip loads the training code to the first memory area after adjusting a size of a channel interleaving unit for channel interleaving associated with the memory device. 6. The electronic device of claim 5, wherein the size of the interleaving unit is adjusted based on a size of the training code. 7. The electronic device of claim 6, wherein the interleaving unit is adjusted to have a size greater than the size of the training code. 8. The electronic device of claim 1, wherein the system-on-a-chip comprises an arbiter that generates a conversion address, which is mapped such that the training code is continuously stored in the first memory area of the memory device, based on a channel interleaving address generated in a mode of operation in which the software training is performed. 9. The electronic device of claim 8, wherein the arbiter generates the conversion address by masking a specific bit of the channel interleaving address. 10. The electronic device of claim 1, wherein the system-on-a-chip further performs the software training on the first memory area by loading the training code into the second area and executing the loaded training code. 11. (canceled) 12. A software training method of an electronic device that drives a memory device managed in units of channels as a working memory, the method comprising: loading a training code into a first memory area of the memory device corresponding to a first channel of the memory device and loading training data into a second memory area of the memory device corresponding to a second channel of the memory device; accessing the training data stored in the second memory area in response to execution of the training code loaded into the first memory area; evaluating the training data read from the second memory area to ascertain an optimum value for an access parameter of the second channel; and setting an operating condition of the second channel by using the ascertained optimum value for the access parameter. 13. The method of claim 12, further comprising: deactivating a channel interleaving mode associated with the memory device. 14. The method of claim 12, further comprising: adjusting a size of a channel interleaving unit of the memory device. 15. (canceled) 16. The method of claim 12, further comprising: remapping a channel interleaving address of the memory device such that the training code is continuously stored in the first memory area of the memory device. 17. The method of claim 12, further comprising: loading the training data into the first memory area and the training code into the second memory area; executing the training code loaded into the second memory area; and accessing the training data to determine an access parameter of the first channel, upon execution of the training code. 18. The method of claim 12, wherein the access parameter comprises timing between a data signal and a strobe signal or a reference value of a signal level. 19. A computing system, comprising: a memory device that is driven as a working memory; and a host connected to a plurality of channels and configured to load data to the memory device and to fetch the data from the memory device via the plurality of channels, wherein the host performs software training on a second channel of the plurality of channels by: loading a training code into a memory area of the working memory corresponding to a first channel of the plurality of channels, and executing the loaded training code. 20. The computing system of claim 19, wherein the host loads the training code into the memory area corresponding to the first channel after deactivating a channel interleaving mode associated with the memory device. 21. The computing system of claim 19, wherein the host loads the training code into the memory area corresponding to the first channel after adjusting a size of a channel interleaving unit associated with the memory device. 22. (canceled) 23. The computing system of claim 19, wherein the host comprises an arbiter that hashes a channel interleaving address of the memory device to a continuous address. 24-36. (canceled)