Apparatus and methods for developing parallel networks. Parallel network design may comprise a general purpose language (GPC) code portion and a network description (ND) portion. GPL tools may be utilized in designing the network. The GPL tools may be configured to produce network specification language (NSL) engine adapted to generate hardware optimized machine executable code corresponding to the network description. The developer may be enabled to describe a parameter of the network. The GPC portion may be automatically updated consistent with the network parameter value. The GPC byte code may be introspected by the NSL engine to provide the underlying source code that may be automatically reinterpreted to produce the hardware optimized machine code. The optimized machine code may be executed in parallel.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. An apparatus for generating machine executable instructions configured to operate a parallel network, the apparatus comprising: a memory; and at least one processor coupled to the memory, the at least one processor being configured: to evaluate a code element of a parallel network design configured to include at least one of a general purpose code portion or a network description portion; to generate a first plurality of machine executable instructions if the code element includes the network description portion; and to generate a second plurality of machine executable instructions if the code element includes the general purpose code portion, wherein the second plurality of machine executable instructions includes instruction for a specific hardware platform of the parallel network; the general purpose code portion comprises a network object definition; the network object definition characterized by at least a first memory location configured to store a reference to the code element corresponding to the general purpose code portion of the parallel network design; and the network description portion comprises an instantiation of at least one network object configured based on the network object definition. 2. The apparatus of claim 1, wherein the at least one processor is further configured to interpret the code element using an interpreter tool associated with the general purpose code portion. 3. The apparatus of claim 1, in which the at least one processor is further configured: to retrieve the code element corresponding to the general purpose code portion of the parallel network design; and to convert at least a portion of the code element corresponding to the general purpose code portion of the parallel network design into the first plurality of machine executable instructions based on at least one characteristic of a target apparatus. 4. The apparatus of claim 3, in which the at least one characteristic comprises a memory level parallelism parameter configured to indicate a number of memory operations for a given memory location accessible by an individual one of multiple processing cores of the target apparatus contemporaneously with at least access by one other individual one of the multiple processing cores. 5. The apparatus of claim 4, in which the at least one processor is further configured to convert the at least a portion of the code element corresponding to the general purpose code portion of the parallel network design into the first plurality of machine executable instructions absent a user interface or an operating system call. 6. The apparatus of claim 4, wherein: the parallel network design comprises a plurality of units; and the at least one characteristic comprises a thread level parallelism parameter configured to indicate a number of multiple threads operable concurrently by a given processing element, an individual one of the threads corresponding to at least one of the plurality of units. 7. The apparatus of claim 6, wherein the at least one characteristic is configured to cause access of a memory location by individual ones of the multiple threads via an atomic operation. 8. The apparatus of claim 1, in which the at least one processor is further configured: to cause introspection of the first plurality of machine executable instructions to retrieve source code associated with the code element; to cause generation of a third plurality of machine executable instructions based on the retrieved source code, the third plurality of machine executable instructions being based on a resource use characteristic of a target apparatus; and wherein the source code retrieval and the generation of the third plurality of machine executable instructions enable optimized operation of one or more instances of at least one network object by the target apparatus, the optimized operation is characterized by the resource use characteristic of the target apparatus. 9. An apparatus for generating machine executable instructions configured to operate a parallel network, the apparatus comprising: means for evaluating a code element of a parallel network design configured to include at least one of a general purpose code portion or a network description portion; means for generating a first plurality of machine executable instructions if the code element includes the network description portion; and means for generating a second plurality of machine executable instructions if the code element includes the general purpose code portion, wherein the second plurality of machine executable instructions includes instruction for a specific hardware platform of the parallel network; the general purpose code portion comprises a network object definition; the network object definition characterized by at least a first memory location configured to store a reference to the code element corresponding to the general purpose code portion of the parallel network design; and the network description portion comprises an instantiation of at least one network object configured based on the network object definition. 10. The apparatus of claim 9, further comprising an interpreter tool associated with the general purpose code portion for interpreting the code element. 11. The apparatus of claim 9, further comprising: means for retrieving the code element corresponding to the general purpose code portion of the parallel network design; and means for converting at least a portion of the code element corresponding to the general purpose code portion of the parallel network design into the first plurality of machine executable instructions based on at least one characteristic of a target apparatus. 12. The apparatus of claim 11, in which the at least one characteristic comprises a memory level parallelism parameter configured to indicate a number of memory operations for a given memory location accessible by an individual one of multiple processing cores of the target apparatus contemporaneously with at least access by one other individual one of the multiple processing cores. 13. The apparatus of claim 12, further comprising means to convert the at least a portion of the code element corresponding to the general purpose code portion of the parallel network design into the first plurality of machine executable instructions absent a user interface or an operating system call. 14. The apparatus of claim 12, wherein: the parallel network design comprises a plurality of units; and the at least one characteristic comprises a thread level parallelism parameter configured to indicate a number of multiple threads operable concurrently by a given processing element, an individual one of the threads corresponding to at least one of the plurality of units. 15. The apparatus of claim 14, wherein the at least one characteristic is configured to cause access of a memory location by individual ones of the multiple threads via an atomic operation. 16. The apparatus of claim 9, further comprising: means for causing introspection of the first plurality of machine executable instructions to retrieve source code associated with the code element; means for causing generation of a third plurality of machine executable instructions based on the retrieved source code, the third plurality of machine executable instructions being based on a resource use characteristic of a target apparatus; and wherein the source code retrieval and the generation of the third plurality of machine executable instructions enable optimized operation of one or more instances of at least one network object by the target apparatus, the optimized operation is characterized by the resource use characteristic of the target apparatus. 17. A method for generating machine executable instructions configured to operate a parallel network, the method comprising: evaluating a code element of a parallel network design configured to include at least one of a general purpose code portion or a network description portion; generating a first plurality of machine executable instructions if the code element includes the network description portion; and generating a second plurality of machine executable instructions if the code element includes the general purpose code portion, wherein the second plurality of machine executable instructions includes instruction for a specific hardware platform of the parallel network and the network description portion comprises an instantiation of at least one network object. 18. The method of claim 17 in which the general purpose code portion comprises a network object definition and the at least one network object is configured based on the network object definition. 19. The method of claim 18, in which the network object definition is characterized by at least a first memory location configured to store a reference to the code element corresponding to the general purpose code portion of the parallel network design. 20. The method of claim 17, further comprising: converting at least a portion of the code element corresponding to the general purpose code portion of the parallel network design into the first plurality of machine executable instructions based on at least one characteristic of a target apparatus. 21. A non-transitory computer-readable medium having encoded thereon program code for generating machine executable instructions configured to operate a parallel network, the program code being executed by a processor and comprising: program code to evaluate a code element of a parallel network design configured to include at least one of a general purpose code portion or a network description portion; program code to generate a first plurality of machine executable instructions if the code element includes the network description portion; and program code to generate a second plurality of machine executable instructions if the code element includes the general purpose code portion, wherein the second plurality of machine executable instructions includes instruction for a specific hardware platform of the parallel network and the network description portion comprises an instantiation of at least one network object. 22. The non-transitory computer-readable medium of claim 21, in which the general purpose code portion comprises a network object definition and the at least one network object is configured based on the network object definition. 23. The non-transitory computer-readable medium of claim 22, in which the network object definition is characterized by at least a first memory location configured to store a reference to the code element corresponding to the general purpose code portion of the parallel network design. 24. The non-transitory computer-readable medium of claim 21, further comprising program code to convert at least a portion of the code element corresponding to the general purpose code portion of the parallel network design into the first plurality of machine executable instructions based on at least one characteristic of a target apparatus.