To provide a data processing device using a neural network that can suppress increase in the occupied area of a chip. A product-sum operation circuit is formed using a transistor including an oxide semiconductor having an extremely small off-state current. Signals are input to and output from the product-sum operation circuits included in a plurality of hidden layers through comparators. The outputs of the comparators are used as digital signals to be input signals for the next-stage hidden layer. The combination of a digital circuit and an analog circuit can eliminate the need for an analog-to-digital converter or a digital-to-analog converter which occupies a large area of a chip.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A data processing device using a neural network comprising: an input layer; a hidden layer; and an output layer, wherein the hidden layer comprises: a digital-to-analog converter; a first neuron circuit; a second neuron circuit; and a comparator, wherein each of the first neuron circuit and the second neuron circuit comprises a first potential holding circuit and a second potential holding circuit, wherein the first potential holding circuit and the second potential holding circuit are electrically connected to a bit line, wherein the first potential holding circuit is configured to hold a potential of a first analog signal, wherein the second potential holding circuit is configured to hold a potential of a second analog signal, wherein the first potential holding circuit comprises a first transistor, a second transistor, and a third transistor, wherein a gate of the second transistor is electrically connected to one of a source and a drain of the first transistor, wherein a gate of the third transistor is electrically connected to a first wiring to which a first digital signal is supplied, wherein the second potential holding circuit comprises a fourth transistor, a fifth transistor, and a sixth transistor, wherein a gate of the fifth transistor is electrically connected to one of a source and a drain of the fourth transistor, wherein a gate of the sixth transistor is electrically connected to a second wiring to which a second digital signal is supplied, wherein a third analog signal is output from the first neuron circuit to the second neuron circuit, is input to the comparator to which a reference voltage is applied, and is converted into a third digital signal, and wherein the third digital signal is output to the gate of the third transistor included in the second neuron circuit or the gate of the sixth transistor included in the second neuron circuit. 2. The data processing device according to claim 1, wherein the third analog signal is a signal obtained by adding a product of the first analog signal and the first digital signal to a product of the second analog signal and the second digital signal. 3. The data processing device according to claim 1, wherein each of the first transistor and the fourth transistor comprises an oxide semiconductor. 4. The data processing device according to claim 1, wherein each of the second transistor, the third transistor, the fifth transistor, and the sixth transistor comprises silicon. 5. The data processing device according to claim 1, further comprising a third neuron circuit in the hidden layer. 6. An electronic component comprising: the data processing device according to claim 1, and a lead electrically connected to the data processing device. 7. An electronic device comprising: the electronic component according to claim 6, a printed circuit board where the electronic component is mounted, and a housing incorporating the printed circuit board. 8. A data processing device using a neural network comprising: an input layer; a hidden layer; and an output layer, wherein the hidden layer comprises: a digital-to-analog converter; a first neuron circuit; and a second neuron circuit, wherein each of the first neuron circuit and the second neuron circuit comprises a first potential holding circuit and a second potential holding circuit, wherein the first potential holding circuit and the second potential holding circuit are electrically connected to a bit line, wherein the first potential holding circuit is configured to hold a potential of a first analog signal, wherein the second potential holding circuit is configured to hold a potential of a second analog signal, wherein the first potential holding circuit comprises a first transistor, a second transistor, and a third transistor, wherein a gate of the second transistor is electrically connected to one of a source and a drain of the first transistor, wherein a gate of the third transistor is electrically connected to a first wiring to which a first digital signal is supplied, wherein the second potential holding circuit comprises a fourth transistor, a fifth transistor, and a sixth transistor, wherein a gate of the fifth transistor is electrically connected to one of a source and a drain of the fourth transistor, wherein a gate of the sixth transistor is electrically connected to a second wiring to which a second digital signal is supplied, and wherein a third analog signal is output from the first neuron circuit to the second neuron circuit. 9. The data processing device according to claim 8, wherein the third analog signal is a signal obtained by adding a product of the first analog signal and the first digital signal to a product of the second analog signal and the second digital signal. 10. The data processing device according to claim 8, wherein each of the first transistor and the fourth transistor comprises an oxide semiconductor. 11. The data processing device according to claim 8, wherein each of the second transistor, the third transistor, the fifth transistor, and the sixth transistor comprises silicon. 12. An electronic component comprising: the data processing device according to claim 8, and a lead electrically connected to the data processing device. 13. An electronic device comprising: the electronic component according to claim 12, a printed circuit board where the electronic component is mounted, and a housing incorporating the printed circuit board.