A method for configuring long short-term memory (LSTM) in a spiking neural network includes decoding input spikes into analog values within the LSTM. The method further includes implementing the LSTM based on an encoded representation of the analog values. The implementing can include encoding the analog values using base expansive coding, rate coding, latency coding or synaptic weight coding.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A method for configuring long short-term memory (LSTM) in a spiking neural network, comprising: decoding input spikes into analog values within the LSTM; and implementing the LSTM based at least in part on an encoded representation of the analog values. 2. The method of claim 1, in which the implementing comprises encoding the analog values using base expansive coding, rate coding, latency coding or synaptic weight coding. 3. The method of claim 1, in which at least one analog value is negative. 4. The method of claim 1, in which the implementing comprises applying an activation function. 5. The method of claim 1, in which the input spikes include an input signal and a gating signal, and in which the implementing further includes generating a state value based at least in part on a product of values corresponding to encoded representations of the input signal and the gating signal. 6. The method of claim 5, in which the input spikes further include a maintenance signal and in which the state value is maintained based at least in part on a product of values corresponding to encoded representations of the maintenance signal and the state value. 7. The method of claim 5, in which the input spikes further include an output gating signal and in which the state value is output based at least in part on a product of values corresponding to encoded representations of the output gating signal and the state value. 8. The method of claim 5, in which the gating signal comprises a binary signal. 9. An apparatus for configuring long short-term memory (LSTM) in a spiking neural network, comprising: a memory; and at least one processor coupled to the memory, the at least one processor being configured: to decode input spikes into analog values within the LSTM; and to implement the LSTM based at least in part on an encoded representation of the analog values. 10. The apparatus of claim 9, in which the at least one processor is further configured to encode the analog values using base expansive coding, rate coding, latency coding or synaptic weight coding. 11. The apparatus of claim 9, in which at least one analog value is negative. 12. The apparatus of claim 9, in which the at least one processor is further configured to implement the LSTM by applying an activation function. 13. The apparatus of claim 9, in which the input spikes include an input signal and a gating signal, and in which the at least one processor is further configured to generate a state value based at least in part on a product of values corresponding to encoded representations of the input signal and the gating signal. 14. The apparatus of claim 13, in which the input spikes further include a maintenance signal and in which the at least one processor is further configured to maintain the state value based at least in part on a product of values corresponding to encoded representations of the maintenance signal and the state value. 15. The apparatus of claim 13, in which the input spikes further include an output gating signal and in which the at least one processor is further configured to output the state value based at least in part on a product of values corresponding to encoded representations of the output gating signal and the state value. 16. The apparatus of claim 13, in which the gating signal comprises a binary signal. 17. An apparatus for configuring long short-term memory (LSTM) in a spiking neural network, comprising: means for decoding input spikes into analog values within the LSTM; and means for implementing the LSTM based at least in part on an encoded representation of the analog values. 18. The apparatus of claim 17, further comprising means for encoding the analog values using base expansive coding, rate coding, latency coding or synaptic weight coding. 19. The apparatus of claim 17, in which at least one analog value is negative. 20. The apparatus of claim 17, further comprising means for applying an activation function. 21. The apparatus of claim 17, in which the input spikes include an input signal and a gating signal, and further comprising means for generating a state value based at least in part on a product of values corresponding to encoded representations of the input signal and the gating signal. 22. The apparatus of claim 21, in which the input spikes further include a maintenance signal and further comprising means for maintaining the state value based at least in part on a product of values corresponding to encoded representations of the maintenance signal and the state value. 23. The apparatus of claim 21, in which the input spikes further include an output gating signal and further comprising means for outputting the state value based at least in part on a product of values corresponding to encoded representations of the output gating signal and the state value. 24. A computer program product for configuring long short-term memory (LSTM) in a spiking neural network, comprising: a non-transitory computer readable medium having encoded thereon program code, the program code comprising: program code to decode input spikes into analog values within the LSTM; and program code to implement the LSTM based at least in part on an encoded representation of the analog values. 25. The computer program product of claim 24, further comprising program code to encode the analog values using base expansive coding, rate coding, latency coding or synaptic weight coding. 26. The computer program product of claim 24, in which at least one analog value is negative. 27. The computer program product of claim 24, further comprising program code to implement the LSTM by applying an activation function. 28. The computer program product of claim 24, in which the input spikes include an input signal and a gating signal, and further comprising program code to generate a state value based at least in part on a product of values corresponding to encoded representations of the input signal and the gating signal. 29. The computer program product of claim 28, in which the input spikes further include a maintenance signal and further comprising program code to maintain the state value based at least in part on a product of values corresponding to encoded representations of the maintenance signal and the state value. 30. The computer program product of claim 28, in which the input spikes further include an output gating signal and further comprising program code to output the state value based at least in part on a product of values corresponding to encoded representations of the output gating signal and the state value.