Self-organizing logic gates formed from a combination of memristor devices and dynamic correction modules configured to provide a stable operation upon application of a signal to any terminal A SOLG of the invention can accept signals from any terminal and does not require an absence of signals at any other terminal. Terminal signals can superpose and the gate finds equilibrium, if an equilibrium exists.
Please help me write a proper abstract based on the patent claims. CLAIM: 1.-21. (canceled) 22. A self-organizing circuit comprising: self-organizing logic gates coupled with each other; wherein each of the self-organizing logic gates is configured to self-organize by simultaneously performing forward logic and reverse logic. 23. The self-organizing circuit of claim 22, wherein each of the self-organizing logic gates comprises terminals. 24. The self-organizing circuit of claim 23, wherein each of the terminals is configured to function as both an input terminal and an output terminal. 25. The self-organizing circuit of claim 23, wherein each of the self-organizing logic gates is configured to implement a logic function with respect to signals present at the terminals. 26. The self-organizing circuit of claim 23, wherein the terminals of each of the self-organizing logic gates comprises a first set of terminals and a second set of terminals, and wherein the forward logic is from the first set of terminals to the second set of terminals and the reverse logic is from the second set of terminals to the first set of terminals. 27. The self-organizing circuit of claim 23, wherein each of the self-organizing logic gates further comprises memory elements connected between the terminals. 28. The self-organizing circuit of claim 27, wherein the memory elements comprise one or more memristor devices. 29. The self-organizing circuit of claim 23, wherein each of the self-organizing logic gates is configured to change a state in response to a signal received at any of the terminals. 30. The self-organizing circuit of claim 23, wherein: each of the self-organizing logic gates further comprises dynamic correction modules configured to dynamically drive an unstable configuration toward a stable configuration in response to a signal applied to any of the terminals; and a logic function implemented by the self-organizing logic gate is satisfied in the stable configuration. 31. The self-organizing circuit of claim 30, wherein each of dynamic correction modules comprises a memristor device. 32. The self-organizing circuit of claim 23, further comprising an auxiliary circuit configured to drive at least one terminal of one or more of the self-organizing logic gates to a respective logical value of either 0 or 1. 33. The self-organizing circuit of claim 22, wherein the self-organizing circuit further comprises a node designated to receive an input signal and each of the self-organizing logic gates performs forward logic and reverse logic in response to the input signal to satisfy a respective logic function. 34. The self-organizing circuit of claim 23, wherein the self-organizing circuit reaches equilibrium when each of the self-organizing logic gates satisfies its respective logic function. 35. The self-organizing circuit of claim 22, wherein one of the self-organizing logic gates satisfies its respective logic function based on a feedback from the self-organizing logic gates. 36. A machine readable non-transitory medium having information recorded thereon, wherein the information, when read by a machine, causes the machine to simulate a self-organizing circuit, wherein: the self-organizing circuit comprises self-organizing logic gates coupled to each other and each of the self-organizing logic gates is configured to self-organize by simultaneously performing forward logic and reverse logic. 37. The medium of claim 36, wherein each of the self-organizing logic gates comprises terminals. 38. The medium of claim 37, wherein each of the terminals is configured to function as both an input terminal and as an output terminal. 39. The medium of claim 37, wherein each of the self-organizing logic gates is configured to perform a logic function with respect to signals present at the terminals. 40. The medium of claim 39, wherein the self-organizing circuit further comprises a node designated for receiving an input signal and each of the self-organizing logic gates performs forward logic and reverse logic in response to the input signal to satisfy its respective logic function. 41. The medium of claim 37, wherein the terminals of each of the self-organizing logic gates comprises a first set of terminals and a second set of terminals, and wherein the forward logic is from the first set of terminals to the second set of terminals and the reverse logic is from the second set of terminals to the first set of terminals. 42. The medium of claim 37, wherein each of the self-organizing logic gates further comprises memory elements connected between the terminals. 43. The medium of claim 37, wherein each of the self-organizing logic gates changes a state in response to a signal received at any of the terminals. 44. A self-organizing logic gate, comprising: at least one terminal able to function as both an input terminal and output terminal; one or more memory elements, each of which is coupled with at least some of the terminals; and at least one dynamic correction module coupled to the at least one terminal, wherein the at least one dynamic correction module is configured to drive the self-organizing logic gate from an unstable configuration to a stable configuration in response to a signal applied to any terminal of the at least one terminal. 45. The self-organizing logic gate of claim 44, wherein the one terminal serves as both the input terminal and the output terminal, and the one terminal has input and output signals superposed thereon. 46. The self-organizing logic state of claim 44, wherein the self-organizing logic gate is configured to simultaneously perform forward logic and reverse logic. 47. The self-organizing logic gate of claim 46, wherein the stable configuration includes a logic state in which an input value is generated, via the reverse logic, at an input terminal of the at least one terminal in response to an output signal applied to one or more output terminals of the at least one terminal. 48. The self-organizing logic gate of claim 46, wherein the stable configuration includes a logic state in which an output value is generated, via the forward logic, at an output terminal of the at least one terminal in response to an output signal applied to one or more input terminals of the at least one terminal. 49. The self-organizing logic gate of claim 44, wherein any of the one or more memory elements is implemented based on a memristor device. 50. The self-organizing logic gate of claim 44, wherein the at least one dynamic correction module applies voltage correction to the corresponding at least one terminal to drive towards the stable configuration. 51. The self-organizing logic gate of claim 50, wherein the voltage correction is generated based on signal at the at least one terminal.