An implementation of neural networks on silicon for the processing of various signals comprises multidimensional signals such as images. The efficient implementation on silicon of a complete processing chain for the signal via the approach using neural networks is provided. The circuit comprises at least: a series of neuro-blocks grouped together in branches composed of a group of neuro-blocks and a broadcasting bus, the neuro-blocks connected to the broadcasting bus; a routing unit connected to the broadcasting bus of the branches, carrying out the routing and broadcasting of data to and from the branches; a transformation module connected to the routing unit via an internal bus and designed to be connected at the input of the circuit to an external databus, the module carrying out the transformation of input data into serial coded data. The processing operations internal to the circuit are carried out according to a serial communications protocol.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A circuit designed to implement a neural network, comprising at least: a series of elementary modules, called neuro-blocks, designed to implement an assembly of neurons, said neuro-blocks being grouped together in branches, a branch being composed of a group of neuro-blocks and of a broadcasting bus, the neuro-blocks being connected to said broadcasting bus; a routing unit connected to the broadcasting bus of said branches, carrying out at least the routing and the broadcasting of data to and from said branches; a transformation module connected to the routing unit via an internal bus and designed to be connected, at the input of said circuit, to an external databus, said module carrying out the transformation of the format of the input data carried by said external bus, a message of N input words with x bits coded in parallel being transformed into a message of N words with x bits coded in series, the N words being parallelized over the internal bus at the output of said module, one wire of the bus being dedicated to one word, the words being broadcast over the broadcasting buses of the branches and the other internal components of said circuit via the routing unit with the same serial coding, in such a manner that all the processing operations internal to said circuit are carried out according to a serial communications protocol. 2. The circuit as claimed in claim 1, wherein the routing unit comprises an input/output bus so as to route and to broadcast data to or from an external unit according to said serial communications protocol. 3. The circuit as claimed in claim 1, wherein the communications protocol comprises, for the transmission of a given message, information indicating the target unit. 4. The circuit as claimed in claim 3, wherein said information indicates the identifier of one or more neuro-blocks. 5. The circuit as claimed in claim 3, wherein said information indicates the destination branch or branches or external unit for said message. 6. The circuit as claimed in claim 1, wherein the routing unit furthermore performs global processing operations on the data. 7. The circuit as claimed in claim 1, comprising a module for direct memory access of the DMA type coupled via a bus to each neuro-block, said module being designed to be interfaced with an external memory. 8. The circuit as claimed in claim 7, comprising a central control module, said module is connected to this central control module via a bus. 9. The circuit as claimed in claim 1, wherein the neuro-blocks each comprising a set of arithmetic and logic units, all the arithmetic and logic units are connected to the same interconnection bus, said bus being designed to be extended outside of said circuit upstream and downstream of the neuro-blocks. 10. The circuit as claimed in claim 1, wherein the broadcasting buses comprise available data wires. 11. The circuit as claimed in claim 1, comprising four branches of 8 neuro-blocks or eight branches of 4 neuro-blocks. 12. The circuit as claimed in claim 1, wherein it performs processing functions on the signal. 13. The circuit as claimed in claim 12, wherein it performs pre-processing and/or post-processing functions on the signal with respect to neural processing functions. 14. A neural system, comprising several circuits as claimed in claim 1.