An integrated circuit (IC), as a computation block of a neuromorphic system, includes a time step controller to activate a time step update signal for performing a time-multiplexed selection of a group of neuromorphic states to update. The IC includes a first circuitry to, responsive to detecting the time step update signal for a selected group of neuromorphic states: generate an outgoing data signal in response to determining that a first membrane potential of the selected group of neuromorphic states exceeds a threshold value, wherein the outgoing data signal includes an identifier that identifies the selected group of neuromorphic states and a memory address (wherein the memory address corresponds to a location in a memory block associated with the integrated circuit), and update a state of the selected group of neuromorphic states in response to generation of the outgoing data signal.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. An integrated circuit comprising: a time step controller to activate a time step update signal for performing a time-multiplexed selection of a group of neuromorphic states to update; and a first circuitry to, responsive to detecting the time step update signal for a selected group of neuromorphic states: generate an outgoing data signal in response to determining that a first membrane potential of the selected group of neuromorphic states exceeds a threshold value, wherein the outgoing data signal includes an identifier that identifies the selected group of neuromorphic states and a memory address, wherein the memory address corresponds to a location in a memory block associated with the integrated circuit; and update a state of the selected group of neuromorphic states in response to generation of the outgoing data signal. 2. The integrated circuit of claim 1, wherein the time step controller is to randomly activate the time step update signal, the integrated circuit further comprising a second circuitry to, responsive to receipt of an incoming data signal corresponding to a second group of neuromorphic states: add a weight value of the incoming data signal to a second membrane potential of the second group of neuromorphic states, to generate an updated second membrane potential; and store the updated second membrane potential back to the register set. 3. The integrated circuit of claim 2, further comprising a register set to store the selected group of neuromorphic states and the second group of neuromorphic states, wherein the second circuitry is further to: identify, within the register set, a register storing the second group of neuromorphic states corresponding to a second identifier retrieved from the incoming data signal; and retrieve the second membrane potential from the register set, wherein the register set comprises a first register set to store a subset of the group of second neuromorphic states accessed by the second circuitry, and a second register set to store a second subset of the group of second neuromorphic states that are also accessed by the first circuitry. 4. The integrated circuit of claim 2, wherein the second circuitry further comprises a learning unit to perform a learning operation by updating the weight value for the second group of neuromorphic states, to generate an updated weight value, and wherein the second circuitry is further to transmit the updated weight value through a router, the updated weight value to be stored in the memory block. 5. The integrated circuit of claim 4, wherein a state of the group of second neuromorphic states is reflected by a learning counter, and the first circuitry is further to: set the learning counter to a maximum counter value upon generation of an outgoing data signal for the second group of neuromorphic states; decrement the learning counter responsive to each time step update signal; and wherein the learning counter is further to trigger selection of a weight update value that is added to or subtracted from the weight value, to generate the updated weight value. 6. The integrated circuit of claim 2, wherein a state of the group of second neuromorphic states is reflected by a refractory period counter, and the first circuitry is further to: set the refractory period counter to a maximum counter value upon generation of an outgoing data signal for the second group of neuromorphic states; and decrement the refractory period counter responsive to each time step update signal, wherein the first circuitry is to block generation of a subsequent outgoing data signal and the second circuitry is to block adding a weight value of a subsequent incoming data signal until the refractory period counter reaches zero. 7. The integrated circuit of claim 1, wherein the first circuitry is further to: multiply the first membrane potential of the selected group of neuromorphic states with a leak factor to generate a first updated membrane potential; and responsive to the first membrane potential being less than the threshold value, replace the first membrane potential with the first updated membrane potential. 8. The integrated circuit of claim 7, wherein the first circuitry is further to: compare an input data value of the selected group of neuromorphic states with a pseudo-randomly-generated input signal threshold; and responsive to the input data value being greater than the pseudo-randomly-generated input signal threshold, add the input data value to the first updated membrane potential before replacing the first membrane potential with the first updated membrane potential. 9. The integrated circuit of claim 7, wherein the first circuitry is further to: compare a bias value for the selected group of neuromorphic states with a pseudo-randomly-generated input bias threshold; and responsive to the bias value being greater than the pseudo-randomly-generated input bias threshold, add the bias value to the first updated membrane potential before replacing the first membrane potential with the first updated membrane potential. 10. A system comprising: a memory block; a computation block; and a router coupled to the memory block and to the computation block; wherein the computation block comprises: a time step controller to activate a time step update signal for performing a time-multiplexed selection of a group of neuromorphic states to update; a first circuitry to, responsive to detecting the time step update signal for a selected group of neuromorphic states: generate an outgoing data signal in response to determining that a first membrane potential of the selected group of neuromorphic states exceeds a threshold value, wherein the outgoing data signal includes an identifier that identifies the selected group of neuromorphic states and a memory address, wherein the memory address corresponds to a location in the memory block; and update a state of the selected group of neuromorphic states in response to generation of the outgoing data signal; and a learning unit to, responsive to detecting no time step update signal and to receipt of an incoming data signal, perform a learning operation by: identifying a second group of neuromorphic states corresponding to an identifier retrieved from the incoming data signal; and updating a weight value of the incoming data signal, to generate an updated weight value to be provided to the router, for storage at a second memory address of the memory block. 11. The system of claim 10, further comprising a register set to store the selected group of neuromorphic states and the second group of neuromorphic states, wherein the computation block further comprises a second circuitry to, responsive to receipt of the incoming data signal: identify a register, within the register set, for the second group of neuromorphic states; retrieve, from the register, a second membrane potential for the second group of neuromorphic states; add the weight value of the incoming data signal to the second membrane potential of the second group of neuromorphic states, to generate an updated second membrane potential; and store the updated second membrane potential back to the register set. 12. The system of claim 11, wherein the register set comprises a first register set to store a subset of the group of second neuromorphic states accessed by the second circuitry, and a second register set to store a second subset of the group of second neuromorphic states that are also accessed by the first circuitry. 13. The system of claim 11, wherein a state of the group of second neuromorphic states is reflected by a learning counter, and the first circuitry is further to: set the learning counter to a maximum counter value upon generation of an outgoing data signal for the second group of neuromorphic states; decrement the learning counter responsive to each time step update signal; and wherein the learning counter is further to trigger selection of a weight update value to one of add to or subtract from the weight value, to generate the updated weight value. 14. The system of claim 10, wherein the first circuitry is further to: multiply the first membrane potential of the selected group of neuromorphic states with a leak factor to generate an updated first membrane potential; and responsive to the membrane potential being less than the threshold value, replace the first membrane potential with the updated first membrane potential. 15. A system comprising a plurality of cores, wherein a first core of the plurality of cores comprises: a register set to store multiple groups of neuromorphic states; and a time step controller comprising: a linear-feedback shift register (LFSR) to pseudo-randomly generate a first value at a time step defined by a plurality of clock cycles; and a cellular automaton (CA) coupled to a second CA of a second core and to a third CA of a third core of the plurality of cores, wherein the CA is to: pseudo-randomly generate a second value different than values generated by the second CA and the third CA; and store the second value into a CA register coupled to the CA; and a logic circuitry to combine the first value with the second value to generate an updated value, and to use the updated value to determine at what time step, and for which group of neuromorphic states of the multiple groups of neuromorphic states, to activate a time step update signal. 16. The system of claim 15, wherein the logic circuitry includes an XOR gate to combine the first value with the second value. 17. The system of claim 15, wherein the logic circuitry is further to: compare a sequencing portion of the updated value with a programmable scan value; and activate the time step update signal responsive to the sequencing portion matching the programmable scan value, the time step update signal to select a group of neuromorphic states having an address provided by an address portion of the updated value, wherein the address corresponds to a location within a register set for storing the group of neuromorphic states. 18. The system of claim 17, wherein the logic circuitry includes clock gating of the CA register controlled by a pseudo-random bit, to ensure the LFSR proceeds through a plurality of available pseudo-random states for the second value stored in CA register. 19. An integrated circuit comprising a core for updating multiple groups of neuromorphic states, the core comprising: a register set to store the multiple groups of neuromorphic states; and a learning unit coupled to the register set and to, responsive to receipt of an incoming data signal, perform a learning operation comprising to: identify a group of neuromorphic states, of the multiple groups of neuromorphic states, corresponding to an identifier retrieved from incoming data signal; retrieve a weight update value corresponding to a learning counter value stored in the register set for the group of neuromorphic states, wherein the weight update value is also based on an incoming learning message type; selectively perform a sign extension to the weight update value depending on a state of a set of learning control bits, to generate a sign-extended weight update value; and add the sign-extended weight update value to a weight value of the incoming data signal, to generate an updated weight value for the group of neuromorphic states. 20. The integrated circuit of claim 19, wherein the incoming learning message type comprises one of long-term depression (LTD) or long-term potentiation (LTP), and wherein the state of the set of learning control bits comprises one of: elimination of the sign-extended update weight value; retaining the weight update value as a positive value in response to an LTP incoming learning message; making the weight update value a negative value in response to an LTD incoming learning message; or selecting one of the positive value or the negative value of the weight update value according to a plurality of modulatory bits received over a network to which the core is communicatively coupled via a router. 21. The integrated circuit of claim 20, further comprising a programmable parameter memory in which is stored a weight update curve comprising an LTD portion and an LTP portion of the weight update curve, and the learning unit is further to: manipulate the weight update curve to control a ratio of LTD versus LTP learning; and generate selectable weight update values based on the LTD portion and the LTP portion of the weight update curve. 22. The integrated circuit of the claim 19, wherein the learning unit is further to perform a set of maximum and minimum boundary checks on the sign-extended weight update value according to a programmable maximum weight and a programmable minimum weight. 23. The integrated circuit of claim 19, wherein the learning unit is further to apply a weight scale to the weight update value before selectively performing the sign extension, to generate a larger weight update value. 24. The integrated circuit of claim 19, wherein the core further comprises a time step controller to activate a time step update signal that performs a time-multiplexed selection of the group of neuromorphic states of the multiple groups of neuromorphic states, and the learning unit is to perform the learning operation when the time step update signal is not detected.