A device includes a state machine. The state machine includes a plurality of blocks, where each of the blocks includes a plurality of rows. Each of these rows includes a plurality of programmable elements. Furthermore, each of the programmable elements are configured to analyze at least a portion of a data stream and to selectively output a result of the analysis. Each of the plurality of blocks also has corresponding block activation logic configured to dynamically power-up the block.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A system, comprising: a state machine engine comprising a core, wherein the core comprises: blocks, each of the blocks comprising rows, each of the rows comprising programmable elements, each of the programmable elements configured to analyze at least a portion of data to be analyzed and to selectively provide a result of the analysis; and block activation logic corresponding to a block of the blocks, wherein the block activation logic is configured to dynamically power-up the block, wherein the block activation logic comprises a register configured to provide a first signal based at least in part on an indication of whether the portion of data to be analyzed is to be initially analyzed in the block. 2. The system of claim 1, wherein the block activation logic is configured to receive an indication of whether any of the programmable elements of the block are active. 3. The system of claim 2, wherein the block activation logic is configured to dynamically power-up the block based at least in part on the indication of whether any of the programmable elements are active. 4. The system of claim 1, wherein the block activation logic is configured to receive a second signal related to whether the block will be involved in analysis of the portion of data to be analyzed. 5. The system of claim 4, wherein the block activation logic comprises an AND gate configured to receive the first signal and the second signal and provide an output based at least in part on the first signal and the second signal. 6. The system of claim 5, wherein the block activation logic is configured to adaptively power-up the block based at least in part on the output. 7. The system of claim 1, comprising a processor configured to be coupled to the state machine engine. 8. The system of claim 7, wherein the processor is configured to transmit instructions corresponding to the data to be analyzed to the state machine engine. 9. The system of claim 7, wherein the state machine engine is configured to transmit the result of the analysis to the processor. 10. The system of claim 1, comprising a memory configured to transmit the data to be analyzed to the state machine engine. 11. A system, comprising: block activation logic configured to: receive a first indication of whether a block is to be involved in an analysis of at least a portion of data; receive a second indication of whether the portion of data to be analyzed is to be initially analyzed in the block; and provide a first activation signal for the block based at least in part on a comparison of the first and second indications. 12. The system of claim 11, wherein the block activation logic is configured to receive a third indication of whether any of the programmable elements of the block are active. 13. The system of claim 12, wherein the block activation logic is configured to receive a fourth indication corresponding to a result of an analysis of at least a portion of the data to be analyzed from a second block. 14. The system of claim 13, wherein the block activation logic is configured to receive provide a second activation signal for the block based at least in part on a comparison of the third and fourth indications. 15. The system of claim 14, wherein the block activation logic is configured to provide a block activation signal configured to allow the block to be powered, wherein the block activation signal is based at least in part on a comparison by the block activation logic of the first activation signal and the second activation signal. 16. The system of claim 15, comprising a state machine engine comprising a core, wherein the core comprises each of the block, the second block, and the block activation logic. 17. A system, comprising: a core comprising: a first block of programmable elements, wherein at least one of the programmable elements is configured to analyze at least a portion of data to be analyzed and to provide a result of the analysis; a second block of programmable elements; and a block switch configured to selectively route the result provided by the first block as a signal to power up the second block. 18. The system of claim 17, wherein the core further comprises block activation logic configured to receive the result from the first block. 19. The system of claim 18, wherein the block activation logic is configured to adaptively power-up the second block based at least in part on the result. 20. The system of claim 18, comprising at least one match buffer coupled to the core and configured to store the result prior to the result being provided to a processer external to the core and the match buffer.