A circuit for implementing an artificial neuron comprises: an integrator for an input signal to produce a voltage signal; a signal generator linked to the integrator output producing two output signals when the voltage is at or above a predetermined voltage, a first signal for an output pulse of the neuron and a second signal for a control pulse; a resistive memory comprising two terminals switching from a high to low resistance state in a time following a statistical distribution specific to the memory, a first terminal linked to the output of the integrator; a transistor linked to a branch at zero potential to a second terminal of the resistive memory, controlled by the second output signal such that in the presence of a pulse of voltage the resistive memory switches from its high resistance state to its low resistance state with a view to lowering the voltage.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A circuit for implementing an artificial neuron, said circuit comprising: an integrator configured to integrate an input signal in such a way as to produce at the output a signal of voltage Vmem; a signal generator linked to the output of the integrator and configured to produce two output signals when the voltage Vmem is above or equal to a predetermined voltage Vth, a first signal corresponding to an output pulse of the neuron and a second signal corresponding to a control pulse Vout; a resistive memory comprising two terminals and able to switch from a high resistance state to a low resistance state in a time Tset following a statistical distribution specific to said memory, a first terminal being linked to the output of the integrator; and a transistor linked to a branch at zero potential as well as to a second terminal of the resistive memory, said transistor being furthermore configured to be controlled by the second output signal of the signal generator in such a way that in the presence of a pulse of voltage Vout the resistive memory switches from its high resistance state to its low resistance state with a view to lowering the voltage Vmem. 2. The circuit according to claim 1, in which the resistive memory is chosen from among the following technologies: CBRAM, PMC, EMC, PCM, OXRAM, MRAM or STT-RAM. 3. The circuit according to either of the preceding claims claim 1, in which the transistor Q1 is of MOSFET type. 4. The circuit according to claim 1, in which the resistive memory is reset to a high resistance state after each switch to the low resistance state. 5. The circuit according to claim 4, in which this reset is carried out as soon as the emission of an output pulse of the neuron is terminated. 6. The circuit according to claim 1, in which the integrator is implemented by a capacitance (Cmem) linked to the branch at zero potential. 7. The circuit according to claim 1, in which the resistive memory is bipolar. 8. The circuit according to claim 1, in which the resistive memory is unipolar. 9. A neuromorphic system comprising a set of at least one input neuron, a set of at least one output neuron and a synaptic network, said synaptic network linking the input neurons to the output neurons, the set of at least one input neuron and/or the set of at least one output neuron being implemented by at least one circuit according to claim 1.