A device includes a match element that includes a first data input configured to receive a first result, wherein the first result is of an analysis performed on at least a portion of a data stream by an element of a state machine. The match element also includes a second data input configured to receive a second result, wherein the second result is of an analysis performed on at least a portion of the data stream by another element of the state machine. The match element further includes an output configured to selectively provide the first result or the second result.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A system, comprising: a processor configured to transmit instructions corresponding to data to be analyzed; and a state machine engine coupled to the processor and configured to be programmed via the instructions to analyze the data, wherein the state machine engine comprises: a first state machine element comprising: a first plurality of memory cells; and a first detection cell coupled to the first plurality of memory cells, wherein the first state machine element is configured analyze a first portion of the data to generate a first result; a first row routing line configured to be coupled to the first state machine element; a second state machine element comprising: a second plurality of memory cells; and a second detection cell coupled to the second plurality of memory cells, wherein the second state machine element is configured analyze a second portion of the data to generate a second result; a second row routing line configured to be coupled to the second state machine element; and a match element comprising: a first data input configured to be coupled to the first row routing line to receive the first result; a second data input configured to be coupled to a second row routing line to receive the second result; and an output configured to selectively provide the first result or the second result. 2. The system of claim 1, comprising a data path separate from any plurality of row routing lines comprising the first row routing line and the second row routing line, wherein the data line is configured to be coupled to the output to receive the first result or the second result. 3. The system of claim 2, comprising an output block of a finite state machine lattice comprising the match element, the first state machine element, and the second state machine element, wherein the match element is configured to selectively provide the first result or the second result via the output along the data path to the output block. 4. The system of claim 1, wherein the match element comprises a first control input configured to receive a first control signal. 5. The system of claim 4, wherein the match element is configured to selectively provide the first result or the second result based on the first control signal. 6. The system of claim 4, wherein the match element comprises a second control input configured to receive an output enable signal. 7. The system of claim 6, wherein the match element is configured to selectively provide no result based on the output enable signal. 8. The system of claim 1, wherein the match element comprises a multiplexer. 9. The system of claim 1, comprising a server, a personal computer, a work station, a router, a network switch, chip test equipment, a laptop, a cell phone, a media player, a game console, or a mainframe computer that comprises the system. 10. A system, comprising: a state machine engine; a processor coupled to the state machine engine, wherein the processor is configured to transmit instructions corresponding to a data stream to be searched to the state machine engine; and a memory coupled to the state machine engine via an interface bus, wherein the state machine engine is configured to receive the data stream to be searched from the memory, wherein the state machine engine comprises a state machine lattice comprising: a plurality of blocks, wherein each block of the plurality of blocks comprises: a plurality of rows, wherein each row of the plurality of rows comprises: a first element, comprising: a first plurality of memory cells; and a first detection cell coupled to the first plurality of memory cells, wherein the first element is configured to generate a first result generated by an analysis of a first portion of the data stream; a second element, comprising: a second plurality of memory cells; and a second detection cell coupled to the second plurality of memory cells, wherein the second element is configured to generate a second result generated by an analysis of a second portion of the data stream; and a match element comprising: a first input configured to receive the first result; a second input configured to receive the second result; and an output configured to selectively provide the first result or the second result. 11. The system of claim 10, wherein the state machine engine comprises a second state machine lattice coupled to the state machine lattice via an output block of the state mate machine engine. 12. The system of claim 11, wherein the match element is configured to selectively provide the first result or the second result to the output block. 13. The system of claim 10, wherein each row of the plurality of rows comprises a third element comprising a third detection cell coupled to a third plurality of memory cells, wherein the third element is configured to generate a third result generated by an analysis of a third portion of the data stream. 14. The system of claim 13, wherein each row of the plurality of rows comprises a special purpose element configured to generate a fourth result based upon at least one of the first result, the second result, or the third result. 15. The system of claim 14, where the match element comprises: a third input configured to receive the third result; a fourth input configured to receive the fourth result; and a second output configured to selectively provide the third result or the fourth result. 16. The system of claim 15, wherein the match element comprises: a first multiplexer coupled to the first input, the second input, and the first output; and a second multiplexer coupled to the third input, the fourth input, and the second output. 17. The system of claim 15, wherein the match element is configured to: selectively provide the first result or the second result based upon a first control signal; and selectively provide the third result or the fourth result based upon a second control signal. 18. A system, comprising: a processor configured to transmit instructions corresponding to data to be analyzed; an interface bus coupled to the processor; and a state machine engine coupled to the interface bus, wherein the state machine engine is configured to receive the instructions corresponding to the data to be analyzed via the interface bus, wherein the state machine engine is configured to be programmed via the instructions, wherein the state machine engine comprises: a match element comprising: a first data input configured to be coupled to a first row routing line to receive a first result, wherein the first result is generated by an analysis of a first portion of the data to be analyzed by a first state machine element comprising: a first plurality of memory cells; and a first detection cell coupled to the first plurality of memory cells; a second data input configured to be coupled to a second row routing line to receive a second result, wherein the second result is generated by an analysis of a second portion of the data to be analyzed a second state machine element comprising: a second plurality of memory cells; and a second detection cell coupled to the second plurality of memory cells; and an output configured to selectively provide the first result or the second result. 19. The system of claim 18, wherein the state machine engine comprises at output buffer configured to receive and store the selectively provided first result or the selectively provided second result as a match result. 20. The system of claim 19, wherein the state machine engine is configured to transmit the match result via the bus interface to the processor.