Methods for receiving a request to process, on a hardware circuit, a neural network comprising a first convolutional neural network layer having a stride greater than one, and in response, generating instructions that cause the hardware circuit to, during processing of an input tensor, generate a layer output tensor equivalent to an output of the first convolutional neural network layer by processing the input tensor using a second convolutional neural network layer having a stride equal to one but that is otherwise equivalent to the first convolutional neural network layer to generate a first tensor, zeroing out elements of the first tensor that would not have been generated if the second convolutional neural network layer had the stride of the first convolutional neural network layer to generate a second tensor, and performing max pooling on the second tensor to generate the layer output tensor.
Please help me write a proper abstract based on the patent claims. CLAIM: 1-20. (canceled) 21. A hardware circuit configured to process a convolutional neural network layer having a stride greater than one, the hardware circuit comprising: matrix computation circuitry configured to: generate a first tensor by convolving an input tensor received by the hardware circuit and a kernel, wherein the convolution is performed with a stride equal to one, and generate a second tensor by performing element-wise multiplication of the first tensor and a masking tensor; and pooling circuitry configured to generate a third tensor corresponding to an output of the convolutional neural network layer having the stride greater than one by performing max pooling on the second tensor. 22. The hardware circuit of claim 21, wherein the element-wise multiplication of the first tensor and the masking tensor zeros out elements of the first tensor that would not have been generated if performing a convolution with the stride greater than one. 23. The hardware circuit of claim 21, wherein the masking tensor comprises zeros at each position that corresponds to an element of the first tensor that would not have been generated if performing a convolution with the stride greater than one, and ones at each other position of the masking tensor. 24. The hardware circuit of claim 21, wherein the input tensor, the kernel, and the masking tensor are each stored at a memory accessible by the hardware circuit. 25. The hardware circuit of claim 21, wherein performing max pooling on the second tensor comprises: obtaining, for each of one or more windows of the second tensor that are defined by the stride greater than one, a maximum value element from among elements in the window. 26. The hardware circuit of claim 25, wherein the windows of the second tensor that are defined by the stride greater than one have rectangular dimensions, each dimension being equal to the stride greater than one, and each window including different elements of the second tensor. 27. The hardware circuit of claim 21, wherein the convolutional neural network layer having the stride greater than one is a first layer in a neural network, and the input tensor is a representation of a digital image comprising elements that correspond to pixels of the digital image. 28. The hardware circuit of claim 21, wherein the pooling circuitry comprises: registers configured to receive elements of the second tensor; and aggregation circuitry configured to access the elements of the second tensor stored at the registers and apply a maximum determining function to the elements of the second tensor stored at the registers. 29. The hardware circuit of claim 21, wherein the pooling circuitry comprises one or more memory units configured to: receive elements of the second tensor; and provide elements of the second tensor to the registers. 30. The hardware circuit of claim 21, wherein the hardware circuit comprises a host interface configured to receive instructions for controlling the hardware circuit to process the convolutional neural network layer having the stride greater than one. 31. The hardware circuit of claim 30, wherein the hardware circuit comprises a sequencer configured to receive the instructions and to generate, based at least on the instructions, control signals for controlling the matrix computation circuitry and the pooling circuitry to process the convolutional neural network layer having the stride greater than one. 32. The hardware circuit of claim 30, wherein the instructions are generated in response to a request to process an input using a neural network that includes the convolutional neural network layer having the stride greater than one. 33. The hardware circuit of claim 21, wherein the input tensor is stored at a unified buffer of the hardware circuit and the kernel is stored at a dynamic memory of the hardware circuit, and wherein the hardware circuit is configured to enable the matrix computation circuitry to generate the first tensor by convolving the input tensor and the kernel by: sending the input tensor from the unified buffer to the matrix computation circuitry; and sending the kernel from the dynamic memory to the matrix computation circuitry. 34. The hardware circuit of claim 21, wherein, to generate the first tensor by convolving the input tensor and the kernel, the matrix computation circuitry is configured to: receive elements of the input tensor at one or more cells of the matrix computation circuitry; receive weights of the kernel at the one or more cells of the matrix computation circuitry; process the received elements of the input tensor and the received weights of the kernel at the one or more cells of the matrix computation circuitry; and output results of the processing to one or more accumulators of the matrix computation circuitry. 35. The hardware circuit of claim 34, wherein each cell of the matrix computation circuitry comprises: an activation register configured to receive an element of the input tensor; a weight register configured to receive a weight of the kernel; and multiplication circuitry configured to multiply the element of the input tensor and the weight of the kernel. 36. The hardware circuit of claim 21, wherein, to generate the second tensor by performing element-wise multiplication of the first tensor and the masking tensor, the matrix computation circuitry is configured to: generate a first output tensor by performing matrix multiplication of the first tensor and an identity matrix; generate a second output tensor by performing matrix multiplication of the masking tensor and an identity matrix; and obtain the second tensor by multiplying the first output tensor and the second output tensor. 37. The hardware circuit of claim 36, wherein the matrix computation circuitry comprises multiplication circuitry configured to multiply the first output tensor and the second output tensor.