A neuromorphic device may include: a pre-synaptic neuron; a plurality of post-synaptic neurons; and a plurality of synapses electrically connected to the pre-synaptic neuron and electrically connected to the plurality of post-synaptic neurons. Each of the post-synaptic neurons may include: an integrator; a main comparator having a first input port connected to an output port of the integrator; and a first sub comparator having a first input port connected to the output port of the integrator.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A neuromorphic device comprising: a pre-synaptic neuron; a plurality of post-synaptic neurons; and a plurality of synapses electrically connected to the pre-synaptic neuron and electrically connected to the plurality of post-synaptic neurons, wherein each of the post-synaptic neurons comprises: an integrator; a main comparator having a first input port connected to an output port of the integrator; and a first sub comparator having a first input port connected to the output port of the integrator. 2. The neuromorphic device of claim 1, wherein the main comparator has a second input port receiving a main reference voltage. 3. The neuromorphic device of claim 2, wherein the first sub comparator has a second input port receiving a first sub reference voltage. 4. The neuromorphic device of claim 3, further comprising a second sub comparator having a first input port connected to the output port of the integrator and a second input port receiving a second sub reference voltage. 5. The neuromorphic device of claim 4, wherein the main reference voltage has a higher voltage level than the first and second sub reference voltage levels, and wherein the second sub reference voltage has a lower voltage level than the first sub reference voltage level. 6. The neuromorphic device of claim 4, wherein the first input ports of the main comparator, the first sub comparator, and the second sub comparator are non-inverting input ports, and wherein the second input ports of the main comparator, the first sub comparator, and the second sub comparator are inverting input ports. 7. The neuromorphic device of claim 1, wherein the output port of the integrator, the first input port of the main comparator, and the first input port of the first sub comparator are directly connected to each other. 8. The neuromorphic device of claim 1, wherein input ports of the integrators of the plurality of post-synaptic neurons are electrically connected to the plurality of synapses, respectively. 9. The neuromorphic device of claim 1, further comprising a switch block disposed between the plurality of post-synaptic neurons and the plurality of synapses. 10. The neuromorphic device of claim 9, wherein the switch block comprises a plurality of switches, wherein the plurality of synapses are grouped into a plurality of column line bundles, and wherein the plurality of switches electrically connects or disconnects a corresponding one of the column line bundles to or from the integrators of the plurality of post-synaptic neurons. 11. A neuromorphic device comprising: a pre-synaptic neuron; a row line electrically connected to the pre-synaptic neuron; a plurality of post-synaptic neurons; a plurality of column lines electrically connected to the plurality of post-synaptic neurons, respectively; and a plurality of synapses arranged at intersections between the low line and the plurality of column lines, wherein each of the plurality of post-synaptic neurons comprises: an integrator; and a comparator having a first input port connected to an output port of the integrator, wherein the comparator has a second input port to which a main reference voltage and a sub reference voltage are inputted, the sub reference voltage having a lower voltage level than the main reference voltage level. 12. The neuromorphic device of claim 11, wherein the sub reference voltage has two or more different voltage levels. 13. The neuromorphic device of claim 11, wherein the integrators of the plurality of post-synaptic neurons comprise input ports electrically connected to the plurality of synapses, respectively. 14-20. (canceled)