G06N504
Please help me predict the CPC LABEL for this patentPATENT ABSTRACT: A machine-learning accelerator (MLA) integrated circuit for extracting features from signals and performing inference computations is disclosed. The MLA integrated circuit includes a framework of finite state machine (FSM) kernels that are machine-learning algorithms implemented in hardware. The MLA integrated circuit further includes a kernel controller having mathematical structures implemented in hardware in communication with the framework of FSM kernels. An arithmetic engine implemented in hardware within the MLA integrated circuit is in communication with the kernel controller to perform computations for the mathematical structures. In at least one embodiment, the MLA integrated circuit includes a compression decompression accelerator (CDA) implemented in hardware and coupled between a memory and the kernel controller for compressing data to be stored in the memory and for decompressing data retrieved from the memory.