A method and system providing a multi-memristive synaptic element for a cognitive computing system. The multi-memristive synaptic element comprises an array of memristive devices. The method comprises arbitrating a synaptic weight allocation, a related synaptic weight being represented by a synaptic weight variable of said multi-memristive synaptic element, updating said synaptic weight variable by a delta amount, and assigning said memristive devices to elements of a clock-like ordered circular list for selecting a particular memristor of said memristive devices requiring to be updated by a deterministic, periodic global clock that points to a different memristor at every clock tick, such that said multi-memristive synaptic element has a larger dynamic range and a more linear conductance response than a single memristor synaptic element.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A computer-implemented method for providing a multi-memristive synaptic element for a cognitive computing system, said multi-memristive synaptic element comprising an array of memristive devices, said method comprising: arbitrating, by a programmed hardware processor, a synaptic weight allocation, a related synaptic weight being represented by a synaptic weight variable of said multi-memristive synaptic element, updating, using said programmed hardware processor, said synaptic weight variable by a delta amount, and assigning, by the programmed hardware processor, said memristive devices to elements of a clock-like ordered circular list for selecting a particular memristor of said memristive devices requiring to be updated by a deterministic, periodic global clock that points to a different memristor at every clock tick, running, by said programmed hardware processor, a reset clock, operating independently of said periodic global clock, for triggering a reset operation to be performed on a memristive device; such that said multi-memristive synaptic element has a larger dynamic range and a more linear conductance response than a single memristor synaptic element; and wherein a number of said ordered list of elements in said ordered circular list and an increment rate for said ordered circular list relate to each other in such a way that during consecutive iterations of selections at least one sub-element is different. 2. The method according to claim 1, wherein said memristive devices are organized in a parallel array. 3. The method according to claim 1, wherein said cognitive computing system is an artificial neural network trained with back-propagation. 4. The method according to claim 3, wherein an output xj of a post-synaptic neuron is given by xj=f(Σ(xi,Wij)), wherein f is a non-linear function, xi is an output of a pre-synaptic neuron, and Wij is said synaptic weight variable. 5. The method according to claim 1, wherein said amount is positive or negative. 6. The method according to claim 1, wherein said delta amount ΔWij of said synaptic weight variable is given by ΔWij=λ*xi*δj, wherein λ is a learning rate, xi is an output of a pre-synaptic neuron, and δj is a back-propagated delta error. 7. The method according to claim 1, wherein said memristor is a binary memristor or a multilevel memristor. 8. The method according to claim 1, wherein said reset clock is in the form of an ordered circular list for selecting a particular memristor of said memristive devices for said reset operation at a periodic update frequency. 9. The method according to claim 8, wherein said reset operations performed at a particular memristor of said memristive devices achieve a gradual change in conductance at said particular memristor. 10. The method according to claim 9, wherein the update frequencies of the periodic global clock and the reset clock are co-prime to each other. 11. The method according to claim 1, wherein a total number of memristors of said memristive synaptic element is equal for each memristive synaptic element in said cognitive computing system. 12. The method according to claim 1, wherein a total number of list elements in said ordered circular list is co-prime to an increment rate for said ordered circular list. 13. A multi-memristive synaptic element for a cognitive computing system, said multi-memristive synaptic element comprising an array of memristive devices, said multi-memristive synaptic element comprising an arbitration module for arbitrating a synaptic weight allocation, the synaptic weight being represented by a synaptic weight variable of said multi-memristive synaptic element, an updating unit adapted for updating said synaptic weight variable by a delta amount, wherein said arbitration module is also adapted for assigning said memristive devices to elements of a clock-like ordered circular list for selecting a particular memristor of said memristive devices requiring to be updated by a deterministic, periodic global clock that points to a different memristor at every clock tick, a reset clock operating independently of said periodic global clock for triggering a reset operation performed on a memristive device; such that said multi-memristive synaptic element has a larger dynamic range and a more linear conductance response than a single memristor synaptic element; and wherein a number of said ordered list of elements in said ordered circular list and an increment rate for said ordered circular list relate to each other in such a way that during consecutive iterations of selections at least one sub-element is different. 14. The multi-memristive synaptic element according to claim 14, wherein said memristive devices are organized in a parallel array. 15. The multi-memristive synaptic element according to claim 16, wherein an output xj of a post-synaptic neuron is given by xj=f(Σ(xi,Wij)), wherein f is a non-linear function, xi is an output of a pre-synaptic neuron, and Wij is said synaptic weight variable. 16. The multi-memristive synaptic element according to claim 14, wherein said delta amount ΔWij of said synaptic weight variable is given by ΔWij=λ*xi*δj, wherein λ is a learning rate, xi is an output of a pre-synaptic neuron, and δj is a back-propagated delta error. 17. The multi-memristive synaptic element according to claim 13, wherein said reset clock is in the form of an ordered circular list for selecting a particular memristor of said memristive devices for said reset operation at a periodic update frequency. 18. The multi-memristive synaptic element according to claim 17, wherein said reset operations performed at a particular memristor of said memristive devices achieve a gradual change in conductance at said particular memristor. 19. The multi-memristive synaptic element according to claim 18, wherein the update frequencies of the periodic global clock and the reset clock are co-prime to each other. 20. A computer program product for operating a multi-memristive synaptic element for a cognitive computing system, said multi-memristive synaptic element comprising an array of memristive devices, said computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, said program instructions being executable by one or more computing systems to cause said one or more computing systems to: arbitrate a synaptic weight allocation, a related synaptic weight being represented by a synaptic weight variable of said multi-memristive synaptic element, update said synaptic weight variable by a delta amount, and assign said memristive devices to elements of a clock-like ordered circular list for selecting a particular memristor of said memristive devices required to be updated by a deterministic, periodic global clock that points to a different memristor at every clock tick, operate a reset clock operating independently of said periodic global clock for triggering a reset operation performed on a memristive device; such that said multi-memristive synaptic element has a larger dynamic range and a more linear conductance response than a single memristor synaptic element; and wherein a number of said ordered list of elements in said ordered circular list and an increment rate for said ordered circular list relate to each other in such a way that during consecutive iterations of selections at least one sub-element is different.