A cognitive learning device includes inputs with each including an input path having a transistor device having a storage capacity. A circuit is responsive to the inputs and selects an input set in accordance with a current task, wherein the input set selected modifies a characteristic of the transistor device of one or more corresponding input paths to bias the input set for selection for subsequent accesses.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A cognitive learning device, comprising: a plurality of inputs, each input including an input path having at least one transistor device having a storage capacity; and a circuit responsive to the plurality of inputs and selecting an input set in accordance with a current task; wherein the input set selected modifies a characteristic of the at least one transistor device of one or more corresponding input paths to bias the input set for selection for subsequent accesses. 2. The device, as recited in claim 1, further comprising: a network of cognitive learning devices coupled to each other by links to perform a computation. 3. The device, as recited in claim 1, wherein the at least one transistor device includes a non-volatile random access memory having a floating gate as the storage capacity. 4. The device, as recited in claim 3, wherein the floating gate is charged or discharged per access to alter a threshold voltage of the at least one transistor device. 5. The device, as recited in claim 1, wherein the circuit includes a comparator. 6. The device, as recited in claim 5, wherein the comparator randomly selects one of the input paths to determine whether the path is correct and if correct usage of the path modifies the characteristic of the at least one transistor device. 7. The device, as recited in claim 1, wherein the at least one transistor device is charged or discharged initially to reset the device. 8. The device, as recited in claim 1, wherein the input set includes at least one input path. 9. The device, as recited in claim 1, wherein the at least one transistor device includes an analog device. 10. A cognitive learning device, comprising: a plurality of inputs, each input including an input path; at least one transistor device associated with each input path, the at least one transistor device having a storage capacity such that a threshold voltage of the at least one transistor device is modified in accordance with access criteria; and a comparator circuit being responsive to the plurality of inputs and selecting an input set in accordance with a current task such that the input set selected modifies the threshold voltage of the at least one transistor device to bias input paths associated with the input set for selection for subsequent accesses. 11. The device, as recited in claim 10, further comprising: a network of cognitive learning devices coupled to each other by links to perform a computation. 12. The device, as recited in claim 10, wherein the at least one transistor device includes a non-volatile random access memory having a floating gate as the storage capacity. 13. The device, as recited in claim 12, wherein the floating gate is charged or discharged per access to alter the threshold voltage of the at least one transistor device. 14. The device, as recited in claim 10, wherein the comparator randomly selects one of the input paths to determine whether the path is correct and, if correct, usage of the path modifies the threshold voltage of the at least one transistor device. 15. The device, as recited in claim 10, wherein the at least one transistor device is charged or discharged initially to reset the device. 16. The device, as recited in claim 10, wherein the input set includes at least one input path. 17. The device, as recited in claim 10, wherein the at least one transistor device includes an analog device. 18. A method for employing a cognitive learning device, comprising: randomly selecting a path initially among a plurality of input paths, each having at least one transistor; determining a correct input path for performing a current task; and modifying a threshold voltage of the at least one transistor associated with the correct path to bias selection of the correct path in subsequent accesses. 19. The method, as recited in claim 18, wherein the at least one transistor device includes a non-volatile random access memory having a floating gate as the storage capacity, the method further comprises charging or discharging per access to modify the threshold voltage of the at least one transistor device. 20. The method, as recited in claim 18, wherein the at least one transistor device is charged or discharged initially to reset the input paths.