A scalable stream synaptic supercomputer for extreme throughput neural networks is provided. The firing state of a plurality of neurons of a first neurosynaptic core is determined substantially in parallel. The firing state of the plurality of neurons is delivered to at least one additional neurosynaptic core substantially in parallel.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A method comprising: determining the firing state of a plurality of neurons of a first neurosynaptic core substantially in parallel; delivering to at least one additional neurosynaptic core the firing state of the plurality of neurons substantially in parallel. 2. The method of claim 1, wherein the first neurosynaptic core and the at least one additional neurosynaptic core are located on a first chip. 3. The method of claim 2, wherein the substantially parallel delivery is via an inter-core network. 4. The method of claim 3, wherein the substantially parallel delivery is performed by a permutation network, a Clos network, or a butterfly network. 5. The method of claim 1, further comprising: pipelining the firing state of the plurality of neurons. 6. The method of claim 1, further comprising: constructing a binary vector corresponding to the firing state of the plurality of neurons; transmitting the binary vector to the at least one additional neurosynaptic core. 7. The method of claim 1, wherein the first neurosynaptic core is located on a first chip, and the at least one additional neurosynaptic core is located on a second chip. 8. The method of claim 7, further comprising: transmitting the firing state of the plurality of neurons via an inter-chip network connecting the first chip and the second chip. 9. The method of claim 8, wherein the inter-chip network comprises an outgoing port of the first chip and an incoming port of the second chip. 10. The method of claim 8, wherein the inter-chip network comprises an outgoing port of the first chip connected to an incoming port of the first chip. 11. The method of claim 7, wherein the first and second chip are located on a first board. 12. The method of claim 7, wherein the first chip is located on a first board and the second chip is located on a second board, the first and second boards being connected. 13. The method of claim 12, wherein a plurality of boards comprising the first board and the second board is hierarchically arranged, and wherein the first board and the second board are connected via a hierarchy of routers. 14. A system comprising: a plurality of neurosynaptic cores, the neurosynaptic cores comprising a plurality of axons, a plurality of synapses, and a plurality of neurons; a first inter-core network connecting the plurality of neurosynaptic cores, wherein the first inter-core network is adapted to deliver from a first neurosynaptic core of the plurality of neurosynaptic cores to at least one additional neurosynaptic core the firing state of the plurality of neurons of the first neurosynaptic core substantially in parallel; 15. The system of claim 14, wherein the inter-core network comprises a permutation network, a Clos network, or a butterfly network. 16. The system of claim 14, wherein the first inter-core network is located on a first chip and a second inter-core network is located on a second chip, the at least one additional neurosynaptic core being connected to the second inter-core network. 17. The system of claim 16, wherein the first chip and the second chip are adjacent. 18. The system of claim 16, further comprising: a port connecting the first inter-core network to the second inter-core network. 19. The system of claim 14, further comprising: a port connecting the first inter-core network to itself 20. The system of claim 16, wherein the first and second chip are located on a first board. 21. The system of claim 16, wherein the first chip is located on a first board and the second chip is located on a second board, the first and second boards being connected. 22. The system of claim 21, wherein a plurality of boards comprising the first board and the second board is hierarchically arranged, and wherein the first board and the second board are connected via a hierarchy of routers. 23. A method comprising: simulating a plurality of neurosynaptic cores, the simulated neurosynaptic cores comprising a plurality of simulated axons, a plurality of simulated synapses, and a plurality of simulated neurons; simulating a network connecting the plurality of simulated neurosynaptic cores; simulating the determination of the firing state of the plurality of simulated neurons of a first of the simulated neurosynaptic cores; simulating the delivery to an at least one additional of the simulated neurosynaptic cores the firing state of the plurality of simulated neurons. 24. The method of claim 19, wherein the simulated network comprises an inter-core network. 25. The method of claim 19, wherein the simulated network comprises an inter-chip network. 26. The method of claim 19, wherein the simulated network comprises an inter-board network. 27. A computer program product for operating a neurosynaptic network, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising: determining the firing state of a plurality of neurons of a first neurosynaptic core substantially in parallel; delivering to at least one additional neurosynaptic core the firing state of the plurality of neurons substantially in parallel. 28. A computer program product for simulating a neurosynaptic network, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising: simulating a plurality of neurosynaptic cores, the simulated neurosynaptic cores comprising a plurality of simulated axons, a plurality of simulated synapses, and a plurality of simulated neurons; simulating a network connecting the plurality of simulated neurosynaptic cores; simulating the determination of the firing state of the plurality of simulated neurons of a first of the simulated neurosynaptic cores; simulating the delivery to an at least one additional second of the simulated neurosynaptic cores the firing state of the plurality of simulated neurons.