A processor comprising a plurality of processing cores, a last level cache memory (LLC) shared by the plurality of processing cores, and a neural network unit (NNU) comprising an array of neural processing units (NPU) and a memory array. The LLC comprises a plurality of slices. To transition from a first mode in which the memory array operates to store neural network weights read by the plurality of NPUs to a second mode in which the memory array operates as a slice of the LLC in addition to the plurality of slices, the processor write-back-invalidates the LLC and updates a hashing algorithm to include the memory array as a slice of the LLC in addition to the plurality of slices. To transition from the second mode to the first mode, the processor write-back-invalidates the LLC and updates the hashing algorithm to exclude the memory array from the LLC.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A processor, comprising: a plurality of processing cores; a last level cache memory (LLC) shared by the plurality of processing cores, the LLC comprising a plurality of slices; and a neural network unit (NNU), comprising: an array of neural processing units (NPU); and a memory array; wherein to transition from a first mode in which the memory array operates to store neural network weights read by the plurality of NPUs to a second mode in which the memory array operates as a slice of the LLC in addition to the plurality of slices, the processor: write-back-invalidates the LLC; and updates a hashing algorithm to include the memory array as a slice of the LLC in addition to the plurality of slices; and wherein to transition from the second mode to the first mode, the processor: write-back-invalidates the LLC; and updates the hashing algorithm to exclude the memory array from the LLC. 2. The processor of claim 1, wherein to transition from the first mode to the second mode, the processor also invalidates the NNU memory array. 3. The processor of claim 1, wherein to write-back-invalidate the LLC to transition from the first mode to the second mode, the processor write-back-invalidates the plurality of slices; and wherein to write-back-invalidate the LLC to transition from the second mode to the first mode, the processor write-back-invalidates the plurality of slices and the memory array. 4. The processor of claim 1, wherein to write-back-invalidate the LLC to transition from the first mode to the second mode, the processor only write-back-invalidates cache lines of the plurality of slices whose addresses the hashing algorithm that excludes the memory array hashes to a different slice than the hashing algorithm that includes the memory array; and wherein to write-back-invalidate the LLC to transition from the second mode to the first mode, the processor only write-back-invalidates cache lines of the plurality of slices and the memory array whose addresses the hashing algorithm that excludes the memory array hashes to a different slice than the hashing algorithm that includes the memory array. 5. The processor of claim 4, wherein all cache lines whose addresses are mapped to the plurality of slices by the hashing algorithm that includes the memory array are mapped to the same slices by the hashing algorithm that excludes the memory; and wherein to write-back-invalidate the LLC to transition from the second mode to the first mode, the processor write-back-invalidates none of cache lines of the plurality of slices and write-back-invalidates cache lines of the memory array. 6. The processor of claim 5, wherein the hashing algorithm that includes the memory array uses the first plurality of bits of the cache line addresses in addition to a second plurality of bits of the cache line addresses that is different from the first plurality of bits of the cache line addresses. 7. The processor of claim 6, wherein the hashing algorithm that includes the memory array selects the memory array when the second plurality of bits of the cache line addresses equals a predetermined value and otherwise selects one of the plurality of slices uses the first plurality of bits of the cache line addresses. 8. The processor of claim 1, further comprising: a ring bus to which are coupled the NNU, the plurality of slices, and the plurality of processing cores. 9. The processor of claim 8, further comprising: wherein when operating in the first mode, the plurality of processing cores access the NNU over the ring bus as a peripheral device for accelerating neural network computations. 10. The processor of claim 1, wherein to transition from the first mode to the second mode and to transition from the second mode to the first mode, the processor synchronizes the plurality of processing cores prior to the write-back-invalidate of the LLC and resumes execution after the write-back-invalidate of the LLC. 11. A method for operating a processor having a plurality of processing cores, a last level cache memory (LLC) shared by the plurality of processing cores, the LLC comprising a plurality of slices, and a neural network unit (NNU) comprising an array of neural processing units (NPU) and a memory array, the method comprising: transitioning from a first mode in which the memory array operates to store neural network weights read by the plurality of NPUs to a second mode in which the memory array operates as a slice of the LLC in addition to the plurality of slices, comprising: write-back-invalidating the LLC; and updating a hashing algorithm to include the memory array as a slice of the LLC in addition to the plurality of slices; and transitioning from the second mode to the first mode, comprising: write-back-invalidating the LLC; and updating the hashing algorithm to exclude the memory array from the LLC. 12. The method of claim 11, said transitioning from the first mode to the second mode further comprises invalidating the NNU memory array. 13. The method of claim 11, wherein said write-back-invalidating the LLC to transition from the first mode to the second mode comprises write-back-invalidating the plurality of slices; and wherein said write-back-invalidating the LLC to transition from the second mode to the first mode comprises write-back-invalidating the plurality of slices and the memory array. 14. The method of claim 11, wherein said write-back-invalidating the LLC to transition from the first mode to the second mode comprises only write-back-invalidating cache lines of the plurality of slices whose addresses the hashing algorithm that excludes the memory array hashes to a different slice than the hashing algorithm that includes the memory array; and wherein said write-back-invalidating the LLC to transition from the second mode to the first mode comprises only write-back-invalidating cache lines of the plurality of slices and the memory array whose addresses the hashing algorithm that excludes the memory array hashes to a different slice than the hashing algorithm that includes the memory array. 15. The method of claim 14, wherein all cache lines whose addresses are mapped to the plurality of slices by the hashing algorithm that includes the memory array are mapped to the same slices by the hashing algorithm that excludes the memory; and wherein said write-back-invalidating the LLC to transition from the second mode to the first mode comprises write-back-invalidating none of cache lines of the plurality of slices and write-back-invalidating cache lines of the memory array. 16. The method of claim 15, wherein the hashing algorithm that includes the memory array uses the first plurality of bits of the cache line addresses in addition to a second plurality of bits of the cache line addresses that is different from the first plurality of bits of the cache line addresses. 17. The method of claim 16, wherein the hashing algorithm that includes the memory array selects the memory array when the second plurality of bits of the cache line addresses equals a predetermined value and otherwise selects one of the plurality of slices uses the first plurality of bits of the cache line addresses. 18. The method of claim 11, wherein the processor further comprises a ring bus to which are coupled the NNU, the plurality of slices, and the plurality of processing cores. 19. The method of claim 18, further comprising: accessing, by the plurality of processing cores when operating in the first mode, the NNU over the ring bus as a peripheral device for accelerating neural network computations. 20. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising: computer usable program code embodied in said medium, for specifying a processor, the computer usable program code comprising: first program code for specifying a plurality of processing cores; second program code for specifying a last level cache memory (LLC) shared by the plurality of processing cores, the LLC comprising a plurality of slices; and third program code for specifying a neural network unit (NNU), comprising: an array of neural processing units (NPU); and a memory array; wherein to transition from a first mode in which the memory array operates to store neural network weights read by the plurality of NPUs to a second mode in which the memory array operates as a slice of the LLC in addition to the plurality of slices, the processor: write-back-invalidates the LLC; and updates a hashing algorithm to include the memory array as a slice of the LLC in addition to the plurality of slices; and wherein to transition from the second mode to the first mode, the processor: write-back-invalidates the LLC; and updates the hashing algorithm to exclude the memory array from the LLC.