Embodiments of the present invention relate to meeting latency constraints in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for power-driven synthesis under latency constraints is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores. Each of the plurality of neurosynaptic cores is modeled as a node in a placement graph. The graph has a plurality of edges. A weight is assigned to each of the plurality of edges based on a spike frequency. An arrangement of the neurosynaptic cores is determined. The arrangement comprises a length of each of the plurality of edges. A maximum length is compared to the length of each of the plurality of edges. The weight of at least one of the plurality of edges is increased where the length is greater than the maximum length.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A method comprising: modeling power consumption of a neurosynaptic network as wire length, the neurosynaptic network comprising a plurality of neurosynaptic cores and each of the plurality of neurosynaptic cores being modeled as a node in a placement graph, the graph having a plurality of edges; assigning a weight to each of the plurality of edges based on a spike frequency; determining an arrangement of the neurosynaptic cores, the arrangement comprising a length of each of the plurality of edges; comparing a maximum length to the length of each of the plurality of edges; increasing the weight of at least one of the plurality of edges having a length greater than the maximum length. 2. The method of claim 1, further comprising: determining a second arrangement of the neurosynaptic cores. 3. The method of claim 1, wherein the determining the arrangement of the neurosynaptic cores comprises: observing at least one placement legality constraint. 4. The method of claim 3, wherein the at least one placement legality constraint comprises avoiding overlapping of the neurosynaptic cores. 5. The method of claim 1, wherein the determining the arrangement of the neurosynaptic cores comprises: minimizing the wire length. 6. The method of claim 5, wherein the minimizing the wire length comprises applying a VLSI placement algorithm. 7. The method of claim 6, wherein the VLSI placement algorithm comprises partitioning-based placement. 8. The method of claim 1, wherein the neurosynaptic network further comprises a plurality of neuron-axon connections, and wherein each of the plurality of edges correspond to one of the neuron-axon connections. 9. The method of claim 1, wherein each of the plurality of neuron-axon connections has a source core and a destination core, and wherein the plurality of edges does not include edges corresponding to those neuron-axon connections whose source core and destination core are the same. 10. A computer program product for power-driven synthesis under latency constraints, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform a method comprising: modeling power consumption of a neurosynaptic network as wire length, the neurosynaptic network comprising a plurality of neurosynaptic cores and each of the plurality of neurosynaptic cores being modeled as a node in a placement graph, the graph having a plurality of edges; assigning a weight to each of the plurality of edges based on a spike frequency; determining an arrangement of the neurosynaptic cores, the arrangement comprising a length of each of the plurality of edges; comparing a maximum length to the length of each of the plurality of edges; increasing the weight of at least one of the plurality of edges having a length greater than the maximum length. 11. The computer program product of claim 10, the method further comprising: determining a second arrangement of the neurosynaptic cores. 12. The computer program product of claim 1, wherein the determining the arrangement of the neurosynaptic cores comprises: observing at least one placement legality constraint. 13. The computer program product of claim 3, wherein the at least one placement legality constraint comprises avoiding overlapping of the neurosynaptic cores. 14. The computer program product of claim 1, wherein the determining the arrangement of the neurosynaptic cores comprises: minimizing the wire length. 15. The computer program product of claim 5, wherein the minimizing the wire length comprises applying a VLSI placement algorithm. 16. The computer program product of claim 6, wherein the VLSI placement algorithm comprises partitioning-based placement. 17. The computer program product of claim 1, wherein the neurosynaptic network further comprises a plurality of neuron-axon connections, and wherein each of the plurality of edges correspond to one of the neuron-axon connections. 18. The computer program product of claim 1, wherein each of the plurality of neuron-axon connections has a source core and a destination core, and wherein the plurality of edges does not include edges corresponding to those neuron-axon connections whose source core and destination core are the same.