A neural network computing device, system and method that operate with a synchronization circuit in which all components are synchronized with a system clock and include a distributed memory structure for storing artificial neural network data and a calculation structure for time-division processing of all neurons on a pipeline circuit. The neural network computing device may include: a control unit for controlling the neural network computing device; a plurality of memory units for outputting an output value of a front-end neuron of a connection line by using a dual port memory; and a calculation sub-system for calculating an output value of a rear-end neuron of a new connection line by using the output value of the front-end neuron of the connection line input from each of the plurality of memory units and for feeding the output value back to each of the plurality of memory units.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A neural network computing device, comprising: a control unit for controlling the neural network computing device; a plurality of memory units each for outputting an output value of a pre-synaptic neuron using dual port memory; and a single calculation sub-system for calculating an output value of a new post-synaptic neuron using the output values of the pre-synaptic neurons received from the plurality of memory units and feeding the new output value back to each of the plurality of memory units, wherein each of the plurality of memory units comprises first memory for storing a reference number of the pre-synaptic neuron; and second memory which comprises the dual port memory having a read port and a write port and which stores an output value of a neuron. 2. (canceled) 3. The neural network computing device of claim 1, wherein the neural network computing device distributes and stores reference numbers of neurons connected to input synapses of all neurons within a neural network to the first memory of the plurality of memory units and performs a calculation function in accordance with step a to step d below. a. The step of sequentially changing values of address inputs of the first memory of the plurality of memory units and sequentially outputting reference numbers of neurons connected to input synapses of the neurons to data outputs of the first memory b. The step of sequentially outputting output values of the neurons connected to the input synapses of the neurons to data outputs of the read ports of the second memory of the plurality of memory units so that the output values are inputted to a plurality of inputs of the calculation sub-system through outputs of the plurality of memory units c. The step of sequentially calculating, by the calculation sub-system, output values of new post-synaptic neurons d. The step of sequentially storing the output values of the post-synaptic neurons calculated by the calculation sub-system through the write ports of the second memory of the plurality of memory units 4. (canceled) 5. The neural network computing device of claim 1, wherein the neural network computing device distributes, accumulates, and stores reference numbers of neurons connected to input synapses of neurons, included in a corresponding layer, in a specific address range of the first memory of the plurality of memory units with respect to each of one or a plurality of hidden layers and an output layer and calculates a neural network comprising a multi-layer network in accordance with step a and step b below. a. The step of storing input data in the second memory of the plurality of memory units as a value of a neuron of an input layer b. The step of sequentially calculating each of the hidden layers and the output layer from a layer connected to an input layer to the output layer in accordance with a process b1 to a process b4 below b1. The process of sequentially changing values of address inputs of the first memory of the plurality of memory units within an address range of the corresponding layer and sequentially outputting reference numbers of neurons, connected to input synapses of neurons within the corresponding layer, to data outputs of the first memory b2. The process of sequentially outputting output values of the neurons, connected to the input synapses of the neurons within the corresponding layer, to data outputs of the read ports of the second memory of the plurality of memory units b3. The process of sequentially calculating, by the calculation sub-system, new output values of all the neurons within the corresponding layer b4. The process of sequentially storing, by the calculation sub-system, the calculated output values of the neurons through the write ports of the second memory of the plurality of memory units 6. (canceled) 7. The neural network computing device of claim 1, wherein the dual port memory comprises physical dual port memory having a logic circuit capable of simultaneously accessing one piece of memory in an identical clock cycle. 8. The neural network computing device of claim 1, wherein the dual port memory comprises two input/output ports accessing one piece of memory in different clock cycles in a time-division way. 9. The neural network computing device of claim 1, wherein the dual port memory comprises: two pieces of identical physical memory, and a dual memory swap circuit for changing and connecting all inputs and outputs of the two pieces of identical physical memory using a plurality of switches controlled in response to a control signal from the control unit. 10. The neural network computing device of claim 1, wherein the calculation sub-system comprises: a plurality of synapse units for receiving outputs of the plurality of memory units, respectively, and performing synapse-specific calculation; a dendrite unit for receiving outputs of the plurality of synapse units and calculating a sum of inputs transferred from all synapses of a neuron; and a soma unit for receiving an output of the dendrite unit, updating a state value of the neuron, and calculating a new output value, or the plurality of synapse units; and the soma unit. 11-12. (canceled) 13. The neural network computing device of claim 1, wherein the calculation sub-system comprises: state value memory for storing a state value; and one or more calculation circuits for sequentially calculating new state values using data sequentially read from an output of the state value memory as some or all of inputs and sequentially storing some or all of results of the calculation in the state value memory. 14. (canceled) 15. The neural network computing device of claim 1, wherein the calculation sub-system comprises: look-up memory for storing a plurality of attribute values and providing the attribute values to the calculation circuit; and one or more pieces of attribute value reference number memory for storing a plurality of attribute value reference numbers and providing the attribute value reference numbers to the look-up memory. 16-27. (canceled) 28. The neural network computing device of claim 1, wherein each of the plurality of memory units comprises: first memory for storing a reference number of a neuron connected to a synapse; second memory comprising the dual port memory having a read port and a write port; third memory comprising the dual port memory having a read port and a write port; and a dual memory swap circuit comprising a plurality of switches which is controlled in response to a control signal from the control unit and which changes and connects all inputs and outputs of the second memory and the third memory. 29-30. (canceled) 31. The neural network computing device of claim 1, wherein each of the plurality of memory units comprises: first memory for storing a reference number of a neuron connected to a synapse; second memory comprising the dual port memory having a read port and a write port; third memory comprising the dual port memory having a read port and a write port; fourth memory comprising the dual port memory having a read port and a write port; and triple memory swap circuit comprising a plurality of switches which is controlled in response to a control signal from the control unit and which sequentially changes and connects all inputs and outputs of the second memory to the fourth memory. 32-40. (canceled) 41. The neural network computing device of claim 1, further comprising an offset circuit for enabling the control unit to easily change an access range of memory to an address input stage of each of the memory unit or one a plurality of pieces of memory within the calculation sub-system by designating a value obtained by adding a designated offset value to an accessed address value as an address of the memory. 42. The neural network computing device of claim 1, wherein the control unit comprises a Stage Operation Table (SOT) comprising information required to generate a control signal for each control step, reads records of the SOT one by one for each control step, and uses the read records in a system operation. 43. (canceled) 44. A neural network computing system, comprising: a control unit for controlling the neural network computing system; a plurality of network sub-systems each comprising a plurality of memory units each for outputting an output value of a pre-synaptic neuron using dual port memory; and a plurality of calculation sub-systems each for calculating an output value of a new post-synaptic neuron using the output values of the pre-synaptic neurons received from a plurality of the memory units included in one of the plurality of network sub-systems and feeding the new output value back to each of the plurality of memory units. 45. The neural network computing system of claim 44, further comprising a multiplexer which is provided between an output stage of the plurality of calculation sub-systems and an input stage to which feedback inputs of the plurality of memory units of the plurality of network sub-systems are connected in common and which multiplexes outputs of the plurality of calculation sub-systems. 46. The neural network computing system of claim 44, wherein the control unit generates control signals having a time lag and varying in identical order using a plurality of shift registers connected in a row and supplies the control signals to address inputs of memory within the neural network computing system. 47-51. (canceled) 52. A memory device, comprising: first memory for storing a reference number of a pre-synaptic neuron; and second memory comprising dual port memory having a read port and a write port, for storing an output value of a neuron. 53. The memory device of claim 52, wherein the dual port memory comprises physical dual port memory having a logic circuit capable of simultaneously accessing one piece of memory in an identical clock cycle. 54. The memory device of claim 52, wherein the dual port memory comprises two input/output ports accessing one piece of memory in different clock cycles in a time-division way. 55. The memory device of claim 52, wherein: the dual port memory comprises two pieces of identical physical memory, and a dual memory swap circuit for changing and connecting all inputs and outputs of the two pieces of identical physical memory using a plurality of switches controlled in response to a control signal from a control unit. 56. (canceled)