The arithmetic processing circuit includes a first layer configured to dispose a learning neural network to compute a coefficient to be set in a recognition neural network, configured to recognize input data by using the coefficient computed on a basis of a recognition result of the recognition neural network with for the input data serving as a reference for computing the coefficient and a recognition result serving as a reference for the input data serving as the reference. The circuit further includes a second layer configured to dispose the recognition neural network to recognize the input data by the coefficient computed by the learning neural network. The circuit still further includes a third layer disposed between the first layer and the second layer, and configured to dispose a memory connected to both of the learning neural network and the recognition neural network.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. An arithmetic processing circuit comprising: a first layer configured to dispose a learning neural network to compute a coefficient to be set in a recognition neural network, wherein the recognition neural network is configured to recognize input data by using the coefficient computed on a basis of a recognition result of the recognition neural network with respect to the input data serving as a reference for computing the coefficient and a recognition result serving as a reference with respect to the input data serving as the reference; a second layer configured to dispose the recognition neural network to recognize the input data by the coefficient computed by the learning neural network; and a third layer disposed between the first layer and the second layer, and configured to dispose a memory connected to both of the learning neural network and the recognition neural network. 2. The arithmetic processing circuit according to claim 1, wherein the input data are data containing array data, the recognition neural network includes: a generation circuit to generate reduced array data from the array data, being configured by connecting, at a plurality of stages, one or more pairs of: a computing circuit to generate a first partial array by a sum-of-product computation of elements contained in part of the array data and the coefficient corresponding to the elements per part of the array data and by a predetermined function computation; and a subsampling circuit to generate a second partial array by subsampling the elements from the first partial array generated per part of the array data; and an output circuit to compute a sum of product of elements of the reduced array data and a coefficient corresponding to the elements of the reduced array data, and to output an output value with a predetermined function computation, and the learning neural network includes: a comparison circuit to compare the recognition result serving as the reference with respect to the input data serving as the reference with an output value from the output circuit; and a coefficient generation circuit configured by connecting, at a plurality of stages, one or more pairs of: a backward propagation computing circuit provided corresponding to the output circuit and respective stages of the generation circuits, and configured to generate a coefficient to be handed over to the output circuit and to each stage and a differential value of a first partial array on a basis of the differential value given by the comparison result of the comparison circuit; and a restoration circuit to restore the first partial array on a basis of associative relational information representing an associative relation of the subsampling for generating the second partial array from the partial array, and the generated differential values. 3. The arithmetic processing circuit according to claim 2, wherein each stage of the recognition neural network hands over the associative relational information, the first partial array generated by the computing circuit at each stage and the coefficient used in the computing circuit at each stage of the recognition neural network to the computing circuit at each stage of the learning neural network at predetermined operation timing, each stage of the learning neural network hands over the coefficient generated by the computing circuit at each stage of the learning neural network to the computing circuit at each stage of the recognition neural network at the predetermined operation timing, and the memory includes: a first FIFO (First In First Out) circuit to hand over the associative relational information, the first partial array and the coefficient at first operation timing to each stage of the learning neural network from each stage of the recognition neural network; and a second FIFO (First In First Out) circuit to hand over the coefficient at second operation timing to each stage of the recognition neural network from each stage of the learning neural network. 4. The arithmetic processing circuit according to claim 3, wherein each stage of the learning neural network includes: a variation generation circuit to generate a variation of the coefficient from the first partial array generated at each stage of the recognition neural network and the differential value in the first partial array; and an update circuit to generate a coefficient to be handed over to each stage of the recognition neural network by sequentially integrating generated variations. 5. An information processing apparatus comprising: a processor; a first memory; and an arithmetic processing circuit, the arithmetic processing circuit including: a first layer configured to dispose a learning neural network to compute a coefficient to be set in a recognition neural network, wherein the recognition neural network is configured to recognize input data from the first memory by using the coefficient computed on a basis of a recognition result of the recognition neural network with respect to the input data serving as a reference for computing the coefficient and a recognition result serving as a reference with respect to the input data serving as the reference in accordance with control of the processor; a second layer configured to dispose the recognition neural network to recognize the input data by the coefficient computed by the learning neural network; and a third layer disposed between the first layer and the second layer, and configured to dispose a second memory connected to both of the learning neural network and the recognition neural network.