A three-dimensional integration of synapse circuitry is formed. One or more neuron layers each comprises a plurality of computing elements, and one or more synapse layers each comprising an array of memory elements are formed on top of the one or more neuron layers. A plurality of staggered through-silicon vias (TSVs) connect the one or more neuron layers to the one or more synapse layers and operate as communication links between one or more computing elements in the one or more neuron layers and one or more memory elements in the one or more synapse layers.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A method comprising: forming one or more neuron layers comprising a plurality of computing elements; forming on top of the one or more neuron layers one or more synapse layers each comprising an array of memory elements; and forming a plurality of staggered through-silicon vias (TSVs) connecting the one or more neuron layers to the one or more synapse layers; wherein the plurality of staggered TSVs operate as communication links between one or more computing elements in the one or more neuron layers and one or more memory elements in the one or more synapse layers. 2. The method of claim 1, wherein the plurality of staggered TSVs are formed in an outer perimeter of the one or more synapse layers. 3. The method of claim 2, wherein the plurality of staggered TSVs are formed in the outside perimeter in a zigzag manner wherein alternating rows and columns of the array of memory elements are connected to the TSVs in respective opposite sides. 4. The method of claim 1, wherein at least one of the synapse layers comprise a plurality of arrays of memory elements wherein the plurality of staggered TSVs are formed in an outer perimeter and through and between each of the plurality of arrays of memory elements. 5. The method of claim 1, further comprising forming a plurality of staggered TSVs wherein each plurality of staggered TSVs connect to respective synapse layer, and wherein each plurality of staggered TSVs are vertically staggered. 6. The method of claim 1, wherein two or more of the synapse layers are heterogeneous synapse layers wherein at least one synapse layer comprises an array of memory elements comprising a first type of memory elements from one of phase-change memory (PCM) elements, resistive random-access memory (RRAM) elements and complementary metal-oxide semiconductor (CMOS) memory elements, and at least one other synapse layer comprises an array of memory elements comprising a second type of memory elements from one of PCM elements, RRAM elements and CMOS memory elements different than the first type of memory elements. 7. The method of claim 1, wherein the array of memory elements is a heterogeneous array of memory elements comprising two or more of phase-change memory (PCM) elements, resistive random-access memory (RRAM) elements and complementary metal-oxide semiconductor (CMOS) memory elements. 8. The method of claim 1, further comprising forming a redistribution layer on top of the one or more neuron layers wherein in the redistribution layer, the plurality of staggered TSVs are selectively coupled to the one or more computing elements of the one or more neuron layers. 9. The method of claim 1, further comprising repeating the forming steps to form a plurality of one or more neuron layers and the plurality of one or more neuron layers each comprising a respective set of one or more synapse layers each comprising an array of memory elements wherein the plurality of staggered TSVs operate as communication links between one or more computing elements in any one of the neuron layers and one or more memory elements in any one of the synapse layers. 10. An apparatus, comprising: one or more neuron layers each comprising a plurality of computing elements; one or more synapse layers formed on top of the one or more neuron layers wherein each of the one or more synapse layers comprises an array of memory elements; and a plurality of staggered through-silicon vias (TSVs) connecting the one or more neuron layers to the one or more synapse layers; wherein the plurality of staggered TSVs operate as communication links between one or more computing elements in the one or more neuron layers and one or more memory elements in the one or more synapse layers. 11. The apparatus of claim 10, wherein the plurality of staggered TSVs are formed in an outer perimeter of the one or more synapse layers. 12. The apparatus of claim 11, wherein the plurality of staggered TSVs are formed in the outside perimeter in a zigzag manner wherein alternating rows and columns of the array of memory elements are connected to the TSVs in respective opposite sides. 13. The apparatus of claim 10, wherein at least one of the synapse layers comprise a plurality of arrays of memory elements wherein the plurality of TSVs are staggered in outer perimeters of each of the plurality of arrays of memory elements. 14. The apparatus of claim 10, further comprising a plurality of staggered TSVs wherein each plurality of staggered TSVs connect to respective synapse layer, and wherein each plurality of staggered TSVs are vertically staggered. 15. The apparatus of claim 10, wherein two or more of the synapse layers are heterogeneous synapse layers wherein at least one synapse layer comprises an array of memory elements comprising a first type of memory elements from one of phase-change memory (PCM) elements, resistive random-access memory (RRAM) elements and complementary metal-oxide semiconductor (CMOS) memory elements, and at least one other synapse layer comprises an array of memory elements comprising a second type of memory elements from one of PCM elements, RRAM elements and CMOS memory elements different than the first type of memory elements. 16. The apparatus of claim 10, wherein the array of memory elements is a heterogeneous array of memory elements comprising two or more of phase-change memory (PCM) elements, resistive random-access memory (RRAM) elements and complementary metal-oxide semiconductor (CMOS) memory elements. 17. The apparatus of claim 10, further comprising a redistribution layer formed on top of the one or more neuron layers wherein in the redistribution layer, the plurality of TSVs are selectively coupled to one or more computing elements of the one or more neuron layers. 18. The apparatus of claim 10, further comprising a plurality of one or more neuron layers and the plurality of one or more neuron layers each comprising a respective set of one or more synapse layers each comprising an array of memory elements wherein the plurality of staggered TSVs operate as communication links between one or more computing elements in any one of the neuron layers and one or more memory elements in any one of the synapse layers. 19. A method comprising: forming a synapse chip core layer; forming on top of the synapse chip core layer one or more paralleled synapse circuit layers wherein each of the one or more paralleled synapse circuit layers comprises an array of synapse circuits; and forming a plurality of staggered through-silicon vias (TSVs) connecting each of the paralleled synapse circuit layers to the synapse chip core layer; wherein the plurality of staggered TSVs operate as communication links between the synapse chip core layer and each of the one or more paralleled synapse circuit layers. 20. An integrated circuit formed via the steps of claim 19.