A neural network unit has a first memory that holds elements of a data matrix and a second memory that holds elements of a convolution kernel. An array of neural processing units (NPU) each have a multiplexed register that receives a corresponding element of a row from the first memory and that also receives the multiplexed register output of an adjacent NPU. A register receives a corresponding element of a row from the second memory. An arithmetic unit receives the outputs of the register, the multiplexed register and an accumulator and performs a multiply-accumulate operation on them. For each sub-matrix of a plurality of sub-matrices of the data matrix, each arithmetic unit selectively receives either the element from the first memory or the adjacent NPU multiplexed register output and performs a series of the multiply-accumulate operations to accumulate into the accumulator a convolution of the sub-matrix with the convolution kernel.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A neural network unit, comprising: a first memory that holds elements of a data matrix; a second memory that holds elements of a convolution kernel; an array of neural processing units (NPU) coupled to the first and second memories, each NPU having: a multiplexed register that has an output and that receives a corresponding element of a row from the first memory and that also receives the multiplexed register output of an adjacent NPU; a register that has an output and that receives a corresponding element of a row from the second memory; an accumulator that has an output; and an arithmetic unit that receives the outputs of the register, the multiplexed register and the accumulator and that performs a multiply-accumulate operation on them; and for each sub-matrix of a plurality of sub-matrices of the data matrix, each of the arithmetic units selectively receives either the element from the first memory or the adjacent NPU multiplexed register output and performs a series of the multiply-accumulate operations to accumulate into the accumulator a convolution of the sub-matrix with the convolution kernel. 2. The neural network unit of claim 1, further comprising: the neural network unit writes the convolutions of the plurality of sub-matrices to the first or second memory. 3. The neural network unit of claim 1, further comprising: a processor comprises the neural network unit; the processor includes architectural registers; and the processor executes architectural instructions of an instruction set of the processor to write the data matrix to the first memory from the architectural registers and to write the convolution kernel from the architectural registers to the second memory and to read the convolutions from the first or second memory into the architectural registers. 4. The neural network unit of claim 1, further comprising: the array of NPUs comprises N NPUs; the convolution kernel is a K×K matrix, and each sub-matrix is a K×K matrix; and the data matrix is a J×N matrix, and each of J rows of the first memory holds N elements of a different row of the J rows of the data matrix. 5. The neural network unit of claim 4, further comprising: the plurality of sub-matrices is approximately (J×N)/(K×K) sub-matrices. 6. The neural network unit of claim 4, further comprising: each of K×K rows of the second memory holds N instances of a different one of the K×K elements of the convolution kernel in row-major order. 7. The neural network unit of claim 6, further comprising: (a) the neural network unit initializes a first row address to point to the first row of the data matrix in the first memory; (b) the NPUs clear the accumulator to zero; (c) the neural network unit initializes a second row address to point to the first row of the K×K rows in the second memory; (d) for each iteration of K iterations: for one instance: the multiplexed registers receive from the first memory the row of data matrix elements pointed to by the first row address for provision to the arithmetic unit, and the first row address is incremented; the registers receive from the second memory the row of convolution kernel elements pointed to by the second row address for provision to the arithmetic unit, and the second row address is incremented; and the arithmetic units perform the multiply-accumulate operations; and for K−1 instances: the multiplexed registers receive the multiplexed register output of the adjacent NPU for provision to the arithmetic unit; and the registers receive from the second memory the row of convolution kernel elements pointed to by the second row address for provision to the arithmetic unit, and the neural network unit increments the second row address; and the arithmetic units perform the multiply-accumulate operations. 8. The neural network unit of claim 7, further comprising: (e) the neural network unit writes the convolutions to a row of the first or second memory; and (f) the first row address is decremented by K−2. 9. The neural network unit of claim 8, further comprising: the neural network unit performs steps (b) through (f) for approximately J iterations. 10. The neural network unit of claim 8, further comprising: at step (e), the NPUs also perform a divide operation on the convolutions and the results of the divide operation are written to the row of the first or second memory rather than the convolutions. 11. A method for operating a neural network unit having an array of neural processing units (NPU) each having a multiplexed register that has an output and that receives a corresponding element of a row from the first memory and that also receives the multiplexed register output of an adjacent NPU, a register that has an output and that receives a corresponding element of a row from the second memory, an accumulator that has an output, and an arithmetic unit that receives the outputs of the register, the multiplexed register and the accumulator and that performs a multiply-accumulate operation on them, the method comprising: holding, by a first memory, elements of a data matrix; holding, by a second memory, elements of a convolution kernel; for each sub-matrix of a plurality of sub-matrices of the data matrix: selectively receiving, by each of the arithmetic units, either the element from the first memory or the adjacent NPU multiplexed register output; and performing a series of the multiply-accumulate operations to accumulate into the accumulator a convolution of the sub-matrix with the convolution kernel. 12. The method of claim 11, further comprising: writing the convolutions of the plurality of sub-matrices to the first or second memory. 13. The method of claim 11, further comprising: a processor comprises the neural network unit; the processor includes architectural registers; and executing, by the processor, architectural instructions of an instruction set of the processor to write the data matrix to the first memory from the architectural registers and to write the convolution kernel from the architectural registers to the second memory and to read the convolutions from the first or second memory into the architectural registers. 14. The method of claim 11, further comprising: the array of NPUs comprises N NPUs; the convolution kernel is a K×K matrix, and each sub-matrix is a K×K matrix; and the data matrix is a J×N matrix, and each of J rows of the first memory holds N elements of a different row of the J rows of the data matrix. 15. The method of claim 14, further comprising: the plurality of sub-matrices is approximately (J×N)/(K×K) sub-matrices. 16. The method of claim 14, further comprising: each of K×K rows of the second memory holds N instances of a different one of the K×K elements of the convolution kernel in row-major order. 17. The method of claim 16, further comprising: (a) initializing a first row address to point to the first row of the data matrix in the first memory; (b) clearing the accumulator to zero; (c) initializing a second row address to point to the first row of the K×K rows in the second memory; (d) for each iteration of K iterations: for one instance: receiving, by the multiplexed registers, from the first memory the row of data matrix elements pointed to by the first row address for provision to the arithmetic unit, and incrementing the first row address; receiving, by the registers, from the second memory the row of convolution kernel elements pointed to by the second row address for provision to the arithmetic unit, and incrementing the second row address; and performing, by the arithmetic units, the multiply-accumulate operations; and for K−1 instances: receiving, by the multiplexed registers, the multiplexed register output of the adjacent NPU for provision to the arithmetic unit; and receiving, by the registers, from the second memory the row of convolution kernel elements pointed to by the second row address for provision to the arithmetic unit, and incrementing the second row address; and performing, by the arithmetic units, the multiply-accumulate operations. 18. The method of claim 17, further comprising: (e) writing the convolutions to a row of the first or second memory; and (f) decrementing the first row address by K−2. 19. The method of claim 18, further comprising: performing steps (b) through (f) for approximately J iterations. 20. The method of claim 18, further comprising: at step (e), also performing a divide operation on the convolutions and writing the results of the divide operation to the row of the first or second memory rather than the convolutions. 21. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising: computer usable program code embodied in said medium, for specifying a neural network unit, the computer usable program code comprising: first program code for specifying a first memory that holds elements of a data matrix; second program code for specifying a second memory that holds elements of a convolution kernel; third program code for specifying an array of neural processing units (NPU) coupled to the first and second memories, each NPU having: a multiplexed register that has an output and that receives a corresponding element of a row from the first memory and that also receives the multiplexed register output of an adjacent NPU; a register that has an output and that receives a corresponding element of a row from the second memory; an accumulator that has an output; and an arithmetic unit that receives the outputs of the register, the multiplexed register and the accumulator and that performs a multiply-accumulate operation on them; and for each sub-matrix of a plurality of sub-matrices of the data matrix, each of the arithmetic units selectively receives either the element from the first memory or the adjacent NPU multiplexed register output and performs a series of the multiply-accumulate operations to accumulate into the accumulator a convolution of the sub-matrix with the convolution kernel.