Programmable devices, hierarchical parallel machines and methods for providing state information are described. In one such programmable device, programmable elements are provided. The programmable elements are configured to implement one or more finite state machines. The programmable elements are configured to receive an N-digit input and provide a M-digit output as a function of the N-digit input. The M-digit output includes state information from less than all of the programmable elements. Other programmable devices, hierarchical parallel machines and methods are also disclosed.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A programmable device comprising: a plurality of programmable elements, wherein the programmable elements are configured to implement one or more finite state machines, wherein the plurality of programmable elements are configured to receive a N-digit input and provide a M-digit output as a function of the N-digit input, wherein the M-digit output includes state information from less than all of the programmable elements. 2. The programmable device of claim 1, wherein the plurality of programmable elements comprises one of two or more groups of programmable elements. 3. The programmable device of claim 2, further comprising: a N-digit input interface coupled to the one group of programmable elements and configured to receive the N-digit input; and a M-digit output interface coupled to the one group of programmable elements and configured to provide the M-digit output. 4. The programmable device of claim 2, wherein the one group of programmable elements comprises a block of programmable elements. 5. The programmable device of claim 4, wherein the block of programmable elements comprises a plurality of rows of programmable elements, wherein each of the rows is coupled to a respective one of a plurality of intra-block switches. 6. The programmable device of claim 5, wherein the programmable elements in each of the rows comprises: a plurality of groups of two state machine elements; and another programmable element. 7. The programmable device of claim 2, further comprising: a programmable switch configured to selectively couple the one group of programmable elements to another one of the groups of programmable elements, an input port, and/or an output port. 8. The programmable device of claim 7, further comprising: a register configured to store a program configured to program the plurality of programmable elements and the plurality of programmable switches. 9. The programmable device of claim 1, wherein N equals M. 10. The programmable device of claim 1, wherein M is an integer multiple of N. 11. The programmable device of claim 1, further comprising: OR logic configured to aggregate output from two or more of the programmable elements used to implement a same one of the finite state machines. 12. The programmable device of claim 11, wherein the programmable elements are configured to implement a logical group of N state machines, wherein the outputs of the N state machines are aggregated to provide the M-digit output. 13. The programmable device of claim 11, wherein the logic comprises an OR gate. 14. The programmable device of claim 1, wherein the state information included in the M-digit output comprises compressed state information. 15. The programmable device of claim 1, wherein the plurality of programmable elements comprise state machine elements. 16. The programmable device of claim 1, wherein the M-digit output comprises a difference vector. 17. The programmable device of claim 16, wherein each state in the implemented one or more finite state machines corresponds to a respective digit in a state vector, and wherein the difference vector includes only those digits in the state vector that change in response to an input symbol provided to the programmable device. 18. The programmable device of claim 1, wherein each state in the implemented one or more finite state machines corresponds to a respective digit in a state vector, and wherein the M-digit output comprises only a subset of the digits in the state vector. 19. The programmable device of claim 1, wherein the subset of the digits comprises those digits corresponding to final states in the one or more finite state machines. 20. The programmable device of claim 1, wherein all state machines implemented in the device receive the N-digit input. 21. The programmable device of claim 1, wherein the plurality of programmable elements comprise one of two or more groups of programmable elements, wherein each of the groups has its own dedicated input. 22. The programmable device of claim 1, wherein the N-digit input is on a bottom of a semiconductor die, and wherein the M-digit output is on a top of the semiconductor die. 23. The programmable device of claim 1, wherein the plurality of programmable elements comprise one of two or more groups of programmable elements, and wherein the programmable device is configured to provide state information from one of the groups to another one of the groups in the programmable device. 24. A programmable device comprising: a plurality of programmable elements wherein the programmable elements are configured to implement one or more finite state machines, wherein the plurality of programmable elements are configured to receive a N-digit input and provide a M-digit output as a function of the N-digit input, wherein the M-digit output is formed by compressing state information from each of the programmable elements. 25. The programmable device of claim 24, wherein N equals M. 26. The programmable device of claim 24, wherein M is an integer multiple of N. 27. The programmable device of claim 24, further comprising: logic configured to aggregate output from two or more of the programmable elements used to implement a same one of the finite state machines. 28. The programmable device of claim 27, wherein the programmable elements are configured to implement a logical group of N state machines, wherein the outputs of the N state machines are aggregated to provide the M-digit output.