Systems and methods for event-driven learning with spike timing dependent plasticity in neuromorphic computers are disclosed. A neuromorphic processor includes a synapse coupled to a pre-synaptic neuron and coupled to a post-synaptic neuron, the synapse including a synapse memory to store a synapse weight and synapse spike timing dependent plasticity (STDP) circuit coupled to the synapse memory. The pre-synaptic neuron includes a pre-synaptic neuron memory to store a pre-synaptic neuron spike history and a pre-synaptic neuron STDP circuit coupled to the pre-synaptic neuron memory, the pre-synaptic neuron STDP circuit to, in response to the pre-synaptic neuron firing, initiate performing long term potentiation. The post-synaptic neuron includes a post-synaptic neuron memory storing a post-synaptic neuron spike history and a post-synaptic neuron STDP circuit coupled to the post-synaptic neuron memory to, in response to the post-synaptic neuron firing, initiate performing long term depression.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A neuromorphic processor, comprising: a synapse coupled to a pre-synaptic neuron and coupled to a post-synaptic neuron, the synapse including: a synapse memory to store a synapse weight; a synapse spike timing dependent plasticity (STDP) circuit coupled to the synapse memory; the pre-synaptic neuron including: a pre-synaptic neuron memory to store a pre-synaptic neuron spike history; and a pre-synaptic neuron STDP circuit coupled to the pre-synaptic neuron memory, the pre-synaptic neuron STDP circuit to, in response to the pre-synaptic neuron firing, initiate performing long term depression; the post-synaptic neuron including: a post-synaptic neuron memory storing a post-synaptic neuron spike history; a post-synaptic neuron STDP circuit coupled to the post-synaptic neuron memory to, in response to the post-synaptic neuron firing, initiate performing long term potentiation. 2. The neuromorphic processor of claim 1, wherein, as part of performing long term potentiation, the post-synaptic neuron STDP circuit is further to: overwrite the post-synaptic neuron spike history with a maximum value; transmit a signal indicating that the post-synaptic neuron has fired to the pre-synaptic neuron STDP circuit; the pre-synaptic neuron STDP circuit is further to: retrieve the pre-synaptic neuron spike history from the pre-synaptic neuron memory; determine a post-synaptic neuron spike history based on receiving the signal indicating that the post-synaptic neuron has fired; calculate a synapse weight offset based on the pre-synaptic neuron spike history and the post-synaptic neuron spike history; transmit the synapse weight offset to the synapse STDP circuit; and the synapse STDP circuit is further to update the synapse weight based on the synapse weight offset. 3. The neuromorphic processor of claim 1, wherein, as part of performing long term depression: the pre-synaptic neuron STDP circuit is further to: overwrite the pre-synaptic neuron spike history with a maximum value; transmit a signal indicating that the pre-synaptic neuron has fired to the post-synaptic neuron STDP circuit; the post-synaptic neuron STDP circuit is further to: retrieve the post-synaptic neuron spike history from the post-synaptic neuron memory; determine a pre-synaptic neuron spike history based on receiving the signal indicating that the pre-synaptic neuron has fired; calculate a synapse weight offset based on the pre-synaptic neuron spike history and the post-synaptic neuron spike history; transmit the synapse weight offset to the synapse STDP circuit; and the synapse STDP circuit is further to update the synapse weight based on the synapse weight offset. 4. The neuromorphic processor of claim 3, wherein the synapse is to transmit the signal indicating that the pre-synaptic neuron has fired to the pre-synaptic neuron. 5. The neuromorphic processor of claim 4, wherein a network on chip is to transmit the signal indicating that the pre-synaptic neuron has fired to the pre-synaptic neuron. 6. The neuromorphic processor of claim 2, further comprising: a reward-based STDP circuit coupled to the post-synaptic neuron, the reward-based STDP circuit to transmit a neuron reward value to the post-synaptic neuron STDP circuit; wherein the post-synaptic neuron STDP circuit is further to, as part of performing long term potentiation, transmit the neuron reward value to the pre-synaptic neuron STDP circuit; and wherein the pre-synaptic neuron STDP circuit is further to, as part of performing long term potentiation, multiply the synapse weight offset by the neuron reward value prior to transmitting the synapse weight offset to the synapse STDP circuit. 7. The neuromorphic processor of claim 3, further comprising a reward-based STDP circuit coupled to the post-synaptic neuron, the reward-based STDP circuit to transmit a neuron reward value to the post-synaptic neuron STDP circuit; wherein the post-synaptic neuron STDP circuit is further to, as part of performing long term depression, multiply the synapse weight offset by the neuron reward value prior to transmission of the synapse weight offset to the synapse STDP circuit. 8. A neuromorphic processor logic unit, comprising: a synapse coupled to a pre-synaptic neuron and coupled to a post-synaptic neuron; the synapse including: a synapse memory to store a synapse weight; a synapse spike timing dependent plasticity (STDP) circuit coupled to the synapse memory; the pre-synaptic neuron including: a pre-synaptic neuron memory to store a pre-synaptic neuron spike history; and a pre-synaptic neuron STDP circuit coupled to the pre-synaptic neuron memory, the pre-synaptic neuron STDP circuit to, in response to the pre-synaptic neuron firing, initiate performing long term depression; the post-synaptic neuron including: a post-synaptic neuron memory storing a post-synaptic neuron spike history; a post-synaptic neuron STDP circuit coupled to the post-synaptic neuron memory to, in response to the post-synaptic neuron firing, initiate performing long term potentiation. 9. The neuromorphic processor logic unit of claim 8 wherein, as part of performing long term potentiation: the post-synaptic neuron STDP circuit is further to: overwrite the post-synaptic neuron spike history with a maximum value; transmit a signal indicating that the post-synaptic neuron has fired to the pre-synaptic neuron STDP circuit; the pre-synaptic neuron STDP circuit is further to: retrieve the pre-synaptic neuron spike history from the pre-synaptic neuron memory; determine a post-synaptic neuron spike history based on receiving the signal indicating that the post-synaptic neuron has fired; calculate a synapse weight offset based on the pre-synaptic neuron spike history and the post-synaptic neuron spike history; transmit the synapse weight offset to the synapse STDP circuit; and the synapse STDP circuit is further to update the synapse weight based on the synapse weight offset. 10. The neuromorphic processor logic unit of claim 8 wherein, as part of performing long term depression: the pre-synaptic neuron STDP circuit is further to: overwrite the pre-synaptic neuron spike history with a maximum value; transmit a signal indicating that the pre-synaptic neuron has fired to the post-synaptic neuron STDP circuit; the post-synaptic neuron STDP circuit is further to, retrieve the post-synaptic neuron spike history from the post-synaptic neuron memory; determine a pre-synaptic neuron spike history based on receiving the signal indicating that the pre-synaptic neuron has fired; calculate a synapse weight offset based on the pre-synaptic neuron spike history and the post-synaptic neuron spike history; transmit the synapse weight offset to the synapse STDP circuit; and the synapse STDP circuit is further to update the synapse weight based on the synapse weight offset. 11. The neuromorphic processor logic unit of claim 9 wherein the synapse is to transmit the signal indicating that the post-synaptic neuron has fired to the pre-synaptic neuron. 12. The neuromorphic processor logic unit of claim 10, wherein a network on chip is to transmit the signal indicating that the pre-synaptic neuron has fired to the pre-synaptic neuron. 13. The neuromorphic processor logic unit of claim 9, further comprising: a reward-based STDP circuit coupled to the post-synaptic neuron; the reward-based STDP circuit to transmit a neuron reward value to the post-synaptic neuron STDP circuit; wherein the post-synaptic neuron STDP circuit is further to, as part of performing long term potentiation, transmit the neuron reward value to the pre-synaptic neuron STDP circuit; and wherein the pre-synaptic neuron STDP circuit is further to, as part of performing long term potentiation, multiply the synapse weight offset by the neuron reward value prior to transmitting the synapse weight offset to the synapse STDP circuit. 14. The neuromorphic processor logic unit of claim 10, further comprising a reward-based STDP circuit coupled to the post-synaptic neuron; the reward-based STDP circuit to transmit a neuron reward value to the post-synaptic neuron STDP circuit; and wherein the post-synaptic neuron STDP circuit is further to, as part of performing long term depression, multiply the synapse weight offset by the neuron reward value prior to transmitting the synapse weight offset to the synapse STDP circuit. 15. A method, comprising, in a neuromorphic processor: receiving a plurality of neuron inputs with a plurality of neurons, the plurality of neurons including a plurality of pre-synaptic neurons and a plurality of post-synaptic neurons; processing the plurality of inputs with the plurality of input neurons; performing long term potentiation based on a determination that at least one of the plurality of post-synaptic neurons has fired; and performing long term depression based on a determination that at least one of the plurality of pre-synaptic neurons has fired. 16. The method of claim 15, wherein performing long term potentiation comprises: overwriting a post-synaptic neuron spike history with a maximum value; transmitting a signal indicating that the post-synaptic neuron has fired to a pre-synaptic neuron spike timing dependent plasticity (STDP) circuit in one of the plurality of pre-synaptic neurons; retrieving a pre-synaptic neuron spike history from a pre-synaptic neuron memory; determining a post-synaptic neuron spike history based on receiving the signal indicating that the post-synaptic neuron has fired; calculating a synapse weight offset based on the pre-synaptic neuron spike history and the post-synaptic neuron spike history; transmitting the synapse weight offset to a synapse STDP circuit; and updating the synapse weight based on the synapse weight offset. 17. The method of claim 15, wherein performing long term depression comprises: overwriting a pre-synaptic neuron spike history with a maximum value; transmitting a signal indicating that the pre-synaptic neuron has fired a post-synaptic neuron STDP circuit in one of the plurality of post-synaptic neurons; retrieving a post-synaptic neuron spike history from a post-synaptic neuron memory; determining a pre-synaptic neuron spike history based on receiving the signal indicating that the pre-synaptic neuron has fired; calculating a synapse weight offset based on the pre-synaptic neuron spike history and the post-synaptic neuron spike history; transmitting the synapse weight offset to the synapse STDP circuit; and updating the synapse weight based on the synapse weight offset. 18. The method of claim 16, further comprising: transmitting a neuron reward value to the pre-synaptic neuron STDP circuit; and multiplying the synapse weight offset by the neuron reward value prior to transmitting the synapse weight offset to the synapse STDP circuit. 19. The method of claim 17, further comprising: transmitting a neuron reward value to a post-synaptic neuron STDP circuit; and multiplying the synapse weight offset by the neuron reward value prior to transmitting the synapse weight offset to the synapse STDP circuit. 20. The method of claim 16, wherein the signal indicating that the post-synaptic neuron has fired is transmitted to the pre-synaptic neuron via a synapse.