A nonlinear neuron classifier comprising a neuron array including a plurality of neuron chips each including a plurality of neurons of variable length and variable depth, the chips processing input vectors of variable length and variable depth that are input into the classifier for comparison against vectors stored in the classifier, wherein an NSP flag is set for a plurality of the neurons to indicate that only that plurality of neurons is to participate in the vector calculations. A virtual content addressable memory flag is set for certain of the neuron chips to enable functions including fast readout of data from the chips. Results of vector calculations are aggregated for fast readout for a host computer interfacing with the classifier.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A nonlinear neuron classifier comprising: a neuron array that comprises a plurality of neurons that have variable component length and variable depth, and that processes an input vector of variable component length and variable component depth that is input into the classifier for comparison against vectors stored in the classifier; a system bus interface configured to detect and capture the input vector; logic that is connected in parallel to individual neurons in the classifier and that broadcasts the input vector concurrently to neurons that store vectors of similar component length and depth, for vector calculations; and storage configured as an internal status that accessible by hardware external to the classifier, the status and results table comprising a combination of registers of varied length configured to store each of the plurality of neurons relating to at least one context. 2. The nonlinear neuron classifier of claim 1 further comprising storage configured as internal local status and results registers that are accessible by hardware external to the classifier, the local status and results registers comprising a combination of registers of varied length configured to store results of vector calculations, each of the plurality of neurons relating to at least one context. 3. The nonlinear neuron classifier of claim 2 wherein the input vector is of a known context, a first plurality of the plurality of neurons relates to the known context and other neurons of the plurality of neurons relate to contexts other than the known context, wherein control logic sets a NSP flag for the first plurality of neurons, the NSP flag indicating that only the first plurality of neurons are to be selected for participation in the vector calculations. 4. The nonlinear neuron classifier of claim 3 wherein the control logic sets the NSP flag by a write command. 5. The nonlinear neuron classifier of claim 3 wherein each neuron has at least one of static information comprising context and category information, and dynamic information comprising vector calculation results, the control logic receives criteria from a user, the criteria comprising the vector calculation results of vectors for which the NSP flag has been set, and the control logic uses the user criteria to identify only the neurons for which the NSP flag has been set and that meet the vector calculation results. 6. The nonlinear neuron classifier of claim 3 wherein the NSP flag is set based on the results of a comparisons of a plurality of pairs of multi-bit registers, or based on testing a flag bit. 7. The nonlinear neuron classifier of claim 6 wherein the comparison of the plurality pairs of multi-bit registers comprises a first set of multiple mathematical comparisons and the flag bit comprises the current state of the NSP flag determined from previous results of mathematical comparisons. 8. The nonlinear neuron classifier of claim 6 wherein the input vector is broadcast for vector calculations with vectors having the NSP flag set, and the vector calculations are completed. 9. The nonlinear neuron classifier of claim 8 wherein a VCAM flag is set based on the results of comparisons of a second plurality of pairs of multi-bit registers, or based on testing a second flag bit. 10. The nonlinear neuron classifier of claim 9 wherein the comparison of the plurality pairs of multi-bit registers comprises a first set of multiple mathematical comparisons and the flag bit comprises the current state of the VCAM flag determined from previous results of mathematical comparisons. 11. The nonlinear neuron classifier of claim 9 wherein neuron IDs are provided to users based on the setting of both the NSP flag and the VCAM flag in neurons. 12. The nonlinear neuron classifier of claim 9 wherein the value of distance registers are provided to users based on the setting of both the NSP flag and the VCAM flag in neurons. 13. The nonlinear neuron classifier of claim 9 wherein at least some of the plurality of neurons are arranged in groups of N neurons connected serially for outputting data to a data bus from at least some of the groups of N neurons, wherein the serial connection of groups include at least a prior group and a subsequent group in the serially connection of groups, wherein a VCAM flag signal from the prior group indicates that the prior group has data to output, and wherein the VCAM flag signal from the prior group is configured to prevent readout of data from the subsequent group until the prior group has completed outputting its data to the data bus. 14. The nonlinear neuron classifier of claim 13 wherein the groups of N neurons read out data according to a system clock wherein a first clock signal enables readout of data from the prior group and a second clock signal resets the VCAM flag signal of the prior group. 15. The nonlinear classifier of claim 1 wherein the neuron array comprises a plurality of neural network chips each comprising a plurality neurons, at least one input port and at least one output port, each chip comprising a search and sort function, the plurality of neural network chips being arranged in a plurality of tree levels comprising an arrangement of lowest tree level to highest tree level, wherein the at least one input port of each chip in a higher level is configured to collect results of vector calculations from the outputs of chips in a lower level, and wherein after completion of a vector calculation the search and sort function of each chip in the array finds the neuron in the chip having the closest or the exact match results of the vector calculation and provides, via its output port, to an input port of a chip at the next higher tree level, the search and sort result of said neuron having the closest or the exact match result, wherein said chip at the next higher tree level selects the neuron having the closest or the exact match result from among the at least one input port of said chip at the next higher tree level and the result of the search and sort function of said chip at the next higher tree level, until the chip at the highest tree level selects the neuron with the closest or the exact match result from among the at least one input port of said chip at the highest tree level and the result of the search and sort function of said chip at the highest tree level, and wherein said chip at the highest tree level receives a neuron address of the neuron having the closest or exact match result that is selected by the chip at the highest tree level and presents at least the result of the closest or exact match result for storage in a storage device that is accessible by hardware external to the classifier. 16. The nonlinear classifier of claim 15 wherein the neuron ID of the neuron having the closest or exact match result, and the chip ID that comprises said the neuron having the closest or exact match result, is presented for storage in the storage device that is accessible by hardware external to the classifier. 17. The nonlinear classifier of claim 15 wherein a chip in the array receives a signal indicating that its provided search and sort result was the closest or exact match result from the vector calculation and, responsive to receiving the signal, said chip in the array removes the neuron having the closest or exact match result from further results search and sort, and immediately begins another search and sort to locate the next closest or exact match result. 18. The nonlinear classifier of claim 15 wherein search and sort results are from a vector calculation comprising a mathematical comparison of the input vector and the contents of any register of the status and results registers. 19. The nonlinear classifier of claim 15 wherein the search and sort results are presented in one of ascending order or descending order. 20. The nonlinear classifier of claim 15 wherein the search and sort results are presented on a parallel busing having signals comprising a data function, a line valid function, and a winner function. 21. The nonlinear classifier of claim 15 wherein the search and sort results are presented on a serial bus that is designated as a high-speed serial bus.