A neural network unit configurable to first/second/third configurations has N narrow and N wide accumulators, multipliers and adders. Each multiplier performs a narrow/wide multiply on first and second narrow/wide inputs to generate a narrow/wide product. A first adder input receives a corresponding narrow/wide accumulator's output and third input receives a widened corresponding narrow multiplier's narrow product in the third configuration. In the first configuration, each narrow/wide adder performs a narrow/wide addition on the first and second inputs to generate a narrow/wide sum for storage into the corresponding narrow/wide accumulator. In the second configuration, each wide adder performs a wide addition on the first and a second input to generate a wide sum for storage into the corresponding wide accumulator. In the third configuration, each wide adder performs a wide addition on the first, second and third inputs to generate a wide sum for storage into the corresponding wide accumulator.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A neural network unit, comprising: a register programmable with an indicator that specifies first, second and third configurations; N narrow and N wide accumulators each having an output; N narrow and N wide multipliers each having first and second narrow/wide inputs upon which it performs a narrow/wide multiply operation to generate a narrow/wide product, respectively; N narrow and N wide adders each having first and second inputs, the first input receives the output of a corresponding one of the N narrow/wide accumulators, respectively; the N wide adders each also having a third input, the third input receives a widened version of the narrow product of a corresponding one of the N narrow multipliers when the indicator indicates the third configuration; when the indicator indicates the first configuration, each of the N narrow/wide adders performs a narrow/wide addition operation on the first and second inputs to generate a narrow/wide sum for storage into the corresponding narrow/wide accumulator, respectively; when the indicator indicates the second configuration, each of the N wide adders performs a wide addition operation on the first and second inputs to generate a wide sum for storage into the corresponding wide accumulator; and when the indicator indicates the third configuration, each of the N wide adders performs a wide addition operation on the first, second and third inputs to generate a wide sum for storage into the corresponding wide accumulator. 2. The neural network unit of claim 1, further comprising: first and second memories that provide operands for reception by the first and second inputs of the multipliers, respectively; when the indicator specifies the first and third configurations, each of the first and second memories provides 2N narrow operands; and when the indicator specifies the second configuration, each of the first and second memories provides N wide operands. 3. The neural network unit of claim 2, further comprising: 2N multiplexed registers each having narrow first, second and third data inputs, a narrow output and a control input that controls selection of the first, second and third data inputs; for each of the 2N multiplexed registers: the first input receives a narrow operand from the first memory; the second input receives the output of an adjacent one of the 2N multiplexed registers; and the third input receives the output of a next-adjacent one of the 2N multiplexed registers. 4. The neural network unit of claim 3, further comprising: when the indicator specifies the first and third configurations, the control input selects either the first input or the second input for provision on the output and the 2N multiplexed registers collectively operate as a 2N narrow word rotator; and when the indicator specifies the second configuration, the control input selects either the first input or the third input for provision on the output and the 2N multiplexed registers collectively operate as an N wide word rotator. 5. The neural network unit of claim 4, further comprising: operation selection logic that receives 2N narrow operands provided by the 2N multiplexed register outputs and that receives 2N narrow operands provided by the second memory; when the indicator specifies the first and third configurations, the operand selection logic: provides, to the first input of the N wide multipliers, N of the 2N narrow operands provided by N of the 2N multiplexed register outputs; provides, to the first input of the N narrow multipliers, the other N of the 2N narrow operands provided by the other N of the 2N multiplexed register outputs; provides, to the second input of the N wide multipliers, N of the 2N narrow operands provided by the second memory; and provides, to the second input of the N narrow multipliers, the other N of the 2N narrow operands provided by the second memory; and when the indicator specifies the second configuration, the operand selection logic: concatenates adjacent ones of the 2N narrow operands provided by the 2N multiplexed register outputs to produce N wide operands for provision to the first input of the N wide multipliers; and concatenates adjacent ones of the 2N narrow operands provided by the second memory to produce N wide operands for provision to the second input of the N wide multipliers. 6. The neural network unit of claim 1, further comprising: when the indicator specifies the first and third configurations, the operand selection logic: widens the N of the 2N narrow operands provided by N of the 2N multiplexed register outputs in order to provide them to the first input of the N wide multipliers; and widens the other N of the 2N narrow operands provided by the second memory in order to provide them to the second input of the N wide multipliers. 7. The neural network unit of claim 1, further comprising: a plurality of activation function units that perform an activation function on the sums stored in the accumulators to generate results; when the indicator specifies the first and third configurations, the plurality of activation function units generate narrow results; and when the indicator specifies the second configuration, the plurality of activation function units generate wide results. 8. The neural network unit of claim 1, further comprising: the wide inputs are twice the width of the narrow inputs. 9. A method for operating a neural network unit having: a register programmable with an indicator that specifies first, second and third configurations; N narrow and N wide accumulators each having an output; N narrow and N wide multipliers each having first and second narrow/wide inputs upon which it performs a narrow/wide multiply operation to generate a narrow/wide product, respectively; N narrow and N wide adders each having first and second inputs, the first input receives the output of a corresponding one of the N narrow/wide accumulators, respectively; and the N wide adders each also having a third input, the third input receives a widened version of the narrow product of a corresponding one of the N narrow multipliers when the indicator indicates the third configuration, the method comprising: performing, by each of the N narrow/wide adders, a narrow/wide addition operation on the first and second inputs to generate a narrow/wide sum for storage into the corresponding narrow/wide accumulator, respectively, when the indicator indicates the first configuration; performing, by each of the N wide adders, a wide addition operation on the first and second inputs to generate a wide sum for storage into the corresponding wide accumulator, when the indicator indicates the second configuration; and performing, by each of the N wide adders, a wide addition operation on the first, second and third inputs to generate a wide sum for storage into the corresponding wide accumulator, when the indicator indicates the third configuration. 10. The method of claim 9, further comprising: the neural network unit also has first and second memories that provide operands for reception by the first and second inputs of the multipliers, respectively; providing, by each of the first and second memories, 2N narrow operands, when the indicator specifies the first and third configurations; and providing, by each of the first and second memories, N wide operands, when the indicator specifies the second configuration. 11. The method of claim 10, further comprising: the neural network unit also has 2N multiplexed registers each having narrow first, second and third data inputs, a narrow output and a control input that controls selection of the first, second and third data inputs; for each of the 2N multiplexed registers: the first input receives a narrow operand from the first memory; the second input receives the output of an adjacent one of the 2N multiplexed registers; and the third input receives the output of a next-adjacent one of the 2N multiplexed registers. 12. The method of claim 11, further comprising: selecting, by the control input, either the first input or the second input for provision on the output and the 2N multiplexed registers collectively operate as a 2N narrow word rotator, when the indicator specifies the first and third configurations; and selecting, by the control input, either the first input or the third input for provision on the output and the 2N multiplexed registers collectively operate as an N wide word rotator, when the indicator specifies the second configuration. 13. The method of claim 12, further comprising: the neural network unit also has operation selection logic that receives 2N narrow operands provided by the 2N multiplexed register outputs and that receives 2N narrow operands provided by the second memory; when the indicator specifies the first and third configurations: providing, by the operand selection logic to the first input of the N wide multipliers, N of the 2N narrow operands provided by N of the 2N multiplexed register outputs; providing, by the operand selection logic to the first input of the N narrow multipliers, the other N of the 2N narrow operands provided by the other N of the 2N multiplexed register outputs; providing, by the operand selection logic to the second input of the N wide multipliers, N of the 2N narrow operands provided by the second memory; and providing, by the operand selection logic to the second input of the N narrow multipliers, the other N of the 2N narrow operands provided by the second memory; and when the indicator specifies the second configuration: concatenating, by the operand selection logic, adjacent ones of the 2N narrow operands provided by the 2N multiplexed register outputs to produce N wide operands for provision to the first input of the N wide multipliers; and concatenating, by the operand selection logic, adjacent ones of the 2N narrow operands provided by the second memory to produce N wide operands for provision to the second input of the N wide multipliers. 14. The method of claim 9, further comprising: when the indicator specifies the first and third configurations: widening, by the operand selection logic, the N of the 2N narrow operands provided by N of the 2N multiplexed register outputs in order to provide them to the first input of the N wide multipliers; and widening, by the operand selection logic, the other N of the 2N narrow operands provided by the second memory in order to provide them to the second input of the N wide multipliers. 15. The method of claim 9, further comprising: the neural network unit also has a plurality of activation function units that perform an activation function on the sums stored in the accumulators to generate results; generating, by the plurality of activation function units, narrow results, when the indicator specifies the first and third configurations; and generating, by the plurality of activation function units, wide results, when the indicator specifies the second configuration. 16. The method of claim 9, further comprising: the wide inputs are twice the width of the narrow inputs. 17. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising: computer usable program code embodied in said medium, for specifying a neural network unit, the computer usable program code comprising: first program code for specifying a register programmable with an indicator that specifies first, second and third configurations; second program code for specifying N narrow and N wide accumulators each having an output; third program code for specifying N narrow and N wide multipliers each having first and second narrow/wide inputs upon which it performs a narrow/wide multiply operation to generate a narrow/wide product, respectively; fourth program code for specifying N narrow and N wide adders each having first and second inputs, the first input receives the output of a corresponding one of the N narrow/wide accumulators, respectively; the N wide adders each also having a third input, the third input receives a widened version of the narrow product of a corresponding one of the N narrow multipliers when the indicator indicates the third configuration; when the indicator indicates the first configuration, each of the N narrow/wide adders performs a narrow/wide addition operation on the first and second inputs to generate a narrow/wide sum for storage into the corresponding narrow/wide accumulator, respectively; when the indicator indicates the second configuration, each of the N wide adders performs a wide addition operation on the first and second inputs to generate a wide sum for storage into the corresponding wide accumulator; and when the indicator indicates the third configuration, each of the N wide adders performs a wide addition operation on the first, second and third inputs to generate a wide sum for storage into the corresponding wide accumulator. 18. The computer program product of claim 17, further comprising: first and second memories that provide operands for reception by the first and second inputs of the multipliers, respectively; when the indicator specifies the first and third configurations, each of the first and second memories provides 2N narrow operands; and when the indicator specifies the second configuration, each of the first and second memories provides N wide operands. 19. The computer program product of claim 17, further comprising: when the indicator specifies the first and third configurations, the operand selection logic: widens the N of the 2N narrow operands provided by N of the 2N multiplexed register outputs in order to provide them to the first input of the N wide multipliers; and widens the other N of the 2N narrow operands provided by the second memory in order to provide them to the second input of the N wide multipliers. 20. The computer program product of claim 17, further comprising: a plurality of activation function units that perform an activation function on the sums stored in the accumulators to generate results; when the indicator specifies the first and third configurations, the plurality of activation function units generate narrow results; and when the indicator specifies the second configuration, the plurality of activation function units generate wide results.