Embodiments of the invention provide a neurosynaptic system comprising a delay unit for receiving and buffering axonal inputs, and a neural computation unit for generating neuronal outputs by performing a set of computations based on at least one axonal input received by the delay unit. The system further comprises a permutation unit for receiving external inputs to the system, and transmitting external outputs from the system. The permutation unit maps each external input received as either an axonal input to the delay unit or an external output from the system. The permutation unit maps each neuronal output generated by the neural computation unit as either an axonal input to the delay unit or an external output from the system. The neural computation unit comprises multiple electronic neurons, multiple electronic axons, and a plurality of electronic synapse devices interconnecting the neurons with the axons.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A neurosynaptic system, comprising: a delay unit for receiving and buffering one or more axonal inputs; a neural computation unit for generating one or more neuronal outputs by performing a set of computations based on at least one axonal input received by said delay unit; and a permutation unit for: receiving one or more external inputs to said system; transmitting one or more external outputs from said system; mapping each external input received as one of an axonal input to said delay unit and an external output from said system; and mapping each neuronal output generated by said neural computation unit as one of an axonal input to said delay unit and an external output from said system; wherein said neural computation unit comprises multiple electronic neurons, multiple electronic axons, and a plurality of electronic synapse devices interconnecting said multiple neurons with said multiple axons. 2. The system of claim 1, wherein said neural computation unit is reconfigurable. 3. The system of claim 1, wherein said permutation unit is reconfigurable. 4. The system of claim 1, wherein said delay unit is reconfigurable. 5. The system of claim 1, wherein: said neural computation unit includes a distributed and parallel set of neurosynaptic core circuits; and each neurosynaptic core circuit comprises multiple electronic neurons, multiple electronic axons, and a plurality of electronic synapse devices interconnecting said multiple neurons with said multiple axons. 6. The system of claim 5, wherein said permutation unit is implemented via an interconnection network interconnecting said set of neurosynaptic core circuits. 7. The system of claim 6, wherein: each neuronal output generated by said neural computation unit represents a neural firing of a neuron of a neurosynaptic core circuit; each neural firing of each neuron of each neurosynaptic core circuit is an event; and said interconnection network is event-driven. 8. The system of claim 7, wherein: each neurosynaptic core circuit has a corresponding packet router enabling inter-core routing; and said permutation unit utilizes each packet router of each neurosynaptic core circuit for mapping. 9. The system of claim 7, wherein: each neurosynaptic core circuit comprises a scheduler delay buffer for maintaining one or more axonal inputs for a pre-determined time delay; and said delay unit utilizes each scheduler delay buffer of each neurosynaptic core circuit for buffering. 10. The system of claim 1, wherein: said set of computations performed by said neural computation unit comprise one of feed-forward computations, recurrent computations, and a hybrid of feed-forward computations and recurrent computations. 11. The system of claim 1, wherein: said set of computations include at least one of an auto-regressive function, a linear function, and a non-linear function. 12. The system of claim 1, wherein: said system includes multiple interconnected computational blocks; each computation block comprises a corresponding permutation unit, a corresponding neural computation unit, and a corresponding delay unit; and each computational block receives at least one of an external input and a neuronal output generated by another computational block connected to said computational block. 13. A method for computing computational functions, comprising: receiving and buffering, via a delay unit, one or more axonal inputs; generating one or more neuronal outputs by performing, via a neural computation unit, a set of computations based on at least one axonal input received; receiving, via a permutation unit, one or more external inputs; transmitting, via said permutation unit, one or more external outputs; mapping, via said permutation unit, each external input received as one of an axonal input to said delay unit and an external output; and mapping, via said permutation unit, each neuronal output generated by said neural computation unit as one of an axonal input to said delay unit and an external output; wherein said neural computation unit comprises multiple electronic neurons, multiple electronic axons, and a plurality of electronic synapse devices interconnecting said multiple neurons with said multiple axons. 14. The method of claim 13, wherein at least one of said neural computation unit, said permutation unit and said delay unit is reconfigurable. 15. The method of claim 13, wherein: said neural computation unit includes a distributed and parallel set of neurosynaptic core circuits; and each neurosynaptic core circuit comprises multiple electronic neurons, multiple electronic axons, and a plurality of electronic synapse devices interconnecting said multiple neurons with said multiple axons. 16. The method of claim 15, wherein: said permutation unit is implemented via an interconnection network interconnecting said set of neurosynaptic core circuits; each neuronal output generated by said neural computation unit represents a neural firing of a neuron of a neurosynaptic core circuit; each neural firing of each neuron of each neurosynaptic core circuit is an event; and said interconnection network is event-driven. 17. The method of claim 16, wherein: each neurosynaptic core circuit has a corresponding packet router enabling inter-core routing; and said permutation unit utilizes each packet router of each neurosynaptic core circuit for mapping. 18. The method of claim 16, wherein: each neurosynaptic core circuit comprises a scheduler delay buffer for maintaining one or more axonal inputs for a pre-determined time delay; and said delay unit utilizes each scheduler delay buffer of each neurosynaptic core circuit for buffering. 19. The method of claim 13, wherein: said set of computations performed by said neural computation unit comprise one of feed-forward computations, recurrent computations, a hybrid of feed-forward computations and recurrent computations. 20. A computer program product for computing computational functions, the computer program product comprising a computer-readable storage medium having program code embodied therewith, the program code being executable by a computer to: receive and buffer, via a delay unit, one or more axonal inputs; generate one or more neuronal outputs by performing, via a neural computation unit, a set of computations based on at least one axonal input received; receive, via a permutation unit, one or more external inputs; transmit, via said permutation unit, one or more external outputs; map, via said permutation unit, each external input received as one of an axonal input to said delay unit and an external output; and map, via said permutation unit, each neuronal output generated by said neural computation unit as one of an axonal input to said delay unit and an external output; wherein said neural computation unit comprises multiple electronic neurons, multiple electronic axons, and a plurality of electronic synapse devices interconnecting said multiple neurons with said multiple axons.