Embodiments of the invention relate to a globally asynchronous and locally synchronous neuromorphic network. One embodiment comprises generating a synchronization signal that is distributed to a plurality of neural core circuits. In response to the synchronization signal, in at least one core circuit, incoming spike events maintained by said at least one core circuit are processed to generate an outgoing spike event. Spike events are asynchronously communicated between the core circuits via a routing fabric comprising multiple asynchronous routers.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A method comprising: at a scheduler for a core circuit of a plurality of hardware core circuits: receiving one or more address-event packets; decoding each of the one or more address-event packets; storing one or more spikes decoded from the one or more address-event packets into a memory of the scheduler, wherein each spike is scheduled for delivery in a future time step; and in response to receiving a signal indicating occurrence of a time step: reading, from the memory, one or more spikes scheduled for delivery in the time step; and sending the one or more spikes scheduled for delivery in the time step to a router connected to the core circuit for delivery to one or more target axons. 2. The method of claim 1, wherein each core circuit comprises a plurality of electronic neurons, a plurality of electronic axons, and a plurality of electronic synapse devices interconnecting the electronic axons to the electronic neurons. 3. The method of claim 1, wherein a plurality of asynchronous routers interconnect the core circuits to facilitate asynchronous communication of spikes between the core circuits. 4. The method of claim 3, wherein the scheduler bridges a high-bandwidth asynchronous router to a relatively low-frequency synchronous core circuit. 5. The method of claim 1, further comprising: selectively imposing a delay on delivery of one or more spikes for deterministic event delivery. 6. A system comprising a computer processor, a computer-readable hardware storage medium, and program code embodied with the computer-readable hardware storage medium for execution by the computer processor to implement a method comprising: at a scheduler for a core circuit of a plurality of hardware core circuits: receiving one or more address-event packets; decoding each of the one or more address-event packets; storing one or more spikes decoded from the one or more address-event packets into a memory of the scheduler, wherein each spike is scheduled for delivery in a future time step; and in response to receiving a signal indicating occurrence of a time step: reading, from the memory, one or more spikes scheduled for delivery in the time step; and sending the one or more spikes scheduled for delivery in the time step to a router connected to the core circuit for delivery to one or more target axons. 7. The system of claim 6, wherein each core circuit comprises a plurality of electronic neurons, a plurality of electronic axons, and a plurality of electronic synapse devices interconnecting the electronic axons to the electronic neurons. 8. The system of claim 6, wherein a plurality of asynchronous routers interconnect the core circuits to facilitate asynchronous communication of spikes between the core circuits. 9. The system of claim 8, wherein the scheduler bridges a high-bandwidth asynchronous router to a relatively low-frequency synchronous core circuit. 10. The system of claim 6, further comprising: selectively imposing a delay on delivery of one or more spikes for deterministic event delivery. 11. A computer program product comprising a computer-readable hardware storage device having program code embodied therewith, the program code being executable by a computer to implement a method comprising: at a scheduler for a core circuit of a plurality of hardware core circuits: receiving one or more address-event packets; decoding each of the one or more address-event packets; storing one or more spikes decoded from the one or more address-event packets into a memory of the scheduler, wherein each spike is scheduled for delivery in a future time step; and in response to receiving a signal indicating occurrence of a time step: reading, from the memory, one or more spikes scheduled for delivery in the time step; and sending the one or more spikes scheduled for delivery in the time step to a router connected to the core circuit for delivery to one or more target axons. 12. The computer program product of claim 11, wherein each core circuit comprises a plurality of electronic neurons, a plurality of electronic axons, and a plurality of electronic synapse devices interconnecting the electronic axons to the electronic neurons. 13. The computer program product of claim 11, wherein a plurality of asynchronous routers interconnect the core circuits to facilitate asynchronous communication of spikes between the core circuits. 14. The computer program product of claim 13, wherein the scheduler bridges a high-bandwidth asynchronous router to a relatively low-frequency synchronous core circuit. 15. The computer program product of claim 11, further comprising: selectively imposing a delay on delivery of one or more spikes for deterministic event delivery.