A logic decoder circuit capable of performing Boolean or fuzzy logic has one or more logic components configured to perform a logic function of an AND-NOT gate, each AND-NOT gate comprising a circuit that performs a conjunction of an excitatory input X and an inhibitory input Y to obtain an output X-AND-NOT-Y substantially linearly for given ranges for X and Y. Certain preferred designs are provided for an X-AND-NOT-Y logic gate and a family of fast fuzzy decoders composed of such gates.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A logic decoder circuit capable of performing Boolean or fuzzy logic comprising: one or more logic components configured to perform a logic function of an AND-NOT gate, each AND-NOT gate comprising a circuit that performs a conjunction of an excitatory input X and an inhibitory input Y to obtain an output X-AND-NOT-Y substantially linearly for given ranges for X and Y. 2. A logic decoder circuit according to claim 1, wherein said AND-NOT gate is configured to emulate the function of a neuron, so that fuzzy logic decoders composed of said AND-NOT gates can closely emulate the brain's method of processing information. 3. A logic decoder circuit according to claim 1, wherein said AND-NOT gate has an X input applied to a high end of resistor, a Y input applied to a gate of N-channel transistor having its source connected in series with the resistor and its drain to ground, and the output X-AND-NOT-Y provided at the connection between resistor and transistor. 4. A logic decoder circuit according to claim 1, wherein said AND-NOT gate has an X input applied to a source of a P-channel transistor, a Y input applied to a gate of the transistor, the drain of the transistor connected in series through the resistor to ground, and the output X-AND-NOT-Y provided at the connection between resistor and transistor. 5. A logic decoder circuit according to claim 1, wherein said AND-NOT gate has an X input applied to a source of a first P-channel transistor connected to a second N-channel transistor to ground, a Y input applied in parallel to the gates of both transistors, and the output X-AND-NOT-Y provided at the connection between the first and second transistors. 6. A logic decoder circuit according to claim 1, wherein said AND-NOT gate has an X input applied to a gate of a first P-channel transistor in a first stage connected in series with a first resistor to ground and biased by bias voltage Vdd, the first stage output connected to a gate of a second P-channel transistor in a second stage connected in series with a third P-channel transistor and biased by bias voltage Vdd, a Y input applied to a gate of the third transistor, the drain of the third transistor connected in series through a second resistor to ground, and the output X-AND-NOT-Y provided at the connection between the second resistor and third transistor. 7. A logic decoder circuit according to claim 1, wherein said AND-NOT gate is used in a master-slave flip flop circuit. 8. A logic decoder circuit according to claim 1, wherein said AND-NOT gate is composed of two operational amplifier circuits. 9. A logic decoder circuit according to claim 8, wherein one operational amplifier is configured as a subtractor. 10. A logic decoder circuit according to claim 9, wherein the subtractor comprises three P-channel MOSFET transistors, one N-channel MOSFET transistor, and four resistors. 11. A logic decoder circuit according to claim 9, wherein, for the subtractor, thresholds of the first, second, and third P-channel transistors are set by bias voltages Vdd, threshold of the N-channel transistor is set by bias voltages Vss, the input X is coupled to a gate of the first P-channel transistor, the input Y is coupled to gates of the second and third P-channel transistors, a source of the first P-channel transistor is coupled to a positive supply voltage of Vdd volts across a first resistor and to a source of the second P-channel transistor across a second resistor, a source of the third P-channel transistor is coupled to the Vdd voltage across a third resistor and to a gate of the N-channel transistor, a source of the N-channel transistor is coupled to a negative supply voltage of Vss volts across a fourth resistor, drains of the first and third P-channel transistor are coupled to ground, and drains of the second P-channel transistor and the N-channel transistor are coupled to the output. 12. A logic decoder circuit according to claim 8, wherein a second operational amplifier is configured as a half-wave rectifier or as a comparator. 13. A logic decoder circuit according to claim 1, wherein said AND-NOT gate is s composed of an operational amplifier and a chopper. 14. A logic decoder circuit according to claim 1, wherein said AND-NOT gate is composed of a single operational amplifier. 15. A logic decoder circuit according to claim 1, comprising FET transistors forming a linear AND-NOT gate. 16. A logic decoder circuit according to claim 1, wherein said AND-NOT gate is used in a fast fuzzy decoder. 17. A logic decoder circuit according to claim 1, comprising CMOS transistors forming the AND-NOT gate. 18. A logic decoder circuit according to claim 1, wherein said AND-NOT gate is used to replace a NAND or a NOR gate in conventional digital logic circuit architecture. 19. A logic decoder circuit according to claim 1, wherein said AND-NOT gate is used to change a digital logic circuit to a fuzzy logic circuit. 20. A logic decoder circuit according to claim 1, wherein said AND-NOT gate is used in a digital subtractor circuit.