The present invention provides a system comprising multiple core circuits. Each core circuit comprises multiple electronic axons for receiving event packets, multiple electronic neurons for generating event packets, and a fanout crossbar including multiple electronic synapse devices for interconnecting the neurons with the axons. The system further comprises a routing system for routing event packets between the core circuits. The routing system virtually connects each neuron with one or more programmable target axons for the neuron by routing each event packet generated by the neuron to the target axons. Each target axon for each neuron of each core circuit is an axon located on the same core circuit as, or a different core circuit than, the neuron.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A system, comprising: multiple neurosynaptic core circuits, wherein each core circuit comprises: multiple electronic neurons for generating event packets; multiple electronic axons for receiving event packets; and a programmable fanout crossbar comprising multiple electronic synapse devices for physically connecting said multiple neurons with said multiple axons; and a routing system for routing event packets between said core circuits, wherein said routing system virtually connects each neuron of each core circuit with one or more programmable target axons for said neuron by routing each event packet generated by said neuron to said one or more target axons. 2. The system of claim 1, wherein: each target axon for each neuron of each core circuit is one of the following: an axon of the same core circuit as said core circuit, and an axon of a different core circuit than said core circuit; and said routing system comprises one or more packet routers for routing event packets between said multiple core circuits. 3. The system of claim 2, wherein: said routing system further comprises one or more look-up tables, wherein each look-up table corresponds to at least one core circuit. 4. The system of claim 3, wherein: for each neuron of each core circuit, a look-up table corresponding to said core circuit maintains at least one target axon address for said neuron, wherein each target axon address corresponds to a target axon for said neuron. 5. The system of claim 4, wherein: for each neuron of each core circuit, each target axon for said neuron is programmable by programming a target axon address corresponding to said target axon in a look-up table corresponding to said core circuit. 6. The system of claim 4, wherein: each target axon address maintained in each look-up table is based on one of the following: relative addressing, and absolute addressing. 7. The system of claim 4, wherein: each target axon address for each neuron identifies a core circuit of said multiple core circuits and an axon of said identified core circuit, wherein each event packet generated by said neuron is routed to said identified axon of said identified core circuit. 8. The system of claim 1, wherein: for each axon of each core circuit, each synapse device connected to said axon is activated by said axon when said axon receives an event packet. 9. The system of claim 4, wherein: each synapse device activates a neuron connected to said synapse device when said synapse device is activated by an axon connected to said synapse device. 10. The system of claim 1, wherein: each neuron generates at least one event packet when said neuron spikes. 11. The system of claim 4, wherein: each neuron generates an event packet for each target axon address for said neuron. 12. The system of claim 1, wherein: each core circuit of said multiple core circuits has the same number of neurons. 13. The system of claim 4, wherein: a total amount of bits of memory required by the system is based on a total number of synapse devices in the system and a size of each look-up table. 14. A method for hardware implementation of a neural network comprising a plurality of neuron groups for generating event packets and a plurality of electronic axons for receiving event packets, wherein each neuron group has multiple electronic neurons, and wherein each neuron has a plurality of connections for inter-neuron communication, the method comprising: for each neuron group, physically connecting said neuron group with one or more axons of said plurality of axons via a fanout crossbar comprising one or more electronic synapse devices; and for each neuron of each neuron group, virtually connecting said neuron with one or more programmable target axons for said neuron by routing each event packet generated by said neuron to said one or more target axons. 15. The method of claim 14, further comprising: routing event packets between said plurality of neuron groups using one or more packet routers; wherein each target axon for each neuron of each core circuit is one of the following: an axon of the same core circuit as said core circuit, and an axon of a different core circuit than said core circuit. 16. The method of claim 14, further comprising: maintaining one or more look-up tables, wherein each look-up table corresponds to at least one neuron group. 17. The method of claim 16, wherein: for each neuron of each neuron group, a look-up table corresponding to said neuron group maintains at least one target axon address for said neuron, wherein each target axon address corresponds to a target axon for said neuron. 18. The method of claim 14, further comprising: for each neuron, generating at least one event packet when said neuron spikes. 19. The method of claim 17, further comprising: for each neuron, generating an event packet for each target axon address for said neuron. 20. A computer program product for hardware implementation of a neural network comprising a plurality of neuron groups for generating event packets and a plurality of electronic axons for receiving event packets, wherein each neuron group has multiple electronic neurons, and wherein each neuron has a plurality of connections for inter-neuron communication, the computer program product comprising a computer-readable storage medium having program code embodied therewith, the program code being executable by a computer to: for each neuron group, physically connect said neuron group with one or more axons of said plurality of axons via a fanout crossbar comprising one or more electronic synapse devices; and for each neuron of each neuron group, virtually connect said neuron with one or more programmable target axons for said neuron by routing each event packet generated by said neuron to said one or more target axons.