First/second memories hold rows of N weight/data words. Each of N processing units (PU) of index J have a register, an accumulator having an output, an arithmetic unit that performs an operation thereon to accumulate a result, the first input receives the output of the accumulator, the second input receives a respective first memory weight word, the third input receives a respective data word output by the register, and multiplexing logic receives a respective second memory data word and a data word output by the register of PU J−1 and outputs a selected data word to the register. PU J−1 for PU 0 is PU N−1. The multiplexing logic of PU N/4 also receives the data word output by the register of PU (3N/4)−1. The multiplexing logic of PU 3N/4 also receives the data word output by the register of PU (N/4)−1.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. An apparatus, comprising: a first memory that holds rows of N weight words, wherein N is at least 512; a second memory that holds rows of N data words; an array of N processing units (PU) indexed as 0 through N−1, each PU of index J having: a register; an accumulator having an output; an arithmetic unit having first, second and third inputs and that performs an operation thereon to generate a result to store in the accumulator, the first input receives the output of the accumulator, the second input receives a respective weight word output by the first memory, the third input receives a respective data word output by the register; and multiplexing logic that receives a respective data word output by the second memory and that receives a data word output by the register of PU J−1 and that outputs a selected data word to the register, wherein PU J−1 for PU 0 is PU N−1; wherein the multiplexing logic of PU N/4 also receives the data word output by the register of PU (3N/4)−1; and wherein the multiplexing logic of PU 3N/4 also receives the data word output by the register of PU (N/4)−1. 2. The apparatus of claim 1, wherein in a first mode, the multiplexing logic of PU N/4 selects the data word output by the register of PU (3N/4)−1, the multiplexing logic of PU 3N/4 selects the data word output by the register of PU (N/4)−1, and the multiplexing logic of the remaining PUs selects the data word output by the register of PU J−1. 3. The apparatus of claim 2, wherein in the first mode, the multiplexing logic alternatively selects the respective data word output by the second memory for provision to the register. 4. The apparatus of claim 2, wherein in a second mode, the multiplexing logic of the N PUs selects the data word output by the register of PU J−1. 5. The apparatus of claim 4, wherein in the second mode, the multiplexing logic alternatively selects the respective data word output by the second memory for provision to the register. 6. The apparatus of claim 4, wherein in the first mode, the multiplexing logic and register of PUs 0 through (N/4)−1 and 3N/4 through N−1 collectively operate as a first N/2-word rotater, and the multiplexing logic and register of PUs N/4 through (3N/4)−1 collectively operate as a second N/2 word rotater; and wherein in the second mode, the multiplexing logic and register of PUs 0 through N−1 collectively operate as an N-word rotater. 7. The apparatus of claim 2, further comprising: wherein the multiplexing logic of PU N/8 also receives the data word output by the register of PU (7N/8)−1; wherein the multiplexing logic of PU 3N/8 also receives the data word output by the register of PU (5N/8)−1; wherein the multiplexing logic of PU 5N/8 also receives the data word output by the register of PU (3N/8)−1; wherein the multiplexing logic of PU 7N/8 also receives the data word output by the register of PU (N/8)−1; and wherein in a second mode: the multiplexing logic of PU 7N/8 selects the data word output by the register of PU (N/8)−1; the multiplexing logic of PU N/8 selects the data word output by the register of PU (7N/8)=1; the multiplexing logic of PU 3N/4 selects the data word output by the register of PU (N/4)−1; the multiplexing logic of PU N/4 selects the data word output by the register of PU (3N/4)−1; the multiplexing logic of PU 5N/8 selects the data word output by the register of PU (3N/8)−1; the multiplexing logic of PU 3N/8 selects the data word output by the register of PU (5N/8)−1; and the multiplexing logic of the remaining PUs selects the data word output by the register of PU J−1. 8. The apparatus of claim 7, wherein in the first mode, the multiplexing logic and register of PUs 0 through (N/4)−1 and 3N/4 through (N/4)−1 collectively operate as a first N/2-word rotater, and the multiplexing logic and register of PUs N/4 through (3N/4)−1 collectively operate as a second N/2 word rotater; and wherein in the second mode: the multiplexing logic and register of PUs 0 through (N/8)−1 and 7N/8 through N−1 collectively operate as a first N/4-word rotater; the multiplexing logic and register of PUs N/8 through (N/4)−1 and 3N/4 through (7N/8)−1 collectively operate as a second N/4-word rotater; the multiplexing logic and register of PUs N/4 through (3N/8)−1 and 5N/8 through (3N/4)−1 collectively operate as a third N/4-word rotater; and the multiplexing logic and register of PUs 3N/8 through (5N/8)−1 collectively operate as a fourth N/4 word rotater. 9. The apparatus of claim 1, wherein the N PUs are physically arranged in a loop such that: PU 0 is located substantially physically adjacent to PU N−1; PU N/4 is located substantially physically adjacent to PU (3N/4)−1; PU N/2 is located substantially physically adjacent to PU (N/2)−1; and PU 3N/4 is located substantially physically adjacent to PU (N/4)−1. 10. The apparatus of claim 1, wherein the N PUs are physically arranged in a loop such that: a length Q of a wiring path that connects an output of the register of PU J−1 and an input of the multiplexing logic of PU J that receives the output of the register of PU J−1 is approximately the same for J equal to 1 through (N/2)−1 and (N/2)+1 through N−1; a length R is approximately the same for: a wiring path that connects the output of the register of PU N−1 and a second input of the multiplexing logic of PU 0 that receives the output of the register of PU N−1; a wiring path that connects the output of the register of PU (3N/4)−1 and a second input of the multiplexing logic of PU N/4 that receives the output of the register of PU (3N/4)−1; a wiring path that connects the output of the register of PU (N/2)−1 and a second input of the multiplexing logic of PU N/2 that receives the output of the register of PU (N/2)−1; and a wiring path that connects the output of the register of PU (N/4)−1 and a second input of the multiplexing logic of PU 3N/4 that receives the output of the register of PU (N/4)−1. 11. The apparatus of claim 10, wherein R and Q are within a factor of five. 12. A method for operating an apparatus having a first memory that holds rows of N weight words, wherein N is at least 512, a second memory that holds rows of N data words, and an array of N processing units (PU) indexed as 0 through N−1, each PU of index J having a register, an accumulator having an output, an arithmetic unit having first, second and third inputs and that performs an operation thereon to generate a result to store in the accumulator, the first input receives the output of the accumulator, the second input receives a respective weight word output by the first memory, the third input receives a respective data word output by the register, and multiplexing logic that receives a respective data word output by the second memory and that receives a data word output by the register of PU J−1 and that outputs a selected data word to the register, wherein PU J−1 for PU 0 is PU N−1, wherein the multiplexing logic of PU N/4 also receives the data word output by the register of PU (3N/4)−1, and wherein the multiplexing logic of PU 3N/4 also receives the data word output by the register of PU (N/4)−1, the method comprising: in a first mode: selecting, by the multiplexing logic of PU N/4, the data word output by the register of PU (3N/4)−1; selecting, by the multiplexing logic of PU 3N/4, the data word output by the register of PU (N/4)−1; and selecting, by the multiplexing logic of the remaining PUs, the data word output by the register of PU J−1. 13. The method of claim 12, in the first mode: alternatively selecting, by the multiplexing logic alternatively, the respective data word output by the second memory for provision to the register. 14. The method of claim 12, in a second mode: selecting, by the multiplexing logic of the N PUs, the data word output by the register of PU J−1. 15. The method of claim 14, in the second mode: alternatively selecting, by the multiplexing logic, the respective data word output by the second memory for provision to the register. 16. The method of claim 14, in the first mode: collectively operating, by the multiplexing logic and register of PUs 0 through (N/4)−1 and 3N/4 through N−1, as a first N/2-word rotater; and collectively operating, by the multiplexing logic and register of PUs N/4 through (3N/4)−1, as a second N/2 word rotater; and in the second mode: collectively operating, by the multiplexing logic and register of PUs 0 through N−1, as an N-word rotater. 17. The method of claim 12, wherein the multiplexing logic of PU N/8 also receives the data word output by the register of PU (7N/8)−1, wherein the multiplexing logic of PU 3N/8 also receives the data word output by the register of PU (5N/8)−1, wherein the multiplexing logic of PU 5N/8 also receives the data word output by the register of PU (3N/8)−1, wherein the multiplexing logic of PU 7N/8 also receives the data word output by the register of PU (N/8)−1, the method further comprising: in a second mode: selecting, by the multiplexing logic of PU 7N/8, the data word output by the register of PU (N/8)−1; selecting, by the multiplexing logic of PU N/8, the data word output by the register of PU (7N/8)−1; selecting, by the multiplexing logic of PU 3N/4, the data word output by the register of PU (N/4)−1; selecting, by the multiplexing logic of PU N/4, the data word output by the register of PU (3N/4)−1; selecting, by the multiplexing logic of PU 5N/8, the data word output by the register of PU (3N/8)−1; selecting, by the multiplexing logic of PU 3N/8, the data word output by the register of PU (5N/8)−1; and selecting, by the multiplexing logic of the remaining PUs, the data word output by the register of PU J−1. 18. The method of claim 17, in the first mode: collectively operating, by the multiplexing logic and register of PUs 0 through (N/4)−1 and 3N/4 through (N/4)−1, as a first N/2-word rotater; and collectively operating, by the multiplexing logic and register of PUs N/4 through (3N/4)−1, as a second N/2 word rotater; and in the second mode: collectively operating, by the multiplexing logic and register of PUs 0 through (N/8)−1 and 7N/8 through N−1, as a first N/4-word rotater; collectively operating, by the multiplexing logic and register of PUs N/8 through (N/4)−1 and 3N/4 through (7N/8)−1, as a second N/4-word rotater; collectively operating, by the multiplexing logic and register of PUs N/4 through (3N/8)−1 and 5N/8 through (3N/4)−1, as a third N/4-word rotater; and collectively operating, by the multiplexing logic and register of PUs 3N/8 through (5N/8)−1, as a fourth N/4 word rotater. 19. An apparatus, comprising: a first memory that holds rows of N weight words, wherein N is at least 512; a second memory that holds rows of N data words; an array of N processing units (PU) indexed as 0 through N−1, each PU of index J having: a register; an accumulator having an output; an arithmetic unit having first, second and third inputs and that performs an operation thereon to generate a result to store in the accumulator, the first input receives the output of the accumulator, the second input receives a respective weight word output by the first memory, the third input receives a respective data word output by the register; and multiplexing logic that receives a respective data word output by the second memory and that receives a data word output by the register of PU J−1 and that outputs a selected data word to the register, wherein PU J−1 for PU 0 is PU N−1; wherein the multiplexing logic of PU K also receives the data word output by the register of PU K+N/2−1, wherein K is between 0 and N/2−1; wherein the multiplexing logic of PU L also receives the data word output by the register of PU L−N/2−1, wherein L is between N/2 and N−1; and wherein L=K+N/2. 20. The apparatus of claim 19, wherein in a first mode, the multiplexing logic of PU K selects the data word output by the register of PU K+N/2−1, the multiplexing logic of PU L selects the data word output by the register of PU L−N/2−1, and the multiplexing logic of the remaining PUs selects the data word output by the register of PU J−1. 21. The apparatus of claim 20, wherein in a second mode, the multiplexing logic of the N PUs selects the data word output by the register of PU J−1.