A reconfigurable neural network circuit is provided. The reconfigurable neural network circuit comprises an electronic synapse array including multiple synapses interconnecting a plurality of digital electronic neurons. Each neuron comprises an integrator that integrates input spikes and generates a signal when the integrated inputs exceed a threshold. The circuit further comprises a control module for reconfiguring the synapse array. The control module comprises a global final state machine that controls timing for operation of the circuit, and a priority encoder that allows spiking neurons to sequentially access the synapse array.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A neural network circuit, comprising: plurality of digital electronic neurons; and an electronic synapse array comprising a plurality of digital synapses interconnecting the neurons; wherein each synapse has a corresponding multi-bit fine-grain value representing a synaptic weight of the synapse; wherein each neuron includes a learning module for updating a synaptic weight of a connected synapse based on one or more learning rules; wherein each learning module is independently reconfigurable; and wherein each learning module of each neuron includes one or more digital counters, each digital counter decays at a corresponding decay rate during each timestep, and each digital counter resets to a pre-determined value in response to the neuron generating a spike signal. 2. The network circuit of claim 1, wherein: each synapse maintains m bits representing a corresponding multi-bit fine-grain value of the synapse; each multi-bit fine-grained value is a value from 0 to 2m−1, thereby enabling the synapses to provide noise tolerance; and each synapse has m pairs of bit lines, such that a corresponding multi-bit fine-grain value is written at once using only one word line when a synaptic weight of the synapse is updated. 3. (canceled) 4. The network circuit of claim 1, wherein, for each digital counter, a decay rate corresponding to the digital counter specifies a learning rule. 5. The network circuit of claim 4, wherein, for each neuron, a synaptic weight of a connected synapse is updated based on a learning rule specified in a decay rate of a digital counter of a learning module of the neuron. 6. The network circuit of claim 4, wherein, for each neuron, a synaptic weight of a connected synapse is updated based on a learning rule specified in a decay rate of a digital counter of a learning module of the neuron and a constant value. 7. The network circuit of claim 6, wherein the constant value is added to the synaptic weight of the connected synapse. 8. The network circuit of claim 6, wherein the constant value is subtracted from the synaptic weight of the connected synapse. 9. The network circuit of claim 4, wherein, for each neuron, a learning module of the neuron generates a digital signal for updating a synaptic weight of a connected synapse. 10. The network circuit of claim 1, wherein the learning rules include at least one of the following: spike-timing dependent plasticity (STDP), anti-STDP, Hebbian and anti-Hebbian. 11. A method comprising: interconnecting a plurality of digital electronic neurons via an electronic synapse array comprising a plurality of digital synapses; and for at least one neuron, updating a synaptic weight of a connected synapse based on one or more learning rules using a learning module of the neuron; wherein each synapse has a corresponding multi-bit fine-grain value representing a synaptic weight of the synapse; wherein each learning module is independently reconfigurable; and wherein each learning module of each neuron includes one or more digital counters, each digital counter decays at a corresponding decay rate during each timestep, and each digital counter resets to a pre-determined value in response to the neuron generating a spike signal. 12. The method of claim 11, wherein: each synapse maintains m bits representing a corresponding multi-bit fine-grain value of the synapse; each multi-bit fine-grained value is a value from 0 to 2m−1, thereby enabling the synapses to provide noise tolerance; and each synapse has m pairs of bit lines, such that a corresponding multi-bit fine-grain value is written at once using only one word line when a synaptic weight of the synapse is updated. 13. (canceled) 14. The method of claim 11, wherein, for each digital counter, a decay rate corresponding to the digital counter specifies a learning rule. 15. The method of claim 14, further comprising: for each neuron, updating a synaptic weight of a connected synapse based on a learning rule specified in a decay rate of a digital counter of a learning module of the neuron. 16. The method of claim 14, further comprising: for each neuron, updating a synaptic weight of a connected synapse based on a learning rule specified in a decay rate of a digital counter of a learning module of the neuron and a constant value. 17. The method of claim 16, further comprising: adding the constant value to the synaptic weight of the connected synapse. 18. The method of claim 16, further comprising: subtracting the constant value from the synaptic weight of the connected synapse. 19. The method of claim 14, further comprising: for each neuron, a learning module of the neuron generating a digital signal for updating a synaptic weight of a connected synapse. 20. The method of claim 11, wherein the learning rules include at least one of the following: spike-timing dependent plasticity (STDP), anti-STDP, Hebbian and anti-Hebbian.