Quantum circuits and circuit designs are based on factorizations of diagonal unitaries using a phase context. The cost/complexity of phase sparse/phase dense approximations is compared, and a suitable implementation is selected. For phase sparse implementations in the Clifford+T basis, required entangling circuits are defined based on a number of occurrences of a phase in the phase context in a factor of the diagonal unitary.
Please help me write a proper abstract based on the patent claims. CLAIM: 1.-15. (canceled) 16. A method of defining a quantum circuit for implementing a diagonal unitary in a quantum computer, comprising: receiving a definition of the diagonal unitary with respect to a set of n qubits, wherein n is a positive integer; receiving an approximation precision; based on a phase context, processing the diagonal unitary so as to select a plurality of single-qubit rotation operators having rotation angles in the phase context; defining the quantum circuit based on the plurality of rotation operators applied to an ancillary qubit; and implementing the quantum circuit based on the definition. 17. The method of claim 16, wherein the phase context is sparse. 18. The method of claim 16, further comprising assessing an implementation complexity associated with the quantum circuit as defined based on the phase context. 19. The method of claim 18, wherein the quantum circuit defined based on the phase context includes a plurality of cascaded entanglement gate sequence pairs, and the complexity of the quantum circuit is estimated based on the plurality of cascaded entanglement gate sequence pairs. 20. The method of claim 19, further comprising assessing an implementation complexity associated with an exact representation of the diagonal unitary; and if the complexity of the phase dense representation is less than that of the phase sparse complexity assessment, defining the quantum circuit based on the exact representation. 21. The method of claim 16, wherein the quantum circuit is defined in a Clifford+T basis. 22. The method of claim 21, further comprising factoring the diagonal unitary into a product of the form ∏ m = 1 k - 1   V  ( φ m ,  m ) , wherein V(φm,lm)=diag(1, . . . , 1,φm, . . . , φm), m is a positive integer, φm is a phase in the phase context, and lm is a number of occurrences of the phase φm in V(φm,lm). 23. The method of claim 22, further comprising defining cascaded entanglement gate sequence pairs associated with one or more of the V(φm,lm) based on the number of qubits n and l. 24. The method of claim 23, wherein the cascaded entanglement gate sequence pairs are determined based on evaluation of └log2(lm)┘ for at least one value of m. 25. A system for designing a quantum computer, comprising: a communication connection that receives a definition of a diagonal unitary over n qubits; and a processor that: factors the diagonal unitary so that the diagonal unitary is representable as a product of the factors of the form V(φm,lm)=diag(1, . . . , 1, φm, . . . φm), wherein m is a positive integer, φm is a phase in a phase context, and lm is a number of occurrences of the phase φm in V(φm,lm); and produces a quantum circuit design corresponding to the diagonal unitary based on the factors V(φm,lm). 26. The system of claim 25, wherein the processor further establishes a single single-qubit rotation gate and at least one cascaded entanglement circuit with each of the factors V(φm,lm), and the quantum circuit design is based on gate sequences associated with the single-qubit rotation gates and the cascaded entanglement circuits. 27. The system of claim 26, wherein processor defines gates for a cascaded entanglement circuit associated with at least one of the factors V(φm,lm) based on lm and a number of qubits n. 28. The system of claim 25, wherein processor defines gates for the at least one cascaded entanglement circuit associated with each of the factors V(φm,lm) based on lm and a number of qubits n. 29. The system of claim 28, wherein the at least one cascaded entanglement circuit is determined based on evaluation of └log2(lm)┘. 30. The system of claim 25, wherein the processor further establishes the phase context as a set of random phases. 31. The system of claim 25, wherein the phase context is sparse. 32. The system of claim 31, wherein a ratio of a number of distinct phases in the diagonal unitary to 2n is less than or equal to ½. 33. The system of claim 25, wherein the processor produces the quantum circuit design based on quantum gates of the Clifford+T basis. 34. A computer-assisted quantum circuit design method, comprising: determining if a diagonal unitary is phase sparse or phase dense; if the diagonal unitary is phase sparse, producing a quantum circuit design based on a factorization of the diagonal unitary over a phase context; and implementing the quantum circuit based on the quantum circuit design. 35. The computer-assisted quantum circuit design method of claim 34, wherein the quantum circuit design includes rotation circuits and entanglement circuits, and further comprising defining at least one entangling circuit based on a number of occurrences of a corresponding phase in the diagonal unitary.