Certain aspects of the present disclosure support operating simultaneously multiple super neuron processing units in an artificial nervous system, wherein a plurality of artificial neurons is assigned to each super neuron processing unit. The super neuron processing units can be interfaced with a memory for storing and loading synaptic weights and plasticity parameters of the artificial nervous system, wherein organization of the memory allows contiguous memory access.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A method for operating an artificial nervous system with a plurality of artificial neurons, comprising: operating simultaneously multiple super neuron processing units in the artificial nervous system for updating states of the artificial neurons, wherein a subset of the artificial neurons is assigned to each super neuron processing unit; and interfacing the super neuron processing units with a memory for accessing synaptic weights and plasticity parameters of the artificial nervous system, wherein organization of the memory allows contiguous memory access. 2. The method of claim 1, wherein operating simultaneously multiple super neuron processing units comprises time-multiplexing the super neuron processing units for input current accumulators and models of the artificial neurons. 3. The method of claim 1, further comprising: updating a state of any artificial neuron assigned to one of the super neuron processing units every defined step. 4. The method of claim 1, further comprising: storing, in the memory, a pointer to a post-synaptic fan-out associated with any of the artificial neurons. 5. The method of claim 1, wherein operating simultaneously multiple super neuron processing units comprises implementing, by each of the super neuron processing units, neural input accumulators. 6. The method of claim 1, wherein a number of computational units in each super neuron processing unit is less than a number of the artificial neurons assigned to that super neuron processing unit. 7. The method of claim 1, wherein: the memory comprises a dynamic random access memory (DRAM), and the contiguous memory access of the DRAM comprises simultaneous access to data related to multiple synapses. 8. The method of claim 1, wherein the organization of memory comprises pre-synaptic and post-synaptic neuron lookup tables for implementing plasticity. 9. The method of claim 1, further comprising: dropping of spikes of the artificial nervous system in a dynamic probabilistic manner. 10. The method of claim 1, further comprising: storing, in the memory, data associated with synapses of the artificial nervous system, wherein the data comprises destination routing information. 11. The method of claim 1, further comprising: integrating, in the artificial nervous system by utilizing the super neuron processing units and organization of the memory, external and internal synapse activations. 12. An apparatus for operating an artificial nervous system with a plurality of artificial neurons, comprising: a first circuit configured to operate simultaneously multiple super neuron processing units in the artificial nervous system for updating states of the artificial neurons, wherein a subset of the artificial neurons is assigned to each super neuron processing unit; and a second circuit configured to interface the super neuron processing units with a memory for accessing synaptic weights and plasticity parameters of the artificial nervous system, wherein organization of the memory allows contiguous memory access. 13. The apparatus of claim 12, wherein the first circuit is also configured to: time-multiplex the super neuron processing units for input current accumulators and models of the artificial neurons. 14. The apparatus of claim 12, further comprising: a third circuit configured to update a state of any artificial neuron assigned to one of the super neuron processing units every defined step. 15. The apparatus of claim 12, further comprising: a third circuit configured to store, in the memory, a pointer to a post-synaptic fan-out associated with any of the artificial neurons. 16. The apparatus of claim 12, further comprising: a third circuit configured to implement, by each of the super neuron processing units, neural input accumulators. 17. The apparatus of claim 12, wherein a number of computational units in each super neuron processing unit is less than a number of the artificial neurons assigned to that super neuron processing unit. 18. The apparatus of claim 12, wherein: the memory comprises a dynamic random access memory (DRAM), and the contiguous memory access of the DRAM comprises simultaneous access to data related to multiple synapses. 19. The apparatus of claim 12, wherein the organization of memory comprises pre-synaptic and post-synaptic neuron lookup tables for implementing plasticity. 20. The apparatus of claim 12, further comprising: a third circuit configured to drop spikes of the artificial nervous system in a dynamic probabilistic manner. 21. The apparatus of claim 12, further comprising: a third circuit configured to store, in the memory, data associated with synapses of the artificial nervous system, wherein the data comprises destination routing information. 22. The apparatus of claim 12, further comprising: a third circuit configured to integrate, in the artificial nervous system by utilizing the super neuron processing units and organization of the memory, external and internal synapse activations. 23. An apparatus for operating an artificial nervous system with a plurality of artificial neurons, comprising: means for operating simultaneously multiple super neuron processing units in the artificial nervous system for updating states of the artificial neurons, wherein a subset of the artificial neurons is assigned to each super neuron processing unit; and means for interfacing the super neuron processing units with a memory for accessing synaptic weights and plasticity parameters of the artificial nervous system, wherein organization of the memory allows contiguous memory access. 24. The apparatus of claim 23, wherein the means for operating simultaneously multiple super neuron processing units further comprises means for time-multiplexing the super neuron processing units for input current accumulators and models of the artificial neurons. 25. The apparatus of claim 23, further comprising: means for updating a state of any artificial neuron assigned to one of the super neuron processing units every defined step. 26. The apparatus of claim 23, further comprising: means for storing, in the memory, a pointer to a post-synaptic fan-out associated with any of the artificial neurons. 27. The apparatus of claim 23, wherein the means for operating simultaneously multiple super neuron processing units further comprises means for implementing, by each of the super neuron processing units, neural input accumulators. 28. The apparatus of claim 23, wherein a number of computational units in each super neuron processing unit is less than a number of the artificial neurons assigned to that super neuron processing unit. 29. The apparatus of claim 23, wherein: the memory comprises a dynamic random access memory (DRAM), and the contiguous memory access of the DRAM comprises simultaneous access to data related to multiple synapses. 30. The apparatus of claim 23, wherein the organization of memory comprises pre-synaptic and post-synaptic neuron lookup tables for implementing plasticity. 31. The apparatus of claim 23, further comprising: means for dropping of spikes of the artificial nervous system in a dynamic probabilistic manner. 32. The apparatus of claim 23, further comprising: means for storing, in the memory, data associated with synapses of the artificial nervous system, wherein the data comprises destination routing information. 33. The apparatus of claim 23, further comprising: means for integrating, in the artificial nervous system by utilizing the super neuron processing units and organization of the memory, external and internal synapse activations. 34. A computer program product for operating an artificial nervous system with a plurality of artificial neurons, comprising a non-transitory computer-readable medium having instructions executable to: operate simultaneously multiple super neuron processing units in the artificial nervous system for updating states of the artificial neurons, wherein a subset of the artificial neurons is assigned to each super neuron processing unit; and interface the super neuron processing units with a memory for accessing synaptic weights and plasticity parameters of the artificial nervous system, wherein organization of the memory allows contiguous memory access. 35. The computer program product of claim 34, wherein the computer-readable medium further comprising code for: time-multiplexing the super neuron processing units for input current accumulators and models of the artificial neurons. 36. The computer program product of claim 34, wherein the computer-readable medium further comprising code for: updating a state of any artificial neuron assigned to one of the super neuron processing units every defined step. 37. The computer program product of claim 34, wherein the computer-readable medium further comprising code for: storing, in the memory, a pointer to a post-synaptic fan-out associated with any of the artificial neurons. 38. The computer program product of claim 34, wherein the computer-readable medium further comprising code for: implementing, by each of the super neuron processing units, neural input accumulators. 39. The computer program product of claim 34, wherein a number of computational units in each super neuron processing unit is less than a number of the artificial neurons assigned to that super neuron processing unit. 40. The computer program product of claim 34, wherein: the memory comprises a dynamic random access memory (DRAM), and the contiguous memory access of the DRAM comprises simultaneous access to data related to multiple synapses. 41. The computer program product of claim 34, wherein the organization of memory comprises pre-synaptic and post-synaptic neuron lookup tables for implementing plasticity. 42. The computer program product of claim 34, wherein the computer-readable medium further comprising code for: dropping of spikes of the artificial nervous system in a dynamic probabilistic manner. 43. The computer program product of claim 34, wherein the computer-readable medium further comprising code for: storing, in the memory, data associated with synapses of the artificial nervous system, wherein the data comprises destination routing information. 44. The computer program product of claim 34, wherein the computer-readable medium further comprising code for: integrating, in the artificial nervous system by utilizing the super neuron processing units and organization of the memory, external and internal synapse activations.