In one embodiment, a method comprises receiving a selection of a neural network topology type; identifying a synapse memory mapping scheme for the selected neural network topology type from a plurality of synapse memory mapping schemes that are each associated with a respective neural network topology type; and mapping a plurality of synapse weights to locations in a memory based on the identified synapse memory mapping scheme.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A processor comprising: a memory to store a plurality of synapse weights of a neural network; at least one neuron core comprising logic associated with a plurality of neurons; a synapse memory mapping engine to: receive a selection of a neural network topology type; identify a synapse memory mapping scheme for the selected neural network topology type from a plurality of synapse memory mapping schemes that are each associated with a respective neural network topology type; and map the plurality of synapse weights to locations in the memory based on the identified synapse memory mapping scheme. 2. The processor of claim 1, wherein a first synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with a first neural network topology type comprising a feed-forward neural network and a second synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with second network topology type comprising a convolutional neural network. 3. The processor of claim 2, wherein a third synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with a third neural network topology type comprising a recurrent neural network. 4. The processor of claim 1, wherein the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-out synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-out synapse weights by the first neuron. 5. The processor of claim 1, wherein the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-in synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-in synapse weights by the first neuron. 6. The processor of claim 1, wherein the processor is to access synapse weights connected to a neuron of the neuromorphic processor based on a memory address including at least one wildcard bit, wherein the memory address identifies locations in the memory of the synapse weights connected to the neuron. 7. The processor of claim 1, wherein the identified synapse memory mapping scheme specifies a pseudorandom sparse connectivity scheme for a first group of rows of the memory. 8. The processor of claim 1, wherein the identified synapse memory mapping scheme specifies a location for a synapse weight of the plurality of synapse weights based on an XOR operation between a row of the memory and a bank of the memory. 9. The processor of claim 1, wherein the identified synapse memory mapping scheme specifies a location for a synapse weight of the plurality of synapse weights based on an arithmetic operation including a position of the synapse weight within an ordered list of synapse weights and a position of a neuron connected to the synapse weight within an ordered list of neurons. 10. The processor of claim 1, wherein the memory comprises a plurality of memory elements distributed among a plurality of synaptic cores of a network on chip. 11. A method comprising: receiving a selection of a neural network topology type; identifying a synapse memory mapping scheme for the selected neural network topology type from a plurality of synapse memory mapping schemes that are each associated with a respective neural network topology type; and mapping a plurality of synapse weights to locations in a memory based on the identified synapse memory mapping scheme. 12. The method of claim 11, wherein a first synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with a first neural network topology type comprising a feed-forward neural network and a second synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with second network topology type comprising a convolutional neural network. 13. The method of claim 12, wherein a third synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with a third neural network topology type comprising a recurrent neural network. 14. The method of claim 11, wherein the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-out synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-out synapse weights by the first neuron. 15. The method of claim 11, wherein the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-in synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-in synapse weights by the first neuron. 16. A non-transitory machine readable storage medium having instructions stored thereon, the instructions when executed by a machine to cause the machine to: receive a selection of a neural network topology type; identify a synapse memory mapping scheme for the selected neural network topology type from a plurality of synapse memory mapping schemes that are each associated with a respective neural network topology type; and map a plurality of synapse weights to locations in a memory based on the identified synapse memory mapping scheme. 17. The medium of claim 16, wherein a first synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with a first neural network topology type comprising a feed-forward neural network and a second synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with second network topology type comprising a convolutional neural network. 18. The medium of claim 17, wherein a third synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with a third neural network topology type comprising a recurrent neural network. 19. The medium of claim 16, wherein the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-out synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-out synapse weights by the first neuron. 20. The medium of claim 16, wherein the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-in synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-in synapse weights by the first neuron. 21. A system comprising: a neuromorphic processor comprising: a memory to store a plurality of synapse weights of a neural network; and logic to implement a plurality of neurons of the neural network; an input/output interface; and a synapse memory mapping engine to: receive a selection of a neural network topology type, the selection to be received via the input/output interface; identify a synapse memory mapping scheme for the selected neural network topology type from a plurality of synapse memory mapping schemes that are each associated with a respective neural network topology type; and map the plurality of synapse weights to locations in the memory based on the identified synapse memory mapping scheme. 22. The system of claim 21, wherein a first synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with a first neural network topology type comprising a feed-forward neural network and a second synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with second network topology type comprising a convolutional neural network. 23. The system of claim 22, wherein a third synapse memory mapping scheme of the plurality of synapse memory mapping schemes is associated with a third neural network topology type comprising a recurrent neural network. 24. The system of claim 21, wherein the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-out synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-out synapse weights by the first neuron. 25. The system of claim 21, wherein the memory includes a plurality of independently accessible banks and the identified synapse memory mapping scheme specifies the storage of fan-in synapse weights of a first neuron in separate banks of the memory to enable parallel access of the fan-in synapse weights by the first neuron.