A digital quaternary fractal computer unit, system and method for applications of artificial intelligence. The digital quaternary fractal computer comprises optical, nano-scale and quantum embodiments. The system of computation is unique to the device and employs relativistic, quaternary and fractal mechanisms to perform computation. The full theory of relative quaternary fractal computation and encoding is documented in the various references herein. Several methods are also disclosed which evolved out of, and help enhance, the various embodiments. It is emphasized that this abstract is provided to enable a searcher to quickly ascertain the subject matter of the technical disclosure and is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A fractal computing unit (FCU) comprising: a clock signal; a propagation unit comprising: a plurality of signal channels; a plurality of phase switch units; and, a plurality of delay units; at least one data signal comprising at least one wave having a frequency in accordance with the equation f=(frequency of said clock signal)/2n, wherein n is an integer and n≧1, and f is the frequency of said at least one wave; and, at least one input, wherein said at least one input sending said at least one data signal to at least one signal channel of said plurality of signal channels; wherein said plurality of delay units operationally coupled to a said plurality of signal channels, wherein said data signal propagates to said plurality of signal channels, wherein at least one signal channel of said plurality of signal channels operationally coupled to at least one phase switch unit of said plurality of phase switch units, wherein said at least one phase switch unit having an operating frequency in accordance with the equation f=(frequency of said clock signal)/2n, wherein n is an integer and n≧1 and wherein f is the frequency of said operating frequency. 2. The fractal computing unit in claim 1, wherein said plurality of signal channels spatially arranged in the form of a surface quadrilateral mesh, wherein said plurality of signal channels logically divided into two functional groupings comprising: a first signal channel grouping and a second signal channel grouping, wherein said first signal channel grouping operationally coupled to said second signal channel grouping by said plurality of phase switch units and wherein, spatially, intersecting signal channels along the length of said at least one signal channel sequentially alternate between the two functional groupings; wherein said fractal computing unit further comprising: a first variable clock signal derived from said clock signal; a second variable clock signal derived from said clock signal; a first signal channel of said first signal channel grouping; a second signal channel of said second signal channel grouping; a third signal channel of said first signal channel grouping, wherein said third signal channel adjacent to said first signal channel; a fourth signal channel of said second signal channel grouping wherein said fourth signal channel adjacent to said second signal channel; a gate signal channel group comprising, said first signal channel, said second signal channel, said third signal channel, said fourth signal channel; and, a phase clock channel group further comprising: a first variable phase clock signal channel, wherein said first variable phase clock signal channel receiving said first phase clock signal; and, a second variable phase clock signal channel, wherein said second variable phase clock signal channel receiving said second phase clock signal; wherein said at least one phase switch comprising: a first delay unit; a second delay unit; a third delay unit; a modulating unit having a carrier frequency equal to the frequency of said phase clock signal; a demodulating unit having a carrier frequency equal to the frequency of said phase clock signal; a filter unit; a variable signal amplifier; and, at least one switching unit comprising: at least one input; at least one output; and at least one gate; wherein said at least one input operationally coupled by a demodulator unit to said first signal channel or by said first delay unit in combination with said demodulator unit to said first signal channel, wherein said at least one output operationally coupled by said filter unit in combination with said modulator unit to said second signal channel or by said second delay unit in combination with said filter unit in combination with said modulator unit to said second signal channel, and wherein said at least one gate operationally coupled by said variable signal amplifier to one signal channel of said gate signal channel group or by said third delay in combination with said variable signal amplifier to one signal channel of said gate signal channel group, wherein said at least one gate further operationally coupled to one signal channel of said phase clock channel group. 3. The fractal computing unit in claim 2, wherein said plurality of signal channels operationally coupled to a plurality of three signal channel delay units, wherein each three signal channel delay unit of said plurality of three signal channel delay units operationally coupled to two adjacent parallel signal channels and a perpendicular signal channel; wherein said each three signal channel delay unit comprising a phase switch or a phase shift oscillator, or any combination thereof; wherein said analog propagation unit further comprising: a first phase shift unit; a second phase shift unit; a third phase shift unit; a fourth phase shift unit; a first fixed phase signal derived from said phase signal; and, a second fixed phase signal derived from said phase signal and phase shifted by said first phase shift unit; wherein said first signal channel grouping receiving a first fixed phase signal along a first axis and a second axis, and further receiving a second fixed phase signal along said first axis and said second axis wherein said second fixed phase signal shifted by a third phase shift unit; and, wherein said second signal channel grouping receiving said second fixed phase signal along said said first axis and said second axis, and further receiving said first fixed phase signal along said first axis and said second axis, wherein said first fixed phase signal shifted by a fourth phase shift unit. 4. The fractal computing unit in claim 2, wherein said at least one data signal comprising: a plurality of waves, wherein each wave of said plurality of waves having a frequency f derived from the following equation, f=(frequency of said phase clock signal)/2n where n is a positive integer and n≧1, and wherein said each wave synchronized with an external phase clock, and wherein a first polarized half wave of said each wave representing a first quaternary bit and a second polarized half wave of said each wave representing a second quaternary bit thus forming a quaternary fractal signal; 5. The fractal computing unit in claim 2, comprising: a first frequency divider; a second frequency divider; a first variable phase signal derived from said phase signal and divided by said first frequency divider unit, or derived from a second signal, or any combination thereof; a second variable phase signal derived from said phase signal, wherein said phase signal phase shifted by a second phase shift unit and further divided by a second frequency divider unit or derived from a third signal, or any combination thereof; and, an output signal, wherein said phase switch upon switching to an active state, routing said input signal to said output, wherein said switching to an active state triggered by an interference signal received on said gate of said phase switch, wherein said interference signal exceeds the trigger threshold of said phase switch, wherein said signal optionally amplified by said threshold amplifier, and wherein said threshold trigger optionally lowered by said programming signals; wherein said interference signal comprising a combination of said input signal, said propagated signal, said variable phase wave signal, and said fixed phase wave signal. 6. The fractal computing unit in claim 2, characterized in that said FCU is a type A FCU, or a type B FCU, or a combined type AB FCU, wherein said polarization of each phase switch of said type A FCU is a first polarization; wherein said polarization of each phase switch of said type B FCU is a second polarization; wherein said polarization of each phase switch of said type AB FCU is a first polarization or a second polarization. 7. The fractal computing unit in claim 2, wherein said phase switch comprising quantum scale components and utilizing quantum effects; 8. The fractal computing unit in claim 2, characterized in that said FCU is a two dimensional spatio-temporal fractal computer unit, or a three dimensional spatio-temporal fractal computer unit, or a four dimensional spatio-temporal fractal computer unit, or an n-dimensional fractal computer unit, or any combination thereof; wherein said two dimensional spatial-temporal fractal computing unit characterized in that said plurality of signal channels of said super mesh arranged forming a mesh of parallel signal channels, wherein said phase shift units comprising a phase shift selected from the group consisting of: 0′, 180; wherein said three dimensional spatial-temporal fractal computing unit characterized in that said plurality of signal channels of said super mesh arranged forming a two dimensional surface quadrilateral mesh, wherein said phase shift units comprising a phase shift selected from the group consisting of: 0′, 90′, 180′, 270′; wherein said four dimensional spatial-temporal fractal computing unit characterized in that said plurality of signal channels of said super mesh arranged forming a three dimensional hexahedron mesh, wherein said phase shift units comprising a phase shift selected from the group consisting of: 0′, 60′, 120′, 180′, 240′, 300′; wherein said n-dimensional spatial-temporal fractal computing unit characterized in that said plurality of signal channels of said super mesh arranged forming a three dimensional hexahedron mesh, wherein said phase shift units comprising a phase shift conforming to the equation x*360/n where n is the spatial-temporal dimension and x is an integer where x≧0. 9. The fractal computing unit in claim 5, wherein said switching unit further comprising a threshold unit having a threshold characteristic selected from the group consisting of: automatically alterable by a signal produced by said fractal computing unit (FCU), alterable by an external signal, alterable by an external wave, alterable by a pulse, alterable and set at the time of manufacture, unalterable and set at the time of manufacture, or any combination thereof. 10. The fractal computing unit in claim 5, wherein said phase switch comprising an optical transistor. 11. The fractal computing system in claim 5, wherein said fractal computing system comprising: a two dimensional fractal computer unit (2-D FCU), or a three dimensional fractal computer unit (3-D FCU), or a four dimensional fractal computer unit (4-D FCU), or an n-dimensional fractal computer unit (N-D FCU), or any combination thereof, wherein each said fractal computer unit (FCU) comprising said combination thereof, operationally coupled thus forming a multi-dimensional fractal computing system. 12. A fractal computing system comprising: a clock; at least one signal comprising at least one wave wherein said at least one wave having a frequency in accordance with the equation f=(frequency of said clock)/2n, wherein n is an integer and n≧1 and f is the frequency of said at least one wave; a second wave having a frequency in accordance with the equation f=(frequency of said clock)/2n, wherein n is an integer and n≧1 and f is the frequency of said second wave; and, means to conditionally route said at least one signal based on the relative frequency, or phase or polarity, or any combination thereof, of said at least one wave with respect to said second wave. 13. The fractal computer system of claim 12 wherein said means to conditionally route comprising at least one crystal, wherein said crystal selected from the group consisting of: nanocrystal, quantum dot, periodically polled crystal, Lithium Niobate crystal, Lithium Tantalate crystal, twisted nematic liquid crystal, optical lattice crystal, rare earth doped laser crystal, rare earth ion doped crystal, indium tin oxide crystal, carbon nanotube crystal, graphene crystal, flouride doped tin oxide crystal, doped zinc oxide crystal, nanowire crystal, or any combination thereof. 14. The fractal computing system of claim 12 wherein said fractal computing system performing at least one application of artificial intelligence (AI) or operatively coupled to a system performing at least one application of artificial intelligence (AI), wherein said performing at least one application of artificial intelligence (AI) comprising: machine learning, speech recognition, natural language understanding, audition systems, computer vision systems, image processing, movement systems, robotics, artificial speech, face recognition systems, expert systems, medical diagnosis, robot control, language translation, machine driving or any combination thereof. 15. The fractal computing system in claim 12, wherein said means to conditionally route comprising at least one FCU, wherein said fractal computing system further comprising a plurality of fractal computer units (FCUs) wherein said plurality of fractal computer units are operationally coupled and further wherein the spatial distribution of said plurality of fractal computer units selected from the group consisting of: a sequentially repeating tiling pattern, a sequentially repeating quadrilateral surface formed on the surface of a cylinder, a sequentially repeating quadrilateral surface tiling pattern formed on the surface of a cube, a sequentially repeating quadrilateral surface tiling pattern formed on the surface of a cuboid, a sequentially repeating quadrilateral surface tiling pattern formed on the surface of a spheroid, an arbitrary spatial distribution, a periodically changing dynamic spatial distribution, an expanding FCU distribution resulting from the dynamic addition of an FCU, a contracting FCU distribution resulting from the dynamic removal of an FCU; an expanding FCU distribution resulting from the dynamic addition of a plurality of FCUs, a contracting FCU distribution resulting from the dynamic removal of a plurality of FCUs, a dynamic spatial configuration of FCUs operationally coupled to a network, a static spatial configuration of FCUs operationally coupled to a network, a second plurality of fractal computer units operationally coupled to at least one fractal computer unit of said plurality of fractal computer units thus forming a nested parallel fractal computer system, or any combination thereof. 16. A method of fractal computation comprising the steps of: a) receiving a first plurality of inputs; b) generating a plurality of signals from said plurality of inputs; c) sending said plurality of signals along a first plurality of signal channels; d) receiving said plurality of signals by an information potential, wherein said information potential comprising a first plurality of phase switches operationally coupled to said first plurality of signal channels; e) comparing characteristics of said plurality of signals with characteristics of said first plurality of phase switches to generate a plurality of signal match characteristics; f) altering said plurality of signals in accordance with said signal match characteristics; g) routing said plurality of signals to a second plurality of signal channels in accordance with said signal match characteristic; h) forming a plurality of closed loops (circuits) each comprising a second plurality of phase switches; i) propagating said plurality of signals with a plurality of time delay units in synchronism with a phase clock signal; j) creating said first plurality of inputs from a second plurality of inputs in combination with said plurality of signals; k) advancing the phase clock signal; and, l) repeating steps a) to k) until there are no further signals of said plurality of signals. 17. The method in claim 16 wherein said information potential comprising: a trunk information potential, wherein said trunk information potential further comprising: a principal information potential with a threshold characteristic of less than trigger signal; a context information potential with a threshold characteristic of less than trigger signal; a branch information potential, wherein said branch information potential further comprising: a principal information potential with a threshold characteristic of more than trigger signal; a context information potential with a threshold characteristic of more than trigger signal; wherein said principal information potential comprising a plurality of phase switch units having a threshold characteristic that matches the threshold characteristic of said principal information potential, and further wherein said context information potential comprising phase switch units having a threshold characteristic that matches the threshold characteristic of said context information potential; and wherein steps a) to k) are repeated for each of: said trunk information potential; said branch information potential; wherein the steps for said branch information potential further comprising: growing said branch information potential from the end of said trunk information potential until a closed circuit is formed; forming a polarized connection between said input signal channel and said output signal channel, said polarized connection forming the essence of a higher level phase switch formed from the plurality of phase switches; sending a programming pulse to all phase switches in said closed circuit; altering the threshold triggers with said programming pulse; and, optionally repeating input signals to further program said threshold triggers. 18. The method in claim 16 wherein step e) ‘comparing characteristics of said plurality of signals with characteristics of said first plurality of phase switches to generate a plurality of signal match characteristics’, further comprising the steps of: extracting a phase shifted input signal in accordance with a phase characteristic of said phase switch; extracting an interference signal by combining a propagated input signal, a phase shifted input signal, and a variable phase signal; extracting a switch activation signal by comparing said interference signal with a threshold characteristic of said phase switch; demodulating said input signal to produce a demodulated input signal; phase shifting said demodulated input signal in accordance with an input phase characteristic of said phase switch, to produce a phase shifted demodulated input signal; comparing the polarity of said phase shifted demodulated input signal with a polarity characteristic of said phase switch, to produce a polarization match characteristic; filtering said phase shifted demodulated input signal, in accordance with a filtering characteristic of said phase switch, to produce a filtered phase shifted demodulated input signal; and further wherein step f) ‘altering said plurality of signals in accordance with said signal match characteristics’ further comprising the steps of: routing said filtered phase shifted demodulated input signal to an output signal in accordance with polarization match characteristic and switching signal characteristic; and, phase shifting output signal in accordance with an output phase shift characteristic of said switch ing signal router, to produce a phase shifted output signal. 19. The method in claim 18 further comprising the steps of: modifying threshold trigger of said second plurality of phase switches; modifying the amplitude of said first variable phase signal; modifying the amplitude of said second variable phase signal; changing the frequency divider unit of said first variable phase signal in accordance with a predefined step sequence; changing the frequency divider unit of said second variable phase signal in accordance with said predefined step sequence; and, optionally activating said phase switch by a second input derived from a second phase switch of which both said phase switch and said second phase switch form an operationally related pair. 20. The method in claim 19 wherein the step sequence of the step ‘changing the frequency divider unit in accordance with a predefined step sequence’ further comprising, either singularly or in combination thereof, the further steps of: increasing said first frequency divider unit to further halve the frequency of said first variable phase signal; increasing said first frequency divider unit to further halve the frequency of said second variable phase signal; increasing said second frequency divider unit to further halve the frequency of said first variable phase signal; increasing said second frequency divider unit to further halve the frequency of said second variable phase signal; decreasing said first frequency divider unit to further halve the frequency of said first variable phase signal; decreasing said first frequency divider unit to further halve the frequency of said second variable phase signal; decreasing said second frequency divider unit to further halve the frequency of said first variable phase signal; decreasing said second frequency divider unit to further halve the frequency of said second variable phase signal; and, alternating modifying first frequency divider unit and second frequency divider unit.