For risk evaluation, a method encodes event data as a linear array that includes a plurality of logic states. The method estimates a success probability for each logic state and identifies path groups of the plurality of logic states. The logic states of each path group must all be healthy for each logic state to contribute to system success. The method further identifies each path combination of path groups and path nodes that result in system success. In addition, the method calculates a system success probability as a sum of success probabilities for each path combination. The success rate for each path combination is calculated as a product of the path group success probabilities for the path combination.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A method comprising: encoding, by use of a processor, event data as a linear array comprising a plurality of logic states, wherein each logic state represents a path between events of the event data, each logic state comprising one or more binary output variables, one or more binary input variables, one or more minterms of the one or more binary input variables, one or more maxterms of the one or more minterms, one or more present state values, and one or more next state values; estimating a success probability for each logic state; identifying path groups of the plurality of logic states, wherein the logic states of each path group must all be healthy for each logic state to contribute to system success; identifying path nodes wherein equivalent contributions to system success are provided by two or more path groups; identifying each path combination of path groups and path nodes that result in system success; and calculating a system success probability as a sum of success probabilities for each path combination, wherein the success rate for each path combination is calculated as a product of the path group success probabilities for the path combination. 2. The method of claim 1, the method further comprising calculating a success probability for each path combination. 3. The method of claim 1, the method further comprising displaying a probability ranking for each path combination. 4. The method of claim 1, the method further comprising: parsing the logic design into a plurality of logic design elements; identifying conditional logic for each logic design element; identifying computation logic for each logic design element; and identifying an end of state logic design element. 5. The method of claim 1, wherein the path combinations resulting in system success are identified using a combination map. 6. The method of claim 5, wherein the combination map comprises one or more combination maps organized by: organizing the plurality of binary input variables into a plurality of fields in the one or more combination maps, each field of the plurality of fields corresponding to a respective display level of a multi-level display format having a top display level combination map and at least one lower display level combination map; selecting a first field of the plurality of fields, the first field corresponding to a first display level; identifying combinations of the binary input variables of a successive combination map that logically defines the first field of the plurality of fields, wherein the successive combination map is at a successive display level lower than the first display level; displaying at each successive display level, combination maps of additional binary input variables that logically define the first field at each successive level until a last display level is reached; and converting the combination of binary input variables for each display level into a logical expression. 7. A program product comprising a non-transitory computer readable storage medium that stores code executable by a processor, the executable code comprising code to perform: encoding event data as a linear array comprising a plurality of logic states, wherein each logic state represents a path between events of the event data, each logic state comprising one or more binary output variables, one or more binary input variables, one or more minterms of the one or more binary input variables, one or more maxterms of the one or more minterms, one or more present state values, and one or more next state values; estimating a success probability for each logic state; identifying path groups of the plurality of logic states, wherein the logic states of each path group must all be healthy for each logic state to contribute to system success; identifying path nodes wherein equivalent contributions to system success are provided by two or more path groups; identifying each path combination of path groups and path nodes that result in system success; and calculating a system success probability as a sum of success probabilities for each path combination, wherein the success rate for each path combination is calculated as a product of the path group success probabilities for the path combination. 8. The program product of claim 7, the code further calculating a success probability for each path combination. 9. The program product of claim 7, the code further displaying a probability ranking for each path combination. 10. The program product of claim 7, the code further: parsing the logic design into a plurality of logic design elements; identifying conditional logic for each logic design element; identifying computation logic for each logic design element; and identifying an end of state logic design element. 11. The program product of claim 7, wherein the path combinations resulting in system success are identified using a combination map. 12. The program product of claim 11, wherein the combination map comprises one or more combination maps organized by: organizing the plurality of binary input variables into a plurality of fields in the one or more combination maps, each field of the plurality of fields corresponding to a respective display level of a multi-level display format having a top display level combination map and at least one lower display level combination map; selecting a first field of the plurality of fields, the first field corresponding to a first display level; identifying combinations of the binary input variables of a successive combination map that logically defines the first field of the plurality of fields, wherein the successive combination map is at a successive display level lower than the first display level; displaying at each successive display level, combination maps of additional binary input variables that logically define the first field at each successive level until a last display level is reached; and converting the combination of binary input variables for each display level into a logical expression. 13. An apparatus comprising: a processor; a non-transitory memory that stores code executable by the processor, the code comprising: code that encodes event data as a linear array comprising a plurality of logic states, wherein each logic state represents a path between events of the event data, each logic state comprising one or more binary output variables, one or more binary input variables, one or more minterms of the one or more binary input variables, one or more maxterms of the one or more minterms, one or more present state values, and one or more next state values; code that estimates a success probability for each logic state; code that identifies path groups of the plurality of logic states, wherein the logic states of each path group must all be healthy for each logic state to contribute to system success; code that identifies path nodes wherein equivalent contributions to system success are provided by two or more path groups; code that identifies each path combination of path groups and path nodes that result in system success; and code that calculates a system success probability as a sum of success probabilities for each path combination, wherein the success rate for each path combination is calculated as a product of the path group success probabilities for the path combination. 14. The apparatus of claim 13, the code further comprising code that calculates a success probability for each path combination. 15. The apparatus of claim 13, the code further comprising code displays a probability ranking for each path combination. 16. The apparatus of claim 13, the code further: parsing the logic design into a plurality of logic design elements; identifying conditional logic for each logic design element; identifying computation logic for each logic design element; and identifying an end of state logic design element. 17. The apparatus of claim 13, wherein the path combinations resulting in system success are identified using a combination map. 18. The apparatus of claim 17, wherein the combination map comprises one or more combination maps organized by: organizing the plurality of binary input variables into a plurality of fields in the one or more combination maps, each field of a plurality of fields corresponding to a respective display level of a multi-level display format having a top display level combination map and at least one lower display level combination map; selecting a first field of the plurality of fields, the first field corresponding to a first display level; identifying combinations of the binary input variables of a successive combination map that logically defines the first field of the plurality of fields, wherein the successive combination map is at a successive display level lower than the first display level; displaying at each successive display level, combination maps of additional binary input variables that logically define the first field at each successive level until a last display level is reached; and converting the combination of binary input variables for each display level into a logical expression.