Embodiments of the invention relate to a multiplexed neural core circuit. One embodiment comprises a core circuit including a memory device that maintains neuronal attributes for multiple neurons. The memory device has multiple entries. Each entry maintains neuronal attributes for a corresponding neuron. The core circuit further comprises a controller for managing the memory device. In response to neuronal firing events targeting one of said neurons, the controller retrieves neuronal attributes for the target neuron from a corresponding entry of the memory device, and integrates said firing events based on the retrieved neuronal attributes to generate a firing event for the target neuron.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A multiplexed neural network system, comprising: a memory device configured to consolidate and maintain neuronal attributes for multiple neurons belonging to a plurality of neural core circuits, wherein the memory device is scaled in at least one dimension, and the neuronal attributes maintained in the memory device are arranged based on the at least one dimension; and at least one controller, wherein each controller is configured to processes a neuronal firing event targeting a neuron of the multiple neurons based on at least one neuronal attribute maintained in the memory device for the neuron. 2. The multiplexed neural network system of claim 1, wherein: the memory device includes multiple entries; and each entry of the memory device maintains at least one neuronal attribute for a neuron of the multiple neurons. 3. The multiplexed neural network system of claim 2, wherein: the multiple entries of the memory device are organized into multiple subsets; and each subset corresponds to a neural core circuit of the plurality of neural core circuits, and, for each neuron of the corresponding neural core circuit, the subset includes an entry maintaining at least one neuronal attribute for the neuron. 4. The multiplexed neural network system of claim 3, wherein: the at least one dimension comprises a height dimension; the memory device is scaled in the height dimension, such that the memory device has multiple rows; and the multiple entries of the memory device are organized into the multiple subsets by dividing the multiple rows into the multiple subsets. 5. The multiplexed neural network system of claim 4, wherein: neuronal firing events targeting the multiple neurons are processed by only one controller, such that the plurality of neural core circuits share the same controller. 6. The multiplexed neural network system of claim 5, wherein: an optimal height of the memory device is based on a maximum number of neurons that the controller can process neuronal firing events for within a time step. 7. The multiplexed neural network system of claim 3, wherein: the at least one dimension comprises a width dimension; the memory device is scaled in the width dimension, such that the memory device has multiple columns; and the multiple entries of the memory device are organized into the multiple subsets by dividing the multiple columns into the multiple subsets. 8. The multiplexed neural network system of claim 7, wherein: each subset has a corresponding controller configured to process neuronal firing events targeting neurons of a corresponding neural core circuit based on neuronal attributes maintained in the subset. 9. The multiplexed neural network system of claim 3, wherein: the at least one dimension comprises a height dimension and a width dimension; the memory device is scaled in the height dimension and the width dimension, such that the memory device has multiple rows and multiple columns; the multiple entries of the memory device are organized into the multiple subsets by dividing the multiple rows and multiple columns into the multiple subsets; and the multiple subsets are organized into multiple groups, wherein each group corresponds to two or more neural core circuits of the plurality of neural core circuits. 10. The multiplexed neural network system of claim 9, wherein: each group has a corresponding controller configured to process neuronal firing events targeting neurons of two or more corresponding neural core circuits based on neuronal attributes maintained in subsets of the group, such that the two or more corresponding neural core circuits share the same controller. 11. The multiplexed neural network system of claim 10, wherein: the multiple neurons are updated sequentially. 12. The multiplexed neural network system of claim 10, wherein: the multiple neurons are updated in parallel. 13. The multiplexed neural network system of claim 1, wherein: consolidating the neuronal attributes for the multiple neurons into the memory device reduces passive power consumption. 14. A method, comprising: consolidating and maintaining neuronal attributes for multiple neurons belonging to a plurality of neural core circuits into a memory device, wherein the memory device is scaled in at least one dimension, and the neuronal attributes maintained in the memory device are arranged based on the at least one dimension; and processing, via a controller, a neuronal firing event targeting a neuron of the multiple neurons based on at least one neuronal attribute maintained in the memory device for the neuron. 15. The method of claim 14, wherein: the memory device includes multiple entries; and each entry of the memory device maintains at least one neuronal attribute for a neuron of the multiple neurons. 16. The method of claim 15, wherein: the multiple entries of the memory device are organized into multiple subsets; and each subset corresponds to a neural core circuit of the plurality of neural core circuits, and, for each neuron of the corresponding neural core circuit, the subset includes an entry maintaining at least one neuronal attribute for the neuron. 17. The method of claim 16, wherein: the at least one dimension comprises a height dimension; the memory device is scaled in the height dimension, such that the memory device has multiple rows; and the multiple entries of the memory device are organized into the multiple subsets by dividing the multiple rows into the multiple subsets. 18. The method of claim 17, wherein: neuronal firing events targeting the multiple neurons are processed by only one controller, such that the plurality of neural core circuits share the same controller. 19. The method of claim 16, wherein: the at least one dimension comprises a width dimension; the memory device is scaled in the width dimension, such that the memory device has multiple columns; and the multiple entries of the memory device are organized into the multiple subsets by dividing the multiple columns into the multiple subsets. 20. The method of claim 19, wherein: each subset has a corresponding controller configured to process neuronal firing events targeting neurons of a corresponding neural core circuit based on neuronal attributes maintained in the subset.