The amount of speed-up that can be obtained by optimizing the program to run on a different architecture is determined by static measurements of the program. Multiple such static measurements are processed by a machine learning system after being discretized to alter their accuracy vs precision. Static analysis requires less analysis overhead and permits analysis of program portions to optimize allocation of porting resources on a large program.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. An electronic computer executing a program stored in non-transitive medium to: (a) perform a static analysis of a target computer program prepared to execute on a first computer architecture to determine static properties of the target computer program selected from a set of static program properties relating to how the target computer program would dynamically execute on a second computer architecture having a different architecture than the first computer architecture; (b) apply the static properties to a machine learning model, the machine learning model trained using a training set of programs each having a first optimization for the first computer architecture and a second optimization for the second computer architecture, the training set providing (1) an empirically measured change in execution speed between the first optimization and the second optimization when running on the respective computer architectures and (2) static properties of the set of static program properties of the first optimization; and (c) output a speed-up value from the machine learning model to a user indicating an expected increase in execution speed of the target computer program when executed on the second computer architecture. 2. The electronic computer of claim 1 wherein each of the static properties and training static properties are discretized to a corresponding sets of ranges less than five. 3. The electronic computer of claim 2 wherein the ranges are selected to provide bins holding substantially equal numbers of the measured static properties of the training set of programs. 4. The electronic computer of claim 1 wherein the empirically measured changes in execution speed are discretized to a set of ranges less than five. 5. The electronic computer of claim 4 wherein the empirically measured changes in execution speed are discretized to a user-selected set of ranges selectable by the user and further wherein the speed-up value output to the user is discretized to the user-selected ranges 6. The electronic computer of claim 1 wherein the set of static program properties provides a static indication of memory coalescing in the target program related to an amount of access to external memory. 7. The electronic computer of claim 6 wherein the static indication of memory coalescing assesses memory access instructions in a loop according to whether an address of the instruction includes loop invariant terms or loop induction variable based terms that are not the loop induction variable times a value. 8. The electronic computer of claim 7 wherein the static indication of memory coalescing is discretized to a binary value. 9. The electronic computer of claim 1 wherein the multiple static program properties further provide a static assessment of an intensity of arithmetic instructions in the instructions of the target program. 10. The electronic computer of claim 9 wherein the static assessment of an intensity of arithmetic instructions is a ratio of arithmetic to memory access instructions. 11. The electronic computer of claim 9 wherein the static assessment of the intensity of arithmetic instructions is discretized to a binary value. 12. The electronic computer of claim 9 wherein the set of static program properties provides a static indication of branch divergence in the target program related to variation in execution paths between successive executions of a branch instruction. 13. The electronic computer of claim 12 wherein the static indication of branch divergence assesses branch instructions in a loop according to whether the branch conditions are loop invariant terms or based on loop induction variables. 14. The electronic computer of claim 12 wherein the static indication of branch divergence assesses whether the branch instructions include branch conditions based on access to processor external memory. 15. The electronic computer of claim 1 wherein the set of static program properties further includes at least one of assessment of kernel size of an average number of instructions in one thread, available parallelism indicating how many threads can potentially run on the second architecture in parallel, control intensity providing a measure of whether control instructions rely on data from external memory and complex arithmetic ratios indicating the number of complex arithmetic instructions selected from the group of multiplication, division, sine, cosign, floating-point log, floating-point exponent and square root. 16. The electronic computer of claim 1 wherein the machine learning model is a random forest classifier. 17. The electronic computer of claim 16 wherein the random forest classifier selects and combines random forests of binary decision trees. 18. The electronic computer of claim 1 wherein the electronic computer further includes each of the first and second architectures. 19. The electronic computer of claim 1 wherein the program is a portion of a main computer program and wherein the electronic computer includes the first architecture and further executes the program to: execute the main program on the first architecture to measure a call hierarchy of different portions of the main program including the target program when the main program is executing on the first architecture; perform a static analysis of the different portions of the main program to determine static properties of the each of the different portions selected from the set of static program properties; apply the static properties of each of the different portions to the machine learning model; and provide a comparison of speed-up value from the machine learning model for each of the different portions to a user indicating a relative increase in execution speed of each of the different portions when executed on the second computer architecture. 20. A method of assessing effects of a computer architecture on program execution speed of a target program comprising the steps of: (a) performing a static analysis of the target computer program prepared to execute on a first computer architecture to determine static properties of the target computer program selected from a set of static program properties relating to how the target computer program would dynamically execute on a second computer architecture having a different architecture than the first computer architecture; (b) applying the static properties to a machine learning model, the machine learning model trained using a training set of programs each having a first optimization for the first computer architecture and a second optimization for the second computer architecture, the training set providing an empirically measured change in execution speed between the first optimization and the second optimization when running on the respective computer architectures and training static properties of the set of static program properties for the first optimization; and (c) outputting a speed-up value from the machine learning model to a user indicating an expected increase in execution speed of the target computer program when executed on the second computer architecture.