Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A system, comprising: a first two-dimensional array of digital-to-analog converters (DACs) comprising a plurality of DACs arranged in a plurality of sub-arrays, each sub-array comprising a number of rows, a first column of DACs, and a second column of DACs; a first power line coupled to selectively provide a current to the DACs of the first column of each sub-array of the plurality of sub-arrays of the first two-dimensional array; a second power line coupled to selectively provide a current to the DACs of the second column of each sub-array of the plurality of sub-arrays of the first two-dimensional array; and a first control line positioned proximate each DAC along a first diagonal of the first two-dimensional array of DACs to communicatively couple with the respective DACs along the first diagonal of the first two-dimensional array of DACs. 2. The system of claim 1 wherein the first diagonal of the first two-dimensional array of DACs extends across each row of the number of rows, the first column, and the second column of each sub-array of the plurality of sub-arrays of the first two-dimensional array of DACs. 3. The system of claim 1, further comprising: at least a second two-dimensional array of DACs comprising a plurality of DACs arranged in a plurality of sub-arrays, each sub-array comprising a number of rows, a first column of DACs, and a second column of DACs; wherein the first power line is further coupled to selectively provide a current to the DACs of the second column of each sub-array of the plurality of sub-arrays of the second two-dimensional array; the second power line is further coupled to selectively provide a current to the DACs of the first column of the sub-arrays of the second two-dimensional array; and the first control line is further positioned proximate each DAC along a first diagonal of the second two-dimensional array of DACs to communicatively couple with the respective DACs along the first diagonal of the second two-dimensional array of DACs. 4. The system of claim 3 wherein the first diagonal of the first two-dimensional array of DACs extends across each row of the number of rows, the first column, and the second column of each sub-array of the plurality of sub-arrays of the first two-dimensional array of DACs. 5. The system of claim 3 wherein the first diagonal of the second two-dimensional array of DACs extends across each row of the number of rows, the first column, and the second column of each sub-array of the plurality of sub-arrays of the second two-dimensional array of DACs. 6. The system of claim 4 wherein the first diagonal of the first two-dimensional array is perpendicular to the first diagonal of the second two-dimensional array. 7. The system of claim 3 wherein the first control line follows a meandering path along the first diagonal of the first two-dimensional array of DACs and the first control line follows a meandering path along the first diagonal of the second two-dimensional array of DACs. 8. The system of claim 3 wherein the first control line follows a meandering path along the first diagonal of the first two-dimensional array of DACs and the first control line follows a meandering path along a second diagonal of the first two-dimensional array of DACs. 9. The system of claim 3 further comprising: a second control line positioned proximate each DAC along a third diagonal of the first two-dimensional array of DACs to communicatively couple with the respective DACs along the third diagonal of the first two-dimensional array of DACs and the second control line further positioned proximate each DAC along a second diagonal of the second two-dimensional array of DACs to communicatively couple with the respective DACs along the second diagonal of the second two-dimensional array of DACs. 10. The system of claim 9 further comprising: a third control line positioned proximate each DAC along a second diagonal of the first array to communicatively couple with the respective DACs along the second diagonal of the first array and the third control line is further positioned proximate each DAC along a third diagonal of the second array to communicatively couple with the respective DACs along the third diagonal of the second array. 11. The system of claim 3 further comprising: a second control line positioned proximate each DAC along a third diagonal of the first two-dimensional array of DACs to communicatively couple with the respective DACs along the third diagonal of the first two-dimensional array of DACs and the second control line further positioned proximate each DAC along a fourth diagonal of the first two-dimensional array of DACs to communicatively couple with the respective DACS along the fourth diagonal of the first two-dimensional array of DACs. 12. The system of claim 11 further comprising: a third control line positioned proximate each DAC along a second diagonal of the first array to communicatively couple with the respective DACs along the second diagonal of the first array and the third control line is further positioned proximate each DAC along a first diagonal of the first array to communicatively couple with the respective DACs along the first diagonal of the first array. 13. The system of claim 1 wherein there are a number n of control lines and a number P of power lines and each of the first and the second array of DACs includes a number P(n−1)2 of DACs. 14. The system of claim 1, further comprising: control circuitry communicatively coupled to cause signals to be supplied to selected ones of the DACs via a respective triplet comprising one power line and two of the signal lines, the triplet uniquely communicatively coupled to operate a single respective DAC. 15. The system of claim 1 wherein: the first power line is coupled to selectively provide a current to the DACs of a third column of the first two-dimensional array of DACs, the third column non-adjacent to the first column; the second power line is coupled to selectively provide a current to the DACs of a fourth column of the first two-dimensional array of DACs, the fourth column non-adjacent to the second column; and the first control line is positioned operatively proximate at least one DAC in each of at least three rows and at least three columns of the first two-dimensional array of DACs to communicatively couple with the respective DACs in each of at least three rows and at least three columns of the first two-dimensional array of DACs. 16. The system of claim 15, further comprising: at least a second two-dimensional array of DACs comprising a plurality of DACs that are not DACs in the first two-dimensional array, and which are arranged in a plurality of rows and a plurality of columns of the second two-dimensional array; wherein the second power line is further coupled to selectively provide a current to the DACs of a third column of the second two-dimensional array of DACs, the third column non-adjacent to the first column of the second two-dimensional array of DACs; and the first power line is further coupled to selectively provide a current to the DACs of a fourth column of the second two-dimensional array of DACs, the fourth column non-adjacent to the second column of the second two-dimensional array of DACs. 17. The system of claim 15, further comprising: a second control line positioned operatively proximate at least one DAC in each of at least three rows and at least three columns of the first two-dimensional array of DACs to communicatively couple with the respective DACs in each of at least three rows and at least three columns of the first two-dimensional array of DACs. 18. The system of claim 17 wherein the first control line and the second control line are positioned operatively proximate different DACs, with no DAC in common. 19. The system of claim 18 wherein the first control line and the second control line are positioned operatively proximate a same at least one of DACs, with the at least one DAC in common. 20. A method of operation in a system including: a first two-dimensional array of digital-to-analog converters (DACs) comprising a plurality of DACs arranged in a plurality of sub-arrays, each sub-array comprising a number of rows, a first column, and a second column of DACs; a first power line coupled to selectively provide a current to the DACs of the first column of each sub-array of the plurality of sub-arrays of the first two-dimensional array; a second power line coupled to selectively provide a current to the DACs of the second column of each sub-array of the plurality of sub-arrays of the first two-dimensional array; a first control line positioned proximate each DAC along a first diagonal of the first two-dimensional array of DACs to communicatively couple with the respective DACs along the first diagonal of the first two-dimensional array of DACs; a second control line positioned proximate each DAC along a second diagonal of the first two-dimensional array of DACs to communicatively couple with the respective DACs along the second diagonal of the first two-dimensional array of DACs, the method comprising: during a first period of time, concurrently: applying signals to a first DAC via the first power line; applying signals to the first DAC via the first control line; and applying signals to the first DAC via the second control line. 21. A system, comprising: a first array of digital-to-analog converters (DACs) comprising a plurality of DACs arranged in a plurality of rows and a plurality of columns of the first array; a first power line coupled to selectively provide a current to each DAC of a first column of the first array, the DACs of the first column positioned in a first arrangement; the first power line further coupled to selectively provide a current to each DAC of a second column of the first array, the DACs of the second column positioned in a second arrangement; a first control line positioned operatively proximate each DAC of the first column and the second column of the first array to communicatively couple with the respective DACs of the first column and the second column of the first array; a second control line positioned operatively proximate each DAC of first column of the first array to communicatively couple with the respective DACs of the first column of the first array; and a third control line positioned operatively proximate each DAC of the second column of the first array to communicatively couple with the respective DACs of second column of the first array. 22. The system of claim 21 further comprising: a third column of DACs positioned in the first arrangement, the third column interposed between the first column and the second column of the first array; a fourth column of DACs positioned in the second arrangement, the fourth column adjacent to the second column of the first array; a second power line coupled to selectively provide a current to each DAC of the third column and the fourth column of the first array; wherein the first control line is further positioned operatively proximate each DAC of the third column and the fourth column of the first array to communicatively couple with the respective DACs of the third column and the fourth column of the first array; the second control line is further positioned operatively proximate each DAC of third column of the first array to communicatively couple with the respective DACs of the third column of the first array; and the third control line is further positioned operatively proximate each DAC of the fourth column of the first array to communicatively couple with the respective DACs of the fourth column of the first array. 23. The system of claim 22 further comprising: a fifth column of DACs positioned in the first arrangement, the fifth column interposed between the third column and the second column of the first array; a sixth column of DACs positioned in the second arrangement, the sixth column adjacent to the fourth column of the first array; a third power line coupled to selectively provide a current to each DAC of the fifth column and the sixth column of the first array; wherein the first control line is further positioned operatively proximate each DAC of the fifth column and the sixth column of the first array to communicatively couple with the respective DACs of the fifth column and the sixth column of the first array; the second control line is further positioned operatively proximate each DAC of the fifth column of the first array to communicatively couple with the respective DACs of the fifth column of the first array; and the third control line is further positioned operatively proximate each DAC of the sixth column of the first array to communicatively couple with the respective DACs of the sixth column of the first array. 24. The system of claim 23 further comprising: a first additional column of DACs positioned in the first arrangement, the first additional column interposed between the second column and a subset of columns of the first array that includes DACs positioned in the first arrangement; a second additional column of DACs positioned in the second arrangement, the second additional column adjacent to a subset of columns of the first array that includes DACs positioned in the second arrangement; an additional power line coupled to selectively provide a current to each DAC of the first additional column and the second additional column of the first array; wherein the first control line is further positioned operatively proximate each DAC of the first additional column and the second additional column to communicatively couple with the respective DACs of the first additional column and the second additional column of the first array; the second control line is further positioned operatively proximate each DAC of the first additional column to communicatively couple with the respective DACs of the first additional column of the first array; and the third control line further is positioned operatively proximate each DAC of the second additional column to communicatively couple with the respective DACs of the second additional column of the first array. 25. The system of claim 21 further comprising: at least a second array of DACs comprising a plurality of DACs that are not DACs in the first array, and which are arranged in a plurality of rows and a plurality of columns of the second array; wherein the first power line is coupled to selectively provide a current to each DAC of a first column of the second array, the DACs of the first column positioned in the first arrangement; the first power line is further coupled to selectively provide a current to each DAC of a second column of the second array, the DACs of the second column positioned in a second arrangement; the second control line is positioned operatively proximate each DAC of the second column of the second array to communicatively couple with the respective DACs of the second column of the second array; a fourth control line positioned operatively proximate each DAC of the first column and the second column of the second array to communicatively couple with the respective DACs of the first column and the second column of the second array; and a fifth control line is positioned operatively proximate each DAC of the first column of the second array to communicatively couple with the respective DACs of the first column of the second array. 26. The system of claim 25 further comprising: a first additional column of DACs positioned in the first arrangement, the first additional column interposed between the second column of the second array and a subset of columns of the second array that includes DACs positioned in the first arrangement; a second additional column of DACs positioned in the second arrangement, the second additional column adjacent to a subset of columns of the second array that includes DACs positioned in the second arrangement; an additional power line coupled to selectively provide a current to each DAC of the first additional column and the second additional column of the second array; the second control line is further positioned operatively proximate each DAC of the second additional column to communicatively couple with the respective DACs of the second additional column of the second array; the fourth control line is further positioned operatively proximate each DAC of the first additional column and the second additional column to communicatively couple with the respective DACs of the first additional column and the second additional column of the second array; and the fifth control line is further positioned operatively proximate each DAC of the first additional column to communicatively couple with the respective DACs of the first additional column of the second array. 27. The system of claim 26 further comprising a third array wherein the fourth control line is electrically coupled to the first control line of the third array. 28. The system of claim 26 further comprising a third array wherein the fifth control line is electrically coupled to the third control line of the third array. 29. The system of claim 21 further comprising: at least a second array of DACs comprising a plurality of DACs that are not DACs in the first array, and which are arranged in a plurality of rows and a plurality of columns of the second array; wherein the first power line is coupled to selectively provide a current to each DAC of a first column and a second column of the second array; wherein the first control line is positioned operatively proximate each DAC of the first column and the second column of the second array to communicatively couple with the respective DACs of the first column and the second column of the second array; a fourth control line is positioned operatively proximate each DAC of the first column of the second array to communicatively couple with the respective DACs of the first column of the second array; and a fifth control line is positioned operatively proximate each DAC of the second column of the second array to communicatively couple with the respective DACs of the second column of the second array. 30. The system of claim 29 further comprising: a first additional column of DACs positioned in the first arrangement, the first additional column interposed between the second column and a subset of columns that includes DACs positioned in the first arrangement of the second array; a second additional column of DACs positioned in the first arrangement, the second additional column adjacent to a subset of columns that includes DACs positioned in the second arrangement of the second array; an additional power line coupled to selectively provide a current to each DAC of the first additional column and the second additional column; wherein the first control line is further positioned operatively proximate each DAC of the first additional column and the second additional column to communicatively couple with the respective DACs of the first additional column and the second additional column; the fourth control line is further positioned operatively proximate each DAC of the first additional column to communicatively couple with the respective DACs of the first additional column; and the fifth control line is further positioned operatively proximate each DAC of the second additional column to communicatively couple with the respective DACs of the second additional column. 31. The system of claim 30 further comprising a third array wherein the fourth control line is electrically coupled to the third control line of the third array. 32. The system of claim 30 further comprising a third array wherein the fifth control line is electrically coupled to the second control line of the third array. 33. The system of claim 21 wherein there are a number n(n−1)P of DACs controlled by a total of n control lines and P power lines. 34. The system of claim 21 wherein there are a total of P power lines and the first array includes a number 2P of DACs. 35. The system of claim 21, further comprising: control circuitry communicatively coupled to cause signals to be supplied to selected ones of the DACs via a respective triplet comprising one power line and two of the signal lines, the triplet uniquely communicatively coupled to operate a single respective DAC. 36. A method of operation in a system, the system including: a first array of digital-to-analog converters (DACs) comprising a plurality of DACs arranged in a plurality of rows and a plurality of columns of the first array; a first power line coupled to selectively provide a current to each DAC of a first column of the first array, the DACs of the first column positioned in a first arrangement; the first power line further coupled to selectively provide a current to each DAC of a second column of the first array, the DACs of the second column positioned in a second arrangement; a second power line coupled to selectively provide a current to each DAC of a third column of DACs positioned in the first arrangement, the third column interposed between the first column and the second column of the first array; the second power line further coupled to selectively provide a current to each DAC of a fourth column of DACs positioned in the second arrangement, the fourth column adjacent to the second column of the first array; and a first control line positioned operatively proximate each DAC of the first column and the second column of the first array to communicatively couple with the respective DACs of the first column and the second column of the first array, the first control line also positioned operatively proximate each DAC of the third column and the fourth column of the first array to communicatively couple with the respective DACs of the third column and the fourth column of the first array; a second control line positioned operatively proximate each DAC of first column of the first array to communicatively couple with the respective DACs of the first column of the first array, the second control line also positioned operatively proximate each DAC of third column of the first array to communicatively couple with the respective DACs of the third column of the first array, the method comprising: during a first period of time, concurrently: applying signals to a first DAC and a second DAC via the first power line; applying signals to a third DAC and a fourth DAC via the second power line; applying signals to the first, the second, the third, and the fourth DACs via the first control line; and applying signals to the first, the second, the third, and the fourth DACs via the second control line. 37. A system, comprising: a number N of control lines; a number P of power lines; a plurality of digital-to-analog converters (DACs), each of the DACs of the plurality of DACs including a respective loop of material and a respective pair of Josephson junctions that interrupt the respective loop and are electrically coupled in parallel with one another in the loop of material; and a plurality of control lines arranged in a braided configuration and communicatively coupled to the DACs of the plurality of DACs; wherein the sum of the DACs in the plurality of DACs includes a number N(N−1)P of DACs that are communicatively coupled to respective triplets of signal lines to be controlled via signals carried by the respective triplet of signal lines. 38. The system of claim 37 wherein each DAC is controlled via a respective triplet of signal lines, each triplet comprising a unique combination of two control lines and one of the power lines.