A memory control unit for handling data stored in a memory device includes a first interface to an interconnection with at least one memory bank; a second interface for communicating with a data requesting unit; and a memory quantization unit. The memory quantization unit is configured to: obtain, via the first interface, a first weight value from the at least one memory bank; quantize the first weight value to generate at least one quantized weight value having a shorter bit length than a bit length of the first weight value; and communicate the at least one quantized weight value to the data requesting unit via the second interface.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A memory control unit comprising: a first interface to an interconnection with at least one memory bank; a second interface for communicating with a data requesting unit; and a memory quantization unit configured to: obtain, via the first interface, a first weight value from the at least one memory bank; quantize the first weight value to generate at least one quantized weight value having a shorter bit length than a bit length of the first weight value; and communicate the at least one quantized weight value to the data requesting unit via the second interface. 2. The memory control unit of claim 1 wherein quantizing the first weight value comprises a deterministic process to determine a quantization level for the first weight value to generate the at least one quantized weight value. 3. The memory control unit of claim 1 wherein quantizing the first weight value comprises a stochastic process for selecting a quantization level from a plurality of quantization levels based on the first weight value to generate the at least one quantized weight value. 4. The memory control unit of claim 1 wherein the memory quantization unit is configured to quantize the first weight value multiple times to generate a plurality of quantized weight values; and communicate the plurality of quantized weight values in parallel to the data requesting unit via the second interface. 5. The memory control unit of claim 1 wherein the first weight value represents a weight for a connection of a neural network. 6. The memory control unit of claim 1 wherein the first interface has a higher bandwidth than the second interface. 7. The memory control unit of claim 1 wherein the at least one quantized weight value is a binary or ternary value. 8. The memory control unit of claim 1 wherein the memory control unit is at least a portion of a logic layer of a memory device. 9. The memory control unit of claim 1 wherein the memory control unit comprises a portion of a stacked memory device. 10. A method for quantizing data stored in a memory device, the method comprising: upon receiving, at a memory control unit, a quantized data request, obtaining a first weight value from the memory device; quantizing, with a memory quantization unit, the first weight value to generate at least one quantized weight value having a shorter bit length than a bit length of the first weight value; and communicating the at least one quantized weight value to a data requesting unit. 11. The method of claim 10 wherein quantizing the first weight value comprises a deterministic process to determine a quantization level for the first weight value to generate the at least one quantized weight value. 12. The method of claim 10 wherein quantizing the first weight value comprises a stochastic process for selecting a quantization level from a plurality of quantization levels based on the first weight value to generate the at least one quantized weight value. 13. The method of claim 10 comprising quantizing the first weight value multiple times to generate a plurality of quantized weight values; and communicating the plurality of quantized weight values in parallel to the data requesting unit via the second interface. 14. The method of claim 10 wherein the at least one quantized weight value is a binary or ternary value. 15. The method of claim 10 wherein the first weight value represents a weight for a connection of a neural network. 16. A circuit comprising: a memory control unit including a first interface to an interconnection with at least one memory bank; a second interface for communicating with a data requesting unit; and a memory quantization unit configured to: obtain, via the first interface, a first weight value from the at least one memory bank; quantize the first weight value to generate at least one quantized weight value having a shorter bit length than a bit length of the first weight value; and communicate the at least one quantized weight value to the data requesting unit via the second interface. 17. The circuit of claim 16 wherein quantizing the first weight value comprises a deterministic process to determine a quantization level for the first weight value to generate the at least one quantized weight value. 18. The circuit of claim 16 wherein quantizing the first weight value comprises a stochastic process for selecting a quantization level from a plurality of quantization levels based on the first weight value to generate the at least one quantized weight value. 19. The circuit of claim 16 wherein the memory quantization unit is configured to quantize the first weight value multiple times to generate a plurality of quantized weight values; and communicate the plurality of quantized weight values in parallel to the data requesting unit via the second interface. 20. The circuit of claim 16 wherein the first interface has a higher bandwidth than the second interface. 21. The circuit of claim 16 comprising a memory device, wherein the memory control unit is at least a portion of a logic layer of the memory device. 22. The circuit of claim 16 comprising the data requesting unit, the data requesting unit including a neural network architecture, wherein the first weight value represents a weight for a connection of the neural network architecture.