Systems and methods for an interconnection scheme for reconfigurable neuromorphic hardware are disclosed. A neuromorphic processor may include a plurality of corelets, each corelet may include a plurality of synapse arrays and a neuron array. Each synapse array may include a plurality of synapses and a synapse array router coupled to synapse outputs in a synapse array. Each synapse may include a synapse input, synapse output; and a synapse memory. A neuron array may include a plurality of neurons, each neuron may include a neuron input and a neuron output. Each synapse array router may include a first logic to route one or more of the synapse outputs to one or more of the neuron inputs.
Please help me write a proper abstract based on the patent claims. CLAIM: 1. A neuromorphic processor, comprising: a plurality of corelets, each corelet to include: a plurality of synapse arrays, each synapse array to include: a plurality of synapses, each synapse to include: a synapse input; a synapse output; and a synapse memory; a synapse array router coupled to the synapse outputs in the synapse array; and a neuron array to include a plurality of neurons, each neuron to include a neuron input and a neuron output; wherein each synapse array router includes a first logic to route one or more of the synapse outputs to one or more of the neuron inputs. 2. The neuromorphic processor of claim 1, wherein a first synapse array router includes a second logic to route a synapse output to a neuron input of a neuron in a different corelet. 3. The neuromorphic processor of claim 1, wherein each synapse further includes a synapse memory to store a synapse destination and a synapse weight. 4. The neuromorphic processor of claim 3, wherein a first synapse array router includes: a second logic to read at least one synapse memory; a third logic identify a synapse destination; a fourth logic to identify a synapse weight; and a fifth logic to transmit a packet including the synapse weight and the synapse destination to a neuron group router, based on a routing algorithm. 5. The neuromorphic processor of claim 4, wherein the neuron group router includes: a sixth logic to receive the packet; a seventh logic to identify the synapse destination; a eighth logic to identify the synapse weight; and a ninth logic to transmit the synapse weight to at least one of the neuron inputs. 6. The neuromorphic processor of claim 1, wherein in one of the corelets the number of synapses to be routed to one of the neuron inputs is greater than the number of synapses in the corelet. 7. The neuromorphic processor of claim 1, further comprising a processor including a second logic to write initial synapse destinations and initial synapse weights into the synapse memory of each of the plurality of synapses in a first corelet, wherein at least one of the synapse destinations is to a neuron array in a second corelet. 8. A reconfigurable neuromorphic processor logic unit, comprising: a plurality of corelets, each corelet to include: a plurality of synapse arrays, each synapse array to include: a plurality of synapses, each synapse to include: a synapse input; a synapse output; and a synapse memory; a synapse array router, the synapse array router coupled to the synapse outputs in the synapse array; a neuron array, including a plurality of neurons, each of the plurality of neurons including a neuron input and a neuron output; wherein wherein each synapse array router includes a first logic to route one or more of the synapse outputs to one or more of the neuron inputs. 9. The reconfigurable neuromorphic processor logic unit of claim 8 wherein a first synapse array router includes a second logic to route a synapse output to a neuron input of a neuron in a different corelet. 10. The reconfigurable neuromorphic processor logic unit of claim 8 wherein each synapse further includes a synapse memory to store a synapse destination and a synapse weight. 11. The reconfigurable neuromorphic processor logic unit of claim 10 wherein a first synapse array router includes: a second logic to read at least one synapse memory; a third logic identify a synapse destination; a fourth logic to identify a synapse weight; and a fifth logic to transmit a packet including the synapse weight and the synapse destination to a neuron group router, based on a routing algorithm. 12. The reconfigurable neuromorphic processor logic unit of claim 11, wherein the neuron group router includes: a sixth logic to receive the packet; a seventh logic to identify the synapse destination; a eighth logic to identify the synapse weight; and a ninth logic to transmit the synapse weight to at least one of the neuron inputs. 13. The reconfigurable neuromorphic processor logic unit of claim 8, wherein in one of the corelets the number of synapses to be routed to one of the neuron inputs is greater than the number of synapses in the corelet. 14. The reconfigurable neuromorphic processor logic unit of claim 8, further comprising a processor including a second logic to write initial synapse destinations and initial synapse weights into the synapse memory of each of the plurality of synapses in a first corelet, wherein at least one of the synapse destinations is to a neuron array in a second corelet. 15. A method, comprising, in a reconfigurable neuromorphic processor: receiving inputs from a plurality of synapses at a first neuron of a neuron array of a corelet; applying a transfer function to the inputs; generating a neuron output to a synapse based on a determination that the transfer function has exceeded a threshold; based on receiving the neuron output, reading a synapse weight and a synapse destination from a synapse memory; and transmitting the synapse weight to the synapse destination through one of a plurality of routing channels in a first synapse router. 16. The method of claim 15, further comprising: receiving, with a neuron group router, the synapse weight and the synapse destination; transmitting the synapse weight to an input of a second neuron identified in the synapse destination. 17. The method of claim 15, wherein the synapse destination is a second neuron. 18. The method of claim 17, wherein the second neuron is in a different corelet from the synapse. 19. The method of claim 15, wherein transmitting the synapse weight to the synapse destination through one of a plurality of routing channels in a synapse router includes: creating a packet containing the synapse weight and the synapse destination; and transmitting the packet to a second synapse router. 20. The method of claim 15, wherein a second neuron receives inputs from a number of synapses greater than the number of synapses in one of the corelets.