Hardware-Conscious Optimization of the Quantum Toffoli Gate
While quantum computing holds great potential in combinatorial optimization,
electronic structure calculation, and number theory, the current era of quantum
computing is limited by noisy hardware. Many quantum compilation approaches can
mitigate the effects of imperfect hardware by optimizing quantum circuits for
objectives such as critical path length. Few approaches consider quantum
circuits in terms of the set of vendor-calibrated operations (i.e., native
gates) available on target hardware. This manuscript expands the analytical and
numerical approaches for optimizing quantum circuits at this abstraction level.
We present a procedure for combining the strengths of analytical native
gate-level optimization with numerical optimization. Although we focus on
optimizing Toffoli gates on the IBMQ native gate set, the methods presented are
generalizable to any gate and superconducting qubit architecture. Our optimized
Toffoli gate implementation demonstrates an $18\%$ reduction in infidelity
compared with the canonical implementation as benchmarked on IBM Jakarta with
quantum process tomography. Assuming the inclusion of multi-qubit
cross-resonance (MCR) gates in the IBMQ native gate set, we produce Toffoli
implementations with only six multi-qubit gates, a $25\%$ reduction from the
canonical eight multi-qubit implementations for linearly connected qubits.
Max Aksel Bowman Pranav Gokhale Jeffrey Larson Ji Liu Martin Suchara