Wide Quantum Circuit Optimization with Topology Aware Synthesis
Unitary synthesis is an optimization technique that can achieve optimal
multi-qubit gate counts while mapping quantum circuits to restrictive qubit
topologies. Because synthesis algorithms are limited in scalability by their
exponentially growing run time and memory requirements, application to circuits
wider than 5 qubits requires divide-and-conquer partitioning of circuits into
smaller components. In this work, we will explore methods to reduce the depth
(program run time) and multi-qubit gate instruction count of wide (16-100
qubit) mapped quantum circuits optimized with synthesis. Reducing circuit depth
and gate count directly impacts program performance and the likelihood of
successful execution for quantum circuits on parallel quantum machines.
  We present TopAS, a topology aware synthesis tool built with the
\emph{BQSKit} framework that preconditions quantum circuits before mapping.
Partitioned subcircuits are optimized and fitted to sparse qubit subtopologies
in a way that balances the often opposing demands of synthesis and mapping
algorithms. This technique can be used to reduce the depth and gate count of
wide quantum circuits mapped to the sparse qubit topologies of Google and IBM.
Compared to large scale synthesis algorithms which focus on optimizing quantum
circuits after mapping, TopAS is able to reduce depth by an average of 35.2%
and CNOT gate count an average of 11.5% when targeting a 2D mesh topology. When
compared with traditional quantum compilers using peephole optimization and
mapping algorithms from the Qiskit or $t|ket\rangle$ toolkits, our approach is
able to provide significant improvements in performance, reducing CNOT counts
by 30.3% and depth by 38.2% on average.
Mathias Weiden Justin Kalloor John Kubiatowicz Ed Younis Costin Iancu