Learning to rank quantum circuits for hardware-optimized performance
  enhancement
We introduce and experimentally test a machine-learning-based method for
ranking logically equivalent quantum circuits based on expected performance
estimates derived from a training procedure conducted on real hardware. We
apply our method to the problem of layout selection, in which abstracted qubits
are assigned to physical qubits on a given device. Circuit measurements
performed on IBM hardware indicate that the maximum and median fidelities of
logically equivalent layouts can differ by an order of magnitude. We introduce
a circuit score used for ranking that is parameterized in terms of a
physics-based, phenomenological error model whose parameters are fit by
training a ranking-loss function over a measured dataset. The dataset consists
of quantum circuits exhibiting a diversity of structures and executed on IBM
hardware, allowing the model to incorporate the contextual nature of real
device noise and errors without the need to perform an exponentially costly
tomographic protocol. We perform model training and execution on the 16-qubit
ibmq_guadalupe device and compare our method to two common approaches: random
layout selection and a publicly available baseline called Mapomatic. Our model
consistently outperforms both approaches, predicting layouts that exhibit lower
noise and higher performance. In particular, we find that our best model leads
to a $1.8\times$ reduction in selection error when compared to the baseline
approach and a $3.2\times$ reduction when compared to random selection. Beyond
delivering a new form of predictive quantum characterization, verification, and
validation, our results reveal the specific way in which context-dependent and
coherent gate errors appear to dominate the divergence from performance
estimates extrapolated from simple proxy measures.
Gavin S. Hartnett Aaron Barbosa Pranav S. Mundada Michael Hush Michael J. Biercuk Yuval Baum