Quantum Fourier Transformation Circuits Compilation
In this research paper, our primary focus revolves around the domain-specific
hardware mapping strategy tailored for Quantum Fourier Transformation (QFT)
circuits. While previous approaches have heavily relied on SAT solvers or
heuristic methods to generate hardware-compatible QFT circuits by inserting
SWAP gates to realign logical qubits with physical qubits at various stages,
they encountered significant challenges. These challenges include extended
compilation times due to the expansive search space for SAT solvers and
suboptimal outcomes in terms of the number of cycles required to execute all
gate operations efficiently. In our study, we adopt a novel approach that
combines technical intuition, often referred to as "educated guesses," and
sophisticated program synthesis tools. Our objective is to uncover QFT mapping
solutions that leverage concepts such as affine loops and modular functions.
The groundbreaking outcome of our research is the introduction of the first set
of linear-depth transformed QFT circuits designed for Google Sycamore, IBM
heavy-hex, and the conventional 2-dimensional (2D) grid configurations,
accommodating an arbitrary number of qubits denoted as 'N'. Additionally, we
have conducted comprehensive analyses to verify the correctness of these
solutions and to develop strategies for handling potential faults within them.
Yuwei Jin Xiangyu Gao Minghao Guo Henry Chen Fei Hua Chi Zhang Eddy Z. Zhang