A Hardware-Aware Heuristic for the Qubit Mapping Problem in the NISQ Era
Due to several physical limitations in the realisation of quantum hardware,
today's quantum computers are qualified as Noisy Intermediate-Scale Quantum
(NISQ) hardware. NISQ hardware is characterized by a small number of qubits (50
to a few hundred) and noisy operations. Moreover, current realisations of
superconducting quantum chips do not have the ideal all-to-all connectivity
between qubits but rather at most a nearest-neighbour connectivity. All these
hardware restrictions add supplementary low-level requirements. They need to be
addressed before submitting the quantum circuit to an actual chip. Satisfying
these requirements is a tedious task for the programmer. Instead, the task of
adapting the quantum circuit to a given hardware is left to the compiler. In
this paper, we propose a Hardware-Aware mapping transition algorithm (HA) that
takes the calibration data into account with the aim to improve the overall
fidelity of the circuit. Evaluation results on IBM quantum hardware show that
our HA approach can outperform the state of the art both in terms of the number
of additional gates and circuit fidelity.
Siyuan Niu Adrien Suau Gabriel Staffelbach Aida Todri-Sanial