user28260: I am under the impression that the origin of RAM on a Cortex M is 0x20000000.  However, in the linker file for it, the ORIGIN of RAM is set to 0x1FFFF800.  Is that an error, or is there a reason for the discrepancy?

user4143: The Cortex M does not "have RAM at 0x2000000". The Cortex M is just a CPU. It is down to the chip manufacturer where they choose to place RAM in the memory map.
In the case of the MKL26Z64VFT4 used on the Teensy LC:

The on-chip SRAM is a single contiguous block split into two ranges: 1/4 is allocated to SRAM_L, and 3/4 is allocated to SRAM_U. Regardless of the block size, the SRAM is implemented such that:

SRAM_L is anchored to 0x1FFF_FFFF and occupies the space before this ending address.
SRAM_U is anchored to 0x2000_0000 and occupies the space after this beginning address.

Valid address ranges for SRAM_L and SRAM_U are then defined as:

SRAM_L = [0x2000_0000–(SRAM_size/4)] to 0x1FFF_FFFF
SRAM_U = 0x2000_0000 to [0x2000_0000+(SRAM_size*(3/4))-1]


Since there is 8kB of SRAM, 2kB is below 0x2000000 and 6kB is above 0x20000000. 2kB is 0x800. 0x2000000 - 0x800 = 0x1FFFF800.

28260: <p>I am under the impression that the origin of RAM on a Cortex M is 0x20000000.  However, in the linker file for it, the ORIGIN of RAM is set to 0x1FFFF800.  Is that an error, or is there a reason for the discrepancy?</p>
 4143: <p>The Cortex M does not "have RAM at 0x2000000". The Cortex M is just a CPU. It is down to the chip manufacturer where they choose to place RAM in the memory map.</p>

<p>In the case of the <a href="https://www.pjrc.com/teensy/KL26P121M48SF4RM.pdf" rel="nofollow noreferrer">MKL26Z64VFT4</a> used on the Teensy LC:</p>

<blockquote>
  <p>The on-chip SRAM is a single contiguous block split into two ranges: 1/4 is allocated to SRAM_L, and 3/4 is allocated to SRAM_U. Regardless of the block size, the SRAM is implemented such that:</p>
  
  <ul>
  <li>SRAM_L is anchored to 0x1FFF_FFFF and occupies the space before this ending address.</li>
  <li>SRAM_U is anchored to 0x2000_0000 and occupies the space after this beginning address.</li>
  </ul>
  
  <p>Valid address ranges for SRAM_L and SRAM_U are then defined as:</p>
  
  <ul>
  <li>SRAM_L = [0x2000_0000–(SRAM_size/4)] to 0x1FFF_FFFF</li>
  <li>SRAM_U = 0x2000_0000 to [0x2000_0000+(SRAM_size*(3/4))-1]</li>
  </ul>
</blockquote>

<p>Since there is 8kB of SRAM, 2kB is below 0x2000000 and 6kB is above 0x20000000. 2kB is 0x800. 0x2000000 - 0x800 = 0x1FFFF800.</p>
