user77985: I have an i2c device that i would like to rreverse engineer. Using the oringal master of the device here is a snapshot from the logical analyzer

I would like to replace the orginal master of the device with an arduino, the device has an interrupt pin that when detected it will do the trasaction above.
So far what i have figuerd out is the address is 0x53 (the first byte). I have also figured out by interactive with the device that the second,third, and last byte are data from the slave device.
How do i write an arduino code to simulate this transaction? Here is the code i have written and the response i got is not quite the same
#include <Wire.h>

void setup() {
  Wire.begin();        // join i2c bus (address optional for master)
  Wire. setClock(100000)
  Serial.begin(9600);  // start serial for output
}

void loop() {
  Wire.requestFrom(0x53, 6);    // request 6 bytes from slave device #8

  while (Wire.available()) { // slave may send less than requested
    char c = Wire.read(); // receive a byte as character
    Serial.print(c);         // print the character
  }

  delay(500);
}



user68310: Customised Protocol
As has been mentioned in the comments, it may be that the controller and target are communicating using a customised protocol for which you will need to modify the Wire library and/or the TWI library.
Modifying the TWI library is not easy because it uses a very convoluted mixture of ISR code and non-ISR polling code.
I've re-written the TWI library so that you can use standard burst-read and burst-write protocols in either ISR mode or polling mode, or build your own protocol using building-block functions. It uses the watchdog timer to detect timeouts when the bus freezes due to an error.
Terminology
The terminology of my TWI library conforms to NXP Semiconductors recently released v7 of the I2C-bus specification which has:

Updated the terms "master/slave" to "controller/target" throughout to align with MIPI I3C specification and NXP's Inclusive Language Project



77985: <p>I have an i2c device that i would like to rreverse engineer. Using the oringal master of the device here is a snapshot from the logical analyzer</p>
<p><a href="https://i.stack.imgur.com/fsPhd.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/fsPhd.png" alt="enter image description here" /></a></p>
<p>I would like to replace the orginal master of the device with an arduino, the device has an interrupt pin that when detected it will do the trasaction above.</p>
<p>So far what i have figuerd out is the address is 0x53 (the first byte). I have also figured out by interactive with the device that the second,third, and last byte are data from the slave device.</p>
<p>How do i write an arduino code to simulate this transaction? Here is the code i have written and the response i got is not quite the same</p>
<pre><code>#include &lt;Wire.h&gt;

void setup() {
  Wire.begin();        // join i2c bus (address optional for master)
  Wire. setClock(100000)
  Serial.begin(9600);  // start serial for output
}

void loop() {
  Wire.requestFrom(0x53, 6);    // request 6 bytes from slave device #8

  while (Wire.available()) { // slave may send less than requested
    char c = Wire.read(); // receive a byte as character
    Serial.print(c);         // print the character
  }

  delay(500);
}
</code></pre>
<p><a href="https://i.stack.imgur.com/n4IiS.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/n4IiS.png" alt="enter image description here" /></a></p>
 68310: <h1>Customised Protocol</h1>
<p>As has been mentioned in the comments, it may be that the controller and target are communicating using a customised protocol for which you will need to modify the <code>Wire</code> library and/or the <code>TWI</code> library.</p>
<p>Modifying the <code>TWI</code> library is not easy because it uses a very convoluted mixture of ISR code and non-ISR polling code.</p>
<p>I've <a href="https://wokwi.com/arduino/projects/306825661000974912" rel="nofollow noreferrer">re-written the TWI library</a> so that you can use standard burst-read and burst-write protocols in either ISR mode or polling mode, or <strong>build your own protocol using building-block functions</strong>. It uses the watchdog timer to detect timeouts when the bus freezes due to an error.</p>
<h1>Terminology</h1>
<p>The terminology of my TWI library conforms to NXP Semiconductors recently released <a href="https://www.nxp.com/webapp/Download?colCode=UM10204" rel="nofollow noreferrer">v7 of the I2C-bus specification</a> which has:</p>
<blockquote>
<p>Updated the terms &quot;master/slave&quot; to &quot;controller/target&quot; throughout to align with MIPI I3C specification and NXP's Inclusive Language Project</p>
</blockquote>
<p><a href="https://i.stack.imgur.com/MWeQh.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/MWeQh.png" alt="UM10204, I2C-bus specification and user manual, v7, 2021-10-01, Table 1, Revision history" /></a></p>
