/// Lower an instruction input to a reg or reg/shift, or reg/extend operand.
///
/// The `narrow_mode` flag indicates whether the consumer of this value needs
/// the high bits clear. For many operations, such as an add/sub/mul or any
/// bitwise logical operation, the low-bit results depend only on the low-bit
/// inputs, so e.g. we can do an 8 bit add on 32 bit registers where the 8-bit
/// value is stored in the low 8 bits of the register and the high 24 bits are
/// undefined. If the op truly needs the high N bits clear (such as for a
/// divide or a right-shift or a compare-to-zero), `narrow_mode` should be
/// set to `ZeroExtend` or `SignExtend` as appropriate, and the resulting
/// register will be provided the extended value.
Lower an instruction input to a reg or reg/shift, or reg/extend operand.
The `narrow_mode` flag indicates whether the consumer of this value needs
the high bits clear. For many operations, such as an add/sub/mul or any
bitwise logical operation, the low-bit results depend only on the low-bit
inputs, so e.g. we can do an 8 bit add on 32 bit registers where the 8-bit
value is stored in the low 8 bits of the register and the high 24 bits are
undefined.
Lower an instruction input to a reg or reg / shift or reg / extend operand . The ` narrow_mode ` flag indicates whether the consumer of this value needs the high bits clear . For many operations such as an add / sub / mul or any bitwise logical operation the low - bit results depend only on the low - bit inputs so e . g . we can do an 8 bit add on 32 bit registers where the 8 - bit value is stored in the low 8 bits of the register and the high 24 bits are undefined .
fn put_input_in_rs<C: LowerCtx<I = Inst>>(
    ctx: &mut C,
    input: InsnInput,
    narrow_mode: NarrowValueMode,
) -> ResultRS {
    let inputs = ctx.get_input(input.insn, input.input);
    if let Some((insn, 0)) = inputs.inst {
        let op = ctx.data(insn).opcode();
        if op == Opcode::Ishl {
            let shiftee = InsnInput { insn, input: 0 };
            let shift_amt = InsnInput { insn, input: 1 };
            // Can we get the shift amount as an immediate?
            if let Some(shiftimm) = input_to_shiftimm(ctx, shift_amt) {
                let shiftee_bits = ty_bits(ctx.input_ty(insn, 0));
                if shiftee_bits <= std::u8::MAX as usize {
                    let shiftimm = shiftimm.mask(shiftee_bits as u8);
                    let reg = put_input_in_reg(ctx, shiftee, narrow_mode);
                    return ResultRS::RegShift(reg, ShiftOpAndAmt::new(ShiftOp::LSL, shiftimm));
                }
            }
        }
    }
    ResultRS::Reg(put_input_in_reg(ctx, input, narrow_mode))
}
fn put_input_in_rs < C : LowerCtx < I = Inst > > ( ctx : & mut C , input : InsnInput , narrow_mode : NarrowValueMode , ) -> ResultRS { let inputs = ctx . get_input ( input . insn , input . input ) ; if let Some ( ( insn , 0 ) ) = inputs . inst { let op = ctx . data ( insn ) . opcode ( ) ; if op == Opcode :: Ishl { let shiftee = InsnInput { insn , input : 0 } ; let shift_amt = InsnInput { insn , input : 1 } ; // Can we get the shift amount as an immediate? if let Some ( shiftimm ) = input_to_shiftimm ( ctx , shift_amt ) { let shiftee_bits = ty_bits ( ctx . input_ty ( insn , 0 ) ) ; if shiftee_bits <= std :: u8 :: MAX as usize { let shiftimm = shiftimm . mask ( shiftee_bits as u8 ) ; let reg = put_input_in_reg ( ctx , shiftee , narrow_mode ) ; return ResultRS :: RegShift ( reg , ShiftOpAndAmt :: new ( ShiftOp :: LSL , shiftimm ) ) ; } } } } ResultRS :: Reg ( put_input_in_reg ( ctx , input , narrow_mode ) ) }
Lower an instruction input to a reg or reg/shift, or reg/extend operand.
Lower an instruction input to a reg or reg / shift or reg / extend operand .
ctx
&mut C
input
InsnInput
narrow_mode
NarrowValueMode