/// Receive arbitrary data
// make sure to set tmod to tmod::RECV
Receive arbitrary data
make sure to set tmod to tmod::RECV
Receive arbitrary data make sure to set tmod to tmod :: RECV
fn recv_data<X: TruncU32>(&self, chip_select: u32, rx: &mut [X]) {
        if rx.len() == 0 {
            return;
        }
        unsafe {
            self.spi.ctrlr1.write(|w| w.bits((rx.len() - 1).try_into().unwrap()));
            self.spi.ssienr.write(|w| w.bits(0x01));
            self.spi.dr[0].write(|w| w.bits(0xffffffff));
            self.spi.ser.write(|w| w.bits(1 << chip_select));
            let mut fifo_len = 0;
            for val in rx.iter_mut() {
                while fifo_len == 0 {
                    fifo_len = self.spi.rxflr.read().bits();
                }
                *val = X::trunc(self.spi.dr[0].read().bits());
                fifo_len -= 1;
            }
            self.spi.ser.write(|w| w.bits(0x00));
            self.spi.ssienr.write(|w| w.bits(0x00));
        }
    }
fn recv_data < X : TruncU32 > ( & self , chip_select : u32 , rx : & mut [ X ] ) { if rx . len ( ) == 0 { return ; } unsafe { self . spi . ctrlr1 . write ( | w | w . bits ( ( rx . len ( ) - 1 ) . try_into ( ) . unwrap ( ) ) ) ; self . spi . ssienr . write ( | w | w . bits ( 0x01 ) ) ; self . spi . dr [ 0 ] . write ( | w | w . bits ( 0xffffffff ) ) ; self . spi . ser . write ( | w | w . bits ( 1 << chip_select ) ) ; let mut fifo_len = 0 ; for val in rx . iter_mut ( ) { while fifo_len == 0 { fifo_len = self . spi . rxflr . read ( ) . bits ( ) ; } * val = X :: trunc ( self . spi . dr [ 0 ] . read ( ) . bits ( ) ) ; fifo_len -= 1 ; } self . spi . ser . write ( | w | w . bits ( 0x00 ) ) ; self . spi . ssienr . write ( | w | w . bits ( 0x00 ) ) ; } }
Receive arbitrary data
make sure to set tmod to tmod::RECV
Receive arbitrary data make sure to set tmod to tmod :: RECV
&self
chip_select
u32
rx
&mut [X]