/// Lower an instruction input to a reg or reg/shift, or reg/extend operand.
/// This does not actually codegen the source instruction; it just uses the
/// vreg into which the source instruction will generate its value.
///
/// The `narrow_mode` flag indicates whether the consumer of this value needs
/// the high bits clear. For many operations, such as an add/sub/mul or any
/// bitwise logical operation, the low-bit results depend only on the low-bit
/// inputs, so e.g. we can do an 8 bit add on 32 bit registers where the 8-bit
/// value is stored in the low 8 bits of the register and the high 24 bits are
/// undefined. If the op truly needs the high N bits clear (such as for a
/// divide or a right-shift or a compare-to-zero), `narrow_mode` should be
/// set to `ZeroExtend` or `SignExtend` as appropriate, and the resulting
/// register will be provided the extended value.
Lower an instruction input to a reg or reg/shift, or reg/extend operand.
This does not actually codegen the source instruction; it just uses the
vreg into which the source instruction will generate its value.

The `narrow_mode` flag indicates whether the consumer of this value needs
the high bits clear. For many operations, such as an add/sub/mul or any
bitwise logical operation, the low-bit results depend only on the low-bit
inputs, so e.g. we can do an 8 bit add on 32 bit registers where the 8-bit
value is stored in the low 8 bits of the register and the high 24 bits are
undefined.
Lower an instruction input to a reg or reg / shift or reg / extend operand . This does not actually codegen the source instruction ; it just uses the vreg into which the source instruction will generate its value . The ` narrow_mode ` flag indicates whether the consumer of this value needs the high bits clear . For many operations such as an add / sub / mul or any bitwise logical operation the low - bit results depend only on the low - bit inputs so e . g . we can do an 8 bit add on 32 bit registers where the 8 - bit value is stored in the low 8 bits of the register and the high 24 bits are undefined .
fn input_to_rs<C: LowerCtx<Inst>>(
    ctx: &mut C,
    input: InsnInput,
    narrow_mode: NarrowValueMode,
) -> ResultRS {
    if let InsnInputSource::Output(out) = input_source(ctx, input) {
        let insn = out.insn;
        assert!(out.output <= ctx.num_outputs(insn));
        let op = ctx.data(insn).opcode();
        if op == Opcode::Ishl {
            let shiftee = get_input(ctx, out, 0);
            let shift_amt = get_input(ctx, out, 1);
            // Can we get the shift amount as an immediate?
            if let Some(shift_amt_out) = input_source(ctx, shift_amt).as_output() {
                if let Some(shiftimm) = output_to_shiftimm(ctx, shift_amt_out) {
                    let reg = input_to_reg(ctx, shiftee, narrow_mode);
                    ctx.merged(insn);
                    ctx.merged(shift_amt_out.insn);
                    return ResultRS::RegShift(reg, ShiftOpAndAmt::new(ShiftOp::LSL, shiftimm));
                }
            }
        }
    }
    ResultRS::Reg(input_to_reg(ctx, input, narrow_mode))
}
fn input_to_rs < C : LowerCtx < Inst > > ( ctx : & mut C , input : InsnInput , narrow_mode : NarrowValueMode , ) -> ResultRS { if let InsnInputSource :: Output ( out ) = input_source ( ctx , input ) { let insn = out . insn ; assert ! ( out output ctx num_outputs ( insn ) ) ; let op = ctx . data ( insn ) . opcode ( ) ; if op == Opcode :: Ishl { let shiftee = get_input ( ctx , out , 0 ) ; let shift_amt = get_input ( ctx , out , 1 ) ; // Can we get the shift amount as an immediate? if let Some ( shift_amt_out ) = input_source ( ctx , shift_amt ) . as_output ( ) { if let Some ( shiftimm ) = output_to_shiftimm ( ctx , shift_amt_out ) { let reg = input_to_reg ( ctx , shiftee , narrow_mode ) ; ctx . merged ( insn ) ; ctx . merged ( shift_amt_out . insn ) ; return ResultRS :: RegShift ( reg , ShiftOpAndAmt :: new ( ShiftOp :: LSL , shiftimm ) ) ; } } } } ResultRS :: Reg ( input_to_reg ( ctx , input , narrow_mode ) ) }
Lower an instruction input to a reg or reg/shift, or reg/extend operand.
Lower an instruction input to a reg or reg / shift or reg / extend operand .
ctx
&mut C
input
InsnInput
narrow_mode
NarrowValueMode