/// Description of the cache (from Intel Manual)
Description of the cache (from Intel Manual)
Description of the cache ( from Intel Manual )
pub fn desc(&self) -> &'static str {
        match self.num {
            0x00 => "Null descriptor, this byte contains no information",
            0x01 => "Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries",
            0x02 => "Instruction TLB: 4 MByte pages, fully associative, 2 entries",
            0x03 => "Data TLB: 4 KByte pages, 4-way set associative, 64 entries",
            0x04 => "Data TLB: 4 MByte pages, 4-way set associative, 8 entries",
            0x05 => "Data TLB1: 4 MByte pages, 4-way set associative, 32 entries",
            0x06 => "1st-level instruction cache: 8 KBytes, 4-way set associative, 32 byte line size",
            0x08 => "1st-level instruction cache: 16 KBytes, 4-way set associative, 32 byte line size",
            0x09 => "1st-level instruction cache: 32KBytes, 4-way set associative, 64 byte line size",
            0x0A => "1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size",
            0x0B => "Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries",
            0x0C => "1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size",
            0x0D => "1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size",
            0x0E => "1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size",
            0x1D => "2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size",
            0x21 => "2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size",
            0x22 => "3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size, 2 lines per sector",
            0x23 => "3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector",
            0x24 => "2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size",
            0x25 => "3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector",
            0x29 => "3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size, 2 lines per sector",
            0x2C => "1st-level data cache: 32 KBytes, 8-way set associative, 64 byte line size",
            0x30 => "1st-level instruction cache: 32 KBytes, 8-way set associative, 64 byte line size",
            0x40 => "No 2nd-level cache or, if processor contains a valid 2nd-level cache, no 3rd-level cache",
            0x41 => "2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size",
            0x42 => "2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size",
            0x43 => "2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size",
            0x44 => "2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size",
            0x45 => "2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size",
            0x46 => "3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size",
            0x47 => "3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size",
            0x48 => "2nd-level cache: 3MByte, 12-way set associative, 64 byte line size",
            0x49 => "3rd-level cache: 4MB, 16-way set associative, 64-byte line size (Intel Xeon processor MP, Family 0FH, Model 06H); 2nd-level cache: 4 MByte, 16-way set ssociative, 64 byte line size",
            0x4A => "3rd-level cache: 6MByte, 12-way set associative, 64 byte line size",
            0x4B => "3rd-level cache: 8MByte, 16-way set associative, 64 byte line size",
            0x4C => "3rd-level cache: 12MByte, 12-way set associative, 64 byte line size",
            0x4D => "3rd-level cache: 16MByte, 16-way set associative, 64 byte line size",
            0x4E => "2nd-level cache: 6MByte, 24-way set associative, 64 byte line size",
            0x4F => "Instruction TLB: 4 KByte pages, 32 entries",
            0x50 => "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries",
            0x51 => "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries",
            0x52 => "Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries",
            0x55 => "Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries",
            0x56 => "Data TLB0: 4 MByte pages, 4-way set associative, 16 entries",
            0x57 => "Data TLB0: 4 KByte pages, 4-way associative, 16 entries",
            0x59 => "Data TLB0: 4 KByte pages, fully associative, 16 entries",
            0x5A => "Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries",
            0x5B => "Data TLB: 4 KByte and 4 MByte pages, 64 entries",
            0x5C => "Data TLB: 4 KByte and 4 MByte pages,128 entries",
            0x5D => "Data TLB: 4 KByte and 4 MByte pages,256 entries",
            0x60 => "1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size",
            0x61 => "Instruction TLB: 4 KByte pages, fully associative, 48 entries",
            0x63 => "Data TLB: 2 MByte or 4 MByte pages, 4-way set associative, 32 entries and a separate array with 1 GByte pages, 4-way set associative, 4 entries",
            0x64 => "Data TLB: 4 KByte pages, 4-way set associative, 512 entries",
            0x66 => "1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size",
            0x67 => "1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size",
            0x68 => "1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size",
            0x6A => "uTLB: 4 KByte pages, 8-way set associative, 64 entries",
            0x6B => "DTLB: 4 KByte pages, 8-way set associative, 256 entries",
            0x6C => "DTLB: 2M/4M pages, 8-way set associative, 128 entries",
            0x6D => "DTLB: 1 GByte pages, fully associative, 16 entries",
            0x70 => "Trace cache: 12 K-μop, 8-way set associative",
            0x71 => "Trace cache: 16 K-μop, 8-way set associative",
            0x72 => "Trace cache: 32 K-μop, 8-way set associative",
            0x76 => "Instruction TLB: 2M/4M pages, fully associative, 8 entries",
            0x78 => "2nd-level cache: 1 MByte, 4-way set associative, 64byte line size",
            0x79 => "2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size, 2 lines per sector",
            0x7A => "2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size, 2 lines per sector",
            0x7B => "2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size, 2 lines per sector",
            0x7C => "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size, 2 lines per sector",
            0x7D => "2nd-level cache: 2 MByte, 8-way set associative, 64byte line size",
            0x7F => "2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size",
            0x80 => "2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size",
            0x82 => "2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size",
            0x83 => "2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size",
            0x84 => "2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size",
            0x85 => "2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size",
            0x86 => "2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size",
            0x87 => "2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size",
            0xA0 => "DTLB: 4k pages, fully associative, 32 entries",
            0xB0 => "Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries",
            0xB1 => "Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries",
            0xB2 => "Instruction TLB: 4KByte pages, 4-way set associative, 64 entries",
            0xB3 => "Data TLB: 4 KByte pages, 4-way set associative, 128 entries",
            0xB4 => "Data TLB1: 4 KByte pages, 4-way associative, 256 entries",
            0xB5 => "Instruction TLB: 4KByte pages, 8-way set associative, 64 entries",
            0xB6 => "Instruction TLB: 4KByte pages, 8-way set associative, 128 entries",
            0xBA => "Data TLB1: 4 KByte pages, 4-way associative, 64 entries",
            0xC0 => "Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries",
            0xC1 => "Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative, 1024 entries",
            0xC2 => "DTLB: 2 MByte/$MByte pages, 4-way associative, 16 entries",
            0xC3 => "Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative, 1536 entries. Also 1GBbyte pages, 4-way, 16 entries.",
            0xC4 => "DTLB: 2M/4M Byte pages, 4-way associative, 32 entries",
            0xCA => "Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries",
            0xD0 => "3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size",
            0xD1 => "3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size",
            0xD2 => "3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size",
            0xD6 => "3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size",
            0xD7 => "3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size",
            0xD8 => "3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size",
            0xDC => "3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size",
            0xDD => "3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size",
            0xDE => "3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size",
            0xE2 => "3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size",
            0xE3 => "3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size",
            0xE4 => "3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size",
            0xEA => "3rd-level cache: 12MByte, 24-way set associative, 64 byte line size",
            0xEB => "3rd-level cache: 18MByte, 24-way set associative, 64 byte line size",
            0xEC => "3rd-level cache: 24MByte, 24-way set associative, 64 byte line size",
            0xF0 => "64-Byte prefetching",
            0xF1 => "128-Byte prefetching",
            0xFE => "CPUID leaf 2 does not report TLB descriptor information; use CPUID leaf 18H to query TLB and other address translation parameters.",
            0xFF => "CPUID leaf 2 does not report cache descriptor information, use CPUID leaf 4 to query cache parameters",
            _ => "Unknown cache type!"
        }
    }
pub fn desc ( & self ) -> & ' static str { match self . num { 0x00 => " " , 0x01 => " " , 0x02 => " " , 0x03 => " " , 0x04 => " " , 0x05 => " " , 0x06 => " " , 0x08 => " " , 0x09 => " " , 0x0A => " " , 0x0B => " " , 0x0C => " " , 0x0D => " " , 0x0E => " " , 0x1D => " " , 0x21 => " " , 0x22 => " " , 0x23 => " " , 0x24 => " " , 0x25 => " " , 0x29 => " " , 0x2C => " " , 0x30 => " " , 0x40 => " " , 0x41 => " " , 0x42 => " " , 0x43 => " " , 0x44 => " " , 0x45 => " " , 0x46 => " " , 0x47 => " " , 0x48 => " " , 0x49 => " " , 0x4A => " " , 0x4B => " " , 0x4C => " " , 0x4D => " " , 0x4E => " " , 0x4F => " " , 0x50 => " " , 0x51 => " " , 0x52 => " " , 0x55 => " " , 0x56 => " " , 0x57 => " " , 0x59 => " " , 0x5A => " " , 0x5B => " " , 0x5C => " " , 0x5D => " " , 0x60 => " " , 0x61 => " " , 0x63 => " " , 0x64 => " " , 0x66 => " " , 0x67 => " " , 0x68 => " " , 0x6A => " " , 0x6B => " " , 0x6C => " " , 0x6D => " " , 0x70 => " , 0x71 => " , 0x72 => " , 0x76 => " " , 0x78 => " " , 0x79 => " " , 0x7A => " " , 0x7B => " " , 0x7C => " " , 0x7D => " " , 0x7F => " " , 0x80 => " " , 0x82 => " " , 0x83 => " " , 0x84 => " " , 0x85 => " " , 0x86 => " " , 0x87 => " " , 0xA0 => " " , 0xB0 => " " , 0xB1 => " " , 0xB2 => " " , 0xB3 => " " , 0xB4 => " " , 0xB5 => " " , 0xB6 => " " , 0xBA => " " , 0xC0 => " " , 0xC1 => " " , 0xC2 => " " , 0xC3 => " " , 0xC4 => " " , 0xCA => " " , 0xD0 => " " , 0xD1 => " " , 0xD2 => " " , 0xD6 => " " , 0xD7 => " " , 0xD8 => " " , 0xDC => " " , 0xDD => " " , 0xDE => " " , 0xE2 => " " , 0xE3 => " " , 0xE4 => " " , 0xEA => " " , 0xEB => " " , 0xEC => " " , 0xF0 => " " , 0xF1 => " " , 0xFE => " " , 0xFF => " " , _ => " " } }
Description of the cache (from Intel Manual)
Description of the cache ( from Intel Manual )
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