/// Gather a list of arguments from the port declarations in a function body.
Gather a list of arguments from the port declarations in a function body.
Gather a list of arguments from the port declarations in a function body .
fn gather_from_items<'a>(
    cx: &impl Context<'a>,
    node: &'a ast::SubroutineDecl<'a>,
    items: &'a [ast::SubroutineItem<'a>],
    next_rib: NodeId,
) -> Vec<FuncArg<'a>> {
    let mut args = vec![];
    let mut non_port = None;
    let mut non_port_reported = false;
    for item in items {
        // Only consider port declarations.
        let port = match item {
            ast::SubroutineItem::PortDecl(x) => x,
            ast::SubroutineItem::Stmt(x) => {
                non_port = Some(non_port.unwrap_or(x));
                continue;
            }
        };
        // Emit a warning if ports and statements are interleaved.
        if let Some(non_port) = non_port {
            if !non_port_reported {
                cx.emit(
                    DiagBuilder2::warning(format!("port after statement"))
                        .span(port.span())
                        .add_note("Port declaration appears after this statement:")
                        .span(non_port.span())
                        .add_note(
                            "This is accepted by moore, but is forbidden according to IEEE \
                             1800-2017 where all ports must appear before regular statements.",
                        ),
                );
                non_port_reported = true;
            }
        }
        // Determine the data type. If it is an implicit type, default to
        // `logic`.
        let ty: &_ = if port.ty.kind.data == ast::ImplicitType {
            let ty = cx.arena().alloc(ast::Type::new(
                port.ty.span(),
                ast::TypeData {
                    kind: ast::TypeKind::new(port.ty.span(), ast::LogicType),
                    sign: port.ty.sign,
                    dims: port.ty.dims.clone(),
                },
            ));
            ty.link_attach(port, port.order());
            cx.register_ast(ty);
            cx.map_ast_with_parent(AstNode::Type(ty), next_rib);
            ty
        } else {
            &port.ty
        };
        // Add an argument to the list for every declared port name.
        for name in &port.names {
            args.push(FuncArg {
                ast: port,
                func: node,
                span: port.span,
                name: Some(Spanned::new(name.name, name.span)),
                dir: port.dir,
                ty,
                var: port.var,
                unpacked_dims: &name.dims,
                default: name.init.as_ref(),
            });
        }
    }
    args
}
fn gather_from_items < ' a > ( cx : & impl Context < ' a > , node : & ' a ast :: SubroutineDecl < ' a > , items : & ' a [ ast :: SubroutineItem < ' a > ] , next_rib : NodeId , ) -> Vec < FuncArg < ' a > > { let mut args = vec ! [ ] ; let mut non_port = None ; let mut non_port_reported = false ; for item in items { // Only consider port declarations. let port = match item { ast :: SubroutineItem :: PortDecl ( x ) => x , ast :: SubroutineItem :: Stmt ( x ) => { non_port = Some ( non_port . unwrap_or ( x ) ) ; continue ; } } ; // Emit a warning if ports and statements are interleaved. if let Some ( non_port ) = non_port { if ! non_port_reported { cx . emit ( DiagBuilder2 :: warning ( format ! ( " " ) ) . span ( port . span ( ) ) . add_note ( " " ) . span ( non_port . span ( ) ) . add_note ( " \
 " , ) , ) ; non_port_reported = true ; } } // Determine the data type. If it is an implicit type, default to // `logic`. let ty : & _ = if port . ty . kind . data == ast :: ImplicitType { let ty = cx . arena ( ) . alloc ( ast :: Type :: new ( port . ty . span ( ) , ast :: TypeData { kind : ast :: TypeKind :: new ( port . ty . span ( ) , ast :: LogicType ) , sign : port . ty . sign , dims : port . ty . dims . clone ( ) , } , ) ) ; ty . link_attach ( port , port . order ( ) ) ; cx . register_ast ( ty ) ; cx . map_ast_with_parent ( AstNode :: Type ( ty ) , next_rib ) ; ty } else { & port . ty } ; // Add an argument to the list for every declared port name. for name in & port . names { args . push ( FuncArg { ast : port , func : node , span : port . span , name : Some ( Spanned :: new ( name . name , name . span ) ) , dir : port . dir , ty , var : port . var , unpacked_dims : & name . dims , default : name . init . as_ref ( ) , } ) ; } } args }
Gather a list of arguments from the port declarations in a function body.
Gather a list of arguments from the port declarations in a function body .
cx
&impl Context<'a>
node
&'a ast::SubroutineDecl<'a>
items
&'a [ast::SubroutineItem<'a>]
next_rib
NodeId