/*
  mvn/mvp can be interrupted by IRQ after every byte move (7 cycles), the simplest way
  to achieve it is treat mvn/mvp as recurrent instructions, not single one. We achieve
  it by settin stepPC to 0, that means that CPU doesn't skip to next command as long
  as accumulator is diffrent than 0xffff

  BTW: specification says that mvn/mvp use full C accumulator

*/
mvn/mvp can be interrupted by IRQ after every byte move (7 cycles), the simplest way
to achieve it is treat mvn/mvp as recurrent instructions, not single one. We achieve
it by settin stepPC to 0, that means that CPU doesn't skip to next command as long
as accumulator is diffrent than 0xffff

specification says that mvn/mvp use full C accumulator
/ * mvn / mvp can be interrupted by IRQ after every byte move ( 7 cycles ) the simplest way to achieve it is treat mvn / mvp as recurrent instructions not single one . We achieve it by settin stepPC to 0 that means that CPU doesn ' t skip to next command as long as accumulator is diffrent than 0xffff BTW : specification says that mvn / mvp use full C accumulator * /
func (cpu *CPU) op_mvn(info *stepInfo) {
	dst := cpu.nRead(cpu.RK, info.addr)
	src := cpu.nRead(cpu.RK, info.addr+1)
	cpu.RDBR = dst
	if cpu.X == 1 {
		cpu.nWrite(dst, uint16(cpu.RYl), cpu.nRead(src, uint16(cpu.RXl)))
		cpu.RYl++
		cpu.RXl++
	} else {
		cpu.nWrite(dst, cpu.RY, cpu.nRead(src, cpu.RX))
		cpu.RY++
		cpu.RX++
	}
	cpu.RA--
	cpu.RAl = uint8(cpu.RA &  0x00ff)
	cpu.RAh = uint8(cpu.RA >> 8)
	if cpu.RA != 0xffff {
		cpu.stepPC = 0
	}
}
func ( cpu * CPU ) op_mvn ( info * stepInfo ) { dst := cpu . nRead ( cpu . RK , info . addr ) src := cpu . nRead ( cpu . RK , info . addr + 1 ) cpu . RDBR = dst if cpu . X == 1 { cpu . nWrite ( dst , uint16 ( cpu . RYl ) , cpu . nRead ( src , uint16 ( cpu . RXl ) ) ) cpu . RYl ++ cpu . RXl ++ } else { cpu . nWrite ( dst , cpu . RY , cpu . nRead ( src , cpu . RX ) ) cpu . RY ++ cpu . RX ++ } cpu . RA -- cpu . RAl = uint8 ( cpu . RA & 0x00ff ) cpu . RAh = uint8 ( cpu . RA >> 8 ) if cpu . RA != 0xffff { cpu . stepPC = 0 } }
mvn/mvp can be interrupted by IRQ after every byte move (7 cycles), the simplest way
to achieve it is treat mvn/mvp as recurrent instructions, not single one.
mvn / mvp can be interrupted by IRQ after every byte move ( 7 cycles ) the simplest way to achieve it is treat mvn / mvp as recurrent instructions not single one .