// initArchState initializes architecture-specific state.
initArchState initializes architecture-specific state.
// initArchState initializes architecture - specific state .
func (c *vCPU) initArchState() error {
	var (
		reg     kvmOneReg
		data    uint64
		regGet  kvmOneReg
		dataGet uint64
	)
	reg.addr = uint64(reflect.ValueOf(&data).Pointer())
	regGet.addr = uint64(reflect.ValueOf(&dataGet).Pointer())
	vcpuInit.features[0] |= (1 << _KVM_ARM_VCPU_PSCI_0_2)
	if _, _, errno := unix.RawSyscall(
		unix.SYS_IOCTL,
		uintptr(c.fd),
		_KVM_ARM_VCPU_INIT,
		uintptr(unsafe.Pointer(&vcpuInit))); errno != 0 {
		panic(fmt.Sprintf("error setting KVM_ARM_VCPU_INIT failed: %v", errno))
	}
	data = _TCR_TXSZ_VA48 | _TCR_CACHE_FLAGS | _TCR_SHARED | _TCR_TG_FLAGS | _TCR_ASID16 | _TCR_IPS_40BITS
	reg.id = _KVM_ARM64_REGS_TCR_EL1
	if err := c.setOneRegister(&reg); err != nil {
		return err
	}
	data = _MT_EL1_INIT
	reg.id = _KVM_ARM64_REGS_MAIR_EL1
	if err := c.setOneRegister(&reg); err != nil {
		return err
	}
	data = c.machine.kernel.PageTables.TTBR0_EL1(false, 0)
	reg.id = _KVM_ARM64_REGS_TTBR0_EL1
	if err := c.setOneRegister(&reg); err != nil {
		return err
	}
	c.SetTtbr0Kvm(uintptr(data))
	data = c.machine.kernel.PageTables.TTBR1_EL1(false, 0)
	reg.id = _KVM_ARM64_REGS_TTBR1_EL1
	if err := c.setOneRegister(&reg); err != nil {
		return err
	}
	data = c.CPU.StackTop()
	reg.id = _KVM_ARM64_REGS_SP_EL1
	if err := c.setOneRegister(&reg); err != nil {
		return err
	}
	reg.id = _KVM_ARM64_REGS_PC
	data = uint64(reflect.ValueOf(ring0.Start).Pointer())
	if err := c.setOneRegister(&reg); err != nil {
		return err
	}
	reg.id = _KVM_ARM64_REGS_R8
	data = uint64(reflect.ValueOf(&c.CPU).Pointer())
	if err := c.setOneRegister(&reg); err != nil {
		return err
	}
	reg.id = _KVM_ARM64_REGS_VBAR_EL1
	fromLocation := reflect.ValueOf(ring0.Vectors).Pointer()
	offset := fromLocation & (1<<11 - 1)
	if offset != 0 {
		offset = 1<<11 - offset
	}
	toLocation := fromLocation + offset
	data = uint64(ring0.KernelStartAddress | toLocation)
	if err := c.setOneRegister(&reg); err != nil {
		return err
	}
	arm64HypercallMMIOBase = toLocation
	if hasGuestPCID {
		c.PCIDs = pagetables.NewPCIDs(fixedKernelPCID+1, poolPCIDs)
	}
	c.floatingPointState = fpu.NewState()
	return c.setSystemTime()
}
func ( c * vCPU ) initArchState ( ) error { var ( reg kvmOneReg data uint64 regGet kvmOneReg dataGet uint64 ) reg . addr = uint64 ( reflect . ValueOf ( & data ) . Pointer ( ) ) regGet . addr = uint64 ( reflect . ValueOf ( & dataGet ) . Pointer ( ) ) vcpuInit . features [ 0 ] |= ( 1 << _KVM_ARM_VCPU_PSCI_0_2 ) if _ , _ , errno := unix . RawSyscall ( unix . SYS_IOCTL , uintptr ( c . fd ) , _KVM_ARM_VCPU_INIT , uintptr ( unsafe . Pointer ( & vcpuInit ) ) ) ; errno != 0 { panic ( fmt . Sprintf ( " " , errno ) ) } data = _TCR_TXSZ_VA48 | _TCR_CACHE_FLAGS | _TCR_SHARED | _TCR_TG_FLAGS | _TCR_ASID16 | _TCR_IPS_40BITS reg . id = _KVM_ARM64_REGS_TCR_EL1 if err := c . setOneRegister ( & reg ) ; err != nil { return err } data = _MT_EL1_INIT reg . id = _KVM_ARM64_REGS_MAIR_EL1 if err := c . setOneRegister ( & reg ) ; err != nil { return err } data = c . machine . kernel . PageTables . TTBR0_EL1 ( false , 0 ) reg . id = _KVM_ARM64_REGS_TTBR0_EL1 if err := c . setOneRegister ( & reg ) ; err != nil { return err } c . SetTtbr0Kvm ( uintptr ( data ) ) data = c . machine . kernel . PageTables . TTBR1_EL1 ( false , 0 ) reg . id = _KVM_ARM64_REGS_TTBR1_EL1 if err := c . setOneRegister ( & reg ) ; err != nil { return err } data = c . CPU . StackTop ( ) reg . id = _KVM_ARM64_REGS_SP_EL1 if err := c . setOneRegister ( & reg ) ; err != nil { return err } reg . id = _KVM_ARM64_REGS_PC data = uint64 ( reflect . ValueOf ( ring0 . Start ) . Pointer ( ) ) if err := c . setOneRegister ( & reg ) ; err != nil { return err } reg . id = _KVM_ARM64_REGS_R8 data = uint64 ( reflect . ValueOf ( & c . CPU ) . Pointer ( ) ) if err := c . setOneRegister ( & reg ) ; err != nil { return err } reg . id = _KVM_ARM64_REGS_VBAR_EL1 fromLocation := reflect . ValueOf ( ring0 . Vectors ) . Pointer ( ) offset := fromLocation & ( 1 << 11 - 1 ) if offset != 0 { offset = 1 << 11 - offset } toLocation := fromLocation + offset data = uint64 ( ring0 . KernelStartAddress | toLocation ) if err := c . setOneRegister ( & reg ) ; err != nil { return err } arm64HypercallMMIOBase = toLocation if hasGuestPCID { c . PCIDs = pagetables . NewPCIDs ( fixedKernelPCID + 1 , poolPCIDs ) } c . floatingPointState = fpu . NewState ( ) return c . setSystemTime ( ) }
initArchState initializes architecture-specific state.
initArchState initializes architecture - specific state .
// tcr_el1 // mair_el1 // ttbr0_el1 // ttbr1_el1 // sp_el1 // pc // r8 // vbar_el1 // Use the address of the exception vector table as // the MMIO address base. // Initialize the PCID database. // Note that NewPCIDs may return a nil table here, in which // case we simply don't use PCID support (see below). In // practice, this should not happen, however.