// interrupt handles the USB hardware interrupt events and notifies the device
// controller driver using a common "virtual interrupt" code.
interrupt handles the USB hardware interrupt events and notifies the device
controller driver using a common "virtual interrupt" code.
// interrupt handles the USB hardware interrupt events and notifies the device // controller driver using a common " virtual interrupt " code .
func (d *dhw) interrupt() {
	status := d.bus.USBSTS.Get() & d.bus.USBINTR.Get()
	d.bus.USBSTS.Set(status)
	if 0 != status&nxp.USB_USBSTS_UI {
		setupStatus := d.bus.ENDPTSETUPSTAT.Get()
		for 0 != setupStatus {
			d.bus.ENDPTSETUPSTAT.Set(setupStatus)
			var setup dcdSetup
			ready := false
			for !ready {
				d.bus.USBCMD.SetBits(nxp.USB_USBCMD_SUTW)
				setup = d.stat.setup
				ready = d.bus.USBCMD.HasBits(nxp.USB_USBCMD_SUTW)
			}
			d.bus.USBCMD.ClearBits(nxp.USB_USBCMD_SUTW)
			d.bus.ENDPTFLUSH.Set(0x00010001)
			for d.bus.ENDPTFLUSH.HasBits(0x00010001) {
			}
			d.event(dcdEvent{
				id:    dcdEventControlSetup,
				setup: setup,
			})
			setupStatus = d.bus.ENDPTSETUPSTAT.Get()
		}
		completeStatus := d.bus.ENDPTCOMPLETE.Get()
		if 0 != completeStatus {
			d.bus.ENDPTCOMPLETE.Set(completeStatus)
			if 0 != completeStatus&d.controlMask {
				d.controlComplete(completeStatus)
			}
			completeStatus &= d.endpointMask
			if 0 != completeStatus {
				tx := completeStatus >> 16
				for 0 != tx {
					num := uint8(bits.TrailingZeros32(tx))
					d.endpointComplete(txEndpoint(num))
					tx &^= 1 << num
				}
				rx := completeStatus & 0xFFFF
				for 0 != rx {
					num := uint8(bits.TrailingZeros32(rx))
					d.endpointComplete(rxEndpoint(num))
					rx &^= 1 << num
				}
			}
			d.event(dcdEvent{
				id:   dcdEventTransactComplete,
				mask: completeStatus,
			})
		}
	}
	if 0 != status&nxp.USB_USBSTS_URI {
		d.bus.ENDPTSETUPSTAT.Set(d.bus.ENDPTSETUPSTAT.Get())
		d.bus.ENDPTCOMPLETE.Set(d.bus.ENDPTCOMPLETE.Get())
		for 0 != d.bus.ENDPTPRIME.Get() {
		}
		d.bus.ENDPTFLUSH.Set(0xFFFFFFFF)
		d.event(dcdEvent{id: dcdEventStatusReset})
	}
	if 0 != status&nxp.USB_USBSTS_TI0 {
		if nil != d.timerInterrupt[0] {
			d.timerInterrupt[0]()
		}
		d.event(dcdEvent{id: dcdEventTimer, mask: 0})
	}
	if 0 != status&nxp.USB_USBSTS_TI1 {
		if nil != d.timerInterrupt[1] {
			d.timerInterrupt[1]()
		}
		d.event(dcdEvent{id: dcdEventTimer, mask: 1})
	}
	if 0 != status&nxp.USB_USBSTS_PCI {
		if d.bus.PORTSC1.HasBits(nxp.USB_PORTSC1_HSP) {
			d.busSpeed = descDeviceSpeedHigh 
		} else {
			d.busSpeed = descDeviceSpeedFull 
		}
		d.event(dcdEvent{id: dcdEventStatusRun})
	}
	if 0 != status&nxp.USB_USBSTS_SLI {
		d.event(dcdEvent{id: dcdEventStatusSuspend})
	}
	if 0 != status&nxp.USB_USBSTS_UEI {
		d.event(dcdEvent{id: dcdEventStatusError})
	}
	if d.bus.USBINTR.HasBits(nxp.USB_USBINTR_SRE) &&
		0 != status&nxp.USB_USBSTS_SRI {
		if 0 != d.timerReboot {
			d.timerReboot -= 1
			if 0 == d.timerReboot {
				d.enableSOF(false, descCDCACMInterfaceCount)
				runBootloader()
			}
		}
	}
}
func ( d * dhw ) interrupt ( ) { status := d . bus . USBSTS . Get ( ) & d . bus . USBINTR . Get ( ) d . bus . USBSTS . Set ( status ) if 0 != status & nxp . USB_USBSTS_UI { setupStatus := d . bus . ENDPTSETUPSTAT . Get ( ) for 0 != setupStatus { d . bus . ENDPTSETUPSTAT . Set ( setupStatus ) var setup dcdSetup ready := false for ! ready { d . bus . USBCMD . SetBits ( nxp . USB_USBCMD_SUTW ) setup = d . stat . setup ready = d . bus . USBCMD . HasBits ( nxp . USB_USBCMD_SUTW ) } d . bus . USBCMD . ClearBits ( nxp . USB_USBCMD_SUTW ) d . bus . ENDPTFLUSH . Set ( 0x00010001 ) for d . bus . ENDPTFLUSH . HasBits ( 0x00010001 ) { } d . event ( dcdEvent { id : dcdEventControlSetup , setup : setup , } ) setupStatus = d . bus . ENDPTSETUPSTAT . Get ( ) } completeStatus := d . bus . ENDPTCOMPLETE . Get ( ) if 0 != completeStatus { d . bus . ENDPTCOMPLETE . Set ( completeStatus ) if 0 != completeStatus & d . controlMask { d . controlComplete ( completeStatus ) } completeStatus &= d . endpointMask if 0 != completeStatus { tx := completeStatus >> 16 for 0 != tx { num := uint8 ( bits . TrailingZeros32 ( tx ) ) d . endpointComplete ( txEndpoint ( num ) ) tx &^= 1 << num } rx := completeStatus & 0xFFFF for 0 != rx { num := uint8 ( bits . TrailingZeros32 ( rx ) ) d . endpointComplete ( rxEndpoint ( num ) ) rx &^= 1 << num } } d . event ( dcdEvent { id : dcdEventTransactComplete , mask : completeStatus , } ) } } if 0 != status & nxp . USB_USBSTS_URI { d . bus . ENDPTSETUPSTAT . Set ( d . bus . ENDPTSETUPSTAT . Get ( ) ) d . bus . ENDPTCOMPLETE . Set ( d . bus . ENDPTCOMPLETE . Get ( ) ) for 0 != d . bus . ENDPTPRIME . Get ( ) { } d . bus . ENDPTFLUSH . Set ( 0xFFFFFFFF ) d . event ( dcdEvent { id : dcdEventStatusReset } ) } if 0 != status & nxp . USB_USBSTS_TI0 { if nil != d . timerInterrupt [ 0 ] { d . timerInterrupt [ 0 ] ( ) } d . event ( dcdEvent { id : dcdEventTimer , mask : 0 } ) } if 0 != status & nxp . USB_USBSTS_TI1 { if nil != d . timerInterrupt [ 1 ] { d . timerInterrupt [ 1 ] ( ) } d . event ( dcdEvent { id : dcdEventTimer , mask : 1 } ) } if 0 != status & nxp . USB_USBSTS_PCI { if d . bus . PORTSC1 . HasBits ( nxp . USB_PORTSC1_HSP ) { d . busSpeed = descDeviceSpeedHigh } else { d . busSpeed = descDeviceSpeedFull } d . event ( dcdEvent { id : dcdEventStatusRun } ) } if 0 != status & nxp . USB_USBSTS_SLI { d . event ( dcdEvent { id : dcdEventStatusSuspend } ) } if 0 != status & nxp . USB_USBSTS_UEI { d . event ( dcdEvent { id : dcdEventStatusError } ) } if d . bus . USBINTR . HasBits ( nxp . USB_USBINTR_SRE ) && 0 != status & nxp . USB_USBSTS_SRI { if 0 != d . timerReboot { d . timerReboot -= 1 if 0 == d . timerReboot { d . enableSOF ( false , descCDCACMInterfaceCount ) runBootloader ( ) } } } }
interrupt handles the USB hardware interrupt events and notifies the device
controller driver using a common "virtual interrupt" code.
interrupt handles the USB hardware interrupt events and notifies the device controller driver using a common " virtual interrupt " code .
// read and clear the interrupts that fired // USB Interrupt (USBINT) - R/WC // This bit is set by the Host/Device Controller when the cause of an // interrupt is a completion of a USB transaction where the Transfer // Descriptor (TD) has an interrupt on complete (IOC) bit set. // This bit is also set by the Host/Device Controller when a short packet is // detected. A short packet is when the actual number of bytes received was // less than the expected number of bytes. // flush endpoint 0 (bit 0=Rx, 16=Tx) // wait for flush to complete // Notify device controller driver // Notify device controller driver // USB Reset Received - R/WC // When the device controller detects a USB Reset and enters the default // state, this bit will be set to a one. // Software can write a 1 to this bit to clear the USB Reset Received status // bit. // Only used in device operation mode. // clear all setup tokens // clear all endpoint complete status // wait on any endpoint priming // General Purpose Timer Interrupt 0(GPTINT0) - R/WC // This bit is set when the counter in the GPTIMER0CTRL register transitions // to zero, writing a one to this bit clears it. // General Purpose Timer Interrupt 1(GPTINT1) - R/WC // This bit is set when the counter in the GPTIMER1CTRL register transitions // to zero, writing a one to this bit will clear it. // Port Change Detect - R/WC // The Host Controller sets this bit to a one when on any port a Connect // Status occurs, a Port Enable/Disable Change occurs, or the Force Port // Resume bit is set as the result of a J-K transition on the suspended port. // The Device Controller sets this bit to a one when the port controller // enters the full or high-speed operational state. When the port controller // exits the full or high-speed operation states due to Reset or Suspend // events, the notification mechanisms are the USB Reset Received bit and the // DCSuspend bits respectively. // 480 Mbit/sec // 12 Mbit/sec // DCSuspend - R/WC // When a controller enters a suspend state from an active state, this bit // will be set to a one. The device controller clears the bit upon exiting // from a suspend state. Only used in device operation mode. // USB Error Interrupt (USBERRINT) - R/WC // When completion of a USB transaction results in an error condition, this // bit is set by the Host/Device Controller. This bit is set along with the // USBINT bit, if the TD on which the error interrupt occurred also had its // interrupt on complete (IOC) bit set. // The device controller detects resume signaling only. // SOF Received - R/WC // When the device controller detects a Start Of (micro) Frame, this bit will // be set to a one. When a SOF is extremely late, the device controller will // automatically set this bit to indicate that an SOF was expected. // Therefore, this bit will be set roughly every 1ms in device FS mode and // every 125us in HS mode and will be synchronized to the actual SOF that is // received. // Because the device controller is initialized to FS before connect, this bit // will be set at an interval of 1ms during the prelude to connect and chirp. // In host mode, this bit will be set every 125us and can be used by host // controller driver as a time base. Software writes a 1 to this bit to clear // it.