// init configures the USB port for device mode operation by initializing all
// endpoint and transfer descriptor data structures, initializing core registers
// and interrupts, resetting the USB PHY, and enabling power on the bust.
init configures the USB port for device mode operation by initializing all
endpoint and transfer descriptor data structures, initializing core registers
and interrupts, resetting the USB PHY, and enabling power on the bust.
// init configures the USB port for device mode operation by initializing all // endpoint and transfer descriptor data structures initializing core registers // and interrupts resetting the USB PHY and enabling power on the bust .
func (d *dhw) init() status {
	d.phy.CTRL_SET.Set(nxp.USBPHY_CTRL_SFTRST)
	d.bus.USBCMD.SetBits(nxp.USB_USBCMD_RST)
	for d.bus.USBCMD.HasBits(nxp.USB_USBCMD_RST) {
	}
	d.irq.SetPriority(dhwInterruptPriority)
	m := arm.DisableInterrupts()
	switch d.port {
	case 0:
		m &^= uintptr(nxp.IRQ_USB_OTG1)
	case 1:
		m &^= uintptr(nxp.IRQ_USB_OTG2)
	}
	arm.EnableInterrupts(m)
	d.phy.CTRL_CLR.Set(nxp.USBPHY_CTRL_CLKGATE | nxp.USBPHY_CTRL_SFTRST)
	d.phy.PWD.Set(0) 
	d.bus.USBMODE.ReplaceBits(nxp.USB_USBMODE_CM_CM_2,
		nxp.USB_USBMODE_CM_Msk>>nxp.USB_USBMODE_CM_Pos, nxp.USB_USBMODE_CM_Pos)
	d.bus.USBCMD.ClearBits(nxp.USB_USBCMD_ITC_Msk)  
	d.bus.USBMODE.SetBits(nxp.USB_USBMODE_SLOM_Msk) 
	d.bus.USBMODE.ClearBits(nxp.USB_USBMODE_ES_Msk) 
	d.stat = d.endpointQueueHead(rxEndpoint(0))
	d.ctrl = d.endpointQueueHead(txEndpoint(0))
	d.stat.config = (descEndptMaxPktSize << 16) | (1 << 15)
	d.ctrl.config = (descEndptMaxPktSize << 16)
	d.bus.ASYNCLISTADDR.Set(uint32(uintptr(unsafe.Pointer(d.stat))))
	d.timerInterrupt[0] = nil
	d.timerInterrupt[1] = nil
	d.bus.USBINTR.Set(
		nxp.USB_USBINTR_UE_Msk | 
			nxp.USB_USBINTR_UEE_Msk | 
			nxp.USB_USBINTR_PCE_Msk | 
			nxp.USB_USBINTR_URE_Msk | 
			nxp.USB_USBINTR_SLE) 
	udelay(5000)
	return statusOK
}
func ( d * dhw ) init ( ) status { d . phy . CTRL_SET . Set ( nxp . USBPHY_CTRL_SFTRST ) d . bus . USBCMD . SetBits ( nxp . USB_USBCMD_RST ) for d . bus . USBCMD . HasBits ( nxp . USB_USBCMD_RST ) { } d . irq . SetPriority ( dhwInterruptPriority ) m := arm . DisableInterrupts ( ) switch d . port { case 0 : m &^= uintptr ( nxp . IRQ_USB_OTG1 ) case 1 : m &^= uintptr ( nxp . IRQ_USB_OTG2 ) } arm . EnableInterrupts ( m ) d . phy . CTRL_CLR . Set ( nxp . USBPHY_CTRL_CLKGATE | nxp . USBPHY_CTRL_SFTRST ) d . phy . PWD . Set ( 0 ) d . bus . USBMODE . ReplaceBits ( nxp . USB_USBMODE_CM_CM_2 , nxp . USB_USBMODE_CM_Msk >> nxp . USB_USBMODE_CM_Pos , nxp . USB_USBMODE_CM_Pos ) d . bus . USBCMD . ClearBits ( nxp . USB_USBCMD_ITC_Msk ) d . bus . USBMODE . SetBits ( nxp . USB_USBMODE_SLOM_Msk ) d . bus . USBMODE . ClearBits ( nxp . USB_USBMODE_ES_Msk ) d . stat = d . endpointQueueHead ( rxEndpoint ( 0 ) ) d . ctrl = d . endpointQueueHead ( txEndpoint ( 0 ) ) d . stat . config = ( descEndptMaxPktSize << 16 ) | ( 1 << 15 ) d . ctrl . config = ( descEndptMaxPktSize << 16 ) d . bus . ASYNCLISTADDR . Set ( uint32 ( uintptr ( unsafe . Pointer ( d . stat ) ) ) ) d . timerInterrupt [ 0 ] = nil d . timerInterrupt [ 1 ] = nil d . bus . USBINTR . Set ( nxp . USB_USBINTR_UE_Msk | nxp . USB_USBINTR_UEE_Msk | nxp . USB_USBINTR_PCE_Msk | nxp . USB_USBINTR_URE_Msk | nxp . USB_USBINTR_SLE ) udelay ( 5000 ) return statusOK }
init configures the USB port for device mode operation by initializing all
endpoint and transfer descriptor data structures, initializing core registers
and interrupts, resetting the USB PHY, and enabling power on the bust.
init configures the USB port for device mode operation by initializing all endpoint and transfer descriptor data structures initializing core registers and interrupts resetting the USB PHY and enabling power on the bust .
// Reset the controller // Initialize USB interrupt priorities // Clear interrupts // Initiate reset, and enable PHY power supply // ["Power down"] 0 = Power enabled, 1 = Power disabled // Clear the controller mode field and set to device mode: //   Controller mode (CM) 0x0=idle, 0x2=device-only, 0x3=host-only // No interrupt threshold // Disable setup lockout // Use little-endianness // Initialize control endpoint 0 (stat = Rx/OUT, ctrl = Tx/IN) // Install base address of endpoints // Clear installed timer callbacks // Enable interrupts in USB core // bus enable // bus error // port change detect // bus reset // sleep enable // Ensure D+ pulled down long enough for host to detect previous disconnect