SharpDisasm/Translators/ATTTranslator.cs
/// <summary>
/// Generates assembly output for each operand
/// </summary>
/// <param name="u"></param>
/// <param name="op"></param>
Generates assembly output for each operand
Generates assembly output for each operand
void
        gen_operand(Instruction u, Operand op)
        {
            switch (op.Type)
            {
                case Udis86.ud_type.UD_OP_CONST:
                    Content.AppendFormat("$0x{0:x4}", op.LvalUDWord);
                    break;
                case Udis86.ud_type.UD_OP_REG:
                    Content.AppendFormat("%{0}", RegisterForType(op.Base));
                    break;
                case Udis86.ud_type.UD_OP_MEM:
                    if (u.br_far != 0)
                    {
                        opr_cast(u, op);
                    }
                    if (u.pfx_seg != 0)
                    {
                        Content.AppendFormat("%{0}:", RegisterForType((Udis86.ud_type)u.pfx_seg));
                    }
                    if (op.Offset != 0)
                    {
                        ud_syn_print_mem_disp(u, op, 0);
                    }
                    bool resolvingRip = ResolveRip && op.Base == Udis86.ud_type.UD_R_RIP && op.Index == Udis86.ud_type.UD_NONE;
                    if (op.Base != Udis86.ud_type.UD_NONE && !resolvingRip)
                    {
                        Content.AppendFormat("(%{0}", RegisterForType(op.Base));
                    }
                    if (op.Index != Udis86.ud_type.UD_NONE)
                    {
                        if (op.Base != Udis86.ud_type.UD_NONE)
                        {
                            Content.Append(",");
                        }
                        else
                        {
                            Content.Append("(");
                        }
                        Content.AppendFormat("%{0}", RegisterForType(op.Index));
                    }
                    if (op.Scale != 0)
                    {
                        Content.AppendFormat(",{0}", op.Scale);
                    }
                    if (!resolvingRip && (op.Base != Udis86.ud_type.UD_NONE || op.Index != Udis86.ud_type.UD_NONE))
                    {
                        Content.Append(")");
                    }
                    break;
                case Udis86.ud_type.UD_OP_IMM:
                    Content.Append("$");
                    ud_syn_print_imm(u, op);
                    break;
                case Udis86.ud_type.UD_OP_JIMM:
                    ud_syn_print_addr(u, (long)ud_syn_rel_target(u, op));
                    break;
                case Udis86.ud_type.UD_OP_PTR:
                    switch (op.Size)
                    {
                        case 32:
                            Content.AppendFormat("$0x{0:x}, $0x{1:x}", op.PtrSegment,
                              op.PtrOffset & 0xFFFF);
                            break;
                        case 48:
                            Content.AppendFormat("$0x{0:x}, $0x{1:x}", op.PtrSegment,
                              op.PtrOffset);
                            break;
                    }
                    break;
                default: return;
            }
        }
void gen_operand ( Instruction u , Operand op ) { switch ( op . Type ) { case Udis86 . ud_type . UD_OP_CONST : Content . AppendFormat ( " " , op . LvalUDWord ) ; break ; case Udis86 . ud_type . UD_OP_REG : Content . AppendFormat ( " " , RegisterForType ( op . Base ) ) ; break ; case Udis86 . ud_type . UD_OP_MEM : if ( u . br_far != 0 ) { opr_cast ( u , op ) ; } if ( u . pfx_seg != 0 ) { Content . AppendFormat ( " " , RegisterForType ( ( Udis86 . ud_type ) u . pfx_seg ) ) ; } if ( op . Offset != 0 ) { ud_syn_print_mem_disp ( u , op , 0 ) ; } bool resolvingRip = ResolveRip && op . Base == Udis86 . ud_type . UD_R_RIP && op . Index == Udis86 . ud_type . UD_NONE ; if ( op . Base != Udis86 . ud_type . UD_NONE && ! resolvingRip ) { Content . AppendFormat ( " " , RegisterForType ( op . Base ) ) ; } if ( op . Index != Udis86 . ud_type . UD_NONE ) { if ( op . Base != Udis86 . ud_type . UD_NONE ) { Content . Append ( " " ) ; } else { Content . Append ( " " ) ; } Content . AppendFormat ( " " , RegisterForType ( op . Index ) ) ; } if ( op . Scale != 0 ) { Content . AppendFormat ( " " , op . Scale ) ; } if ( ! resolvingRip && ( op . Base != Udis86 . ud_type . UD_NONE || op . Index != Udis86 . ud_type . UD_NONE ) ) { Content . Append ( " " ) ; } break ; case Udis86 . ud_type . UD_OP_IMM : Content . Append ( " " ) ; ud_syn_print_imm ( u , op ) ; break ; case Udis86 . ud_type . UD_OP_JIMM : ud_syn_print_addr ( u , ( long ) ud_syn_rel_target ( u , op ) ) ; break ; case Udis86 . ud_type . UD_OP_PTR : switch ( op . Size ) { case 32 : Content . AppendFormat ( " " , op . PtrSegment , op . PtrOffset & 0xFFFF ) ; break ; case 48 : Content . AppendFormat ( " " , op . PtrSegment , op . PtrOffset ) ; break ; } break ; default : return ; } }
Generates assembly output for each operand
Generates assembly output for each operand
// don't print out the base register rip if resolve rip option is enabled
u
Instruction
None
op
Operand
None