openfpga/src/fabric/build_mux_modules.cpp
/***********************************************
 * Generate Verilog modules for all the unique
 * multiplexers in the FPGA device
 **********************************************/
Generate Verilog modules for all the unique
multiplexers in the FPGA device
Generate Verilog modules for all the unique multiplexers in the FPGA device
void build_mux_modules(ModuleManager& module_manager,
                       const MuxLibrary& mux_lib,
                       const CircuitLibrary& circuit_lib) {
  vtr::ScopedStartFinishTimer timer("Building multiplexer modules");
  for (auto mux : mux_lib.muxes()) {
    const MuxGraph& mux_graph = mux_lib.mux_graph(mux);
    CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux); 
    std::vector<MuxGraph> branch_mux_graphs = mux_graph.build_mux_branch_graphs();
    for (auto branch_mux_graph : branch_mux_graphs) {
      build_mux_branch_module(module_manager, circuit_lib, mux_circuit_model, 
                              branch_mux_graph);
    }
  }
  for (auto mux : mux_lib.muxes()) {
    const MuxGraph& mux_graph = mux_lib.mux_graph(mux);
    CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux); 
    build_mux_module(module_manager, circuit_lib, mux_circuit_model, mux_graph);
  }
}
void build_mux_modules ( ModuleManager & module_manager , const MuxLibrary & mux_lib , const CircuitLibrary & circuit_lib ) { vtr :: ScopedStartFinishTimer timer ( " " ) ; for ( auto mux : mux_lib . muxes ( ) ) { const MuxGraph & mux_graph = mux_lib . mux_graph ( mux ) ; CircuitModelId mux_circuit_model = mux_lib . mux_circuit_model ( mux ) ; std :: vector < MuxGraph > branch_mux_graphs = mux_graph . build_mux_branch_graphs ( ) ; for ( auto branch_mux_graph : branch_mux_graphs ) { build_mux_branch_module ( module_manager , circuit_lib , mux_circuit_model , branch_mux_graph ) ; } } for ( auto mux : mux_lib . muxes ( ) ) { const MuxGraph & mux_graph = mux_lib . mux_graph ( mux ) ; CircuitModelId mux_circuit_model = mux_lib . mux_circuit_model ( mux ) ; build_mux_module ( module_manager , circuit_lib , mux_circuit_model , mux_graph ) ; } }
Generate Verilog modules for all the unique
 multiplexers in the FPGA device
Generate Verilog modules for all the unique multiplexers in the FPGA device
/* Generate basis sub-circuit for unique branches shared by the multiplexers */ /* Create a mux graph for the branch circuit */ /* Create branch circuits, which are N:1 one-level or 2:1 tree-like MUXes */ /* Generate unique Verilog modules for the multiplexers */ /* Create MUX circuits */