openfpga/src/base/openfpga_build_fabric.cpp
/********************************************************************
 * Build the module graph for FPGA device
 *******************************************************************/
Build the module graph for FPGA device
Build the module graph for FPGA device
int write_fabric_hierarchy(const OpenfpgaContext& openfpga_ctx,
                           const Command& cmd, const CommandContext& cmd_context) { 
  CommandOptionId opt_verbose = cmd.option("verbose");
  CommandOptionId opt_file = cmd.option("file");
  VTR_ASSERT(true == cmd_context.option_enable(cmd, opt_file));
  VTR_ASSERT(false == cmd_context.option_value(cmd, opt_file).empty());
  int depth = -1;
  CommandOptionId opt_depth = cmd.option("depth");
  if (true == cmd_context.option_enable(cmd, opt_depth)) {
    depth = std::atoi(cmd_context.option_value(cmd, opt_depth).c_str());
    if (0 > depth) {
      VTR_LOG_ERROR("Invalid depth '%d' which should be 0 or a positive number!\n",
                    depth);
      return CMD_EXEC_FATAL_ERROR; 
    }
  }
  std::string hie_file_name = cmd_context.option_value(cmd, opt_file);
  return write_fabric_hierarchy_to_text_file(openfpga_ctx.module_graph(),
                                             hie_file_name,
                                             size_t(depth),
                                             cmd_context.option_enable(cmd, opt_verbose));
}
int write_fabric_hierarchy ( const OpenfpgaContext & openfpga_ctx , const Command & cmd , const CommandContext & cmd_context ) { CommandOptionId opt_verbose = cmd . option ( " " ) ; CommandOptionId opt_file = cmd . option ( " " ) ; VTR_ASSERT ( true == cmd_context . option_enable ( cmd , opt_file ) ) ; VTR_ASSERT ( false == cmd_context . option_value ( cmd , opt_file ) . empty ( ) ) ; int depth = -1 ; CommandOptionId opt_depth = cmd . option ( " " ) ; if ( true == cmd_context . option_enable ( cmd , opt_depth ) ) { depth = std :: atoi ( cmd_context . option_value ( cmd , opt_depth ) . c_str ( ) ) ; if ( 0 > depth ) { VTR_LOG_ERROR ( " \n " , depth ) ; return CMD_EXEC_FATAL_ERROR ; } } std :: string hie_file_name = cmd_context . option_value ( cmd , opt_file ) ; return write_fabric_hierarchy_to_text_file ( openfpga_ctx . module_graph ( ) , hie_file_name , size_t ( depth ) , cmd_context . option_enable ( cmd , opt_verbose ) ) ; }
Build the module graph for FPGA device
Build the module graph for FPGA device
/* Check the option '--file' is enabled or not 
   * Actually, it must be enabled as the shell interface will check 
   * before reaching this fuction
   */ /* Default depth requirement, will not stop until the leaf */ /* Error out if we have negative depth */ /* Write hierarchy to a file */