openfpga/src/fpga_sdc/sdc_writer_utils.cpp
/********************************************************************
 * Constrain a path between two ports of a module with a given timing value
 * Note: this function uses set_max_delay !!!
 *******************************************************************/
Constrain a path between two ports of a module with a given timing value
Note: this function uses set_max_delay
Constrain a path between two ports of a module with a given timing value Note : this function uses set_max_delay
void print_pnr_sdc_constrain_module_port2port_timing(std::fstream& fp,
                                                     const ModuleManager& module_manager,
                                                     const ModuleId& input_parent_module_id, 
                                                     const ModulePortId& module_input_port_id, 
                                                     const ModuleId& output_parent_module_id, 
                                                     const ModulePortId& module_output_port_id, 
                                                     const float& tmax) {
  print_pnr_sdc_constrain_max_delay(fp,
                                    module_manager.module_name(input_parent_module_id),
                                    generate_sdc_port(module_manager.module_port(input_parent_module_id, module_input_port_id)),
                                    module_manager.module_name(output_parent_module_id),
                                    generate_sdc_port(module_manager.module_port(output_parent_module_id, module_output_port_id)),
                                    tmax);
}
void print_pnr_sdc_constrain_module_port2port_timing ( std :: fstream & fp , const ModuleManager & module_manager , const ModuleId & input_parent_module_id , const ModulePortId & module_input_port_id , const ModuleId & output_parent_module_id , const ModulePortId & module_output_port_id , const float & tmax ) { print_pnr_sdc_constrain_max_delay ( fp , module_manager . module_name ( input_parent_module_id ) , generate_sdc_port ( module_manager . module_port ( input_parent_module_id , module_input_port_id ) ) , module_manager . module_name ( output_parent_module_id ) , generate_sdc_port ( module_manager . module_port ( output_parent_module_id , module_output_port_id ) ) , tmax ) ; }
Constrain a path between two ports of a module with a given timing value
 Note: this function uses set_max_delay !
Constrain a path between two ports of a module with a given timing value Note : this function uses set_max_delay !