openfpga/src/base/openfpga_sdc.cpp
/********************************************************************
 * A wrapper function to call the analysis SDC generator of FPGA-SDC
 *******************************************************************/
A wrapper function to call the analysis SDC generator of FPGA-SDC
A wrapper function to call the analysis SDC generator of FPGA - SDC
int write_analysis_sdc(const OpenfpgaContext& openfpga_ctx,
                       const Command& cmd, const CommandContext& cmd_context) {
  CommandOptionId opt_output_dir = cmd.option("file");
  CommandOptionId opt_flatten_names = cmd.option("flatten_names");
  CommandOptionId opt_time_unit = cmd.option("time_unit");
  std::string sdc_dir_path = format_dir_path(cmd_context.option_value(cmd, opt_output_dir));
  create_directory(sdc_dir_path);
  AnalysisSdcOption options(sdc_dir_path);
  options.set_generate_sdc_analysis(true);
  options.set_flatten_names(cmd_context.option_enable(cmd, opt_flatten_names));
  if (true == cmd_context.option_enable(cmd, opt_time_unit)) {
    options.set_time_unit(string_to_time_unit(cmd_context.option_value(cmd, opt_time_unit)));
  }
  if (true == options.generate_sdc_analysis()) {
    print_analysis_sdc(options,
                       1./openfpga_ctx.simulation_setting().default_operating_clock_frequency(),
                       g_vpr_ctx, 
                       openfpga_ctx,
                       openfpga_ctx.flow_manager().compress_routing());
  }
  return CMD_EXEC_SUCCESS;
}
int write_analysis_sdc ( const OpenfpgaContext & openfpga_ctx , const Command & cmd , const CommandContext & cmd_context ) { CommandOptionId opt_output_dir = cmd . option ( " " ) ; CommandOptionId opt_flatten_names = cmd . option ( " " ) ; CommandOptionId opt_time_unit = cmd . option ( " " ) ; std :: string sdc_dir_path = format_dir_path ( cmd_context . option_value ( cmd , opt_output_dir ) ) ; create_directory ( sdc_dir_path ) ; AnalysisSdcOption options ( sdc_dir_path ) ; options . set_generate_sdc_analysis ( true ) ; options . set_flatten_names ( cmd_context . option_enable ( cmd , opt_flatten_names ) ) ; if ( true == cmd_context . option_enable ( cmd , opt_time_unit ) ) { options . set_time_unit ( string_to_time_unit ( cmd_context . option_value ( cmd , opt_time_unit ) ) ) ; } if ( true == options . generate_sdc_analysis ( ) ) { print_analysis_sdc ( options , 1. / openfpga_ctx . simulation_setting ( ) . default_operating_clock_frequency ( ) , g_vpr_ctx , openfpga_ctx , openfpga_ctx . flow_manager ( ) . compress_routing ( ) ) ; } return CMD_EXEC_SUCCESS ; }
A wrapper function to call the analysis SDC generator of FPGA-SDC
A wrapper function to call the analysis SDC generator of FPGA - SDC
/* This is an intermediate data structure which is designed to modularize the FPGA-SDC
   * Keep it independent from any other outside data structures
   */ /* Create directories */ /* TODO: should identify the error code from internal function execution */