16_USART_DMA_sender/user/RCC.cpp
/* System clocks init ------------------------------------------------------- */
/**
 * @brief  Configures the System clock source, PLL Multiplier and Divider
 * factors AHB/APBx prescalers and Flash settings
 * @Note   This function should be called only once the RCC clock configuration
 *         is reset to the default reset state (done in SystemInit() function).
 * @param  None
 * @retval None
 */
System clocks init
@brief  Configures the System clock source, PLL Multiplier and Divider
factors AHB/APBx prescalers and Flash settings
@Note   This function should be called only once the RCC clock configuration
is reset to the default reset state (done in SystemInit() function).
@param  None
@retval None
System clocks init @brief Configures the System clock source PLL Multiplier and Divider factors AHB / APBx prescalers and Flash settings @Note This function should be called only once the RCC clock configuration is reset to the default reset state ( done in SystemInit () function ) . @param None @retval None
void InitSystemClock(void) {
  uint32_t StartUpCounter = 0u;
  uint32_t HSEStatus = 0u;
  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
  while ((HSEStatus == 0u) && (StartUpCounter < HSE_STARTUP_TIMEOUT)) {
    HSEStatus = RCC->CR & RCC_CR_HSERDY;
    ++StartUpCounter;
  }
  if (HSEStatus == RCC_CR_HSERDY) {
    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
    PWR->CR |= PWR_CR_VOS;
    RCC->CFGR |= AHB_PRESCALER;
    RCC->CFGR |= APB2_PRESCALER;
    RCC->CFGR |= APB1_PRESCALER;
    RCC->PLLCFGR = PLL_M | (PLL_N << 6u) | (((PLL_P >> 1u) - 1u) << 16u) |
                   (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24u);
    RCC->CR |= RCC_CR_PLLON;
    while ((RCC->CR & RCC_CR_PLLRDY) == 0u) {
    }
#if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
    defined(STM32F446xx)
    PWR->CR |= PWR_CR_ODEN;
    while ((PWR->CSR & PWR_CSR_ODRDY) == 0u) {
    }
    PWR->CR |= PWR_CR_ODSWEN;
    while ((PWR->CSR & PWR_CSR_ODSWRDY) == 0u) {
    }
    FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN |
                 FLASH_ACR_LATENCY_5WS;
#endif 
#if defined(STM32F407xx)
    FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN |
                 FLASH_ACR_LATENCY_5WS;
#endif 
#if defined(STM32F401xx)
    FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN |
                 FLASH_ACR_LATENCY_2WS;
#endif 
    RCC->CFGR &= (uint32_t)((uint32_t) ~(RCC_CFGR_SW));
    RCC->CFGR |= RCC_CFGR_SW_PLL;
    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {
    }
    SystemCoreClockUpdate();
  } else {
    while (1) {
    }
  }
}
void InitSystemClock ( void ) { uint32_t StartUpCounter = 0u ; uint32_t HSEStatus = 0u ; RCC -> CR |= ( ( uint32_t ) RCC_CR_HSEON ) ; while ( ( HSEStatus == 0u ) && ( StartUpCounter < HSE_STARTUP_TIMEOUT ) ) { HSEStatus = RCC -> CR & RCC_CR_HSERDY ; ++ StartUpCounter ; } if ( HSEStatus == RCC_CR_HSERDY ) { RCC -> APB1ENR |= RCC_APB1ENR_PWREN ; PWR -> CR |= PWR_CR_VOS ; RCC -> CFGR |= AHB_PRESCALER ; RCC -> CFGR |= APB2_PRESCALER ; RCC -> CFGR |= APB1_PRESCALER ; RCC -> PLLCFGR = PLL_M | ( PLL_N << 6u ) | ( ( ( PLL_P >> 1u ) - 1u ) << 16u ) | ( RCC_PLLCFGR_PLLSRC_HSE ) | ( PLL_Q << 24u ) ; RCC -> CR |= RCC_CR_PLLON ; while ( ( RCC -> CR & RCC_CR_PLLRDY ) == 0u ) { } #if defined ( STM32F427xx ) || defined ( STM32F429xx ) || defined ( STM32F439xx ) || defined ( STM32F446xx ) PWR -> CR |= PWR_CR_ODEN ; while ( ( PWR -> CSR & PWR_CSR_ODRDY ) == 0u ) { } PWR -> CR |= PWR_CR_ODSWEN ; while ( ( PWR -> CSR & PWR_CSR_ODSWRDY ) == 0u ) { } FLASH -> ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_5WS ; #endif #if defined ( STM32F407xx ) FLASH -> ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_5WS ; #endif #if defined ( STM32F401xx ) FLASH -> ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_2WS ; #endif RCC -> CFGR &= ( uint32_t ) ( ( uint32_t ) ~ ( RCC_CFGR_SW ) ) ; RCC -> CFGR |= RCC_CFGR_SW_PLL ; while ( ( RCC -> CFGR & ( uint32_t ) RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL ) { } SystemCoreClockUpdate ( ) ; } else { while ( 1 ) { } } }
System clocks init 
 @brief  Configures the System clock source, PLL Multiplier and Divider
 factors AHB/APBx prescalers and Flash settings
 @Note   This function should be called only once the RCC clock configuration
         is reset to the default reset state (done in SystemInit() function).
System clocks init @brief Configures the System clock source PLL Multiplier and Divider factors AHB / APBx prescalers and Flash settings @Note This function should be called only once the RCC clock configuration is reset to the default reset state ( done in SystemInit () function ) .
/**************************************************************************/ /*            PLL (clocked by HSE) used as System clock source            */ /**************************************************************************/ /* Enable HSE */ /* Wait till HSE is ready and if Time out is reached exit */ /* Voltage regulator Scale 1 */ /* HCLK = SYSCLK / 1 */ /* PCLK2 = HCLK / 2 */ /* PCLK1 = HCLK / 4 */ /* Configure the main PLL */ /* Enable the main PLL */ /* Wait till the main PLL is ready */ /* Enable the Over-drive to extend the clock frequency to 180 Mhz */ /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ /* STM32F427xx || STM32F429xx  */ /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ /* STM32F407xx  */ /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ /* STM32F401xx */ /* Select the main PLL as system clock source */ /* Wait till the main PLL is used as system clock source */ /* If HSE fails to start-up, the application will have wrong clock
    configuration. User can add here some code to deal with this error */