openfpga/src/fabric/build_module_graph_utils.cpp
/********************************************************************
 * Find input port of a buffer/inverter module
 ********************************************************************/
Find input port of a buffer/inverter module
Find input port of a buffer / inverter module
ModulePortId find_inverter_buffer_module_port(const ModuleManager& module_manager, 
                                              const ModuleId& module_id, 
                                              const CircuitLibrary& circuit_lib, 
                                              const CircuitModelId& model_id,
                                              const e_circuit_model_port_type& port_type) {
  VTR_ASSERT(true == module_manager.valid_module_id(module_id));
  VTR_ASSERT(CIRCUIT_MODEL_INVBUF == circuit_lib.model_type(model_id));
  std::vector<CircuitPortId> model_ports = circuit_lib.model_ports_by_type(model_id, port_type, true);
  VTR_ASSERT(1 == model_ports.size());
  ModulePortId module_port_id = module_manager.find_module_port(module_id, circuit_lib.port_prefix(model_ports[0]));
  VTR_ASSERT(true == module_manager.valid_module_port_id(module_id, module_port_id));
  return module_port_id;  
}
ModulePortId find_inverter_buffer_module_port ( const ModuleManager & module_manager , const ModuleId & module_id , const CircuitLibrary & circuit_lib , const CircuitModelId & model_id , const e_circuit_model_port_type & port_type ) { VTR_ASSERT ( true == module_manager . valid_module_id ( module_id ) ) ; VTR_ASSERT ( CIRCUIT_MODEL_INVBUF == circuit_lib . model_type ( model_id ) ) ; std :: vector < CircuitPortId > model_ports = circuit_lib . model_ports_by_type ( model_id , port_type , true ) ; VTR_ASSERT ( 1 == model_ports . size ( ) ) ; ModulePortId module_port_id = module_manager . find_module_port ( module_id , circuit_lib . port_prefix ( model_ports [ 0 ] ) ) ; VTR_ASSERT ( true == module_manager . valid_module_port_id ( module_id , module_port_id ) ) ; return module_port_id ; }
Find input port of a buffer/inverter module
Find input port of a buffer / inverter module
/* We must have a valid module id */ /* Check the type of model */ /* Add module nets to wire to the buffer module */ /* To match the context, Buffer should have only 2 non-global ports: 1 input port and 1 output port */ /* Find the input and output module ports */