libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp
/********************************************************************
 * Top-level function to parse an XML file and load data to :
 * 1. circuit library
 *******************************************************************/
Top-level function to parse an XML file and load data to :
1. circuit library
Top - level function to parse an XML file and load data to : 1 . circuit library
openfpga::Arch read_xml_openfpga_arch(const char* arch_file_name) {
  vtr::ScopedStartFinishTimer timer("Read OpenFPGA architecture");
  openfpga::Arch openfpga_arch;
  pugi::xml_node Next;
  pugi::xml_document doc;
  pugiutil::loc_data loc_data;
  try {
    loc_data = pugiutil::load_xml(doc, arch_file_name);
    auto xml_openfpga_arch = get_single_child(doc, "openfpga_architecture", loc_data); 
    auto xml_circuit_models = get_single_child(xml_openfpga_arch, "circuit_library", loc_data);
    openfpga_arch.circuit_lib = read_xml_circuit_library(xml_circuit_models, loc_data);
    openfpga_arch.circuit_lib.auto_detect_default_models();
    openfpga_arch.circuit_lib.build_model_links();
    openfpga_arch.circuit_lib.build_timing_graphs();
    auto xml_tech_lib = get_single_child(xml_openfpga_arch, "technology_library", loc_data); 
    openfpga_arch.tech_lib = read_xml_technology_library(xml_tech_lib, loc_data);
    openfpga_arch.tech_lib.link_models_to_variations();
    bind_circuit_model_to_technology_model(openfpga_arch);
    openfpga_arch.config_protocol = read_xml_config_protocol(xml_openfpga_arch, loc_data);
    link_config_protocol_to_circuit_library(openfpga_arch);
    config_circuit_models_sram_port_to_default_sram_model(openfpga_arch.circuit_lib,
                                                          openfpga_arch.config_protocol.memory_model());
    openfpga_arch.cb_switch2circuit = read_xml_cb_switch_circuit(xml_openfpga_arch, loc_data,
                                                                 openfpga_arch.circuit_lib);
    openfpga_arch.cb_switch2circuit = read_xml_cb_switch_circuit(xml_openfpga_arch, loc_data,
                                                                 openfpga_arch.circuit_lib);
    openfpga_arch.sb_switch2circuit = read_xml_sb_switch_circuit(xml_openfpga_arch, loc_data,
                                                                 openfpga_arch.circuit_lib);
    openfpga_arch.routing_seg2circuit = read_xml_routing_segment_circuit(xml_openfpga_arch, loc_data,
                                                                         openfpga_arch.circuit_lib);
    openfpga_arch.arch_direct = read_xml_direct_circuit(xml_openfpga_arch, loc_data,
                                                        openfpga_arch.circuit_lib);
    openfpga_arch.tile_annotations = read_xml_tile_annotations(xml_openfpga_arch, loc_data);
    openfpga_arch.pb_type_annotations = read_xml_pb_type_annotations(xml_openfpga_arch, loc_data);
  } catch (pugiutil::XmlError& e) {
    archfpga_throw(arch_file_name, e.line(),
                   "%s", e.what());
  }
  return openfpga_arch;
}
openfpga :: Arch read_xml_openfpga_arch ( const char * arch_file_name ) { vtr :: ScopedStartFinishTimer timer ( " " ) ; openfpga :: Arch openfpga_arch ; pugi :: xml_node Next ; pugi :: xml_document doc ; pugiutil :: loc_data loc_data ; try { loc_data = pugiutil :: load_xml ( doc , arch_file_name ) ; auto xml_openfpga_arch = get_single_child ( doc , " " , loc_data ) ; auto xml_circuit_models = get_single_child ( xml_openfpga_arch , " " , loc_data ) ; openfpga_arch . circuit_lib = read_xml_circuit_library ( xml_circuit_models , loc_data ) ; openfpga_arch . circuit_lib . auto_detect_default_models ( ) ; openfpga_arch . circuit_lib . build_model_links ( ) ; openfpga_arch . circuit_lib . build_timing_graphs ( ) ; auto xml_tech_lib = get_single_child ( xml_openfpga_arch , " " , loc_data ) ; openfpga_arch . tech_lib = read_xml_technology_library ( xml_tech_lib , loc_data ) ; openfpga_arch . tech_lib . link_models_to_variations ( ) ; bind_circuit_model_to_technology_model ( openfpga_arch ) ; openfpga_arch . config_protocol = read_xml_config_protocol ( xml_openfpga_arch , loc_data ) ; link_config_protocol_to_circuit_library ( openfpga_arch ) ; config_circuit_models_sram_port_to_default_sram_model ( openfpga_arch . circuit_lib , openfpga_arch . config_protocol . memory_model ( ) ) ; openfpga_arch . cb_switch2circuit = read_xml_cb_switch_circuit ( xml_openfpga_arch , loc_data , openfpga_arch . circuit_lib ) ; openfpga_arch . cb_switch2circuit = read_xml_cb_switch_circuit ( xml_openfpga_arch , loc_data , openfpga_arch . circuit_lib ) ; openfpga_arch . sb_switch2circuit = read_xml_sb_switch_circuit ( xml_openfpga_arch , loc_data , openfpga_arch . circuit_lib ) ; openfpga_arch . routing_seg2circuit = read_xml_routing_segment_circuit ( xml_openfpga_arch , loc_data , openfpga_arch . circuit_lib ) ; openfpga_arch . arch_direct = read_xml_direct_circuit ( xml_openfpga_arch , loc_data , openfpga_arch . circuit_lib ) ; openfpga_arch . tile_annotations = read_xml_tile_annotations ( xml_openfpga_arch , loc_data ) ; openfpga_arch . pb_type_annotations = read_xml_pb_type_annotations ( xml_openfpga_arch , loc_data ) ; } catch ( pugiutil :: XmlError & e ) { archfpga_throw ( arch_file_name , e . line ( ) , " " , e . what ( ) ) ; } return openfpga_arch ; }
Top-level function to parse an XML file and load data to :
 1. circuit library
Top - level function to parse an XML file and load data to : 1 . circuit library
/* Parse the file */ /* First node should be <openfpga_architecture> */ /* Parse circuit_models to circuit library 
     * under the node <module_circuit_models> 
     */ /* Automatically identify the default models for circuit library */ /* Build the internal links for the circuit library */ /* Build the timing graph inside the circuit library */ /* Parse technology library */ /* Build the internal link for technology library */ /* Binding circuit models to device models */ /* Parse configuration protocol to data structure */ /* Build the internal link between configuration protocol and circuit library */ /* Now, we can know the default configurable memory model 
     * Apply it to all the SRAM ports of circuit models
     */ /* Parse the connection block circuit definition */ /* Parse the connection block circuit definition */ /* Parse the switch block circuit definition */ /* Parse the routing segment circuit definition */ /* Parse the direct circuit definition */ /* Parse the pb_type annotation */ /* Parse the pb_type annotation */