third_party/virtualbox/src/VBox/Devices/Network/DevE1000.cpp
/**
 * Read handler for Interrupt Cause Read register.
 *
 * Reading this register acknowledges all interrupts.
 *
 * @returns VBox status code.
 *
 * @param   pThis       The device state structure.
 * @param   offset      Register offset in memory-mapped frame.
 * @param   index       Register index in register array.
 * @param   mask        Not used.
 * @thread  EMT
 */
Read handler for Interrupt Cause Read register.
Reading this register acknowledges all interrupts.

@returns VBox status code.

@param   pThis       The device state structure.
@param   offset      Register offset in memory-mapped frame.
@param   index       Register index in register array.
@param   mask        Not used.
@thread  EMT
Read handler for Interrupt Cause Read register . Reading this register acknowledges all interrupts . @returns VBox status code . @param pThis The device state structure . @param offset Register offset in memory - mapped frame . @param index Register index in register array . @param mask Not used . @thread EMT
static int e1kRegReadICR(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t *pu32Value)
{
    int rc = e1kCsEnter(pThis, VINF_IOM_R3_MMIO_READ);
    if (RT_UNLIKELY(rc != VINF_SUCCESS))
        return rc;
    uint32_t value = 0;
    rc = e1kRegReadDefault(pThis, offset, index, &value);
    if (RT_SUCCESS(rc))
    {
        if (value)
        {
            if (!pThis->fIntRaised)
                E1K_INC_ISTAT_CNT(pThis->uStatNoIntICR);
            if (1)
            {
                E1kLogRel(("E1000: irq lowered, icr=0x%x\n", ICR));
                E1kLog(("%s e1kRegReadICR: Lowered IRQ (%08x)\n", pThis->szPrf, ICR));
                ICR = 0;
                pThis->fIntRaised = false;
                PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 0);
                pThis->u64AckedAt = TMTimerGet(pThis->CTX_SUFF(pIntTimer));
                if (pThis->fIntMaskUsed)
                    pThis->fDelayInts = true;
            }
            else
            {
                E1kLog(("%s e1kRegReadICR: Suppressing auto-clear due to disabled interrupts (%08x)\n", pThis->szPrf, ICR));
            }
        }
        *pu32Value = value;
    }
    e1kCsLeave(pThis);
    return rc;
}
static int e1kRegReadICR ( PE1KSTATE pThis , uint32_t offset , uint32_t index , uint32_t * pu32Value ) { int rc = e1kCsEnter ( pThis , VINF_IOM_R3_MMIO_READ ) ; if ( RT_UNLIKELY ( rc != VINF_SUCCESS ) ) return rc ; uint32_t value = 0 ; rc = e1kRegReadDefault ( pThis , offset , index , & value ) ; if ( RT_SUCCESS ( rc ) ) { if ( value ) { if ( ! pThis -> fIntRaised ) E1K_INC_ISTAT_CNT ( pThis -> uStatNoIntICR ) ; if ( 1 ) { E1kLogRel ( ( " \n " , ICR ) ) ; E1kLog ( ( " \n " , pThis -> szPrf , ICR ) ) ; ICR = 0 ; pThis -> fIntRaised = false ; PDMDevHlpPCISetIrq ( pThis -> CTX_SUFF ( pDevIns ) , 0 , 0 ) ; pThis -> u64AckedAt = TMTimerGet ( pThis -> CTX_SUFF ( pIntTimer ) ) ; if ( pThis -> fIntMaskUsed ) pThis -> fDelayInts = true ; } else { E1kLog ( ( " \n " , pThis -> szPrf , ICR ) ) ; } } * pu32Value = value ; } e1kCsLeave ( pThis ) ; return rc ; }
Read handler for Interrupt Cause Read register.
Read handler for Interrupt Cause Read register .
/*
             * Not clearing ICR causes QNX to hang as it reads ICR in a loop
             * with disabled interrupts.
             */ //if (IMS) /*
                 * Interrupts were enabled -- we are supposedly at the very
                 * beginning of interrupt handler
                 */ /* Clear all pending interrupts */ /* Lower(0) INTA(0) */ /*
                 * Interrupts are disabled -- in windows guests ICR read is done
                 * just before re-enabling interrupts
                 */