openfpga/src/fabric/build_top_module_memory.cpp
/********************************************************************
 * TODO:
 * Add the port-to-port connection between a memory module 
 * and the configuration bus of a primitive module
 *
 * Create nets to wire the control signals of memory module to 
 *    the configuration ports of primitive module
 *
 *              Primitive module
 *             +----------------------------+
 *             |                +--------+  |
 *  config     |                |        |  |
 *   ports --->|--------------->| Memory |  |
 *             |                | Module |  |
 *             |                |        |  |
 *             |                +--------+  |
 *             +----------------------------+
 *     The detailed config ports really depend on the type
 *     of SRAM organization. 
 *
 * The config_bus in the argument is the reserved address of configuration
 * bus in the parent_module for this memory module
 *
 * The configuration bus connection will depend not only 
 * the design technology of the memory cells but also the 
 * configuration styles of FPGA fabric.
 * Here we will branch on the design technology
 *
 * Note: this function SHOULD be called after the pb_type_module is created
 * and its child module (logic_module and memory_module) is created! 
 *******************************************************************/
Add the port-to-port connection between a memory module
and the configuration bus of a primitive module

Create nets to wire the control signals of memory module to
the configuration ports of primitive module



The config_bus in the argument is the reserved address of configuration
bus in the parent_module for this memory module

The configuration bus connection will depend not only
the design technology of the memory cells but also the
configuration styles of FPGA fabric.
Here we will branch on the design technology

this function SHOULD be called after the pb_type_module is created
and its child module (logic_module and memory_module) is created!
Add the port - to - port connection between a memory module and the configuration bus of a primitive module Create nets to wire the control signals of memory module to the configuration ports of primitive module The config_bus in the argument is the reserved address of configuration bus in the parent_module for this memory module The configuration bus connection will depend not only the design technology of the memory cells but also the configuration styles of FPGA fabric . Here we will branch on the design technology this function SHOULD be called after the pb_type_module is created and its child module ( logic_module and memory_module ) is created!
void add_top_module_nets_memory_config_bus(ModuleManager& module_manager,
                                           DecoderLibrary& decoder_lib,
                                           const ModuleId& parent_module,
                                           const ConfigProtocol& config_protocol, 
                                           const e_circuit_model_design_tech& mem_tech,
                                           const vtr::vector<ConfigRegionId, size_t>& num_config_bits) {
  vtr::ScopedStartFinishTimer timer("Add module nets for configuration buses");
  switch (mem_tech) {
  case CIRCUIT_MODEL_DESIGN_CMOS:
    add_top_module_nets_cmos_memory_config_bus(module_manager, decoder_lib,
                                               parent_module, 
                                               config_protocol,
                                               num_config_bits);
    break;
  case CIRCUIT_MODEL_DESIGN_RRAM:
    break;
  default:
    VTR_LOGF_ERROR(__FILE__, __LINE__,
                  "Invalid type of memory design technology!\n");
    exit(1);
  }
}
void add_top_module_nets_memory_config_bus ( ModuleManager & module_manager , DecoderLibrary & decoder_lib , const ModuleId & parent_module , const ConfigProtocol & config_protocol , const e_circuit_model_design_tech & mem_tech , const vtr :: vector < ConfigRegionId , size_t > & num_config_bits ) { vtr :: ScopedStartFinishTimer timer ( " " ) ; switch ( mem_tech ) { case CIRCUIT_MODEL_DESIGN_CMOS : add_top_module_nets_cmos_memory_config_bus ( module_manager , decoder_lib , parent_module , config_protocol , num_config_bits ) ; break ; case CIRCUIT_MODEL_DESIGN_RRAM : break ; default : VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " ) ; exit ( 1 ) ; } }
TODO:
 Add the port-to-port connection between a memory module
 and the configuration bus of a primitive module
TODO : Add the port - to - port connection between a memory module and the configuration bus of a primitive module
/* TODO: */