openfpga/src/fabric/build_top_module_memory.cpp
/*********************************************************************
 * Add framed-based decoders to the top-level module
 * and build net connections between decoders and subblocks
 * 
 * For each configuration region, we create an independent decoder
 * Note that to avoid parasitic programming, all the decoders will
 * be in the same size, sharing the same principle as memory banks
 *
 * For each region, decoder and net addition will depend on the following cases:
 * - If there is no configurable child, nothing to do.
 * - If there is only one configurable child, short wire the EN, ADDR and DATA_IN to it
 * - If there are more than two configurable childern, add a decoder and build interconnection
 *   between it and the children 
 **********************************************************************/
Add framed-based decoders to the top-level module
and build net connections between decoders and subblocks

For each configuration region, we create an independent decoder
Note that to avoid parasitic programming, all the decoders will
be in the same size, sharing the same principle as memory banks

For each region, decoder and net addition will depend on the following cases:
- If there is no configurable child, nothing to do.
- If there is only one configurable child, short wire the EN, ADDR and DATA_IN to it
- If there are more than two configurable childern, add a decoder and build interconnection
between it and the children
Add framed - based decoders to the top - level module and build net connections between decoders and subblocks For each configuration region we create an independent decoder Note that to avoid parasitic programming all the decoders will be in the same size sharing the same principle as memory banks For each region decoder and net addition will depend on the following cases : - If there is no configurable child nothing to do . - If there is only one configurable child short wire the EN ADDR and DATA_IN to it - If there are more than two configurable childern add a decoder and build interconnection between it and the children
static 
void add_top_module_nets_cmos_memory_frame_config_bus(ModuleManager& module_manager,
                                                      DecoderLibrary& decoder_lib,
                                                      const ModuleId& top_module,
                                                      const vtr::vector<ConfigRegionId, size_t>& num_config_bits) {
  ModulePortId top_addr_port = module_manager.find_module_port(top_module, std::string(DECODER_ADDRESS_PORT_NAME));
  BasicPort top_addr_port_info = module_manager.module_port(top_module, top_addr_port);
  size_t top_addr_size = top_addr_port_info.get_width();
  for (const ConfigRegionId& config_region : module_manager.regions(top_module)) {
    if (0 == module_manager.region_configurable_children(top_module, config_region).size()) {
      continue; 
    }
    if ( (1 == module_manager.region_configurable_children(top_module, config_region).size())
       && (num_config_bits[config_region] == top_addr_size)) { 
      add_top_module_nets_cmos_memory_frame_short_config_bus(module_manager, top_module, config_region);
    } else {
      add_top_module_nets_cmos_memory_frame_decoder_config_bus(module_manager, decoder_lib, top_module, config_region);
    }
  }  
}
static void add_top_module_nets_cmos_memory_frame_config_bus ( ModuleManager & module_manager , DecoderLibrary & decoder_lib , const ModuleId & top_module , const vtr :: vector < ConfigRegionId , size_t > & num_config_bits ) { ModulePortId top_addr_port = module_manager . find_module_port ( top_module , std :: string ( DECODER_ADDRESS_PORT_NAME ) ) ; BasicPort top_addr_port_info = module_manager . module_port ( top_module , top_addr_port ) ; size_t top_addr_size = top_addr_port_info . get_width ( ) ; for ( const ConfigRegionId & config_region : module_manager . regions ( top_module ) ) { if ( 0 == module_manager . region_configurable_children ( top_module , config_region ) . size ( ) ) { continue ; } if ( ( 1 == module_manager . region_configurable_children ( top_module , config_region ) . size ( ) ) && ( num_config_bits [ config_region ] == top_addr_size ) ) { add_top_module_nets_cmos_memory_frame_short_config_bus ( module_manager , top_module , config_region ) ; } else { add_top_module_nets_cmos_memory_frame_decoder_config_bus ( module_manager , decoder_lib , top_module , config_region ) ; } } }
Add framed-based decoders to the top-level module
 and build net connections between decoders and subblocks
Add framed - based decoders to the top - level module and build net connections between decoders and subblocks
/* Find the number of address bits for the top-level module */ /* Short-wiring is applicable only when all the following situations are met:
     * - There is only 1 configurable child in the region
     * - The number of address bits of the configurable child is the same as top-level
     */