openfpga/src/fabric/build_routing_module_utils.cpp
/*********************************************************************
 * Generate a port for a routing track of a swtich block
 ********************************************************************/
Generate a port for a routing track of a swtich block
Generate a port for a routing track of a swtich block
ModulePortId find_connection_block_module_ipin_port(const ModuleManager& module_manager,
                                                    const ModuleId& cb_module, 
                                                    const RRGraph& rr_graph,
                                                    const RRGSB& rr_gsb, 
                                                    const RRNodeId& src_rr_node) {
  VTR_ASSERT(IPIN == rr_graph.node_type(src_rr_node));
  vtr::Point<size_t> port_coord(rr_graph.node_xlow(src_rr_node), rr_graph.node_ylow(src_rr_node));
  enum e_side cb_ipin_side = NUM_SIDES;
  int cb_ipin_index = -1;
  rr_gsb.get_node_side_and_index(rr_graph, src_rr_node, OUT_PORT, cb_ipin_side, cb_ipin_index);
  VTR_ASSERT((-1 != cb_ipin_index)&&(NUM_SIDES != cb_ipin_side));
  std::string port_name = generate_cb_module_grid_port_name(cb_ipin_side, 
                                                            rr_graph.node_pin_num(rr_gsb.get_ipin_node(cb_ipin_side, cb_ipin_index))); 
  ModulePortId ipin_port_id = module_manager.find_module_port(cb_module, port_name); 
  VTR_ASSERT(true == module_manager.valid_module_port_id(cb_module, ipin_port_id));
  return ipin_port_id;
}
ModulePortId find_connection_block_module_ipin_port ( const ModuleManager & module_manager , const ModuleId & cb_module , const RRGraph & rr_graph , const RRGSB & rr_gsb , const RRNodeId & src_rr_node ) { VTR_ASSERT ( IPIN == rr_graph . node_type ( src_rr_node ) ) ; vtr :: Point < size_t > port_coord ( rr_graph . node_xlow ( src_rr_node ) , rr_graph . node_ylow ( src_rr_node ) ) ; enum e_side cb_ipin_side = NUM_SIDES ; int cb_ipin_index = -1 ; rr_gsb . get_node_side_and_index ( rr_graph , src_rr_node , OUT_PORT , cb_ipin_side , cb_ipin_index ) ; VTR_ASSERT ( ( -1 != cb_ipin_index ) && ( NUM_SIDES != cb_ipin_side ) ) ; std :: string port_name = generate_cb_module_grid_port_name ( cb_ipin_side , rr_graph . node_pin_num ( rr_gsb . get_ipin_node ( cb_ipin_side , cb_ipin_index ) ) ) ; ModulePortId ipin_port_id = module_manager . find_module_port ( cb_module , port_name ) ; VTR_ASSERT ( true == module_manager . valid_module_port_id ( cb_module , ipin_port_id ) ) ; return ipin_port_id ; }
Generate a port for a routing track of a swtich block
Generate a port for a routing track of a swtich block
/* Ensure the src_rr_node is an input pin of a CLB */ /* Create port description for input pin of a CLB */ /* Search all the sides of a SB, see this drive_rr_node is an INPUT of this SB */ /* We need to be sure that drive_rr_node is part of the CB */ /* Must find a valid port id in the Switch Block module */