openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp
/********************************************************************
 * Top-level function writes SDC commands to disable unused ports 
 * of grids, such as Configurable Logic Block (CLBs), heterogeneous blocks, etc.
 *
 * This function will iterate over all the grids available in the FPGA fabric
 * It will disable the timing analysis for
 * 1. Grids, which are totally not used (no logic has been mapped to)
 * 2. Unused part of grids, including the ports, inputs of routing multiplexers 
 *
 * Note that it is a must to disable the unused inputs of routing multiplexers
 * because it will cause unexpected paths in timing analysis
 * For example:
 *                           +---------------------+
 *     inputA (net0) ------->|                     |
 *                           | Routing multiplexer |----> output (net0)
 *     inputB (net1) ------->|                     |
 *                           +---------------------+
 *
 * During timing analysis, the path from inputA to output should be considered
 * while the path from inputB to output should NOT be considered!!!
 *
 *******************************************************************/
Top-level function writes SDC commands to disable unused ports
of grids, such as Configurable Logic Block (CLBs), heterogeneous blocks, etc.

This function will iterate over all the grids available in the FPGA fabric
It will disable the timing analysis for
1. Grids, which are totally not used (no logic has been mapped to)
2. Unused part of grids, including the ports, inputs of routing multiplexers



During timing analysis, the path from inputA to output should be considered
while the path from inputB to output should NOT be considered
Top - level function writes SDC commands to disable unused ports of grids such as Configurable Logic Block ( CLBs ) heterogeneous blocks etc . This function will iterate over all the grids available in the FPGA fabric It will disable the timing analysis for 1 . Grids which are totally not used ( no logic has been mapped to ) 2 . Unused part of grids including the ports inputs of routing multiplexers During timing analysis the path from inputA to output should be considered while the path from inputB to output should NOT be considered
void print_analysis_sdc_disable_unused_grids(std::fstream& fp, 
                                             const DeviceGrid& grids, 
                                             const VprDeviceAnnotation& device_annotation,
                                             const VprClusteringAnnotation& cluster_annotation,
                                             const VprPlacementAnnotation& place_annotation,
                                             const ModuleManager& module_manager) {
  for (size_t ix = 1; ix < grids.width() - 1; ++ix) {
    for (size_t iy = 1; iy < grids.height() - 1; ++iy) {
      print_analysis_sdc_disable_unused_grid(fp, vtr::Point<size_t>(ix, iy),
                                             grids, device_annotation, cluster_annotation, place_annotation,
                                             module_manager, NUM_SIDES);
    }
  }
  std::map<e_side, std::vector<vtr::Point<size_t>>> io_coordinates = generate_perimeter_grid_coordinates( grids);
  for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) {
    for (const vtr::Point<size_t>& io_coordinate : io_coordinates[io_side]) {
      print_analysis_sdc_disable_unused_grid(fp, io_coordinate,
                                             grids, device_annotation, cluster_annotation, place_annotation,
                                             module_manager, io_side);
    }
  }
}
void print_analysis_sdc_disable_unused_grids ( std :: fstream & fp , const DeviceGrid & grids , const VprDeviceAnnotation & device_annotation , const VprClusteringAnnotation & cluster_annotation , const VprPlacementAnnotation & place_annotation , const ModuleManager & module_manager ) { for ( size_t ix = 1 ; ix < grids . width ( ) - 1 ; ++ ix ) { for ( size_t iy = 1 ; iy < grids . height ( ) - 1 ; ++ iy ) { print_analysis_sdc_disable_unused_grid ( fp , vtr :: Point < size_t > ( ix , iy ) , grids , device_annotation , cluster_annotation , place_annotation , module_manager , NUM_SIDES ) ; } } std :: map < e_side , std :: vector < vtr :: Point < size_t > > > io_coordinates = generate_perimeter_grid_coordinates ( grids ) ; for ( const e_side & io_side : FPGA_SIDES_CLOCKWISE ) { for ( const vtr :: Point < size_t > & io_coordinate : io_coordinates [ io_side ] ) { print_analysis_sdc_disable_unused_grid ( fp , io_coordinate , grids , device_annotation , cluster_annotation , place_annotation , module_manager , io_side ) ; } } }
Top-level function writes SDC commands to disable unused ports
 of grids, such as Configurable Logic Block (CLBs), heterogeneous blocks, etc.
Top - level function writes SDC commands to disable unused ports of grids such as Configurable Logic Block ( CLBs ) heterogeneous blocks etc .
/* Process unused core grids */ /* Instanciate I/O grids */ /* Create the coordinate range for each side of FPGA fabric */ /* Add instances of I/O grids to top_module */