libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp
/********************************************************************
 * A writer to output a circuit port to XML format
 *******************************************************************/
A writer to output a circuit port to XML format
A writer to output a circuit port to XML format
static 
void write_xml_circuit_port(std::fstream& fp,
                            const char* fname,
                            const CircuitLibrary& circuit_lib,
                            const CircuitPortId& port) {
  openfpga::check_file_stream(fname, fp);
  const CircuitModelId& model = circuit_lib.port_parent_model(port);
  fp << "\t\t\t" << "<port";
  write_xml_attribute(fp, "type", CIRCUIT_MODEL_PORT_TYPE_STRING[circuit_lib.port_type(port)]); 
  write_xml_attribute(fp, "prefix", circuit_lib.port_prefix(port).c_str()); 
  if (circuit_lib.port_prefix(port) != circuit_lib.port_lib_name(port)) {
    write_xml_attribute(fp, "lib_name", circuit_lib.port_lib_name(port).c_str()); 
  } 
  write_xml_attribute(fp, "size", std::to_string(circuit_lib.port_size(port)).c_str()); 
  if (true == circuit_lib.port_is_global(port)) {
    write_xml_attribute(fp, "default_val", std::to_string(circuit_lib.port_default_value(port)).c_str()); 
  }
  if (CIRCUIT_MODEL_PORT_SRAM == circuit_lib.port_type(port)) {
    if (true == circuit_lib.port_is_mode_select(port)) {
      write_xml_attribute(fp, "mode_select", "true"); 
    }
  }
  if ( (CIRCUIT_MODEL_LUT == circuit_lib.model_type(model))
    && (CIRCUIT_MODEL_PORT_INPUT == circuit_lib.port_type(port)) ) {
    if (!circuit_lib.port_tri_state_map(port).empty()) {
      write_xml_attribute(fp, "tri_state_map", circuit_lib.port_tri_state_map(port).c_str()); 
    }
  }
  if ( (CIRCUIT_MODEL_LUT == circuit_lib.model_type(model))
    && (CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib.port_type(port)) ) {
    if (size_t(-1) != circuit_lib.port_lut_frac_level(port)) {
      write_xml_attribute(fp, "lut_frac_level", std::to_string(circuit_lib.port_lut_frac_level(port)).c_str()); 
    }
  }
  if ( (CIRCUIT_MODEL_LUT == circuit_lib.model_type(model))
    && (CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib.port_type(port)) ) {
    std::string output_mask_string;
    for (const size_t& mask : circuit_lib.port_lut_output_mask(port)) {
      if (!output_mask_string.empty()) {
        output_mask_string += std::string(",");
      }
      output_mask_string += std::to_string(mask);
    }
    if (!output_mask_string.empty()) {
      write_xml_attribute(fp, "lut_output_mask", output_mask_string.c_str()); 
    }
  }
  if (CIRCUIT_MODEL_LUT == circuit_lib.model_type(model)) {
    if (true == circuit_lib.port_is_harden_lut_port(port)) {
      write_xml_attribute(fp, "is_harden_lut_port", "true"); 
    }
  }
  if (true == circuit_lib.port_is_io(port)) {
    write_xml_attribute(fp, "is_io", "true"); 
  }
  if (true == circuit_lib.port_is_data_io(port)) {
    write_xml_attribute(fp, "is_data_io", "true"); 
  }
  if (true == circuit_lib.port_is_global(port)) {
    write_xml_attribute(fp, "is_global", "true"); 
  }
  if (true == circuit_lib.port_is_reset(port)) {
    write_xml_attribute(fp, "is_reset", "true"); 
  }
  if (true == circuit_lib.port_is_set(port)) {
    write_xml_attribute(fp, "is_set", "true"); 
  }
  if (true == circuit_lib.port_is_prog(port)) {
    write_xml_attribute(fp, "is_prog", "true"); 
  }
  if (true == circuit_lib.port_is_config_enable(port)) {
    write_xml_attribute(fp, "is_config_enable", "true"); 
  }
  if (!circuit_lib.port_tri_state_model_name(port).empty()) {
    write_xml_attribute(fp, "circuit_model_name", circuit_lib.port_tri_state_model_name(port).c_str());
  }
  if (  (CIRCUIT_MODEL_PORT_BL  == circuit_lib.port_type(port))
     || (CIRCUIT_MODEL_PORT_WL  == circuit_lib.port_type(port))
     || (CIRCUIT_MODEL_PORT_BLB == circuit_lib.port_type(port))
     || (CIRCUIT_MODEL_PORT_WLB == circuit_lib.port_type(port)) ) {
    if (!circuit_lib.port_inv_model_name(port).empty()) {
      write_xml_attribute(fp, "inv_circuit_model_name", circuit_lib.port_inv_model_name(port).c_str());
    }
  }
  fp << "/>" << "\n";
}
static void write_xml_circuit_port ( std :: fstream & fp , const char * fname , const CircuitLibrary & circuit_lib , const CircuitPortId & port ) { openfpga :: check_file_stream ( fname , fp ) ; const CircuitModelId & model = circuit_lib . port_parent_model ( port ) ; fp << " \t \t \t " << " " ; write_xml_attribute ( fp , " " , CIRCUIT_MODEL_PORT_TYPE_STRING [ circuit_lib . port_type ( port ) ] ) ; write_xml_attribute ( fp , " " , circuit_lib . port_prefix ( port ) . c_str ( ) ) ; if ( circuit_lib . port_prefix ( port ) != circuit_lib . port_lib_name ( port ) ) { write_xml_attribute ( fp , " " , circuit_lib . port_lib_name ( port ) . c_str ( ) ) ; } write_xml_attribute ( fp , " " , std :: to_string ( circuit_lib . port_size ( port ) ) . c_str ( ) ) ; if ( true == circuit_lib . port_is_global ( port ) ) { write_xml_attribute ( fp , " " , std :: to_string ( circuit_lib . port_default_value ( port ) ) . c_str ( ) ) ; } if ( CIRCUIT_MODEL_PORT_SRAM == circuit_lib . port_type ( port ) ) { if ( true == circuit_lib . port_is_mode_select ( port ) ) { write_xml_attribute ( fp , " " , " " ) ; } } if ( ( CIRCUIT_MODEL_LUT == circuit_lib . model_type ( model ) ) && ( CIRCUIT_MODEL_PORT_INPUT == circuit_lib . port_type ( port ) ) ) { if ( ! circuit_lib . port_tri_state_map ( port ) . empty ( ) ) { write_xml_attribute ( fp , " " , circuit_lib . port_tri_state_map ( port ) . c_str ( ) ) ; } } if ( ( CIRCUIT_MODEL_LUT == circuit_lib . model_type ( model ) ) && ( CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib . port_type ( port ) ) ) { if ( size_t ( -1 ) != circuit_lib . port_lut_frac_level ( port ) ) { write_xml_attribute ( fp , " " , std :: to_string ( circuit_lib . port_lut_frac_level ( port ) ) . c_str ( ) ) ; } } if ( ( CIRCUIT_MODEL_LUT == circuit_lib . model_type ( model ) ) && ( CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib . port_type ( port ) ) ) { std :: string output_mask_string ; for ( const size_t & mask : circuit_lib . port_lut_output_mask ( port ) ) { if ( ! output_mask_string . empty ( ) ) { output_mask_string += std :: string ( " " ) ; } output_mask_string += std :: to_string ( mask ) ; } if ( ! output_mask_string . empty ( ) ) { write_xml_attribute ( fp , " " , output_mask_string . c_str ( ) ) ; } } if ( CIRCUIT_MODEL_LUT == circuit_lib . model_type ( model ) ) { if ( true == circuit_lib . port_is_harden_lut_port ( port ) ) { write_xml_attribute ( fp , " " , " " ) ; } } if ( true == circuit_lib . port_is_io ( port ) ) { write_xml_attribute ( fp , " " , " " ) ; } if ( true == circuit_lib . port_is_data_io ( port ) ) { write_xml_attribute ( fp , " " , " " ) ; } if ( true == circuit_lib . port_is_global ( port ) ) { write_xml_attribute ( fp , " " , " " ) ; } if ( true == circuit_lib . port_is_reset ( port ) ) { write_xml_attribute ( fp , " " , " " ) ; } if ( true == circuit_lib . port_is_set ( port ) ) { write_xml_attribute ( fp , " " , " " ) ; } if ( true == circuit_lib . port_is_prog ( port ) ) { write_xml_attribute ( fp , " " , " " ) ; } if ( true == circuit_lib . port_is_config_enable ( port ) ) { write_xml_attribute ( fp , " " , " " ) ; } if ( ! circuit_lib . port_tri_state_model_name ( port ) . empty ( ) ) { write_xml_attribute ( fp , " " , circuit_lib . port_tri_state_model_name ( port ) . c_str ( ) ) ; } if ( ( CIRCUIT_MODEL_PORT_BL == circuit_lib . port_type ( port ) ) || ( CIRCUIT_MODEL_PORT_WL == circuit_lib . port_type ( port ) ) || ( CIRCUIT_MODEL_PORT_BLB == circuit_lib . port_type ( port ) ) || ( CIRCUIT_MODEL_PORT_WLB == circuit_lib . port_type ( port ) ) ) { if ( ! circuit_lib . port_inv_model_name ( port ) . empty ( ) ) { write_xml_attribute ( fp , " " , circuit_lib . port_inv_model_name ( port ) . c_str ( ) ) ; } } fp << " " << " \n " ; }
A writer to output a circuit port to XML format
A writer to output a circuit port to XML format
/* Validate the file stream */ /* Get the parent circuit model for this port */ /* Generic information about a port */ /* Output the lib_name when it is different than prefix */ /* Output the default value only when this is a global port */ /* SRAM port may be for mode selection. Output it only when it is true */ /* Output the tri-state map of the port 
   * This is only applicable to input ports of a LUT
   */ /* Identify the fracturable-level of the port in LUTs, by default it will be -1
   * This is only applicable to output ports of a LUT
   */ /* Output the output mask of the port 
   * This is only applicable to output ports of a LUT
   */ /* LUT harden port attributes */ /* I/O port attributes */ /* Global, reset, set port attributes */ /* Output the name of circuit model that this port is linked to */ /* Find the name of circuit model that port is used for inversion of signals,
   * This is only applicable to BL/WL/BLB/WLB ports
   */ /* Finish all the attributes, we can return here */