openfpga/src/fpga_sdc/sdc_writer_utils.cpp
/********************************************************************
 * Constrain a path between two ports of a module with a given minimum timing value
 *******************************************************************/
Constrain a path between two ports of a module with a given minimum timing value
Constrain a path between two ports of a module with a given minimum timing value
void print_pnr_sdc_constrain_min_delay(std::fstream& fp,
                                       const std::string& src_instance_name,
                                       const std::string& src_port_name,
                                       const std::string& des_instance_name,
                                       const std::string& des_port_name,
                                       const float& delay) {
  valid_file_stream(fp);
  fp << "set_min_delay";
  fp << " -from ";
  if (!src_instance_name.empty()) {
    fp << format_dir_path(src_instance_name);
  }
  fp << src_port_name;
  fp << " -to ";
  if (!des_instance_name.empty()) {
    fp << format_dir_path(des_instance_name);
  }
  fp << des_port_name;
  fp << " " << std::setprecision(10) << delay;
  fp << std::endl;
}
void print_pnr_sdc_constrain_min_delay ( std :: fstream & fp , const std :: string & src_instance_name , const std :: string & src_port_name , const std :: string & des_instance_name , const std :: string & des_port_name , const float & delay ) { valid_file_stream ( fp ) ; fp << " " ; fp << " " ; if ( ! src_instance_name . empty ( ) ) { fp << format_dir_path ( src_instance_name ) ; } fp << src_port_name ; fp << " " ; if ( ! des_instance_name . empty ( ) ) { fp << format_dir_path ( des_instance_name ) ; } fp << des_port_name ; fp << " " << std :: setprecision ( 10 ) << delay ; fp << std :: endl ; }
Constrain a path between two ports of a module with a given minimum timing value
Constrain a path between two ports of a module with a given minimum timing value
/* Validate file stream */