openfpga/src/utils/memory_utils.cpp
/*********************************************************************
 * Create a port-to-port map for a memory module 
 * The content of the port-to-port map will depend not only 
 * the design technology of the memory cells but also the 
 * configuration styles of FPGA fabric.
 * Here we will branch on the design technology
 **********************************************************************/
Create a port-to-port map for a memory module
The content of the port-to-port map will depend not only
the design technology of the memory cells but also the
configuration styles of FPGA fabric.
Here we will branch on the design technology
Create a port - to - port map for a memory module The content of the port - to - port map will depend not only the design technology of the memory cells but also the configuration styles of FPGA fabric . Here we will branch on the design technology
std::map<std::string, BasicPort> generate_mem_module_port2port_map(const BasicPort& config_bus,
                                                                   const std::vector<BasicPort>& mem_output_bus_ports,
                                                                   const e_circuit_model_design_tech& mem_design_tech,
                                                                   const e_config_protocol_type& sram_orgz_type) {
  std::map<std::string, BasicPort> port2port_name_map;
  switch (mem_design_tech) {
  case CIRCUIT_MODEL_DESIGN_CMOS:
    port2port_name_map = generate_cmos_mem_module_port2port_map(config_bus, mem_output_bus_ports, sram_orgz_type);
    break;
  case CIRCUIT_MODEL_DESIGN_RRAM:
    port2port_name_map = generate_rram_mem_module_port2port_map(config_bus, mem_output_bus_ports, sram_orgz_type);
    break;
  default:
    VTR_LOG_ERROR("Invalid type of memory design technology!\n");
    exit(1);
  }
  return port2port_name_map;
}
std :: map < std :: string , BasicPort > generate_mem_module_port2port_map ( const BasicPort & config_bus , const std :: vector < BasicPort > & mem_output_bus_ports , const e_circuit_model_design_tech & mem_design_tech , const e_config_protocol_type & sram_orgz_type ) { std :: map < std :: string , BasicPort > port2port_name_map ; switch ( mem_design_tech ) { case CIRCUIT_MODEL_DESIGN_CMOS : port2port_name_map = generate_cmos_mem_module_port2port_map ( config_bus , mem_output_bus_ports , sram_orgz_type ) ; break ; case CIRCUIT_MODEL_DESIGN_RRAM : port2port_name_map = generate_rram_mem_module_port2port_map ( config_bus , mem_output_bus_ports , sram_orgz_type ) ; break ; default : VTR_LOG_ERROR ( " \n " ) ; exit ( 1 ) ; } return port2port_name_map ; }
Create a port-to-port map for a memory module
 The content of the port-to-port map will depend not only
 the design technology of the memory cells but also the
 configuration styles of FPGA fabric.
Create a port - to - port map for a memory module The content of the port - to - port map will depend not only the design technology of the memory cells but also the configuration styles of FPGA fabric .