third_party/virtualbox/src/VBox/Devices/Network/DevE1000.cpp
/**
 * Write handler for Interrupt Mask Clear register.
 *
 * Bits corresponding to 1s in 'value' will be cleared in IMS register.
 *
 * @param   pThis       The device state structure.
 * @param   offset      Register offset in memory-mapped frame.
 * @param   index       Register index in register array.
 * @param   value       The value to store.
 * @param   mask        Used to implement partial writes (8 and 16-bit).
 * @thread  EMT
 */
Write handler for Interrupt Mask Clear register.
Bits corresponding to 1s in 'value' will be cleared in IMS register.

@param   pThis       The device state structure.
@param   offset      Register offset in memory-mapped frame.
@param   index       Register index in register array.
@param   value       The value to store.
@param   mask        Used to implement partial writes (8 and 16-bit).
@thread  EMT
Write handler for Interrupt Mask Clear register . Bits corresponding to 1s in ' value ' will be cleared in IMS register . @param pThis The device state structure . @param offset Register offset in memory - mapped frame . @param index Register index in register array . @param value The value to store . @param mask Used to implement partial writes ( 8 and 16 - bit ) . @thread EMT
static int e1kRegWriteIMC(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
{
    RT_NOREF_PV(offset); RT_NOREF_PV(index);
    int rc = e1kCsEnter(pThis, VINF_IOM_R3_MMIO_WRITE);
    if (RT_UNLIKELY(rc != VINF_SUCCESS))
        return rc;
    if (pThis->fIntRaised)
    {
        E1K_INC_ISTAT_CNT(pThis->uStatIntLower);
        STAM_COUNTER_INC(&pThis->StatIntsPrevented);
        E1kLogRel(("E1000: irq lowered (IMC), icr=0x%x\n", ICR));
        PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 0);
        pThis->fIntRaised = false;
        E1kLog(("%s e1kRegWriteIMC: Lowered IRQ: ICR=%08x\n", pThis->szPrf, ICR));
    }
    IMS &= ~value;
    E1kLog(("%s e1kRegWriteIMC: IRQ disabled\n", pThis->szPrf));
    e1kCsLeave(pThis);
    return VINF_SUCCESS;
}
static int e1kRegWriteIMC ( PE1KSTATE pThis , uint32_t offset , uint32_t index , uint32_t value ) { RT_NOREF_PV ( offset ) ; RT_NOREF_PV ( index ) ; int rc = e1kCsEnter ( pThis , VINF_IOM_R3_MMIO_WRITE ) ; if ( RT_UNLIKELY ( rc != VINF_SUCCESS ) ) return rc ; if ( pThis -> fIntRaised ) { E1K_INC_ISTAT_CNT ( pThis -> uStatIntLower ) ; STAM_COUNTER_INC ( & pThis -> StatIntsPrevented ) ; E1kLogRel ( ( " \n " , ICR ) ) ; PDMDevHlpPCISetIrq ( pThis -> CTX_SUFF ( pDevIns ) , 0 , 0 ) ; pThis -> fIntRaised = false ; E1kLog ( ( " \n " , pThis -> szPrf , ICR ) ) ; } IMS &= ~ value ; E1kLog ( ( " \n " , pThis -> szPrf ) ) ; e1kCsLeave ( pThis ) ; return VINF_SUCCESS ; }
Write handler for Interrupt Mask Clear register.
Write handler for Interrupt Mask Clear register .
/*
         * Technically we should reset fIntRaised in ICR read handler, but it will cause
         * Windows to freeze since it may receive an interrupt while still in the very beginning
         * of interrupt handler.
         */ /* Lower(0) INTA(0) */