openfpga/src/fpga_spice/spice_mux.cpp
/***********************************************
 * Generate primitive SPICE subcircuits for all the unique
 * multiplexers in the FPGA device
 **********************************************/
Generate primitive SPICE subcircuits for all the unique
multiplexers in the FPGA device
Generate primitive SPICE subcircuits for all the unique multiplexers in the FPGA device
static 
int print_spice_submodule_mux_primitives(NetlistManager& netlist_manager,
                                         const ModuleManager& module_manager,
                                         const MuxLibrary& mux_lib,
                                         const CircuitLibrary& circuit_lib,
                                         const std::string& submodule_dir) {
  int status = CMD_EXEC_SUCCESS;
  std::string spice_fname(submodule_dir + std::string(MUX_PRIMITIVES_SPICE_FILE_NAME));
  std::fstream fp;
  fp.open(spice_fname, std::fstream::out | std::fstream::trunc);
  check_file_stream(spice_fname.c_str(), fp);
  VTR_LOG("Writing SPICE netlist for Multiplexer primitives '%s' ...",
          spice_fname.c_str()); 
  print_spice_file_header(fp, "Multiplexer primitives"); 
  std::map<std::string, bool> branch_mux_module_is_outputted;
  for (auto mux : mux_lib.muxes()) {
    const MuxGraph& mux_graph = mux_lib.mux_graph(mux);
    CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux); 
    std::vector<MuxGraph> branch_mux_graphs = mux_graph.build_mux_branch_graphs();
    for (auto branch_mux_graph : branch_mux_graphs) {
      generate_spice_mux_branch_subckt(module_manager, circuit_lib, fp, mux_circuit_model, 
                                       branch_mux_graph,
                                       branch_mux_module_is_outputted);
    }
  }
  fp.close();
  NetlistId nlist_id = netlist_manager.add_netlist(spice_fname);
  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
  netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST);
  VTR_LOG("Done\n");
  return status;
}
static int print_spice_submodule_mux_primitives ( NetlistManager & netlist_manager , const ModuleManager & module_manager , const MuxLibrary & mux_lib , const CircuitLibrary & circuit_lib , const std :: string & submodule_dir ) { int status = CMD_EXEC_SUCCESS ; std :: string spice_fname ( submodule_dir + std :: string ( MUX_PRIMITIVES_SPICE_FILE_NAME ) ) ; std :: fstream fp ; fp . open ( spice_fname , std :: fstream :: out | std :: fstream :: trunc ) ; check_file_stream ( spice_fname . c_str ( ) , fp ) ; VTR_LOG ( " " , spice_fname . c_str ( ) ) ; print_spice_file_header ( fp , " " ) ; std :: map < std :: string , bool > branch_mux_module_is_outputted ; for ( auto mux : mux_lib . muxes ( ) ) { const MuxGraph & mux_graph = mux_lib . mux_graph ( mux ) ; CircuitModelId mux_circuit_model = mux_lib . mux_circuit_model ( mux ) ; std :: vector < MuxGraph > branch_mux_graphs = mux_graph . build_mux_branch_graphs ( ) ; for ( auto branch_mux_graph : branch_mux_graphs ) { generate_spice_mux_branch_subckt ( module_manager , circuit_lib , fp , mux_circuit_model , branch_mux_graph , branch_mux_module_is_outputted ) ; } } fp . close ( ) ; NetlistId nlist_id = netlist_manager . add_netlist ( spice_fname ) ; VTR_ASSERT ( NetlistId :: INVALID ( ) != nlist_id ) ; netlist_manager . set_netlist_type ( nlist_id , NetlistManager :: SUBMODULE_NETLIST ) ; VTR_LOG ( " \n " ) ; return status ; }
Generate primitive SPICE subcircuits for all the unique
 multiplexers in the FPGA device
Generate primitive SPICE subcircuits for all the unique multiplexers in the FPGA device
/* Create the file stream */ /* Print out debugging information for if the file is not opened/created properly */ /* Record if the branch module has been outputted
   * since different sizes of routing multiplexers may share the same branch module
   */ /* Generate basis sub-circuit for unique branches shared by the multiplexers */ /* Create a mux graph for the branch circuit */ /* Create branch circuits, which are N:1 one-level or 2:1 tree-like MUXes */ /* Close the file stream */ /* Add fname to the netlist name list */