openfpga/src/fabric/build_essential_modules.cpp
/************************************************
 * Build a module of inverter or buffer 
 * or tapered buffer to a file 
 ***********************************************/
Build a module of inverter or buffer
or tapered buffer to a file
Build a module of inverter or buffer or tapered buffer to a file
static 
void build_invbuf_module(ModuleManager& module_manager, 
                         const CircuitLibrary& circuit_lib,
                         const CircuitModelId& circuit_model) {
  std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
  std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
  std::vector<CircuitPortId> global_ports = circuit_lib.model_global_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true, true);
  VTR_ASSERT( (1 == input_ports.size()) && (1 == circuit_lib.port_size(input_ports[0])) );
  VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
  if (true == circuit_lib.is_power_gated(circuit_model)) { 
    size_t num_err = 0;
    if (0 == global_ports.size())  {
      num_err++;
    }
    for (const auto& port : global_ports) {
      if (false == circuit_lib.port_is_config_enable(port)) {
        num_err++;
      }
    }
    if (0 < num_err) {
      VTR_LOGF_ERROR(__FILE__, __LINE__, "Inverter/buffer circuit model '%s' is power-gated. At least one config-enable global port is required!\n",
                 circuit_lib.model_name(circuit_model).c_str()); 
      exit(1);
    }
  }
  ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model); 
  VTR_ASSERT(true == module_manager.valid_module_id(module_id));
}
static void build_invbuf_module ( ModuleManager & module_manager , const CircuitLibrary & circuit_lib , const CircuitModelId & circuit_model ) { std :: vector < CircuitPortId > input_ports = circuit_lib . model_ports_by_type ( circuit_model , CIRCUIT_MODEL_PORT_INPUT , true ) ; std :: vector < CircuitPortId > output_ports = circuit_lib . model_ports_by_type ( circuit_model , CIRCUIT_MODEL_PORT_OUTPUT , true ) ; std :: vector < CircuitPortId > global_ports = circuit_lib . model_global_ports_by_type ( circuit_model , CIRCUIT_MODEL_PORT_INPUT , true , true ) ; VTR_ASSERT ( ( 1 == input_ports . size ( ) ) && ( 1 == circuit_lib . port_size ( input_ports [ 0 ] ) ) ) ; VTR_ASSERT ( ( 1 == output_ports . size ( ) ) && ( 1 == circuit_lib . port_size ( output_ports [ 0 ] ) ) ) ; if ( true == circuit_lib . is_power_gated ( circuit_model ) ) { size_t num_err = 0 ; if ( 0 == global_ports . size ( ) ) { num_err ++ ; } for ( const auto & port : global_ports ) { if ( false == circuit_lib . port_is_config_enable ( port ) ) { num_err ++ ; } } if ( 0 < num_err ) { VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " , circuit_lib . model_name ( circuit_model ) . c_str ( ) ) ; exit ( 1 ) ; } } ModuleId module_id = add_circuit_model_to_module_manager ( module_manager , circuit_lib , circuit_model ) ; VTR_ASSERT ( true == module_manager . valid_module_id ( module_id ) ) ; }
Build a module of inverter or buffer
 or tapered buffer to a file
Build a module of inverter or buffer or tapered buffer to a file
/* Find the input port, output port and global inputs*/ /* Make sure:
   * There is only 1 input port and 1 output port, 
   * each size of which is 1
   */ /* TODO: move the check codes to check_circuit_library.h */ /* If the circuit model is power-gated, we need to find at least one global config_enable signals */ /* Check all the ports we have are good for a power-gated circuit model */ /* We need at least one global port */ /* All the global ports should be config_enable */ /* Report errors if there are any */ /* Create a Verilog Module based on the circuit model, and add to module manager */