openfpga/src/fabric/build_essential_modules.cpp
/*********************************************************************
 * This function will rename the ports of primitive modules 
 * using lib_name instead of prefix
 * Primitive modules are defined as those modules in the module manager 
 * which have user defined netlists
 ********************************************************************/
This function will rename the ports of primitive modules
using lib_name instead of prefix
Primitive modules are defined as those modules in the module manager
which have user defined netlists
This function will rename the ports of primitive modules using lib_name instead of prefix Primitive modules are defined as those modules in the module manager which have user defined netlists
void rename_primitive_module_port_names(ModuleManager& module_manager, 
                                        const CircuitLibrary& circuit_lib) {
  for (const CircuitModelId& model : circuit_lib.models()) {
    if ( (true == circuit_lib.model_verilog_netlist(model).empty())
      && (true == circuit_lib.model_spice_netlist(model).empty()) ) {
      if ( (CIRCUIT_MODEL_INVBUF != circuit_lib.model_type(model))
          && (CIRCUIT_MODEL_PASSGATE != circuit_lib.model_type(model))
          && (CIRCUIT_MODEL_GATE != circuit_lib.model_type(model)) ) {
        continue;
      }
    }
    if (CIRCUIT_MODEL_CHAN_WIRE == circuit_lib.model_type(model)) {
      continue;
    }
    ModuleId module = module_manager.find_module(circuit_lib.model_name(model));
    VTR_ASSERT(true == module_manager.valid_module_id(module));
    for (const CircuitPortId& model_port : circuit_lib.model_ports(model)) {
      ModulePortId module_port = module_manager.find_module_port(module, circuit_lib.port_prefix(model_port));
      VTR_ASSERT(true == module_manager.valid_module_port_id(module, module_port));
      module_manager.set_module_port_name(module, module_port, circuit_lib.port_lib_name(model_port));
    }
  }
}
void rename_primitive_module_port_names ( ModuleManager & module_manager , const CircuitLibrary & circuit_lib ) { for ( const CircuitModelId & model : circuit_lib . models ( ) ) { if ( ( true == circuit_lib . model_verilog_netlist ( model ) . empty ( ) ) && ( true == circuit_lib . model_spice_netlist ( model ) . empty ( ) ) ) { if ( ( CIRCUIT_MODEL_INVBUF != circuit_lib . model_type ( model ) ) && ( CIRCUIT_MODEL_PASSGATE != circuit_lib . model_type ( model ) ) && ( CIRCUIT_MODEL_GATE != circuit_lib . model_type ( model ) ) ) { continue ; } } if ( CIRCUIT_MODEL_CHAN_WIRE == circuit_lib . model_type ( model ) ) { continue ; } ModuleId module = module_manager . find_module ( circuit_lib . model_name ( model ) ) ; VTR_ASSERT ( true == module_manager . valid_module_id ( module ) ) ; for ( const CircuitPortId & model_port : circuit_lib . model_ports ( model ) ) { ModulePortId module_port = module_manager . find_module_port ( module , circuit_lib . port_prefix ( model_port ) ) ; VTR_ASSERT ( true == module_manager . valid_module_port_id ( module , module_port ) ) ; module_manager . set_module_port_name ( module , module_port , circuit_lib . port_lib_name ( model_port ) ) ; } } }
This function will rename the ports of primitive modules
 using lib_name instead of prefix
 Primitive modules are defined as those modules in the module manager
 which have user defined netlists
This function will rename the ports of primitive modules using lib_name instead of prefix Primitive modules are defined as those modules in the module manager which have user defined netlists
/* We only care about user-defined models */ /* Exception circuit models as primitive cells
       * - Inverter, buffer, pass-gate logic, logic gate
       * which should be renamed even when auto-generated
       */ /* Skip Routing channel wire models because they need a different name. Do it later */ /* Find the module in module manager */ /* We must find one! */ /* Rename all the ports to use lib_name! */ /* Find the module port in module manager. We used prefix when creating the ports */ /* We must find one! */ /* Name it with lib_name */