openfpga/src/fabric/build_top_module_memory.cpp
/********************************************************************
 * This function will create nets for the following types of connections:
 *  - Connect the enable signal to the EN of memory module
 *  - Connect the address port to the address port of memory module
 *  - Connect the data_in (Din) to the data_in of the memory module
 *    Note that the top-level module may have multiple regions and 
 *    therefore the Din port have multiple pins. The Din of local decoder
 *    should be connected the Din pin indexed by current configuration region
 *
 *       EN  ADDR[X-1:0] DATA_IN[N-1:0]
 *        |     |            |
 *        |     |            |     Top module
 *   +----+-----+------------+------------------
 *   |    |     |            |
 *   |    v     v            v                              
 *   | +-------------------------------+
 *   | | EN ADDR[X-1:0] DATA_IN[N-1:0] |
 *   | |                               |
 *   | |    Configurable Child         |
 *   | |                               |
 *   | +-------------------------------+
 *
 * Note:
 *  - This function is ONLY applicable to single configurable child case!!!
 *  - This function is applicable to the configurable child in a specific region!!! 
 *********************************************************************/
This function will create nets for the following types of connections:
- Connect the enable signal to the EN of memory module
- Connect the address port to the address port of memory module
- Connect the data_in (Din) to the data_in of the memory module
Note that the top-level module may have multiple regions and
therefore the Din port have multiple pins. The Din of local decoder
should be connected the Din pin indexed by current configuration region



- This function is ONLY applicable to single configurable child case
- This function is applicable to the configurable child in a specific region
This function will create nets for the following types of connections : - Connect the enable signal to the EN of memory module - Connect the address port to the address port of memory module - Connect the data_in ( Din ) to the data_in of the memory module Note that the top - level module may have multiple regions and therefore the Din port have multiple pins . The Din of local decoder should be connected the Din pin indexed by current configuration region - This function is ONLY applicable to single configurable child case - This function is applicable to the configurable child in a specific region
static 
void add_top_module_nets_cmos_memory_frame_short_config_bus(ModuleManager& module_manager,
                                                            const ModuleId& top_module,
                                                            const ConfigRegionId& config_region) {
  std::vector<ModuleId> configurable_children = module_manager.region_configurable_children(top_module, config_region);
  VTR_ASSERT(1 == configurable_children.size());
  ModuleId child_module = configurable_children[0]; 
  size_t child_instance = module_manager.region_configurable_child_instances(top_module, config_region)[0];
  ModulePortId parent_en_port = module_manager.find_module_port(top_module, std::string(DECODER_ENABLE_PORT_NAME));
  ModulePortId child_en_port = module_manager.find_module_port(child_module, std::string(DECODER_ENABLE_PORT_NAME));
  add_module_bus_nets(module_manager, top_module,
                      top_module, 0, parent_en_port,
                      child_module, child_instance, child_en_port);
  ModulePortId parent_addr_port = module_manager.find_module_port(top_module, std::string(DECODER_ADDRESS_PORT_NAME));
  ModulePortId child_addr_port = module_manager.find_module_port(child_module, std::string(DECODER_ADDRESS_PORT_NAME));
  add_module_bus_nets(module_manager, top_module,
                      top_module, 0, parent_addr_port,
                      child_module, child_instance, child_addr_port);
  ModulePortId parent_din_port = module_manager.find_module_port(top_module, std::string(DECODER_DATA_IN_PORT_NAME));
  BasicPort parent_din_port_info = module_manager.module_port(top_module, parent_din_port);
  ModulePortId child_din_port = module_manager.find_module_port(child_module, std::string(DECODER_DATA_IN_PORT_NAME));
  BasicPort child_din_port_info = module_manager.module_port(child_module, child_din_port);
  VTR_ASSERT(size_t(config_region) < parent_din_port_info.get_width());
  VTR_ASSERT(1 == child_din_port_info.get_width());
  ModuleNetId din_net = create_module_source_pin_net(module_manager, top_module, 
                                                     top_module, 0, 
                                                     parent_din_port,
                                                     parent_din_port_info.pins()[size_t(config_region)]);
  VTR_ASSERT(ModuleNetId::INVALID() != din_net);
  module_manager.add_module_net_sink(top_module, din_net, child_module, child_instance, child_din_port, child_din_port_info.pins()[0]);
}
static void add_top_module_nets_cmos_memory_frame_short_config_bus ( ModuleManager & module_manager , const ModuleId & top_module , const ConfigRegionId & config_region ) { std :: vector < ModuleId > configurable_children = module_manager . region_configurable_children ( top_module , config_region ) ; VTR_ASSERT ( 1 == configurable_children . size ( ) ) ; ModuleId child_module = configurable_children [ 0 ] ; size_t child_instance = module_manager . region_configurable_child_instances ( top_module , config_region ) [ 0 ] ; ModulePortId parent_en_port = module_manager . find_module_port ( top_module , std :: string ( DECODER_ENABLE_PORT_NAME ) ) ; ModulePortId child_en_port = module_manager . find_module_port ( child_module , std :: string ( DECODER_ENABLE_PORT_NAME ) ) ; add_module_bus_nets ( module_manager , top_module , top_module , 0 , parent_en_port , child_module , child_instance , child_en_port ) ; ModulePortId parent_addr_port = module_manager . find_module_port ( top_module , std :: string ( DECODER_ADDRESS_PORT_NAME ) ) ; ModulePortId child_addr_port = module_manager . find_module_port ( child_module , std :: string ( DECODER_ADDRESS_PORT_NAME ) ) ; add_module_bus_nets ( module_manager , top_module , top_module , 0 , parent_addr_port , child_module , child_instance , child_addr_port ) ; ModulePortId parent_din_port = module_manager . find_module_port ( top_module , std :: string ( DECODER_DATA_IN_PORT_NAME ) ) ; BasicPort parent_din_port_info = module_manager . module_port ( top_module , parent_din_port ) ; ModulePortId child_din_port = module_manager . find_module_port ( child_module , std :: string ( DECODER_DATA_IN_PORT_NAME ) ) ; BasicPort child_din_port_info = module_manager . module_port ( child_module , child_din_port ) ; VTR_ASSERT ( size_t ( config_region ) < parent_din_port_info . get_width ( ) ) ; VTR_ASSERT ( 1 == child_din_port_info . get_width ( ) ) ; ModuleNetId din_net = create_module_source_pin_net ( module_manager , top_module , top_module , 0 , parent_din_port , parent_din_port_info . pins ( ) [ size_t ( config_region ) ] ) ; VTR_ASSERT ( ModuleNetId :: INVALID ( ) != din_net ) ; module_manager . add_module_net_sink ( top_module , din_net , child_module , child_instance , child_din_port , child_din_port_info . pins ( ) [ 0 ] ) ; }
This function will create nets for the following types of connections:
  - Connect the enable signal to the EN of memory module
  - Connect the address port to the address port of memory module
  - Connect the data_in (Din) to the data_in of the memory module
    Note that the top-level module may have multiple regions and
    therefore the Din port have multiple pins.
This function will create nets for the following types of connections : - Connect the enable signal to the EN of memory module - Connect the address port to the address port of memory module - Connect the data_in ( Din ) to the data_in of the memory module Note that the top - level module may have multiple regions and therefore the Din port have multiple pins .
/* Connect the enable (EN) port of the parent module
   * to the EN port of memory module
   */ /* Connect the address port of the parent module to the child module address port */ /* Connect the data_in (Din) of parent module to the data_in of the memory module
   */ /* Ensure pin indices are in range! */ /* Create a net for the Din[config_region] pin */ /* Configure the net sink */