openfpga/src/fabric/build_lut_modules.cpp
/******************************************************************** 
 * Print Verilog modules for the Look-Up Tables (LUTs) 
 * in the circuit library
 ********************************************************************/
Print Verilog modules for the Look-Up Tables (LUTs)
in the circuit library
Print Verilog modules for the Look - Up Tables ( LUTs ) in the circuit library
void build_lut_modules(ModuleManager& module_manager,
                       const CircuitLibrary& circuit_lib) {
  vtr::ScopedStartFinishTimer timer("Build Look-Up Table (LUT) modules");
  for (const auto& lut_model : circuit_lib.models()) {
    if (CIRCUIT_MODEL_LUT != circuit_lib.model_type(lut_model)) {
      continue;
    }
    if ( (false == circuit_lib.model_verilog_netlist(lut_model).empty())
      || (false == circuit_lib.model_spice_netlist(lut_model).empty()) ) {
      continue;
    }
    build_lut_module(module_manager, circuit_lib, lut_model);
  }
}
void build_lut_modules ( ModuleManager & module_manager , const CircuitLibrary & circuit_lib ) { vtr :: ScopedStartFinishTimer timer ( " " ) ; for ( const auto & lut_model : circuit_lib . models ( ) ) { if ( CIRCUIT_MODEL_LUT != circuit_lib . model_type ( lut_model ) ) { continue ; } if ( ( false == circuit_lib . model_verilog_netlist ( lut_model ) . empty ( ) ) || ( false == circuit_lib . model_spice_netlist ( lut_model ) . empty ( ) ) ) { continue ; } build_lut_module ( module_manager , circuit_lib , lut_model ) ; } }
Print Verilog modules for the Look-Up Tables (LUTs)
 in the circuit library
Print Verilog modules for the Look - Up Tables ( LUTs ) in the circuit library
/* Search for each LUT circuit model */ /* Bypas non-LUT modules */ /* We skip user-defined models */