openfpga/src/base/openfpga_lut_truth_table_fixup.cpp
/********************************************************************
 * Top-level function to fix up the lut truth table results after packing is done
 * The problem comes from a mismatch between the packing results and 
 * original truth tables in users' BLIF file
 * As LUT inputs are equivalent in nature, the router of packer will try
 * to swap the net mapping among these pins so as to achieve best 
 * routing optimization.
 * However, it will cause the original truth table out-of-date when packing is done.
 * This function aims to fix the mess after packing so that the truth table
 * can be synchronized
 *******************************************************************/
Top-level function to fix up the lut truth table results after packing is done
The problem comes from a mismatch between the packing results and
original truth tables in users' BLIF file
As LUT inputs are equivalent in nature, the router of packer will try
to swap the net mapping among these pins so as to achieve best
routing optimization.
However, it will cause the original truth table out-of-date when packing is done.
This function aims to fix the mess after packing so that the truth table
can be synchronized
Top - level function to fix up the lut truth table results after packing is done The problem comes from a mismatch between the packing results and original truth tables in users ' BLIF file As LUT inputs are equivalent in nature the router of packer will try to swap the net mapping among these pins so as to achieve best routing optimization . However it will cause the original truth table out - of - date when packing is done . This function aims to fix the mess after packing so that the truth table can be synchronized
int lut_truth_table_fixup(OpenfpgaContext& openfpga_context,
                          const Command& cmd, const CommandContext& cmd_context) { 
  vtr::ScopedStartFinishTimer timer("Fix up LUT truth tables after packing optimization");
  CommandOptionId opt_verbose = cmd.option("verbose");
  update_lut_tt_with_post_packing_results(g_vpr_ctx.atom(), 
                                          g_vpr_ctx.clustering(),
                                          openfpga_context.mutable_vpr_clustering_annotation(),
                                          cmd_context.option_enable(cmd, opt_verbose));
  return CMD_EXEC_SUCCESS;
}
int lut_truth_table_fixup ( OpenfpgaContext & openfpga_context , const Command & cmd , const CommandContext & cmd_context ) { vtr :: ScopedStartFinishTimer timer ( " " ) ; CommandOptionId opt_verbose = cmd . option ( " " ) ; update_lut_tt_with_post_packing_results ( g_vpr_ctx . atom ( ) , g_vpr_ctx . clustering ( ) , openfpga_context . mutable_vpr_clustering_annotation ( ) , cmd_context . option_enable ( cmd , opt_verbose ) ) ; return CMD_EXEC_SUCCESS ; }
Top-level function to fix up the lut truth table results after packing is done
 The problem comes from a mismatch between the packing results and
 original truth tables in users' BLIF file
 As LUT inputs are equivalent in nature, the router of packer will try
 to swap the net mapping among these pins so as to achieve best
 routing optimization.
Top - level function to fix up the lut truth table results after packing is done The problem comes from a mismatch between the packing results and original truth tables in users ' BLIF file As LUT inputs are equivalent in nature the router of packer will try to swap the net mapping among these pins so as to achieve best routing optimization .
/* Apply fix-up to each packed block */ /* TODO: should identify the error code from internal function execution */