openfpga/src/annotation/annotate_simulation_setting.cpp
/********************************************************************
 * Find the number of clock cycles in simulation based on the average signal density
 *******************************************************************/
Find the number of clock cycles in simulation based on the average signal density
Find the number of clock cycles in simulation based on the average signal density
static 
size_t recommend_num_sim_clock_cycle(const AtomContext& atom_ctx,
                                     const std::unordered_map<AtomNetId, t_net_power>& net_activity, 
                                     const float& sim_window_size) {
  float average_density = average_atom_net_signal_density(atom_ctx, net_activity);
  float average_weighted_density = average_weighted_atom_net_signal_density(atom_ctx, net_activity);
  float median_density = median_atom_net_signal_density(atom_ctx, net_activity);
  VTR_LOG("Average net density: %.2f\n",
          average_density);
  VTR_LOG("Median net density: %.2f\n",
          median_density);
  VTR_LOG("Average net density after weighting: %.2f\n",
          average_weighted_density);
  size_t recmd_num_clock_cycles = 0;
  if ( (0. == median_density) 
    && (0. == average_density) ) {
    recmd_num_clock_cycles = 1;
    VTR_LOG_WARN("All the signal density is zero!\nNumber of clock cycles in simulations are set to be %ld!\n",
                 recmd_num_clock_cycles);
  } else if (0. == average_density) {
    recmd_num_clock_cycles = (size_t)round(1 / median_density); 
  } else if (0. == median_density) {
    recmd_num_clock_cycles = (size_t)round(1 / average_density);
  } else {
    recmd_num_clock_cycles = (size_t)round(1 / (sim_window_size * average_density + (1 - sim_window_size) * median_density ));
    VTR_LOG("Window size set for simulation: %.2f\n",
            sim_window_size);
    VTR_LOG("Net density after applying window size : %.2f\n", 
            (sim_window_size * average_density + (1 - sim_window_size) * median_density));
  }
  VTR_ASSERT(0 < recmd_num_clock_cycles);
  if (MIN_NUM_SIM_OPERATING_CLOCK_CYCLES > recmd_num_clock_cycles) {
    recmd_num_clock_cycles = MIN_NUM_SIM_OPERATING_CLOCK_CYCLES;
  }
  return recmd_num_clock_cycles; 
}
static size_t recommend_num_sim_clock_cycle ( const AtomContext & atom_ctx , const std :: unordered_map < AtomNetId , t_net_power > & net_activity , const float & sim_window_size ) { float average_density = average_atom_net_signal_density ( atom_ctx , net_activity ) ; float average_weighted_density = average_weighted_atom_net_signal_density ( atom_ctx , net_activity ) ; float median_density = median_atom_net_signal_density ( atom_ctx , net_activity ) ; VTR_LOG ( " \n " , average_density ) ; VTR_LOG ( " \n " , median_density ) ; VTR_LOG ( " \n " , average_weighted_density ) ; size_t recmd_num_clock_cycles = 0 ; if ( ( 0. == median_density ) && ( 0. == average_density ) ) { recmd_num_clock_cycles = 1 ; VTR_LOG_WARN ( " \n \n " , recmd_num_clock_cycles ) ; } else if ( 0. == average_density ) { recmd_num_clock_cycles = ( size_t ) round ( 1 / median_density ) ; } else if ( 0. == median_density ) { recmd_num_clock_cycles = ( size_t ) round ( 1 / average_density ) ; } else { recmd_num_clock_cycles = ( size_t ) round ( 1 / ( sim_window_size * average_density + ( 1 - sim_window_size ) * median_density ) ) ; VTR_LOG ( " \n " , sim_window_size ) ; VTR_LOG ( " \n " , ( sim_window_size * average_density + ( 1 - sim_window_size ) * median_density ) ) ; } VTR_ASSERT ( 0 < recmd_num_clock_cycles ) ; if ( MIN_NUM_SIM_OPERATING_CLOCK_CYCLES > recmd_num_clock_cycles ) { recmd_num_clock_cycles = MIN_NUM_SIM_OPERATING_CLOCK_CYCLES ; } return recmd_num_clock_cycles ; }
Find the number of clock cycles in simulation based on the average signal density
Find the number of clock cycles in simulation based on the average signal density
/* We have three choices in selecting the number of clock cycles based on signal density
   * 1. average signal density 
   * 2. median signal density
   * 3. a mixed of average and median signal density 
   */ /* add a sim window size to balance the weight of average density and median density
     * In practice, we find that there could be huge difference between avereage and median values 
     * For a reasonable number of simulation clock cycles, we do this window size.
     */ /* Minimum number of clock cycles should be at least 2
   * so that self-testing testbench can work!!!
   */