openfpga/src/utils/fabric_bitstream_utils.cpp
/********************************************************************
 * Reorganize the fabric bitstream for memory banks
 * by the same address across regions:
 * This is due to that the length of fabric bitstream could be different in each region.
 * Template:
 *   <bl_address> <wl_address> <din_values_from_different_regions>
 * An example:
 *   000000  00000 1011
 *
 * Note: the std::map may cause large memory footprint for large bitstream databases!
 *******************************************************************/
Reorganize the fabric bitstream for memory banks
by the same address across regions:
This is due to that the length of fabric bitstream could be different in each region.

the std::map may cause large memory footprint for large bitstream databases!
Reorganize the fabric bitstream for memory banks by the same address across regions : This is due to that the length of fabric bitstream could be different in each region . the std :: map may cause large memory footprint for large bitstream databases!
std::map<std::pair<std::string, std::string>, std::vector<bool>> build_memory_bank_fabric_bitstream_by_address(const FabricBitstream& fabric_bitstream) {
  std::map<std::pair<std::string, std::string>, std::vector<bool>> fabric_bits_by_addr;
  for (const FabricBitRegionId& region : fabric_bitstream.regions()) {
    for (const FabricBitId& bit_id : fabric_bitstream.region_bits(region)) {
      std::string bl_addr_str;
      for (const char& addr_bit : fabric_bitstream.bit_bl_address(bit_id)) {
        bl_addr_str.push_back(addr_bit);
      }
      std::string wl_addr_str;
      for (const char& addr_bit : fabric_bitstream.bit_wl_address(bit_id)) {
        wl_addr_str.push_back(addr_bit);
      }
      auto result = fabric_bits_by_addr.find(std::make_pair(bl_addr_str, wl_addr_str));
      if (result == fabric_bits_by_addr.end()) {
        fabric_bits_by_addr[std::make_pair(bl_addr_str, wl_addr_str)] = std::vector<bool>(fabric_bitstream.regions().size(), false);
        fabric_bits_by_addr[std::make_pair(bl_addr_str, wl_addr_str)][size_t(region)] = fabric_bitstream.bit_din(bit_id);
      } else {
        VTR_ASSERT_SAFE(result != fabric_bits_by_addr.end());
        result->second[size_t(region)] = fabric_bitstream.bit_din(bit_id);
      }
    }
  }
  return fabric_bits_by_addr;
}
std :: map < std :: pair < std :: string , std :: string > , std :: vector < bool > > build_memory_bank_fabric_bitstream_by_address ( const FabricBitstream & fabric_bitstream ) { std :: map < std :: pair < std :: string , std :: string > , std :: vector < bool > > fabric_bits_by_addr ; for ( const FabricBitRegionId & region : fabric_bitstream . regions ( ) ) { for ( const FabricBitId & bit_id : fabric_bitstream . region_bits ( region ) ) { std :: string bl_addr_str ; for ( const char & addr_bit : fabric_bitstream . bit_bl_address ( bit_id ) ) { bl_addr_str . push_back ( addr_bit ) ; } std :: string wl_addr_str ; for ( const char & addr_bit : fabric_bitstream . bit_wl_address ( bit_id ) ) { wl_addr_str . push_back ( addr_bit ) ; } auto result = fabric_bits_by_addr . find ( std :: make_pair ( bl_addr_str , wl_addr_str ) ) ; if ( result == fabric_bits_by_addr . end ( ) ) { fabric_bits_by_addr [ std :: make_pair ( bl_addr_str , wl_addr_str ) ] = std :: vector < bool > ( fabric_bitstream . regions ( ) . size ( ) , false ) ; fabric_bits_by_addr [ std :: make_pair ( bl_addr_str , wl_addr_str ) ] [ size_t ( region ) ] = fabric_bitstream . bit_din ( bit_id ) ; } else { VTR_ASSERT_SAFE ( result != fabric_bits_by_addr . end ( ) ) ; result -> second [ size_t ( region ) ] = fabric_bitstream . bit_din ( bit_id ) ; } } } return fabric_bits_by_addr ; }
Reorganize the fabric bitstream for memory banks
 by the same address across regions:
 This is due to that the length of fabric bitstream could be different in each region.
Reorganize the fabric bitstream for memory banks by the same address across regions : This is due to that the length of fabric bitstream could be different in each region .
/* Create string for BL address */ /* Create string for WL address */ /* Place the config bit */ /* This is a new bit, resize the vector to the number of regions
         * and deposit '0' to all the bits
         */