10.02_devices/2_src/rx11.cpp
// Access to QBUS/UNIBUS register interface
// called with 100% CPU highest RT priority.
// QBUS/UNIBUS is stopped by SSYN/RPLY while this is running.
// No loops! no drive, console, file or other operations!
// QBUS/UNIBUS DATO cycles let dati_flipflops "flicker" outside of this proc:
//      do not read back dati_flipflops.
Access to QBUS/UNIBUS register interface
called with 100% CPU highest RT priority.
QBUS/UNIBUS is stopped by SSYN/RPLY while this is running.
No loops. no drive, console, file or other operations.
QBUS/UNIBUS DATO cycles let dati_flipflops "flicker" outside of this proc:
do not read back dati_flipflops.
Access to QBUS / UNIBUS register interface called with 100% CPU highest RT priority . QBUS / UNIBUS is stopped by SSYN / RPLY while this is running . No loops . no drive console file or other operations . QBUS / UNIBUS DATO cycles let dati_flipflops " flicker " outside of this proc : do not read back dati_flipflops .
void RX11_c::on_after_register_access(qunibusdevice_register_t *device_reg,
                                      uint8_t qunibus_control) {
    switch (device_reg->index) {
    case 0:  
        if (qunibus_control == QUNIBUS_CYCLE_DATO) {
            pthread_mutex_lock(&on_after_register_access_mutex);
            uCPU->signal_selected_drive_unitno = (busreg_RXCS->active_dato_flipflops >> 4) & 1;
            uCPU->signal_function_code = (busreg_RXCS->active_dato_flipflops >> 1) & 0x07;
            interrupt_enable = !!(busreg_RXCS->active_dato_flipflops & (1 << 6));
            uCPU->signal_function_density = (busreg_RXCS->active_dato_flipflops >> 8) & 1;
            uCPU->rxdb = 0 ;
            if ((busreg_RXCS->active_dato_flipflops >> 14) & 1) { 
                uCPU->init() ;
            } else if (uCPU->signal_done && busreg_RXCS->active_dato_flipflops & 1) { 
                uCPU->go() ; 
            } else
                update_status("on_after_register_access() -> update_status") ; 
            pthread_mutex_unlock(&on_after_register_access_mutex);
        } else {
        }
        break;
    case 1:  
        if (qunibus_control == QUNIBUS_CYCLE_DATI) {
            uCPU->rxdb_after_read() ;
        } else if (qunibus_control == QUNIBUS_CYCLE_DATO) {
            uint16_t w  = get_register_dato_value(busreg_RXDB);
            uCPU->rxdb_after_write(w) ;
        }
        break ;
    default: ; 
    }
}
void RX11_c :: on_after_register_access ( qunibusdevice_register_t * device_reg , uint8_t qunibus_control ) { switch ( device_reg -> index ) { case 0 : if ( qunibus_control == QUNIBUS_CYCLE_DATO ) { pthread_mutex_lock ( & on_after_register_access_mutex ) ; uCPU -> signal_selected_drive_unitno = ( busreg_RXCS -> active_dato_flipflops >> 4 ) & 1 ; uCPU -> signal_function_code = ( busreg_RXCS -> active_dato_flipflops >> 1 ) & 0x07 ; interrupt_enable = ! ! ( busreg_RXCS -> active_dato_flipflops & ( 1 << 6 ) ) ; uCPU -> signal_function_density = ( busreg_RXCS -> active_dato_flipflops >> 8 ) & 1 ; uCPU -> rxdb = 0 ; if ( ( busreg_RXCS -> active_dato_flipflops >> 14 ) & 1 ) { uCPU -> init ( ) ; } else if ( uCPU -> signal_done && busreg_RXCS -> active_dato_flipflops & 1 ) { uCPU -> go ( ) ; } else update_status ( " " ) ; pthread_mutex_unlock ( & on_after_register_access_mutex ) ; } else { } break ; case 1 : if ( qunibus_control == QUNIBUS_CYCLE_DATI ) { uCPU -> rxdb_after_read ( ) ; } else if ( qunibus_control == QUNIBUS_CYCLE_DATO ) { uint16_t w = get_register_dato_value ( busreg_RXDB ) ; uCPU -> rxdb_after_write ( w ) ; } break ; default : ; } }
Access to QBUS/UNIBUS register interface
called with 100% CPU highest RT priority.
Access to QBUS / UNIBUS register interface called with 100% CPU highest RT priority .
// on drive select: // move  status of new drive to controller status register // on command: signal worker thread // RXCS //GPIO_SETVAL(gpios.led[0], 1); // inverted, led OFF // Not clear, which bits may be written when DONE=0 (busy) // "go" disabled // RX11 DX.MAC: sets INT enable while INIT active // INIT interrupts GO ? // But: Changes of Unit select" while CPU active??" // write only allowed if RX02 is not busy // if (! uCPU->signal_done) //    break; // ignore write // CS<4> = drive select, write only, forwad to uCPU // CS<1:3> is cmd, write only // CS<6> is IE // write to RXCS clears RXDB? // Only reference: AH-9341F-MC__RX11__RX11_INTFC__CZRXBF0__(C)74-79.pdf, line #916 //set_register_dati_value(busreg_RXDB, 0, __func__); // INIT bit // GO bit // execute uCPU.function_code // register status NOT updated via uCPU activity // may trigger interrupt // CS reg is not "active_on_dati" //  set value in code with "set_register_dati_value(reg_CS, CS_read) ;" // AFTER access to RXDB, multifunction // read from data port to RXDB // read moves next byte to rxdb // has read current value of rxdb, now deliver next via // on_uCPU_status_changed() to rxdb, calling //  set_register_dati_value(busreg_RXDB, w, __func__); // write RXDB to data port // ignore write