openfpga/src/utils/memory_utils.cpp
/*********************************************************************
 * Update the LSB and MSB of a configuration bus based on the number of 
 * memory bits of a ReRAM memory module. 
 **********************************************************************/
Update the LSB and MSB of a configuration bus based on the number of
memory bits of a ReRAM memory module.
Update the LSB and MSB of a configuration bus based on the number of memory bits of a ReRAM memory module .
static 
void update_rram_mem_module_config_bus(const e_config_protocol_type& sram_orgz_type,
                                       BasicPort& config_bus) {
  switch (sram_orgz_type) {
  case CONFIG_MEM_STANDALONE:
    break;
  case CONFIG_MEM_SCAN_CHAIN:
    VTR_ASSERT(true == config_bus.rotate(1));
    break;
  case CONFIG_MEM_MEMORY_BANK:
    VTR_ASSERT(true == config_bus.rotate(1));
    break;
  default:
    VTR_LOG_ERROR("Invalid type of SRAM organization!\n");
    exit(1);
  }
}
static void update_rram_mem_module_config_bus ( const e_config_protocol_type & sram_orgz_type , BasicPort & config_bus ) { switch ( sram_orgz_type ) { case CONFIG_MEM_STANDALONE : break ; case CONFIG_MEM_SCAN_CHAIN : VTR_ASSERT ( true == config_bus . rotate ( 1 ) ) ; break ; case CONFIG_MEM_MEMORY_BANK : VTR_ASSERT ( true == config_bus . rotate ( 1 ) ) ; break ; default : VTR_LOG_ERROR ( " \n " ) ; exit ( 1 ) ; } }
Update the LSB and MSB of a configuration bus based on the number of
 memory bits of a ReRAM memory module.
Update the LSB and MSB of a configuration bus based on the number of memory bits of a ReRAM memory module .
/* Not supported */ /* Scan-chain of a memory module only has a head and a tail.
     * LSB and MSB of configuration bus will be shifted to the next head. 
     * TODO: this may be changed later!!!
     */ /* In this case, a memory module contains unique BL/WL or BLB/WLB,
     * which are not shared with other modules   
     * TODO: this may be changed later!!!
     */