gowin/arch.cc
// Add all MUXes for the cell
Add all MUXes for the cell
Add all MUXes for the cell
void Arch::addMuxBels(const DatabasePOD *db, int row, int col)
{
    IdString belname, bel_id;
    char buf[40];
    int z;
    struct
    {
        char type;         
        char bel_idx;      
        char in_prefix[2]; 
        char in_idx[2];    
    } const mux_names[] = {{'5', '0', "", {'0', '1'}},  {'6', '0', "O", {'2', '0'}}, {'5', '1', "", {'2', '3'}},
                           {'7', '0', "O", {'5', '1'}}, {'5', '2', "", {'4', '5'}},  {'6', '1', "O", {'6', '4'}},
                           {'5', '3', "", {'6', '7'}},  {'8', '0', "O", {'3', '3'}}};
    for (int j = 0; j < 8; ++j) {
        z = j + mux_0_z;
        int grow = row + 1;
        int gcol = col + 1;
        if (j == 7 && col == getGridDimX() - 2) {
            continue;
        }
        snprintf(buf, 40, "R%dC%d_MUX2_LUT%c%c", grow, gcol, mux_names[j].type, mux_names[j].bel_idx);
        belname = id(buf);
        snprintf(buf, 40, "GW_MUX2_LUT%c", mux_names[j].type);
        bel_id = id(buf);
        addBel(belname, bel_id, Loc(col, row, z), false);
        snprintf(buf, 40, "I0MUX%d", j);
        IdString id_wire_i0 = id(buf);
        IdString wire_i0_name = wireToGlobal(row, col, db, id_wire_i0);
        addWire(wire_i0_name, id_wire_i0, col, row);
        snprintf(buf, 40, "I1MUX%d", j);
        IdString id_wire_i1 = id(buf);
        IdString wire_i1_name = wireToGlobal(row, col, db, id_wire_i1);
        addWire(wire_i1_name, id_wire_i1, col, row);
        DelayQuad delay = getWireTypeDelay(id_I0);
        snprintf(buf, 40, "%sF%c", mux_names[j].in_prefix, mux_names[j].in_idx[1]);
        IdString id_src_F = id(buf);
        IdString src_F = wireToGlobal(row, col, db, id_src_F);
        snprintf(buf, 40, "R%dC%d_%s_DUMMY_%s", grow, gcol, id_src_F.c_str(this), id_wire_i1.c_str(this));
        addPip(id(buf), id_wire_i1, src_F, wire_i1_name, delay, Loc(col, row, 0));
        snprintf(buf, 40, "%sF%c", mux_names[j].in_prefix, mux_names[j].in_idx[0]);
        id_src_F = id(buf);
        int src_col = col;
        if (j == 7) {
            ++src_col;
            delay = getWireTypeDelay(id_I01);
        }
        src_F = wireToGlobal(row, src_col, db, id_src_F);
        snprintf(buf, 40, "R%dC%d_%s_DUMMY_%s", grow, gcol, id_src_F.c_str(this), id_wire_i0.c_str(this));
        addPip(id(buf), id_wire_i0, src_F, wire_i0_name, delay, Loc(col, row, 0));
        snprintf(buf, 40, "R%dC%d_OF%d", grow, gcol, j);
        addBelOutput(belname, id_OF, id(buf));
        snprintf(buf, 40, "R%dC%d_SEL%d", grow, gcol, j);
        addBelInput(belname, id_SEL, id(buf));
        snprintf(buf, 40, "R%dC%d_I0MUX%d", grow, gcol, j);
        addBelInput(belname, id_I0, id(buf));
        snprintf(buf, 40, "R%dC%d_I1MUX%d", grow, gcol, j);
        addBelInput(belname, id_I1, id(buf));
    }
}
void Arch :: addMuxBels ( const DatabasePOD * db , int row , int col ) { IdString belname , bel_id ; char buf [ 40 ] ; int z ; struct { char type ; char bel_idx ; char in_prefix [ 2 ] ; char in_idx [ 2 ] ; } const mux_names [ ] = { { ' ' , ' ' , " " , { ' ' , ' ' } } , { ' ' , ' ' , " " , { ' ' , ' ' } } , { ' ' , ' ' , " " , { ' ' , ' ' } } , { ' ' , ' ' , " " , { ' ' , ' ' } } , { ' ' , ' ' , " " , { ' ' , ' ' } } , { ' ' , ' ' , " " , { ' ' , ' ' } } , { ' ' , ' ' , " " , { ' ' , ' ' } } , { ' ' , ' ' , " " , { ' ' , ' ' } } } ; for ( int j = 0 ; j < 8 ; ++ j ) { z = j + mux_0_z ; int grow = row + 1 ; int gcol = col + 1 ; if ( j == 7 && col == getGridDimX ( ) - 2 ) { continue ; } snprintf ( buf , 40 , " " , grow , gcol , mux_names [ j ] . type , mux_names [ j ] . bel_idx ) ; belname = id ( buf ) ; snprintf ( buf , 40 , " " , mux_names [ j ] . type ) ; bel_id = id ( buf ) ; addBel ( belname , bel_id , Loc ( col , row , z ) , false ) ; snprintf ( buf , 40 , " " , j ) ; IdString id_wire_i0 = id ( buf ) ; IdString wire_i0_name = wireToGlobal ( row , col , db , id_wire_i0 ) ; addWire ( wire_i0_name , id_wire_i0 , col , row ) ; snprintf ( buf , 40 , " " , j ) ; IdString id_wire_i1 = id ( buf ) ; IdString wire_i1_name = wireToGlobal ( row , col , db , id_wire_i1 ) ; addWire ( wire_i1_name , id_wire_i1 , col , row ) ; DelayQuad delay = getWireTypeDelay ( id_I0 ) ; snprintf ( buf , 40 , " " , mux_names [ j ] . in_prefix , mux_names [ j ] . in_idx [ 1 ] ) ; IdString id_src_F = id ( buf ) ; IdString src_F = wireToGlobal ( row , col , db , id_src_F ) ; snprintf ( buf , 40 , " " , grow , gcol , id_src_F . c_str ( this ) , id_wire_i1 . c_str ( this ) ) ; addPip ( id ( buf ) , id_wire_i1 , src_F , wire_i1_name , delay , Loc ( col , row , 0 ) ) ; snprintf ( buf , 40 , " " , mux_names [ j ] . in_prefix , mux_names [ j ] . in_idx [ 0 ] ) ; id_src_F = id ( buf ) ; int src_col = col ; if ( j == 7 ) { ++ src_col ; delay = getWireTypeDelay ( id_I01 ) ; } src_F = wireToGlobal ( row , src_col , db , id_src_F ) ; snprintf ( buf , 40 , " " , grow , gcol , id_src_F . c_str ( this ) , id_wire_i0 . c_str ( this ) ) ; addPip ( id ( buf ) , id_wire_i0 , src_F , wire_i0_name , delay , Loc ( col , row , 0 ) ) ; snprintf ( buf , 40 , " " , grow , gcol , j ) ; addBelOutput ( belname , id_OF , id ( buf ) ) ; snprintf ( buf , 40 , " " , grow , gcol , j ) ; addBelInput ( belname , id_SEL , id ( buf ) ) ; snprintf ( buf , 40 , " " , grow , gcol , j ) ; addBelInput ( belname , id_I0 , id ( buf ) ) ; snprintf ( buf , 40 , " " , grow , gcol , j ) ; addBelInput ( belname , id_I1 , id ( buf ) ) ; } }
Add all MUXes for the cell
Add all MUXes for the cell
// make all wide luts with these parameters // MUX type 5,6,7,8 // just bel name suffix // input from F or OF // input from bel with idx // 4 MUX2_LUT5, 2 MUX2_LUT6, 1 MUX2_LUT7, 1 MUX2_LUT8 // no MUX2_LUT8 in the last column // bel // dummy wires // dummy right pip // dummy left pip // LUT8's I0 is wired to the right cell // the MUX ports