openfpga/src/fabric/build_mux_modules.cpp
/***********************************************
 * Generate Verilog codes modeling an branch circuit 
 * for a multiplexer with the given size 
 **********************************************/
Generate Verilog codes modeling an branch circuit
for a multiplexer with the given size
Generate Verilog codes modeling an branch circuit for a multiplexer with the given size
static 
void build_mux_branch_module(ModuleManager& module_manager,
                             const CircuitLibrary& circuit_lib, 
                             const CircuitModelId& mux_model, 
                             const MuxGraph& mux_graph) {
  std::string module_name = generate_mux_branch_subckt_name(circuit_lib, mux_model, mux_graph.num_inputs(), mux_graph.num_memory_bits(), MUX_BASIS_MODULE_POSTFIX);
  if (module_manager.valid_module_id(module_manager.find_module(module_name))) {
    return;
  }
  switch (circuit_lib.design_tech_type(mux_model)) {
  case CIRCUIT_MODEL_DESIGN_CMOS:
    build_cmos_mux_branch_module(module_manager, circuit_lib, mux_model, module_name, mux_graph);
    break;
  case CIRCUIT_MODEL_DESIGN_RRAM:
    build_rram_mux_branch_module(module_manager, circuit_lib, mux_model, module_name, mux_graph);
    break;
  default:
    VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid design technology of multiplexer '%s'\n",
                  circuit_lib.model_name(mux_model).c_str()); 
    exit(1);
  }
}
static void build_mux_branch_module ( ModuleManager & module_manager , const CircuitLibrary & circuit_lib , const CircuitModelId & mux_model , const MuxGraph & mux_graph ) { std :: string module_name = generate_mux_branch_subckt_name ( circuit_lib , mux_model , mux_graph . num_inputs ( ) , mux_graph . num_memory_bits ( ) , MUX_BASIS_MODULE_POSTFIX ) ; if ( module_manager . valid_module_id ( module_manager . find_module ( module_name ) ) ) { return ; } switch ( circuit_lib . design_tech_type ( mux_model ) ) { case CIRCUIT_MODEL_DESIGN_CMOS : build_cmos_mux_branch_module ( module_manager , circuit_lib , mux_model , module_name , mux_graph ) ; break ; case CIRCUIT_MODEL_DESIGN_RRAM : build_rram_mux_branch_module ( module_manager , circuit_lib , mux_model , module_name , mux_graph ) ; break ; default : VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " , circuit_lib . model_name ( mux_model ) . c_str ( ) ) ; exit ( 1 ) ; } }
Generate Verilog codes modeling an branch circuit
 for a multiplexer with the given size
Generate Verilog codes modeling an branch circuit for a multiplexer with the given size
/* Skip the module building if it is already there */ /* Multiplexers built with different technology is in different organization */