pic32/libraries/SoftSPI/SoftSPI.cpp
/* ------------------------------------------------------------ */
/***	SoftSPI::transfer
**
**	Parameters:
**		bVal		- byte to transfer to the SPI slave device
**
**	Return Value:
**		Returns byte received from the slave
**
**	Errors:
**		none
**
**	Description:
**		Send the specified byte to the slave and return the byte
**		received from the slave.
*/
:transfer

bVal            - byte to transfer to the SPI slave device

Return Value:
Returns byte received from the slave

none

Send the specified byte to the slave and return the byte
received from the slave.
: transfer bVal - byte to transfer to the SPI slave device Return Value : Returns byte received from the slave none Send the specified byte to the slave and return the byte received from the slave .
uint8_t
SoftSPI::transfer(uint8_t bVal) {
	int				cbit;
	uint8_t			bOut;
	uint8_t			bIn = 0;
	bOut = bVal;
	switch(modCur) {
		case 0:		
			for (cbit = 0; cbit < 8; cbit++) {
				if ((bOut & 0x80) != 0) {
					iopMOSI->lat.set = bitMOSI;
				}
				else {
					iopMOSI->lat.clr = bitMOSI;
				}
				bOut <<= 1;
                waitCoreTime(cntClk);
				iopSCK->lat.set = bitSCK;
				bIn = (bIn << 1) | ((iopMISO->port.reg & bitMISO) == 0 ? 0 : 1);
                waitCoreTime(cntClk);
				iopSCK->lat.clr = bitSCK;
			}
			break;
		case 1:		
			for (cbit = 0; cbit < 8; cbit++) {
				if ((bOut & 0x01) != 0) {
					iopMOSI->lat.set = bitMOSI;
				}
				else {
					iopMOSI->lat.clr = bitMOSI;
				}
				bOut >>= 1;
                waitCoreTime(cntClk);
				iopSCK->lat.set = bitSCK;
				bIn = (bIn >> 1) | ((iopMISO->port.reg & bitMISO) == 0 ? 0 : 0x80);
                waitCoreTime(cntClk);
				iopSCK->lat.clr = bitSCK;
			}
			break;
		case 2:		
			for (cbit = 0; cbit < 8; cbit++) {
				iopSCK->lat.set = bitSCK;
				if ((bOut & 0x80) != 0) {
					iopMOSI->lat.set = bitMOSI;
				}
				else {
					iopMOSI->lat.clr = bitMOSI;
				}
				bOut <<= 1;
                waitCoreTime(cntClk);
				iopSCK->lat.clr = bitSCK;
				bIn = (bIn << 1) | ((iopMISO->port.reg & bitMISO) == 0 ? 0 : 1);
                waitCoreTime(cntClk);
			}
			break;
		case 3:		
			for (cbit = 0; cbit < 8; cbit++) {
				iopSCK->lat.set = bitSCK;
				if ((bOut & 0x01) != 0) {
					iopMOSI->lat.set = bitMOSI;
				}
				else {
					iopMOSI->lat.clr = bitMOSI;
				}
				bOut >>= 1;
                waitCoreTime(cntClk);
				iopSCK->lat.clr = bitSCK;
				bIn = (bIn >> 1) | ((iopMISO->port.reg & bitMISO) == 0 ? 0 : 0x80);
                waitCoreTime(cntClk);
			}
			break;
		case 4:		
			for (cbit = 0; cbit < 8; cbit++) {
				if ((bOut & 0x80) != 0) {
					iopMOSI->lat.set = bitMOSI;
				}
				else {
					iopMOSI->lat.clr = bitMOSI;
				}
				bOut <<= 1;
                waitCoreTime(cntClk);
				iopSCK->lat.clr = bitSCK;
				bIn = (bIn << 1) | ((iopMISO->port.reg & bitMISO) == 0 ? 0 : 1);
                waitCoreTime(cntClk);
				iopSCK->lat.set = bitSCK;
			}
			break;
		case 5:		
			for (cbit = 0; cbit < 8; cbit++) {
				if ((bOut & 0x01) != 0) {
					iopMOSI->lat.set = bitMOSI;
				}
				else {
					iopMOSI->lat.clr = bitMOSI;
				}
				bOut >>= 1;
                waitCoreTime(cntClk);
				iopSCK->lat.clr = bitSCK;
				bIn = (bIn >> 1) | ((iopMISO->port.reg & bitMISO) == 0 ? 0 : 0x80);
                waitCoreTime(cntClk);
				iopSCK->lat.set = bitSCK;
			}
			break;
		case 6:		
			for (cbit = 0; cbit < 8; cbit++) {
				iopSCK->lat.clr = bitSCK;
				if ((bOut & 0x80) != 0) {
					iopMOSI->lat.set = bitMOSI;
				}
				else {
					iopMOSI->lat.clr = bitMOSI;
				}
				bOut <<= 1;
                waitCoreTime(cntClk);
				iopSCK->lat.set = bitSCK;
				bIn = (bIn << 1) | ((iopMISO->port.reg & bitMISO) == 0 ? 0 : 1);
                waitCoreTime(cntClk);
			}
			break;
		case 7:		
			for (cbit = 0; cbit < 8; cbit++) {
				iopSCK->lat.clr = bitSCK;
				if ((bOut & 0x01) != 0) {
					iopMOSI->lat.set = bitMOSI;
				}
				else {
					iopMOSI->lat.clr = bitMOSI;
				}
				bOut >>= 1;
                waitCoreTime(cntClk);
				iopSCK->lat.set = bitSCK;
				bIn = (bIn >> 1) | ((iopMISO->port.reg & bitMISO) == 0 ? 0 : 0x80);
                waitCoreTime(cntClk);
			}
			break;
	}
	return	bIn;
}
uint8_t SoftSPI :: transfer ( uint8_t bVal ) { int cbit ; uint8_t bOut ; uint8_t bIn = 0 ; bOut = bVal ; switch ( modCur ) { case 0 : for ( cbit = 0 ; cbit < 8 ; cbit ++ ) { if ( ( bOut & 0x80 ) != 0 ) { iopMOSI -> lat . set = bitMOSI ; } else { iopMOSI -> lat . clr = bitMOSI ; } bOut <<= 1 ; waitCoreTime ( cntClk ) ; iopSCK -> lat . set = bitSCK ; bIn = ( bIn << 1 ) | ( ( iopMISO -> port . reg & bitMISO ) == 0 ? 0 : 1 ) ; waitCoreTime ( cntClk ) ; iopSCK -> lat . clr = bitSCK ; } break ; case 1 : for ( cbit = 0 ; cbit < 8 ; cbit ++ ) { if ( ( bOut & 0x01 ) != 0 ) { iopMOSI -> lat . set = bitMOSI ; } else { iopMOSI -> lat . clr = bitMOSI ; } bOut >>= 1 ; waitCoreTime ( cntClk ) ; iopSCK -> lat . set = bitSCK ; bIn = ( bIn >> 1 ) | ( ( iopMISO -> port . reg & bitMISO ) == 0 ? 0 : 0x80 ) ; waitCoreTime ( cntClk ) ; iopSCK -> lat . clr = bitSCK ; } break ; case 2 : for ( cbit = 0 ; cbit < 8 ; cbit ++ ) { iopSCK -> lat . set = bitSCK ; if ( ( bOut & 0x80 ) != 0 ) { iopMOSI -> lat . set = bitMOSI ; } else { iopMOSI -> lat . clr = bitMOSI ; } bOut <<= 1 ; waitCoreTime ( cntClk ) ; iopSCK -> lat . clr = bitSCK ; bIn = ( bIn << 1 ) | ( ( iopMISO -> port . reg & bitMISO ) == 0 ? 0 : 1 ) ; waitCoreTime ( cntClk ) ; } break ; case 3 : for ( cbit = 0 ; cbit < 8 ; cbit ++ ) { iopSCK -> lat . set = bitSCK ; if ( ( bOut & 0x01 ) != 0 ) { iopMOSI -> lat . set = bitMOSI ; } else { iopMOSI -> lat . clr = bitMOSI ; } bOut >>= 1 ; waitCoreTime ( cntClk ) ; iopSCK -> lat . clr = bitSCK ; bIn = ( bIn >> 1 ) | ( ( iopMISO -> port . reg & bitMISO ) == 0 ? 0 : 0x80 ) ; waitCoreTime ( cntClk ) ; } break ; case 4 : for ( cbit = 0 ; cbit < 8 ; cbit ++ ) { if ( ( bOut & 0x80 ) != 0 ) { iopMOSI -> lat . set = bitMOSI ; } else { iopMOSI -> lat . clr = bitMOSI ; } bOut <<= 1 ; waitCoreTime ( cntClk ) ; iopSCK -> lat . clr = bitSCK ; bIn = ( bIn << 1 ) | ( ( iopMISO -> port . reg & bitMISO ) == 0 ? 0 : 1 ) ; waitCoreTime ( cntClk ) ; iopSCK -> lat . set = bitSCK ; } break ; case 5 : for ( cbit = 0 ; cbit < 8 ; cbit ++ ) { if ( ( bOut & 0x01 ) != 0 ) { iopMOSI -> lat . set = bitMOSI ; } else { iopMOSI -> lat . clr = bitMOSI ; } bOut >>= 1 ; waitCoreTime ( cntClk ) ; iopSCK -> lat . clr = bitSCK ; bIn = ( bIn >> 1 ) | ( ( iopMISO -> port . reg & bitMISO ) == 0 ? 0 : 0x80 ) ; waitCoreTime ( cntClk ) ; iopSCK -> lat . set = bitSCK ; } break ; case 6 : for ( cbit = 0 ; cbit < 8 ; cbit ++ ) { iopSCK -> lat . clr = bitSCK ; if ( ( bOut & 0x80 ) != 0 ) { iopMOSI -> lat . set = bitMOSI ; } else { iopMOSI -> lat . clr = bitMOSI ; } bOut <<= 1 ; waitCoreTime ( cntClk ) ; iopSCK -> lat . set = bitSCK ; bIn = ( bIn << 1 ) | ( ( iopMISO -> port . reg & bitMISO ) == 0 ? 0 : 1 ) ; waitCoreTime ( cntClk ) ; } break ; case 7 : for ( cbit = 0 ; cbit < 8 ; cbit ++ ) { iopSCK -> lat . clr = bitSCK ; if ( ( bOut & 0x01 ) != 0 ) { iopMOSI -> lat . set = bitMOSI ; } else { iopMOSI -> lat . clr = bitMOSI ; } bOut >>= 1 ; waitCoreTime ( cntClk ) ; iopSCK -> lat . set = bitSCK ; bIn = ( bIn >> 1 ) | ( ( iopMISO -> port . reg & bitMISO ) == 0 ? 0 : 0x80 ) ; waitCoreTime ( cntClk ) ; } break ; } return bIn ; }
SoftSPI::transfer
SoftSPI :: transfer
/* Transfer control to the case that handles the current
	** combination of SPI mode and shift direction. The shift
	** direction is in bit 0 and the SPI mode is in bits 2 & 3.
	**
	** SPI mode 0 & 2 - sample on leading edge of clock, shift on trailing edge
	** SPI mode 1 & 3 - shift on leading edge of clock, sample on trailing edge
	**
	** SPI mode 0 - clock idles low, sample on rising edge
	** SPI mode 1 - clock idles low, sample on falling edge
	** SPI mode 2 - clock idles high, sample on falling edge
	** SPI mode 3 - clock idles high, sample on rising edge
	*/ // SPI mode 0, shift left /* Set MOSI to the appropriate state.
				*/ /* Wait for half the clock period.
				*/ /* Set the leading edge of the clock.
				*/ /* Sample the state of the MISO pin.
				*/ /* Wait for half the clock period.
				*/ /* Set the trailing edge of the clock
				*/ // SPI MODE 0, shift right /* Set MOSI to the appropriate state.
				*/ /* Wait for half the clock period.
				*/ /* Set the leading edge of the clock.
				*/ /* Sample the state of the MISO pin.
				*/ /* Wait for half the clock period.
				*/ /* Set the trailing edge of the clock
				*/ // SPI MODE 1, shift left /* Set the leading edge of the clock.
				*/ /* Set MOSI to the appropriate state.
				*/ /* Wait for half the clock period.
				*/ /* Set the trailing edge of the clock
				*/ /* Sample the state of the MISO pin.
				*/ /* Wait for half the clock period.
				*/ // SPI mode 1, shift right /* Set the leading edge of the clock.
				*/ /* Set MOSI to the appropriate state.
				*/ /* Wait for half the clock period.
				*/ /* Set the trailing edge of the clock
				*/ /* Sample the state of the MISO pin.
				*/ /* Wait for half the clock period.
				*/ //SPI mode 2, shift left /* Set MOSI to the appropriate state.
				*/ /* Wait for half the clock period.
				*/ /* Set the leading edge of the clock.
				*/ /* Sample the state of the MISO pin.
				*/ /* Wait for half the clock period.
				*/ /* Set the trailing edge of the clock
				*/ //SPI mode 2, shift right /* Set MOSI to the appropriate state.
				*/ /* Wait for half the clock period.
				*/ /* Set the leading edge of the clock.
				*/ /* Sample the state of the MISO pin.
				*/ /* Wait for half the clock period.
				*/ /* Set the trailing edge of the clock
				*/ //SPI mode 3, shift left /* Set the leading edge of the clock.
				*/ /* Set MOSI to the appropriate state.
				*/ /* Wait for half the clock period.
				*/ /* Set the trailing edge of the clock
				*/ /* Sample the state of the MISO pin.
				*/ /* Wait for half the clock period.
				*/ //SPI mode 3, shift right /* Set the leading edge of the clock.
				*/ /* Set MOSI to the appropriate state.
				*/ /* Wait for half the clock period.
				*/ /* Set the trailing edge of the clock
				*/ /* Sample the state of the MISO pin.
				*/ /* Wait for half the clock period.
				*/