openfpga/src/fabric/build_routing_module_utils.cpp
/*********************************************************************
 * Generate an input port for routing multiplexer inside the switch block
 * In addition to give the Routing Resource node of the input
 * Users should provide the side of input, which is different case by case:
 * 1. When the input is a pin of a CLB/Logic Block, the input_side should
 *    be the side of the node on its grid!
 *    For example, the input pin is on the top side of a switch block
 *    but on the right side of a switch block
 *                      +--------+
 *                      |        |
 *                      |  Grid  |---+
 *                      |        |   |
 *                      +--------+   v input_pin
 *                      +----------------+
 *                      |  Switch Block  |
 *                      +----------------+
 * 2. When the input is a routing track, the input_side should be
 *    the side of the node locating on the switch block
 ********************************************************************/
Generate an input port for routing multiplexer inside the switch block
In addition to give the Routing Resource node of the input
Users should provide the side of input, which is different case by case:
1. When the input is a pin of a CLB/Logic Block, the input_side should
be the side of the node on its grid.
Generate an input port for routing multiplexer inside the switch block In addition to give the Routing Resource node of the input Users should provide the side of input which is different case by case : 1 . When the input is a pin of a CLB / Logic Block the input_side should be the side of the node on its grid .
ModulePinInfo find_switch_block_module_input_port(const ModuleManager& module_manager,
                                                  const ModuleId& sb_module, 
                                                  const RRGraph& rr_graph,
                                                  const RRGSB& rr_gsb, 
                                                  const e_side& input_side,
                                                  const RRNodeId& input_rr_node) {
  ModulePinInfo input_port(ModulePortId::INVALID(), 0);
  switch (rr_graph.node_type(input_rr_node)) {
  case OPIN: {
    vtr::Point<size_t> input_port_coord(rr_graph.node_xlow(input_rr_node),
                                        rr_graph.node_ylow(input_rr_node));
    enum e_side grid_pin_side = rr_graph.node_side(input_rr_node);
    VTR_ASSERT(NUM_SIDES != grid_pin_side);
    std::string input_port_name = generate_sb_module_grid_port_name(input_side,
                                                                    grid_pin_side,
                                                                    rr_graph.node_pin_num(input_rr_node)); 
    input_port.first = module_manager.find_module_port(sb_module, input_port_name); 
    VTR_ASSERT(true == module_manager.valid_module_port_id(sb_module, input_port.first));
    break;
  }
  case CHANX:
  case CHANY: {
    input_port = find_switch_block_module_chan_port(module_manager, sb_module, rr_graph, 
                                                    rr_gsb, input_side, input_rr_node, IN_PORT);
    break;
  }
  default: 
    VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n");
    exit(1);
  }
  return input_port; 
}
ModulePinInfo find_switch_block_module_input_port ( const ModuleManager & module_manager , const ModuleId & sb_module , const RRGraph & rr_graph , const RRGSB & rr_gsb , const e_side & input_side , const RRNodeId & input_rr_node ) { ModulePinInfo input_port ( ModulePortId :: INVALID ( ) , 0 ) ; switch ( rr_graph . node_type ( input_rr_node ) ) { case OPIN : { vtr :: Point < size_t > input_port_coord ( rr_graph . node_xlow ( input_rr_node ) , rr_graph . node_ylow ( input_rr_node ) ) ; enum e_side grid_pin_side = rr_graph . node_side ( input_rr_node ) ; VTR_ASSERT ( NUM_SIDES != grid_pin_side ) ; std :: string input_port_name = generate_sb_module_grid_port_name ( input_side , grid_pin_side , rr_graph . node_pin_num ( input_rr_node ) ) ; input_port . first = module_manager . find_module_port ( sb_module , input_port_name ) ; VTR_ASSERT ( true == module_manager . valid_module_port_id ( sb_module , input_port . first ) ) ; break ; } case CHANX : case CHANY : { input_port = find_switch_block_module_chan_port ( module_manager , sb_module , rr_graph , rr_gsb , input_side , input_rr_node , IN_PORT ) ; break ; } default : VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " ) ; exit ( 1 ) ; } return input_port ; }
Generate an input port for routing multiplexer inside the switch block
 In addition to give the Routing Resource node of the input
 Users should provide the side of input, which is different case by case:
 1.
Generate an input port for routing multiplexer inside the switch block In addition to give the Routing Resource node of the input Users should provide the side of input which is different case by case : 1 .
/* Deposit an invalid value */ /* Generate the input port object */ /* case SOURCE: */ /* Find the coordinator (grid_x and grid_y) for the input port */ /* Find the side where the grid pin locates in the grid */ /* Must find a valid port id in the Switch Block module */ /* SOURCE, IPIN, SINK are invalid*/