openfpga/src/fabric/build_top_module_memory.cpp
/********************************************************************
 * Connect all the memory modules under the parent module in a chain
 * 
 *  Region 0: 
 *                   +--------+    +--------+            +--------+
 *  ccff_head[0] --->| Memory |--->| Memory |--->... --->| Memory |----> ccff_tail[0]
 *                   | Module |    | Module |            | Module |
 *                   |   [0]  |    |   [1]  |            |  [N-1] |             
 *                   +--------+    +--------+            +--------+
 *
 *  Region 1: 
 *                   +--------+    +--------+            +--------+
 *  ccff_head[1] --->| Memory |--->| Memory |--->... --->| Memory |----> ccff_tail[1]
 *                   | Module |    | Module |            | Module |
 *                   |   [0]  |    |   [1]  |            |  [N-1] |             
 *                   +--------+    +--------+            +--------+
 *
 *  For the 1st memory module:
 *    net source is the configuration chain head of the primitive module
 *    net sink is the configuration chain head of the next memory module
 *
 *  For the rest of memory modules:
 *    net source is the configuration chain tail of the previous memory module
 *    net sink is the configuration chain head of the next memory module
 *********************************************************************/
Connect all the memory modules under the parent module in a chain





For the 1st memory module:
net source is the configuration chain head of the primitive module
net sink is the configuration chain head of the next memory module

For the rest of memory modules:
net source is the configuration chain tail of the previous memory module
net sink is the configuration chain head of the next memory module
Connect all the memory modules under the parent module in a chain For the 1st memory module : net source is the configuration chain head of the primitive module net sink is the configuration chain head of the next memory module For the rest of memory modules : net source is the configuration chain tail of the previous memory module net sink is the configuration chain head of the next memory module
static 
void add_top_module_nets_cmos_memory_chain_config_bus(ModuleManager& module_manager,
                                                      const ModuleId& parent_module,
                                                      const ConfigProtocol& config_protocol) {
  for (const ConfigRegionId& config_region : module_manager.regions(parent_module)) {
    for (size_t mem_index = 0; mem_index < module_manager.region_configurable_children(parent_module, config_region).size(); ++mem_index) {
      ModuleId net_src_module_id;
      size_t net_src_instance_id;
      ModulePortId net_src_port_id;
      size_t net_src_pin_id;
      ModuleId net_sink_module_id;
      size_t net_sink_instance_id;
      ModulePortId net_sink_port_id;
      size_t net_sink_pin_id;
      if (0 == mem_index) {
        std::string src_port_name = generate_sram_port_name(config_protocol.type(), CIRCUIT_MODEL_PORT_INPUT);
        net_src_module_id = parent_module; 
        net_src_instance_id = 0;
        net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); 
        net_src_pin_id = size_t(config_region);
        std::string sink_port_name = generate_configuration_chain_head_name();
        net_sink_module_id = module_manager.region_configurable_children(parent_module, config_region)[mem_index]; 
        net_sink_instance_id = module_manager.region_configurable_child_instances(parent_module, config_region)[mem_index];
        net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); 
        net_sink_pin_id = 0;
      } else {
        std::string src_port_name = generate_configuration_chain_tail_name();
        net_src_module_id = module_manager.region_configurable_children(parent_module, config_region)[mem_index - 1]; 
        net_src_instance_id = module_manager.region_configurable_child_instances(parent_module, config_region)[mem_index - 1];
        net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); 
        net_src_pin_id = 0;
        std::string sink_port_name = generate_configuration_chain_head_name();
        net_sink_module_id = module_manager.region_configurable_children(parent_module, config_region)[mem_index]; 
        net_sink_instance_id = module_manager.region_configurable_child_instances(parent_module, config_region)[mem_index];
        net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); 
        net_sink_pin_id = 0;
      }
      BasicPort net_src_port = module_manager.module_port(net_src_module_id, net_src_port_id); 
      BasicPort net_sink_port = module_manager.module_port(net_sink_module_id, net_sink_port_id); 
      VTR_ASSERT(net_src_pin_id < net_src_port.get_width());
      VTR_ASSERT(net_sink_pin_id < net_sink_port.get_width());
      ModuleNetId net = create_module_source_pin_net(module_manager, parent_module, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[net_src_pin_id]);
      module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[net_sink_pin_id]);
    }
    std::string src_port_name = generate_configuration_chain_tail_name();
    ModuleId net_src_module_id = module_manager.region_configurable_children(parent_module, config_region).back(); 
    size_t net_src_instance_id = module_manager.region_configurable_child_instances(parent_module, config_region).back();
    ModulePortId net_src_port_id = module_manager.find_module_port(net_src_module_id, src_port_name); 
    size_t net_src_pin_id = 0;
    std::string sink_port_name = generate_sram_port_name(config_protocol.type(), CIRCUIT_MODEL_PORT_OUTPUT);
    ModuleId net_sink_module_id = parent_module; 
    size_t net_sink_instance_id = 0;
    ModulePortId net_sink_port_id = module_manager.find_module_port(net_sink_module_id, sink_port_name); 
    size_t net_sink_pin_id = size_t(config_region);
    BasicPort net_src_port = module_manager.module_port(net_src_module_id, net_src_port_id); 
    BasicPort net_sink_port = module_manager.module_port(net_sink_module_id, net_sink_port_id); 
    VTR_ASSERT(net_src_pin_id < net_src_port.get_width());
    VTR_ASSERT(net_sink_pin_id < net_sink_port.get_width());
    ModuleNetId net = create_module_source_pin_net(module_manager, parent_module, net_src_module_id, net_src_instance_id, net_src_port_id, net_src_port.pins()[net_src_pin_id]);
    module_manager.add_module_net_sink(parent_module, net, net_sink_module_id, net_sink_instance_id, net_sink_port_id, net_sink_port.pins()[net_sink_pin_id]);
  }
}
static void add_top_module_nets_cmos_memory_chain_config_bus ( ModuleManager & module_manager , const ModuleId & parent_module , const ConfigProtocol & config_protocol ) { for ( const ConfigRegionId & config_region : module_manager . regions ( parent_module ) ) { for ( size_t mem_index = 0 ; mem_index < module_manager . region_configurable_children ( parent_module , config_region ) . size ( ) ; ++ mem_index ) { ModuleId net_src_module_id ; size_t net_src_instance_id ; ModulePortId net_src_port_id ; size_t net_src_pin_id ; ModuleId net_sink_module_id ; size_t net_sink_instance_id ; ModulePortId net_sink_port_id ; size_t net_sink_pin_id ; if ( 0 == mem_index ) { std :: string src_port_name = generate_sram_port_name ( config_protocol . type ( ) , CIRCUIT_MODEL_PORT_INPUT ) ; net_src_module_id = parent_module ; net_src_instance_id = 0 ; net_src_port_id = module_manager . find_module_port ( net_src_module_id , src_port_name ) ; net_src_pin_id = size_t ( config_region ) ; std :: string sink_port_name = generate_configuration_chain_head_name ( ) ; net_sink_module_id = module_manager . region_configurable_children ( parent_module , config_region ) [ mem_index ] ; net_sink_instance_id = module_manager . region_configurable_child_instances ( parent_module , config_region ) [ mem_index ] ; net_sink_port_id = module_manager . find_module_port ( net_sink_module_id , sink_port_name ) ; net_sink_pin_id = 0 ; } else { std :: string src_port_name = generate_configuration_chain_tail_name ( ) ; net_src_module_id = module_manager . region_configurable_children ( parent_module , config_region ) [ mem_index - 1 ] ; net_src_instance_id = module_manager . region_configurable_child_instances ( parent_module , config_region ) [ mem_index - 1 ] ; net_src_port_id = module_manager . find_module_port ( net_src_module_id , src_port_name ) ; net_src_pin_id = 0 ; std :: string sink_port_name = generate_configuration_chain_head_name ( ) ; net_sink_module_id = module_manager . region_configurable_children ( parent_module , config_region ) [ mem_index ] ; net_sink_instance_id = module_manager . region_configurable_child_instances ( parent_module , config_region ) [ mem_index ] ; net_sink_port_id = module_manager . find_module_port ( net_sink_module_id , sink_port_name ) ; net_sink_pin_id = 0 ; } BasicPort net_src_port = module_manager . module_port ( net_src_module_id , net_src_port_id ) ; BasicPort net_sink_port = module_manager . module_port ( net_sink_module_id , net_sink_port_id ) ; VTR_ASSERT ( net_src_pin_id < net_src_port . get_width ( ) ) ; VTR_ASSERT ( net_sink_pin_id < net_sink_port . get_width ( ) ) ; ModuleNetId net = create_module_source_pin_net ( module_manager , parent_module , net_src_module_id , net_src_instance_id , net_src_port_id , net_src_port . pins ( ) [ net_src_pin_id ] ) ; module_manager . add_module_net_sink ( parent_module , net , net_sink_module_id , net_sink_instance_id , net_sink_port_id , net_sink_port . pins ( ) [ net_sink_pin_id ] ) ; } std :: string src_port_name = generate_configuration_chain_tail_name ( ) ; ModuleId net_src_module_id = module_manager . region_configurable_children ( parent_module , config_region ) . back ( ) ; size_t net_src_instance_id = module_manager . region_configurable_child_instances ( parent_module , config_region ) . back ( ) ; ModulePortId net_src_port_id = module_manager . find_module_port ( net_src_module_id , src_port_name ) ; size_t net_src_pin_id = 0 ; std :: string sink_port_name = generate_sram_port_name ( config_protocol . type ( ) , CIRCUIT_MODEL_PORT_OUTPUT ) ; ModuleId net_sink_module_id = parent_module ; size_t net_sink_instance_id = 0 ; ModulePortId net_sink_port_id = module_manager . find_module_port ( net_sink_module_id , sink_port_name ) ; size_t net_sink_pin_id = size_t ( config_region ) ; BasicPort net_src_port = module_manager . module_port ( net_src_module_id , net_src_port_id ) ; BasicPort net_sink_port = module_manager . module_port ( net_sink_module_id , net_sink_port_id ) ; VTR_ASSERT ( net_src_pin_id < net_src_port . get_width ( ) ) ; VTR_ASSERT ( net_sink_pin_id < net_sink_port . get_width ( ) ) ; ModuleNetId net = create_module_source_pin_net ( module_manager , parent_module , net_src_module_id , net_src_instance_id , net_src_port_id , net_src_port . pins ( ) [ net_src_pin_id ] ) ; module_manager . add_module_net_sink ( parent_module , net , net_sink_module_id , net_sink_instance_id , net_sink_port_id , net_sink_port . pins ( ) [ net_sink_pin_id ] ) ; } }
Connect all the memory modules under the parent module in a chain
Connect all the memory modules under the parent module in a chain
/* Find the port name of configuration chain head */ /* Find the port name of next memory module */ /* Find the port name of previous memory module */ /* Find the port name of next memory module */ /* Get the pin id for source port */ /* Get the pin id for sink port */ /* Create a net and add source and sink to it */ /* Add net sink */ /* For the last memory module:
     *    net source is the configuration chain tail of the previous memory module
     *    net sink is the configuration chain tail of the primitive module
     */ /* Find the port name of previous memory module */ /* Find the port name of next memory module */ /* Get the pin id for source port */ /* Get the pin id for sink port */ /* Create a net and add source and sink to it */ /* Add net sink */