openfpga/src/fpga_spice/spice_grid.cpp
/********************************************************************
 * Print SPICE subckts of a primitive node in the pb_graph_node graph
 * This generic function can support all the different types of primitive nodes
 * i.e., Look-Up Tables (LUTs), Flip-flops (FFs) and hard logic blocks such as adders.
 *
 * The SPICE subckt will consist of two parts:
 * 1. Logic module of the primitive node
 *    This module performs the logic function of the block
 * 2. Memory module of the primitive node
 *    This module stores the configuration bits for the logic module
 *    if the logic module is a programmable resource, such as LUT
 *
 * SPICE subckt structure:
 *
 *       Primitive block
 *     +---------------------------------------+
 *     |                                       | 
 *     |      +---------+    +---------+       |
 *  in |----->|         |--->|         |<------|configuration lines
 *     |      |  Logic  |... |  Memory |       |
 *  out|<-----|         |--->|         |       |
 *     |      +---------+    +---------+       |
 *     |                                       | 
 *     +---------------------------------------+
 *
 *******************************************************************/
Print SPICE subckts of a primitive node in the pb_graph_node graph
This generic function can support all the different types of primitive nodes
i.e., Look-Up Tables (LUTs), Flip-flops (FFs) and hard logic blocks such as adders.

The SPICE subckt will consist of two parts:
1. Logic module of the primitive node
This module performs the logic function of the block
2. Memory module of the primitive node
This module stores the configuration bits for the logic module
if the logic module is a programmable resource, such as LUT

SPICE subckt structure.


Print SPICE subckts of a primitive node in the pb_graph_node graph This generic function can support all the different types of primitive nodes i . e . Look - Up Tables ( LUTs ) Flip - flops ( FFs ) and hard logic blocks such as adders . The SPICE subckt will consist of two parts : 1 . Logic module of the primitive node This module performs the logic function of the block 2 . Memory module of the primitive node This module stores the configuration bits for the logic module if the logic module is a programmable resource such as LUT SPICE subckt structure .
static 
void print_spice_primitive_block(NetlistManager& netlist_manager,
                                 const ModuleManager& module_manager,
                                 const std::string& subckt_dir,
                                 t_pb_graph_node* primitive_pb_graph_node,
                                 const bool& verbose) {
  if (nullptr == primitive_pb_graph_node) {
    VTR_LOGF_ERROR(__FILE__, __LINE__,
                   "Invalid primitive_pb_graph_node!\n");
    exit(1);
  }
  std::string spice_fname(subckt_dir 
                          + generate_logical_tile_netlist_name(std::string(), primitive_pb_graph_node, std::string(SPICE_NETLIST_FILE_POSTFIX))
                           );
  VTR_LOG("Writing SPICE netlist '%s' for primitive pb_type '%s' ...",
          spice_fname.c_str(), primitive_pb_graph_node->pb_type->name);
  VTR_LOGV(verbose, "\n");
  std::fstream fp;
  fp.open(spice_fname, std::fstream::out | std::fstream::trunc);
  check_file_stream(spice_fname.c_str(), fp);
  print_spice_file_header(fp, std::string("SPICE subckts for primitive pb_type: " + std::string(primitive_pb_graph_node->pb_type->name))); 
  std::string primitive_module_name = generate_physical_block_module_name(primitive_pb_graph_node->pb_type);
  ModuleId primitive_module = module_manager.find_module(primitive_module_name);
  VTR_ASSERT(true == module_manager.valid_module_id(primitive_module));
  VTR_LOGV(verbose,
          "Writing SPICE codes of logical tile primitive block '%s'...",
           module_manager.module_name(primitive_module).c_str());
  write_spice_subckt_to_file(fp, module_manager, primitive_module);
  fp.close();
  NetlistId nlist_id = netlist_manager.add_netlist(spice_fname);
  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
  netlist_manager.set_netlist_type(nlist_id, NetlistManager::LOGIC_BLOCK_NETLIST);
  VTR_LOGV(verbose, "Done\n");
}
static void print_spice_primitive_block ( NetlistManager & netlist_manager , const ModuleManager & module_manager , const std :: string & subckt_dir , t_pb_graph_node * primitive_pb_graph_node , const bool & verbose ) { if ( nullptr == primitive_pb_graph_node ) { VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " ) ; exit ( 1 ) ; } std :: string spice_fname ( subckt_dir + generate_logical_tile_netlist_name ( std :: string ( ) , primitive_pb_graph_node , std :: string ( SPICE_NETLIST_FILE_POSTFIX ) ) ) ; VTR_LOG ( " " , spice_fname . c_str ( ) , primitive_pb_graph_node -> pb_type -> name ) ; VTR_LOGV ( verbose , " \n " ) ; std :: fstream fp ; fp . open ( spice_fname , std :: fstream :: out | std :: fstream :: trunc ) ; check_file_stream ( spice_fname . c_str ( ) , fp ) ; print_spice_file_header ( fp , std :: string ( " " + std :: string ( primitive_pb_graph_node -> pb_type -> name ) ) ) ; std :: string primitive_module_name = generate_physical_block_module_name ( primitive_pb_graph_node -> pb_type ) ; ModuleId primitive_module = module_manager . find_module ( primitive_module_name ) ; VTR_ASSERT ( true == module_manager . valid_module_id ( primitive_module ) ) ; VTR_LOGV ( verbose , " " , module_manager . module_name ( primitive_module ) . c_str ( ) ) ; write_spice_subckt_to_file ( fp , module_manager , primitive_module ) ; fp . close ( ) ; NetlistId nlist_id = netlist_manager . add_netlist ( spice_fname ) ; VTR_ASSERT ( NetlistId :: INVALID ( ) != nlist_id ) ; netlist_manager . set_netlist_type ( nlist_id , NetlistManager :: LOGIC_BLOCK_NETLIST ) ; VTR_LOGV ( verbose , " \n " ) ; }
Print SPICE subckts of a primitive node in the pb_graph_node graph
 This generic function can support all the different types of primitive nodes
 i.e., Look-Up Tables (LUTs), Flip-flops (FFs) and hard logic blocks such as adders.
Print SPICE subckts of a primitive node in the pb_graph_node graph This generic function can support all the different types of primitive nodes i . e . Look - Up Tables ( LUTs ) Flip - flops ( FFs ) and hard logic blocks such as adders .
/* Ensure a valid pb_graph_node */ /* Give a name to the Verilog netlist */ /* Create the file name for Verilog */ /* Create the file stream */ /* Generate the module name for this primitive pb_graph_node*/ /* Create a module of the primitive LUT and register it to module manager */ /* Ensure that the module has been created and thus unique! */ /* Write the spice module */ /* Close file handler */ /* Add fname to the netlist name list */