vpr/src/route/rr_graph_reader.cpp
/*loads the given RR_graph file into the appropriate data structures
 * as specified by read_rr_graph_name. Set up correct routing data
 * structures as well*/
loads the given RR_graph file into the appropriate data structures
as specified by read_rr_graph_name. Set up correct routing data
structures as well
loads the given RR_graph file into the appropriate data structures as specified by read_rr_graph_name . Set up correct routing data structures as well
void load_rr_file(const t_graph_type graph_type,
                  const DeviceGrid& grid,
                  const std::vector<t_segment_inf>& segment_inf,
                  const enum e_base_cost_type base_cost_type,
                  int* wire_to_rr_ipin_switch,
                  const char* read_rr_graph_name) {
    vtr::ScopedStartFinishTimer timer("Loading routing resource graph");
    const char* Prop;
    pugi::xml_node next_component;
    pugi::xml_document doc;
    pugiutil::loc_data loc_data;
    if (vtr::check_file_name_extension(read_rr_graph_name, ".xml") == false) {
        VTR_LOG_WARN(
            "RR graph file '%s' may be in incorrect format. "
            "Expecting .xml format\n",
            read_rr_graph_name);
    }
    try {
        loc_data = pugiutil::load_xml(doc, read_rr_graph_name);
        auto& device_ctx = g_vpr_ctx.mutable_device();
        auto rr_graph = get_single_child(doc, "rr_graph", loc_data);
        Prop = get_attribute(rr_graph, "tool_version", loc_data, pugiutil::OPTIONAL).as_string(nullptr);
        if (Prop != nullptr) {
            if (strcmp(Prop, vtr::VERSION) != 0) {
                VTR_LOG("\n");
                VTR_LOG_WARN("This architecture version is for VPR %s while your current VPR version is %s compatability issues may arise\n",
                             vtr::VERSION, Prop);
                VTR_LOG("\n");
            }
        }
        Prop = get_attribute(rr_graph, "tool_comment", loc_data, pugiutil::OPTIONAL).as_string(nullptr);
        std::string correct_string = "Generated from arch file ";
        correct_string += get_arch_file_name();
        if (Prop != nullptr) {
            if (Prop != correct_string) {
                VTR_LOG("\n");
                VTR_LOG_WARN("This RR graph file is based on %s while your input architecture file is %s compatability issues may arise\n",
                             get_arch_file_name(), Prop);
                VTR_LOG("\n");
            }
        }
        next_component = get_single_child(rr_graph, "grid", loc_data);
        verify_grid(next_component, loc_data, grid);
        next_component = get_single_child(rr_graph, "block_types", loc_data);
        verify_blocks(next_component, loc_data);
        next_component = get_single_child(rr_graph, "segments", loc_data);
        verify_segments(next_component, loc_data, segment_inf);
        VTR_LOG("Starting build routing resource graph...\n");
        for (const auto& inf : segment_inf) {
            device_ctx.rr_graph.create_segment(inf);
        }
        next_component = get_first_child(rr_graph, "channels", loc_data);
        t_chan_width nodes_per_chan;
        process_channels(nodes_per_chan, grid, next_component, loc_data);
        bool is_global_graph = (GRAPH_GLOBAL == graph_type ? true : false);
        int max_chan_width = (is_global_graph ? 1 : nodes_per_chan.max);
        VTR_ASSERT(max_chan_width > 0);
        next_component = get_single_child(rr_graph, "rr_nodes", loc_data);
        int num_rr_nodes = count_children(next_component, "node", loc_data);
        device_ctx.rr_graph.reserve_nodes(num_rr_nodes);
        process_nodes(next_component, loc_data);
        next_component = get_single_child(rr_graph, "switches", loc_data);
        int numSwitches = count_children(next_component, "switch", loc_data);
        device_ctx.rr_switch_inf.resize(numSwitches);
        process_switches(next_component, loc_data);
        next_component = get_single_child(rr_graph, "rr_edges", loc_data);
        process_edges(next_component, loc_data, wire_to_rr_ipin_switch, numSwitches);
        device_ctx.rr_graph.rebuild_node_edges();
        next_component = get_single_child(rr_graph, "rr_nodes", loc_data);
        set_cost_indices(next_component, loc_data, is_global_graph, segment_inf.size());
        alloc_and_load_rr_indexed_data(segment_inf, device_ctx.rr_graph,
                                       max_chan_width, *wire_to_rr_ipin_switch, base_cost_type);
        process_seg_id(next_component, loc_data);
        if (false == device_ctx.rr_graph.validate()) {
            vpr_throw(VPR_ERROR_ROUTE,
                      __FILE__,
                      __LINE__,
                      "Fundamental errors occurred when validating rr_graph object!\n");
        }
        device_ctx.chan_width = nodes_per_chan;
        device_ctx.read_rr_graph_filename = std::string(read_rr_graph_name);
        check_rr_graph(graph_type, grid, device_ctx.physical_tile_types);
        if (false == check_rr_graph(device_ctx.rr_graph)) {
            vpr_throw(VPR_ERROR_ROUTE,
                      __FILE__,
                      __LINE__,
                      "Advanced checking rr_graph object fails! Routing may still work "
                      "but not smooth\n");
        }
    } catch (pugiutil::XmlError& e) {
        vpr_throw(VPR_ERROR_ROUTE, read_rr_graph_name, e.line(), "%s", e.what());
    }
}
void load_rr_file ( const t_graph_type graph_type , const DeviceGrid & grid , const std :: vector < t_segment_inf > & segment_inf , const enum e_base_cost_type base_cost_type , int * wire_to_rr_ipin_switch , const char * read_rr_graph_name ) { vtr :: ScopedStartFinishTimer timer ( " " ) ; const char * Prop ; pugi :: xml_node next_component ; pugi :: xml_document doc ; pugiutil :: loc_data loc_data ; if ( vtr :: check_file_name_extension ( read_rr_graph_name , " " ) == false ) { VTR_LOG_WARN ( " " " \n " , read_rr_graph_name ) ; } try { loc_data = pugiutil :: load_xml ( doc , read_rr_graph_name ) ; auto & device_ctx = g_vpr_ctx . mutable_device ( ) ; auto rr_graph = get_single_child ( doc , " " , loc_data ) ; Prop = get_attribute ( rr_graph , " " , loc_data , pugiutil :: OPTIONAL ) . as_string ( nullptr ) ; if ( Prop != nullptr ) { if ( strcmp ( Prop , vtr :: VERSION ) != 0 ) { VTR_LOG ( " \n " ) ; VTR_LOG_WARN ( " \n " , vtr :: VERSION , Prop ) ; VTR_LOG ( " \n " ) ; } } Prop = get_attribute ( rr_graph , " " , loc_data , pugiutil :: OPTIONAL ) . as_string ( nullptr ) ; std :: string correct_string = " " ; correct_string += get_arch_file_name ( ) ; if ( Prop != nullptr ) { if ( Prop != correct_string ) { VTR_LOG ( " \n " ) ; VTR_LOG_WARN ( " \n " , get_arch_file_name ( ) , Prop ) ; VTR_LOG ( " \n " ) ; } } next_component = get_single_child ( rr_graph , " " , loc_data ) ; verify_grid ( next_component , loc_data , grid ) ; next_component = get_single_child ( rr_graph , " " , loc_data ) ; verify_blocks ( next_component , loc_data ) ; next_component = get_single_child ( rr_graph , " " , loc_data ) ; verify_segments ( next_component , loc_data , segment_inf ) ; VTR_LOG ( " \n " ) ; for ( const auto & inf : segment_inf ) { device_ctx . rr_graph . create_segment ( inf ) ; } next_component = get_first_child ( rr_graph , " " , loc_data ) ; t_chan_width nodes_per_chan ; process_channels ( nodes_per_chan , grid , next_component , loc_data ) ; bool is_global_graph = ( GRAPH_GLOBAL == graph_type ? true : false ) ; int max_chan_width = ( is_global_graph ? 1 : nodes_per_chan . max ) ; VTR_ASSERT ( max_chan_width > 0 ) ; next_component = get_single_child ( rr_graph , " " , loc_data ) ; int num_rr_nodes = count_children ( next_component , " " , loc_data ) ; device_ctx . rr_graph . reserve_nodes ( num_rr_nodes ) ; process_nodes ( next_component , loc_data ) ; next_component = get_single_child ( rr_graph , " " , loc_data ) ; int numSwitches = count_children ( next_component , " " , loc_data ) ; device_ctx . rr_switch_inf . resize ( numSwitches ) ; process_switches ( next_component , loc_data ) ; next_component = get_single_child ( rr_graph , " " , loc_data ) ; process_edges ( next_component , loc_data , wire_to_rr_ipin_switch , numSwitches ) ; device_ctx . rr_graph . rebuild_node_edges ( ) ; next_component = get_single_child ( rr_graph , " " , loc_data ) ; set_cost_indices ( next_component , loc_data , is_global_graph , segment_inf . size ( ) ) ; alloc_and_load_rr_indexed_data ( segment_inf , device_ctx . rr_graph , max_chan_width , * wire_to_rr_ipin_switch , base_cost_type ) ; process_seg_id ( next_component , loc_data ) ; if ( false == device_ctx . rr_graph . validate ( ) ) { vpr_throw ( VPR_ERROR_ROUTE , __FILE__ , __LINE__ , " \n " ) ; } device_ctx . chan_width = nodes_per_chan ; device_ctx . read_rr_graph_filename = std :: string ( read_rr_graph_name ) ; check_rr_graph ( graph_type , grid , device_ctx . physical_tile_types ) ; if ( false == check_rr_graph ( device_ctx . rr_graph ) ) { vpr_throw ( VPR_ERROR_ROUTE , __FILE__ , __LINE__ , " " " \n " ) ; } } catch ( pugiutil :: XmlError & e ) { vpr_throw ( VPR_ERROR_ROUTE , read_rr_graph_name , e . line ( ) , " " , e . what ( ) ) ; } }
loads the given RR_graph file into the appropriate data structures
 as specified by read_rr_graph_name.
loads the given RR_graph file into the appropriate data structures as specified by read_rr_graph_name .
//parse the file //Check for errors //Compare with the architecture file to ensure consistency /* Add segments */ /* Decode the graph_type */ /* Global routing uses a single longwire track */ /* Alloc rr nodes and count count nodes */ /* Loads edges, switches, and node look up tables*/ //Partition the rr graph edges for efficient access to configurable/non-configurable //edge subsets. Must be done after RR switches have been allocated //sets the cost index and seg id information /* Essential check for rr_graph, build look-up */ /* Error out if built-in validator of rr_graph fails */ /* Error out if advanced checker of rr_graph fails */