extsrc/mesa/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
/* If the RHS processing resulted in an instruction generating a
 * temporary value, and it would be easy to rewrite the instruction to
 * generate its result right into the LHS instead, do so.  This ends
 * up reliably removing instructions where it can be tricky to do so
 * later without real UD chain information.
 */
If the RHS processing resulted in an instruction generating a
temporary value, and it would be easy to rewrite the instruction to
generate its result right into the LHS instead, do so.  This ends
up reliably removing instructions where it can be tricky to do so
later without real UD chain information.
If the RHS processing resulted in an instruction generating a temporary value and it would be easy to rewrite the instruction to generate its result right into the LHS instead do so . This ends up reliably removing instructions where it can be tricky to do so later without real UD chain information .
bool
fs_visitor::try_rewrite_rhs_to_dst(ir_assignment *ir,
                                   fs_reg dst,
                                   fs_reg src,
                                   fs_inst *pre_rhs_inst,
                                   fs_inst *last_rhs_inst)
{
   if (pre_rhs_inst == last_rhs_inst)
      return false; 
   if (ir->condition ||
       !(ir->lhs->type->is_scalar() ||
        (ir->lhs->type->is_vector() &&
         ir->write_mask == (1 << ir->lhs->type->vector_elements) - 1)))
      return false;
   if (last_rhs_inst->predicated ||
       last_rhs_inst->force_uncompressed ||
       last_rhs_inst->force_sechalf ||
       !src.equals(&last_rhs_inst->dst))
      return false;
   if (ir->lhs->type->vector_elements != last_rhs_inst->regs_written())
      return false;
   last_rhs_inst->dst = dst;
   return true;
}
bool fs_visitor :: try_rewrite_rhs_to_dst ( ir_assignment * ir , fs_reg dst , fs_reg src , fs_inst * pre_rhs_inst , fs_inst * last_rhs_inst ) { if ( pre_rhs_inst == last_rhs_inst ) return false ; if ( ir -> condition || ! ( ir -> lhs -> type -> is_scalar ( ) || ( ir -> lhs -> type -> is_vector ( ) && ir -> write_mask == ( 1 << ir -> lhs -> type -> vector_elements ) - 1 ) ) ) return false ; if ( last_rhs_inst -> predicated || last_rhs_inst -> force_uncompressed || last_rhs_inst -> force_sechalf || ! src . equals ( & last_rhs_inst -> dst ) ) return false ; if ( ir -> lhs -> type -> vector_elements != last_rhs_inst -> regs_written ( ) ) return false ; last_rhs_inst -> dst = dst ; return true ; }
If the RHS processing resulted in an instruction generating a
 temporary value, and it would be easy to rewrite the instruction to
 generate its result right into the LHS instead, do so.
If the RHS processing resulted in an instruction generating a temporary value and it would be easy to rewrite the instruction to generate its result right into the LHS instead do so .
/* No instructions generated to work with. */ /* Only attempt if we're doing a direct assignment. */ /* Make sure the last instruction generated our source reg. */ /* If last_rhs_inst wrote a different number of components than our LHS,
    * we can't safely rewrite it.
    */ /* Success!  Rewrite the instruction. */