openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
/********************************************************************
 * Print a Verilog file containing preprocessing flags
 * which are used enable/disable some features in FPGA Verilog modules
 *******************************************************************/
Print a Verilog file containing preprocessing flags
which are used enable/disable some features in FPGA Verilog modules
Print a Verilog file containing preprocessing flags which are used enable / disable some features in FPGA Verilog modules
void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
                                               const FabricVerilogOption& fabric_verilog_opts) {
  std::string verilog_fname = src_dir + std::string(DEFINES_VERILOG_FILE_NAME);
  std::fstream fp;
  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
  check_file_stream(verilog_fname.c_str(), fp);
  print_verilog_file_header(fp, std::string("Preprocessing flags to enable/disable features in FPGA Verilog modules")); 
  if (true == fabric_verilog_opts.include_timing()) {
    print_verilog_define_flag(fp, std::string(VERILOG_TIMING_PREPROC_FLAG), 1);
    fp << std::endl;
  } 
  fp.close();
}
void print_verilog_preprocessing_flags_netlist ( const std :: string & src_dir , const FabricVerilogOption & fabric_verilog_opts ) { std :: string verilog_fname = src_dir + std :: string ( DEFINES_VERILOG_FILE_NAME ) ; std :: fstream fp ; fp . open ( verilog_fname , std :: fstream :: out | std :: fstream :: trunc ) ; check_file_stream ( verilog_fname . c_str ( ) , fp ) ; print_verilog_file_header ( fp , std :: string ( " " ) ) ; if ( true == fabric_verilog_opts . include_timing ( ) ) { print_verilog_define_flag ( fp , std :: string ( VERILOG_TIMING_PREPROC_FLAG ) , 1 ) ; fp << std :: endl ; } fp . close ( ) ; }
Print a Verilog file containing preprocessing flags
 which are used enable/disable some features in FPGA Verilog modules
Print a Verilog file containing preprocessing flags which are used enable / disable some features in FPGA Verilog modules
/* Create the file stream */ /* Validate the file stream */ /* Print the title */ /* To enable timing */ /* Close the file stream */