openfpga/src/repack/build_physical_lb_rr_graph.cpp
/***************************************************************************************
 * Create all the edges and special nodes (SOURCE/SINK) for lb_rr_graph for each pb_graph_node.
 * Different from the lb_rr_graph builder in VPR packer, this function only consider 
 * the pb_graph_node under physical modes
 ***************************************************************************************/
Create all the edges and special nodes (SOURCE/SINK) for lb_rr_graph for each pb_graph_node.
Different from the lb_rr_graph builder in VPR packer, this function only consider
the pb_graph_node under physical modes
Create all the edges and special nodes ( SOURCE / SINK ) for lb_rr_graph for each pb_graph_node . Different from the lb_rr_graph builder in VPR packer this function only consider the pb_graph_node under physical modes
static 
void rec_build_physical_lb_rr_edge_for_pb_graph_node(t_pb_graph_node* pb_graph_node,
                                                     LbRRGraph& lb_rr_graph,
                                                     const LbRRNodeId& ext_rr_index,
                                                     const VprDeviceAnnotation& device_annotation) {
  t_pb_type* pb_type = pb_graph_node->pb_type;
  t_pb_graph_node* parent_node = pb_graph_node->parent_pb_graph_node;
  for (int iport = 0; iport < pb_graph_node->num_input_ports; iport++) {
    LbRRNodeId sink_node = LbRRNodeId::INVALID();
    for (int ipin = 0; ipin < pb_graph_node->num_input_pins[iport]; ipin++) {
      t_pb_graph_pin* pb_pin = &pb_graph_node->input_pins[iport][ipin];
      t_mode* physical_mode = device_annotation.physical_mode(pb_type);
      if (true == is_primitive_pb_type(pb_type)) {
        build_lb_rr_edge_primitive_pb_graph_input_pin(lb_rr_graph, pb_pin, sink_node);
      } else {
        VTR_ASSERT(false == is_primitive_pb_type(pb_type));
        build_lb_rr_edge_pb_graph_pin(lb_rr_graph, pb_pin, LB_INTERMEDIATE, physical_mode);
      }
    }
  }
  for (int iport = 0; iport < pb_graph_node->num_clock_ports; iport++) {
    LbRRNodeId sink_node = LbRRNodeId::INVALID();
    for (int ipin = 0; ipin < pb_graph_node->num_clock_pins[iport]; ipin++) {
      t_pb_graph_pin* pb_pin = &pb_graph_node->clock_pins[iport][ipin];
      t_mode* physical_mode = device_annotation.physical_mode(pb_type);
      if (true == is_primitive_pb_type(pb_type)) {
        build_lb_rr_edge_primitive_pb_graph_input_pin(lb_rr_graph, pb_pin, sink_node);
      } else {
        VTR_ASSERT(false == is_primitive_pb_type(pb_type));
        build_lb_rr_edge_pb_graph_pin(lb_rr_graph, pb_pin, LB_INTERMEDIATE, physical_mode);
      }
    }
  }
  e_lb_rr_type output_pin_rr_type = LB_INTERMEDIATE;
  if (true == is_primitive_pb_type(pb_type)) {
    output_pin_rr_type = LB_SOURCE;
  }
  for (int iport = 0; iport < pb_graph_node->num_output_ports; iport++) {
    for (int ipin = 0; ipin < pb_graph_node->num_output_pins[iport]; ipin++) {
      t_pb_graph_pin* pb_pin = &pb_graph_node->output_pins[iport][ipin];
      if (true == pb_graph_node->is_root()) {
        build_lb_rr_edge_root_pb_graph_pin(lb_rr_graph, pb_pin, output_pin_rr_type, ext_rr_index);
      } else {
        VTR_ASSERT(false == pb_graph_node->is_root());
        t_mode* physical_mode = device_annotation.physical_mode(parent_node->pb_type);
        build_lb_rr_edge_pb_graph_pin(lb_rr_graph, pb_pin, output_pin_rr_type, physical_mode);
      }
    }
  }
  if (true == is_primitive_pb_type(pb_type)) {
    return; 
  }
  t_mode* physical_mode = device_annotation.physical_mode(pb_graph_node->pb_type);
  for (int ipb_type = 0; ipb_type < physical_mode->num_pb_type_children; ipb_type++) {
    for (int ipb = 0; ipb < physical_mode->pb_type_children[ipb_type].num_pb; ipb++) {
      rec_build_physical_lb_rr_edge_for_pb_graph_node(&(pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb_type][ipb]), lb_rr_graph, ext_rr_index, device_annotation);
    }
  }
}
static void rec_build_physical_lb_rr_edge_for_pb_graph_node ( t_pb_graph_node * pb_graph_node , LbRRGraph & lb_rr_graph , const LbRRNodeId & ext_rr_index , const VprDeviceAnnotation & device_annotation ) { t_pb_type * pb_type = pb_graph_node -> pb_type ; t_pb_graph_node * parent_node = pb_graph_node -> parent_pb_graph_node ; for ( int iport = 0 ; iport < pb_graph_node -> num_input_ports ; iport ++ ) { LbRRNodeId sink_node = LbRRNodeId :: INVALID ( ) ; for ( int ipin = 0 ; ipin < pb_graph_node -> num_input_pins [ iport ] ; ipin ++ ) { t_pb_graph_pin * pb_pin = & pb_graph_node -> input_pins [ iport ] [ ipin ] ; t_mode * physical_mode = device_annotation . physical_mode ( pb_type ) ; if ( true == is_primitive_pb_type ( pb_type ) ) { build_lb_rr_edge_primitive_pb_graph_input_pin ( lb_rr_graph , pb_pin , sink_node ) ; } else { VTR_ASSERT ( false == is_primitive_pb_type ( pb_type ) ) ; build_lb_rr_edge_pb_graph_pin ( lb_rr_graph , pb_pin , LB_INTERMEDIATE , physical_mode ) ; } } } for ( int iport = 0 ; iport < pb_graph_node -> num_clock_ports ; iport ++ ) { LbRRNodeId sink_node = LbRRNodeId :: INVALID ( ) ; for ( int ipin = 0 ; ipin < pb_graph_node -> num_clock_pins [ iport ] ; ipin ++ ) { t_pb_graph_pin * pb_pin = & pb_graph_node -> clock_pins [ iport ] [ ipin ] ; t_mode * physical_mode = device_annotation . physical_mode ( pb_type ) ; if ( true == is_primitive_pb_type ( pb_type ) ) { build_lb_rr_edge_primitive_pb_graph_input_pin ( lb_rr_graph , pb_pin , sink_node ) ; } else { VTR_ASSERT ( false == is_primitive_pb_type ( pb_type ) ) ; build_lb_rr_edge_pb_graph_pin ( lb_rr_graph , pb_pin , LB_INTERMEDIATE , physical_mode ) ; } } } e_lb_rr_type output_pin_rr_type = LB_INTERMEDIATE ; if ( true == is_primitive_pb_type ( pb_type ) ) { output_pin_rr_type = LB_SOURCE ; } for ( int iport = 0 ; iport < pb_graph_node -> num_output_ports ; iport ++ ) { for ( int ipin = 0 ; ipin < pb_graph_node -> num_output_pins [ iport ] ; ipin ++ ) { t_pb_graph_pin * pb_pin = & pb_graph_node -> output_pins [ iport ] [ ipin ] ; if ( true == pb_graph_node -> is_root ( ) ) { build_lb_rr_edge_root_pb_graph_pin ( lb_rr_graph , pb_pin , output_pin_rr_type , ext_rr_index ) ; } else { VTR_ASSERT ( false == pb_graph_node -> is_root ( ) ) ; t_mode * physical_mode = device_annotation . physical_mode ( parent_node -> pb_type ) ; build_lb_rr_edge_pb_graph_pin ( lb_rr_graph , pb_pin , output_pin_rr_type , physical_mode ) ; } } } if ( true == is_primitive_pb_type ( pb_type ) ) { return ; } t_mode * physical_mode = device_annotation . physical_mode ( pb_graph_node -> pb_type ) ; for ( int ipb_type = 0 ; ipb_type < physical_mode -> num_pb_type_children ; ipb_type ++ ) { for ( int ipb = 0 ; ipb < physical_mode -> pb_type_children [ ipb_type ] . num_pb ; ipb ++ ) { rec_build_physical_lb_rr_edge_for_pb_graph_node ( & ( pb_graph_node -> child_pb_graph_nodes [ physical_mode -> index ] [ ipb_type ] [ ipb ] ) , lb_rr_graph , ext_rr_index , device_annotation ) ; } } }
Create all the edges and special nodes (SOURCE/SINK) for lb_rr_graph for each pb_graph_node.
Create all the edges and special nodes ( SOURCE / SINK ) for lb_rr_graph for each pb_graph_node .
/* TODO: think if we need to consider wire mode of LUT when creating the lb_rr_graph here! 
   * Should we create edges through the LUT input and output nodes?
   */ /* The only difference between primitive node and intermediate nodes is
   * the output pins of primitive node will be SINK node
   * Otherwise it is always INTERMEDIATE node
   */ /* The input pins should connect to sinks */ /* load intermediate indices */ /* The input pins should connect to sinks */ /* load intermediate indices */ /* The output pins should connect to its fan-outs */ /* load intermediate indices */ /* For non-primitive node: 
   * This pb_graph_node is a logic block or subcluster 
   * Go recusrively 
   */