openfpga/src/fpga_spice/spice_memory.cpp
/*********************************************************************
 * Generate Verilog modules for the memories that are used
 * by multiplexers  
 *
 *            +----------------+
 * mem_in --->|  Memory Module |---> mem_out
 *            +----------------+
 *              |  |  ... |  | 
 *              v  v      v  v SRAM ports of multiplexer
 *          +---------------------+
 *    in--->|  Multiplexer Module |---> out
 *          +---------------------+
 ********************************************************************/
Generate Verilog modules for the memories that are used
by multiplexers


Generate Verilog modules for the memories that are used by multiplexers
static 
void print_spice_mux_memory_module(const ModuleManager& module_manager,
                                   const CircuitLibrary& circuit_lib,
                                   std::fstream& fp,
                                   const CircuitModelId& mux_model,
                                   const MuxGraph& mux_graph) {
  switch (circuit_lib.design_tech_type(mux_model)) {
  case CIRCUIT_MODEL_DESIGN_CMOS: {
    std::string module_name = generate_mux_subckt_name(circuit_lib, mux_model, 
                                                       find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()), 
                                                       std::string(SPICE_MEM_POSTFIX));
    ModuleId mem_module = module_manager.find_module(module_name);
    VTR_ASSERT(true == module_manager.valid_module_id(mem_module));
    write_spice_subckt_to_file(fp, module_manager, mem_module);
    fp << std::endl;
    break;
  }
  case CIRCUIT_MODEL_DESIGN_RRAM:
    break;
  default:
    VTR_LOGF_ERROR(__FILE__, __LINE__,
                   "Invalid design technology of multiplexer '%s'\n",
                   circuit_lib.model_name(mux_model).c_str()); 
    exit(1);
  }
}
static void print_spice_mux_memory_module ( const ModuleManager & module_manager , const CircuitLibrary & circuit_lib , std :: fstream & fp , const CircuitModelId & mux_model , const MuxGraph & mux_graph ) { switch ( circuit_lib . design_tech_type ( mux_model ) ) { case CIRCUIT_MODEL_DESIGN_CMOS : { std :: string module_name = generate_mux_subckt_name ( circuit_lib , mux_model , find_mux_num_datapath_inputs ( circuit_lib , mux_model , mux_graph . num_inputs ( ) ) , std :: string ( SPICE_MEM_POSTFIX ) ) ; ModuleId mem_module = module_manager . find_module ( module_name ) ; VTR_ASSERT ( true == module_manager . valid_module_id ( mem_module ) ) ; write_spice_subckt_to_file ( fp , module_manager , mem_module ) ; fp << std :: endl ; break ; } case CIRCUIT_MODEL_DESIGN_RRAM : break ; default : VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " , circuit_lib . model_name ( mux_model ) . c_str ( ) ) ; exit ( 1 ) ; } }
Generate Verilog modules for the memories that are used
 by multiplexers
Generate Verilog modules for the memories that are used by multiplexers
/* Multiplexers built with different technology is in different organization */ /* Generate module name */ /* Write the module content in Verilog format */ /* Add an empty line as a splitter */ /* We do not need a memory submodule for RRAM MUX,
     * RRAM are embedded in the datapath  
     * TODO: generate local encoders for RRAM-based multiplexers here!!!
     */