openfpga/src/fpga_spice/spice_buffer.cpp
/********************************************************************
 * Generate the SPICE subckt for an buffer 
 * which consists of multiple stage of inverters
 *******************************************************************/
Generate the SPICE subckt for an buffer
which consists of multiple stage of inverters
Generate the SPICE subckt for an buffer which consists of multiple stage of inverters
int print_spice_buffer_subckt(std::fstream& fp,
                              const ModuleManager& module_manager,
                              const ModuleId& module_id,
                              const CircuitLibrary& circuit_lib,
                              const CircuitModelId& circuit_model,
                              const TechnologyLibrary& tech_lib,
                              const TechnologyModelId& tech_model) {
  int status = CMD_EXEC_SUCCESS;
  if (true == circuit_lib.is_power_gated(circuit_model)) {
    status = print_spice_powergated_buffer_subckt(fp,
                                                  module_manager, module_id,
                                                  circuit_lib, circuit_model,
                                                  tech_lib, tech_model);
  } else { 
    VTR_ASSERT_SAFE(false == circuit_lib.is_power_gated(circuit_model));
    status = print_spice_regular_buffer_subckt(fp,
                                               module_manager, module_id,
                                               circuit_lib, circuit_model,
                                               tech_lib, tech_model);
  }
  return status;
}
int print_spice_buffer_subckt ( std :: fstream & fp , const ModuleManager & module_manager , const ModuleId & module_id , const CircuitLibrary & circuit_lib , const CircuitModelId & circuit_model , const TechnologyLibrary & tech_lib , const TechnologyModelId & tech_model ) { int status = CMD_EXEC_SUCCESS ; if ( true == circuit_lib . is_power_gated ( circuit_model ) ) { status = print_spice_powergated_buffer_subckt ( fp , module_manager , module_id , circuit_lib , circuit_model , tech_lib , tech_model ) ; } else { VTR_ASSERT_SAFE ( false == circuit_lib . is_power_gated ( circuit_model ) ) ; status = print_spice_regular_buffer_subckt ( fp , module_manager , module_id , circuit_lib , circuit_model , tech_lib , tech_model ) ; } return status ; }
Generate the SPICE subckt for an buffer
 which consists of multiple stage of inverters
Generate the SPICE subckt for an buffer which consists of multiple stage of inverters