openfpga/src/utils/lut_utils.cpp
/********************************************************************
 * Generate bitstream for a fracturable LUT (also applicable to single-output LUT)
 * Check type of truth table of each mapped logical block
 * if it is on-set, we give a all 0 base bitstream
 * if it is off-set, we give a all 1 base bitstream
 *******************************************************************/
Generate bitstream for a fracturable LUT (also applicable to single-output LUT)
Check type of truth table of each mapped logical block
if it is on-set, we give a all 0 base bitstream
if it is off-set, we give a all 1 base bitstream
Generate bitstream for a fracturable LUT ( also applicable to single - output LUT ) Check type of truth table of each mapped logical block if it is on - set we give a all 0 base bitstream if it is off - set we give a all 1 base bitstream
std::vector<bool> build_frac_lut_bitstream(const CircuitLibrary& circuit_lib,
                                           const MuxGraph& lut_mux_graph, 
                                           const VprDeviceAnnotation& device_annotation, 
                                           const std::map<const t_pb_graph_pin*, AtomNetlist::TruthTable>& truth_tables,
                                           const size_t& default_sram_bit_value) {
  std::vector<bool> lut_bitstream(lut_mux_graph.num_inputs(), default_sram_bit_value);
  for (const std::pair<const t_pb_graph_pin*, AtomNetlist::TruthTable>& element : truth_tables) {
    CircuitPortId lut_model_output_port = device_annotation.pb_circuit_port(element.first->port);
    size_t lut_frac_level = circuit_lib.port_lut_frac_level(lut_model_output_port);
    if (size_t(-1) == lut_frac_level) {
      lut_frac_level = lut_mux_graph.num_levels();
    }
    size_t lut_output_mask = circuit_lib.port_lut_output_mask(lut_model_output_port)[element.first->pin_number];
    std::vector<bool> temp_bitstream = build_single_output_lut_bitstream(element.second, lut_mux_graph, default_sram_bit_value); 
    size_t length_of_temp_bitstream_to_copy = (size_t)pow(2., (double)(lut_frac_level)); 
    size_t bitstream_offset = length_of_temp_bitstream_to_copy * lut_output_mask; 
    VTR_ASSERT(bitstream_offset < lut_bitstream.size());
    VTR_ASSERT(bitstream_offset + length_of_temp_bitstream_to_copy <= lut_bitstream.size());
    for (size_t bit = bitstream_offset; bit < bitstream_offset + length_of_temp_bitstream_to_copy; ++bit) {
      lut_bitstream[bit] = temp_bitstream[bit];
    }
  }
  return lut_bitstream; 
}
std :: vector < bool > build_frac_lut_bitstream ( const CircuitLibrary & circuit_lib , const MuxGraph & lut_mux_graph , const VprDeviceAnnotation & device_annotation , const std :: map < const t_pb_graph_pin * , AtomNetlist :: TruthTable > & truth_tables , const size_t & default_sram_bit_value ) { std :: vector < bool > lut_bitstream ( lut_mux_graph . num_inputs ( ) , default_sram_bit_value ) ; for ( const std :: pair < const t_pb_graph_pin * , AtomNetlist :: TruthTable > & element : truth_tables ) { CircuitPortId lut_model_output_port = device_annotation . pb_circuit_port ( element . first -> port ) ; size_t lut_frac_level = circuit_lib . port_lut_frac_level ( lut_model_output_port ) ; if ( size_t ( -1 ) == lut_frac_level ) { lut_frac_level = lut_mux_graph . num_levels ( ) ; } size_t lut_output_mask = circuit_lib . port_lut_output_mask ( lut_model_output_port ) [ element . first -> pin_number ] ; std :: vector < bool > temp_bitstream = build_single_output_lut_bitstream ( element . second , lut_mux_graph , default_sram_bit_value ) ; size_t length_of_temp_bitstream_to_copy = ( size_t ) pow ( 2. , ( double ) ( lut_frac_level ) ) ; size_t bitstream_offset = length_of_temp_bitstream_to_copy * lut_output_mask ; VTR_ASSERT ( bitstream_offset < lut_bitstream . size ( ) ) ; VTR_ASSERT ( bitstream_offset + length_of_temp_bitstream_to_copy <= lut_bitstream . size ( ) ) ; for ( size_t bit = bitstream_offset ; bit < bitstream_offset + length_of_temp_bitstream_to_copy ; ++ bit ) { lut_bitstream [ bit ] = temp_bitstream [ bit ] ; } } return lut_bitstream ; }
Generate bitstream for a fracturable LUT (also applicable to single-output LUT)
 Check type of truth table of each mapped logical block
 if it is on-set, we give a all 0 base bitstream
 if it is off-set, we give a all 1 base bitstream
Generate bitstream for a fracturable LUT ( also applicable to single - output LUT ) Check type of truth table of each mapped logical block if it is on - set we give a all 0 base bitstream if it is off - set we give a all 1 base bitstream
/* Initialization */ /* Find the corresponding circuit model output port and assoicated lut_output_mask */ /* By default, lut_frac_level will be the lut_size, i.e., number of levels of the mux graph */ /* Find the corresponding circuit model output port and assoicated lut_output_mask */ /* Decode lut sram bits */ /* Depending on the frac-level, we get the location(starting/end points) of sram bits */ /* Ensure the offset is in range */ /* Print debug information 
    bool verbose = true;
    VTR_LOGV(verbose, "Full truth table\n");
    for (const std::string& tt_line : truth_table_to_string(element.second)) {
      VTR_LOGV(verbose, "\t%s\n", tt_line.c_str());
    }
    VTR_LOGV(verbose, "\n");

    VTR_LOGV(verbose, "Bitstream (size = %ld)\n", temp_bitstream.size());
    for (const bool& bit : temp_bitstream) {
      if (true == bit) {
        VTR_LOGV(verbose, "1");
      } else {
        VTR_ASSERT(false == bit);
        VTR_LOGV(verbose, "0");
      }
    }
    VTR_LOGV(verbose, "\n");

    VTR_LOGV(verbose, "Bitstream offset = %d\n", bitstream_offset);
    VTR_LOGV(verbose, "Bitstream length to be used = %d\n", length_of_temp_bitstream_to_copy);
     */ /* Copy to the segment of bitstream */