openfpga/src/fabric/build_top_module_memory.cpp
/*********************************************************************
 * Add the port-to-port connection between all the memory modules 
 * and their parent module
 *
 * Create nets to wire the control signals of memory module to 
 *    the configuration ports of primitive module
 *
 * Configuration Chain 
 * -------------------
 *
 *        config_bus (head)   config_bus (tail) 
 *            |                   ^
 * primitive  |                   |
 *   +---------------------------------------------+
 *   |        |                   |                |
 *   |        v                   |                |
 *   |  +-------------------------------------+    |
 *   |  |        CMOS-based Memory Modules    |    |
 *   |  +-------------------------------------+    |
 *   |        |                   |                |
 *   |        v                   v                |
 *   |     sram_out             sram_outb          |
 *   |                                             |
 *   +---------------------------------------------+
 *
 * Memory bank 
 * -----------
 *
 *        config_bus (BL)   config_bus (WL) 
 *            |                   |
 * primitive  |                   |
 *   +---------------------------------------------+
 *   |        |                   |                |
 *   |        v                   v                |
 *   |  +-------------------------------------+    |
 *   |  |        CMOS-based Memory Modules    |    |
 *   |  +-------------------------------------+    |
 *   |        |                   |                |
 *   |        v                   v                |
 *   |     sram_out             sram_outb          |
 *   |                                             |
 *   +---------------------------------------------+
 *
 **********************************************************************/
Add the port-to-port connection between all the memory modules
and their parent module

Create nets to wire the control signals of memory module to
the configuration ports of primitive module

Configuration Chain



Memory bank


Add the port - to - port connection between all the memory modules and their parent module Create nets to wire the control signals of memory module to the configuration ports of primitive module Configuration Chain Memory bank
static 
void add_top_module_nets_cmos_memory_config_bus(ModuleManager& module_manager,
                                                DecoderLibrary& decoder_lib,
                                                const ModuleId& parent_module,
                                                const ConfigProtocol& config_protocol, 
                                                const vtr::vector<ConfigRegionId, size_t>& num_config_bits) {
  switch (config_protocol.type()) {
  case CONFIG_MEM_STANDALONE:
    add_module_nets_cmos_flatten_memory_config_bus(module_manager, parent_module,
                                                   config_protocol.type(), CIRCUIT_MODEL_PORT_BL);
    add_module_nets_cmos_flatten_memory_config_bus(module_manager, parent_module,
                                                   config_protocol.type(), CIRCUIT_MODEL_PORT_WL);
    break;
  case CONFIG_MEM_SCAN_CHAIN: {
    add_top_module_nets_cmos_memory_chain_config_bus(module_manager, parent_module, config_protocol);
    break;
  }
  case CONFIG_MEM_MEMORY_BANK:
    add_top_module_nets_cmos_memory_bank_config_bus(module_manager, decoder_lib, parent_module, num_config_bits);
    break;
  case CONFIG_MEM_FRAME_BASED:
    add_top_module_nets_cmos_memory_frame_config_bus(module_manager, decoder_lib, parent_module, num_config_bits);
    break;
  default:
    VTR_LOGF_ERROR(__FILE__, __LINE__,
                   "Invalid type of SRAM organization!\n");
    exit(1);
  }
}
static void add_top_module_nets_cmos_memory_config_bus ( ModuleManager & module_manager , DecoderLibrary & decoder_lib , const ModuleId & parent_module , const ConfigProtocol & config_protocol , const vtr :: vector < ConfigRegionId , size_t > & num_config_bits ) { switch ( config_protocol . type ( ) ) { case CONFIG_MEM_STANDALONE : add_module_nets_cmos_flatten_memory_config_bus ( module_manager , parent_module , config_protocol . type ( ) , CIRCUIT_MODEL_PORT_BL ) ; add_module_nets_cmos_flatten_memory_config_bus ( module_manager , parent_module , config_protocol . type ( ) , CIRCUIT_MODEL_PORT_WL ) ; break ; case CONFIG_MEM_SCAN_CHAIN : { add_top_module_nets_cmos_memory_chain_config_bus ( module_manager , parent_module , config_protocol ) ; break ; } case CONFIG_MEM_MEMORY_BANK : add_top_module_nets_cmos_memory_bank_config_bus ( module_manager , decoder_lib , parent_module , num_config_bits ) ; break ; case CONFIG_MEM_FRAME_BASED : add_top_module_nets_cmos_memory_frame_config_bus ( module_manager , decoder_lib , parent_module , num_config_bits ) ; break ; default : VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " ) ; exit ( 1 ) ; } }
Add the port-to-port connection between all the memory modules
 and their parent module
Add the port - to - port connection between all the memory modules and their parent module