openfpga/src/fpga_spice/spice_grid.cpp
/*****************************************************************************
 * This function will create a Verilog file and print out a Verilog netlist 
 * for a type of physical block 
 *
 * For IO blocks: 
 * The param 'border_side' is required, which is specify which side of fabric
 * the I/O block locates at.
 *****************************************************************************/
This function will create a Verilog file and print out a Verilog netlist
for a type of physical block

For IO blocks:
The param 'border_side' is required, which is specify which side of fabric
the I/O block locates at.
This function will create a Verilog file and print out a Verilog netlist for a type of physical block For IO blocks : The param ' border_side ' is required which is specify which side of fabric the I / O block locates at .
static 
void print_spice_physical_tile_netlist(NetlistManager& netlist_manager,
                                       const ModuleManager& module_manager,
                                       const std::string& subckt_dir,
                                       t_physical_tile_type_ptr phy_block_type,
                                       const e_side& border_side) {
  if (true == is_io_type(phy_block_type)) {
    VTR_ASSERT(NUM_SIDES != border_side);
  }
  std::string spice_fname(subckt_dir 
                          + generate_grid_block_netlist_name(std::string(GRID_MODULE_NAME_PREFIX) + std::string(phy_block_type->name), 
                                                             is_io_type(phy_block_type), 
                                                             border_side, 
                                                             std::string(SPICE_NETLIST_FILE_POSTFIX))
                           );
  if (true == is_io_type(phy_block_type)) {
    SideManager side_manager(border_side);
    VTR_LOG("Writing SPICE Netlist '%s' for physical tile '%s' at %s side ...",
            spice_fname.c_str(), phy_block_type->name, 
            side_manager.c_str());
  } else { 
    VTR_LOG("Writing SPICE Netlist '%s' for physical_tile '%s'...",
            spice_fname.c_str(), phy_block_type->name);
  }
  std::fstream fp;
  fp.open(spice_fname, std::fstream::out | std::fstream::trunc);
  check_file_stream(spice_fname.c_str(), fp);
  print_spice_file_header(fp, std::string("SPICE subckts for physical tile: " + std::string(phy_block_type->name) + "]")); 
  std::string grid_module_name = generate_grid_block_module_name(std::string(GRID_SPICE_FILE_NAME_PREFIX), std::string(phy_block_type->name), is_io_type(phy_block_type), border_side);
  ModuleId grid_module = module_manager.find_module(grid_module_name); 
  VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
  print_spice_comment(fp, std::string("BEGIN Grid SPICE subckt: " + module_manager.module_name(grid_module)));
  write_spice_subckt_to_file(fp, module_manager, grid_module);
  print_spice_comment(fp, std::string("END Grid SPICE subckt: " + module_manager.module_name(grid_module)));
  fp << std::endl;
  fp.close();
  NetlistId nlist_id = netlist_manager.add_netlist(spice_fname);
  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
  netlist_manager.set_netlist_type(nlist_id, NetlistManager::LOGIC_BLOCK_NETLIST);
  VTR_LOG("Done\n");
}
static void print_spice_physical_tile_netlist ( NetlistManager & netlist_manager , const ModuleManager & module_manager , const std :: string & subckt_dir , t_physical_tile_type_ptr phy_block_type , const e_side & border_side ) { if ( true == is_io_type ( phy_block_type ) ) { VTR_ASSERT ( NUM_SIDES != border_side ) ; } std :: string spice_fname ( subckt_dir + generate_grid_block_netlist_name ( std :: string ( GRID_MODULE_NAME_PREFIX ) + std :: string ( phy_block_type -> name ) , is_io_type ( phy_block_type ) , border_side , std :: string ( SPICE_NETLIST_FILE_POSTFIX ) ) ) ; if ( true == is_io_type ( phy_block_type ) ) { SideManager side_manager ( border_side ) ; VTR_LOG ( " " , spice_fname . c_str ( ) , phy_block_type -> name , side_manager . c_str ( ) ) ; } else { VTR_LOG ( " " , spice_fname . c_str ( ) , phy_block_type -> name ) ; } std :: fstream fp ; fp . open ( spice_fname , std :: fstream :: out | std :: fstream :: trunc ) ; check_file_stream ( spice_fname . c_str ( ) , fp ) ; print_spice_file_header ( fp , std :: string ( " " + std :: string ( phy_block_type -> name ) + " " ) ) ; std :: string grid_module_name = generate_grid_block_module_name ( std :: string ( GRID_SPICE_FILE_NAME_PREFIX ) , std :: string ( phy_block_type -> name ) , is_io_type ( phy_block_type ) , border_side ) ; ModuleId grid_module = module_manager . find_module ( grid_module_name ) ; VTR_ASSERT ( true == module_manager . valid_module_id ( grid_module ) ) ; print_spice_comment ( fp , std :: string ( " " + module_manager . module_name ( grid_module ) ) ) ; write_spice_subckt_to_file ( fp , module_manager , grid_module ) ; print_spice_comment ( fp , std :: string ( " " + module_manager . module_name ( grid_module ) ) ) ; fp << std :: endl ; fp . close ( ) ; NetlistId nlist_id = netlist_manager . add_netlist ( spice_fname ) ; VTR_ASSERT ( NetlistId :: INVALID ( ) != nlist_id ) ; netlist_manager . set_netlist_type ( nlist_id , NetlistManager :: LOGIC_BLOCK_NETLIST ) ; VTR_LOG ( " \n " ) ; }
This function will create a Verilog file and print out a Verilog netlist
 for a type of physical block
This function will create a Verilog file and print out a Verilog netlist for a type of physical block
/* Check code: if this is an IO block, the border side MUST be valid */ /* Give a name to the Verilog netlist */ /* Create the file name for Verilog */ /* Echo status */ /* Create the file stream */ /* Create a Verilog Module for the top-level physical block, and add to module manager */ /* Write the spice module */ /* Add an empty line as a splitter */ /* Close file handler */ /* Add fname to the netlist name list */