openfpga/src/fpga_spice/spice_subckt_writer.cpp
/********************************************************************
 * Print a SPICE wire connection 
 * We search all the sources of the net, 
 * if we find a module input, we try to find a module output 
 * among the sinks of the net
 * If we find such a pair, we print a wire connection 
 *******************************************************************/
Print a SPICE wire connection
We search all the sources of the net,
if we find a module input, we try to find a module output
among the sinks of the net
If we find such a pair, we print a wire connection
Print a SPICE wire connection We search all the sources of the net if we find a module input we try to find a module output among the sinks of the net If we find such a pair we print a wire connection
static 
void print_spice_subckt_local_short_connection(std::fstream& fp, 
                                               const ModuleManager& module_manager,
                                               const ModuleId& module_id,
                                               const ModuleNetId& module_net) {
  VTR_ASSERT(true == valid_file_stream(fp));
  for (ModuleNetSrcId net_src : module_manager.module_net_sources(module_id, module_net)) {
    ModuleId src_module = module_manager.net_source_modules(module_id, module_net)[net_src];
    if (module_id != src_module) {
      continue;
    }
    print_spice_comment(fp, std::string("Net source id " + std::to_string(size_t(net_src))));
    ModulePortId src_port_id = module_manager.net_source_ports(module_id, module_net)[net_src];
    size_t src_pin = module_manager.net_source_pins(module_id, module_net)[net_src];
    BasicPort src_port(module_manager.module_port(module_id, src_port_id).get_name(), src_pin, src_pin);
    for (ModuleNetSinkId net_sink : module_manager.module_net_sinks(module_id, module_net)) {
      ModuleId sink_module = module_manager.net_sink_modules(module_id, module_net)[net_sink];
      if (module_id != sink_module) {
        continue;
      }
      print_spice_comment(fp, std::string("Net sink id " + std::to_string(size_t(net_sink))));
      ModulePortId sink_port_id = module_manager.net_sink_ports(module_id, module_net)[net_sink];
      size_t sink_pin = module_manager.net_sink_pins(module_id, module_net)[net_sink];
      BasicPort sink_port(module_manager.module_port(module_id, sink_port_id).get_name(), sink_pin, sink_pin);
      VTR_ASSERT(src_port.get_width() == sink_port.get_width());
      for (size_t ipin = 0; ipin < src_port.pins().size(); ++ipin) {
        BasicPort src_spice_pin(src_port.get_name(), src_port.pins()[ipin], src_port.pins()[ipin]);
        BasicPort sink_spice_pin(sink_port.get_name(), sink_port.pins()[ipin], sink_port.pins()[ipin]);
        print_spice_short_connection(fp,
                                     generate_spice_port(src_spice_pin),
                                     generate_spice_port(sink_spice_pin));
      }
    }
  }
}
static void print_spice_subckt_local_short_connection ( std :: fstream & fp , const ModuleManager & module_manager , const ModuleId & module_id , const ModuleNetId & module_net ) { VTR_ASSERT ( true == valid_file_stream ( fp ) ) ; for ( ModuleNetSrcId net_src : module_manager . module_net_sources ( module_id , module_net ) ) { ModuleId src_module = module_manager . net_source_modules ( module_id , module_net ) [ net_src ] ; if ( module_id != src_module ) { continue ; } print_spice_comment ( fp , std :: string ( " " + std :: to_string ( size_t ( net_src ) ) ) ) ; ModulePortId src_port_id = module_manager . net_source_ports ( module_id , module_net ) [ net_src ] ; size_t src_pin = module_manager . net_source_pins ( module_id , module_net ) [ net_src ] ; BasicPort src_port ( module_manager . module_port ( module_id , src_port_id ) . get_name ( ) , src_pin , src_pin ) ; for ( ModuleNetSinkId net_sink : module_manager . module_net_sinks ( module_id , module_net ) ) { ModuleId sink_module = module_manager . net_sink_modules ( module_id , module_net ) [ net_sink ] ; if ( module_id != sink_module ) { continue ; } print_spice_comment ( fp , std :: string ( " " + std :: to_string ( size_t ( net_sink ) ) ) ) ; ModulePortId sink_port_id = module_manager . net_sink_ports ( module_id , module_net ) [ net_sink ] ; size_t sink_pin = module_manager . net_sink_pins ( module_id , module_net ) [ net_sink ] ; BasicPort sink_port ( module_manager . module_port ( module_id , sink_port_id ) . get_name ( ) , sink_pin , sink_pin ) ; VTR_ASSERT ( src_port . get_width ( ) == sink_port . get_width ( ) ) ; for ( size_t ipin = 0 ; ipin < src_port . pins ( ) . size ( ) ; ++ ipin ) { BasicPort src_spice_pin ( src_port . get_name ( ) , src_port . pins ( ) [ ipin ] , src_port . pins ( ) [ ipin ] ) ; BasicPort sink_spice_pin ( sink_port . get_name ( ) , sink_port . pins ( ) [ ipin ] , sink_port . pins ( ) [ ipin ] ) ; print_spice_short_connection ( fp , generate_spice_port ( src_spice_pin ) , generate_spice_port ( sink_spice_pin ) ) ; } } } }
Print a SPICE wire connection
 We search all the sources of the net,
 if we find a module input, we try to find a module output
 among the sinks of the net
 If we find such a pair, we print a wire connection
Print a SPICE wire connection We search all the sources of the net if we find a module input we try to find a module output among the sinks of the net If we find such a pair we print a wire connection
/* Ensure a valid file stream */ /* Find the source port and pin information */ /* We have found a module input, now check all the sink modules of the net */ /* Find the sink port and pin information */ /* We need to print a wire connection here */