openfpga/src/fpga_sdc/configure_port_sdc_writer.cpp
/********************************************************************
 * Break combinational loops in FPGA fabric, which mainly come from
 * the configure ports of each programmable module. 
 * To handle this, we disable the configure ports of 
 *   - routing multiplexers
 *   - other circuit model that has SRAM ports
 *******************************************************************/
Break combinational loops in FPGA fabric, which mainly come from
the configure ports of each programmable module.
To handle this, we disable the configure ports of
- routing multiplexers
- other circuit model that has SRAM ports
Break combinational loops in FPGA fabric which mainly come from the configure ports of each programmable module . To handle this we disable the configure ports of - routing multiplexers - other circuit model that has SRAM ports
int print_sdc_disable_timing_configure_ports(const std::string& sdc_fname,
                                             const bool& flatten_names,
                                             const MuxLibrary& mux_lib,
                                             const CircuitLibrary& circuit_lib,
                                             const ModuleManager& module_manager,
                                             const bool& verbose) {
  create_directory(find_path_dir_name(sdc_fname));
  std::string timer_message = std::string("Write SDC to disable timing on configuration outputs of programmable cells for P&R flow '") + sdc_fname + std::string("'");
  vtr::ScopedStartFinishTimer timer(timer_message);
  std::fstream fp;
  fp.open(sdc_fname, std::fstream::out | std::fstream::trunc);
  check_file_stream(sdc_fname.c_str(), fp);
  print_sdc_file_header(fp, std::string("Disable configuration outputs of all the programmable cells for PnR"));
  std::string top_module_name = generate_fpga_top_module_name();
  ModuleId top_module = module_manager.find_module(top_module_name);
  VTR_ASSERT(true == module_manager.valid_module_id(top_module));
  VTR_LOGV(verbose, "Write disable timing for Look-Up Tables...");
  if (CMD_EXEC_FATAL_ERROR == print_sdc_disable_lut_configure_ports(fp,
                                                                    flatten_names,
                                                                    circuit_lib,
                                                                    module_manager,
                                                                    top_module)) {
    VTR_LOGF_ERROR(__FILE__, __LINE__, 
                   "Fatal errors occurred\n");
    return CMD_EXEC_FATAL_ERROR;
  }
  VTR_LOGV(verbose, "Done\n");
  VTR_LOGV(verbose, "Write disable timing for routing multiplexers...");
  if (CMD_EXEC_FATAL_ERROR == print_sdc_disable_routing_multiplexer_configure_ports(fp,
                                                                                    flatten_names,
                                                                                    mux_lib,
                                                                                    circuit_lib,
                                                                                    module_manager,
                                                                                    top_module)) {
    VTR_LOGF_ERROR(__FILE__, __LINE__, 
                   "Fatal errors occurred\n");
    return CMD_EXEC_FATAL_ERROR;
  }
  VTR_LOGV(verbose, "Done\n");
  VTR_LOGV(verbose, "Write disable timing for other programmable modules...");
  if (CMD_EXEC_FATAL_ERROR == print_sdc_disable_non_mux_circuit_configure_ports(fp,
                                                                                flatten_names,
                                                                                circuit_lib,
                                                                                module_manager,
                                                                                top_module)) {
    VTR_LOGF_ERROR(__FILE__, __LINE__, 
                   "Fatal errors occurred\n");
    return CMD_EXEC_FATAL_ERROR;
  }
  VTR_LOGV(verbose, "Done\n");
  fp.close();
  return CMD_EXEC_SUCCESS;
}
int print_sdc_disable_timing_configure_ports ( const std :: string & sdc_fname , const bool & flatten_names , const MuxLibrary & mux_lib , const CircuitLibrary & circuit_lib , const ModuleManager & module_manager , const bool & verbose ) { create_directory ( find_path_dir_name ( sdc_fname ) ) ; std :: string timer_message = std :: string ( " " ) + sdc_fname + std :: string ( " " ) ; vtr :: ScopedStartFinishTimer timer ( timer_message ) ; std :: fstream fp ; fp . open ( sdc_fname , std :: fstream :: out | std :: fstream :: trunc ) ; check_file_stream ( sdc_fname . c_str ( ) , fp ) ; print_sdc_file_header ( fp , std :: string ( " " ) ) ; std :: string top_module_name = generate_fpga_top_module_name ( ) ; ModuleId top_module = module_manager . find_module ( top_module_name ) ; VTR_ASSERT ( true == module_manager . valid_module_id ( top_module ) ) ; VTR_LOGV ( verbose , " " ) ; if ( CMD_EXEC_FATAL_ERROR == print_sdc_disable_lut_configure_ports ( fp , flatten_names , circuit_lib , module_manager , top_module ) ) { VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " ) ; return CMD_EXEC_FATAL_ERROR ; } VTR_LOGV ( verbose , " \n " ) ; VTR_LOGV ( verbose , " " ) ; if ( CMD_EXEC_FATAL_ERROR == print_sdc_disable_routing_multiplexer_configure_ports ( fp , flatten_names , mux_lib , circuit_lib , module_manager , top_module ) ) { VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " ) ; return CMD_EXEC_FATAL_ERROR ; } VTR_LOGV ( verbose , " \n " ) ; VTR_LOGV ( verbose , " " ) ; if ( CMD_EXEC_FATAL_ERROR == print_sdc_disable_non_mux_circuit_configure_ports ( fp , flatten_names , circuit_lib , module_manager , top_module ) ) { VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " ) ; return CMD_EXEC_FATAL_ERROR ; } VTR_LOGV ( verbose , " \n " ) ; fp . close ( ) ; return CMD_EXEC_SUCCESS ; }
Break combinational loops in FPGA fabric, which mainly come from
 the configure ports of each programmable module.
Break combinational loops in FPGA fabric which mainly come from the configure ports of each programmable module .
/* Create the directory */ /* Start time count */ /* Create the file stream */ /* Generate the descriptions*/ /* Disable timing for the configure ports of all the Look-Up Tables */ /* Disable timing for the configure ports of all the routing multiplexer */ /* Disable timing for the other programmable circuit models */ /* Close file handler */