src/cpu/testers/traffic_gen/dram_rot_gen.hh
/**
     * Create a DRAM address sequence generator.
     * This sequence generator will rotate through:
     * 1) Banks per rank
     * 2) Command type (if applicable)
     * 3) Ranks per channel
     *
     * @param obj SimObject owning this sequence generator
     * @param requestor_id RequestorID related to the memory requests
     * @param _duration duration of this state before transitioning
     * @param start_addr Start address
     * @param end_addr End address
     * @param _blocksize Size used for transactions injected
     * @param cacheline_size cache line size in the system
     * @param min_period Lower limit of random inter-transaction time
     * @param max_period Upper limit of random inter-transaction time
     * @param read_percent Percent of transactions that are reads
     * @param data_limit Upper limit on how much data to read/write
     * @param num_seq_pkts Number of packets per stride, each of _blocksize
     * @param page_size Page size (bytes) used in the DRAM
     * @param nbr_of_banks_DRAM Total number of banks in DRAM
     * @param nbr_of_banks_util Number of banks to utilized,
     *                          for N banks, we will use banks: 0->(N-1)
     * @param nbr_of_ranks Number of ranks utilized,
     * @param addr_mapping Address mapping to be used,
     *                     assumes single channel system
     */
Create a DRAM address sequence generator.
This sequence generator will rotate through:
1) Banks per rank
2) Command type (if applicable)
3) Ranks per channel


Create a DRAM address sequence generator . This sequence generator will rotate through : 1 ) Banks per rank 2 ) Command type ( if applicable ) 3 ) Ranks per channel
DramRotGen(SimObject &obj, RequestorID requestor_id, Tick _duration,
            Addr start_addr, Addr end_addr,
            Addr _blocksize, Addr cacheline_size,
            Tick min_period, Tick max_period,
            uint8_t read_percent, Addr data_limit,
            unsigned int num_seq_pkts, unsigned int page_size,
            unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util,
            enums::AddrMap addr_mapping,
            unsigned int nbr_of_ranks,
            unsigned int max_seq_count_per_rank)
        : DramGen(obj, requestor_id, _duration, start_addr, end_addr,
          _blocksize, cacheline_size, min_period, max_period,
          read_percent, data_limit,
          num_seq_pkts, page_size, nbr_of_banks_DRAM,
          nbr_of_banks_util, addr_mapping,
          nbr_of_ranks),
          maxSeqCountPerRank(max_seq_count_per_rank),
          nextSeqCount(0)
    {
        if (readPercent != 50  && readPercent != 100 && readPercent != 0) {
           fatal("%s: Unsupported read percentage for DramRotGen: %d",
                 _name, readPercent);
        }
    }
DramRotGen ( SimObject & obj , RequestorID requestor_id , Tick _duration , Addr start_addr , Addr end_addr , Addr _blocksize , Addr cacheline_size , Tick min_period , Tick max_period , uint8_t read_percent , Addr data_limit , unsigned int num_seq_pkts , unsigned int page_size , unsigned int nbr_of_banks_DRAM , unsigned int nbr_of_banks_util , enums :: AddrMap addr_mapping , unsigned int nbr_of_ranks , unsigned int max_seq_count_per_rank ) : DramGen ( obj , requestor_id , _duration , start_addr , end_addr , _blocksize , cacheline_size , min_period , max_period , read_percent , data_limit , num_seq_pkts , page_size , nbr_of_banks_DRAM , nbr_of_banks_util , addr_mapping , nbr_of_ranks ) , maxSeqCountPerRank ( max_seq_count_per_rank ) , nextSeqCount ( 0 ) { if ( readPercent != 50 && readPercent != 100 && readPercent != 0 ) { fatal ( " " , _name , readPercent ) ; } }
Create a DRAM address sequence generator.
Create a DRAM address sequence generator .
// Rotating traffic generation can only support a read // percentage of 0, 50, or 100