openfpga/src/fpga_sdc/analysis_sdc_grid_writer.cpp
/********************************************************************
 * Recursively visit all the pb_types in the hierarchy 
 * and disable all the ports
 *
 * Note: it is a must to disable all the ports in all the child pb_types!
 * This can prohibit timing analyzer to consider any FF-to-FF path or 
 * combinatinal path inside an unused grid, when finding critical paths!!!
 *******************************************************************/
Recursively visit all the pb_types in the hierarchy
and disable all the ports

it is a must to disable all the ports in all the child pb_types.
This can prohibit timing analyzer to consider any FF-to-FF path or
combinatinal path inside an unused grid, when finding critical paths
Recursively visit all the pb_types in the hierarchy and disable all the ports it is a must to disable all the ports in all the child pb_types . This can prohibit timing analyzer to consider any FF - to - FF path or combinatinal path inside an unused grid when finding critical paths
static 
void rec_print_analysis_sdc_disable_unused_pb_graph_nodes(std::fstream& fp, 
                                                          const VprDeviceAnnotation& device_annotation,
                                                          const ModuleManager& module_manager,
                                                          const ModuleId& parent_module,
                                                          const std::string& hierarchy_name,
                                                          t_pb_graph_node* physical_pb_graph_node) {
  t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type;
  valid_file_stream(fp);
  fp << "#######################################" << std::endl; 
  fp << "# Disable all the ports for pb_graph_node " << physical_pb_graph_node->pb_type->name << "[" << physical_pb_graph_node->placement_index << "]" << std::endl;
  fp << "#######################################" << std::endl; 
  fp << "set_disable_timing ";
  fp << hierarchy_name; 
  fp << "*";
  fp << std::endl;
  if (true == is_primitive_pb_type(physical_pb_type)) {
    return;
  }
  t_mode* physical_mode = device_annotation.physical_mode(physical_pb_type);
  for (int ichild = 0; ichild < physical_mode->num_pb_type_children; ++ichild) {
    std::string child_module_name = generate_physical_block_module_name(&(physical_mode->pb_type_children[ichild]));
    ModuleId child_module = module_manager.find_module(child_module_name);
    VTR_ASSERT(true == module_manager.valid_module_id(child_module));
    for (int inst = 0; inst < physical_mode->pb_type_children[ichild].num_pb; ++inst) {
      std::string child_instance_name = module_manager.instance_name(parent_module, child_module, module_manager.child_module_instances(parent_module, child_module)[inst]);
      VTR_ASSERT(false == child_instance_name.empty()); 
      std::string updated_hierarchy_name = hierarchy_name + child_instance_name + std::string("/");
      rec_print_analysis_sdc_disable_unused_pb_graph_nodes(fp, device_annotation, module_manager, child_module, updated_hierarchy_name, 
                                                           &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ichild][inst])); 
    }
  }
}
static void rec_print_analysis_sdc_disable_unused_pb_graph_nodes ( std :: fstream & fp , const VprDeviceAnnotation & device_annotation , const ModuleManager & module_manager , const ModuleId & parent_module , const std :: string & hierarchy_name , t_pb_graph_node * physical_pb_graph_node ) { t_pb_type * physical_pb_type = physical_pb_graph_node -> pb_type ; valid_file_stream ( fp ) ; fp << " " << std :: endl ; fp << " " << physical_pb_graph_node -> pb_type -> name << " " << physical_pb_graph_node -> placement_index << " " << std :: endl ; fp << " " << std :: endl ; fp << " " ; fp << hierarchy_name ; fp << " " ; fp << std :: endl ; if ( true == is_primitive_pb_type ( physical_pb_type ) ) { return ; } t_mode * physical_mode = device_annotation . physical_mode ( physical_pb_type ) ; for ( int ichild = 0 ; ichild < physical_mode -> num_pb_type_children ; ++ ichild ) { std :: string child_module_name = generate_physical_block_module_name ( & ( physical_mode -> pb_type_children [ ichild ] ) ) ; ModuleId child_module = module_manager . find_module ( child_module_name ) ; VTR_ASSERT ( true == module_manager . valid_module_id ( child_module ) ) ; for ( int inst = 0 ; inst < physical_mode -> pb_type_children [ ichild ] . num_pb ; ++ inst ) { std :: string child_instance_name = module_manager . instance_name ( parent_module , child_module , module_manager . child_module_instances ( parent_module , child_module ) [ inst ] ) ; VTR_ASSERT ( false == child_instance_name . empty ( ) ) ; std :: string updated_hierarchy_name = hierarchy_name + child_instance_name + std :: string ( " " ) ; rec_print_analysis_sdc_disable_unused_pb_graph_nodes ( fp , device_annotation , module_manager , child_module , updated_hierarchy_name , & ( physical_pb_graph_node -> child_pb_graph_nodes [ physical_mode -> index ] [ ichild ] [ inst ] ) ) ; } } }
Recursively visit all the pb_types in the hierarchy
 and disable all the ports
Recursively visit all the pb_types in the hierarchy and disable all the ports
/* Validate file stream */ /* Disable all the ports of current module (parent_module)!
   * Hierarchy name already includes the instance name of parent_module 
   */ /* Return if this is the primitive pb_type */ /* Go recursively */ /* Disable all the ports by iterating over its instance in the parent module */ /* Generate the name of the Verilog module for this child */ /* Each child may exist multiple times in the hierarchy*/ /* Must have a valid instance name!!! */