openfpga/src/fpga_spice/spice_essential_gates.cpp
/************************************************
 * Generate the SPICE netlist for a constant generator,
 * i.e., either VDD or GND
 ***********************************************/
Generate the SPICE netlist for a constant generator,
i.e., either VDD or GND
Generate the SPICE netlist for a constant generator i . e . either VDD or GND
static 
void print_spice_supply_wrapper_subckt(const ModuleManager& module_manager, 
                                       std::fstream& fp, 
                                       const size_t& const_value) {
  std::string module_name = generate_const_value_module_name(const_value);
  ModuleId const_val_module = module_manager.find_module(module_name);
  VTR_ASSERT(true == module_manager.valid_module_id(const_val_module));
  VTR_ASSERT(true == valid_file_stream(fp));
  print_spice_subckt_definition(fp, module_manager, const_val_module);
  for (const ModulePortId& module_port_id : module_manager.module_ports(const_val_module)) {
    BasicPort module_port = module_manager.module_port(const_val_module, module_port_id);
    for (const auto& pin : module_port.pins()) {
      BasicPort spice_pin(module_port.get_name(), pin, pin);
      std::string const_pin_name = std::string(SPICE_SUBCKT_VDD_PORT_NAME);
      if (0 == const_value) {
        const_pin_name = std::string(SPICE_SUBCKT_GND_PORT_NAME);
      } else {
        VTR_ASSERT(1 == const_value);
      }
      print_spice_short_connection(fp,
                                   generate_spice_port(spice_pin, true),
                                   const_pin_name);
    }
  }
  print_spice_subckt_end(fp, module_name);
}
static void print_spice_supply_wrapper_subckt ( const ModuleManager & module_manager , std :: fstream & fp , const size_t & const_value ) { std :: string module_name = generate_const_value_module_name ( const_value ) ; ModuleId const_val_module = module_manager . find_module ( module_name ) ; VTR_ASSERT ( true == module_manager . valid_module_id ( const_val_module ) ) ; VTR_ASSERT ( true == valid_file_stream ( fp ) ) ; print_spice_subckt_definition ( fp , module_manager , const_val_module ) ; for ( const ModulePortId & module_port_id : module_manager . module_ports ( const_val_module ) ) { BasicPort module_port = module_manager . module_port ( const_val_module , module_port_id ) ; for ( const auto & pin : module_port . pins ( ) ) { BasicPort spice_pin ( module_port . get_name ( ) , pin , pin ) ; std :: string const_pin_name = std :: string ( SPICE_SUBCKT_VDD_PORT_NAME ) ; if ( 0 == const_value ) { const_pin_name = std :: string ( SPICE_SUBCKT_GND_PORT_NAME ) ; } else { VTR_ASSERT ( 1 == const_value ) ; } print_spice_short_connection ( fp , generate_spice_port ( spice_pin , true ) , const_pin_name ) ; } } print_spice_subckt_end ( fp , module_name ) ; }
Generate the SPICE netlist for a constant generator,
 i.e., either VDD or GND
Generate the SPICE netlist for a constant generator i . e . either VDD or GND
/* Find the module in module manager */ /* Ensure a valid file handler*/ /* dump module definition + ports */ /* Finish dumping ports */ /* Find the only output*/ /* Put an end to the SPICE subcircuit */