openfpga/src/base/openfpga_build_fabric.cpp
/********************************************************************
 * Build the module graph for FPGA device
 *******************************************************************/
Build the module graph for FPGA device
Build the module graph for FPGA device
int build_fabric(OpenfpgaContext& openfpga_ctx,
                 const Command& cmd, const CommandContext& cmd_context) { 
  CommandOptionId opt_frame_view = cmd.option("frame_view");
  CommandOptionId opt_compress_routing = cmd.option("compress_routing");
  CommandOptionId opt_duplicate_grid_pin = cmd.option("duplicate_grid_pin");
  CommandOptionId opt_gen_random_fabric_key = cmd.option("generate_random_fabric_key");
  CommandOptionId opt_write_fabric_key = cmd.option("write_fabric_key");
  CommandOptionId opt_load_fabric_key = cmd.option("load_fabric_key");
  CommandOptionId opt_verbose = cmd.option("verbose");
  if (true == cmd_context.option_enable(cmd, opt_compress_routing)) {
    compress_routing_hierarchy(openfpga_ctx, cmd_context.option_enable(cmd, opt_verbose));
    openfpga_ctx.mutable_flow_manager().set_compress_routing(true);
  }
  VTR_LOG("\n");
  int curr_status = CMD_EXEC_SUCCESS;
  int final_status = CMD_EXEC_SUCCESS;
  FabricKey predefined_fabric_key;
  if (true == cmd_context.option_enable(cmd, opt_load_fabric_key)) {
    std::string fkey_fname = cmd_context.option_value(cmd, opt_load_fabric_key);
    VTR_ASSERT(false == fkey_fname.empty());
    predefined_fabric_key = read_xml_fabric_key(fkey_fname.c_str());
  }
  VTR_LOG("\n");
  curr_status = build_device_module_graph(openfpga_ctx.mutable_module_graph(),
                                          openfpga_ctx.mutable_decoder_lib(),
                                          const_cast<const OpenfpgaContext&>(openfpga_ctx),
                                          g_vpr_ctx.device(),
                                          cmd_context.option_enable(cmd, opt_frame_view),
                                          cmd_context.option_enable(cmd, opt_compress_routing),
                                          cmd_context.option_enable(cmd, opt_duplicate_grid_pin),
                                          predefined_fabric_key,
                                          cmd_context.option_enable(cmd, opt_gen_random_fabric_key),
                                          cmd_context.option_enable(cmd, opt_verbose));
  if (CMD_EXEC_SUCCESS != curr_status) {
    final_status = curr_status;
  }
  openfpga_ctx.mutable_io_location_map() = build_fabric_io_location_map(openfpga_ctx.module_graph(),
                                                                        g_vpr_ctx.device().grid);
  openfpga_ctx.mutable_fabric_global_port_info() = build_fabric_global_port_info(openfpga_ctx.module_graph(),
                                                                                 openfpga_ctx.arch().tile_annotations,
                                                                                 openfpga_ctx.arch().circuit_lib);
  if (true == cmd_context.option_enable(cmd, opt_write_fabric_key)) {
    std::string fkey_fname = cmd_context.option_value(cmd, opt_write_fabric_key);
    VTR_ASSERT(false == fkey_fname.empty());
    curr_status = write_fabric_key_to_xml_file(openfpga_ctx.module_graph(),
                                               fkey_fname,
                                               cmd_context.option_enable(cmd, opt_verbose));
    if (CMD_EXEC_SUCCESS != curr_status) {
      final_status = curr_status;
    }
  }
  return final_status;
}
int build_fabric ( OpenfpgaContext & openfpga_ctx , const Command & cmd , const CommandContext & cmd_context ) { CommandOptionId opt_frame_view = cmd . option ( " " ) ; CommandOptionId opt_compress_routing = cmd . option ( " " ) ; CommandOptionId opt_duplicate_grid_pin = cmd . option ( " " ) ; CommandOptionId opt_gen_random_fabric_key = cmd . option ( " " ) ; CommandOptionId opt_write_fabric_key = cmd . option ( " " ) ; CommandOptionId opt_load_fabric_key = cmd . option ( " " ) ; CommandOptionId opt_verbose = cmd . option ( " " ) ; if ( true == cmd_context . option_enable ( cmd , opt_compress_routing ) ) { compress_routing_hierarchy ( openfpga_ctx , cmd_context . option_enable ( cmd , opt_verbose ) ) ; openfpga_ctx . mutable_flow_manager ( ) . set_compress_routing ( true ) ; } VTR_LOG ( " \n " ) ; int curr_status = CMD_EXEC_SUCCESS ; int final_status = CMD_EXEC_SUCCESS ; FabricKey predefined_fabric_key ; if ( true == cmd_context . option_enable ( cmd , opt_load_fabric_key ) ) { std :: string fkey_fname = cmd_context . option_value ( cmd , opt_load_fabric_key ) ; VTR_ASSERT ( false == fkey_fname . empty ( ) ) ; predefined_fabric_key = read_xml_fabric_key ( fkey_fname . c_str ( ) ) ; } VTR_LOG ( " \n " ) ; curr_status = build_device_module_graph ( openfpga_ctx . mutable_module_graph ( ) , openfpga_ctx . mutable_decoder_lib ( ) , const_cast < const OpenfpgaContext & > ( openfpga_ctx ) , g_vpr_ctx . device ( ) , cmd_context . option_enable ( cmd , opt_frame_view ) , cmd_context . option_enable ( cmd , opt_compress_routing ) , cmd_context . option_enable ( cmd , opt_duplicate_grid_pin ) , predefined_fabric_key , cmd_context . option_enable ( cmd , opt_gen_random_fabric_key ) , cmd_context . option_enable ( cmd , opt_verbose ) ) ; if ( CMD_EXEC_SUCCESS != curr_status ) { final_status = curr_status ; } openfpga_ctx . mutable_io_location_map ( ) = build_fabric_io_location_map ( openfpga_ctx . module_graph ( ) , g_vpr_ctx . device ( ) . grid ) ; openfpga_ctx . mutable_fabric_global_port_info ( ) = build_fabric_global_port_info ( openfpga_ctx . module_graph ( ) , openfpga_ctx . arch ( ) . tile_annotations , openfpga_ctx . arch ( ) . circuit_lib ) ; if ( true == cmd_context . option_enable ( cmd , opt_write_fabric_key ) ) { std :: string fkey_fname = cmd_context . option_value ( cmd , opt_write_fabric_key ) ; VTR_ASSERT ( false == fkey_fname . empty ( ) ) ; curr_status = write_fabric_key_to_xml_file ( openfpga_ctx . module_graph ( ) , fkey_fname , cmd_context . option_enable ( cmd , opt_verbose ) ) ; if ( CMD_EXEC_SUCCESS != curr_status ) { final_status = curr_status ; } } return final_status ; }
Build the module graph for FPGA device
Build the module graph for FPGA device
/* Update flow manager to enable compress routing */ /* Record the execution status in curr_status for each command 
   * and summarize them in the final status
   */ /* Load fabric key from file */ /* If there is any error, final status cannot be overwritten by a success flag */ /* Build I/O location map */ /* Build fabric global port information */ /* Output fabric key if user requested */ /* If there is any error, final status cannot be overwritten by a success flag */