openfpga/src/fpga_spice/spice_buffer.cpp
/********************************************************************
 * Generate the SPICE modeling for the PMOS part of a regular inverter
 *
 * This function is created to be shared by inverter and buffer SPICE netlist writer
 *
 * Note: 
 * - This function does NOT create a file
 *   but requires a file stream created
 * - This function only output SPICE modeling for 
 *   an inverter. Any preprocessing or subckt definition should not be included!
 *******************************************************************/
Generate the SPICE modeling for the PMOS part of a regular inverter
This function is created to be shared by inverter and buffer SPICE netlist writer

- This function does NOT create a file
but requires a file stream created
- This function only output SPICE modeling for
an inverter. Any preprocessing or subckt definition should not be included!
Generate the SPICE modeling for the PMOS part of a regular inverter This function is created to be shared by inverter and buffer SPICE netlist writer - This function does NOT create a file but requires a file stream created - This function only output SPICE modeling for an inverter . Any preprocessing or subckt definition should not be included!
static 
int print_spice_regular_inverter_pmos_modeling(std::fstream& fp,
                                               const std::string& trans_name_postfix,
                                               const std::string& input_port_name,
                                               const std::string& output_port_name,
                                               const TechnologyLibrary& tech_lib,
                                               const TechnologyModelId& tech_model,
                                               const float& trans_width) {
  if (false == valid_file_stream(fp)) {
    return CMD_EXEC_FATAL_ERROR;
  }
  fp << "Xpmos_" << trans_name_postfix << " ";
  fp << output_port_name << " "; 
  fp << input_port_name << " "; 
  fp << SPICE_SUBCKT_VDD_PORT_NAME << " "; 
  fp << SPICE_SUBCKT_VDD_PORT_NAME << " "; 
  fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_PMOS) << TRANSISTOR_WRAPPER_POSTFIX; 
  fp << " W=" << std::setprecision(10) << trans_width;
  fp << "\n";
  return CMD_EXEC_SUCCESS;
}
static int print_spice_regular_inverter_pmos_modeling ( std :: fstream & fp , const std :: string & trans_name_postfix , const std :: string & input_port_name , const std :: string & output_port_name , const TechnologyLibrary & tech_lib , const TechnologyModelId & tech_model , const float & trans_width ) { if ( false == valid_file_stream ( fp ) ) { return CMD_EXEC_FATAL_ERROR ; } fp << " " << trans_name_postfix << " " ; fp << output_port_name << " " ; fp << input_port_name << " " ; fp << SPICE_SUBCKT_VDD_PORT_NAME << " " ; fp << SPICE_SUBCKT_VDD_PORT_NAME << " " ; fp << tech_lib . transistor_model_name ( tech_model , TECH_LIB_TRANSISTOR_PMOS ) << TRANSISTOR_WRAPPER_POSTFIX ; fp << " " << std :: setprecision ( 10 ) << trans_width ; fp << " \n " ; return CMD_EXEC_SUCCESS ; }
Generate the SPICE modeling for the PMOS part of a regular inverter
 This function is created to be shared by inverter and buffer SPICE netlist writer
Generate the SPICE modeling for the PMOS part of a regular inverter This function is created to be shared by inverter and buffer SPICE netlist writer
/* Write transistor pairs using the technology model */