openfpga/src/utils/check_tile_annotation.cpp
/********************************************************************
 * Check if the tile annotation is valid without any conflict with
 * circuit library content.
 * Items to check:
 * - The global port defined in tile annotation has no conflicts with 
 * the global ports which are defined in circuit library:
 *   - If a port has the same name, must ensure that its attributes are the same
 *     i.e., is_clock, is_reset, is_set
 *   - Otherwise, error out
 *******************************************************************/
Check if the tile annotation is valid without any conflict with
circuit library content.
Items to check:
- The global port defined in tile annotation has no conflicts with
the global ports which are defined in circuit library:
- If a port has the same name, must ensure that its attributes are the same
i.e., is_clock, is_reset, is_set
- Otherwise, error out
Check if the tile annotation is valid without any conflict with circuit library content . Items to check : - The global port defined in tile annotation has no conflicts with the global ports which are defined in circuit library : - If a port has the same name must ensure that its attributes are the same i . e . is_clock is_reset is_set - Otherwise error out
static 
int check_tile_annotation_conflicts_with_circuit_library(const TileAnnotation& tile_annotation,
                                                         const CircuitLibrary& circuit_lib) {
  int num_err = 0;
  std::vector<CircuitPortId> ckt_global_ports = find_circuit_library_global_ports(circuit_lib);
  for (const TileGlobalPortId& tile_global_port : tile_annotation.global_ports()) {
    for (const CircuitPortId& ckt_global_port : ckt_global_ports) {
      if (tile_annotation.global_port_name(tile_global_port) != circuit_lib.port_prefix(ckt_global_port)) {
        continue;
      }
      bool is_both_op_signal = !circuit_lib.port_is_prog(ckt_global_port);
      if (false == is_both_op_signal) {
        VTR_LOGF_ERROR(__FILE__, __LINE__,
                       "Global port '%s' in tile annotation share the same name as global port '%s' in circuit library, which is defined for programming usage!\n",
                       tile_annotation.global_port_name(tile_global_port).c_str(),
                       circuit_lib.port_prefix(ckt_global_port).c_str());
        num_err++;
      }
      bool is_clock_attr_same = (tile_annotation.global_port_is_clock(tile_global_port) != (CIRCUIT_MODEL_PORT_CLOCK == circuit_lib.port_type(ckt_global_port)));
      if (false == is_clock_attr_same) {
        VTR_LOGF_ERROR(__FILE__, __LINE__,
                       "Global port '%s' in tile annotation share the same name as global port '%s' in circuit library but has different definition as clock!\n",
                       tile_annotation.global_port_name(tile_global_port).c_str(),
                       circuit_lib.port_prefix(ckt_global_port).c_str());
        num_err++;
      }
      bool is_reset_attr_same = (tile_annotation.global_port_is_reset(tile_global_port) != circuit_lib.port_is_reset(ckt_global_port));
      if (false == is_reset_attr_same) {
        VTR_LOGF_ERROR(__FILE__, __LINE__,
                       "Global port '%s' in tile annotation share the same name as global port '%s' in circuit library but has different definition as reset!\n",
                       tile_annotation.global_port_name(tile_global_port).c_str(),
                       circuit_lib.port_prefix(ckt_global_port).c_str());
        num_err++;
      }
      bool is_set_attr_same = (tile_annotation.global_port_is_set(tile_global_port) != circuit_lib.port_is_set(ckt_global_port));
      if (false == is_set_attr_same) {
        VTR_LOGF_ERROR(__FILE__, __LINE__,
                       "Global port '%s' in tile annotation share the same name as global port '%s' in circuit library but has different definition as set!\n",
                       tile_annotation.global_port_name(tile_global_port).c_str(),
                       circuit_lib.port_prefix(ckt_global_port).c_str());
        num_err++;
      }
    }
  }
  return num_err;
}
static int check_tile_annotation_conflicts_with_circuit_library ( const TileAnnotation & tile_annotation , const CircuitLibrary & circuit_lib ) { int num_err = 0 ; std :: vector < CircuitPortId > ckt_global_ports = find_circuit_library_global_ports ( circuit_lib ) ; for ( const TileGlobalPortId & tile_global_port : tile_annotation . global_ports ( ) ) { for ( const CircuitPortId & ckt_global_port : ckt_global_ports ) { if ( tile_annotation . global_port_name ( tile_global_port ) != circuit_lib . port_prefix ( ckt_global_port ) ) { continue ; } bool is_both_op_signal = ! circuit_lib . port_is_prog ( ckt_global_port ) ; if ( false == is_both_op_signal ) { VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " , tile_annotation . global_port_name ( tile_global_port ) . c_str ( ) , circuit_lib . port_prefix ( ckt_global_port ) . c_str ( ) ) ; num_err ++ ; } bool is_clock_attr_same = ( tile_annotation . global_port_is_clock ( tile_global_port ) != ( CIRCUIT_MODEL_PORT_CLOCK == circuit_lib . port_type ( ckt_global_port ) ) ) ; if ( false == is_clock_attr_same ) { VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " , tile_annotation . global_port_name ( tile_global_port ) . c_str ( ) , circuit_lib . port_prefix ( ckt_global_port ) . c_str ( ) ) ; num_err ++ ; } bool is_reset_attr_same = ( tile_annotation . global_port_is_reset ( tile_global_port ) != circuit_lib . port_is_reset ( ckt_global_port ) ) ; if ( false == is_reset_attr_same ) { VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " , tile_annotation . global_port_name ( tile_global_port ) . c_str ( ) , circuit_lib . port_prefix ( ckt_global_port ) . c_str ( ) ) ; num_err ++ ; } bool is_set_attr_same = ( tile_annotation . global_port_is_set ( tile_global_port ) != circuit_lib . port_is_set ( ckt_global_port ) ) ; if ( false == is_set_attr_same ) { VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " , tile_annotation . global_port_name ( tile_global_port ) . c_str ( ) , circuit_lib . port_prefix ( ckt_global_port ) . c_str ( ) ) ; num_err ++ ; } } } return num_err ; }
Check if the tile annotation is valid without any conflict with
 circuit library content.
Check if the tile annotation is valid without any conflict with circuit library content .
/* All the global clock port here must be operating clock */ /* Error out if one is defined as clock while another is not */ /* Error out if one is defined as reset while another is not */ /* Error out if one is defined as set while another is not */