libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp
/********************************************************************
 * A writer to output a circuit model to XML format
 *******************************************************************/
A writer to output a circuit model to XML format
A writer to output a circuit model to XML format
static 
void write_xml_circuit_model(std::fstream& fp,
                             const char* fname,
                             const CircuitLibrary& circuit_lib,
                             const CircuitModelId& model) {
  openfpga::check_file_stream(fname, fp);
  fp << "\t\t" << "<circuit_model";
  write_xml_attribute(fp, "type", CIRCUIT_MODEL_TYPE_STRING[circuit_lib.model_type(model)]); 
  write_xml_attribute(fp, "name", circuit_lib.model_name(model).c_str()); 
  write_xml_attribute(fp, "prefix", circuit_lib.model_prefix(model).c_str()); 
  if (true == circuit_lib.model_is_default(model)) { 
    write_xml_attribute(fp, "is_default", "true"); 
  }
  if (true == circuit_lib.dump_structural_verilog(model)) { 
    write_xml_attribute(fp, "dump_structural_verilog", "true"); 
  }
  if (!circuit_lib.model_spice_netlist(model).empty()) {
    write_xml_attribute(fp, "spice_netlist", circuit_lib.model_spice_netlist(model).c_str()); 
  }
  if (!circuit_lib.model_verilog_netlist(model).empty()) {
    write_xml_attribute(fp, "verilog_netlist", circuit_lib.model_verilog_netlist(model).c_str()); 
  }
  fp << ">" << "\n";
  write_xml_design_technology(fp, fname, circuit_lib, model);
  write_xml_device_technology(fp, fname, circuit_lib, model);
  if (CIRCUIT_MODEL_INVBUF != circuit_lib.model_type(model)) {
    if (true == circuit_lib.is_input_buffered(model)) {
      fp << "\t\t\t" << "<input_buffer";
      write_xml_attribute(fp, "exist", circuit_lib.is_input_buffered(model)); 
      write_xml_attribute(fp, "circuit_model_name", circuit_lib.model_name(circuit_lib.input_buffer_model(model)).c_str()); 
      fp << "/>" << "\n";
    }
  }
  if (CIRCUIT_MODEL_INVBUF != circuit_lib.model_type(model)) {
    if (true == circuit_lib.is_output_buffered(model)) {
      fp << "\t\t\t" << "<output_buffer";
      write_xml_attribute(fp, "exist", circuit_lib.is_input_buffered(model)); 
      write_xml_attribute(fp, "circuit_model_name", circuit_lib.model_name(circuit_lib.output_buffer_model(model)).c_str()); 
      fp << "/>" << "\n";
    }
  }
  if (CIRCUIT_MODEL_LUT == circuit_lib.model_type(model)) {
    fp << "\t\t\t" << "<lut_input_buffer";
    write_xml_attribute(fp, "exist", true); 
    write_xml_attribute(fp, "circuit_model_name", circuit_lib.model_name(circuit_lib.lut_input_buffer_model(model)).c_str()); 
    fp << "/>" << "\n";
    fp << "\t\t\t" << "<lut_input_inverter";
    write_xml_attribute(fp, "exist", true); 
    write_xml_attribute(fp, "circuit_model_name", circuit_lib.model_name(circuit_lib.lut_input_inverter_model(model)).c_str()); 
    fp << "/>" << "\n";
    if (true == circuit_lib.is_lut_intermediate_buffered(model)) {
      fp << "\t\t\t" << "<lut_intermediate_buffer";
      write_xml_attribute(fp, "exist", circuit_lib.is_lut_intermediate_buffered(model)); 
      write_xml_attribute(fp, "circuit_model_name", circuit_lib.model_name(circuit_lib.lut_intermediate_buffer_model(model)).c_str()); 
      if (!circuit_lib.lut_intermediate_buffer_location_map(model).empty()) {
        write_xml_attribute(fp, "location_map", circuit_lib.lut_intermediate_buffer_location_map(model).c_str());
      }
      fp << "/>" << "\n";
    }
  }
  if ( (CIRCUIT_MODEL_LUT == circuit_lib.model_type(model)) 
    || (CIRCUIT_MODEL_MUX == circuit_lib.model_type(model)) ) {
    fp << "\t\t\t" << "<pass_gate_logic";
    write_xml_attribute(fp, "circuit_model_name", circuit_lib.model_name(circuit_lib.pass_gate_logic_model(model)).c_str()); 
    fp << "/>" << "\n";
  }
  for (const CircuitPortId& port : circuit_lib.model_ports(model)) {
    write_xml_circuit_port(fp, fname, circuit_lib, port);
  }
  if ( (CIRCUIT_MODEL_WIRE == circuit_lib.model_type(model))
    || (CIRCUIT_MODEL_CHAN_WIRE == circuit_lib.model_type(model)) ) {
    write_xml_wire_param(fp, fname, circuit_lib, model);
  }
  if (0 < circuit_lib.num_delay_info(model)) {
    write_xml_delay_matrix(fp, fname, circuit_lib, model);
  }
  fp << "\t\t" << "</circuit_model>\n";
}
static void write_xml_circuit_model ( std :: fstream & fp , const char * fname , const CircuitLibrary & circuit_lib , const CircuitModelId & model ) { openfpga :: check_file_stream ( fname , fp ) ; fp << " \t \t " << " " ; write_xml_attribute ( fp , " " , CIRCUIT_MODEL_TYPE_STRING [ circuit_lib . model_type ( model ) ] ) ; write_xml_attribute ( fp , " " , circuit_lib . model_name ( model ) . c_str ( ) ) ; write_xml_attribute ( fp , " " , circuit_lib . model_prefix ( model ) . c_str ( ) ) ; if ( true == circuit_lib . model_is_default ( model ) ) { write_xml_attribute ( fp , " " , " " ) ; } if ( true == circuit_lib . dump_structural_verilog ( model ) ) { write_xml_attribute ( fp , " " , " " ) ; } if ( ! circuit_lib . model_spice_netlist ( model ) . empty ( ) ) { write_xml_attribute ( fp , " " , circuit_lib . model_spice_netlist ( model ) . c_str ( ) ) ; } if ( ! circuit_lib . model_verilog_netlist ( model ) . empty ( ) ) { write_xml_attribute ( fp , " " , circuit_lib . model_verilog_netlist ( model ) . c_str ( ) ) ; } fp << " " << " \n " ; write_xml_design_technology ( fp , fname , circuit_lib , model ) ; write_xml_device_technology ( fp , fname , circuit_lib , model ) ; if ( CIRCUIT_MODEL_INVBUF != circuit_lib . model_type ( model ) ) { if ( true == circuit_lib . is_input_buffered ( model ) ) { fp << " \t \t \t " << " " ; write_xml_attribute ( fp , " " , circuit_lib . is_input_buffered ( model ) ) ; write_xml_attribute ( fp , " " , circuit_lib . model_name ( circuit_lib . input_buffer_model ( model ) ) . c_str ( ) ) ; fp << " " << " \n " ; } } if ( CIRCUIT_MODEL_INVBUF != circuit_lib . model_type ( model ) ) { if ( true == circuit_lib . is_output_buffered ( model ) ) { fp << " \t \t \t " << " " ; write_xml_attribute ( fp , " " , circuit_lib . is_input_buffered ( model ) ) ; write_xml_attribute ( fp , " " , circuit_lib . model_name ( circuit_lib . output_buffer_model ( model ) ) . c_str ( ) ) ; fp << " " << " \n " ; } } if ( CIRCUIT_MODEL_LUT == circuit_lib . model_type ( model ) ) { fp << " \t \t \t " << " " ; write_xml_attribute ( fp , " " , true ) ; write_xml_attribute ( fp , " " , circuit_lib . model_name ( circuit_lib . lut_input_buffer_model ( model ) ) . c_str ( ) ) ; fp << " " << " \n " ; fp << " \t \t \t " << " " ; write_xml_attribute ( fp , " " , true ) ; write_xml_attribute ( fp , " " , circuit_lib . model_name ( circuit_lib . lut_input_inverter_model ( model ) ) . c_str ( ) ) ; fp << " " << " \n " ; if ( true == circuit_lib . is_lut_intermediate_buffered ( model ) ) { fp << " \t \t \t " << " " ; write_xml_attribute ( fp , " " , circuit_lib . is_lut_intermediate_buffered ( model ) ) ; write_xml_attribute ( fp , " " , circuit_lib . model_name ( circuit_lib . lut_intermediate_buffer_model ( model ) ) . c_str ( ) ) ; if ( ! circuit_lib . lut_intermediate_buffer_location_map ( model ) . empty ( ) ) { write_xml_attribute ( fp , " " , circuit_lib . lut_intermediate_buffer_location_map ( model ) . c_str ( ) ) ; } fp << " " << " \n " ; } } if ( ( CIRCUIT_MODEL_LUT == circuit_lib . model_type ( model ) ) || ( CIRCUIT_MODEL_MUX == circuit_lib . model_type ( model ) ) ) { fp << " \t \t \t " << " " ; write_xml_attribute ( fp , " " , circuit_lib . model_name ( circuit_lib . pass_gate_logic_model ( model ) ) . c_str ( ) ) ; fp << " " << " \n " ; } for ( const CircuitPortId & port : circuit_lib . model_ports ( model ) ) { write_xml_circuit_port ( fp , fname , circuit_lib , port ) ; } if ( ( CIRCUIT_MODEL_WIRE == circuit_lib . model_type ( model ) ) || ( CIRCUIT_MODEL_CHAN_WIRE == circuit_lib . model_type ( model ) ) ) { write_xml_wire_param ( fp , fname , circuit_lib , model ) ; } if ( 0 < circuit_lib . num_delay_info ( model ) ) { write_xml_delay_matrix ( fp , fname , circuit_lib , model ) ; } fp << " \t \t " << " \n " ; }
A writer to output a circuit model to XML format
A writer to output a circuit model to XML format
/* Validate the file stream */ /* Write the definition of circuit model */ /* Write the design technology of circuit model */ /* Write the device technology of circuit model */ /* Write the input buffer information of circuit model, 
   * only applicable when this circuit model is neither inverter nor buffer
   */ /* Write the output buffer information of circuit model */ /* Write the lut input buffer information of circuit model
     * This is a mandatory attribute for LUT, so it must exist 
     */ /* Write the lut input inverter information of circuit model
     * This is a mandatory attribute for LUT, so it must exist 
     */ /* Write the lut intermediate buffer information of circuit model */ /* Write the pass-gate-logic information of circuit model */ /* Write the ports of circuit model */ /* Write the wire parasticis of circuit model */ /* Write the delay matrix of circuit model
   * Skip circuit models without delay matrices 
   */ /* Put an end to the XML definition of this circuit model */