vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp
/************************************************************************
 * Build the edges for all the SOURCE and SINKs nodes:
 * 1. create edges between SOURCE and OPINs
 ***********************************************************************/
Build the edges for all the SOURCE and SINKs nodes:
1. create edges between SOURCE and OPINs
Build the edges for all the SOURCE and SINKs nodes : 1 . create edges between SOURCE and OPINs
static 
void build_rr_graph_edges_for_source_nodes(RRGraph& rr_graph,
                                           const vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches,
                                           const DeviceGrid& grids) {
  for (const RRNodeId& node : rr_graph.nodes()) {
    if (OPIN != rr_graph.node_type(node)) {
      continue;
    }
    short xlow = rr_graph.node_xlow(node); 
    short ylow = rr_graph.node_ylow(node); 
    short src_node_class_num = get_grid_pin_class_index(grids[xlow][ylow], 
                                                        rr_graph.node_pin_num(node));
    const RRNodeId& src_node = rr_graph.find_node(xlow - grids[xlow][ylow].width_offset,
                                                  ylow - grids[xlow][ylow].height_offset,
                                                  SOURCE, src_node_class_num);
    VTR_ASSERT(true == rr_graph.valid_node_id(src_node));
    rr_graph.create_edge(src_node, node, rr_node_driver_switches[node]);
  }
}
static void build_rr_graph_edges_for_source_nodes ( RRGraph & rr_graph , const vtr :: vector < RRNodeId , RRSwitchId > & rr_node_driver_switches , const DeviceGrid & grids ) { for ( const RRNodeId & node : rr_graph . nodes ( ) ) { if ( OPIN != rr_graph . node_type ( node ) ) { continue ; } short xlow = rr_graph . node_xlow ( node ) ; short ylow = rr_graph . node_ylow ( node ) ; short src_node_class_num = get_grid_pin_class_index ( grids [ xlow ] [ ylow ] , rr_graph . node_pin_num ( node ) ) ; const RRNodeId & src_node = rr_graph . find_node ( xlow - grids [ xlow ] [ ylow ] . width_offset , ylow - grids [ xlow ] [ ylow ] . height_offset , SOURCE , src_node_class_num ) ; VTR_ASSERT ( true == rr_graph . valid_node_id ( src_node ) ) ; rr_graph . create_edge ( src_node , node , rr_node_driver_switches [ node ] ) ; } }
Build the edges for all the SOURCE and SINKs nodes:
 1. create edges between SOURCE and OPINs
Build the edges for all the SOURCE and SINKs nodes : 1 . create edges between SOURCE and OPINs
/* Bypass all the non OPIN nodes */ /* Now, we have an OPIN node, we get the source node index */ /* Create edges between SOURCE and OPINs */ /* add edges to the src_node */