pic32/libraries/DSPI/DSPI.cpp
/* ------------------------------------------------------------ */
/***	DSPI::init
**
**	Parameters:
**		irqErr		- IRQ for the SPI error interrupt
**		irqRx		- IRQ for the SPI receive interrupt
**		irqTx		- IRQ for the SPI transmit interrupt
**
**	Return Value:
**		none
**
**	Errors:
**		none
**
**	Description:
**		Initialize the object. This is called from the constructors
**		of the derived classes.
*/
:init

irqErr          - IRQ for the SPI error interrupt
irqRx           - IRQ for the SPI receive interrupt
irqTx           - IRQ for the SPI transmit interrupt

Return Value:
none

none

Initialize the object. This is called from the constructors
of the derived classes.
: init irqErr - IRQ for the SPI error interrupt irqRx - IRQ for the SPI receive interrupt irqTx - IRQ for the SPI transmit interrupt Return Value : none none Initialize the object . This is called from the constructors of the derived classes .
void
DSPI::init(uint8_t irqErr, uint8_t irqRx, uint8_t irqTx, isrFunc isrHandler) {
	pregIec = ((p32_regset *)&IEC0) + (irqErr / 32);	
	pregIfs = ((p32_regset *)&IFS0) + (irqErr / 32);	
	bitErr = 1 << (irqErr % 32);	
	bitRx  = 1 << (irqRx % 32);		
	bitTx  = 1 << (irqTx % 32);		
    isr = isrHandler;
}
void DSPI :: init ( uint8_t irqErr , uint8_t irqRx , uint8_t irqTx , isrFunc isrHandler ) { pregIec = ( ( p32_regset * ) & IEC0 ) + ( irqErr / 32 ) ; pregIfs = ( ( p32_regset * ) & IFS0 ) + ( irqErr / 32 ) ; bitErr = 1 << ( irqErr % 32 ) ; bitRx = 1 << ( irqRx % 32 ) ; bitTx = 1 << ( irqTx % 32 ) ; isr = isrHandler ; }
DSPI::init
DSPI :: init
/* The interrupt flag and enable control register addresses and
	** the bit numbers for the flag bits can be computed from the
	** IRQ numbers for the SPI port. There are 32 IRQ bits in each IFS
	** and IEC register. For each IFS register, there is a SET, CLR,
	** and INV register, so the distance (in dwords) from IFS0 to IFS1
	** is 4. This code assumes that all of the enable control and flag
	** bits for an SPI controller are in the same IEC and IFS registers.
	*/ // interrupt enable control register // interrupt flag register // error interrupt flag/enable bit // rx interrupt flag/enable bit // tx interrupt flag/enable bit