openfpga/src/utils/lut_utils.cpp
/********************************************************************
 * Adapt the truth table from the short-wire connection 
 * from the input nets of a LUT to an output of a LUT
 * 
 *                  LUT
 *                +-------------+
 *   lut_input--->|----+        |
 *                |    |        |
 *                |    +------->|---> lut_output
 *                |             |
 *                +-------------+
 *
 * In this case, LUT is configured as a wiring module
 * This function will generate a truth for the wiring LUT
 *
 * For example: 
 * The truth table of the case where the 3rd input of 
 * a 4-input LUT is wired to output 
 *    
 *    --1- 1
 * 
 ********************************************************************/
Adapt the truth table from the short-wire connection
from the input nets of a LUT to an output of a LUT



In this case, LUT is configured as a wiring module
This function will generate a truth for the wiring LUT

For example:
The truth table of the case where the 3rd input of
a 4-input LUT is wired to output

1- 1
Adapt the truth table from the short - wire connection from the input nets of a LUT to an output of a LUT In this case LUT is configured as a wiring module This function will generate a truth for the wiring LUT For example : The truth table of the case where the 3rd input of a 4 - input LUT is wired to output 1 - 1
AtomNetlist::TruthTable build_wired_lut_truth_table(const size_t& lut_size, 
                                                    const size_t& wire_input_id) {
  AtomNetlist::TruthTable tt;
  tt.resize(1);
  tt[0].resize(lut_size, vtr::LogicValue::DONT_CARE);
  VTR_ASSERT(wire_input_id < lut_size);
  tt[0][wire_input_id] = vtr::LogicValue::TRUE; 
  tt[0].push_back(vtr::LogicValue::TRUE);
  return tt;
}
AtomNetlist :: TruthTable build_wired_lut_truth_table ( const size_t & lut_size , const size_t & wire_input_id ) { AtomNetlist :: TruthTable tt ; tt . resize ( 1 ) ; tt [ 0 ] . resize ( lut_size , vtr :: LogicValue :: DONT_CARE ) ; VTR_ASSERT ( wire_input_id < lut_size ) ; tt [ 0 ] [ wire_input_id ] = vtr :: LogicValue :: TRUE ; tt [ 0 ] . push_back ( vtr :: LogicValue :: TRUE ) ; return tt ; }
Adapt the truth table from the short-wire connection
 from the input nets of a LUT to an output of a LUT
Adapt the truth table from the short - wire connection from the input nets of a LUT to an output of a LUT
/* There is always only one line in this truth table */ /* Pre-allocate the truth table: 
   * Each truth table line is organized in BLIF format:
   *     |<---LUT size--->|
   *   < a string of 0 or 1> <0 or 1>
   * The first <lut_size> of characters represent the input values of each LUT input
   * Here, we add 2 characters, which denote the space and a digit (0|1)
   * By default, we set all the inputs as don't care value '-'
   *
   * For more details, please refer to the BLIF format documentation
   */ /* Fill the truth table !!! */