libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
/************************************************************************
 * Check points to make sure we have a valid circuit library
 * Detailed checkpoints: 
 * 1. Circuit models have unique names 
 * 2. Circuit models have unique prefix
 * 3. Check IOPADs have input and output ports
 * 4. Check MUXes has been defined and has input and output ports
 * 5. We must have at least one SRAM or CCFF 
 * 6. SRAM must have at least an input and an output ports
 * 7. CCFF must have at least a clock, an input and an output ports
 * 8. FF must have at least a clock, an input and an output ports
 * 9. LUT must have at least an input, an output and a SRAM ports
 * 10. We must have default circuit models for these types: MUX, channel wires and wires
 *
 * Note:
 *   - NO modification on the circuit library is allowed!
 *     The circuit library should be read-only!!!
 ***********************************************************************/
Check points to make sure we have a valid circuit library
Detailed checkpoints:
1. Circuit models have unique names
2. Circuit models have unique prefix
3. Check IOPADs have input and output ports
4. Check MUXes has been defined and has input and output ports
5. We must have at least one SRAM or CCFF
6. SRAM must have at least an input and an output ports
7. CCFF must have at least a clock, an input and an output ports
8. FF must have at least a clock, an input and an output ports
9. LUT must have at least an input, an output and a SRAM ports
10. We must have default circuit models for these types: MUX, channel wires and wires

- NO modification on the circuit library is allowed.
The circuit library should be read-only
Check points to make sure we have a valid circuit library Detailed checkpoints : 1 . Circuit models have unique names 2 . Circuit models have unique prefix 3 . Check IOPADs have input and output ports 4 . Check MUXes has been defined and has input and output ports 5 . We must have at least one SRAM or CCFF 6 . SRAM must have at least an input and an output ports 7 . CCFF must have at least a clock an input and an output ports 8 . FF must have at least a clock an input and an output ports 9 . LUT must have at least an input an output and a SRAM ports 10 . We must have default circuit models for these types : MUX channel wires and wires - NO modification on the circuit library is allowed . The circuit library should be read - only
bool check_circuit_library(const CircuitLibrary& circuit_lib) {
  size_t num_err = 0;
  vtr::ScopedStartFinishTimer timer("Check circuit library");
  num_err += check_circuit_library_unique_names(circuit_lib);
  num_err += check_circuit_library_unique_prefix(circuit_lib);
  num_err += check_circuit_library_ports(circuit_lib);
  num_err += check_circuit_model_required(circuit_lib, CIRCUIT_MODEL_IOPAD);
  num_err += check_io_circuit_model(circuit_lib);
  num_err += check_circuit_model_required(circuit_lib, CIRCUIT_MODEL_MUX);
  std::vector<enum e_circuit_model_port_type> mux_port_types_required;
  mux_port_types_required.push_back(CIRCUIT_MODEL_PORT_INPUT);
  mux_port_types_required.push_back(CIRCUIT_MODEL_PORT_OUTPUT);
  mux_port_types_required.push_back(CIRCUIT_MODEL_PORT_SRAM);
  num_err += check_circuit_model_port_required(circuit_lib, CIRCUIT_MODEL_MUX, mux_port_types_required);
  if ( ( 0 == circuit_lib.models_by_type(CIRCUIT_MODEL_SRAM).size())
    && ( 0 == circuit_lib.models_by_type(CIRCUIT_MODEL_CCFF).size()) ) {
    VTR_LOG_ERROR("At least one %s or %s circuit model is required!\n",
                  CIRCUIT_MODEL_TYPE_STRING[size_t(CIRCUIT_MODEL_SRAM)], 
                  CIRCUIT_MODEL_TYPE_STRING[size_t(CIRCUIT_MODEL_CCFF)]);
    num_err++;
  }
  std::vector<enum e_circuit_model_port_type> sram_port_types_required;
  sram_port_types_required.push_back(CIRCUIT_MODEL_PORT_OUTPUT);
  num_err += check_circuit_model_port_required(circuit_lib, CIRCUIT_MODEL_SRAM, sram_port_types_required);
  std::vector<enum e_circuit_model_port_type> ccff_port_types_required;
  ccff_port_types_required.push_back(CIRCUIT_MODEL_PORT_CLOCK);
  ccff_port_types_required.push_back(CIRCUIT_MODEL_PORT_INPUT);
  ccff_port_types_required.push_back(CIRCUIT_MODEL_PORT_OUTPUT);
  num_err += check_circuit_model_port_required(circuit_lib, CIRCUIT_MODEL_CCFF, ccff_port_types_required);
  std::vector<enum e_circuit_model_port_type> ff_port_types_required;
  ff_port_types_required.push_back(CIRCUIT_MODEL_PORT_CLOCK);
  ff_port_types_required.push_back(CIRCUIT_MODEL_PORT_INPUT);
  ff_port_types_required.push_back(CIRCUIT_MODEL_PORT_OUTPUT);
  num_err += check_circuit_model_port_required(circuit_lib, CIRCUIT_MODEL_FF, ff_port_types_required);
  std::vector<enum e_circuit_model_port_type> lut_port_types_required;
  lut_port_types_required.push_back(CIRCUIT_MODEL_PORT_SRAM);
  lut_port_types_required.push_back(CIRCUIT_MODEL_PORT_INPUT);
  lut_port_types_required.push_back(CIRCUIT_MODEL_PORT_OUTPUT);
  num_err += check_circuit_model_port_required(circuit_lib, CIRCUIT_MODEL_LUT, lut_port_types_required);
  num_err += check_default_circuit_model_by_types(circuit_lib);
  num_err += check_required_default_circuit_model(circuit_lib, CIRCUIT_MODEL_MUX);
  num_err += check_required_default_circuit_model(circuit_lib, CIRCUIT_MODEL_CHAN_WIRE);
  num_err += check_required_default_circuit_model(circuit_lib, CIRCUIT_MODEL_WIRE);
  num_err += check_power_gated_circuit_models(circuit_lib);
  if (0 < num_err) {
    VTR_LOG("Finished checking circuit library with %d errors!\n",
            num_err);
    return false;
  }
  VTR_LOG("Checking circuit library passed.\n");
  return true;
}
bool check_circuit_library ( const CircuitLibrary & circuit_lib ) { size_t num_err = 0 ; vtr :: ScopedStartFinishTimer timer ( " " ) ; num_err += check_circuit_library_unique_names ( circuit_lib ) ; num_err += check_circuit_library_unique_prefix ( circuit_lib ) ; num_err += check_circuit_library_ports ( circuit_lib ) ; num_err += check_circuit_model_required ( circuit_lib , CIRCUIT_MODEL_IOPAD ) ; num_err += check_io_circuit_model ( circuit_lib ) ; num_err += check_circuit_model_required ( circuit_lib , CIRCUIT_MODEL_MUX ) ; std :: vector < enum e_circuit_model_port_type > mux_port_types_required ; mux_port_types_required . push_back ( CIRCUIT_MODEL_PORT_INPUT ) ; mux_port_types_required . push_back ( CIRCUIT_MODEL_PORT_OUTPUT ) ; mux_port_types_required . push_back ( CIRCUIT_MODEL_PORT_SRAM ) ; num_err += check_circuit_model_port_required ( circuit_lib , CIRCUIT_MODEL_MUX , mux_port_types_required ) ; if ( ( 0 == circuit_lib . models_by_type ( CIRCUIT_MODEL_SRAM ) . size ( ) ) && ( 0 == circuit_lib . models_by_type ( CIRCUIT_MODEL_CCFF ) . size ( ) ) ) { VTR_LOG_ERROR ( " \n " , CIRCUIT_MODEL_TYPE_STRING [ size_t ( CIRCUIT_MODEL_SRAM ) ] , CIRCUIT_MODEL_TYPE_STRING [ size_t ( CIRCUIT_MODEL_CCFF ) ] ) ; num_err ++ ; } std :: vector < enum e_circuit_model_port_type > sram_port_types_required ; sram_port_types_required . push_back ( CIRCUIT_MODEL_PORT_OUTPUT ) ; num_err += check_circuit_model_port_required ( circuit_lib , CIRCUIT_MODEL_SRAM , sram_port_types_required ) ; std :: vector < enum e_circuit_model_port_type > ccff_port_types_required ; ccff_port_types_required . push_back ( CIRCUIT_MODEL_PORT_CLOCK ) ; ccff_port_types_required . push_back ( CIRCUIT_MODEL_PORT_INPUT ) ; ccff_port_types_required . push_back ( CIRCUIT_MODEL_PORT_OUTPUT ) ; num_err += check_circuit_model_port_required ( circuit_lib , CIRCUIT_MODEL_CCFF , ccff_port_types_required ) ; std :: vector < enum e_circuit_model_port_type > ff_port_types_required ; ff_port_types_required . push_back ( CIRCUIT_MODEL_PORT_CLOCK ) ; ff_port_types_required . push_back ( CIRCUIT_MODEL_PORT_INPUT ) ; ff_port_types_required . push_back ( CIRCUIT_MODEL_PORT_OUTPUT ) ; num_err += check_circuit_model_port_required ( circuit_lib , CIRCUIT_MODEL_FF , ff_port_types_required ) ; std :: vector < enum e_circuit_model_port_type > lut_port_types_required ; lut_port_types_required . push_back ( CIRCUIT_MODEL_PORT_SRAM ) ; lut_port_types_required . push_back ( CIRCUIT_MODEL_PORT_INPUT ) ; lut_port_types_required . push_back ( CIRCUIT_MODEL_PORT_OUTPUT ) ; num_err += check_circuit_model_port_required ( circuit_lib , CIRCUIT_MODEL_LUT , lut_port_types_required ) ; num_err += check_default_circuit_model_by_types ( circuit_lib ) ; num_err += check_required_default_circuit_model ( circuit_lib , CIRCUIT_MODEL_MUX ) ; num_err += check_required_default_circuit_model ( circuit_lib , CIRCUIT_MODEL_CHAN_WIRE ) ; num_err += check_required_default_circuit_model ( circuit_lib , CIRCUIT_MODEL_WIRE ) ; num_err += check_power_gated_circuit_models ( circuit_lib ) ; if ( 0 < num_err ) { VTR_LOG ( " \n " , num_err ) ; return false ; } VTR_LOG ( " \n " ) ; return true ; }
Check points to make sure we have a valid circuit library
 Detailed checkpoints:
 1.
Check points to make sure we have a valid circuit library Detailed checkpoints : 1 .
/* 1. Circuit models have unique names  
   * For each circuit model, we always make sure it does not share any name with any circuit model locating after it
   */ /* 2. Circuit models have unique prefix
   * For each circuit model, we always make sure it does not share any prefix with any circuit model locating after it
   */ /* Check global ports */ /* 3. Check io has been defined and has input and output ports 
   * [a] We must have global I/O port, either its type is inout, input or output
   * [b] For each IOPAD, we must have at least an input an output 
   */ /* 4. Check mux has been defined and has input and output ports
   * [a] We must have a MUX! 
   * [b] For each MUX, we must have at least an input, an output, and an SRAM port
   */ /* 5. We must have at least one SRAM or CCFF */ /* Incremental the counter for errors */ /* 6. SRAM must have at least an input and an output ports*/ /* 7. CCFF must have at least a clock, an input and an output ports*/ /* 8. FF must have at least a clock, an input and an output ports*/ /* 9. LUT must have at least an input, an output and a SRAM ports*/ /* 10. For each type of circuit models that are define, we must have 1 default model
   *     We must have default circuit models for these types: MUX, channel wires and wires 
   */ /* 11. Check power-gated inverter/buffer models */ /* If we have any errors, exit */