src/dev/arm/ufs_device.cc
/**
 * UFSHCD write function. This function allows access to the writeable
 * registers. If any function attempts to write value to an unwriteable
 * register entry, then the value will not be written.
 */
UFSHCD write function. This function allows access to the writeable
registers. If any function attempts to write value to an unwriteable
register entry, then the value will not be written.
UFSHCD write function . This function allows access to the writeable registers . If any function attempts to write value to an unwriteable register entry then the value will not be written .
Tick
UFSHostDevice::write(PacketPtr pkt)
{
    assert(pkt->getSize() <= 4);
    const uint32_t data = pkt->getUintX(ByteOrder::little);
    switch (pkt->getAddr() & 0xFF)
    {
      case regControllerCapabilities:
        break;
      case regUFSVersion:
        break;
      case regControllerDEVID:
        break;
      case regControllerPRODID:
        break;
      case regInterruptStatus:
        break;
      case regInterruptEnable:
        UFSHCIMem.ORInterruptEnable = data;
        break;
      case regControllerStatus:
        UFSHCIMem.ORHostControllerStatus = data;
        break;
      case regControllerEnable:
        UFSHCIMem.ORHostControllerEnable = data;
        break;
      case regUICErrorCodePHYAdapterLayer:
        UFSHCIMem.ORUECPA = data;
        break;
      case regUICErrorCodeDataLinkLayer:
        UFSHCIMem.ORUECDL = data;
        break;
      case regUICErrorCodeNetworkLayer:
        UFSHCIMem.ORUECN = data;
        break;
      case regUICErrorCodeTransportLayer:
        UFSHCIMem.ORUECT = data;
        break;
      case regUICErrorCodeDME:
        UFSHCIMem.ORUECDME = data;
        break;
      case regUTPTransferREQINTAGGControl:
        UFSHCIMem.ORUTRIACR = data;
        break;
      case regUTPTransferREQListBaseL:
        UFSHCIMem.TRUTRLBA = data;
        if (((UFSHCIMem.TRUTRLBA | UFSHCIMem.TRUTRLBAU) != 0x00) &&
            ((UFSHCIMem.TMUTMRLBA | UFSHCIMem.TMUTMRLBAU)!= 0x00))
            UFSHCIMem.ORHostControllerStatus |= UICCommandReady;
        break;
      case regUTPTransferREQListBaseH:
        UFSHCIMem.TRUTRLBAU = data;
        if (((UFSHCIMem.TRUTRLBA | UFSHCIMem.TRUTRLBAU) != 0x00) &&
            ((UFSHCIMem.TMUTMRLBA | UFSHCIMem.TMUTMRLBAU) != 0x00))
            UFSHCIMem.ORHostControllerStatus |= UICCommandReady;
        break;
      case regUTPTransferREQDoorbell:
        if (!(UFSHCIMem.TRUTRLDBR) && data)
            stats.idleTimes.sample(curTick() - idlePhaseStart);
        UFSHCIMem.TRUTRLDBR |= data;
        requestHandler();
        break;
      case regUTPTransferREQListClear:
        UFSHCIMem.TRUTRLCLR = data;
        break;
      case regUTPTransferREQListRunStop:
        UFSHCIMem.TRUTRLRSR = data;
        break;
      case regUTPTaskREQListBaseL:
        UFSHCIMem.TMUTMRLBA = data;
        if (((UFSHCIMem.TRUTRLBA | UFSHCIMem.TRUTRLBAU) != 0x00) &&
            ((UFSHCIMem.TMUTMRLBA | UFSHCIMem.TMUTMRLBAU) != 0x00))
            UFSHCIMem.ORHostControllerStatus |= UICCommandReady;
        break;
      case regUTPTaskREQListBaseH:
        UFSHCIMem.TMUTMRLBAU = data;
        if (((UFSHCIMem.TRUTRLBA | UFSHCIMem.TRUTRLBAU) != 0x00) &&
            ((UFSHCIMem.TMUTMRLBA | UFSHCIMem.TMUTMRLBAU) != 0x00))
            UFSHCIMem.ORHostControllerStatus |= UICCommandReady;
        break;
      case regUTPTaskREQDoorbell:
        UFSHCIMem.TMUTMRLDBR |= data;
        requestHandler();
        break;
      case regUTPTaskREQListClear:
        UFSHCIMem.TMUTMRLCLR = data;
        break;
      case regUTPTaskREQListRunStop:
        UFSHCIMem.TMUTMRLRSR = data;
        break;
      case regUICCommand:
        UFSHCIMem.CMDUICCMDR = data;
        requestHandler();
        break;
      case regUICCommandArg1:
        UFSHCIMem.CMDUCMDARG1 = data;
        break;
      case regUICCommandArg2:
        UFSHCIMem.CMDUCMDARG2 = data;
        break;
      case regUICCommandArg3:
        UFSHCIMem.CMDUCMDARG3 = data;
        break;
      default:break;
    }
    pkt->makeResponse();
    return pioDelay;
}
Tick UFSHostDevice :: write ( PacketPtr pkt ) { assert ( pkt -> getSize ( ) <= 4 ) ; const uint32_t data = pkt -> getUintX ( ByteOrder :: little ) ; switch ( pkt -> getAddr ( ) & 0xFF ) { case regControllerCapabilities : break ; case regUFSVersion : break ; case regControllerDEVID : break ; case regControllerPRODID : break ; case regInterruptStatus : break ; case regInterruptEnable : UFSHCIMem . ORInterruptEnable = data ; break ; case regControllerStatus : UFSHCIMem . ORHostControllerStatus = data ; break ; case regControllerEnable : UFSHCIMem . ORHostControllerEnable = data ; break ; case regUICErrorCodePHYAdapterLayer : UFSHCIMem . ORUECPA = data ; break ; case regUICErrorCodeDataLinkLayer : UFSHCIMem . ORUECDL = data ; break ; case regUICErrorCodeNetworkLayer : UFSHCIMem . ORUECN = data ; break ; case regUICErrorCodeTransportLayer : UFSHCIMem . ORUECT = data ; break ; case regUICErrorCodeDME : UFSHCIMem . ORUECDME = data ; break ; case regUTPTransferREQINTAGGControl : UFSHCIMem . ORUTRIACR = data ; break ; case regUTPTransferREQListBaseL : UFSHCIMem . TRUTRLBA = data ; if ( ( ( UFSHCIMem . TRUTRLBA | UFSHCIMem . TRUTRLBAU ) != 0x00 ) && ( ( UFSHCIMem . TMUTMRLBA | UFSHCIMem . TMUTMRLBAU ) != 0x00 ) ) UFSHCIMem . ORHostControllerStatus |= UICCommandReady ; break ; case regUTPTransferREQListBaseH : UFSHCIMem . TRUTRLBAU = data ; if ( ( ( UFSHCIMem . TRUTRLBA | UFSHCIMem . TRUTRLBAU ) != 0x00 ) && ( ( UFSHCIMem . TMUTMRLBA | UFSHCIMem . TMUTMRLBAU ) != 0x00 ) ) UFSHCIMem . ORHostControllerStatus |= UICCommandReady ; break ; case regUTPTransferREQDoorbell : if ( ! ( UFSHCIMem . TRUTRLDBR ) && data ) stats . idleTimes . sample ( curTick ( ) - idlePhaseStart ) ; UFSHCIMem . TRUTRLDBR |= data ; requestHandler ( ) ; break ; case regUTPTransferREQListClear : UFSHCIMem . TRUTRLCLR = data ; break ; case regUTPTransferREQListRunStop : UFSHCIMem . TRUTRLRSR = data ; break ; case regUTPTaskREQListBaseL : UFSHCIMem . TMUTMRLBA = data ; if ( ( ( UFSHCIMem . TRUTRLBA | UFSHCIMem . TRUTRLBAU ) != 0x00 ) && ( ( UFSHCIMem . TMUTMRLBA | UFSHCIMem . TMUTMRLBAU ) != 0x00 ) ) UFSHCIMem . ORHostControllerStatus |= UICCommandReady ; break ; case regUTPTaskREQListBaseH : UFSHCIMem . TMUTMRLBAU = data ; if ( ( ( UFSHCIMem . TRUTRLBA | UFSHCIMem . TRUTRLBAU ) != 0x00 ) && ( ( UFSHCIMem . TMUTMRLBA | UFSHCIMem . TMUTMRLBAU ) != 0x00 ) ) UFSHCIMem . ORHostControllerStatus |= UICCommandReady ; break ; case regUTPTaskREQDoorbell : UFSHCIMem . TMUTMRLDBR |= data ; requestHandler ( ) ; break ; case regUTPTaskREQListClear : UFSHCIMem . TMUTMRLCLR = data ; break ; case regUTPTaskREQListRunStop : UFSHCIMem . TMUTMRLRSR = data ; break ; case regUICCommand : UFSHCIMem . CMDUICCMDR = data ; requestHandler ( ) ; break ; case regUICCommandArg1 : UFSHCIMem . CMDUCMDARG1 = data ; break ; case regUICCommandArg2 : UFSHCIMem . CMDUCMDARG2 = data ; break ; case regUICCommandArg3 : UFSHCIMem . CMDUCMDARG3 = data ; break ; default : break ; } pkt -> makeResponse ( ) ; return pioDelay ; }
UFSHCD write function.
UFSHCD write function .
//you shall not write to this //you shall not write to this //you shall not write to this //you shall not write to this //you shall not write to this //nothing happens, you try to access a register that //does not exist