vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp
/* Deteremine the side of a io grid */
Deteremine the side of a io grid
Deteremine the side of a io grid
e_side determine_io_grid_pin_side(const vtr::Point<size_t>& device_size, 
                                  const vtr::Point<size_t>& grid_coordinate) {
  if (device_size.y() == grid_coordinate.y()) {
    return BOTTOM; 
  } else if (device_size.x() == grid_coordinate.x()) { 
    return LEFT; 
  } else if (0 == grid_coordinate.y()) { 
    return TOP; 
  } else if (0 == grid_coordinate.x()) { 
    return RIGHT; 
  } else if ((grid_coordinate.x() < device_size.x()) && (grid_coordinate.y() < device_size.y())) {
    return NUM_SIDES;
  }
  VTR_LOGF_ERROR(__FILE__, __LINE__,
                 "Invalid coordinate (%lu, %lu) for I/O Grid whose size is (%lu, %lu)!\n",
                grid_coordinate.x(), grid_coordinate.y(),
                device_size.x(), device_size.y());
  exit(1);
}
e_side determine_io_grid_pin_side ( const vtr :: Point < size_t > & device_size , const vtr :: Point < size_t > & grid_coordinate ) { if ( device_size . y ( ) == grid_coordinate . y ( ) ) { return BOTTOM ; } else if ( device_size . x ( ) == grid_coordinate . x ( ) ) { return LEFT ; } else if ( 0 == grid_coordinate . y ( ) ) { return TOP ; } else if ( 0 == grid_coordinate . x ( ) ) { return RIGHT ; } else if ( ( grid_coordinate . x ( ) < device_size . x ( ) ) && ( grid_coordinate . y ( ) < device_size . y ( ) ) ) { return NUM_SIDES ; } VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " , grid_coordinate . x ( ) , grid_coordinate . y ( ) , device_size . x ( ) , device_size . y ( ) ) ; exit ( 1 ) ; }
Deteremine the side of a io grid
Deteremine the side of a io grid
/* TOP side IO of FPGA */ /* Such I/O has only Bottom side pins */ /* RIGHT side IO of FPGA */ /* Such I/O has only Left side pins */ /* BOTTOM side IO of FPGA */ /* Such I/O has only Top side pins */ /* LEFT side IO of FPGA */ /* Such I/O has only Right side pins */ /* I/O grid in the center grid */