openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
/********************************************************************
 * A top-level function re-organizes the bitstream for a specific 
 * FPGA fabric, where configuration bits are organized in the sequence
 * that can be directly loaded to the FPGA configuration protocol.
 * Support:
 * 1. Configuration chain
 * 2. Memory decoders
 * This function does NOT modify the bitstream database
 * Instead, it builds a vector of ids for configuration bits in bitstream manager
 *
 * This function can be called ONLY after the function build_device_bitstream() 
 * Note that this function does NOT decode bitstreams from circuit implementation
 * It was done in the function build_device_bitstream() 
 *******************************************************************/
A top-level function re-organizes the bitstream for a specific
FPGA fabric, where configuration bits are organized in the sequence
that can be directly loaded to the FPGA configuration protocol.
Support:
1. Configuration chain
2. Memory decoders
This function does NOT modify the bitstream database
Instead, it builds a vector of ids for configuration bits in bitstream manager

This function can be called ONLY after the function build_device_bitstream()
Note that this function does NOT decode bitstreams from circuit implementation
It was done in the function build_device_bitstream()
A top - level function re - organizes the bitstream for a specific FPGA fabric where configuration bits are organized in the sequence that can be directly loaded to the FPGA configuration protocol . Support : 1 . Configuration chain 2 . Memory decoders This function does NOT modify the bitstream database Instead it builds a vector of ids for configuration bits in bitstream manager This function can be called ONLY after the function build_device_bitstream () Note that this function does NOT decode bitstreams from circuit implementation It was done in the function build_device_bitstream ()
FabricBitstream build_fabric_dependent_bitstream(const BitstreamManager& bitstream_manager,
                                                 const ModuleManager& module_manager,
                                                 const ConfigProtocol& config_protocol,
                                                 const bool& verbose) {
  FabricBitstream fabric_bitstream; 
  vtr::ScopedStartFinishTimer timer("\nBuild fabric dependent bitstream\n");
  std::string top_module_name = generate_fpga_top_module_name();
  ModuleId top_module = module_manager.find_module(top_module_name);
  VTR_ASSERT(true == module_manager.valid_module_id(top_module));
  std::vector<ConfigBlockId> top_block = find_bitstream_manager_top_blocks(bitstream_manager);
  VTR_ASSERT(1 == top_block.size());
  VTR_ASSERT(0 == top_module_name.compare(bitstream_manager.block_name(top_block[0])));
  build_module_fabric_dependent_bitstream(config_protocol,
                                          bitstream_manager, top_block[0],
                                          module_manager, top_module, 
                                          fabric_bitstream);
  VTR_LOGV(verbose,
           "Built %lu configuration bits for fabric\n",
           fabric_bitstream.num_bits());
  return fabric_bitstream;
}
FabricBitstream build_fabric_dependent_bitstream ( const BitstreamManager & bitstream_manager , const ModuleManager & module_manager , const ConfigProtocol & config_protocol , const bool & verbose ) { FabricBitstream fabric_bitstream ; vtr :: ScopedStartFinishTimer timer ( " \n \n " ) ; std :: string top_module_name = generate_fpga_top_module_name ( ) ; ModuleId top_module = module_manager . find_module ( top_module_name ) ; VTR_ASSERT ( true == module_manager . valid_module_id ( top_module ) ) ; std :: vector < ConfigBlockId > top_block = find_bitstream_manager_top_blocks ( bitstream_manager ) ; VTR_ASSERT ( 1 == top_block . size ( ) ) ; VTR_ASSERT ( 0 == top_module_name . compare ( bitstream_manager . block_name ( top_block [ 0 ] ) ) ) ; build_module_fabric_dependent_bitstream ( config_protocol , bitstream_manager , top_block [ 0 ] , module_manager , top_module , fabric_bitstream ) ; VTR_LOGV ( verbose , " \n " , fabric_bitstream . num_bits ( ) ) ; return fabric_bitstream ; }
A top-level function re-organizes the bitstream for a specific
 FPGA fabric, where configuration bits are organized in the sequence
 that can be directly loaded to the FPGA configuration protocol.
A top - level function re - organizes the bitstream for a specific FPGA fabric where configuration bits are organized in the sequence that can be directly loaded to the FPGA configuration protocol .
/* Get the top module name in module manager, which is our starting point */ /* Find the top block in bitstream manager, which has not parents */ /* Make sure we have only 1 top block and its name matches the top module */ /* Start build-up formally */