openfpga/src/fabric/build_module_graph_utils.cpp
/********************************************************************
 * Add inverter/buffer module to a parent module
 * and complete the wiring to the input port of inverter/buffer
 * This function will return the wire created for the output port of inverter/buffer
 *
 *  parent_module
 *  +-----------------------------------------------------------------
 *  |       
 *  |                 input_net                    output_net
 *  |                    |                           |
 *  |                    v      +---------------+    v
 *  | src_module_port --------->|  child_module |--------> 
 *  |                           +---------------+
 *
 ********************************************************************/
Add inverter/buffer module to a parent module
and complete the wiring to the input port of inverter/buffer
This function will return the wire created for the output port of inverter/buffer


Add inverter / buffer module to a parent module and complete the wiring to the input port of inverter / buffer This function will return the wire created for the output port of inverter / buffer
ModuleNetId add_inverter_buffer_child_module_and_nets(ModuleManager& module_manager,
                                                      const ModuleId& parent_module, 
                                                      const CircuitLibrary& circuit_lib, 
                                                      const CircuitModelId& model_id, 
                                                      const ModuleNetId& input_net) {
  VTR_ASSERT(true == module_manager.valid_module_id(parent_module));
  std::string module_name = circuit_lib.model_name(model_id);
  ModuleId child_module = module_manager.find_module(module_name);
  VTR_ASSERT(true == module_manager.valid_module_id(child_module));
  ModulePortId module_input_port_id = find_inverter_buffer_module_port(module_manager, child_module, circuit_lib, model_id, CIRCUIT_MODEL_PORT_INPUT);
  ModulePortId module_output_port_id = find_inverter_buffer_module_port(module_manager, child_module, circuit_lib, model_id, CIRCUIT_MODEL_PORT_OUTPUT);
  VTR_ASSERT(1 == module_manager.module_port(child_module, module_input_port_id).get_width());
  VTR_ASSERT(1 == module_manager.module_port(child_module, module_output_port_id).get_width());
  size_t child_instance = module_manager.num_instance(parent_module, child_module);
  module_manager.add_child_module(parent_module, child_module);
  module_manager.add_module_net_sink(parent_module, input_net, child_module, child_instance, module_input_port_id, 0);
  ModuleNetId output_net = module_manager.create_module_net(parent_module);
  module_manager.add_module_net_source(parent_module, output_net, child_module, child_instance, module_output_port_id, 0);
  return output_net;
}
ModuleNetId add_inverter_buffer_child_module_and_nets ( ModuleManager & module_manager , const ModuleId & parent_module , const CircuitLibrary & circuit_lib , const CircuitModelId & model_id , const ModuleNetId & input_net ) { VTR_ASSERT ( true == module_manager . valid_module_id ( parent_module ) ) ; std :: string module_name = circuit_lib . model_name ( model_id ) ; ModuleId child_module = module_manager . find_module ( module_name ) ; VTR_ASSERT ( true == module_manager . valid_module_id ( child_module ) ) ; ModulePortId module_input_port_id = find_inverter_buffer_module_port ( module_manager , child_module , circuit_lib , model_id , CIRCUIT_MODEL_PORT_INPUT ) ; ModulePortId module_output_port_id = find_inverter_buffer_module_port ( module_manager , child_module , circuit_lib , model_id , CIRCUIT_MODEL_PORT_OUTPUT ) ; VTR_ASSERT ( 1 == module_manager . module_port ( child_module , module_input_port_id ) . get_width ( ) ) ; VTR_ASSERT ( 1 == module_manager . module_port ( child_module , module_output_port_id ) . get_width ( ) ) ; size_t child_instance = module_manager . num_instance ( parent_module , child_module ) ; module_manager . add_child_module ( parent_module , child_module ) ; module_manager . add_module_net_sink ( parent_module , input_net , child_module , child_instance , module_input_port_id , 0 ) ; ModuleNetId output_net = module_manager . create_module_net ( parent_module ) ; module_manager . add_module_net_source ( parent_module , output_net , child_module , child_instance , module_output_port_id , 0 ) ; return output_net ; }
Add inverter/buffer module to a parent module
 and complete the wiring to the input port of inverter/buffer
 This function will return the wire created for the output port of inverter/buffer
Add inverter / buffer module to a parent module and complete the wiring to the input port of inverter / buffer This function will return the wire created for the output port of inverter / buffer
/* We must have a valid module id */ /* Port size should be 1 ! */ /* Instanciate a child module */ /* Use the net to connect to the input net of buffer */ /* Create a net to bridge the input inverter and LUT MUX */