openfpga/src/utils/check_tile_annotation.cpp
/********************************************************************
 * Check if the tile annotation is valid without any conflict with
 * physical tile definition.
 * Items to check:
 * - The global port defined in tile annotation is a valid port/pin in 
 *   the physical tile definition.
 * - If the port properties match:
 *   - the port in physical tile should have Fc = 0 
 *   - a clock port should be also a clock port in physical tile
 *   - a non-clock port should be defined as a non-clock global port in physical tile
 *******************************************************************/
Check if the tile annotation is valid without any conflict with
physical tile definition.
Items to check:
- The global port defined in tile annotation is a valid port/pin in
the physical tile definition.
Check if the tile annotation is valid without any conflict with physical tile definition . Items to check : - The global port defined in tile annotation is a valid port / pin in the physical tile definition .
static 
int check_tile_annotation_conflicts_with_physical_tile(const TileAnnotation& tile_annotation,
                                                       const std::vector<t_physical_tile_type>& physical_tile_types) {
  int num_err = 0;
  for (const TileGlobalPortId& tile_global_port : tile_annotation.global_ports()) {
    for (size_t tile_info_id = 0; tile_info_id < tile_annotation.global_port_tile_names(tile_global_port).size(); ++tile_info_id) {
      size_t found_matched_physical_tile = 0; 
      size_t found_matched_physical_tile_port = 0; 
      std::string required_tile_name = tile_annotation.global_port_tile_names(tile_global_port)[tile_info_id];
      BasicPort required_tile_port = tile_annotation.global_port_tile_ports(tile_global_port)[tile_info_id];
      for (const t_physical_tile_type& physical_tile : physical_tile_types) { 
        if (std::string(physical_tile.name) != required_tile_name) {
          continue;
        }
        found_matched_physical_tile++;
        for (const t_physical_tile_port& tile_port : physical_tile.ports) { 
          if (std::string(tile_port.name) != required_tile_port.get_name()) {
            continue;
          }
          BasicPort ref_tile_port(tile_port.name, tile_port.num_pins);
          if (false == ref_tile_port.contained(required_tile_port)) {
            VTR_LOG_ERROR("Tile annotation port '%s[%lu:%lu]' is out of the range of physical tile port '%s[%lu:%lu]'!",
                          required_tile_port.get_name().c_str(),
                          required_tile_port.get_lsb(),
                          required_tile_port.get_msb(),
                          ref_tile_port.get_name().c_str(),
                          ref_tile_port.get_lsb(),
                          ref_tile_port.get_msb());
            num_err++;
            continue;
          }
          int grid_pin_index = tile_port.absolute_first_pin_index;
          if (tile_port.is_clock != tile_annotation.global_port_is_clock(tile_global_port)) {
            VTR_LOGF_ERROR(__FILE__, __LINE__,
                           "Tile port '%s.%s[%ld:%ld]' in tile annotation '%s' does not match physical tile port %s.%s in clock property (one is defined as clock while the other is not)!\n",
                           required_tile_name.c_str(),
                           required_tile_port.get_name().c_str(),
                           required_tile_port.get_lsb(),
                           required_tile_port.get_msb(),
                           tile_annotation.global_port_name(tile_global_port).c_str(),
                           physical_tile.name, tile_port.name);
            num_err++;
          }
          if ((false == tile_port.is_clock)
            && (false == tile_port.is_non_clock_global)) {
            VTR_LOGF_ERROR(__FILE__, __LINE__,
                           "Tile port '%s.%s[%ld:%ld]' in tile annotation '%s' match physical tile port %s.%s  but is not defined as a non-clock global port!\n",
                           required_tile_name.c_str(),
                           required_tile_port.get_name().c_str(),
                           required_tile_port.get_lsb(),
                           required_tile_port.get_msb(),
                           tile_annotation.global_port_name(tile_global_port).c_str(),
                           physical_tile.name, tile_port.name);
            num_err++;
          }
          float pin_Fc = find_physical_tile_pin_Fc(&physical_tile, grid_pin_index);
          if (0. != pin_Fc) { 
            VTR_LOGF_ERROR(__FILE__, __LINE__,
                           "Tile port '%s.%s[%ld:%ld]' in tile annotation '%s' match physical tile port %s.%s  but its Fc is not zero '%g' !\n",
                           required_tile_name.c_str(),
                           required_tile_port.get_name().c_str(),
                           required_tile_port.get_lsb(),
                           required_tile_port.get_msb(),
                           tile_annotation.global_port_name(tile_global_port).c_str(),
                           physical_tile.name, tile_port.name, pin_Fc);
          }
          found_matched_physical_tile_port++; 
        }
      }
      if (0 == found_matched_physical_tile) {
        VTR_LOGF_ERROR(__FILE__, __LINE__,
                       "Tile name '%s' in tile annotation '%s' does not match any physical tile!\n",
                       required_tile_name.c_str(),
                       tile_annotation.global_port_name(tile_global_port).c_str());
        num_err++;
      }
      if (0 == found_matched_physical_tile_port) {
        VTR_LOGF_ERROR(__FILE__, __LINE__,
                       "Tile port '%s.%s[%ld:%ld]' in tile annotation '%s' does not match any physical tile port!\n",
                       required_tile_name.c_str(),
                       required_tile_port.get_name().c_str(),
                       required_tile_port.get_lsb(),
                       required_tile_port.get_msb(),
                       tile_annotation.global_port_name(tile_global_port).c_str());
        num_err++;
      }
      if (1 < found_matched_physical_tile) {
        VTR_LOGF_ERROR(__FILE__, __LINE__,
                       "Tile name '%s' in tile annotation '%s' match more than 1 physical tile!\n",
                       required_tile_name.c_str(),
                       tile_annotation.global_port_name(tile_global_port).c_str());
        num_err++;
      }
      if (1 < found_matched_physical_tile_port) {
        VTR_LOGF_ERROR(__FILE__, __LINE__,
                       "Tile port '%s.%s[%ld:%ld]' in tile annotation '%s' match more than 1 physical tile port!\n",
                       required_tile_name.c_str(),
                       required_tile_port.get_name().c_str(),
                       required_tile_port.get_lsb(),
                       required_tile_port.get_msb(),
                       tile_annotation.global_port_name(tile_global_port).c_str());
        num_err++;
      }
    }
  }
  return num_err;
}
static int check_tile_annotation_conflicts_with_physical_tile ( const TileAnnotation & tile_annotation , const std :: vector < t_physical_tile_type > & physical_tile_types ) { int num_err = 0 ; for ( const TileGlobalPortId & tile_global_port : tile_annotation . global_ports ( ) ) { for ( size_t tile_info_id = 0 ; tile_info_id < tile_annotation . global_port_tile_names ( tile_global_port ) . size ( ) ; ++ tile_info_id ) { size_t found_matched_physical_tile = 0 ; size_t found_matched_physical_tile_port = 0 ; std :: string required_tile_name = tile_annotation . global_port_tile_names ( tile_global_port ) [ tile_info_id ] ; BasicPort required_tile_port = tile_annotation . global_port_tile_ports ( tile_global_port ) [ tile_info_id ] ; for ( const t_physical_tile_type & physical_tile : physical_tile_types ) { if ( std :: string ( physical_tile . name ) != required_tile_name ) { continue ; } found_matched_physical_tile ++ ; for ( const t_physical_tile_port & tile_port : physical_tile . ports ) { if ( std :: string ( tile_port . name ) != required_tile_port . get_name ( ) ) { continue ; } BasicPort ref_tile_port ( tile_port . name , tile_port . num_pins ) ; if ( false == ref_tile_port . contained ( required_tile_port ) ) { VTR_LOG_ERROR ( " " , required_tile_port . get_name ( ) . c_str ( ) , required_tile_port . get_lsb ( ) , required_tile_port . get_msb ( ) , ref_tile_port . get_name ( ) . c_str ( ) , ref_tile_port . get_lsb ( ) , ref_tile_port . get_msb ( ) ) ; num_err ++ ; continue ; } int grid_pin_index = tile_port . absolute_first_pin_index ; if ( tile_port . is_clock != tile_annotation . global_port_is_clock ( tile_global_port ) ) { VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " , required_tile_name . c_str ( ) , required_tile_port . get_name ( ) . c_str ( ) , required_tile_port . get_lsb ( ) , required_tile_port . get_msb ( ) , tile_annotation . global_port_name ( tile_global_port ) . c_str ( ) , physical_tile . name , tile_port . name ) ; num_err ++ ; } if ( ( false == tile_port . is_clock ) && ( false == tile_port . is_non_clock_global ) ) { VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " , required_tile_name . c_str ( ) , required_tile_port . get_name ( ) . c_str ( ) , required_tile_port . get_lsb ( ) , required_tile_port . get_msb ( ) , tile_annotation . global_port_name ( tile_global_port ) . c_str ( ) , physical_tile . name , tile_port . name ) ; num_err ++ ; } float pin_Fc = find_physical_tile_pin_Fc ( & physical_tile , grid_pin_index ) ; if ( 0. != pin_Fc ) { VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " , required_tile_name . c_str ( ) , required_tile_port . get_name ( ) . c_str ( ) , required_tile_port . get_lsb ( ) , required_tile_port . get_msb ( ) , tile_annotation . global_port_name ( tile_global_port ) . c_str ( ) , physical_tile . name , tile_port . name , pin_Fc ) ; } found_matched_physical_tile_port ++ ; } } if ( 0 == found_matched_physical_tile ) { VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " , required_tile_name . c_str ( ) , tile_annotation . global_port_name ( tile_global_port ) . c_str ( ) ) ; num_err ++ ; } if ( 0 == found_matched_physical_tile_port ) { VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " , required_tile_name . c_str ( ) , required_tile_port . get_name ( ) . c_str ( ) , required_tile_port . get_lsb ( ) , required_tile_port . get_msb ( ) , tile_annotation . global_port_name ( tile_global_port ) . c_str ( ) ) ; num_err ++ ; } if ( 1 < found_matched_physical_tile ) { VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " , required_tile_name . c_str ( ) , tile_annotation . global_port_name ( tile_global_port ) . c_str ( ) ) ; num_err ++ ; } if ( 1 < found_matched_physical_tile_port ) { VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " , required_tile_name . c_str ( ) , required_tile_port . get_name ( ) . c_str ( ) , required_tile_port . get_lsb ( ) , required_tile_port . get_msb ( ) , tile_annotation . global_port_name ( tile_global_port ) . c_str ( ) ) ; num_err ++ ; } } } return num_err ; }
Check if the tile annotation is valid without any conflict with
 physical tile definition.
Check if the tile annotation is valid without any conflict with physical tile definition .
/* Must find a valid physical tile in the same name */ /* Found a match, increment the counter */ /* Must found a valid port where both port name and port size must match!!! */ /* Port size must be in range!!! */ /* Check if port property matches */ /* If we found no match, error out */ /* If we found more than 1 match, error out */