openfpga/src/fpga_spice/spice_transistor_wrapper.cpp
/********************************************************************
 * Generate the SPICE netlist for transistors
 *******************************************************************/
Generate the SPICE netlist for transistors
Generate the SPICE netlist for transistors
int print_spice_transistor_wrapper(NetlistManager& netlist_manager,
                                   const TechnologyLibrary& tech_lib,
                                   const std::string& submodule_dir) {
  std::string spice_fname = submodule_dir + std::string(TRANSISTORS_SPICE_FILE_NAME);
  std::fstream fp;
  fp.open(spice_fname, std::fstream::out | std::fstream::trunc);
  check_file_stream(spice_fname.c_str(), fp); 
  VTR_LOG("Generating SPICE netlist '%s' for transistors...",
          spice_fname.c_str()); 
  print_spice_file_header(fp, std::string("Transistor wrappers"));
  for (const TechnologyModelId& model : tech_lib.models()) {
    if (TECH_LIB_MODEL_TRANSISTOR != tech_lib.model_type(model)) {
      continue;
    }
    if (CMD_EXEC_SUCCESS != print_spice_transistor_model_wrapper(fp, tech_lib, model)) {
      return CMD_EXEC_FATAL_ERROR;
    }
  } 
  fp.close();
  NetlistId nlist_id = netlist_manager.add_netlist(spice_fname);
  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
  netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST);
  VTR_LOG("Done\n");
  return CMD_EXEC_SUCCESS;
}
int print_spice_transistor_wrapper ( NetlistManager & netlist_manager , const TechnologyLibrary & tech_lib , const std :: string & submodule_dir ) { std :: string spice_fname = submodule_dir + std :: string ( TRANSISTORS_SPICE_FILE_NAME ) ; std :: fstream fp ; fp . open ( spice_fname , std :: fstream :: out | std :: fstream :: trunc ) ; check_file_stream ( spice_fname . c_str ( ) , fp ) ; VTR_LOG ( " " , spice_fname . c_str ( ) ) ; print_spice_file_header ( fp , std :: string ( " " ) ) ; for ( const TechnologyModelId & model : tech_lib . models ( ) ) { if ( TECH_LIB_MODEL_TRANSISTOR != tech_lib . model_type ( model ) ) { continue ; } if ( CMD_EXEC_SUCCESS != print_spice_transistor_model_wrapper ( fp , tech_lib , model ) ) { return CMD_EXEC_FATAL_ERROR ; } } fp . close ( ) ; NetlistId nlist_id = netlist_manager . add_netlist ( spice_fname ) ; VTR_ASSERT ( NetlistId :: INVALID ( ) != nlist_id ) ; netlist_manager . set_netlist_type ( nlist_id , NetlistManager :: SUBMODULE_NETLIST ) ; VTR_LOG ( " \n " ) ; return CMD_EXEC_SUCCESS ; }
Generate the SPICE netlist for transistors
Generate the SPICE netlist for transistors
/* Create the file stream */ /* Check if the file stream if valid or not */ /* Create file */ /* Iterate over the transistor models */ /* Focus on transistor model */ /* Write a wrapper for the transistor model */ /* Close file handler*/ /* Add fname to the netlist name list */