openfpga/src/fabric/build_mux_modules.cpp
/*********************************************************************
 * Generate  Verilog codes modeling an branch circuit 
 * for a CMOS multiplexer with the given size 
 * Support structural and behavioral Verilog codes
 *********************************************************************/
Generate  Verilog codes modeling an branch circuit
for a CMOS multiplexer with the given size
Support structural and behavioral Verilog codes
Generate Verilog codes modeling an branch circuit for a CMOS multiplexer with the given size Support structural and behavioral Verilog codes
static 
void build_cmos_mux_branch_module(ModuleManager& module_manager,
                                  const CircuitLibrary& circuit_lib, 
                                  const CircuitModelId& mux_model, 
                                  const std::string& module_name, 
                                  const MuxGraph& mux_graph) {
  CircuitModelId tgate_model = circuit_lib.pass_gate_logic_model(mux_model);
  if (CIRCUIT_MODEL_GATE == circuit_lib.model_type(tgate_model)) {
    VTR_ASSERT(CIRCUIT_MODEL_GATE_MUX2 == circuit_lib.gate_type(tgate_model));
    return;
  }
  std::vector<CircuitPortId> tgate_global_ports = circuit_lib.model_global_ports_by_type(tgate_model, CIRCUIT_MODEL_PORT_INPUT, true, true);
  size_t num_inputs = mux_graph.num_inputs();
  size_t num_outputs = mux_graph.num_outputs();
  size_t num_mems = mux_graph.num_memory_bits();
  VTR_ASSERT(1 == num_outputs);
  VTR_ASSERT(1 == mux_graph.num_levels());
  ModuleId mux_module = module_manager.add_module(module_name); 
  VTR_ASSERT(true == module_manager.valid_module_id(mux_module));
  BasicPort input_port("in", num_inputs);
  ModulePortId module_input_port = module_manager.add_port(mux_module, input_port, ModuleManager::MODULE_INPUT_PORT);
  BasicPort output_port("out", num_outputs);
  ModulePortId module_output_port = module_manager.add_port(mux_module, output_port, ModuleManager::MODULE_OUTPUT_PORT);
  BasicPort mem_port("mem", num_mems);
  ModulePortId module_mem_port = module_manager.add_port(mux_module, mem_port, ModuleManager::MODULE_INPUT_PORT);
  BasicPort mem_inv_port("mem_inv", num_mems);
  ModulePortId module_mem_inv_port = module_manager.add_port(mux_module, mem_inv_port, ModuleManager::MODULE_INPUT_PORT);
  build_cmos_mux_branch_body(module_manager, circuit_lib, tgate_model, mux_module, module_input_port, module_output_port, module_mem_port, module_mem_inv_port, mux_graph);
  add_module_global_ports_from_child_modules(module_manager, mux_module);
}
static void build_cmos_mux_branch_module ( ModuleManager & module_manager , const CircuitLibrary & circuit_lib , const CircuitModelId & mux_model , const std :: string & module_name , const MuxGraph & mux_graph ) { CircuitModelId tgate_model = circuit_lib . pass_gate_logic_model ( mux_model ) ; if ( CIRCUIT_MODEL_GATE == circuit_lib . model_type ( tgate_model ) ) { VTR_ASSERT ( CIRCUIT_MODEL_GATE_MUX2 == circuit_lib . gate_type ( tgate_model ) ) ; return ; } std :: vector < CircuitPortId > tgate_global_ports = circuit_lib . model_global_ports_by_type ( tgate_model , CIRCUIT_MODEL_PORT_INPUT , true , true ) ; size_t num_inputs = mux_graph . num_inputs ( ) ; size_t num_outputs = mux_graph . num_outputs ( ) ; size_t num_mems = mux_graph . num_memory_bits ( ) ; VTR_ASSERT ( 1 == num_outputs ) ; VTR_ASSERT ( 1 == mux_graph . num_levels ( ) ) ; ModuleId mux_module = module_manager . add_module ( module_name ) ; VTR_ASSERT ( true == module_manager . valid_module_id ( mux_module ) ) ; BasicPort input_port ( " " , num_inputs ) ; ModulePortId module_input_port = module_manager . add_port ( mux_module , input_port , ModuleManager :: MODULE_INPUT_PORT ) ; BasicPort output_port ( " " , num_outputs ) ; ModulePortId module_output_port = module_manager . add_port ( mux_module , output_port , ModuleManager :: MODULE_OUTPUT_PORT ) ; BasicPort mem_port ( " " , num_mems ) ; ModulePortId module_mem_port = module_manager . add_port ( mux_module , mem_port , ModuleManager :: MODULE_INPUT_PORT ) ; BasicPort mem_inv_port ( " " , num_mems ) ; ModulePortId module_mem_inv_port = module_manager . add_port ( mux_module , mem_inv_port , ModuleManager :: MODULE_INPUT_PORT ) ; build_cmos_mux_branch_body ( module_manager , circuit_lib , tgate_model , mux_module , module_input_port , module_output_port , module_mem_port , module_mem_inv_port , mux_graph ) ; add_module_global_ports_from_child_modules ( module_manager , mux_module ) ; }
Generate  Verilog codes modeling an branch circuit
 for a CMOS multiplexer with the given size
 Support structural and behavioral Verilog codes
Generate Verilog codes modeling an branch circuit for a CMOS multiplexer with the given size Support structural and behavioral Verilog codes
/* Get the tgate model */ /* Skip output if the tgate model is a MUX2, it is handled by essential-gate generator */ /* Generate the Verilog netlist according to the mux_graph */ /* Find out the number of inputs */ /* Find out the number of outputs */ /* Find out the number of memory bits */ /* Check codes to ensure the port of Verilog netlists will match */ /* MUX graph must have only 1 output */ /* MUX graph must have only 1 level*/ /* Create a Verilog Module based on the circuit model, and add to module manager */ /* Add module ports */ /* Add each input port */ /* Add each output port */ /* Add each memory port */ /* By default we give a structural description, 
   * Writers can freely write the module in their styles 
   * For instance, Verilog writer can ignore the internal structure and write in behavioral codes 
   */ /* Add global ports to the mux module:
   * This is a much easier job after adding sub modules (instances), 
   * we just need to find all the global ports from the child modules and build a list of it
   */