openfpga/src/fpga_sdc/configuration_chain_sdc_writer.cpp
/********************************************************************
 * Print SDC commands to constrain the timing between outputs and inputs
 * of all the configurable memory modules
 *   
 *           |<------Max/Min delay-->|
 *           |                       | 
 *    +------+ out               in  +------+
 *    | CCFF |---------------------->| CCFF |
 *    +------+                       +------+
 *
 * This function will be executed in a recursive way, 
 * using a Depth-First Search (DFS) strategy
 * It will iterate over all the configurable children under each module
 * and print a SDC command
 *
 *******************************************************************/
Print SDC commands to constrain the timing between outputs and inputs
of all the configurable memory modules



This function will be executed in a recursive way,
using a Depth-First Search (DFS) strategy
It will iterate over all the configurable children under each module
and print a SDC command
Print SDC commands to constrain the timing between outputs and inputs of all the configurable memory modules This function will be executed in a recursive way using a Depth - First Search ( DFS ) strategy It will iterate over all the configurable children under each module and print a SDC command
static 
void rec_print_pnr_sdc_constrain_configurable_chain(std::fstream& fp, 
                                                    const float& tmax,
                                                    const float& tmin,
                                                    const ModuleManager& module_manager, 
                                                    const ModuleId& parent_module,
                                                    const std::string& parent_module_path,
                                                    std::string& previous_module_path,
                                                    ModuleId& previous_module) {
  for (size_t child_index = 0; child_index < module_manager.configurable_children(parent_module).size(); ++child_index) {
    std::string child_module_path = parent_module_path;
    ModuleId child_module_id = module_manager.configurable_children(parent_module)[child_index];
    size_t child_instance_id = module_manager.configurable_child_instances(parent_module)[child_index];
    std::string child_instance_name;
    if (true == module_manager.instance_name(parent_module, child_module_id, child_instance_id).empty()) {
      child_instance_name = generate_instance_name(module_manager.module_name(child_module_id), child_instance_id);
    } else {
      child_instance_name = module_manager.instance_name(parent_module, child_module_id, child_instance_id);
    }
    child_module_path += child_instance_name;
    child_module_path = format_dir_path(child_module_path);
    rec_print_pnr_sdc_constrain_configurable_chain(fp,
                                                   tmax, tmin,
                                                   module_manager, 
                                                   child_module_id, 
                                                   child_module_path,
                                                   previous_module_path,
                                                   previous_module);
  }
  if (0 < module_manager.configurable_children(parent_module).size()) {
    return;
  }
  valid_file_stream(fp);
  if (!previous_module_path.empty()) {
    bool first_port = true;
    for (const BasicPort& output_port : module_manager.module_ports_by_type(previous_module, ModuleManager::MODULE_OUTPUT_PORT)) {
      if (false == first_port) {
        continue;
      }
      for (const BasicPort& input_port : module_manager.module_ports_by_type(parent_module, ModuleManager::MODULE_INPUT_PORT)) {
        print_pnr_sdc_constrain_max_delay(fp, 
                                          previous_module_path, 
                                          output_port.get_name(),
                                          parent_module_path, 
                                          input_port.get_name(),
                                          tmax);
        print_pnr_sdc_constrain_min_delay(fp, 
                                          previous_module_path, 
                                          output_port.get_name(),
                                          parent_module_path, 
                                          input_port.get_name(),
                                          tmin);
      }
      first_port = false;
    }
  }
  previous_module_path = parent_module_path;
  previous_module = parent_module;
}
static void rec_print_pnr_sdc_constrain_configurable_chain ( std :: fstream & fp , const float & tmax , const float & tmin , const ModuleManager & module_manager , const ModuleId & parent_module , const std :: string & parent_module_path , std :: string & previous_module_path , ModuleId & previous_module ) { for ( size_t child_index = 0 ; child_index < module_manager . configurable_children ( parent_module ) . size ( ) ; ++ child_index ) { std :: string child_module_path = parent_module_path ; ModuleId child_module_id = module_manager . configurable_children ( parent_module ) [ child_index ] ; size_t child_instance_id = module_manager . configurable_child_instances ( parent_module ) [ child_index ] ; std :: string child_instance_name ; if ( true == module_manager . instance_name ( parent_module , child_module_id , child_instance_id ) . empty ( ) ) { child_instance_name = generate_instance_name ( module_manager . module_name ( child_module_id ) , child_instance_id ) ; } else { child_instance_name = module_manager . instance_name ( parent_module , child_module_id , child_instance_id ) ; } child_module_path += child_instance_name ; child_module_path = format_dir_path ( child_module_path ) ; rec_print_pnr_sdc_constrain_configurable_chain ( fp , tmax , tmin , module_manager , child_module_id , child_module_path , previous_module_path , previous_module ) ; } if ( 0 < module_manager . configurable_children ( parent_module ) . size ( ) ) { return ; } valid_file_stream ( fp ) ; if ( ! previous_module_path . empty ( ) ) { bool first_port = true ; for ( const BasicPort & output_port : module_manager . module_ports_by_type ( previous_module , ModuleManager :: MODULE_OUTPUT_PORT ) ) { if ( false == first_port ) { continue ; } for ( const BasicPort & input_port : module_manager . module_ports_by_type ( parent_module , ModuleManager :: MODULE_INPUT_PORT ) ) { print_pnr_sdc_constrain_max_delay ( fp , previous_module_path , output_port . get_name ( ) , parent_module_path , input_port . get_name ( ) , tmax ) ; print_pnr_sdc_constrain_min_delay ( fp , previous_module_path , output_port . get_name ( ) , parent_module_path , input_port . get_name ( ) , tmin ) ; } first_port = false ; } } previous_module_path = parent_module_path ; previous_module = parent_module ; }
Print SDC commands to constrain the timing between outputs and inputs
 of all the configurable memory modules
Print SDC commands to constrain the timing between outputs and inputs of all the configurable memory modules
/* For each configurable child, we will go one level down in priority */ /* If there is no configurable children any more, this is a leaf module, print a SDC command for disable timing */ /* Validate file stream */ /* Disable timing for each output port of this module */ /* Only the first output port will be considered,
       * being consistent with build_memory_module.cpp:395
       */ /* Update previous module */