openfpga/src/fpga_spice/spice_subckt_writer.cpp
/********************************************************************
 * Name a net for a local wire for a SPICE subckt
 * 1. If this is a local wire, name it after the <src_module_name>_<instance_id>_<src_port_name>
 * 2. If this is not a local wire, name it after the port name of parent module 
 *
 * In addition, it will assign the pin index as well  
 *
 * Restriction: this function requires each net has single driver
 * which is definitely always true in circuits.
 *******************************************************************/
Name a net for a local wire for a SPICE subckt
1. If this is a local wire, name it after the __
2. If this is not a local wire, name it after the port name of parent module

In addition, it will assign the pin index as well

this function requires each net has single driver
which is definitely always true in circuits.
Name a net for a local wire for a SPICE subckt 1 . If this is a local wire name it after the __ 2 . If this is not a local wire name it after the port name of parent module In addition it will assign the pin index as well this function requires each net has single driver which is definitely always true in circuits .
static 
BasicPort generate_spice_port_for_module_net(const ModuleManager& module_manager,
                                             const ModuleId& module_id,
                                             const ModuleNetId& module_net) {
  for (ModuleNetSrcId src_id : module_manager.module_net_sources(module_id, module_net)) {
    if (module_id == module_manager.net_source_modules(module_id, module_net)[src_id]) {
      ModulePortId net_src_port = module_manager.net_source_ports(module_id, module_net)[src_id];
      size_t src_pin_index = module_manager.net_source_pins(module_id, module_net)[src_id];
      return BasicPort(module_manager.module_port(module_id, net_src_port).get_name(), src_pin_index, src_pin_index);
    }
  }
  for (ModuleNetSinkId sink_id : module_manager.module_net_sinks(module_id, module_net)) {
    if (module_id == module_manager.net_sink_modules(module_id, module_net)[sink_id]) {
      ModulePortId net_sink_port = module_manager.net_sink_ports(module_id, module_net)[sink_id];
      size_t sink_pin_index = module_manager.net_sink_pins(module_id, module_net)[sink_id];
      return BasicPort(module_manager.module_port(module_id, net_sink_port).get_name(), sink_pin_index, sink_pin_index);
    }
  }
  std::string net_name;
  VTR_ASSERT(1 == module_manager.net_source_modules(module_id, module_net).size());
  ModuleId net_src_module = module_manager.net_source_modules(module_id, module_net)[ModuleNetSrcId(0)];
  size_t net_src_instance = module_manager.net_source_instances(module_id, module_net)[ModuleNetSrcId(0)]; 
  ModulePortId net_src_port = module_manager.net_source_ports(module_id, module_net)[ModuleNetSrcId(0)]; 
  size_t net_src_pin = module_manager.net_source_pins(module_id, module_net)[ModuleNetSrcId(0)]; 
  if (false == module_manager.net_name(module_id, module_net).empty()) {
    net_name = module_manager.net_name(module_id, module_net);
  } else {
    net_name  = module_manager.module_name(net_src_module); 
    net_name += std::string("_") + std::to_string(net_src_instance) + std::string("_");
    net_name += module_manager.module_port(net_src_module, net_src_port).get_name();
  }
  return BasicPort(net_name, net_src_pin, net_src_pin);
}
static BasicPort generate_spice_port_for_module_net ( const ModuleManager & module_manager , const ModuleId & module_id , const ModuleNetId & module_net ) { for ( ModuleNetSrcId src_id : module_manager . module_net_sources ( module_id , module_net ) ) { if ( module_id == module_manager . net_source_modules ( module_id , module_net ) [ src_id ] ) { ModulePortId net_src_port = module_manager . net_source_ports ( module_id , module_net ) [ src_id ] ; size_t src_pin_index = module_manager . net_source_pins ( module_id , module_net ) [ src_id ] ; return BasicPort ( module_manager . module_port ( module_id , net_src_port ) . get_name ( ) , src_pin_index , src_pin_index ) ; } } for ( ModuleNetSinkId sink_id : module_manager . module_net_sinks ( module_id , module_net ) ) { if ( module_id == module_manager . net_sink_modules ( module_id , module_net ) [ sink_id ] ) { ModulePortId net_sink_port = module_manager . net_sink_ports ( module_id , module_net ) [ sink_id ] ; size_t sink_pin_index = module_manager . net_sink_pins ( module_id , module_net ) [ sink_id ] ; return BasicPort ( module_manager . module_port ( module_id , net_sink_port ) . get_name ( ) , sink_pin_index , sink_pin_index ) ; } } std :: string net_name ; VTR_ASSERT ( 1 == module_manager . net_source_modules ( module_id , module_net ) . size ( ) ) ; ModuleId net_src_module = module_manager . net_source_modules ( module_id , module_net ) [ ModuleNetSrcId ( 0 ) ] ; size_t net_src_instance = module_manager . net_source_instances ( module_id , module_net ) [ ModuleNetSrcId ( 0 ) ] ; ModulePortId net_src_port = module_manager . net_source_ports ( module_id , module_net ) [ ModuleNetSrcId ( 0 ) ] ; size_t net_src_pin = module_manager . net_source_pins ( module_id , module_net ) [ ModuleNetSrcId ( 0 ) ] ; if ( false == module_manager . net_name ( module_id , module_net ) . empty ( ) ) { net_name = module_manager . net_name ( module_id , module_net ) ; } else { net_name = module_manager . module_name ( net_src_module ) ; net_name += std :: string ( " " ) + std :: to_string ( net_src_instance ) + std :: string ( " " ) ; net_name += module_manager . module_port ( net_src_module , net_src_port ) . get_name ( ) ; } return BasicPort ( net_name , net_src_pin , net_src_pin ) ; }
Name a net for a local wire for a SPICE subckt
 1.
Name a net for a local wire for a SPICE subckt 1 .
/* Check all the sink modules of the net, 
   * if we have a source module is the current module, this is not local wire 
   */ /* Here, this is not a local wire, return the port name of the src_port */ /* Check all the sink modules of the net */ /* Here, this is not a local wire, return the port name of the sink_port */ /* Reach here, this is a local wire */ /* Each net must only one 1 source */ /* Get the source module */ /* Get the instance id */ /* Get the port id */ /* Get the pin id */ /* Load user-defined name if we have it */