libopenfpga/libarchopenfpga/src/openfpga_arch_linker.cpp
/********************************************************************
 * Link the circuit model of SRAM ports of each circuit model
 * to a default SRAM circuit model.
 * This function aims to ease the XML writing, allowing users to skip
 * the circuit model definition for SRAM ports that are used by default
 * TODO: Maybe deprecated as we prefer strict definition 
 *******************************************************************/
Link the circuit model of SRAM ports of each circuit model
to a default SRAM circuit model.
This function aims to ease the XML writing, allowing users to skip
the circuit model definition for SRAM ports that are used by default
TODO: Maybe deprecated as we prefer strict definition
Link the circuit model of SRAM ports of each circuit model to a default SRAM circuit model . This function aims to ease the XML writing allowing users to skip the circuit model definition for SRAM ports that are used by default TODO : Maybe deprecated as we prefer strict definition
void config_circuit_models_sram_port_to_default_sram_model(CircuitLibrary& circuit_lib,
                                                           const CircuitModelId& default_sram_model) {
  VTR_ASSERT(CircuitModelId::INVALID() != default_sram_model);
  for (const auto& model : circuit_lib.models()) {
    for (const auto& port : circuit_lib.model_ports(model)) {
      if (CIRCUIT_MODEL_PORT_SRAM != circuit_lib.port_type(port)) {
        continue;
      }
      circuit_lib.set_port_tri_state_model_id(port, default_sram_model);
      if (true == circuit_lib.port_tri_state_model_name(port).empty()) { 
        VTR_LOG("Use the default configurable memory model '%s' for circuit model '%s' port '%s')\n",
                circuit_lib.model_name(default_sram_model).c_str(),
                circuit_lib.model_name(model).c_str(),
                circuit_lib.port_prefix(port).c_str());
        continue;
      }
      if (circuit_lib.model_name(default_sram_model) != circuit_lib.port_tri_state_model_name(port)) {
        VTR_LOG_WARN("Overwrite SRAM circuit model for circuit model port (name:%s, port:%s) to be the correct one (name:%s)!\n",
                     circuit_lib.model_name(model).c_str(),
                     circuit_lib.port_prefix(port).c_str(),
                     circuit_lib.model_name(default_sram_model).c_str());
      }
    }
  }
  circuit_lib.build_model_links();
}
void config_circuit_models_sram_port_to_default_sram_model ( CircuitLibrary & circuit_lib , const CircuitModelId & default_sram_model ) { VTR_ASSERT ( CircuitModelId :: INVALID ( ) != default_sram_model ) ; for ( const auto & model : circuit_lib . models ( ) ) { for ( const auto & port : circuit_lib . model_ports ( model ) ) { if ( CIRCUIT_MODEL_PORT_SRAM != circuit_lib . port_type ( port ) ) { continue ; } circuit_lib . set_port_tri_state_model_id ( port , default_sram_model ) ; if ( true == circuit_lib . port_tri_state_model_name ( port ) . empty ( ) ) { VTR_LOG ( " \n " , circuit_lib . model_name ( default_sram_model ) . c_str ( ) , circuit_lib . model_name ( model ) . c_str ( ) , circuit_lib . port_prefix ( port ) . c_str ( ) ) ; continue ; } if ( circuit_lib . model_name ( default_sram_model ) != circuit_lib . port_tri_state_model_name ( port ) ) { VTR_LOG_WARN ( " \n " , circuit_lib . model_name ( model ) . c_str ( ) , circuit_lib . port_prefix ( port ) . c_str ( ) , circuit_lib . model_name ( default_sram_model ) . c_str ( ) ) ; } } } circuit_lib . build_model_links ( ) ; }
Link the circuit model of SRAM ports of each circuit model
 to a default SRAM circuit model.
Link the circuit model of SRAM ports of each circuit model to a default SRAM circuit model .
/* Bypass non SRAM ports */ /* Write for the default SRAM SPICE model! */ /* Only show warning when we try to override the given spice_model_name ! */ /* Give a warning !!! */ /* Rebuild the submodels for circuit_library
   * because we have created links for ports 
   */