openfpga/src/fabric/build_essential_modules.cpp
/*********************************************************************
 * Register all the user-defined modules in the module manager
 * Walk through the circuit library and add user-defined circuit models
 * to the module_manager
 ********************************************************************/
Register all the user-defined modules in the module manager
Walk through the circuit library and add user-defined circuit models
to the module_manager
Register all the user - defined modules in the module manager Walk through the circuit library and add user - defined circuit models to the module_manager
void build_user_defined_modules(ModuleManager& module_manager, 
                                const CircuitLibrary& circuit_lib) {
  vtr::ScopedStartFinishTimer timer("Build user-defined modules");
  for (const auto& model : circuit_lib.models()) {
    if ( (true == circuit_lib.model_verilog_netlist(model).empty())
      && (true == circuit_lib.model_spice_netlist(model).empty()) ) {
      continue;
    }
    if (CIRCUIT_MODEL_CHAN_WIRE == circuit_lib.model_type(model)) {
      continue;
    }
    add_circuit_model_to_module_manager(module_manager, circuit_lib, model);
  }
}
void build_user_defined_modules ( ModuleManager & module_manager , const CircuitLibrary & circuit_lib ) { vtr :: ScopedStartFinishTimer timer ( " " ) ; for ( const auto & model : circuit_lib . models ( ) ) { if ( ( true == circuit_lib . model_verilog_netlist ( model ) . empty ( ) ) && ( true == circuit_lib . model_spice_netlist ( model ) . empty ( ) ) ) { continue ; } if ( CIRCUIT_MODEL_CHAN_WIRE == circuit_lib . model_type ( model ) ) { continue ; } add_circuit_model_to_module_manager ( module_manager , circuit_lib , model ) ; } }
Register all the user-defined modules in the module manager
 Walk through the circuit library and add user-defined circuit models
 to the module_manager
Register all the user - defined modules in the module manager Walk through the circuit library and add user - defined circuit models to the module_manager
/* Iterate over Verilog modules */ /* We only care about user-defined models */ /* Skip Routing channel wire models because they need a different name. Do it later */ /* Reach here, the model requires a user-defined Verilog netlist, 
     * Register it in the module_manager  
     */