openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
/********************************************************************
 * Print a file that includes all the fabric netlists 
 * that have been generated  and user-defined.
 * This does NOT include any testbenches!
 * Some netlists are open to compile under specific preprocessing flags
 *******************************************************************/
Print a file that includes all the fabric netlists
that have been generated  and user-defined.
This does NOT include any testbenches.
Some netlists are open to compile under specific preprocessing flags
Print a file that includes all the fabric netlists that have been generated and user - defined . This does NOT include any testbenches . Some netlists are open to compile under specific preprocessing flags
void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager,
                                          const std::string& src_dir,
                                          const CircuitLibrary& circuit_lib) {
  std::string verilog_fname = src_dir + std::string(FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME);
  std::fstream fp;
  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
  check_file_stream(verilog_fname.c_str(), fp);
  print_verilog_file_header(fp, std::string("Fabric Netlist Summary")); 
  print_verilog_comment(fp, std::string("------ Include defines: preproc flags -----"));
  print_verilog_include_netlist(fp, std::string(src_dir + std::string(DEFINES_VERILOG_FILE_NAME)));
  fp << std::endl;
  print_verilog_comment(fp, std::string("------ Include user-defined netlists -----"));
  for (const std::string& user_defined_netlist : find_circuit_library_unique_verilog_netlists(circuit_lib)) {
    print_verilog_include_netlist(fp, user_defined_netlist);
  }
  print_verilog_comment(fp, std::string("------ Include primitive module netlists -----"));
  for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::SUBMODULE_NETLIST)) {
    print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
  }
  fp << std::endl;
  print_verilog_comment(fp, std::string("------ Include logic block netlists -----"));
  for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::LOGIC_BLOCK_NETLIST)) {
    print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
  }
  fp << std::endl;
  print_verilog_comment(fp, std::string("------ Include routing module netlists -----"));
  for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::ROUTING_MODULE_NETLIST)) {
    print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
  }
  fp << std::endl;
  print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----"));
  for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::TOP_MODULE_NETLIST)) {
    print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
  }
  fp << std::endl;
  fp.close();
}
void print_verilog_fabric_include_netlist ( const NetlistManager & netlist_manager , const std :: string & src_dir , const CircuitLibrary & circuit_lib ) { std :: string verilog_fname = src_dir + std :: string ( FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME ) ; std :: fstream fp ; fp . open ( verilog_fname , std :: fstream :: out | std :: fstream :: trunc ) ; check_file_stream ( verilog_fname . c_str ( ) , fp ) ; print_verilog_file_header ( fp , std :: string ( " " ) ) ; print_verilog_comment ( fp , std :: string ( " " ) ) ; print_verilog_include_netlist ( fp , std :: string ( src_dir + std :: string ( DEFINES_VERILOG_FILE_NAME ) ) ) ; fp << std :: endl ; print_verilog_comment ( fp , std :: string ( " " ) ) ; for ( const std :: string & user_defined_netlist : find_circuit_library_unique_verilog_netlists ( circuit_lib ) ) { print_verilog_include_netlist ( fp , user_defined_netlist ) ; } print_verilog_comment ( fp , std :: string ( " " ) ) ; for ( const NetlistId & nlist_id : netlist_manager . netlists_by_type ( NetlistManager :: SUBMODULE_NETLIST ) ) { print_verilog_include_netlist ( fp , netlist_manager . netlist_name ( nlist_id ) ) ; } fp << std :: endl ; print_verilog_comment ( fp , std :: string ( " " ) ) ; for ( const NetlistId & nlist_id : netlist_manager . netlists_by_type ( NetlistManager :: LOGIC_BLOCK_NETLIST ) ) { print_verilog_include_netlist ( fp , netlist_manager . netlist_name ( nlist_id ) ) ; } fp << std :: endl ; print_verilog_comment ( fp , std :: string ( " " ) ) ; for ( const NetlistId & nlist_id : netlist_manager . netlists_by_type ( NetlistManager :: ROUTING_MODULE_NETLIST ) ) { print_verilog_include_netlist ( fp , netlist_manager . netlist_name ( nlist_id ) ) ; } fp << std :: endl ; print_verilog_comment ( fp , std :: string ( " " ) ) ; for ( const NetlistId & nlist_id : netlist_manager . netlists_by_type ( NetlistManager :: TOP_MODULE_NETLIST ) ) { print_verilog_include_netlist ( fp , netlist_manager . netlist_name ( nlist_id ) ) ; } fp << std :: endl ; fp . close ( ) ; }
Print a file that includes all the fabric netlists
 that have been generated  and user-defined.
Print a file that includes all the fabric netlists that have been generated and user - defined .
/* Create the file stream */ /* Validate the file stream */ /* Print the title */ /* Print preprocessing flags */ /* Include all the user-defined netlists */ /* Include all the primitive modules */ /* Include all the CLB, heterogeneous block modules */ /* Include all the routing architecture modules */ /* Include FPGA top module */ /* Close the file stream */