openfpga/src/utils/memory_utils.cpp
/********************************************************************
 * Generate a list of ports that are used for SRAM configuration to a module
 * The type and names of added ports strongly depend on the 
 * organization of SRAMs.
 * 1. Standalone SRAMs: 
 *    two ports will be added, which are regular output and inverted output 
 * 2. Scan-chain Flip-flops:
 *    two ports will be added, which are the head of scan-chain 
 *    and the tail of scan-chain
 *    IMPORTANT: the port size will be forced to 1 in this case 
 *               because the head and tail are both 1-bit ports!!!
 * 3. Memory decoders:
 *    2-4 ports will be added, depending on the ports available in the SRAM
 *    Among these, two ports are mandatory: BL and WL 
 *    The other two ports are optional: BLB and WLB
 *    Note that the constraints are correletated to the checking rules 
 *    in check_circuit_library()
 ********************************************************************/
Generate a list of ports that are used for SRAM configuration to a module
The type and names of added ports strongly depend on the
organization of SRAMs.
1. Standalone SRAMs:
two ports will be added, which are regular output and inverted output
2.
Generate a list of ports that are used for SRAM configuration to a module The type and names of added ports strongly depend on the organization of SRAMs . 1 . Standalone SRAMs : two ports will be added which are regular output and inverted output 2 .
std::vector<std::string> generate_sram_port_names(const CircuitLibrary& circuit_lib,
                                                  const CircuitModelId& sram_model,
                                                  const e_config_protocol_type sram_orgz_type) {
  std::vector<std::string> sram_port_names;
  std::vector<e_circuit_model_port_type> model_port_types; 
  switch (sram_orgz_type) {
  case CONFIG_MEM_SCAN_CHAIN: 
    model_port_types.push_back(CIRCUIT_MODEL_PORT_INPUT);
    model_port_types.push_back(CIRCUIT_MODEL_PORT_OUTPUT);
    break;
  case CONFIG_MEM_STANDALONE: 
  case CONFIG_MEM_MEMORY_BANK: {
    std::vector<e_circuit_model_port_type> ports_to_search;
    ports_to_search.push_back(CIRCUIT_MODEL_PORT_BL);
    ports_to_search.push_back(CIRCUIT_MODEL_PORT_WL);
    for (const auto& port_to_search : ports_to_search) {
      std::vector<CircuitPortId> found_port = circuit_lib.model_ports_by_type(sram_model, port_to_search);
      if (0 == found_port.size()) {
        continue;
      }
      model_port_types.push_back(port_to_search);
    }
    break;
  }
  case CONFIG_MEM_FRAME_BASED: {
    model_port_types.push_back(CIRCUIT_MODEL_PORT_INPUT);
    break;
  }
  default:
    VTR_LOGF_ERROR(__FILE__, __LINE__,
                   "Invalid type of SRAM organization !\n");
    exit(1);
  }
  for (size_t iport = 0; iport < model_port_types.size(); ++iport) {
    std::string port_name = generate_sram_port_name(sram_orgz_type, model_port_types[iport]);
    sram_port_names.push_back(port_name);
  }
  return sram_port_names;
}
std :: vector < std :: string > generate_sram_port_names ( const CircuitLibrary & circuit_lib , const CircuitModelId & sram_model , const e_config_protocol_type sram_orgz_type ) { std :: vector < std :: string > sram_port_names ; std :: vector < e_circuit_model_port_type > model_port_types ; switch ( sram_orgz_type ) { case CONFIG_MEM_SCAN_CHAIN : model_port_types . push_back ( CIRCUIT_MODEL_PORT_INPUT ) ; model_port_types . push_back ( CIRCUIT_MODEL_PORT_OUTPUT ) ; break ; case CONFIG_MEM_STANDALONE : case CONFIG_MEM_MEMORY_BANK : { std :: vector < e_circuit_model_port_type > ports_to_search ; ports_to_search . push_back ( CIRCUIT_MODEL_PORT_BL ) ; ports_to_search . push_back ( CIRCUIT_MODEL_PORT_WL ) ; for ( const auto & port_to_search : ports_to_search ) { std :: vector < CircuitPortId > found_port = circuit_lib . model_ports_by_type ( sram_model , port_to_search ) ; if ( 0 == found_port . size ( ) ) { continue ; } model_port_types . push_back ( port_to_search ) ; } break ; } case CONFIG_MEM_FRAME_BASED : { model_port_types . push_back ( CIRCUIT_MODEL_PORT_INPUT ) ; break ; } default : VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " ) ; exit ( 1 ) ; } for ( size_t iport = 0 ; iport < model_port_types . size ( ) ; ++ iport ) { std :: string port_name = generate_sram_port_name ( sram_orgz_type , model_port_types [ iport ] ) ; sram_port_names . push_back ( port_name ) ; } return sram_port_names ; }
Generate a list of ports that are used for SRAM configuration to a module
 The type and names of added ports strongly depend on the
 organization of SRAMs.
Generate a list of ports that are used for SRAM configuration to a module The type and names of added ports strongly depend on the organization of SRAMs .
/* Prepare a list of port types to be added, the port type will be used to create port names */ /* Try to find a BL/WL/BLB/WLB port and update the port types/module port types to be added */ /* Add ports to the module manager */ /* Create a port */