openfpga/src/utils/pb_type_utils.cpp
/************************************************************************ 
 * A pb_type is considered to be primitive when it has zero modes
 * However, this not always true. An exception is the LUT_CLASS
 * VPR added two modes by default to a LUT pb_type. Therefore,   
 * for LUT_CLASS, it is a primitive when it is binded to a blif model
 *
 * Note: 
 * - if VPR changes its mode organization for LUT pb_type
 *   this code should be adapted as well!
 ************************************************************************/
A pb_type is considered to be primitive when it has zero modes
However, this not always true. An exception is the LUT_CLASS
VPR added two modes by default to a LUT pb_type. Therefore,
for LUT_CLASS, it is a primitive when it is binded to a blif model

- if VPR changes its mode organization for LUT pb_type
this code should be adapted as well!
A pb_type is considered to be primitive when it has zero modes However this not always true . An exception is the LUT_CLASS VPR added two modes by default to a LUT pb_type . Therefore for LUT_CLASS it is a primitive when it is binded to a blif model - if VPR changes its mode organization for LUT pb_type this code should be adapted as well!
bool is_primitive_pb_type(t_pb_type* pb_type) {
  if (LUT_CLASS == pb_type->class_type) {
    if (0 == pb_type->num_modes) {
      return false;
    }
    VTR_ASSERT( (std::string("wire") == std::string(pb_type->modes[0].name))
             && (std::string(pb_type->name) == std::string(pb_type->modes[1].name)));
    return true;
  } else if (MEMORY_CLASS == pb_type->class_type) {
    if (0 == pb_type->num_modes) {
      return false;
    }
    VTR_ASSERT( (std::string("memory_slice") == std::string(pb_type->modes[0].name))
             || (std::string("memory_slice_1bit") == std::string(pb_type->modes[0].name)));
    return true;
  }
  return 0 == pb_type->num_modes;
}
bool is_primitive_pb_type ( t_pb_type * pb_type ) { if ( LUT_CLASS == pb_type -> class_type ) { if ( 0 == pb_type -> num_modes ) { return false ; } VTR_ASSERT ( ( std :: string ( " " ) == std :: string ( pb_type -> modes [ 0 ] . name ) ) && ( std :: string ( pb_type -> name ) == std :: string ( pb_type -> modes [ 1 ] . name ) ) ) ; return true ; } else if ( MEMORY_CLASS == pb_type -> class_type ) { if ( 0 == pb_type -> num_modes ) { return false ; } VTR_ASSERT ( ( std :: string ( " " ) == std :: string ( pb_type -> modes [ 0 ] . name ) ) || ( std :: string ( " " ) == std :: string ( pb_type -> modes [ 0 ] . name ) ) ) ; return true ; } return 0 == pb_type -> num_modes ; }
A pb_type is considered to be primitive when it has zero modes
 However, this not always true.
A pb_type is considered to be primitive when it has zero modes However this not always true .
/* The only primitive LUT we recognize is the one which have 
     * a first mode of LUT is wire, the second is the regular LUT
     * VPR contructed two modes under a regular LUT, and these children
     * are labelled as LUT_CLASS as well. OpenFPGA does not consider
     * them as primitive as they are for CAD usage only
     */ /* The only primitive memory we recognize is the one which has a mode
     * either named after 'memory_slice' or 'memory_slice_1bit'
     * VPR contructed 1 default mode under a regular memory, and these children
     * are labelled as LUT_CLASS as well. OpenFPGA does not consider
     * them as primitive as they are for CAD usage only
     */