libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
/************************************************************************
 * Check all the ports make sure, they satisfy the restriction 
 ***********************************************************************/
Check all the ports make sure, they satisfy the restriction
Check all the ports make sure they satisfy the restriction
static 
size_t check_circuit_library_ports(const CircuitLibrary& circuit_lib) {
  size_t num_err = 0;
  for (const auto& port : circuit_lib.ports()) {
    if ( (circuit_lib.port_is_global(port)) 
      && (!circuit_lib.is_input_port(port)) 
      && (!circuit_lib.is_output_port(port)) ) {
      VTR_LOG_ERROR("Circuit port (type=%s) of model (name=%s) is defined as global but not an input/output port!\n",
                    CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(circuit_lib.port_type(port))],
                    circuit_lib.model_name(port).c_str());
      num_err++;
    }
  }
  for (const auto& port : circuit_lib.ports()) {
    if ( (circuit_lib.port_is_global(port)) 
      && (CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib.port_type(port))
      && (false == circuit_lib.port_is_io(port)) ) {
      VTR_LOG_ERROR("Circuit port (type=%s) of model (name=%s) is defined as global output port but not an I/O!\n",
                    CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(circuit_lib.port_type(port))],
                    circuit_lib.model_name(port).c_str());
      num_err++;
    }
  }
  for (const auto& port : circuit_lib.ports()) {
    if ( ( (circuit_lib.port_is_set(port)) 
        || (circuit_lib.port_is_reset(port)) 
        || (circuit_lib.port_is_config_enable(port)) )
      && (!circuit_lib.port_is_global(port)) ) {
      VTR_LOG_ERROR("Circuit port (type=%s) of model (name=%s) is defined as a set/reset/config_enable port but it is not global!\n",
                    CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(circuit_lib.port_type(port))],
                    circuit_lib.model_name(port).c_str());
      num_err++;
    }
  }
  for (const auto& port : circuit_lib.ports()) {
    if (circuit_lib.port_tri_state_map(port).empty()) {
      continue; 
    }
    if (circuit_lib.port_tri_state_map(port).length() == circuit_lib.port_size(port)) {
      continue; 
    }
    VTR_LOG_ERROR("Tri-state map (=%s) of circuit port (type=%s) of model (name=%s) does not match the port size (=%lu)!\n",
               circuit_lib.port_tri_state_map(port).c_str(),
               CIRCUIT_MODEL_PORT_TYPE_STRING[size_t(circuit_lib.port_type(port))],
               circuit_lib.model_name(port).c_str(),
               circuit_lib.port_size(port));
    num_err++;
  }
  std::vector<CircuitPortId> global_ports;
  for (auto port : circuit_lib.ports()) {
    if (false == circuit_lib.port_is_global(port)) {
      continue;
    }
    global_ports.push_back(port);
  }
  for (size_t iport = 0; iport < global_ports.size() - 1; ++iport) {
    for (size_t jport = iport + 1; jport < global_ports.size(); ++jport) {
      if (0 != circuit_lib.port_prefix(global_ports[iport]).compare(circuit_lib.port_prefix(global_ports[jport]))) {
        continue;
      }
      CircuitModelId iport_parent_model = circuit_lib.port_parent_model(global_ports[iport]);
      CircuitModelId jport_parent_model = circuit_lib.port_parent_model(global_ports[jport]);
      if (circuit_lib.port_default_value(global_ports[iport]) != circuit_lib.port_default_value(global_ports[jport])) { 
        VTR_LOG_ERROR("Global ports %s from circuit model %s and %s share the same name but have different dfefault values(%lu and %lu)!\n",
                      circuit_lib.port_prefix(global_ports[iport]).c_str(),
                      circuit_lib.model_name(iport_parent_model).c_str(),
                      circuit_lib.model_name(jport_parent_model).c_str(),
                      circuit_lib.port_default_value(global_ports[iport]),
                      circuit_lib.port_default_value(global_ports[jport])
                      ); 
        num_err++;
      }
      if (circuit_lib.port_is_reset(global_ports[iport]) != circuit_lib.port_is_reset(global_ports[jport])) { 
        VTR_LOG_ERROR("Global ports %s from circuit model %s and %s share the same name but have different is_reset attributes!\n",
                      circuit_lib.port_prefix(global_ports[iport]).c_str(),
                      circuit_lib.model_name(iport_parent_model).c_str(),
                      circuit_lib.model_name(jport_parent_model).c_str() 
                      ); 
        num_err++;
      }
      if (circuit_lib.port_is_set(global_ports[iport]) != circuit_lib.port_is_set(global_ports[jport])) { 
        VTR_LOG_ERROR("Global ports %s from circuit model %s and %s share the same name but have different is_set attributes!\n",
                      circuit_lib.port_prefix(global_ports[iport]).c_str(),
                      circuit_lib.model_name(iport_parent_model).c_str(),
                      circuit_lib.model_name(jport_parent_model).c_str() 
                      ); 
        num_err++;
      }
      if (circuit_lib.port_is_config_enable(global_ports[iport]) != circuit_lib.port_is_config_enable(global_ports[jport])) { 
        VTR_LOG_ERROR("Global ports %s from circuit model %s and %s share the same name but have different is_config_enable attributes!\n",
                      circuit_lib.port_prefix(global_ports[iport]).c_str(),
                      circuit_lib.model_name(iport_parent_model).c_str(),
                      circuit_lib.model_name(jport_parent_model).c_str() 
                      ); 
        num_err++;
      }
      if (circuit_lib.port_is_prog(global_ports[iport]) != circuit_lib.port_is_prog(global_ports[jport])) { 
        VTR_LOG_ERROR("Global ports %s from circuit model %s and %s share the same name but have different is_prog attributes!\n",
                      circuit_lib.port_prefix(global_ports[iport]).c_str(),
                      circuit_lib.model_name(iport_parent_model).c_str(),
                      circuit_lib.model_name(jport_parent_model).c_str() 
                      ); 
        num_err++;
      }
    }
  }
  return num_err;
}
static size_t check_circuit_library_ports ( const CircuitLibrary & circuit_lib ) { size_t num_err = 0 ; for ( const auto & port : circuit_lib . ports ( ) ) { if ( ( circuit_lib . port_is_global ( port ) ) && ( ! circuit_lib . is_input_port ( port ) ) && ( ! circuit_lib . is_output_port ( port ) ) ) { VTR_LOG_ERROR ( " \n " , CIRCUIT_MODEL_PORT_TYPE_STRING [ size_t ( circuit_lib . port_type ( port ) ) ] , circuit_lib . model_name ( port ) . c_str ( ) ) ; num_err ++ ; } } for ( const auto & port : circuit_lib . ports ( ) ) { if ( ( circuit_lib . port_is_global ( port ) ) && ( CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib . port_type ( port ) ) && ( false == circuit_lib . port_is_io ( port ) ) ) { VTR_LOG_ERROR ( " \n " , CIRCUIT_MODEL_PORT_TYPE_STRING [ size_t ( circuit_lib . port_type ( port ) ) ] , circuit_lib . model_name ( port ) . c_str ( ) ) ; num_err ++ ; } } for ( const auto & port : circuit_lib . ports ( ) ) { if ( ( ( circuit_lib . port_is_set ( port ) ) || ( circuit_lib . port_is_reset ( port ) ) || ( circuit_lib . port_is_config_enable ( port ) ) ) && ( ! circuit_lib . port_is_global ( port ) ) ) { VTR_LOG_ERROR ( " \n " , CIRCUIT_MODEL_PORT_TYPE_STRING [ size_t ( circuit_lib . port_type ( port ) ) ] , circuit_lib . model_name ( port ) . c_str ( ) ) ; num_err ++ ; } } for ( const auto & port : circuit_lib . ports ( ) ) { if ( circuit_lib . port_tri_state_map ( port ) . empty ( ) ) { continue ; } if ( circuit_lib . port_tri_state_map ( port ) . length ( ) == circuit_lib . port_size ( port ) ) { continue ; } VTR_LOG_ERROR ( " \n " , circuit_lib . port_tri_state_map ( port ) . c_str ( ) , CIRCUIT_MODEL_PORT_TYPE_STRING [ size_t ( circuit_lib . port_type ( port ) ) ] , circuit_lib . model_name ( port ) . c_str ( ) , circuit_lib . port_size ( port ) ) ; num_err ++ ; } std :: vector < CircuitPortId > global_ports ; for ( auto port : circuit_lib . ports ( ) ) { if ( false == circuit_lib . port_is_global ( port ) ) { continue ; } global_ports . push_back ( port ) ; } for ( size_t iport = 0 ; iport < global_ports . size ( ) - 1 ; ++ iport ) { for ( size_t jport = iport + 1 ; jport < global_ports . size ( ) ; ++ jport ) { if ( 0 != circuit_lib . port_prefix ( global_ports [ iport ] ) . compare ( circuit_lib . port_prefix ( global_ports [ jport ] ) ) ) { continue ; } CircuitModelId iport_parent_model = circuit_lib . port_parent_model ( global_ports [ iport ] ) ; CircuitModelId jport_parent_model = circuit_lib . port_parent_model ( global_ports [ jport ] ) ; if ( circuit_lib . port_default_value ( global_ports [ iport ] ) != circuit_lib . port_default_value ( global_ports [ jport ] ) ) { VTR_LOG_ERROR ( " \n " , circuit_lib . port_prefix ( global_ports [ iport ] ) . c_str ( ) , circuit_lib . model_name ( iport_parent_model ) . c_str ( ) , circuit_lib . model_name ( jport_parent_model ) . c_str ( ) , circuit_lib . port_default_value ( global_ports [ iport ] ) , circuit_lib . port_default_value ( global_ports [ jport ] ) ) ; num_err ++ ; } if ( circuit_lib . port_is_reset ( global_ports [ iport ] ) != circuit_lib . port_is_reset ( global_ports [ jport ] ) ) { VTR_LOG_ERROR ( " \n " , circuit_lib . port_prefix ( global_ports [ iport ] ) . c_str ( ) , circuit_lib . model_name ( iport_parent_model ) . c_str ( ) , circuit_lib . model_name ( jport_parent_model ) . c_str ( ) ) ; num_err ++ ; } if ( circuit_lib . port_is_set ( global_ports [ iport ] ) != circuit_lib . port_is_set ( global_ports [ jport ] ) ) { VTR_LOG_ERROR ( " \n " , circuit_lib . port_prefix ( global_ports [ iport ] ) . c_str ( ) , circuit_lib . model_name ( iport_parent_model ) . c_str ( ) , circuit_lib . model_name ( jport_parent_model ) . c_str ( ) ) ; num_err ++ ; } if ( circuit_lib . port_is_config_enable ( global_ports [ iport ] ) != circuit_lib . port_is_config_enable ( global_ports [ jport ] ) ) { VTR_LOG_ERROR ( " \n " , circuit_lib . port_prefix ( global_ports [ iport ] ) . c_str ( ) , circuit_lib . model_name ( iport_parent_model ) . c_str ( ) , circuit_lib . model_name ( jport_parent_model ) . c_str ( ) ) ; num_err ++ ; } if ( circuit_lib . port_is_prog ( global_ports [ iport ] ) != circuit_lib . port_is_prog ( global_ports [ jport ] ) ) { VTR_LOG_ERROR ( " \n " , circuit_lib . port_prefix ( global_ports [ iport ] ) . c_str ( ) , circuit_lib . model_name ( iport_parent_model ) . c_str ( ) , circuit_lib . model_name ( jport_parent_model ) . c_str ( ) ) ; num_err ++ ; } } } return num_err ; }
Check all the ports make sure, they satisfy the restriction
Check all the ports make sure they satisfy the restriction
/* Check global ports: make sure all the global ports are input ports */ /* Check global output ports: make sure they are all I/Os */ /* Check set/reset/config_enable ports: make sure they are all global ports */ /* Check the tri-state map of ports, the length should match the port size! */ /* No tri-state map is found, go to the next */ /* Sizes match, go to the next */ /* We have a problem here, sizes do not match, leave a message and raise the error flag */ /* Check all the global ports which sare the same name also share the same attributes:
   * default_value, is_config, is_reset, is_set etc. 
   */ /* Collect all the global ports */ /* By pass non-global ports*/ /* Bypass those do not share the same name */ /* Check if a same port share the same attributes */