openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
/********************************************************************
 * Print a Verilog file containing simulation-related preprocessing flags
 *******************************************************************/
Print a Verilog file containing simulation-related preprocessing flags
Print a Verilog file containing simulation - related preprocessing flags
void print_verilog_simulation_preprocessing_flags(const std::string& src_dir,
                                                  const VerilogTestbenchOption& verilog_testbench_opts) {
  std::string verilog_fname = src_dir + std::string(DEFINES_VERILOG_SIMULATION_FILE_NAME);
  std::fstream fp;
  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
  check_file_stream(verilog_fname.c_str(), fp);
  print_verilog_file_header(fp, std::string("Preprocessing flags to enable/disable simulation features")); 
  if (true == verilog_testbench_opts.include_signal_init()) {
    print_verilog_define_flag(fp, std::string(VERILOG_SIGNAL_INIT_PREPROC_FLAG), 1);
    fp << std::endl;
  } 
  if (true == verilog_testbench_opts.support_icarus_simulator()) {
    print_verilog_define_flag(fp, std::string(ICARUS_SIMULATOR_FLAG), 1);
    fp << std::endl;
  } 
  if (true == verilog_testbench_opts.print_top_testbench()) {
    print_verilog_define_flag(fp, std::string(INITIAL_SIMULATION_FLAG), 1);
    fp << std::endl;
  } 
  if ( (true == verilog_testbench_opts.print_preconfig_top_testbench())
    || (true == verilog_testbench_opts.print_top_testbench()) ) {
    print_verilog_define_flag(fp, std::string(AUTOCHECKED_SIMULATION_FLAG), 1);
    fp << std::endl;
  } 
  if (true == verilog_testbench_opts.print_formal_verification_top_netlist()) {
    print_verilog_define_flag(fp, std::string(VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG), 1);
    fp << std::endl;
  } 
  if (true == verilog_testbench_opts.print_preconfig_top_testbench()) {
    print_verilog_define_flag(fp, std::string(FORMAL_SIMULATION_FLAG), 1);
    fp << std::endl;
  } 
  fp.close();
}
void print_verilog_simulation_preprocessing_flags ( const std :: string & src_dir , const VerilogTestbenchOption & verilog_testbench_opts ) { std :: string verilog_fname = src_dir + std :: string ( DEFINES_VERILOG_SIMULATION_FILE_NAME ) ; std :: fstream fp ; fp . open ( verilog_fname , std :: fstream :: out | std :: fstream :: trunc ) ; check_file_stream ( verilog_fname . c_str ( ) , fp ) ; print_verilog_file_header ( fp , std :: string ( " " ) ) ; if ( true == verilog_testbench_opts . include_signal_init ( ) ) { print_verilog_define_flag ( fp , std :: string ( VERILOG_SIGNAL_INIT_PREPROC_FLAG ) , 1 ) ; fp << std :: endl ; } if ( true == verilog_testbench_opts . support_icarus_simulator ( ) ) { print_verilog_define_flag ( fp , std :: string ( ICARUS_SIMULATOR_FLAG ) , 1 ) ; fp << std :: endl ; } if ( true == verilog_testbench_opts . print_top_testbench ( ) ) { print_verilog_define_flag ( fp , std :: string ( INITIAL_SIMULATION_FLAG ) , 1 ) ; fp << std :: endl ; } if ( ( true == verilog_testbench_opts . print_preconfig_top_testbench ( ) ) || ( true == verilog_testbench_opts . print_top_testbench ( ) ) ) { print_verilog_define_flag ( fp , std :: string ( AUTOCHECKED_SIMULATION_FLAG ) , 1 ) ; fp << std :: endl ; } if ( true == verilog_testbench_opts . print_formal_verification_top_netlist ( ) ) { print_verilog_define_flag ( fp , std :: string ( VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG ) , 1 ) ; fp << std :: endl ; } if ( true == verilog_testbench_opts . print_preconfig_top_testbench ( ) ) { print_verilog_define_flag ( fp , std :: string ( FORMAL_SIMULATION_FLAG ) , 1 ) ; fp << std :: endl ; } fp . close ( ) ; }
Print a Verilog file containing simulation-related preprocessing flags
Print a Verilog file containing simulation - related preprocessing flags
/* Create the file stream */ /* Validate the file stream */ /* Print the title */ /* To enable signal initialization */ /* To enable functional verfication with Icarus */ /* To enable manualy checked simulation */ /* To enable auto-checked simulation */ /* To enable pre-configured FPGA simulation */ /* To enable pre-configured FPGA simulation */ /* Close the file stream */