openfpga/src/utils/memory_utils.cpp
/********************************************************************
 * Generate a list of ports that are used for SRAM configuration to a module
 * 1. Standalone SRAMs: 
 *    use the suggested port_size 
 * 2. Scan-chain Flip-flops:
 *    IMPORTANT: the port size will be forced to 1 in this case 
 * 3. Memory decoders:
 *    use the suggested port_size 
 ********************************************************************/
Generate a list of ports that are used for SRAM configuration to a module
1. Standalone SRAMs:
use the suggested port_size
2. Scan-chain Flip-flops:
IMPORTANT: the port size will be forced to 1 in this case
3. Memory decoders:
use the suggested port_size
Generate a list of ports that are used for SRAM configuration to a module 1 . Standalone SRAMs : use the suggested port_size 2 . Scan - chain Flip - flops : IMPORTANT : the port size will be forced to 1 in this case 3 . Memory decoders : use the suggested port_size
size_t generate_sram_port_size(const e_config_protocol_type sram_orgz_type,
                               const size_t& num_config_bits) {
  size_t sram_port_size = num_config_bits;
  switch (sram_orgz_type) {
  case CONFIG_MEM_STANDALONE: 
    break;
  case CONFIG_MEM_SCAN_CHAIN: 
    sram_port_size = 1;
    break;
  case CONFIG_MEM_MEMORY_BANK:
    break;
  case CONFIG_MEM_FRAME_BASED:
    break;
  default:
    VTR_LOGF_ERROR(__FILE__, __LINE__,
                   "Invalid type of SRAM organization!\n");
    exit(1);
  }
  return sram_port_size;
}
size_t generate_sram_port_size ( const e_config_protocol_type sram_orgz_type , const size_t & num_config_bits ) { size_t sram_port_size = num_config_bits ; switch ( sram_orgz_type ) { case CONFIG_MEM_STANDALONE : break ; case CONFIG_MEM_SCAN_CHAIN : sram_port_size = 1 ; break ; case CONFIG_MEM_MEMORY_BANK : break ; case CONFIG_MEM_FRAME_BASED : break ; default : VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " ) ; exit ( 1 ) ; } return sram_port_size ; }
Generate a list of ports that are used for SRAM configuration to a module
 1.
Generate a list of ports that are used for SRAM configuration to a module 1 .
/* CCFF head/tail are single-bit ports */