libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp
/********************************************************************
 * Parse XML codes of a circuit model to circuit library
 *******************************************************************/
Parse XML codes of a circuit model to circuit library
Parse XML codes of a circuit model to circuit library
static 
void read_xml_circuit_model(pugi::xml_node& xml_model,
                            const pugiutil::loc_data& loc_data,
                            CircuitLibrary& circuit_lib) {
  const char* type_attr = get_attribute(xml_model, "type", loc_data).value();
  e_circuit_model_type model_type = string_to_circuit_model_type(std::string(type_attr));
  if (NUM_CIRCUIT_MODEL_TYPES == model_type) {
    archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_model),
                   "Invalid 'type' attribute '%s'\n",
                   type_attr);
  }
  CircuitModelId model = circuit_lib.add_model(model_type);
  const char* name_attr = get_attribute(xml_model, "name", loc_data).value();
  circuit_lib.set_model_name(model, std::string(name_attr));
  const char* prefix_attr = get_attribute(xml_model, "prefix", loc_data).value();
  circuit_lib.set_model_prefix(model, std::string(prefix_attr));
  circuit_lib.set_model_spice_netlist(model, get_attribute(xml_model, "spice_netlist", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string(""));
  circuit_lib.set_model_verilog_netlist(model, get_attribute(xml_model, "verilog_netlist", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string(""));
  circuit_lib.set_model_is_default(model, get_attribute(xml_model, "is_default", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
  circuit_lib.set_model_dump_structural_verilog(model, get_attribute(xml_model, "dump_structural_verilog", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
  read_xml_model_design_technology(xml_model, loc_data, circuit_lib, model);
  if (CIRCUIT_MODEL_LUT == circuit_lib.model_type(model)) { 
    auto xml_input_buffer = get_single_child(xml_model, "lut_input_buffer", loc_data); 
    std::string input_buffer_circuit_model_name = read_xml_buffer(xml_input_buffer, loc_data);
    circuit_lib.set_model_lut_input_buffer(model, 
                                           true != input_buffer_circuit_model_name.empty(), 
                                           input_buffer_circuit_model_name);
    auto xml_input_inverter = get_single_child(xml_model, "lut_input_inverter", loc_data); 
    std::string input_inverter_circuit_model_name = read_xml_buffer(xml_input_inverter, loc_data);
    circuit_lib.set_model_lut_input_inverter(model, 
                                             true != input_inverter_circuit_model_name.empty(), 
                                             input_inverter_circuit_model_name);
    auto xml_intermediate_buffer = get_single_child(xml_model, "lut_intermediate_buffer", loc_data, pugiutil::ReqOpt::OPTIONAL); 
    if (xml_intermediate_buffer) {
      std::string intermediate_buffer_circuit_model_name = read_xml_buffer(xml_intermediate_buffer, loc_data);
      circuit_lib.set_model_lut_intermediate_buffer(model, 
                                                    true != intermediate_buffer_circuit_model_name.empty(), 
                                                    intermediate_buffer_circuit_model_name);
      if (true != intermediate_buffer_circuit_model_name.empty()) { 
        circuit_lib.set_model_lut_intermediate_buffer_location_map(model, get_attribute(xml_intermediate_buffer, "location_map", loc_data).as_string());
      }
    }
  }
  if ((CIRCUIT_MODEL_INVBUF == circuit_lib.model_type(model))
      || (CIRCUIT_MODEL_PASSGATE == circuit_lib.model_type(model))
      || (CIRCUIT_MODEL_GATE == circuit_lib.model_type(model))) {
    read_xml_model_device_technology(xml_model, loc_data, circuit_lib, model); 
  }
  if (CIRCUIT_MODEL_INVBUF != circuit_lib.model_type(model)) {
    auto xml_input_buffer = get_single_child(xml_model, "input_buffer", loc_data); 
    std::string input_buffer_circuit_model_name = read_xml_buffer(xml_input_buffer, loc_data);
    circuit_lib.set_model_input_buffer(model, 
                                       true != input_buffer_circuit_model_name.empty(), 
                                       input_buffer_circuit_model_name);
  }
  if (CIRCUIT_MODEL_INVBUF != circuit_lib.model_type(model)) {
    auto xml_output_buffer = get_single_child(xml_model, "output_buffer", loc_data); 
    std::string output_buffer_circuit_model_name = read_xml_buffer(xml_output_buffer, loc_data);
    circuit_lib.set_model_output_buffer(model, 
                                        true != output_buffer_circuit_model_name.empty(), 
                                        output_buffer_circuit_model_name);
  }
  if ( (CIRCUIT_MODEL_LUT == circuit_lib.model_type(model)) 
    || (CIRCUIT_MODEL_MUX == circuit_lib.model_type(model)) ) {
    auto xml_pass_gate_logic = get_single_child(xml_model, "pass_gate_logic", loc_data); 
    circuit_lib.set_model_pass_gate_logic(model, get_attribute(xml_pass_gate_logic, "circuit_model_name", loc_data).as_string());
  } 
  size_t num_ports = count_children(xml_model, "port", loc_data, pugiutil::ReqOpt::OPTIONAL);
  if (0 < num_ports) {
    pugi::xml_node xml_port = get_first_child(xml_model, "port", loc_data);
    while (xml_port) {
      read_xml_circuit_port(xml_port, loc_data, circuit_lib, model);
      xml_port = xml_port.next_sibling(xml_port.name());
    } 
  }
  if ( (CIRCUIT_MODEL_WIRE == circuit_lib.model_type(model))
    || (CIRCUIT_MODEL_CHAN_WIRE == circuit_lib.model_type(model)) ) {
    auto xml_wire_param = get_single_child(xml_model, "wire_param", loc_data); 
    read_xml_wire_param(xml_wire_param, loc_data, circuit_lib, model);
  }
  size_t num_delay_matrix = count_children(xml_model, "delay_matrix", loc_data, pugiutil::ReqOpt::OPTIONAL);
  if (0 < num_delay_matrix) {
    pugi::xml_node xml_delay_matrix = get_first_child(xml_model, "delay_matrix", loc_data);
    while (xml_delay_matrix) {
      read_xml_delay_matrix(xml_delay_matrix, loc_data, circuit_lib, model);
      xml_delay_matrix = xml_delay_matrix.next_sibling(xml_delay_matrix.name());
    }
  }
}
static void read_xml_circuit_model ( pugi :: xml_node & xml_model , const pugiutil :: loc_data & loc_data , CircuitLibrary & circuit_lib ) { const char * type_attr = get_attribute ( xml_model , " " , loc_data ) . value ( ) ; e_circuit_model_type model_type = string_to_circuit_model_type ( std :: string ( type_attr ) ) ; if ( NUM_CIRCUIT_MODEL_TYPES == model_type ) { archfpga_throw ( loc_data . filename_c_str ( ) , loc_data . line ( xml_model ) , " \n " , type_attr ) ; } CircuitModelId model = circuit_lib . add_model ( model_type ) ; const char * name_attr = get_attribute ( xml_model , " " , loc_data ) . value ( ) ; circuit_lib . set_model_name ( model , std :: string ( name_attr ) ) ; const char * prefix_attr = get_attribute ( xml_model , " " , loc_data ) . value ( ) ; circuit_lib . set_model_prefix ( model , std :: string ( prefix_attr ) ) ; circuit_lib . set_model_spice_netlist ( model , get_attribute ( xml_model , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) . as_string ( " " ) ) ; circuit_lib . set_model_verilog_netlist ( model , get_attribute ( xml_model , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) . as_string ( " " ) ) ; circuit_lib . set_model_is_default ( model , get_attribute ( xml_model , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) . as_bool ( false ) ) ; circuit_lib . set_model_dump_structural_verilog ( model , get_attribute ( xml_model , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) . as_bool ( false ) ) ; read_xml_model_design_technology ( xml_model , loc_data , circuit_lib , model ) ; if ( CIRCUIT_MODEL_LUT == circuit_lib . model_type ( model ) ) { auto xml_input_buffer = get_single_child ( xml_model , " " , loc_data ) ; std :: string input_buffer_circuit_model_name = read_xml_buffer ( xml_input_buffer , loc_data ) ; circuit_lib . set_model_lut_input_buffer ( model , true != input_buffer_circuit_model_name . empty ( ) , input_buffer_circuit_model_name ) ; auto xml_input_inverter = get_single_child ( xml_model , " " , loc_data ) ; std :: string input_inverter_circuit_model_name = read_xml_buffer ( xml_input_inverter , loc_data ) ; circuit_lib . set_model_lut_input_inverter ( model , true != input_inverter_circuit_model_name . empty ( ) , input_inverter_circuit_model_name ) ; auto xml_intermediate_buffer = get_single_child ( xml_model , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) ; if ( xml_intermediate_buffer ) { std :: string intermediate_buffer_circuit_model_name = read_xml_buffer ( xml_intermediate_buffer , loc_data ) ; circuit_lib . set_model_lut_intermediate_buffer ( model , true != intermediate_buffer_circuit_model_name . empty ( ) , intermediate_buffer_circuit_model_name ) ; if ( true != intermediate_buffer_circuit_model_name . empty ( ) ) { circuit_lib . set_model_lut_intermediate_buffer_location_map ( model , get_attribute ( xml_intermediate_buffer , " " , loc_data ) . as_string ( ) ) ; } } } if ( ( CIRCUIT_MODEL_INVBUF == circuit_lib . model_type ( model ) ) || ( CIRCUIT_MODEL_PASSGATE == circuit_lib . model_type ( model ) ) || ( CIRCUIT_MODEL_GATE == circuit_lib . model_type ( model ) ) ) { read_xml_model_device_technology ( xml_model , loc_data , circuit_lib , model ) ; } if ( CIRCUIT_MODEL_INVBUF != circuit_lib . model_type ( model ) ) { auto xml_input_buffer = get_single_child ( xml_model , " " , loc_data ) ; std :: string input_buffer_circuit_model_name = read_xml_buffer ( xml_input_buffer , loc_data ) ; circuit_lib . set_model_input_buffer ( model , true != input_buffer_circuit_model_name . empty ( ) , input_buffer_circuit_model_name ) ; } if ( CIRCUIT_MODEL_INVBUF != circuit_lib . model_type ( model ) ) { auto xml_output_buffer = get_single_child ( xml_model , " " , loc_data ) ; std :: string output_buffer_circuit_model_name = read_xml_buffer ( xml_output_buffer , loc_data ) ; circuit_lib . set_model_output_buffer ( model , true != output_buffer_circuit_model_name . empty ( ) , output_buffer_circuit_model_name ) ; } if ( ( CIRCUIT_MODEL_LUT == circuit_lib . model_type ( model ) ) || ( CIRCUIT_MODEL_MUX == circuit_lib . model_type ( model ) ) ) { auto xml_pass_gate_logic = get_single_child ( xml_model , " " , loc_data ) ; circuit_lib . set_model_pass_gate_logic ( model , get_attribute ( xml_pass_gate_logic , " " , loc_data ) . as_string ( ) ) ; } size_t num_ports = count_children ( xml_model , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) ; if ( 0 < num_ports ) { pugi :: xml_node xml_port = get_first_child ( xml_model , " " , loc_data ) ; while ( xml_port ) { read_xml_circuit_port ( xml_port , loc_data , circuit_lib , model ) ; xml_port = xml_port . next_sibling ( xml_port . name ( ) ) ; } } if ( ( CIRCUIT_MODEL_WIRE == circuit_lib . model_type ( model ) ) || ( CIRCUIT_MODEL_CHAN_WIRE == circuit_lib . model_type ( model ) ) ) { auto xml_wire_param = get_single_child ( xml_model , " " , loc_data ) ; read_xml_wire_param ( xml_wire_param , loc_data , circuit_lib , model ) ; } size_t num_delay_matrix = count_children ( xml_model , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) ; if ( 0 < num_delay_matrix ) { pugi :: xml_node xml_delay_matrix = get_first_child ( xml_model , " " , loc_data ) ; while ( xml_delay_matrix ) { read_xml_delay_matrix ( xml_delay_matrix , loc_data , circuit_lib , model ) ; xml_delay_matrix = xml_delay_matrix . next_sibling ( xml_delay_matrix . name ( ) ) ; } } }
Parse XML codes of a circuit model to circuit library
Parse XML codes of a circuit model to circuit library
/* Find the type of the circuit model
   * so that we can add a new circuit model to circuit library 
   */ /* Translate the type of circuit model to enumerate */ /* Find the name of the circuit model */ /* TODO: This attribute is going to be DEPRECATED 
   * Find the prefix of the circuit model
   */ /* Find a SPICE netlist which is an optional attribute*/ /* Find a Verilog netlist which is an optional attribute*/ /* Find if the circuit model is default in its type */ /* Find if the circuit model is should be dumped in structural verilog */ /* Parse attributes under the <circuit_model> */ /* Design technology -related attributes */ /* Parse special buffer attributes required by LUTs only */ /* Input buffer of LUTs */ /* Input inverter of LUTs */ /* Intermediate buffer of LUTs */ /* If intermediate buffer is defined, try to find the location map */ /* Parse device technology attributes
   * This is applicable to only atom circuit models:
   * - inverter/buffer
   * - pass gate
   * - logic gates
   */ /* Input buffer attributes, NOT required for circuit models which are inverters or buffers */ /* Output buffer attributes, NOT required for circuit models which are inverters or buffers */ /* Pass-gate-logic attributes, required by LUT and MUX */ /* Parse all the ports belonging to this circuit model
   * We count the number of ports in total and then add one by one 
   */ /* Parse the parasitics of wires */ /* Parse all the delay matrix if defined */