openfpga/src/fpga_spice/spice_writer_utils.cpp
/************************************************
 * Print a SPICE subckt definition
 * We use the following format:
 * module <module_name> (<ports without directions>);
 ***********************************************/
Print a SPICE subckt definition
We use the following format:
module  ().
Print a SPICE subckt definition We use the following format : module () .
void print_spice_subckt_definition(std::fstream& fp, 
                                   const ModuleManager& module_manager,
                                   const ModuleId& module_id,
                                   const bool& include_supply_ports) {
  VTR_ASSERT(true == valid_file_stream(fp));
  print_spice_comment(fp, std::string("SPICE module for " + module_manager.module_name(module_id)));
  std::string module_head_line = ".subckt " + module_manager.module_name(module_id) + " ";
  fp << module_head_line;
  bool new_line = false;
  size_t pin_cnt = 0;
  for (int port_type = ModuleManager::MODULE_GLOBAL_PORT;
       port_type < ModuleManager::NUM_MODULE_PORT_TYPES;
       ++port_type) {
    for (const auto& port : module_manager.module_ports_by_type(module_id, static_cast<ModuleManager::e_module_port_type>(port_type))) {
      ModulePortId port_id = module_manager.find_module_port(module_id, port.get_name());
      VTR_ASSERT(ModulePortId::INVALID() != port_id);
      for (const auto& pin : port.pins()) {
        if (true == new_line) {
          std::string port_whitespace(module_head_line.length() - 2, ' ');
          fp << "+ " << port_whitespace;
        }
        if (0 != pin_cnt) {
          write_space_to_file(fp, 1);
        }
        BasicPort port_pin(port.get_name(), pin, pin);
        bool omit_pin_zero = false;
        if ((1 == port.pins().size())
           && (0 == pin)) {
          omit_pin_zero = true;
        }
        fp << generate_spice_port(port_pin, omit_pin_zero);
        pin_cnt++;
        new_line = false;
        if (SPICE_NETLIST_MAX_NUM_PORTS_PER_LINE == pin_cnt) {
          pin_cnt = 0;
          fp << std::endl;
          new_line = true;
        }
      }
    }
  }
  if (true == include_supply_ports) {
    if (true == new_line) {
      std::string port_whitespace(module_head_line.length() - 2, ' ');
      fp << "+ " << port_whitespace;
    }
    write_space_to_file(fp, 1);
    fp << SPICE_SUBCKT_VDD_PORT_NAME;
    write_space_to_file(fp, 1);
    fp << SPICE_SUBCKT_GND_PORT_NAME;
  }
  fp << std::endl;
}
void print_spice_subckt_definition ( std :: fstream & fp , const ModuleManager & module_manager , const ModuleId & module_id , const bool & include_supply_ports ) { VTR_ASSERT ( true == valid_file_stream ( fp ) ) ; print_spice_comment ( fp , std :: string ( " " + module_manager . module_name ( module_id ) ) ) ; std :: string module_head_line = " " + module_manager . module_name ( module_id ) + " " ; fp << module_head_line ; bool new_line = false ; size_t pin_cnt = 0 ; for ( int port_type = ModuleManager :: MODULE_GLOBAL_PORT ; port_type < ModuleManager :: NUM_MODULE_PORT_TYPES ; ++ port_type ) { for ( const auto & port : module_manager . module_ports_by_type ( module_id , static_cast < ModuleManager :: e_module_port_type > ( port_type ) ) ) { ModulePortId port_id = module_manager . find_module_port ( module_id , port . get_name ( ) ) ; VTR_ASSERT ( ModulePortId :: INVALID ( ) != port_id ) ; for ( const auto & pin : port . pins ( ) ) { if ( true == new_line ) { std :: string port_whitespace ( module_head_line . length ( ) - 2 , ' ' ) ; fp << " " << port_whitespace ; } if ( 0 != pin_cnt ) { write_space_to_file ( fp , 1 ) ; } BasicPort port_pin ( port . get_name ( ) , pin , pin ) ; bool omit_pin_zero = false ; if ( ( 1 == port . pins ( ) . size ( ) ) && ( 0 == pin ) ) { omit_pin_zero = true ; } fp << generate_spice_port ( port_pin , omit_pin_zero ) ; pin_cnt ++ ; new_line = false ; if ( SPICE_NETLIST_MAX_NUM_PORTS_PER_LINE == pin_cnt ) { pin_cnt = 0 ; fp << std :: endl ; new_line = true ; } } } } if ( true == include_supply_ports ) { if ( true == new_line ) { std :: string port_whitespace ( module_head_line . length ( ) - 2 , ' ' ) ; fp << " " << port_whitespace ; } write_space_to_file ( fp , 1 ) ; fp << SPICE_SUBCKT_VDD_PORT_NAME ; write_space_to_file ( fp , 1 ) ; fp << SPICE_SUBCKT_GND_PORT_NAME ; } fp << std :: endl ; }
Print a SPICE subckt definition
 We use the following format:
 module <module_name> (<ports without directions>);
Print a SPICE subckt definition We use the following format : module <module_name > ( <ports without directions > ) ;
/* Port sequence: global, inout, input, output and clock ports, */ /* Print port: only the port name is enough */ /* For single-bit port,
         * we can print the port name directly
         */ /* Increase the counter */ /* Currently we limit 10 ports per line to keep a clean netlist */ /* Add supply ports if specified */ /* Print VDD and VSS ports
     * TODO: the supply ports should be derived from module manager
     */