openfpga/src/fpga_sdc/sdc_hierarchy_writer.cpp
/***************************************************************************************
 * Write the hierarchy of Switch Block module and its instances to a plain text file
 * e.g.,
 *    <sdc_file_for_the_module>
 *      <module_name>/<instance_name>
 *        ...
 * This file is mainly used by hierarchical P&R flow 
 *
 * Return 0 if successful
 * Return 1 if there are more serious bugs in the architecture 
 * Return 2 if fail when creating files
 ***************************************************************************************/
Write the hierarchy of Switch Block module and its instances to a plain text file
e.g.,

/

This file is mainly used by hierarchical P&R flow

Return 0 if successful
Return 1 if there are more serious bugs in the architecture
Return 2 if fail when creating files
Write the hierarchy of Switch Block module and its instances to a plain text file e . g . / This file is mainly used by hierarchical P&R flow Return 0 if successful Return 1 if there are more serious bugs in the architecture Return 2 if fail when creating files
void print_pnr_sdc_routing_sb_hierarchy(const std::string& sdc_dir,
                                        const ModuleManager& module_manager,
                                        const ModuleId& top_module,
                                        const DeviceRRGSB& device_rr_gsb) {
  std::string fname(sdc_dir + std::string(SDC_SB_HIERARCHY_FILE_NAME));
  std::string timer_message = std::string("Write Switch Block hierarchy to plain-text file '") + fname + std::string("'");
  std::string dir_path = format_dir_path(find_path_dir_name(fname));
  create_directory(dir_path);
  vtr::ScopedStartFinishTimer timer(timer_message);
  VTR_ASSERT(true != fname.empty());
  std::fstream fp;
  fp.open(fname, std::fstream::out | std::fstream::trunc);
  check_file_stream(fname.c_str(), fp);
  for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) {
    const RRGSB& rr_gsb = device_rr_gsb.get_sb_unique_module(isb);
    if (false == rr_gsb.is_sb_exist()) {
      continue;
    }
    vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
    std::string sb_module_name = generate_switch_block_module_name(gsb_coordinate); 
    ModuleId sb_module = module_manager.find_module(sb_module_name);
    VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
    std::string sdc_fname(sdc_dir + generate_switch_block_module_name(gsb_coordinate) + std::string(SDC_FILE_NAME_POSTFIX));
    fp << "- " << sb_module_name << ":" << "\n";
    for (const size_t& instance_id : module_manager.child_module_instances(top_module, sb_module)) {
      std::string sb_instance_name = module_manager.instance_name(top_module, sb_module, instance_id);
      fp << "  ";
      fp << "- " << sb_instance_name << "\n";  
    } 
    fp << "\n";
  }
  fp.close();
}
void print_pnr_sdc_routing_sb_hierarchy ( const std :: string & sdc_dir , const ModuleManager & module_manager , const ModuleId & top_module , const DeviceRRGSB & device_rr_gsb ) { std :: string fname ( sdc_dir + std :: string ( SDC_SB_HIERARCHY_FILE_NAME ) ) ; std :: string timer_message = std :: string ( " " ) + fname + std :: string ( " " ) ; std :: string dir_path = format_dir_path ( find_path_dir_name ( fname ) ) ; create_directory ( dir_path ) ; vtr :: ScopedStartFinishTimer timer ( timer_message ) ; VTR_ASSERT ( true != fname . empty ( ) ) ; std :: fstream fp ; fp . open ( fname , std :: fstream :: out | std :: fstream :: trunc ) ; check_file_stream ( fname . c_str ( ) , fp ) ; for ( size_t isb = 0 ; isb < device_rr_gsb . get_num_sb_unique_module ( ) ; ++ isb ) { const RRGSB & rr_gsb = device_rr_gsb . get_sb_unique_module ( isb ) ; if ( false == rr_gsb . is_sb_exist ( ) ) { continue ; } vtr :: Point < size_t > gsb_coordinate ( rr_gsb . get_sb_x ( ) , rr_gsb . get_sb_y ( ) ) ; std :: string sb_module_name = generate_switch_block_module_name ( gsb_coordinate ) ; ModuleId sb_module = module_manager . find_module ( sb_module_name ) ; VTR_ASSERT ( true == module_manager . valid_module_id ( sb_module ) ) ; std :: string sdc_fname ( sdc_dir + generate_switch_block_module_name ( gsb_coordinate ) + std :: string ( SDC_FILE_NAME_POSTFIX ) ) ; fp << " " << sb_module_name << " " << " \n " ; for ( const size_t & instance_id : module_manager . child_module_instances ( top_module , sb_module ) ) { std :: string sb_instance_name = module_manager . instance_name ( top_module , sb_module , instance_id ) ; fp << " " ; fp << " " << sb_instance_name << " \n " ; } fp << " \n " ; } fp . close ( ) ; }
Write the hierarchy of Switch Block module and its instances to a plain text file
 e.g.,
    <sdc_file_for_the_module>
      <module_name>/<instance_name>
        ...
Write the hierarchy of Switch Block module and its instances to a plain text file e . g . <sdc_file_for_the_module > <module_name > / <instance_name > ...
/* Create directories */ /* Start time count */ /* Use default name if user does not provide one */ /* Create a file handler*/ /* Open a file */ /* Validate the file stream */ /* Find all the sb instance under this module
     * Create a regular expression to include these instance names 
     */ /* Create the file name for SDC */ /* Go through all the instance */ /* close a file */