openfpga/src/utils/memory_utils.cpp
/*********************************************************************
 * Create a port-to-port map for a ReRAM-based memory module 
 * Memory bank 
 * -----------
 *
 *        config_bus (BL)   config_bus (WL) 
 *            |                   |
 *            v                   v
 *      +-------------------------------------+
 *      |        ReRAM-based Memory Module    |
 *      +-------------------------------------+
 *            |                   |
 *            v                   v
 *         Mem_out              Mem_outb
 **********************************************************************/
Create a port-to-port map for a ReRAM-based memory module
Memory bank


Create a port - to - port map for a ReRAM - based memory module Memory bank
static 
std::map<std::string, BasicPort> generate_rram_mem_module_port2port_map(const BasicPort& config_bus,
                                                                        const std::vector<BasicPort>& mem_output_bus_ports,
                                                                        const e_config_protocol_type& sram_orgz_type) {
  std::map<std::string, BasicPort> port2port_name_map;
  switch (sram_orgz_type) {
  case CONFIG_MEM_STANDALONE:
    break;
  case CONFIG_MEM_SCAN_CHAIN: {
    std::vector<BasicPort> config_bus_ports;
    config_bus_ports.push_back(BasicPort(generate_local_config_bus_port_name(), config_bus.get_msb(), config_bus.get_msb() + 1));
    BasicPort head_port(config_bus_ports[0].get_name(), config_bus_ports[0].get_lsb(), config_bus_ports[0].get_lsb()); 
    port2port_name_map[generate_configuration_chain_head_name()] = head_port;
    BasicPort tail_port(config_bus_ports[0].get_name(), config_bus_ports[0].get_msb(), config_bus_ports[0].get_msb()); 
    port2port_name_map[generate_configuration_chain_tail_name()] = tail_port;
    VTR_ASSERT( 2 == mem_output_bus_ports.size() );
    port2port_name_map[generate_configurable_memory_data_out_name()] = mem_output_bus_ports[0];
    port2port_name_map[generate_configurable_memory_inverted_data_out_name()] = mem_output_bus_ports[1];
    break;
  }
  case CONFIG_MEM_MEMORY_BANK:
    break;
  default:
    VTR_LOGF_ERROR(__FILE__, __LINE__,
                   "Invalid type of SRAM organization!\n");
    exit(1);
  }
  return port2port_name_map;
}
static std :: map < std :: string , BasicPort > generate_rram_mem_module_port2port_map ( const BasicPort & config_bus , const std :: vector < BasicPort > & mem_output_bus_ports , const e_config_protocol_type & sram_orgz_type ) { std :: map < std :: string , BasicPort > port2port_name_map ; switch ( sram_orgz_type ) { case CONFIG_MEM_STANDALONE : break ; case CONFIG_MEM_SCAN_CHAIN : { std :: vector < BasicPort > config_bus_ports ; config_bus_ports . push_back ( BasicPort ( generate_local_config_bus_port_name ( ) , config_bus . get_msb ( ) , config_bus . get_msb ( ) + 1 ) ) ; BasicPort head_port ( config_bus_ports [ 0 ] . get_name ( ) , config_bus_ports [ 0 ] . get_lsb ( ) , config_bus_ports [ 0 ] . get_lsb ( ) ) ; port2port_name_map [ generate_configuration_chain_head_name ( ) ] = head_port ; BasicPort tail_port ( config_bus_ports [ 0 ] . get_name ( ) , config_bus_ports [ 0 ] . get_msb ( ) , config_bus_ports [ 0 ] . get_msb ( ) ) ; port2port_name_map [ generate_configuration_chain_tail_name ( ) ] = tail_port ; VTR_ASSERT ( 2 == mem_output_bus_ports . size ( ) ) ; port2port_name_map [ generate_configurable_memory_data_out_name ( ) ] = mem_output_bus_ports [ 0 ] ; port2port_name_map [ generate_configurable_memory_inverted_data_out_name ( ) ] = mem_output_bus_ports [ 1 ] ; break ; } case CONFIG_MEM_MEMORY_BANK : break ; default : VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " ) ; exit ( 1 ) ; } return port2port_name_map ; }
Create a port-to-port map for a ReRAM-based memory module
 Memory bank
Create a port - to - port map for a ReRAM - based memory module Memory bank
/* Not supported */ /* Link the head port of the memory module: 
     * the LSB of config bus port is the head port index
     */ /* Link the tail port of the memory module: 
     * the MSB of config bus port is the tail port index 
     */ /* Link the SRAM output ports of the memory module */ /* TODO: link BL/WL/Reserved Ports to the inputs of a memory module */