libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp
/********************************************************************
 * A writer to output the design technology of a circuit model to XML format
 *******************************************************************/
A writer to output the design technology of a circuit model to XML format
A writer to output the design technology of a circuit model to XML format
static 
void write_xml_design_technology(std::fstream& fp,
                                 const char* fname,
                                 const CircuitLibrary& circuit_lib,
                                 const CircuitModelId& model) {
  openfpga::check_file_stream(fname, fp);
  fp << "\t\t\t" << "<design_technology";
  write_xml_attribute(fp, "type", CIRCUIT_MODEL_DESIGN_TECH_TYPE_STRING[circuit_lib.design_tech_type(model)]);
  if (true == circuit_lib.is_power_gated(model)) {
    write_xml_attribute(fp, "power_gated", "true");
  }
  if (CIRCUIT_MODEL_INVBUF == circuit_lib.model_type(model)) {
    write_xml_attribute(fp, "topology", CIRCUIT_MODEL_BUFFER_TYPE_STRING[circuit_lib.buffer_type(model)]); 
    write_xml_attribute(fp, "size", std::to_string(circuit_lib.buffer_size(model)).c_str()); 
    if (1 < circuit_lib.buffer_num_levels(model)) {
      write_xml_attribute(fp, "num_level", std::to_string(circuit_lib.buffer_num_levels(model)).c_str()); 
      write_xml_attribute(fp, "f_per_stage", std::to_string(circuit_lib.buffer_f_per_stage(model)).c_str()); 
    }
  }
  if (CIRCUIT_MODEL_PASSGATE == circuit_lib.model_type(model)) {
    write_xml_attribute(fp, "topology", CIRCUIT_MODEL_PASSGATE_TYPE_STRING[circuit_lib.pass_gate_logic_type(model)]); 
    write_xml_attribute(fp, "pmos_size", std::to_string(circuit_lib.pass_gate_logic_pmos_size(model)).c_str()); 
    write_xml_attribute(fp, "nmos_size", std::to_string(circuit_lib.pass_gate_logic_nmos_size(model)).c_str()); 
  }
  if (CIRCUIT_MODEL_LUT == circuit_lib.model_type(model)) {
    if (true == circuit_lib.is_lut_fracturable(model)) {
      write_xml_attribute(fp, "fracturable_lut", "true");
    }
  }
  if (CIRCUIT_MODEL_MUX == circuit_lib.model_type(model)) {
    write_xml_attribute(fp, "structure", CIRCUIT_MODEL_STRUCTURE_TYPE_STRING[circuit_lib.mux_structure(model)]); 
    if (true == circuit_lib.mux_add_const_input(model)) {
      write_xml_attribute(fp, "add_const_input", "true"); 
      write_xml_attribute(fp, "const_input_val", std::to_string(circuit_lib.mux_const_input_value(model)).c_str()); 
    }
    if (CIRCUIT_MODEL_STRUCTURE_MULTILEVEL == circuit_lib.mux_structure(model)) {
      write_xml_attribute(fp, "num_level", std::to_string(circuit_lib.mux_num_levels(model)).c_str()); 
    }
    if (true == circuit_lib.mux_use_advanced_rram_design(model)) {
      write_xml_attribute(fp, "advanced_rram_design", "true"); 
    }
    if (true == circuit_lib.mux_use_local_encoder(model)) {
      write_xml_attribute(fp, "local_encoder", "true"); 
    }
  }
  if (CIRCUIT_MODEL_GATE == circuit_lib.model_type(model)) {
    write_xml_attribute(fp, "topology", CIRCUIT_MODEL_GATE_TYPE_STRING[circuit_lib.gate_type(model)]); 
  }
  if (CIRCUIT_MODEL_DESIGN_RRAM == circuit_lib.design_tech_type(model)) {
    write_xml_attribute(fp, "ron", std::to_string(circuit_lib.rram_rlrs(model)).c_str()); 
    write_xml_attribute(fp, "roff", std::to_string(circuit_lib.rram_rhrs(model)).c_str()); 
    write_xml_attribute(fp, "wprog_set_pmos", std::to_string(circuit_lib.rram_wprog_set_pmos(model)).c_str()); 
    write_xml_attribute(fp, "wprog_set_nmos", std::to_string(circuit_lib.rram_wprog_set_nmos(model)).c_str()); 
    write_xml_attribute(fp, "wprog_reset_pmos", std::to_string(circuit_lib.rram_wprog_reset_pmos(model)).c_str()); 
    write_xml_attribute(fp, "wprog_reset_nmos", std::to_string(circuit_lib.rram_wprog_reset_nmos(model)).c_str()); 
  }
  fp << "/>" << "\n";
}
static void write_xml_design_technology ( std :: fstream & fp , const char * fname , const CircuitLibrary & circuit_lib , const CircuitModelId & model ) { openfpga :: check_file_stream ( fname , fp ) ; fp << " \t \t \t " << " " ; write_xml_attribute ( fp , " " , CIRCUIT_MODEL_DESIGN_TECH_TYPE_STRING [ circuit_lib . design_tech_type ( model ) ] ) ; if ( true == circuit_lib . is_power_gated ( model ) ) { write_xml_attribute ( fp , " " , " " ) ; } if ( CIRCUIT_MODEL_INVBUF == circuit_lib . model_type ( model ) ) { write_xml_attribute ( fp , " " , CIRCUIT_MODEL_BUFFER_TYPE_STRING [ circuit_lib . buffer_type ( model ) ] ) ; write_xml_attribute ( fp , " " , std :: to_string ( circuit_lib . buffer_size ( model ) ) . c_str ( ) ) ; if ( 1 < circuit_lib . buffer_num_levels ( model ) ) { write_xml_attribute ( fp , " " , std :: to_string ( circuit_lib . buffer_num_levels ( model ) ) . c_str ( ) ) ; write_xml_attribute ( fp , " " , std :: to_string ( circuit_lib . buffer_f_per_stage ( model ) ) . c_str ( ) ) ; } } if ( CIRCUIT_MODEL_PASSGATE == circuit_lib . model_type ( model ) ) { write_xml_attribute ( fp , " " , CIRCUIT_MODEL_PASSGATE_TYPE_STRING [ circuit_lib . pass_gate_logic_type ( model ) ] ) ; write_xml_attribute ( fp , " " , std :: to_string ( circuit_lib . pass_gate_logic_pmos_size ( model ) ) . c_str ( ) ) ; write_xml_attribute ( fp , " " , std :: to_string ( circuit_lib . pass_gate_logic_nmos_size ( model ) ) . c_str ( ) ) ; } if ( CIRCUIT_MODEL_LUT == circuit_lib . model_type ( model ) ) { if ( true == circuit_lib . is_lut_fracturable ( model ) ) { write_xml_attribute ( fp , " " , " " ) ; } } if ( CIRCUIT_MODEL_MUX == circuit_lib . model_type ( model ) ) { write_xml_attribute ( fp , " " , CIRCUIT_MODEL_STRUCTURE_TYPE_STRING [ circuit_lib . mux_structure ( model ) ] ) ; if ( true == circuit_lib . mux_add_const_input ( model ) ) { write_xml_attribute ( fp , " " , " " ) ; write_xml_attribute ( fp , " " , std :: to_string ( circuit_lib . mux_const_input_value ( model ) ) . c_str ( ) ) ; } if ( CIRCUIT_MODEL_STRUCTURE_MULTILEVEL == circuit_lib . mux_structure ( model ) ) { write_xml_attribute ( fp , " " , std :: to_string ( circuit_lib . mux_num_levels ( model ) ) . c_str ( ) ) ; } if ( true == circuit_lib . mux_use_advanced_rram_design ( model ) ) { write_xml_attribute ( fp , " " , " " ) ; } if ( true == circuit_lib . mux_use_local_encoder ( model ) ) { write_xml_attribute ( fp , " " , " " ) ; } } if ( CIRCUIT_MODEL_GATE == circuit_lib . model_type ( model ) ) { write_xml_attribute ( fp , " " , CIRCUIT_MODEL_GATE_TYPE_STRING [ circuit_lib . gate_type ( model ) ] ) ; } if ( CIRCUIT_MODEL_DESIGN_RRAM == circuit_lib . design_tech_type ( model ) ) { write_xml_attribute ( fp , " " , std :: to_string ( circuit_lib . rram_rlrs ( model ) ) . c_str ( ) ) ; write_xml_attribute ( fp , " " , std :: to_string ( circuit_lib . rram_rhrs ( model ) ) . c_str ( ) ) ; write_xml_attribute ( fp , " " , std :: to_string ( circuit_lib . rram_wprog_set_pmos ( model ) ) . c_str ( ) ) ; write_xml_attribute ( fp , " " , std :: to_string ( circuit_lib . rram_wprog_set_nmos ( model ) ) . c_str ( ) ) ; write_xml_attribute ( fp , " " , std :: to_string ( circuit_lib . rram_wprog_reset_pmos ( model ) ) . c_str ( ) ) ; write_xml_attribute ( fp , " " , std :: to_string ( circuit_lib . rram_wprog_reset_nmos ( model ) ) . c_str ( ) ) ; } fp << " " << " \n " ; }
A writer to output the design technology of a circuit model to XML format
A writer to output the design technology of a circuit model to XML format
/* Validate the file stream */ /* Buffer-related information */ /* Pass-gate-logic -related information */ /* Look-Up Table (LUT)-related information */ /* Multiplexer-related information */ /* Gate-related information */ /* ReRAM-related information */ /* Finish all the attributes, we can return here */