third_party/virtualbox/src/VBox/Devices/Network/DevE1000.cpp
/**
 * Write handler for Interrupt Mask Set register.
 *
 * Will trigger pending interrupts.
 *
 * @param   pThis       The device state structure.
 * @param   offset      Register offset in memory-mapped frame.
 * @param   index       Register index in register array.
 * @param   value       The value to store.
 * @param   mask        Used to implement partial writes (8 and 16-bit).
 * @thread  EMT
 */
Write handler for Interrupt Mask Set register.
Will trigger pending interrupts.

@param   pThis       The device state structure.
@param   offset      Register offset in memory-mapped frame.
@param   index       Register index in register array.
@param   value       The value to store.
@param   mask        Used to implement partial writes (8 and 16-bit).
@thread  EMT
Write handler for Interrupt Mask Set register . Will trigger pending interrupts . @param pThis The device state structure . @param offset Register offset in memory - mapped frame . @param index Register index in register array . @param value The value to store . @param mask Used to implement partial writes ( 8 and 16 - bit ) . @thread EMT
static int e1kRegWriteIMS(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
{
    RT_NOREF_PV(offset); RT_NOREF_PV(index);
    IMS |= value;
    E1kLogRel(("E1000: irq enabled, RDH=%x RDT=%x TDH=%x TDT=%x\n", RDH, RDT, TDH, TDT));
    E1kLog(("%s e1kRegWriteIMS: IRQ enabled\n", pThis->szPrf));
    if ((ICR & IMS) && !pThis->fLocked)
    {
        E1K_INC_ISTAT_CNT(pThis->uStatIntIMS);
        e1kPostponeInterrupt(pThis, E1K_IMS_INT_DELAY_NS);
    }
    return VINF_SUCCESS;
}
static int e1kRegWriteIMS ( PE1KSTATE pThis , uint32_t offset , uint32_t index , uint32_t value ) { RT_NOREF_PV ( offset ) ; RT_NOREF_PV ( index ) ; IMS |= value ; E1kLogRel ( ( " \n " , RDH , RDT , TDH , TDT ) ) ; E1kLog ( ( " \n " , pThis -> szPrf ) ) ; if ( ( ICR & IMS ) && ! pThis -> fLocked ) { E1K_INC_ISTAT_CNT ( pThis -> uStatIntIMS ) ; e1kPostponeInterrupt ( pThis , E1K_IMS_INT_DELAY_NS ) ; } return VINF_SUCCESS ; }
Write handler for Interrupt Mask Set register.
Write handler for Interrupt Mask Set register .
/*
     * We cannot raise an interrupt here as it will occasionally cause an interrupt storm
     * in Windows guests (see @bugref{8624}, @bugref{5023}).
     */