openfpga/src/repack/build_physical_lb_rr_graph.cpp
/***************************************************************************************
 * Build the edge for an input/clock pb_graph_pin for a primitive pb_graph node
 * This function will identify if the port equivalence should be considered 
 ***************************************************************************************/
Build the edge for an input/clock pb_graph_pin for a primitive pb_graph node
This function will identify if the port equivalence should be considered
Build the edge for an input / clock pb_graph_pin for a primitive pb_graph node This function will identify if the port equivalence should be considered
static 
void build_lb_rr_edge_primitive_pb_graph_input_pin(LbRRGraph& lb_rr_graph,
                                                   t_pb_graph_pin* pb_pin,
                                                   LbRRNodeId& sink_node) {
  LbRRNodeId node = lb_rr_graph.find_node(LB_INTERMEDIATE, pb_pin);
  VTR_ASSERT(true == lb_rr_graph.valid_node_id(node));
  PortEquivalence port_equivalent = pb_pin->port->equivalent;
  if (port_equivalent == PortEquivalence::NONE || sink_node == LbRRNodeId::INVALID()) {
    LbRRNodeId new_sink = lb_rr_graph.create_node(LB_SINK);
    if (port_equivalent != PortEquivalence::NONE) {
      lb_rr_graph.set_node_capacity(new_sink, pb_pin->port->num_pins);
    } else {
      lb_rr_graph.set_node_capacity(new_sink, 1);
    }
    sink_node = new_sink;
  }
  LbRREdgeId edge = lb_rr_graph.create_edge(node, sink_node, nullptr);
  lb_rr_graph.set_edge_intrinsic_cost(edge, 1.); 
}
static void build_lb_rr_edge_primitive_pb_graph_input_pin ( LbRRGraph & lb_rr_graph , t_pb_graph_pin * pb_pin , LbRRNodeId & sink_node ) { LbRRNodeId node = lb_rr_graph . find_node ( LB_INTERMEDIATE , pb_pin ) ; VTR_ASSERT ( true == lb_rr_graph . valid_node_id ( node ) ) ; PortEquivalence port_equivalent = pb_pin -> port -> equivalent ; if ( port_equivalent == PortEquivalence :: NONE || sink_node == LbRRNodeId :: INVALID ( ) ) { LbRRNodeId new_sink = lb_rr_graph . create_node ( LB_SINK ) ; if ( port_equivalent != PortEquivalence :: NONE ) { lb_rr_graph . set_node_capacity ( new_sink , pb_pin -> port -> num_pins ) ; } else { lb_rr_graph . set_node_capacity ( new_sink , 1 ) ; } sink_node = new_sink ; } LbRREdgeId edge = lb_rr_graph . create_edge ( node , sink_node , nullptr ) ; lb_rr_graph . set_edge_intrinsic_cost ( edge , 1. ) ; }
Build the edge for an input/clock pb_graph_pin for a primitive pb_graph node
 This function will identify if the port equivalence should be considered
Build the edge for an input / clock pb_graph_pin for a primitive pb_graph node This function will identify if the port equivalence should be considered
/* Find the node that we have already created */ /* Create new sink for input to primitive */ /* Connect the nodes denoting the input pins to sink, since this is a primtive node, we do not have any mode */ /* TODO: Double check if this is the case */