src/bins/decode.cc
/*
 * Queues an absolute addressed reg indexed write instruction using the given
 * micro operation.
 */
Queues an absolute addressed reg indexed write instruction using the given
micro operation.
Queues an absolute addressed reg indexed write instruction using the given micro operation .
void Decode::DecodeWAbR(CpuOperation op, CpuReg reg) {
  state_->AddCycle(MEM_READ | MEM_OP1(REG_ADDRL) | MEM_ADDR(REG_PCL) | PC_INC);
  state_->AddCycle(MEM_READ | MEM_OP1(REG_ADDRH) | MEM_ADDR(REG_PCL)
                 | DAT_ADD | DAT_DST(REG_ADDRL) | DAT_SRC(reg) | PC_INC);
  state_->AddCycle(MEM_READ | MEM_OP1(REG_TMP1) | MEM_ADDR(REG_ADDRL)
                 | DAT_ADD | DAT_DST(REG_ADDRH) | DAT_SRC(REG_TMP2));
  state_->AddCycle(op);
  state_->AddCycle(MEM_FETCH | PC_INC);
  return;
}
void Decode :: DecodeWAbR ( CpuOperation op , CpuReg reg ) { state_ -> AddCycle ( MEM_READ | MEM_OP1 ( REG_ADDRL ) | MEM_ADDR ( REG_PCL ) | PC_INC ) ; state_ -> AddCycle ( MEM_READ | MEM_OP1 ( REG_ADDRH ) | MEM_ADDR ( REG_PCL ) | DAT_ADD | DAT_DST ( REG_ADDRL ) | DAT_SRC ( reg ) | PC_INC ) ; state_ -> AddCycle ( MEM_READ | MEM_OP1 ( REG_TMP1 ) | MEM_ADDR ( REG_ADDRL ) | DAT_ADD | DAT_DST ( REG_ADDRH ) | DAT_SRC ( REG_TMP2 ) ) ; state_ -> AddCycle ( op ) ; state_ -> AddCycle ( MEM_FETCH | PC_INC ) ; return ; }
Queues an absolute addressed reg indexed write instruction using the given
 micro operation.
Queues an absolute addressed reg indexed write instruction using the given micro operation .