third_party/virtualbox/src/VBox/Devices/Network/DevE1000.cpp
/**
 * Write handler for Interrupt Cause Read register.
 *
 * Bits corresponding to 1s in 'value' will be cleared in ICR register.
 *
 * @param   pThis       The device state structure.
 * @param   offset      Register offset in memory-mapped frame.
 * @param   index       Register index in register array.
 * @param   value       The value to store.
 * @param   mask        Used to implement partial writes (8 and 16-bit).
 * @thread  EMT
 */
Write handler for Interrupt Cause Read register.
Bits corresponding to 1s in 'value' will be cleared in ICR register.

@param   pThis       The device state structure.
@param   offset      Register offset in memory-mapped frame.
@param   index       Register index in register array.
@param   value       The value to store.
@param   mask        Used to implement partial writes (8 and 16-bit).
@thread  EMT
Write handler for Interrupt Cause Read register . Bits corresponding to 1s in ' value ' will be cleared in ICR register . @param pThis The device state structure . @param offset Register offset in memory - mapped frame . @param index Register index in register array . @param value The value to store . @param mask Used to implement partial writes ( 8 and 16 - bit ) . @thread EMT
static int e1kRegWriteICR(PE1KSTATE pThis, uint32_t offset, uint32_t index, uint32_t value)
{
    ICR &= ~value;
    RT_NOREF_PV(pThis); RT_NOREF_PV(offset); RT_NOREF_PV(index);
    return VINF_SUCCESS;
}
static int e1kRegWriteICR ( PE1KSTATE pThis , uint32_t offset , uint32_t index , uint32_t value ) { ICR &= ~ value ; RT_NOREF_PV ( pThis ) ; RT_NOREF_PV ( offset ) ; RT_NOREF_PV ( index ) ; return VINF_SUCCESS ; }
Write handler for Interrupt Cause Read register.
Write handler for Interrupt Cause Read register .