src/dev/arm/ufs_device.cc
/**
 * UFSHCD read register. This function allows the system to read the
 * register entries
 */
UFSHCD read register. This function allows the system to read the
register entries
UFSHCD read register . This function allows the system to read the register entries
Tick
UFSHostDevice::read(PacketPtr pkt)
{
    uint32_t data = 0;
    switch (pkt->getAddr() & 0xFF)
    {
      case regControllerCapabilities:
        data = UFSHCIMem.HCCAP;
        break;
      case regUFSVersion:
        data = UFSHCIMem.HCversion;
        break;
      case regControllerDEVID:
        data = UFSHCIMem.HCHCDDID;
        break;
      case regControllerPRODID:
        data = UFSHCIMem.HCHCPMID;
        break;
      case regInterruptStatus:
        data = UFSHCIMem.ORInterruptStatus;
        UFSHCIMem.ORInterruptStatus = 0x00;
        clearInterrupt();
        break;
      case regInterruptEnable:
        data = UFSHCIMem.ORInterruptEnable;
        break;
      case regControllerStatus:
        data = UFSHCIMem.ORHostControllerStatus;
        break;
      case regControllerEnable:
        data = UFSHCIMem.ORHostControllerEnable;
        break;
      case regUICErrorCodePHYAdapterLayer:
        data = UFSHCIMem.ORUECPA;
        break;
      case regUICErrorCodeDataLinkLayer:
        data = UFSHCIMem.ORUECDL;
        break;
      case regUICErrorCodeNetworkLayer:
        data = UFSHCIMem.ORUECN;
        break;
      case regUICErrorCodeTransportLayer:
        data = UFSHCIMem.ORUECT;
        break;
      case regUICErrorCodeDME:
        data = UFSHCIMem.ORUECDME;
        break;
      case regUTPTransferREQINTAGGControl:
        data = UFSHCIMem.ORUTRIACR;
        break;
      case regUTPTransferREQListBaseL:
        data = UFSHCIMem.TRUTRLBA;
        break;
      case regUTPTransferREQListBaseH:
        data = UFSHCIMem.TRUTRLBAU;
        break;
      case regUTPTransferREQDoorbell:
        data = UFSHCIMem.TRUTRLDBR;
        break;
      case regUTPTransferREQListClear:
        data = UFSHCIMem.TRUTRLCLR;
        break;
      case regUTPTransferREQListRunStop:
        data = UFSHCIMem.TRUTRLRSR;
        break;
      case regUTPTaskREQListBaseL:
        data = UFSHCIMem.TMUTMRLBA;
        break;
      case regUTPTaskREQListBaseH:
        data = UFSHCIMem.TMUTMRLBAU;
        break;
      case regUTPTaskREQDoorbell:
        data = UFSHCIMem.TMUTMRLDBR;
        break;
      case regUTPTaskREQListClear:
        data = UFSHCIMem.TMUTMRLCLR;
        break;
      case regUTPTaskREQListRunStop:
        data = UFSHCIMem.TMUTMRLRSR;
        break;
      case regUICCommand:
        data = UFSHCIMem.CMDUICCMDR;
        break;
      case regUICCommandArg1:
        data = UFSHCIMem.CMDUCMDARG1;
        break;
      case regUICCommandArg2:
        data = UFSHCIMem.CMDUCMDARG2;
        break;
      case regUICCommandArg3:
        data = UFSHCIMem.CMDUCMDARG3;
        break;
      default:
        data = 0x00;
        break;
    }
    pkt->setLE<uint32_t>(data);
    pkt->makeResponse();
    return pioDelay;
}
Tick UFSHostDevice :: read ( PacketPtr pkt ) { uint32_t data = 0 ; switch ( pkt -> getAddr ( ) & 0xFF ) { case regControllerCapabilities : data = UFSHCIMem . HCCAP ; break ; case regUFSVersion : data = UFSHCIMem . HCversion ; break ; case regControllerDEVID : data = UFSHCIMem . HCHCDDID ; break ; case regControllerPRODID : data = UFSHCIMem . HCHCPMID ; break ; case regInterruptStatus : data = UFSHCIMem . ORInterruptStatus ; UFSHCIMem . ORInterruptStatus = 0x00 ; clearInterrupt ( ) ; break ; case regInterruptEnable : data = UFSHCIMem . ORInterruptEnable ; break ; case regControllerStatus : data = UFSHCIMem . ORHostControllerStatus ; break ; case regControllerEnable : data = UFSHCIMem . ORHostControllerEnable ; break ; case regUICErrorCodePHYAdapterLayer : data = UFSHCIMem . ORUECPA ; break ; case regUICErrorCodeDataLinkLayer : data = UFSHCIMem . ORUECDL ; break ; case regUICErrorCodeNetworkLayer : data = UFSHCIMem . ORUECN ; break ; case regUICErrorCodeTransportLayer : data = UFSHCIMem . ORUECT ; break ; case regUICErrorCodeDME : data = UFSHCIMem . ORUECDME ; break ; case regUTPTransferREQINTAGGControl : data = UFSHCIMem . ORUTRIACR ; break ; case regUTPTransferREQListBaseL : data = UFSHCIMem . TRUTRLBA ; break ; case regUTPTransferREQListBaseH : data = UFSHCIMem . TRUTRLBAU ; break ; case regUTPTransferREQDoorbell : data = UFSHCIMem . TRUTRLDBR ; break ; case regUTPTransferREQListClear : data = UFSHCIMem . TRUTRLCLR ; break ; case regUTPTransferREQListRunStop : data = UFSHCIMem . TRUTRLRSR ; break ; case regUTPTaskREQListBaseL : data = UFSHCIMem . TMUTMRLBA ; break ; case regUTPTaskREQListBaseH : data = UFSHCIMem . TMUTMRLBAU ; break ; case regUTPTaskREQDoorbell : data = UFSHCIMem . TMUTMRLDBR ; break ; case regUTPTaskREQListClear : data = UFSHCIMem . TMUTMRLCLR ; break ; case regUTPTaskREQListRunStop : data = UFSHCIMem . TMUTMRLRSR ; break ; case regUICCommand : data = UFSHCIMem . CMDUICCMDR ; break ; case regUICCommandArg1 : data = UFSHCIMem . CMDUCMDARG1 ; break ; case regUICCommandArg2 : data = UFSHCIMem . CMDUCMDARG2 ; break ; case regUICCommandArg3 : data = UFSHCIMem . CMDUCMDARG3 ; break ; default : data = 0x00 ; break ; } pkt -> setLE < uint32_t > ( data ) ; pkt -> makeResponse ( ) ; return pioDelay ; }
UFSHCD read register.
UFSHCD read register .
//TODO: Revise and extend