openfpga/src/fpga_spice/spice_subckt_writer.cpp
/********************************************************************
 * Print a SPICE wire connection 
 * We search all the sinks of the net, 
 * if we find a module output, we try to find the next module output 
 * among the sinks of the net
 * For each module output (except the first one), we print a wire connection 
 *******************************************************************/
Print a SPICE wire connection
We search all the sinks of the net,
if we find a module output, we try to find the next module output
among the sinks of the net
For each module output (except the first one), we print a wire connection
Print a SPICE wire connection We search all the sinks of the net if we find a module output we try to find the next module output among the sinks of the net For each module output ( except the first one ) we print a wire connection
static 
void print_spice_subckt_output_short_connection(std::fstream& fp, 
                                                const ModuleManager& module_manager,
                                                const ModuleId& module_id,
                                                const ModuleNetId& module_net) {
  VTR_ASSERT(true == valid_file_stream(fp));
  bool first_port = true;
  BasicPort src_port;
  for (ModuleNetSinkId net_sink : module_manager.module_net_sinks(module_id, module_net)) {
    ModuleId sink_module = module_manager.net_sink_modules(module_id, module_net)[net_sink];
    if (module_id != sink_module) {
      continue;
    }
    ModulePortId sink_port_id = module_manager.net_sink_ports(module_id, module_net)[net_sink];
    size_t sink_pin = module_manager.net_sink_pins(module_id, module_net)[net_sink];
    BasicPort sink_port(module_manager.module_port(module_id, sink_port_id).get_name(), sink_pin, sink_pin);
    if (true == first_port) {
      src_port = sink_port;
      first_port = false;
      continue;
    }
    VTR_ASSERT(src_port.get_width() == sink_port.get_width());
    for (size_t ipin = 0; ipin < src_port.pins().size(); ++ipin) {
      BasicPort src_spice_pin(src_port.get_name(), src_port.pins()[ipin], src_port.pins()[ipin]);
      BasicPort sink_spice_pin(sink_port.get_name(), sink_port.pins()[ipin], sink_port.pins()[ipin]);
      print_spice_short_connection(fp,
                                   generate_spice_port(src_spice_pin),
                                   generate_spice_port(sink_spice_pin));
    }
  }
}
static void print_spice_subckt_output_short_connection ( std :: fstream & fp , const ModuleManager & module_manager , const ModuleId & module_id , const ModuleNetId & module_net ) { VTR_ASSERT ( true == valid_file_stream ( fp ) ) ; bool first_port = true ; BasicPort src_port ; for ( ModuleNetSinkId net_sink : module_manager . module_net_sinks ( module_id , module_net ) ) { ModuleId sink_module = module_manager . net_sink_modules ( module_id , module_net ) [ net_sink ] ; if ( module_id != sink_module ) { continue ; } ModulePortId sink_port_id = module_manager . net_sink_ports ( module_id , module_net ) [ net_sink ] ; size_t sink_pin = module_manager . net_sink_pins ( module_id , module_net ) [ net_sink ] ; BasicPort sink_port ( module_manager . module_port ( module_id , sink_port_id ) . get_name ( ) , sink_pin , sink_pin ) ; if ( true == first_port ) { src_port = sink_port ; first_port = false ; continue ; } VTR_ASSERT ( src_port . get_width ( ) == sink_port . get_width ( ) ) ; for ( size_t ipin = 0 ; ipin < src_port . pins ( ) . size ( ) ; ++ ipin ) { BasicPort src_spice_pin ( src_port . get_name ( ) , src_port . pins ( ) [ ipin ] , src_port . pins ( ) [ ipin ] ) ; BasicPort sink_spice_pin ( sink_port . get_name ( ) , sink_port . pins ( ) [ ipin ] , sink_port . pins ( ) [ ipin ] ) ; print_spice_short_connection ( fp , generate_spice_port ( src_spice_pin ) , generate_spice_port ( sink_spice_pin ) ) ; } } }
Print a SPICE wire connection
 We search all the sinks of the net,
 if we find a module output, we try to find the next module output
 among the sinks of the net
 For each module output (except the first one), we print a wire connection
Print a SPICE wire connection We search all the sinks of the net if we find a module output we try to find the next module output among the sinks of the net For each module output ( except the first one ) we print a wire connection
/* Ensure a valid file stream */ /* We have found a module input, now check all the sink modules of the net */ /* Find the sink port and pin information */ /* For the first module output, this is the source port, we do nothing and go to the next */ /* Flip the flag */ /* We need to print a wire connection here */