openfpga/src/utils/mux_utils.cpp
/**************************************************
 * Build a location map for intermediate buffers
 * that may appear at the multiplexing structure of a LUT
 * Here is a tricky thing: 
 * By default, the first and last stage should not exist any intermediate buffers
 * For example: 
 * There are 5 stages in a 4-stage multiplexer is available for buffering
 * but only 3 stages [1,2,3] are intermedate buffers 
 * and these are users' specification
 *  
 *          +-------+          +-------+           +-------+           +-------+
 * location | stage | location | stage |  location | stage |  location | stage | location 
 *    [0]   |  [0]  |   [1]    |  [1]  |    [2]    |  [2]  |    [3]    |  [3]  |    [5]
 *          +-------+          +-------+           +-------+           +-------+
 *
 * We will check if the length of location map matches the number of
 * multiplexer levels. And then complete a location map
 * for the given multiplexers
 *************************************************/
Build a location map for intermediate buffers
that may appear at the multiplexing structure of a LUT
Here is a tricky thing:
By default, the first and last stage should not exist any intermediate buffers
For example:
There are 5 stages in a 4-stage multiplexer is available for buffering
but only 3 stages [1,2,3] are intermedate buffers
and these are users' specification



We will check if the length of location map matches the number of
multiplexer levels. And then complete a location map
for the given multiplexers
Build a location map for intermediate buffers that may appear at the multiplexing structure of a LUT Here is a tricky thing : By default the first and last stage should not exist any intermediate buffers For example : There are 5 stages in a 4 - stage multiplexer is available for buffering but only 3 stages [ 1 2 3 ] are intermedate buffers and these are users ' specification We will check if the length of location map matches the number of multiplexer levels . And then complete a location map for the given multiplexers
std::vector<bool> build_mux_intermediate_buffer_location_map(const CircuitLibrary& circuit_lib, 
                                                             const CircuitModelId& circuit_model,
                                                             const size_t& num_mux_levels) {
  std::vector<bool> location_map(num_mux_levels, false); 
  std::string location_map_str;
  if (CIRCUIT_MODEL_LUT != circuit_lib.model_type(circuit_model)) {
    return location_map;
  }
  if (true == circuit_lib.is_lut_intermediate_buffered(circuit_model)) { 
    location_map_str = circuit_lib.lut_intermediate_buffer_location_map(circuit_model);
  }
  if (location_map_str.empty()) {
    return location_map;
  }
  VTR_ASSERT(num_mux_levels - 2 == location_map_str.length());
  for (size_t i = 0; i < location_map_str.length(); ++i) {
    if ('1' == location_map_str[i]) {
      location_map[i + 1] = true;
    }
  }
  return location_map;
}
std :: vector < bool > build_mux_intermediate_buffer_location_map ( const CircuitLibrary & circuit_lib , const CircuitModelId & circuit_model , const size_t & num_mux_levels ) { std :: vector < bool > location_map ( num_mux_levels , false ) ; std :: string location_map_str ; if ( CIRCUIT_MODEL_LUT != circuit_lib . model_type ( circuit_model ) ) { return location_map ; } if ( true == circuit_lib . is_lut_intermediate_buffered ( circuit_model ) ) { location_map_str = circuit_lib . lut_intermediate_buffer_location_map ( circuit_model ) ; } if ( location_map_str . empty ( ) ) { return location_map ; } VTR_ASSERT ( num_mux_levels - 2 == location_map_str . length ( ) ) ; for ( size_t i = 0 ; i < location_map_str . length ( ) ; ++ i ) { if ( ' ' == location_map_str [ i ] ) { location_map [ i + 1 ] = true ; } } return location_map ; }
Build a location map for intermediate buffers
 that may appear at the multiplexing structure of a LUT
 Here is a tricky thing:
 By default, the first and last stage should not exist any intermediate buffers
 For example:
 There are 5 stages in a 4-stage multiplexer is available for buffering
 but only 3 stages [1,2,3] are intermedate buffers
 and these are users' specification
Build a location map for intermediate buffers that may appear at the multiplexing structure of a LUT Here is a tricky thing : By default the first and last stage should not exist any intermediate buffers For example : There are 5 stages in a 4 - stage multiplexer is available for buffering but only 3 stages [ 1 2 3 ] are intermedate buffers and these are users ' specification
/* Deposite a default location map */ /* ONLY for LUTs: intermediate buffers may exist if specified */ /* Get location map when the flag of intermediate buffer is on */ /* If no location map is specified, we can return here */ /* Check if the user-defined location map matches the number of mux levels*/ /* Apply the location_map string to the intermediate stages of multiplexers */ /* '1' indicates that an intermediate buffer is needed at the location */