src/CodeGen_CoreIR_Target.cpp
// This function is used when the output is going to be connected to a useable wire
This function is used when the output is going to be connected to a useable wire
This function is used when the output is going to be connected to a useable wire
CoreIR::Wireable* CodeGen_CoreIR_Target::CodeGen_CoreIR_C::get_wire(string name, Expr e, std::vector<uint> indices) {
  if (is_const(e)) {
    int const_value = id_const_value(e);
    string const_name = unique_name("const" + std::to_string(const_value) + "_" + name);
    CoreIR::Wireable* const_inst;
    uint const_bitwidth = get_const_bitwidth(e);
    if (const_bitwidth == 1) {
      const_inst = def->addInstance(const_name, gens["bitconst"], {{"value",CoreIR::Const::make(context,(bool)const_value)}});
    } else {
      int bw = inst_bitwidth(const_bitwidth);
      const_inst = def->addInstance(const_name, gens["const"], {{"width", CoreIR::Const::make(context,bw)}},
                                    {{"value",CoreIR::Const::make(context,BitVector(bw,const_value))}});
    }
    stream << "// created const: " << const_name << " with name " << name << "\n";
    return const_inst->sel("out");
  } else if (is_fconst(e)) {
    float fconst_value = id_fconst_value(e);
    string const_name = unique_name("fconst" + std::to_string((int)fconst_value) + "_" + name);
    CoreIR::Wireable* const_inst;
    uint const_bitwidth = get_const_bitwidth(e);
    int bw = inst_bitwidth(const_bitwidth);
    const_inst = def->addInstance(const_name, gens["fconst"], {{"width", CoreIR::Const::make(context,bw)}},
                                  {{"value",CoreIR::Const::make(context,BitVector(bw,bfloat16_t(fconst_value).to_bits()))}});
    const_inst->getMetaData()["float_value"] = "Equivalent float = " + std::to_string(fconst_value);
    stream << "// created fconst: " << const_name << " with name " << name << " with float value " << fconst_value << "\n";
    return const_inst->sel("out");
  } else if (is_input(name)) {
    CoreIR::Wireable* input_wire = hw_input_set[name];
    stream << "// " << name << " added as input " << name << endl;
    auto current_wire = index_wire(input_wire, indices);
    return current_wire;
  } else if (is_storage(name)) {
    auto pt_struct = hw_store_set[name];
    CoreIR::Wireable* current_wire;
    if (!pt_struct->was_written) {
      internal_assert(pt_struct->is_reg());
      current_wire = pt_struct->reg->sel("out");
    } else {
      current_wire = pt_struct->wire->sel("out");
    }
    current_wire = index_wire(current_wire, indices);
    pt_struct->was_read = true;
    return current_wire;
  } else if (is_wire(name)) {
    CoreIR::Wireable* wire = hw_wire_set[name];
    if (wire==NULL) {
      user_warning << "wire was not defined: " << name << "\n";
      stream       << "// wire was not defined: " << name << endl;
      return self->sel("in");
    }
    CoreIR::Wireable* current_wire = index_wire(wire, indices);
    return current_wire;
  } else if (is_defined(name)) {
    std::shared_ptr<CoreIR_Inst_Args> inst_args = hw_def_set[name];
    assert(inst_args);
    stream << "// creating element called: " << name << endl;
    string inst_name = unique_name(inst_args->name);
    CoreIR::Wireable* inst = def->addInstance(inst_name, inst_args->gen, inst_args->args, inst_args->genargs);
    add_wire(name, inst->sel(inst_args->selname));
    if (inst_args->gen == gens["ram2"]) {
      add_wire(name + "_waddr", inst->sel("waddr"));
      add_wire(name + "_wdata", inst->sel("wdata"));
      add_wire(name + "_raddr", inst->sel("raddr"));
      CoreIR::Wireable* rom_ren = def->addInstance(inst_name + "_ren", gens["bitconst"], {{"value", CoreIR::Const::make(context,true)}});
      def->connect(rom_ren->sel("out"), inst->sel("ren"));
      auto ram_wen = def->addInstance(name + "_wen", gens["bitconst"], {{"value",CoreIR::Const::make(context,false)}});
      def->connect(ram_wen->sel("out"), inst->sel("wen"));
    }
    auto ref_name = inst_args->ref_name;
    return inst->sel(inst_args->selname);
  } else {
    user_warning << "ERROR- invalid wire: " << name << "\n";
    stream << "// invalid wire: couldn't find " << name
           << "\n// hw_wire_set contains: ";
    for (auto x : hw_wire_set) {
      stream << " " << x.first;
    }
    stream << "\n";
    return self->sel("in");
  }
}
CoreIR :: Wireable * CodeGen_CoreIR_Target :: CodeGen_CoreIR_C :: get_wire ( string name , Expr e , std :: vector < uint > indices ) { if ( is_const ( e ) ) { int const_value = id_const_value ( e ) ; string const_name = unique_name ( " " + std :: to_string ( const_value ) + " " + name ) ; CoreIR :: Wireable * const_inst ; uint const_bitwidth = get_const_bitwidth ( e ) ; if ( const_bitwidth == 1 ) { const_inst = def -> addInstance ( const_name , gens [ " " ] , { { " " , CoreIR :: Const :: make ( context , ( bool ) const_value ) } } ) ; } else { int bw = inst_bitwidth ( const_bitwidth ) ; const_inst = def -> addInstance ( const_name , gens [ " " ] , { { " " , CoreIR :: Const :: make ( context , bw ) } } , { { " " , CoreIR :: Const :: make ( context , BitVector ( bw , const_value ) ) } } ) ; } stream << " " << const_name << " " << name << " \n " ; return const_inst -> sel ( " " ) ; } else if ( is_fconst ( e ) ) { float fconst_value = id_fconst_value ( e ) ; string const_name = unique_name ( " " + std :: to_string ( ( int ) fconst_value ) + " " + name ) ; CoreIR :: Wireable * const_inst ; uint const_bitwidth = get_const_bitwidth ( e ) ; int bw = inst_bitwidth ( const_bitwidth ) ; const_inst = def -> addInstance ( const_name , gens [ " " ] , { { " " , CoreIR :: Const :: make ( context , bw ) } } , { { " " , CoreIR :: Const :: make ( context , BitVector ( bw , bfloat16_t ( fconst_value ) . to_bits ( ) ) ) } } ) ; const_inst -> getMetaData ( ) [ " " ] = " " + std :: to_string ( fconst_value ) ; stream << " " << const_name << " " << name << " " << fconst_value << " \n " ; return const_inst -> sel ( " " ) ; } else if ( is_input ( name ) ) { CoreIR :: Wireable * input_wire = hw_input_set [ name ] ; stream << " " << name << " " << name << endl ; auto current_wire = index_wire ( input_wire , indices ) ; return current_wire ; } else if ( is_storage ( name ) ) { auto pt_struct = hw_store_set [ name ] ; CoreIR :: Wireable * current_wire ; if ( ! pt_struct -> was_written ) { internal_assert ( pt_struct -> is_reg ( ) ) ; current_wire = pt_struct -> reg -> sel ( " " ) ; } else { current_wire = pt_struct -> wire -> sel ( " " ) ; } current_wire = index_wire ( current_wire , indices ) ; pt_struct -> was_read = true ; return current_wire ; } else if ( is_wire ( name ) ) { CoreIR :: Wireable * wire = hw_wire_set [ name ] ; if ( wire == NULL ) { user_warning << " " << name << " \n " ; stream << " " << name << endl ; return self -> sel ( " " ) ; } CoreIR :: Wireable * current_wire = index_wire ( wire , indices ) ; return current_wire ; } else if ( is_defined ( name ) ) { std :: shared_ptr < CoreIR_Inst_Args > inst_args = hw_def_set [ name ] ; assert ( inst_args ) ; stream << " " << name << endl ; string inst_name = unique_name ( inst_args -> name ) ; CoreIR :: Wireable * inst = def -> addInstance ( inst_name , inst_args -> gen , inst_args -> args , inst_args -> genargs ) ; add_wire ( name , inst -> sel ( inst_args -> selname ) ) ; if ( inst_args -> gen == gens [ " " ] ) { add_wire ( name + " " , inst -> sel ( " " ) ) ; add_wire ( name + " " , inst -> sel ( " " ) ) ; add_wire ( name + " " , inst -> sel ( " " ) ) ; CoreIR :: Wireable * rom_ren = def -> addInstance ( inst_name + " " , gens [ " " ] , { { " " , CoreIR :: Const :: make ( context , true ) } } ) ; def -> connect ( rom_ren -> sel ( " " ) , inst -> sel ( " " ) ) ; auto ram_wen = def -> addInstance ( name + " " , gens [ " " ] , { { " " , CoreIR :: Const :: make ( context , false ) } } ) ; def -> connect ( ram_wen -> sel ( " " ) , inst -> sel ( " " ) ) ; } auto ref_name = inst_args -> ref_name ; return inst -> sel ( inst_args -> selname ) ; } else { user_warning << " " << name << " \n " ; stream << " " << name << " \n " ; for ( auto x : hw_wire_set ) { stream << " " << x . first ; } stream << " \n " ; return self -> sel ( " " ) ; } }
This function is used when the output is going to be connected to a useable wire
This function is used when the output is going to be connected to a useable wire
//cout << "connect for " << name << "\n"; // Create a constant. // Create a constant with floating point value // Return an input wire // Return a reusable element // Return an existing module wire. // hardware element defined, but not added yet //cout << "named " << inst_args->gen <<endl; //attach a read enable