libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
/************************************************************************
 * Check io has been defined and has input and output ports 
 * - We must have global I/O port, either its type is inout, input or output
 * - For each IOPAD, we must have at least an input an output 
 ***********************************************************************/
Check io has been defined and has input and output ports
- We must have global I/O port, either its type is inout, input or output
- For each IOPAD, we must have at least an input an output
Check io has been defined and has input and output ports - We must have global I / O port either its type is inout input or output - For each IOPAD we must have at least an input an output
static 
size_t check_io_circuit_model(const CircuitLibrary& circuit_lib) {
  size_t num_err = 0;
  for (const auto& io_model : circuit_lib.models_by_type(CIRCUIT_MODEL_IOPAD)) {
    bool has_data_io = false;
    bool has_data_input_only_io = false;
    bool has_data_output_only_io = false;
    bool has_internal_connection = false;
    for (const auto& port : circuit_lib.model_ports(io_model)) {
      if ( (true == circuit_lib.port_is_io(port))
        && (true == circuit_lib.port_is_data_io(port))
        && (CIRCUIT_MODEL_PORT_INOUT == circuit_lib.port_type(port))
        && (true == circuit_lib.port_is_global(port))) {
        has_data_io = true;
        continue; 
      }
      if ( (true == circuit_lib.port_is_io(port))
        && (true == circuit_lib.port_is_data_io(port))
        && (CIRCUIT_MODEL_PORT_INPUT == circuit_lib.port_type(port))
        && (true == circuit_lib.port_is_global(port))) {
        has_data_input_only_io = true;
        continue; 
      }
      if ( (true == circuit_lib.port_is_io(port))
        && (true == circuit_lib.port_is_data_io(port))
        && (CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib.port_type(port))
        && (true == circuit_lib.port_is_global(port))) {
        has_data_output_only_io = true;
        continue; 
      }
      if ( (false == circuit_lib.port_is_io(port)
        && (false == circuit_lib.port_is_global(port)))
        && (CIRCUIT_MODEL_PORT_SRAM != circuit_lib.port_type(port))) {
        has_internal_connection = true;
        continue; 
      }
    }
    if ( (false == has_data_io) 
      && (false == has_data_input_only_io) 
      && (false == has_data_output_only_io)) {
      VTR_LOGF_ERROR(__FILE__, __LINE__,
                     "I/O circuit model '%s' does not have any data I/O port defined!\n",
                     circuit_lib.model_name(io_model).c_str()); 
      num_err++;
    }
    if (false == has_internal_connection) {
      VTR_LOGF_ERROR(__FILE__, __LINE__,
                     "I/O circuit model '%s' does not have any port connected to FPGA core!\n",
                     circuit_lib.model_name(io_model).c_str()); 
      num_err++;
    }
  }
  return num_err;
}
static size_t check_io_circuit_model ( const CircuitLibrary & circuit_lib ) { size_t num_err = 0 ; for ( const auto & io_model : circuit_lib . models_by_type ( CIRCUIT_MODEL_IOPAD ) ) { bool has_data_io = false ; bool has_data_input_only_io = false ; bool has_data_output_only_io = false ; bool has_internal_connection = false ; for ( const auto & port : circuit_lib . model_ports ( io_model ) ) { if ( ( true == circuit_lib . port_is_io ( port ) ) && ( true == circuit_lib . port_is_data_io ( port ) ) && ( CIRCUIT_MODEL_PORT_INOUT == circuit_lib . port_type ( port ) ) && ( true == circuit_lib . port_is_global ( port ) ) ) { has_data_io = true ; continue ; } if ( ( true == circuit_lib . port_is_io ( port ) ) && ( true == circuit_lib . port_is_data_io ( port ) ) && ( CIRCUIT_MODEL_PORT_INPUT == circuit_lib . port_type ( port ) ) && ( true == circuit_lib . port_is_global ( port ) ) ) { has_data_input_only_io = true ; continue ; } if ( ( true == circuit_lib . port_is_io ( port ) ) && ( true == circuit_lib . port_is_data_io ( port ) ) && ( CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib . port_type ( port ) ) && ( true == circuit_lib . port_is_global ( port ) ) ) { has_data_output_only_io = true ; continue ; } if ( ( false == circuit_lib . port_is_io ( port ) && ( false == circuit_lib . port_is_global ( port ) ) ) && ( CIRCUIT_MODEL_PORT_SRAM != circuit_lib . port_type ( port ) ) ) { has_internal_connection = true ; continue ; } } if ( ( false == has_data_io ) && ( false == has_data_input_only_io ) && ( false == has_data_output_only_io ) ) { VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " , circuit_lib . model_name ( io_model ) . c_str ( ) ) ; num_err ++ ; } if ( false == has_internal_connection ) { VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " , circuit_lib . model_name ( io_model ) . c_str ( ) ) ; num_err ++ ; } } return num_err ; }
Check io has been defined and has input and output ports
 - We must have global I/O port, either its type is inout, input or output
 - For each IOPAD, we must have at least an input an output
Check io has been defined and has input and output ports - We must have global I / O port either its type is inout input or output - For each IOPAD we must have at least an input an output
/* Each I/O cell must have 
   *  - One of the following ports
   *    - At least 1 ASIC-to-FPGA (A2F) port that is defined as global data I/O 
   *    - At least 1 FPGA-to-ASIC (F2A) port that is defined as global data I/O!
   *  - At least 1 regular port that is non-global which is connected to global routing architecture
   */ /* Go to next */ /* Go to next */ /* Go to next */ /* Go to next */ /* Error out when
     *   - there is no data io, data input-only io and data output-only io
     */