openfpga/src/annotation/check_pb_type_annotation.cpp
/********************************************************************
 * This function will recursively traverse only the physical mode
 * and physical pb_types in the graph to ensure
 *  - Every physical pb_type should be linked to a valid circuit model
 *  - Every port of the pb_type have been linked to a valid port of a circuit model
 *  - Every interconnect has been linked to a valid circuit model
 *    in a correct type
 *******************************************************************/
This function will recursively traverse only the physical mode
and physical pb_types in the graph to ensure
- Every physical pb_type should be linked to a valid circuit model
- Every port of the pb_type have been linked to a valid port of a circuit model
- Every interconnect has been linked to a valid circuit model
in a correct type
This function will recursively traverse only the physical mode and physical pb_types in the graph to ensure - Every physical pb_type should be linked to a valid circuit model - Every port of the pb_type have been linked to a valid port of a circuit model - Every interconnect has been linked to a valid circuit model in a correct type
static 
void rec_check_vpr_pb_type_circuit_model_annotation(t_pb_type* cur_pb_type,
                                                    const CircuitLibrary& circuit_lib,
                                                    const VprDeviceAnnotation& vpr_device_annotation,
                                                    size_t& num_err) {
  if (true == is_primitive_pb_type(cur_pb_type)) {
    if (CircuitModelId::INVALID() == vpr_device_annotation.pb_type_circuit_model(cur_pb_type)) {
      VTR_LOG_ERROR("Found a physical pb_type '%s' missing circuit model binding!\n",
                    generate_pb_type_hierarchy_path(cur_pb_type).c_str());
      num_err++;
      return; 
    }
    for (t_port* port : pb_type_ports(cur_pb_type)) {
      if (CircuitPortId::INVALID() == vpr_device_annotation.pb_circuit_port(port)) {
        VTR_LOG_ERROR("Found a port '%s' of physical pb_type '%s' missing circuit port binding!\n",
                      port->name,
                      generate_pb_type_hierarchy_path(cur_pb_type).c_str());
        num_err++;
      }
    }
    return;
  }
  t_mode* physical_mode = vpr_device_annotation.physical_mode(cur_pb_type);
  for (t_interconnect* interc : pb_mode_interconnects(physical_mode)) {
    CircuitModelId interc_circuit_model = vpr_device_annotation.interconnect_circuit_model(interc);
    if (CircuitModelId::INVALID() == interc_circuit_model) {
      VTR_LOG_ERROR("Found an interconnect '%s' under physical mode '%s' of pb_type '%s' missing circuit model binding!\n",
                    interc->name,
                    physical_mode->name,
                    generate_pb_type_hierarchy_path(cur_pb_type).c_str());
      num_err++;
      continue;
    }
    e_circuit_model_type required_circuit_model_type = pb_interconnect_require_circuit_model_type(vpr_device_annotation.interconnect_physical_type(interc));
    if (circuit_lib.model_type(interc_circuit_model) != required_circuit_model_type) {
      VTR_LOG_ERROR("Found an interconnect '%s' under physical mode '%s' of pb_type '%s' linked to a circuit model '%s' with a wrong type!\nExpect: '%s' Linked: '%s'\n",
                    interc->name,
                    physical_mode->name, 
                    generate_pb_type_hierarchy_path(cur_pb_type).c_str(),
                    circuit_lib.model_name(interc_circuit_model).c_str(),
                    CIRCUIT_MODEL_TYPE_STRING[circuit_lib.model_type(interc_circuit_model)],
                    CIRCUIT_MODEL_TYPE_STRING[required_circuit_model_type]);
      num_err++;
    }
  } 
  for (int ichild = 0; ichild < physical_mode->num_pb_type_children; ++ichild) { 
    rec_check_vpr_pb_type_circuit_model_annotation(&(physical_mode->pb_type_children[ichild]),
                                                   circuit_lib,
                                                   vpr_device_annotation,
                                                   num_err);
  }
}
static void rec_check_vpr_pb_type_circuit_model_annotation ( t_pb_type * cur_pb_type , const CircuitLibrary & circuit_lib , const VprDeviceAnnotation & vpr_device_annotation , size_t & num_err ) { if ( true == is_primitive_pb_type ( cur_pb_type ) ) { if ( CircuitModelId :: INVALID ( ) == vpr_device_annotation . pb_type_circuit_model ( cur_pb_type ) ) { VTR_LOG_ERROR ( " \n " , generate_pb_type_hierarchy_path ( cur_pb_type ) . c_str ( ) ) ; num_err ++ ; return ; } for ( t_port * port : pb_type_ports ( cur_pb_type ) ) { if ( CircuitPortId :: INVALID ( ) == vpr_device_annotation . pb_circuit_port ( port ) ) { VTR_LOG_ERROR ( " \n " , port -> name , generate_pb_type_hierarchy_path ( cur_pb_type ) . c_str ( ) ) ; num_err ++ ; } } return ; } t_mode * physical_mode = vpr_device_annotation . physical_mode ( cur_pb_type ) ; for ( t_interconnect * interc : pb_mode_interconnects ( physical_mode ) ) { CircuitModelId interc_circuit_model = vpr_device_annotation . interconnect_circuit_model ( interc ) ; if ( CircuitModelId :: INVALID ( ) == interc_circuit_model ) { VTR_LOG_ERROR ( " \n " , interc -> name , physical_mode -> name , generate_pb_type_hierarchy_path ( cur_pb_type ) . c_str ( ) ) ; num_err ++ ; continue ; } e_circuit_model_type required_circuit_model_type = pb_interconnect_require_circuit_model_type ( vpr_device_annotation . interconnect_physical_type ( interc ) ) ; if ( circuit_lib . model_type ( interc_circuit_model ) != required_circuit_model_type ) { VTR_LOG_ERROR ( " \n \n " , interc -> name , physical_mode -> name , generate_pb_type_hierarchy_path ( cur_pb_type ) . c_str ( ) , circuit_lib . model_name ( interc_circuit_model ) . c_str ( ) , CIRCUIT_MODEL_TYPE_STRING [ circuit_lib . model_type ( interc_circuit_model ) ] , CIRCUIT_MODEL_TYPE_STRING [ required_circuit_model_type ] ) ; num_err ++ ; } } for ( int ichild = 0 ; ichild < physical_mode -> num_pb_type_children ; ++ ichild ) { rec_check_vpr_pb_type_circuit_model_annotation ( & ( physical_mode -> pb_type_children [ ichild ] ) , circuit_lib , vpr_device_annotation , num_err ) ; } }
This function will recursively traverse only the physical mode
 and physical pb_types in the graph to ensure
  - Every physical pb_type should be linked to a valid circuit model
  - Every port of the pb_type have been linked to a valid port of a circuit model
  - Every interconnect has been linked to a valid circuit model
    in a correct type
This function will recursively traverse only the physical mode and physical pb_types in the graph to ensure - Every physical pb_type should be linked to a valid circuit model - Every port of the pb_type have been linked to a valid port of a circuit model - Every interconnect has been linked to a valid circuit model in a correct type
/* Primitive pb_type should always been binded to a physical pb_type */ /* Every physical pb_type should be linked to a valid circuit model */ /* Invalid id already, further check is not applicable */ /* Every port of the pb_type have been linked to a valid port of a circuit model */ /* Every interconnect in the physical mode has been linked to a valid circuit model in a correct type */ /* Traverse only the physical mode */