openfpga/src/fpga_spice/spice_mux.cpp
/***********************************************
 * Generate SPICE modeling for a multiplexer 
 * with the given graph-level description
 **********************************************/
Generate SPICE modeling for a multiplexer
with the given graph-level description
Generate SPICE modeling for a multiplexer with the given graph - level description
static 
void generate_spice_mux_subckt(const ModuleManager& module_manager,
                               const CircuitLibrary& circuit_lib, 
                               std::fstream& fp, 
                               const CircuitModelId& mux_model, 
                               const MuxGraph& mux_graph) {
  std::string module_name = generate_mux_subckt_name(circuit_lib, mux_model, 
                                                     find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()), 
                                                     std::string(""));
  switch (circuit_lib.design_tech_type(mux_model)) {
  case CIRCUIT_MODEL_DESIGN_CMOS: {
    ModuleId mux_module = module_manager.find_module(module_name);
    VTR_ASSERT(true == module_manager.valid_module_id(mux_module));
    write_spice_subckt_to_file(fp, module_manager, mux_module);
    fp << std::endl;
    break;
  }
  case CIRCUIT_MODEL_DESIGN_RRAM:
    VTR_LOGF_ERROR(__FILE__, __LINE__,
                   "RRAM multiplexer '%s' is not supported yet\n",
                   circuit_lib.model_name(mux_model).c_str()); 
    exit(1);
    break;
  default:
    VTR_LOGF_ERROR(__FILE__, __LINE__,
                   "Invalid design technology of multiplexer '%s'\n",
                   circuit_lib.model_name(mux_model).c_str()); 
    exit(1);
  }
}
static void generate_spice_mux_subckt ( const ModuleManager & module_manager , const CircuitLibrary & circuit_lib , std :: fstream & fp , const CircuitModelId & mux_model , const MuxGraph & mux_graph ) { std :: string module_name = generate_mux_subckt_name ( circuit_lib , mux_model , find_mux_num_datapath_inputs ( circuit_lib , mux_model , mux_graph . num_inputs ( ) ) , std :: string ( " " ) ) ; switch ( circuit_lib . design_tech_type ( mux_model ) ) { case CIRCUIT_MODEL_DESIGN_CMOS : { ModuleId mux_module = module_manager . find_module ( module_name ) ; VTR_ASSERT ( true == module_manager . valid_module_id ( mux_module ) ) ; write_spice_subckt_to_file ( fp , module_manager , mux_module ) ; fp << std :: endl ; break ; } case CIRCUIT_MODEL_DESIGN_RRAM : VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " , circuit_lib . model_name ( mux_model ) . c_str ( ) ) ; exit ( 1 ) ; break ; default : VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " , circuit_lib . model_name ( mux_model ) . c_str ( ) ) ; exit ( 1 ) ; } }
Generate SPICE modeling for a multiplexer
 with the given graph-level description
Generate SPICE modeling for a multiplexer with the given graph - level description
/* Multiplexers built with different technology is in different organization */ /* Use Verilog writer to print the module to file */ /* Add an empty line as a splitter */ /* TODO: RRAM-based Multiplexer SPICE module generation */