libopenfpga/libarchopenfpga/src/read_xml_tile_annotation.cpp
/********************************************************************
 * Parse XML description for an interconnection annotation 
 * under a <global_port> XML node
 *******************************************************************/
Parse XML description for an interconnection annotation
under a  XML node
Parse XML description for an interconnection annotation under a XML node
static 
void read_xml_tile_global_port_annotation(pugi::xml_node& xml_tile,
                                          const pugiutil::loc_data& loc_data,
                                          openfpga::TileAnnotation& tile_annotation) {
  const std::string& name_attr = get_attribute(xml_tile, "name", loc_data).as_string();
  TileGlobalPortId tile_global_port_id = tile_annotation.create_global_port(name_attr);
  if (TileGlobalPortId::INVALID() == tile_global_port_id) {
    archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_tile),
                   "Invalid port name '%s' which is defined more than once in the global port list!\n",
                   name_attr.c_str());
  }
  for (pugi::xml_node xml_tile_port : xml_tile.children()) {
    if (xml_tile_port.name() != std::string("tile")) {
      bad_tag(xml_tile_port, loc_data, xml_tile, {"tile"});
    }
    const std::string& tile_name_attr = get_attribute(xml_tile_port, "name", loc_data).as_string();
    const std::string& port_name_attr = get_attribute(xml_tile_port, "port", loc_data).as_string();
    openfpga::PortParser tile_port_parser(port_name_attr);
    vtr::Point<size_t> tile_coord(get_attribute(xml_tile_port, "x", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(-1), 
                                  get_attribute(xml_tile_port, "y", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(-1));
    tile_annotation.add_global_port_tile_information(tile_global_port_id,
                                                     tile_name_attr, 
                                                     tile_port_parser.port(),
                                                     tile_coord);
  } 
  if (true == tile_annotation.global_port_tile_names(tile_global_port_id).empty()) {
    archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_tile),
                   "Invalid tile annotation for global port '%s'! At least 1 tile port definition is expected!\n",
                   name_attr.c_str());
  }
  tile_annotation.set_global_port_is_clock(tile_global_port_id, get_attribute(xml_tile, "is_clock", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
  tile_annotation.set_global_port_is_set(tile_global_port_id, get_attribute(xml_tile, "is_set", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
  tile_annotation.set_global_port_is_reset(tile_global_port_id, get_attribute(xml_tile, "is_reset", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
  tile_annotation.set_global_port_default_value(tile_global_port_id, get_attribute(xml_tile, "default_val", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(0));
  if (false == tile_annotation.valid_global_port_attributes(tile_global_port_id)) {
    archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_tile),
                   "Invalid port attributes for '%s'! A port can only be clock or set or reset.\n",
                   name_attr.c_str());
  }
}
static void read_xml_tile_global_port_annotation ( pugi :: xml_node & xml_tile , const pugiutil :: loc_data & loc_data , openfpga :: TileAnnotation & tile_annotation ) { const std :: string & name_attr = get_attribute ( xml_tile , " " , loc_data ) . as_string ( ) ; TileGlobalPortId tile_global_port_id = tile_annotation . create_global_port ( name_attr ) ; if ( TileGlobalPortId :: INVALID ( ) == tile_global_port_id ) { archfpga_throw ( loc_data . filename_c_str ( ) , loc_data . line ( xml_tile ) , " \n " , name_attr . c_str ( ) ) ; } for ( pugi :: xml_node xml_tile_port : xml_tile . children ( ) ) { if ( xml_tile_port . name ( ) != std :: string ( " " ) ) { bad_tag ( xml_tile_port , loc_data , xml_tile , { " " } ) ; } const std :: string & tile_name_attr = get_attribute ( xml_tile_port , " " , loc_data ) . as_string ( ) ; const std :: string & port_name_attr = get_attribute ( xml_tile_port , " " , loc_data ) . as_string ( ) ; openfpga :: PortParser tile_port_parser ( port_name_attr ) ; vtr :: Point < size_t > tile_coord ( get_attribute ( xml_tile_port , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) . as_int ( -1 ) , get_attribute ( xml_tile_port , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) . as_int ( -1 ) ) ; tile_annotation . add_global_port_tile_information ( tile_global_port_id , tile_name_attr , tile_port_parser . port ( ) , tile_coord ) ; } if ( true == tile_annotation . global_port_tile_names ( tile_global_port_id ) . empty ( ) ) { archfpga_throw ( loc_data . filename_c_str ( ) , loc_data . line ( xml_tile ) , " \n " , name_attr . c_str ( ) ) ; } tile_annotation . set_global_port_is_clock ( tile_global_port_id , get_attribute ( xml_tile , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) . as_bool ( false ) ) ; tile_annotation . set_global_port_is_set ( tile_global_port_id , get_attribute ( xml_tile , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) . as_bool ( false ) ) ; tile_annotation . set_global_port_is_reset ( tile_global_port_id , get_attribute ( xml_tile , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) . as_bool ( false ) ) ; tile_annotation . set_global_port_default_value ( tile_global_port_id , get_attribute ( xml_tile , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) . as_int ( 0 ) ) ; if ( false == tile_annotation . valid_global_port_attributes ( tile_global_port_id ) ) { archfpga_throw ( loc_data . filename_c_str ( ) , loc_data . line ( xml_tile ) , " \n " , name_attr . c_str ( ) ) ; } }
Parse XML description for an interconnection annotation
 under a <global_port> XML node
Parse XML description for an interconnection annotation under a <global_port > XML node
/* We have mandatory XML attributes: 
   * - name of the port 
   */ /* Report any duplicated port names */ /* Iterate over the children under this node,
   * each child should be named after <pb_type>
   */ /* Error out if the XML child has an invalid name! */ /* Parse the name of the tiles and ports */ /* Extract the tile port information */ /* Parse tile coordinates */ /* Add tile port information */ /* Check: Must have at least one global port tile information */ /* Get is_clock attributes */ /* Get is_set attributes */ /* Get is_reset attributes */ /* Get default_value attributes */ /* Ensure valid port attributes */