openfpga/src/fpga_spice/spice_mux.cpp
/***********************************************
 * Generate SPICE modeling for an branch circuit 
 * for a multiplexer with the given size 
 **********************************************/
Generate SPICE modeling for an branch circuit
for a multiplexer with the given size
Generate SPICE modeling for an branch circuit for a multiplexer with the given size
static 
void generate_spice_mux_branch_subckt(const ModuleManager& module_manager,
                                      const CircuitLibrary& circuit_lib, 
                                      std::fstream& fp, 
                                      const CircuitModelId& mux_model, 
                                      const MuxGraph& mux_graph,
                                      std::map<std::string, bool>& branch_mux_module_is_outputted) {
  std::string module_name = generate_mux_branch_subckt_name(circuit_lib, mux_model, mux_graph.num_inputs(), mux_graph.num_memory_bits(), SPICE_MUX_BASIS_POSTFIX);
  auto result = branch_mux_module_is_outputted.find(module_name);
  if ((result != branch_mux_module_is_outputted.end())
    && (true == result->second)) {
    return;
  }
  switch (circuit_lib.design_tech_type(mux_model)) {
  case CIRCUIT_MODEL_DESIGN_CMOS: {
    if (true == circuit_lib.valid_model_id(circuit_lib.model(module_name))) {
      VTR_ASSERT(CIRCUIT_MODEL_GATE == circuit_lib.model_type(circuit_lib.model(module_name)));
      VTR_ASSERT(CIRCUIT_MODEL_GATE_MUX2 == circuit_lib.gate_type(circuit_lib.model(module_name)));
      break;
    }
    ModuleId mux_module = module_manager.find_module(module_name);
    VTR_ASSERT(true == module_manager.valid_module_id(mux_module));
    write_spice_subckt_to_file(fp, module_manager, mux_module);
    fp << std::endl;
    break;
  }
  case CIRCUIT_MODEL_DESIGN_RRAM:
    VTR_LOGF_ERROR(__FILE__, __LINE__,
                   "RRAM multiplexer '%s' is not supported yet\n",
                   circuit_lib.model_name(mux_model).c_str()); 
    exit(1);
    break;
  default:
    VTR_LOGF_ERROR(__FILE__, __LINE__,
                   "Invalid design technology of multiplexer '%s'\n",
                   circuit_lib.model_name(mux_model).c_str()); 
    exit(1);
  }
  branch_mux_module_is_outputted[module_name] = true;
}
static void generate_spice_mux_branch_subckt ( const ModuleManager & module_manager , const CircuitLibrary & circuit_lib , std :: fstream & fp , const CircuitModelId & mux_model , const MuxGraph & mux_graph , std :: map < std :: string , bool > & branch_mux_module_is_outputted ) { std :: string module_name = generate_mux_branch_subckt_name ( circuit_lib , mux_model , mux_graph . num_inputs ( ) , mux_graph . num_memory_bits ( ) , SPICE_MUX_BASIS_POSTFIX ) ; auto result = branch_mux_module_is_outputted . find ( module_name ) ; if ( ( result != branch_mux_module_is_outputted . end ( ) ) && ( true == result -> second ) ) { return ; } switch ( circuit_lib . design_tech_type ( mux_model ) ) { case CIRCUIT_MODEL_DESIGN_CMOS : { if ( true == circuit_lib . valid_model_id ( circuit_lib . model ( module_name ) ) ) { VTR_ASSERT ( CIRCUIT_MODEL_GATE == circuit_lib . model_type ( circuit_lib . model ( module_name ) ) ) ; VTR_ASSERT ( CIRCUIT_MODEL_GATE_MUX2 == circuit_lib . gate_type ( circuit_lib . model ( module_name ) ) ) ; break ; } ModuleId mux_module = module_manager . find_module ( module_name ) ; VTR_ASSERT ( true == module_manager . valid_module_id ( mux_module ) ) ; write_spice_subckt_to_file ( fp , module_manager , mux_module ) ; fp << std :: endl ; break ; } case CIRCUIT_MODEL_DESIGN_RRAM : VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " , circuit_lib . model_name ( mux_model ) . c_str ( ) ) ; exit ( 1 ) ; break ; default : VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " , circuit_lib . model_name ( mux_model ) . c_str ( ) ) ; exit ( 1 ) ; } branch_mux_module_is_outputted [ module_name ] = true ; }
Generate SPICE modeling for an branch circuit
 for a multiplexer with the given size
Generate SPICE modeling for an branch circuit for a multiplexer with the given size
/* Skip outputting if the module has already been outputted */ /* Multiplexers built with different technology is in different organization */ /* Skip module writing if the branch subckt is a standard cell! */ /* This model must be a MUX2 gate */ /* Structural verilog can be easily generated by module writer */ /* Add an empty line as a splitter */ /* TODO: RRAM-based Multiplexer SPICE module generation */ /* Record that this branch module has been outputted */