vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp
/************************************************************************
 * Build the edges of each rr_node tile by tile:
 * We classify rr_nodes into a general switch block (GSB) data structure
 * where we create edges to each rr_nodes in the GSB with respect to
 * Fc_in and Fc_out, switch block patterns 
 * For each GSB: 
 * 1. create edges between CHANX | CHANY and IPINs (connections inside connection blocks)
 * 2. create edges between OPINs, CHANX and CHANY (connections inside switch blocks)
 * 3. create edges between OPINs and IPINs (direct-connections)
 ***********************************************************************/
Build the edges of each rr_node tile by tile:
We classify rr_nodes into a general switch block (GSB) data structure
where we create edges to each rr_nodes in the GSB with respect to
Fc_in and Fc_out, switch block patterns
For each GSB:
1. create edges between CHANX | CHANY and IPINs (connections inside connection blocks)
2. create edges between OPINs, CHANX and CHANY (connections inside switch blocks)
3. create edges between OPINs and IPINs (direct-connections)
Build the edges of each rr_node tile by tile : We classify rr_nodes into a general switch block ( GSB ) data structure where we create edges to each rr_nodes in the GSB with respect to Fc_in and Fc_out switch block patterns For each GSB : 1 . create edges between CHANX | CHANY and IPINs ( connections inside connection blocks ) 2 . create edges between OPINs CHANX and CHANY ( connections inside switch blocks ) 3 . create edges between OPINs and IPINs ( direct - connections )
void build_rr_graph_edges(RRGraph& rr_graph, 
                          const vtr::vector<RRNodeId, RRSwitchId>& rr_node_driver_switches,
                          const DeviceGrid& grids,
                          const vtr::Point<size_t>& device_chan_width, 
                          const std::vector<t_segment_inf>& segment_inf,
                          const std::vector<vtr::Matrix<int>>& Fc_in,
                          const std::vector<vtr::Matrix<int>>& Fc_out,
                          const e_switch_block_type& sb_type, const int& Fs,
                          const e_switch_block_type& sb_subtype, const int& subFs,
                          const bool& wire_opposite_side) {
  build_rr_graph_edges_for_source_nodes(rr_graph, rr_node_driver_switches, grids);
  build_rr_graph_edges_for_sink_nodes(rr_graph, rr_node_driver_switches, grids);
  vtr::Point<size_t> gsb_range(grids.width() - 2, grids.height() - 2);
  for (size_t ix = 0; ix <= gsb_range.x(); ++ix) {
    for (size_t iy = 0; iy <= gsb_range.y(); ++iy) { 
      vtr::Point<size_t> gsb_coord(ix, iy);
      const RRGSB& rr_gsb = build_one_tileable_rr_gsb(grids, rr_graph,
                                                      device_chan_width, segment_inf,
                                                      gsb_coord);
      t_track2pin_map track2ipin_map; 
      track2ipin_map = build_gsb_track_to_ipin_map(rr_graph, rr_gsb, grids, segment_inf, Fc_in);
      t_pin2track_map opin2track_map; 
      opin2track_map = build_gsb_opin_to_track_map(rr_graph, rr_gsb, grids, segment_inf, Fc_out);
      t_track2track_map sb_conn; 
      sb_conn = build_gsb_track_to_track_map(rr_graph, rr_gsb, 
                                             sb_type, Fs, sb_subtype, subFs, wire_opposite_side, 
                                             segment_inf);
      build_edges_for_one_tileable_rr_gsb(rr_graph, rr_gsb,
                                          track2ipin_map, opin2track_map, 
                                          sb_conn, rr_node_driver_switches);
    }
  }
}
void build_rr_graph_edges ( RRGraph & rr_graph , const vtr :: vector < RRNodeId , RRSwitchId > & rr_node_driver_switches , const DeviceGrid & grids , const vtr :: Point < size_t > & device_chan_width , const std :: vector < t_segment_inf > & segment_inf , const std :: vector < vtr :: Matrix < int > > & Fc_in , const std :: vector < vtr :: Matrix < int > > & Fc_out , const e_switch_block_type & sb_type , const int & Fs , const e_switch_block_type & sb_subtype , const int & subFs , const bool & wire_opposite_side ) { build_rr_graph_edges_for_source_nodes ( rr_graph , rr_node_driver_switches , grids ) ; build_rr_graph_edges_for_sink_nodes ( rr_graph , rr_node_driver_switches , grids ) ; vtr :: Point < size_t > gsb_range ( grids . width ( ) - 2 , grids . height ( ) - 2 ) ; for ( size_t ix = 0 ; ix <= gsb_range . x ( ) ; ++ ix ) { for ( size_t iy = 0 ; iy <= gsb_range . y ( ) ; ++ iy ) { vtr :: Point < size_t > gsb_coord ( ix , iy ) ; const RRGSB & rr_gsb = build_one_tileable_rr_gsb ( grids , rr_graph , device_chan_width , segment_inf , gsb_coord ) ; t_track2pin_map track2ipin_map ; track2ipin_map = build_gsb_track_to_ipin_map ( rr_graph , rr_gsb , grids , segment_inf , Fc_in ) ; t_pin2track_map opin2track_map ; opin2track_map = build_gsb_opin_to_track_map ( rr_graph , rr_gsb , grids , segment_inf , Fc_out ) ; t_track2track_map sb_conn ; sb_conn = build_gsb_track_to_track_map ( rr_graph , rr_gsb , sb_type , Fs , sb_subtype , subFs , wire_opposite_side , segment_inf ) ; build_edges_for_one_tileable_rr_gsb ( rr_graph , rr_gsb , track2ipin_map , opin2track_map , sb_conn , rr_node_driver_switches ) ; } } }
Build the edges of each rr_node tile by tile:
 We classify rr_nodes into a general switch block (GSB) data structure
 where we create edges to each rr_nodes in the GSB with respect to
 Fc_in and Fc_out, switch block patterns
 For each GSB:
 1. create edges between CHANX | CHANY and IPINs (connections inside connection blocks)
 2. create edges between OPINs, CHANX and CHANY (connections inside switch blocks)
 3. create edges between OPINs and IPINs (direct-connections)
Build the edges of each rr_node tile by tile : We classify rr_nodes into a general switch block ( GSB ) data structure where we create edges to each rr_nodes in the GSB with respect to Fc_in and Fc_out switch block patterns For each GSB : 1 . create edges between CHANX | CHANY and IPINs ( connections inside connection blocks ) 2 . create edges between OPINs CHANX and CHANY ( connections inside switch blocks ) 3 . create edges between OPINs and IPINs ( direct - connections )
/* Create edges for SOURCE and SINK nodes for a tileable rr_graph */ /* Go Switch Block by Switch Block */ //vpr_printf(TIO_MESSAGE_INFO, "Building edges for GSB[%lu][%lu]\n", ix, iy); /* Create a GSB object */ /* adapt the track_to_ipin_lookup for the GSB nodes */ /* [0..track_gsb_side][0..num_tracks][ipin_indices] */ /* adapt the opin_to_track_map for the GSB nodes */ /* [0..gsb_side][0..num_opin_node][track_indices] */ /* adapt the switch_block_conn for the GSB nodes */ /* [0..from_gsb_side][0..chan_width-1][track_indices] */ /* Build edges for a GSB */ /* Finish this GSB, go to the next*/