openfpga/src/fabric/build_mux_modules.cpp
/*********************************************************************
 * Generate  Verilog codes modeling an branch circuit 
 * for a RRAM-based multiplexer with the given size 
 * Support structural and behavioral Verilog codes
 *********************************************************************/
Generate  Verilog codes modeling an branch circuit
for a RRAM-based multiplexer with the given size
Support structural and behavioral Verilog codes
Generate Verilog codes modeling an branch circuit for a RRAM - based multiplexer with the given size Support structural and behavioral Verilog codes
static 
void build_rram_mux_branch_module(ModuleManager& module_manager,
                                  const CircuitLibrary& circuit_lib, 
                                  const CircuitModelId& mux_model, 
                                  const std::string& module_name, 
                                  const MuxGraph& mux_graph) {
  std::vector<CircuitPortId> mux_input_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_INPUT, true);
  std::vector<CircuitPortId> mux_output_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
  std::vector<CircuitPortId> mux_blb_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_BLB, true);
  std::vector<CircuitPortId> mux_wl_ports = circuit_lib.model_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_WL, true);
  size_t num_inputs = mux_graph.num_inputs();
  size_t num_outputs = mux_graph.num_outputs();
  size_t num_mems = mux_graph.num_memory_bits();
  VTR_ASSERT(1 == num_outputs);
  VTR_ASSERT(1 == mux_graph.num_levels());
  VTR_ASSERT(1 == mux_input_ports.size());
  VTR_ASSERT(1 == mux_output_ports.size());
  VTR_ASSERT(1 == mux_blb_ports.size());
  VTR_ASSERT(1 == mux_wl_ports.size());
  ModuleId mux_module = module_manager.add_module(module_name); 
  VTR_ASSERT(ModuleId::INVALID() != mux_module);
  std::vector<CircuitPortId> prog_enable_ports = circuit_lib.model_global_ports_by_type(mux_model, CIRCUIT_MODEL_PORT_INPUT, true, true);
  for (const auto& port : prog_enable_ports) {
    BasicPort global_port(circuit_lib.port_prefix(port), circuit_lib.port_size(port));
    module_manager.add_port(mux_module, global_port, ModuleManager::MODULE_GLOBAL_PORT);
  }
  BasicPort input_port(circuit_lib.port_prefix(mux_input_ports[0]), num_inputs);
  module_manager.add_port(mux_module, input_port, ModuleManager::MODULE_INPUT_PORT);
  BasicPort output_port(circuit_lib.port_prefix(mux_output_ports[0]), num_outputs);
  module_manager.add_port(mux_module, output_port, ModuleManager::MODULE_OUTPUT_PORT);
  BasicPort blb_port(circuit_lib.port_prefix(mux_blb_ports[0]), num_mems + 1);
  module_manager.add_port(mux_module, blb_port, ModuleManager::MODULE_INPUT_PORT);
  BasicPort wl_port(circuit_lib.port_prefix(mux_wl_ports[0]), num_mems + 1);
  module_manager.add_port(mux_module, wl_port, ModuleManager::MODULE_INPUT_PORT);
}
static void build_rram_mux_branch_module ( ModuleManager & module_manager , const CircuitLibrary & circuit_lib , const CircuitModelId & mux_model , const std :: string & module_name , const MuxGraph & mux_graph ) { std :: vector < CircuitPortId > mux_input_ports = circuit_lib . model_ports_by_type ( mux_model , CIRCUIT_MODEL_PORT_INPUT , true ) ; std :: vector < CircuitPortId > mux_output_ports = circuit_lib . model_ports_by_type ( mux_model , CIRCUIT_MODEL_PORT_OUTPUT , true ) ; std :: vector < CircuitPortId > mux_blb_ports = circuit_lib . model_ports_by_type ( mux_model , CIRCUIT_MODEL_PORT_BLB , true ) ; std :: vector < CircuitPortId > mux_wl_ports = circuit_lib . model_ports_by_type ( mux_model , CIRCUIT_MODEL_PORT_WL , true ) ; size_t num_inputs = mux_graph . num_inputs ( ) ; size_t num_outputs = mux_graph . num_outputs ( ) ; size_t num_mems = mux_graph . num_memory_bits ( ) ; VTR_ASSERT ( 1 == num_outputs ) ; VTR_ASSERT ( 1 == mux_graph . num_levels ( ) ) ; VTR_ASSERT ( 1 == mux_input_ports . size ( ) ) ; VTR_ASSERT ( 1 == mux_output_ports . size ( ) ) ; VTR_ASSERT ( 1 == mux_blb_ports . size ( ) ) ; VTR_ASSERT ( 1 == mux_wl_ports . size ( ) ) ; ModuleId mux_module = module_manager . add_module ( module_name ) ; VTR_ASSERT ( ModuleId :: INVALID ( ) != mux_module ) ; std :: vector < CircuitPortId > prog_enable_ports = circuit_lib . model_global_ports_by_type ( mux_model , CIRCUIT_MODEL_PORT_INPUT , true , true ) ; for ( const auto & port : prog_enable_ports ) { BasicPort global_port ( circuit_lib . port_prefix ( port ) , circuit_lib . port_size ( port ) ) ; module_manager . add_port ( mux_module , global_port , ModuleManager :: MODULE_GLOBAL_PORT ) ; } BasicPort input_port ( circuit_lib . port_prefix ( mux_input_ports [ 0 ] ) , num_inputs ) ; module_manager . add_port ( mux_module , input_port , ModuleManager :: MODULE_INPUT_PORT ) ; BasicPort output_port ( circuit_lib . port_prefix ( mux_output_ports [ 0 ] ) , num_outputs ) ; module_manager . add_port ( mux_module , output_port , ModuleManager :: MODULE_OUTPUT_PORT ) ; BasicPort blb_port ( circuit_lib . port_prefix ( mux_blb_ports [ 0 ] ) , num_mems + 1 ) ; module_manager . add_port ( mux_module , blb_port , ModuleManager :: MODULE_INPUT_PORT ) ; BasicPort wl_port ( circuit_lib . port_prefix ( mux_wl_ports [ 0 ] ) , num_mems + 1 ) ; module_manager . add_port ( mux_module , wl_port , ModuleManager :: MODULE_INPUT_PORT ) ; }
Generate  Verilog codes modeling an branch circuit
 for a RRAM-based multiplexer with the given size
 Support structural and behavioral Verilog codes
Generate Verilog codes modeling an branch circuit for a RRAM - based multiplexer with the given size Support structural and behavioral Verilog codes
/* Get the input ports from the mux */ /* Get the output ports from the mux */ /* Get the BL and WL ports from the mux */ /* Generate the Verilog netlist according to the mux_graph */ /* Find out the number of inputs */ /* Find out the number of outputs */ /* Find out the number of memory bits */ /* Check codes to ensure the port of Verilog netlists will match */ /* MUX graph must have only 1 output */ /* MUX graph must have only 1 level*/ /* MUX graph must have only 1 input and 1 BLB and 1 WL port */ /* Create a Verilog Module based on the circuit model, and add to module manager */ /* Add module ports */ /* Add each global programming enable/disable ports */ /* Configure each global port */ /* Add each input port */ /* Add each output port */ /* Add RRAM programming ports, 
   * RRAM MUXes require one more pair of BLB and WL 
   * to configure the memories. See schematic for details
   */ /* Note: we do not generate the internal structure of the ReRAM-based MUX
   * circuit as a module graph! 
   * This is mainly due to that the internal structure could be different
   * in Verilog or SPICE netlists
   * Leave the writers to customize this 
   */