openfpga/src/fabric/build_essential_modules.cpp
/************************************************
 * Build a module of a pass-gate,
 * either transmission-gate or pass-transistor
 ***********************************************/
Build a module of a pass-gate,
either transmission-gate or pass-transistor
Build a module of a pass - gate either transmission - gate or pass - transistor
static 
void build_passgate_module(ModuleManager& module_manager, 
                           const CircuitLibrary& circuit_lib,
                           const CircuitModelId& circuit_model) {
  std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
  std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
  std::vector<CircuitPortId> global_ports = circuit_lib.model_global_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true, true);
  switch (circuit_lib.pass_gate_logic_type(circuit_model)) {
  case CIRCUIT_MODEL_PASS_GATE_TRANSMISSION:
    VTR_ASSERT( 3 == input_ports.size() );
    for (const auto& input_port : input_ports) {
      VTR_ASSERT(1 == circuit_lib.port_size(input_port));
    }
    break;
  case CIRCUIT_MODEL_PASS_GATE_TRANSISTOR:
    VTR_ASSERT( 2 == input_ports.size() );
    for (const auto& input_port : input_ports) {
      VTR_ASSERT(1 == circuit_lib.port_size(input_port));
    }
    break;
  default:
    VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid topology for circuit model '%s'!\n",
                  circuit_lib.model_name(circuit_model).c_str());
    exit(1);
  }
  VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
  ModuleId module_id = add_circuit_model_to_module_manager(module_manager, circuit_lib, circuit_model); 
  VTR_ASSERT(true == module_manager.valid_module_id(module_id));
}
static void build_passgate_module ( ModuleManager & module_manager , const CircuitLibrary & circuit_lib , const CircuitModelId & circuit_model ) { std :: vector < CircuitPortId > input_ports = circuit_lib . model_ports_by_type ( circuit_model , CIRCUIT_MODEL_PORT_INPUT , true ) ; std :: vector < CircuitPortId > output_ports = circuit_lib . model_ports_by_type ( circuit_model , CIRCUIT_MODEL_PORT_OUTPUT , true ) ; std :: vector < CircuitPortId > global_ports = circuit_lib . model_global_ports_by_type ( circuit_model , CIRCUIT_MODEL_PORT_INPUT , true , true ) ; switch ( circuit_lib . pass_gate_logic_type ( circuit_model ) ) { case CIRCUIT_MODEL_PASS_GATE_TRANSMISSION : VTR_ASSERT ( 3 == input_ports . size ( ) ) ; for ( const auto & input_port : input_ports ) { VTR_ASSERT ( 1 == circuit_lib . port_size ( input_port ) ) ; } break ; case CIRCUIT_MODEL_PASS_GATE_TRANSISTOR : VTR_ASSERT ( 2 == input_ports . size ( ) ) ; for ( const auto & input_port : input_ports ) { VTR_ASSERT ( 1 == circuit_lib . port_size ( input_port ) ) ; } break ; default : VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " , circuit_lib . model_name ( circuit_model ) . c_str ( ) ) ; exit ( 1 ) ; } VTR_ASSERT ( ( 1 == output_ports . size ( ) ) && ( 1 == circuit_lib . port_size ( output_ports [ 0 ] ) ) ) ; ModuleId module_id = add_circuit_model_to_module_manager ( module_manager , circuit_lib , circuit_model ) ; VTR_ASSERT ( true == module_manager . valid_module_id ( module_id ) ) ; }
Build a module of a pass-gate,
 either transmission-gate or pass-transistor
Build a module of a pass - gate either transmission - gate or pass - transistor
/* Find the input port, output port*/ /* Make sure:
     * There is only 3 input port (in, sel, selb), 
     * each size of which is 1
     */ /* Make sure:
     * There is only 2 input port (in, sel), 
     * each size of which is 1
     */ /* Make sure:
   * There is only 1 output port, 
   * each size of which is 1
   */ /* Create a Verilog Module based on the circuit model, and add to module manager */