openfpga/src/fabric/build_mux_modules.cpp
/***********************************************
 * Generate Verilog codes modeling a multiplexer 
 * with the given graph-level description
 **********************************************/
Generate Verilog codes modeling a multiplexer
with the given graph-level description
Generate Verilog codes modeling a multiplexer with the given graph - level description
static 
void build_mux_module(ModuleManager& module_manager,
                      const CircuitLibrary& circuit_lib, 
                      const CircuitModelId& circuit_model, 
                      const MuxGraph& mux_graph) {
  std::string module_name = generate_mux_subckt_name(circuit_lib, circuit_model, 
                                                     find_mux_num_datapath_inputs(circuit_lib, circuit_model, mux_graph.num_inputs()), 
                                                     std::string(""));
  switch (circuit_lib.design_tech_type(circuit_model)) {
  case CIRCUIT_MODEL_DESIGN_CMOS:
    build_cmos_mux_module(module_manager, circuit_lib, circuit_model, module_name, mux_graph);
    break;
  case CIRCUIT_MODEL_DESIGN_RRAM:
    build_rram_mux_module(module_manager, circuit_lib, circuit_model, module_name, mux_graph);
    break;
  default:
    VTR_LOGF_ERROR(__FILE__, __LINE__, "Invalid design technology of multiplexer '%s'\n",
                 circuit_lib.model_name(circuit_model).c_str()); 
    exit(1);
  }
}
static void build_mux_module ( ModuleManager & module_manager , const CircuitLibrary & circuit_lib , const CircuitModelId & circuit_model , const MuxGraph & mux_graph ) { std :: string module_name = generate_mux_subckt_name ( circuit_lib , circuit_model , find_mux_num_datapath_inputs ( circuit_lib , circuit_model , mux_graph . num_inputs ( ) ) , std :: string ( " " ) ) ; switch ( circuit_lib . design_tech_type ( circuit_model ) ) { case CIRCUIT_MODEL_DESIGN_CMOS : build_cmos_mux_module ( module_manager , circuit_lib , circuit_model , module_name , mux_graph ) ; break ; case CIRCUIT_MODEL_DESIGN_RRAM : build_rram_mux_module ( module_manager , circuit_lib , circuit_model , module_name , mux_graph ) ; break ; default : VTR_LOGF_ERROR ( __FILE__ , __LINE__ , " \n " , circuit_lib . model_name ( circuit_model ) . c_str ( ) ) ; exit ( 1 ) ; } }
Generate Verilog codes modeling a multiplexer
 with the given graph-level description
Generate Verilog codes modeling a multiplexer with the given graph - level description
/* Multiplexers built with different technology is in different organization */ /* SRAM-based Multiplexer Verilog module generation */ /* TODO: RRAM-based Multiplexer Verilog module generation */