openfpga/src/fpga_spice/spice_grid.cpp
/*****************************************************************************
 * This function will create a Verilog file and print out a Verilog netlist 
 * for the logical tile (pb_graph/pb_type) 
 *****************************************************************************/
This function will create a Verilog file and print out a Verilog netlist
for the logical tile (pb_graph/pb_type)
This function will create a Verilog file and print out a Verilog netlist for the logical tile ( pb_graph / pb_type )
static 
void print_spice_logical_tile_netlist(NetlistManager& netlist_manager,
                                        const ModuleManager& module_manager,
                                        const VprDeviceAnnotation& device_annotation,
                                        const std::string& subckt_dir,
                                        t_pb_graph_node* pb_graph_head,
                                        const bool& verbose) {
  VTR_LOG("Writing Verilog netlists for logic tile '%s' ...",
          pb_graph_head->pb_type->name);
  VTR_LOG("\n");
  rec_print_spice_logical_tile(netlist_manager,
                               module_manager,
                               device_annotation, 
                               subckt_dir,
                               pb_graph_head,
                               verbose);
  VTR_LOG("Done\n");
  VTR_LOG("\n");
}
static void print_spice_logical_tile_netlist ( NetlistManager & netlist_manager , const ModuleManager & module_manager , const VprDeviceAnnotation & device_annotation , const std :: string & subckt_dir , t_pb_graph_node * pb_graph_head , const bool & verbose ) { VTR_LOG ( " " , pb_graph_head -> pb_type -> name ) ; VTR_LOG ( " \n " ) ; rec_print_spice_logical_tile ( netlist_manager , module_manager , device_annotation , subckt_dir , pb_graph_head , verbose ) ; VTR_LOG ( " \n " ) ; VTR_LOG ( " \n " ) ; }
This function will create a Verilog file and print out a Verilog netlist
 for the logical tile (pb_graph/pb_type)
This function will create a Verilog file and print out a Verilog netlist for the logical tile ( pb_graph / pb_type )
/* Print SPICE subckts for all the pb_types/pb_graph_nodes
   * use a Depth-First Search Algorithm to print the sub-modules 
   * Note: DFS is the right way. Do NOT use BFS.
   * DFS can guarantee that all the sub-modules can be registered properly
   * to its parent in module manager  
   */ /* Print SPICE subckts starting from the top-level pb_type/pb_graph_node, and traverse the graph in a recursive way */