openfpga/src/fpga_spice/spice_grid.cpp
/*****************************************************************************
 * Create logic block modules in a compact way:
 * 1. Only one module for each I/O on each border side (IO_TYPE)
 * 2. Only one module for each CLB (FILL_TYPE)
 * 3. Only one module for each heterogeneous block
 ****************************************************************************/
Create logic block modules in a compact way:
1. Only one module for each I/O on each border side (IO_TYPE)
2. Only one module for each CLB (FILL_TYPE)
3. Only one module for each heterogeneous block
Create logic block modules in a compact way : 1 . Only one module for each I / O on each border side ( IO_TYPE ) 2 . Only one module for each CLB ( FILL_TYPE ) 3 . Only one module for each heterogeneous block
void print_spice_grids(NetlistManager& netlist_manager,
                       const ModuleManager& module_manager,
                       const DeviceContext& device_ctx,
                       const VprDeviceAnnotation& device_annotation,
                       const std::string& subckt_dir,
                       const bool& verbose) {
  std::vector<std::string> netlist_names;
  VTR_LOG("Writing logical tiles...");
  VTR_LOGV(verbose, "\n");
  for (const t_logical_block_type& logical_tile : device_ctx.logical_block_types) {
    if (nullptr == logical_tile.pb_graph_head) {
      continue;
    }
    print_spice_logical_tile_netlist(netlist_manager,
                                       module_manager,
                                       device_annotation,
                                       subckt_dir,
                                       logical_tile.pb_graph_head,
                                       verbose);
  }
  VTR_LOG("Writing logical tiles...");
  VTR_LOG("Done\n");
  VTR_LOG("\n");
  VTR_LOG("Building physical tiles...");
  VTR_LOGV(verbose, "\n");
  for (const t_physical_tile_type& physical_tile : device_ctx.physical_tile_types) {
    if (true == is_empty_type(&physical_tile)) {
      continue;
    } else if (true == is_io_type(&physical_tile)) {
      std::set<e_side> io_type_sides = find_physical_io_tile_located_sides(device_ctx.grid,
                                                                           &physical_tile);
      for (const e_side& io_type_side : io_type_sides) {
        print_spice_physical_tile_netlist(netlist_manager,
                                          module_manager,
                                          subckt_dir, 
                                          &physical_tile,
                                          io_type_side);
      } 
      continue;
    } else {
      print_spice_physical_tile_netlist(netlist_manager,
                                        module_manager,
                                        subckt_dir, 
                                        &physical_tile,
                                        NUM_SIDES);
    }
  }
  VTR_LOG("Building physical tiles...");
  VTR_LOG("Done\n");
  VTR_LOG("\n");
}
void print_spice_grids ( NetlistManager & netlist_manager , const ModuleManager & module_manager , const DeviceContext & device_ctx , const VprDeviceAnnotation & device_annotation , const std :: string & subckt_dir , const bool & verbose ) { std :: vector < std :: string > netlist_names ; VTR_LOG ( " " ) ; VTR_LOGV ( verbose , " \n " ) ; for ( const t_logical_block_type & logical_tile : device_ctx . logical_block_types ) { if ( nullptr == logical_tile . pb_graph_head ) { continue ; } print_spice_logical_tile_netlist ( netlist_manager , module_manager , device_annotation , subckt_dir , logical_tile . pb_graph_head , verbose ) ; } VTR_LOG ( " " ) ; VTR_LOG ( " \n " ) ; VTR_LOG ( " \n " ) ; VTR_LOG ( " " ) ; VTR_LOGV ( verbose , " \n " ) ; for ( const t_physical_tile_type & physical_tile : device_ctx . physical_tile_types ) { if ( true == is_empty_type ( & physical_tile ) ) { continue ; } else if ( true == is_io_type ( & physical_tile ) ) { std :: set < e_side > io_type_sides = find_physical_io_tile_located_sides ( device_ctx . grid , & physical_tile ) ; for ( const e_side & io_type_side : io_type_sides ) { print_spice_physical_tile_netlist ( netlist_manager , module_manager , subckt_dir , & physical_tile , io_type_side ) ; } continue ; } else { print_spice_physical_tile_netlist ( netlist_manager , module_manager , subckt_dir , & physical_tile , NUM_SIDES ) ; } } VTR_LOG ( " " ) ; VTR_LOG ( " \n " ) ; VTR_LOG ( " \n " ) ; }
Create logic block modules in a compact way:
 1.
Create logic block modules in a compact way : 1 .
/* Create a vector to contain all the Verilog netlist names that have been generated in this function */ /* Enumerate the types of logical tiles, and build a module for each 
   * Write modules for all the pb_types/pb_graph_nodes
   * use a Depth-First Search Algorithm to print the sub-modules 
   * Note: DFS is the right way. Do NOT use BFS.
   * DFS can guarantee that all the sub-modules can be registered properly
   * to its parent in module manager  
   */ /* Bypass empty pb_graph */ /* Enumerate the types of physical tiles
   * Use the logical tile module to build the physical tiles
   */ /* Bypass empty type or nullptr */ /* Special for I/O block:
       * We will search the grids and see where the I/O blocks are located:
       * - If a I/O block locates on border sides of FPGA fabric:
       *   i.e., one or more from {TOP, RIGHT, BOTTOM, LEFT},
       *   we will generate one module for each border side 
       * - If a I/O block locates in the center of FPGA fabric:
       *   we will generate one module with NUM_SIDES (same treatment as regular grids) 
       */ /* For CLB and heterogenenous blocks */ /* Output a header file for all the logic blocks */ /*
  std::string grid_spice_fname(LOGIC_BLOCK_VERILOG_FILE_NAME);
  VTR_LOG("Writing header file for grid SPICE subckts '%s' ...",
          grid_spice_fname.c_str());
  print_spice_netlist_include_header_file(netlist_names,
                                          subckt_dir.c_str(),
                                          grid_spice_fname.c_str());
  VTR_LOG("Done\n");
   */