openfpga/src/repack/build_physical_lb_rr_graph.cpp
/***************************************************************************************
 * This functio will create a physical lb_rr_graph for a pb_graph considering physical modes only
 ***************************************************************************************/
This functio will create a physical lb_rr_graph for a pb_graph considering physical modes only
This functio will create a physical lb_rr_graph for a pb_graph considering physical modes only
static 
LbRRGraph build_lb_type_physical_lb_rr_graph(t_pb_graph_node* pb_graph_head,
                                             const VprDeviceAnnotation& device_annotation,
                                             const bool& verbose) {
  LbRRGraph lb_rr_graph;
  LbRRNodeId ext_source_index = lb_rr_graph.create_node(LB_SOURCE); 
  LbRRNodeId ext_sink_index = lb_rr_graph.create_node(LB_SINK); 
  LbRRNodeId ext_rr_index = lb_rr_graph.create_node(LB_INTERMEDIATE); 
  rec_build_physical_lb_rr_node_for_pb_graph_node(pb_graph_head, lb_rr_graph, device_annotation);
  rec_build_physical_lb_rr_edge_for_pb_graph_node(pb_graph_head, lb_rr_graph, ext_rr_index, device_annotation);
  t_pb_type* pb_type = pb_graph_head->pb_type;
  lb_rr_graph.set_node_capacity(ext_source_index, pb_type->num_input_pins + pb_type->num_clock_pins);
  for (int iport = 0; iport < pb_graph_head->num_input_ports; iport++) {
    for (int ipin = 0; ipin < pb_graph_head->num_input_pins[iport]; ipin++) {
      LbRRNodeId to_node = lb_rr_graph.find_node(LB_INTERMEDIATE, &(pb_graph_head->input_pins[iport][ipin]));
      VTR_ASSERT(true == lb_rr_graph.valid_node_id(to_node));
      LbRREdgeId edge = lb_rr_graph.create_edge(ext_source_index, to_node, nullptr);
      lb_rr_graph.set_edge_intrinsic_cost(edge, 1.);
    }
  }
  for (int iport = 0; iport < pb_graph_head->num_clock_ports; iport++) {
    for (int ipin = 0; ipin < pb_graph_head->num_clock_pins[iport]; ipin++) {
      LbRRNodeId to_node = lb_rr_graph.find_node(LB_INTERMEDIATE, &(pb_graph_head->clock_pins[iport][ipin]));
      VTR_ASSERT(true == lb_rr_graph.valid_node_id(to_node));
      LbRREdgeId edge = lb_rr_graph.create_edge(ext_source_index, to_node, nullptr);
      lb_rr_graph.set_edge_intrinsic_cost(edge, 1.);
    }
  }
  lb_rr_graph.set_node_capacity(ext_sink_index, pb_type->num_output_pins);
  lb_rr_graph.set_node_capacity(ext_rr_index, pb_type->num_output_pins);
  {
    LbRREdgeId edge = lb_rr_graph.create_edge(ext_rr_index, ext_sink_index, nullptr);
    lb_rr_graph.set_edge_intrinsic_cost(edge, 1.);
  }
  for (int iport = 0; iport < pb_graph_head->num_input_ports; iport++) {
    for (int ipin = 0; ipin < pb_graph_head->num_input_pins[iport]; ipin++) {
      LbRRNodeId to_node = lb_rr_graph.find_node(LB_INTERMEDIATE, &(pb_graph_head->input_pins[iport][ipin]));
      VTR_ASSERT(true == lb_rr_graph.valid_node_id(to_node));
      LbRREdgeId edge = lb_rr_graph.create_edge(ext_rr_index, to_node, nullptr);
      lb_rr_graph.set_edge_intrinsic_cost(edge, 1000.);
    }
  }
  for (int iport = 0; iport < pb_graph_head->num_clock_ports; iport++) {
    for (int ipin = 0; ipin < pb_graph_head->num_clock_pins[iport]; ipin++) {
      LbRRNodeId to_node = lb_rr_graph.find_node(LB_INTERMEDIATE, &(pb_graph_head->clock_pins[iport][ipin]));
      VTR_ASSERT(true == lb_rr_graph.valid_node_id(to_node));
      LbRREdgeId edge = lb_rr_graph.create_edge(ext_rr_index, to_node, nullptr);
      lb_rr_graph.set_edge_intrinsic_cost(edge, 1000.);
    }
  }
  VTR_LOGV(verbose,
           "\n\tNumber of nodes: %lu\n",
           lb_rr_graph.nodes().size());
  VTR_LOGV(verbose,
           "\tNumber of edges: %lu\n",
           lb_rr_graph.edges().size());
  return lb_rr_graph;
}
static LbRRGraph build_lb_type_physical_lb_rr_graph ( t_pb_graph_node * pb_graph_head , const VprDeviceAnnotation & device_annotation , const bool & verbose ) { LbRRGraph lb_rr_graph ; LbRRNodeId ext_source_index = lb_rr_graph . create_node ( LB_SOURCE ) ; LbRRNodeId ext_sink_index = lb_rr_graph . create_node ( LB_SINK ) ; LbRRNodeId ext_rr_index = lb_rr_graph . create_node ( LB_INTERMEDIATE ) ; rec_build_physical_lb_rr_node_for_pb_graph_node ( pb_graph_head , lb_rr_graph , device_annotation ) ; rec_build_physical_lb_rr_edge_for_pb_graph_node ( pb_graph_head , lb_rr_graph , ext_rr_index , device_annotation ) ; t_pb_type * pb_type = pb_graph_head -> pb_type ; lb_rr_graph . set_node_capacity ( ext_source_index , pb_type -> num_input_pins + pb_type -> num_clock_pins ) ; for ( int iport = 0 ; iport < pb_graph_head -> num_input_ports ; iport ++ ) { for ( int ipin = 0 ; ipin < pb_graph_head -> num_input_pins [ iport ] ; ipin ++ ) { LbRRNodeId to_node = lb_rr_graph . find_node ( LB_INTERMEDIATE , & ( pb_graph_head -> input_pins [ iport ] [ ipin ] ) ) ; VTR_ASSERT ( true == lb_rr_graph . valid_node_id ( to_node ) ) ; LbRREdgeId edge = lb_rr_graph . create_edge ( ext_source_index , to_node , nullptr ) ; lb_rr_graph . set_edge_intrinsic_cost ( edge , 1. ) ; } } for ( int iport = 0 ; iport < pb_graph_head -> num_clock_ports ; iport ++ ) { for ( int ipin = 0 ; ipin < pb_graph_head -> num_clock_pins [ iport ] ; ipin ++ ) { LbRRNodeId to_node = lb_rr_graph . find_node ( LB_INTERMEDIATE , & ( pb_graph_head -> clock_pins [ iport ] [ ipin ] ) ) ; VTR_ASSERT ( true == lb_rr_graph . valid_node_id ( to_node ) ) ; LbRREdgeId edge = lb_rr_graph . create_edge ( ext_source_index , to_node , nullptr ) ; lb_rr_graph . set_edge_intrinsic_cost ( edge , 1. ) ; } } lb_rr_graph . set_node_capacity ( ext_sink_index , pb_type -> num_output_pins ) ; lb_rr_graph . set_node_capacity ( ext_rr_index , pb_type -> num_output_pins ) ; { LbRREdgeId edge = lb_rr_graph . create_edge ( ext_rr_index , ext_sink_index , nullptr ) ; lb_rr_graph . set_edge_intrinsic_cost ( edge , 1. ) ; } for ( int iport = 0 ; iport < pb_graph_head -> num_input_ports ; iport ++ ) { for ( int ipin = 0 ; ipin < pb_graph_head -> num_input_pins [ iport ] ; ipin ++ ) { LbRRNodeId to_node = lb_rr_graph . find_node ( LB_INTERMEDIATE , & ( pb_graph_head -> input_pins [ iport ] [ ipin ] ) ) ; VTR_ASSERT ( true == lb_rr_graph . valid_node_id ( to_node ) ) ; LbRREdgeId edge = lb_rr_graph . create_edge ( ext_rr_index , to_node , nullptr ) ; lb_rr_graph . set_edge_intrinsic_cost ( edge , 1000. ) ; } } for ( int iport = 0 ; iport < pb_graph_head -> num_clock_ports ; iport ++ ) { for ( int ipin = 0 ; ipin < pb_graph_head -> num_clock_pins [ iport ] ; ipin ++ ) { LbRRNodeId to_node = lb_rr_graph . find_node ( LB_INTERMEDIATE , & ( pb_graph_head -> clock_pins [ iport ] [ ipin ] ) ) ; VTR_ASSERT ( true == lb_rr_graph . valid_node_id ( to_node ) ) ; LbRREdgeId edge = lb_rr_graph . create_edge ( ext_rr_index , to_node , nullptr ) ; lb_rr_graph . set_edge_intrinsic_cost ( edge , 1000. ) ; } } VTR_LOGV ( verbose , " \n \t \n " , lb_rr_graph . nodes ( ) . size ( ) ) ; VTR_LOGV ( verbose , " \t \n " , lb_rr_graph . edges ( ) . size ( ) ) ; return lb_rr_graph ; }
This functio will create a physical lb_rr_graph for a pb_graph considering physical modes only
This functio will create a physical lb_rr_graph for a pb_graph considering physical modes only
/* TODO: ensure we have an empty lb_rr_graph */ /* Define the external source, sink, and external interconnect for the routing resource graph of the logic block type */ /* Build the main body of lb rr_graph by walking through the pb_graph recursively */ /* Build all the regular nodes first */ /* Build all the edges and special node (SOURCE/SINK) */ /*******************************************************************************
   * Build logic block source node
   *******************************************************************************/ /* External source node drives all inputs going into logic block type */ /*******************************************************************************
   * Build logic block sink node
   *******************************************************************************/ /* External sink node driven by all outputs exiting logic block type */ /*******************************************************************************
   * Build node that approximates external interconnect
   *******************************************************************************/ /* External rr node that drives all existing logic block input pins and is driven by all outputs exiting logic block type */ /* Connect opin of logic block to sink */ /* Connect opin of logic block to all input and clock pins of logic block type */ /* set cost high to avoid using external interconnect unless necessary */ /* set cost high to avoid using external interconnect unless necessary */