libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp
/********************************************************************
 * This is a generic function to parse XML codes that describe
 * a port of a circuit model to circuit library
  *******************************************************************/
This is a generic function to parse XML codes that describe
a port of a circuit model to circuit library
This is a generic function to parse XML codes that describe a port of a circuit model to circuit library
static 
void read_xml_circuit_port(pugi::xml_node& xml_port,
                           const pugiutil::loc_data& loc_data,
                           CircuitLibrary& circuit_lib, const CircuitModelId& model) {
  const char* type_attr = get_attribute(xml_port, "type", loc_data).value();
  e_circuit_model_port_type port_type = string_to_circuit_model_port_type(std::string(type_attr));
  if (NUM_CIRCUIT_MODEL_PORT_TYPES == port_type) {
    archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_port),
                   "Invalid 'type' attribute '%s'\n",
                   type_attr);
  }
  CircuitPortId port = circuit_lib.add_model_port(model, port_type);
  circuit_lib.set_port_prefix(port, get_attribute(xml_port, "prefix", loc_data).as_string());
  const char* lib_name_attr = get_attribute(xml_port, "lib_name", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string(nullptr);
  if (nullptr != lib_name_attr) {
    circuit_lib.set_port_lib_name(port, get_attribute(xml_port, "lib_name", loc_data).as_string());
  } else {
    circuit_lib.set_port_lib_name(port, circuit_lib.port_prefix(port));
  }
  circuit_lib.set_port_size(port, get_attribute(xml_port, "size", loc_data).as_int(1));
  circuit_lib.set_port_is_io(port, get_attribute(xml_port, "is_io", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
  if (true == circuit_lib.port_is_io(port)) {
    circuit_lib.set_port_is_data_io(port, get_attribute(xml_port, "is_data_io", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
  }
  if (CIRCUIT_MODEL_PORT_SRAM == circuit_lib.port_type(port)) {
    circuit_lib.set_port_is_mode_select(port, get_attribute(xml_port, "mode_select", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
  } 
  circuit_lib.set_port_default_value(port, get_attribute(xml_port, "default_val", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(0));
  if ( (CIRCUIT_MODEL_LUT == circuit_lib.model_type(model))
    && (CIRCUIT_MODEL_PORT_INPUT == circuit_lib.port_type(port)) ) {
    const char* tri_state_map_attr = get_attribute(xml_port, "tri_state_map", loc_data, pugiutil::ReqOpt::OPTIONAL).value();
    if (nullptr != tri_state_map_attr) {
      circuit_lib.set_port_tri_state_map(port, get_attribute(xml_port, "tri_state_map", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string());
    }
  }
  if ( (CIRCUIT_MODEL_LUT == circuit_lib.model_type(model))
    && (CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib.port_type(port)) ) {
    circuit_lib.set_port_lut_frac_level(port, get_attribute(xml_port, "lut_frac_level", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(-1));
  }
  if (CIRCUIT_MODEL_LUT == circuit_lib.model_type(model)) {
    circuit_lib.set_port_is_harden_lut_port(port, get_attribute(xml_port, "is_harden_lut_port", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
  }
  if ( (CIRCUIT_MODEL_LUT == circuit_lib.model_type(model))
    && (CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib.port_type(port)) ) {
    read_xml_output_mask(xml_port, loc_data, circuit_lib, port);
  }
  circuit_lib.set_port_is_global(port, get_attribute(xml_port, "is_global", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
  circuit_lib.set_port_is_reset(port, get_attribute(xml_port, "is_reset", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
  circuit_lib.set_port_is_set(port, get_attribute(xml_port, "is_set", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
  circuit_lib.set_port_is_prog(port, get_attribute(xml_port, "is_prog", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
  circuit_lib.set_port_is_config_enable(port, get_attribute(xml_port, "is_config_enable", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
  circuit_lib.set_port_tri_state_model_name(port, get_attribute(xml_port, "circuit_model_name", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string());
  if (  (CIRCUIT_MODEL_PORT_BL  == circuit_lib.port_type(port))
     || (CIRCUIT_MODEL_PORT_WL  == circuit_lib.port_type(port))
     || (CIRCUIT_MODEL_PORT_BLB == circuit_lib.port_type(port))
     || (CIRCUIT_MODEL_PORT_WLB == circuit_lib.port_type(port)) ) {
    circuit_lib.set_port_inv_model_name(port, get_attribute(xml_port, "inv_circuit_model_name", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string());
  }
}
static void read_xml_circuit_port ( pugi :: xml_node & xml_port , const pugiutil :: loc_data & loc_data , CircuitLibrary & circuit_lib , const CircuitModelId & model ) { const char * type_attr = get_attribute ( xml_port , " " , loc_data ) . value ( ) ; e_circuit_model_port_type port_type = string_to_circuit_model_port_type ( std :: string ( type_attr ) ) ; if ( NUM_CIRCUIT_MODEL_PORT_TYPES == port_type ) { archfpga_throw ( loc_data . filename_c_str ( ) , loc_data . line ( xml_port ) , " \n " , type_attr ) ; } CircuitPortId port = circuit_lib . add_model_port ( model , port_type ) ; circuit_lib . set_port_prefix ( port , get_attribute ( xml_port , " " , loc_data ) . as_string ( ) ) ; const char * lib_name_attr = get_attribute ( xml_port , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) . as_string ( nullptr ) ; if ( nullptr != lib_name_attr ) { circuit_lib . set_port_lib_name ( port , get_attribute ( xml_port , " " , loc_data ) . as_string ( ) ) ; } else { circuit_lib . set_port_lib_name ( port , circuit_lib . port_prefix ( port ) ) ; } circuit_lib . set_port_size ( port , get_attribute ( xml_port , " " , loc_data ) . as_int ( 1 ) ) ; circuit_lib . set_port_is_io ( port , get_attribute ( xml_port , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) . as_bool ( false ) ) ; if ( true == circuit_lib . port_is_io ( port ) ) { circuit_lib . set_port_is_data_io ( port , get_attribute ( xml_port , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) . as_bool ( false ) ) ; } if ( CIRCUIT_MODEL_PORT_SRAM == circuit_lib . port_type ( port ) ) { circuit_lib . set_port_is_mode_select ( port , get_attribute ( xml_port , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) . as_bool ( false ) ) ; } circuit_lib . set_port_default_value ( port , get_attribute ( xml_port , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) . as_int ( 0 ) ) ; if ( ( CIRCUIT_MODEL_LUT == circuit_lib . model_type ( model ) ) && ( CIRCUIT_MODEL_PORT_INPUT == circuit_lib . port_type ( port ) ) ) { const char * tri_state_map_attr = get_attribute ( xml_port , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) . value ( ) ; if ( nullptr != tri_state_map_attr ) { circuit_lib . set_port_tri_state_map ( port , get_attribute ( xml_port , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) . as_string ( ) ) ; } } if ( ( CIRCUIT_MODEL_LUT == circuit_lib . model_type ( model ) ) && ( CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib . port_type ( port ) ) ) { circuit_lib . set_port_lut_frac_level ( port , get_attribute ( xml_port , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) . as_int ( -1 ) ) ; } if ( CIRCUIT_MODEL_LUT == circuit_lib . model_type ( model ) ) { circuit_lib . set_port_is_harden_lut_port ( port , get_attribute ( xml_port , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) . as_bool ( false ) ) ; } if ( ( CIRCUIT_MODEL_LUT == circuit_lib . model_type ( model ) ) && ( CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib . port_type ( port ) ) ) { read_xml_output_mask ( xml_port , loc_data , circuit_lib , port ) ; } circuit_lib . set_port_is_global ( port , get_attribute ( xml_port , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) . as_bool ( false ) ) ; circuit_lib . set_port_is_reset ( port , get_attribute ( xml_port , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) . as_bool ( false ) ) ; circuit_lib . set_port_is_set ( port , get_attribute ( xml_port , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) . as_bool ( false ) ) ; circuit_lib . set_port_is_prog ( port , get_attribute ( xml_port , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) . as_bool ( false ) ) ; circuit_lib . set_port_is_config_enable ( port , get_attribute ( xml_port , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) . as_bool ( false ) ) ; circuit_lib . set_port_tri_state_model_name ( port , get_attribute ( xml_port , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) . as_string ( ) ) ; if ( ( CIRCUIT_MODEL_PORT_BL == circuit_lib . port_type ( port ) ) || ( CIRCUIT_MODEL_PORT_WL == circuit_lib . port_type ( port ) ) || ( CIRCUIT_MODEL_PORT_BLB == circuit_lib . port_type ( port ) ) || ( CIRCUIT_MODEL_PORT_WLB == circuit_lib . port_type ( port ) ) ) { circuit_lib . set_port_inv_model_name ( port , get_attribute ( xml_port , " " , loc_data , pugiutil :: ReqOpt :: OPTIONAL ) . as_string ( ) ) ; } }
This is a generic function to parse XML codes that describe
 a port of a circuit model to circuit library
This is a generic function to parse XML codes that describe a port of a circuit model to circuit library
/* Find the type of the circuit port
   * so that we can add a new circuit port to circuit library 
   */ /* Translate the type of circuit model to enumerate */ /* Parse the name of the port */ /* Parse the name of the port in cell library. By default, the lib_name is the same as port name */ /* Parse the port size, by default it will be 1 */ /* Identify if the port is for io, this is only applicable to INPUT ports.
   * By default, it will NOT be a mode selection port
   */ /* Identify if the port is a data io, ONLY applicable to I/O port 
   * By default, it will NOT be a data io port
   */ /* Identify if the port is for mode selection, this is only applicable to SRAM ports.
   * By default, it will NOT be a mode selection port
   */ /* Identify the default value of the port, by default it will be 0 */ /* Identify the tri-state map of the port, by default it will be nullptr 
   * This is only applicable to input ports of a LUT
   */ /* Identify the fracturable-level of the port in LUTs, by default it will be -1
   * This is only applicable to output ports of a LUT
   */ /* Identify if the port carries a harden functionality rather than a reconfigurable port
   * This is only applicable to LUT circuit models.
   * The super LUT circuit model (whose netlists are supposed to be provided by users) contains
   * some hard logic inside, e.g., a carry logic.
   * By default, a port does NOT carry a hard functionality
   */ /* Identify the output mask of the port in LUTs, by default it will be applied to each pin of this port
   * This is only applicable to output ports of a LUT
   */ /* Identify if the port is a global port, by default it is NOT */ /* Identify if the port is a reset port, by default it is NOT */ /* Identify if the port is a set port, by default it is NOT */ /* Identify if the port is in programming purpose, by default it is NOT */ /* Identify if the port is to enable programming for FPGAs, by default it is NOT */ /* Find the name of circuit model that this port is linked to */ /* Find the name of circuit model that port is used for inversion of signals,
   * This is only applicable to BL/WL/BLB/WLB ports
   */