src/dev/net/ns_gige.cc
/**
 * This reads the device registers, which are detailed in the NS83820
 * spec sheet
 */
This reads the device registers, which are detailed in the NS83820
spec sheet
This reads the device registers which are detailed in the NS83820 spec sheet
Tick
NSGigE::read(PacketPtr pkt)
{
    assert(ioEnable);
    Addr daddr = pkt->getAddr() & 0xfff;
    DPRINTF(EthernetPIO, "read  da=%#x pa=%#x size=%d\n",
            daddr, pkt->getAddr(), pkt->getSize());
    if (daddr > LAST && daddr <=  RESERVED) {
        panic("Accessing reserved register");
    } else if (daddr > RESERVED && daddr <= 0x3FC) {
        return readConfig(pkt);
    } else if (daddr >= MIB_START && daddr <= MIB_END) {
        pkt->setLE<uint32_t>(0);
        pkt->makeAtomicResponse();
        return pioDelay;
    } else if (daddr > 0x3FC)
        panic("Something is messed up!\n");
    assert(pkt->getSize() == sizeof(uint32_t));
        uint32_t &reg = *pkt->getPtr<uint32_t>();
        uint16_t rfaddr;
        switch (daddr) {
          case CR:
            reg = regs.command;
            reg &= ~(CR_RXD | CR_TXD | CR_TXR | CR_RXR);
            break;
          case CFGR:
            reg = regs.config;
            break;
          case MEAR:
            reg = regs.mear;
            break;
          case PTSCR:
            reg = regs.ptscr;
            break;
          case ISR:
            reg = regs.isr;
            devIntrClear(ISR_ALL);
            break;
          case IMR:
            reg = regs.imr;
            break;
          case IER:
            reg = regs.ier;
            break;
          case IHR:
            reg = regs.ihr;
            break;
          case TXDP:
            reg = regs.txdp;
            break;
          case TXDP_HI:
            reg = regs.txdp_hi;
            break;
          case TX_CFG:
            reg = regs.txcfg;
            break;
          case GPIOR:
            reg = regs.gpior;
            break;
          case RXDP:
            reg = regs.rxdp;
            break;
          case RXDP_HI:
            reg = regs.rxdp_hi;
            break;
          case RX_CFG:
            reg = regs.rxcfg;
            break;
          case PQCR:
            reg = regs.pqcr;
            break;
          case WCSR:
            reg = regs.wcsr;
            break;
          case PCR:
            reg = regs.pcr;
            break;
          case RFCR:
            reg = regs.rfcr;
            break;
          case RFDR:
            rfaddr = (uint16_t)(regs.rfcr & RFCR_RFADDR);
            switch (rfaddr) {
              case 0x000:
                reg = rom.perfectMatch[1];
                reg = reg << 8;
                reg += rom.perfectMatch[0];
                break;
              case 0x002:
                reg = rom.perfectMatch[3] << 8;
                reg += rom.perfectMatch[2];
                break;
              case 0x004:
                reg = rom.perfectMatch[5] << 8;
                reg += rom.perfectMatch[4];
                break;
              default:
                if (rfaddr >= FHASH_ADDR &&
                    rfaddr < FHASH_ADDR + FHASH_SIZE) {
                    if (rfaddr % 2)
                        panic("unaligned read from filter hash table!");
                    reg = rom.filterHash[rfaddr - FHASH_ADDR + 1] << 8;
                    reg += rom.filterHash[rfaddr - FHASH_ADDR];
                    break;
                }
                panic("reading RFDR for something other than pattern"
                      " matching or hashing! %#x\n", rfaddr);
            }
            break;
          case SRR:
            reg = regs.srr;
            break;
          case MIBC:
            reg = regs.mibc;
            reg &= ~(MIBC_MIBS | MIBC_ACLR);
            break;
          case VRCR:
            reg = regs.vrcr;
            break;
          case VTCR:
            reg = regs.vtcr;
            break;
          case VDR:
            reg = regs.vdr;
            break;
          case CCSR:
            reg = regs.ccsr;
            break;
          case TBICR:
            reg = regs.tbicr;
            break;
          case TBISR:
            reg = regs.tbisr;
            break;
          case TANAR:
            reg = regs.tanar;
            break;
          case TANLPAR:
            reg = regs.tanlpar;
            break;
          case TANER:
            reg = regs.taner;
            break;
          case TESR:
            reg = regs.tesr;
            break;
          case M5REG:
            reg = 0;
            if (params().rx_thread)
                reg |= M5REG_RX_THREAD;
            if (params().tx_thread)
                reg |= M5REG_TX_THREAD;
            if (params().rss)
                reg |= M5REG_RSS;
            break;
          default:
            panic("reading unimplemented register: addr=%#x", daddr);
        }
        DPRINTF(EthernetPIO, "read from %#x: data=%d data=%#x\n",
                daddr, reg, reg);
    pkt->makeAtomicResponse();
    return pioDelay;
}
Tick NSGigE :: read ( PacketPtr pkt ) { assert ( ioEnable ) ; Addr daddr = pkt -> getAddr ( ) & 0xfff ; DPRINTF ( EthernetPIO , " \n " , daddr , pkt -> getAddr ( ) , pkt -> getSize ( ) ) ; if ( daddr > LAST && daddr <= RESERVED ) { panic ( " " ) ; } else if ( daddr > RESERVED && daddr <= 0x3FC ) { return readConfig ( pkt ) ; } else if ( daddr >= MIB_START && daddr <= MIB_END ) { pkt -> setLE < uint32_t > ( 0 ) ; pkt -> makeAtomicResponse ( ) ; return pioDelay ; } else if ( daddr > 0x3FC ) panic ( " \n " ) ; assert ( pkt -> getSize ( ) == sizeof ( uint32_t ) ) ; uint32_t & reg = * pkt -> getPtr < uint32_t > ( ) ; uint16_t rfaddr ; switch ( daddr ) { case CR : reg = regs . command ; reg &= ~ ( CR_RXD | CR_TXD | CR_TXR | CR_RXR ) ; break ; case CFGR : reg = regs . config ; break ; case MEAR : reg = regs . mear ; break ; case PTSCR : reg = regs . ptscr ; break ; case ISR : reg = regs . isr ; devIntrClear ( ISR_ALL ) ; break ; case IMR : reg = regs . imr ; break ; case IER : reg = regs . ier ; break ; case IHR : reg = regs . ihr ; break ; case TXDP : reg = regs . txdp ; break ; case TXDP_HI : reg = regs . txdp_hi ; break ; case TX_CFG : reg = regs . txcfg ; break ; case GPIOR : reg = regs . gpior ; break ; case RXDP : reg = regs . rxdp ; break ; case RXDP_HI : reg = regs . rxdp_hi ; break ; case RX_CFG : reg = regs . rxcfg ; break ; case PQCR : reg = regs . pqcr ; break ; case WCSR : reg = regs . wcsr ; break ; case PCR : reg = regs . pcr ; break ; case RFCR : reg = regs . rfcr ; break ; case RFDR : rfaddr = ( uint16_t ) ( regs . rfcr & RFCR_RFADDR ) ; switch ( rfaddr ) { case 0x000 : reg = rom . perfectMatch [ 1 ] ; reg = reg << 8 ; reg += rom . perfectMatch [ 0 ] ; break ; case 0x002 : reg = rom . perfectMatch [ 3 ] << 8 ; reg += rom . perfectMatch [ 2 ] ; break ; case 0x004 : reg = rom . perfectMatch [ 5 ] << 8 ; reg += rom . perfectMatch [ 4 ] ; break ; default : if ( rfaddr >= FHASH_ADDR && rfaddr < FHASH_ADDR + FHASH_SIZE ) { if ( rfaddr % 2 ) panic ( " " ) ; reg = rom . filterHash [ rfaddr - FHASH_ADDR + 1 ] << 8 ; reg += rom . filterHash [ rfaddr - FHASH_ADDR ] ; break ; } panic ( " " " \n " , rfaddr ) ; } break ; case SRR : reg = regs . srr ; break ; case MIBC : reg = regs . mibc ; reg &= ~ ( MIBC_MIBS | MIBC_ACLR ) ; break ; case VRCR : reg = regs . vrcr ; break ; case VTCR : reg = regs . vtcr ; break ; case VDR : reg = regs . vdr ; break ; case CCSR : reg = regs . ccsr ; break ; case TBICR : reg = regs . tbicr ; break ; case TBISR : reg = regs . tbisr ; break ; case TANAR : reg = regs . tanar ; break ; case TANLPAR : reg = regs . tanlpar ; break ; case TANER : reg = regs . taner ; break ; case TESR : reg = regs . tesr ; break ; case M5REG : reg = 0 ; if ( params ( ) . rx_thread ) reg |= M5REG_RX_THREAD ; if ( params ( ) . tx_thread ) reg |= M5REG_TX_THREAD ; if ( params ( ) . rss ) reg |= M5REG_RSS ; break ; default : panic ( " " , daddr ) ; } DPRINTF ( EthernetPIO , " \n " , daddr , reg , reg ) ; pkt -> makeAtomicResponse ( ) ; return pioDelay ; }
This reads the device registers, which are detailed in the NS83820
 spec sheet
This reads the device registers which are detailed in the NS83820 spec sheet
//The mask is to give you only the offset into the device register file // there are some reserved registers, you can see ns_gige_reg.h and // the spec sheet for details // don't implement all the MIB's.  hopefully the kernel // doesn't actually DEPEND upon their values // MIB are just hardware stats keepers //these are supposed to be cleared on a read // see the spec sheet for how RFCR and RFDR work // basically, you write to RFCR to tell the machine // what you want to do next, then you act upon RFDR, // and the device will be prepared b/c of what you // wrote to RFCR // Read from perfect match ROM octets // Read filter hash table // Only word-aligned reads supported