src/CodeGen_CoreIR_Target.cpp
// This adds another usable wire, generally the output of a new module.
This adds another usable wire, generally the output of a new module.
This adds another usable wire generally the output of a new module .
void CodeGen_CoreIR_Target::CodeGen_CoreIR_C::add_wire(string out_name, CoreIR::Wireable* in_wire, vector<uint> out_indices) {
  if (is_storage(out_name)) {
    auto pt_struct = hw_store_set[out_name];
    if (!pt_struct->was_read && !pt_struct->was_written &&
        out_indices.empty() && !pt_struct->is_reg()) {
      auto pt_wire = hw_store_set[out_name]->wire;
      internal_assert(CoreIR::Instance::classof(pt_wire));
      CoreIR::Instance* pt_inst = &(cast<CoreIR::Instance>(*pt_wire));
      def->removeInstance(pt_inst);
      hw_store_set.erase(out_name);
      hw_wire_set[out_name] = in_wire;
    } else {
      if (pt_struct->was_written && pt_struct->was_read) {
        string pt_name = "pt" + out_name + "_" + unique_name('p');
        CoreIR::Type* ptype = pt_struct->ptype;
        stream << "// created passthrough with name " << pt_name << endl;
        CoreIR::Wireable* pt = def->addInstance(pt_name, gens["passthrough"], {{"type",CoreIR::Const::make(context,ptype)}});
        pt_struct->wire = pt;
        pt_struct->was_read = false;
      }
      if (pt_struct->is_reg()) {
        stream << "// disconnecting wire for reg " << out_name << endl;
        CoreIR::Wireable* d_wire = pt_struct->reg->sel("in");
        for (int i=out_indices.size()-1; i >= 0; --i) {
          d_wire = d_wire->sel(out_indices[i]);
        }
        def->disconnect(d_wire);
        def->connect(in_wire, d_wire);
      }
      pt_struct->was_written = true;
      stream << "// added passthrough wire to " << out_name << endl;
      CoreIR::Wireable* current_wire = pt_struct->wire->sel("in");
      for (int i=out_indices.size()-1; i >= 0; --i) {
        current_wire = current_wire->sel(out_indices[i]);
      }
      def->connect(in_wire, current_wire);
    }
  } else {
    internal_assert(out_indices.empty());
    hw_wire_set[out_name] = in_wire;
  }
}
void CodeGen_CoreIR_Target :: CodeGen_CoreIR_C :: add_wire ( string out_name , CoreIR :: Wireable * in_wire , vector < uint > out_indices ) { if ( is_storage ( out_name ) ) { auto pt_struct = hw_store_set [ out_name ] ; if ( ! pt_struct -> was_read && ! pt_struct -> was_written && out_indices . empty ( ) && ! pt_struct -> is_reg ( ) ) { auto pt_wire = hw_store_set [ out_name ] -> wire ; internal_assert ( CoreIR :: Instance :: classof ( pt_wire ) ) ; CoreIR :: Instance * pt_inst = & ( cast < CoreIR :: Instance > ( * pt_wire ) ) ; def -> removeInstance ( pt_inst ) ; hw_store_set . erase ( out_name ) ; hw_wire_set [ out_name ] = in_wire ; } else { if ( pt_struct -> was_written && pt_struct -> was_read ) { string pt_name = " " + out_name + " " + unique_name ( ' ' ) ; CoreIR :: Type * ptype = pt_struct -> ptype ; stream << " " << pt_name << endl ; CoreIR :: Wireable * pt = def -> addInstance ( pt_name , gens [ " " ] , { { " " , CoreIR :: Const :: make ( context , ptype ) } } ) ; pt_struct -> wire = pt ; pt_struct -> was_read = false ; } if ( pt_struct -> is_reg ( ) ) { stream << " " << out_name << endl ; CoreIR :: Wireable * d_wire = pt_struct -> reg -> sel ( " " ) ; for ( int i = out_indices . size ( ) - 1 ; i >= 0 ; -- i ) { d_wire = d_wire -> sel ( out_indices [ i ] ) ; } def -> disconnect ( d_wire ) ; def -> connect ( in_wire , d_wire ) ; } pt_struct -> was_written = true ; stream << " " << out_name << endl ; CoreIR :: Wireable * current_wire = pt_struct -> wire -> sel ( " " ) ; for ( int i = out_indices . size ( ) - 1 ; i >= 0 ; -- i ) { current_wire = current_wire -> sel ( out_indices [ i ] ) ; } def -> connect ( in_wire , current_wire ) ; } } else { internal_assert ( out_indices . empty ( ) ) ; hw_wire_set [ out_name ] = in_wire ; } }
This adds another usable wire, generally the output of a new module.
This adds another usable wire generally the output of a new module .
//cout << "add wire to " << out_name << "\n"; // this passthrough hasn't been used, so remove it // use the found passthrough // create a new passthrough, since this one is already connected // FIXME: copy over all stores (since wire might not encompass entire passthrough) //cout << "// wiring to " << out_name << endl; // disconnect associated wire in reg, and connect new wire //cout << "selecting in reg add_wire: " << out_indices[i] << endl; //cout << "select in add_wire done" << endl; //cout << "// added passthrough wire to " << out_name << endl; // connect wire to passthrough //cout << "selecting in add_wire: " << out_indices[i] << endl; // wire is being stored for use as an input