libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp
/********************************************************************
 * A writer to output delay matrices of a circuit model to XML format
 *******************************************************************/
A writer to output delay matrices of a circuit model to XML format
A writer to output delay matrices of a circuit model to XML format
static 
void write_xml_delay_matrix(std::fstream& fp,
                            const char* fname,
                            const CircuitLibrary& circuit_lib,
                            const CircuitModelId& model) {
  openfpga::check_file_stream(fname, fp);
  std::vector<CircuitPortId> in_ports;
  std::vector<CircuitPortId> out_ports;
  for (const auto& timing_edge : circuit_lib.timing_edges_by_model(model)) {
     CircuitPortId src_port = circuit_lib.timing_edge_src_port(timing_edge);
     if (in_ports.end() == std::find(in_ports.begin(), in_ports.end(), src_port)) {
       in_ports.push_back(src_port);
     }
     CircuitPortId sink_port = circuit_lib.timing_edge_sink_port(timing_edge);
     if (out_ports.end() == std::find(out_ports.begin(), out_ports.end(), sink_port)) {
       out_ports.push_back(sink_port);
     }
  }
  std::string in_port_string;
  for (const CircuitPortId& in_port : in_ports) {
    if (!in_port_string.empty()) {
      in_port_string += std::string(" ");
    }
    in_port_string += circuit_lib.port_prefix(in_port);
  } 
  std::string out_port_string;
  for (const CircuitPortId& out_port : out_ports) {
    if (!out_port_string.empty()) {
      out_port_string += std::string(" ");
    }
    out_port_string += circuit_lib.port_prefix(out_port);
  } 
  fp << "\t\t\t";
  fp << "<delay_matrix";
  write_xml_attribute(fp, "type", CIRCUIT_MODEL_DELAY_TYPE_STRING[CIRCUIT_MODEL_DELAY_RISE]); 
  write_xml_attribute(fp, "in_port", in_port_string.c_str()); 
  write_xml_attribute(fp, "out_port", out_port_string.c_str()); 
  fp << ">\n";
  for (const CircuitPortId& out_port : out_ports) {
    for (const size_t& out_pin : circuit_lib.pins(out_port)) {
      fp << "\t\t\t\t";
      size_t counter = 0;  
      for (const CircuitPortId& in_port : in_ports) {
        for (const size_t& in_pin : circuit_lib.pins(in_port)) {
          for (const auto& timing_edge : circuit_lib.timing_edges_by_model(model)) {
            CircuitPortId src_port = circuit_lib.timing_edge_src_port(timing_edge);
            size_t src_pin = circuit_lib.timing_edge_src_pin(timing_edge);
            CircuitPortId sink_port = circuit_lib.timing_edge_sink_port(timing_edge);
            size_t sink_pin = circuit_lib.timing_edge_sink_pin(timing_edge);
            if ( (src_port != in_port)
              || (src_pin != in_pin)
              || (sink_port != out_port)
              || (sink_pin != out_pin) ) {
              continue;
            }
            if (0 < counter) {
              fp << std::string(" ");
            }
            fp << std::scientific << circuit_lib.timing_edge_delay(timing_edge, CIRCUIT_MODEL_DELAY_RISE);
            counter++;
          }
        }
      }
      fp << "\n";
    }
  }
  fp << "\t\t\t";
  fp << "</delay_matrix>" << "\n";
  fp << "\t\t\t";
  fp << "<delay_matrix";
  write_xml_attribute(fp, "type", CIRCUIT_MODEL_DELAY_TYPE_STRING[CIRCUIT_MODEL_DELAY_FALL]); 
  write_xml_attribute(fp, "in_port", in_port_string.c_str()); 
  write_xml_attribute(fp, "out_port", out_port_string.c_str()); 
  fp << ">\n";
  for (const CircuitPortId& out_port : out_ports) {
    for (const size_t& out_pin : circuit_lib.pins(out_port)) {
      fp << "\t\t\t\t";
      size_t counter = 0;  
      for (const CircuitPortId& in_port : in_ports) {
        for (const size_t& in_pin : circuit_lib.pins(in_port)) {
          for (const auto& timing_edge : circuit_lib.timing_edges_by_model(model)) {
            CircuitPortId src_port = circuit_lib.timing_edge_src_port(timing_edge);
            size_t src_pin = circuit_lib.timing_edge_src_pin(timing_edge);
            CircuitPortId sink_port = circuit_lib.timing_edge_sink_port(timing_edge);
            size_t sink_pin = circuit_lib.timing_edge_sink_pin(timing_edge);
            if ( (src_port != in_port)
              || (src_pin != in_pin)
              || (sink_port != out_port)
              || (sink_pin != out_pin) ) {
              continue;
            }
            if (0 < counter) {
              fp << std::string(" ");
            }
            fp << std::scientific << circuit_lib.timing_edge_delay(timing_edge, CIRCUIT_MODEL_DELAY_FALL);
            counter++;
          }
        }
      }
      fp << "\n";
    }
  }
  fp << "\t\t\t";
  fp << "</delay_matrix>" << "\n";
}
static void write_xml_delay_matrix ( std :: fstream & fp , const char * fname , const CircuitLibrary & circuit_lib , const CircuitModelId & model ) { openfpga :: check_file_stream ( fname , fp ) ; std :: vector < CircuitPortId > in_ports ; std :: vector < CircuitPortId > out_ports ; for ( const auto & timing_edge : circuit_lib . timing_edges_by_model ( model ) ) { CircuitPortId src_port = circuit_lib . timing_edge_src_port ( timing_edge ) ; if ( in_ports . end ( ) == std :: find ( in_ports . begin ( ) , in_ports . end ( ) , src_port ) ) { in_ports . push_back ( src_port ) ; } CircuitPortId sink_port = circuit_lib . timing_edge_sink_port ( timing_edge ) ; if ( out_ports . end ( ) == std :: find ( out_ports . begin ( ) , out_ports . end ( ) , sink_port ) ) { out_ports . push_back ( sink_port ) ; } } std :: string in_port_string ; for ( const CircuitPortId & in_port : in_ports ) { if ( ! in_port_string . empty ( ) ) { in_port_string += std :: string ( " " ) ; } in_port_string += circuit_lib . port_prefix ( in_port ) ; } std :: string out_port_string ; for ( const CircuitPortId & out_port : out_ports ) { if ( ! out_port_string . empty ( ) ) { out_port_string += std :: string ( " " ) ; } out_port_string += circuit_lib . port_prefix ( out_port ) ; } fp << " \t \t \t " ; fp << " " ; write_xml_attribute ( fp , " " , CIRCUIT_MODEL_DELAY_TYPE_STRING [ CIRCUIT_MODEL_DELAY_RISE ] ) ; write_xml_attribute ( fp , " " , in_port_string . c_str ( ) ) ; write_xml_attribute ( fp , " " , out_port_string . c_str ( ) ) ; fp << " \n " ; for ( const CircuitPortId & out_port : out_ports ) { for ( const size_t & out_pin : circuit_lib . pins ( out_port ) ) { fp << " \t \t \t \t " ; size_t counter = 0 ; for ( const CircuitPortId & in_port : in_ports ) { for ( const size_t & in_pin : circuit_lib . pins ( in_port ) ) { for ( const auto & timing_edge : circuit_lib . timing_edges_by_model ( model ) ) { CircuitPortId src_port = circuit_lib . timing_edge_src_port ( timing_edge ) ; size_t src_pin = circuit_lib . timing_edge_src_pin ( timing_edge ) ; CircuitPortId sink_port = circuit_lib . timing_edge_sink_port ( timing_edge ) ; size_t sink_pin = circuit_lib . timing_edge_sink_pin ( timing_edge ) ; if ( ( src_port != in_port ) || ( src_pin != in_pin ) || ( sink_port != out_port ) || ( sink_pin != out_pin ) ) { continue ; } if ( 0 < counter ) { fp << std :: string ( " " ) ; } fp << std :: scientific << circuit_lib . timing_edge_delay ( timing_edge , CIRCUIT_MODEL_DELAY_RISE ) ; counter ++ ; } } } fp << " \n " ; } } fp << " \t \t \t " ; fp << " " << " \n " ; fp << " \t \t \t " ; fp << " " ; write_xml_attribute ( fp , " " , CIRCUIT_MODEL_DELAY_TYPE_STRING [ CIRCUIT_MODEL_DELAY_FALL ] ) ; write_xml_attribute ( fp , " " , in_port_string . c_str ( ) ) ; write_xml_attribute ( fp , " " , out_port_string . c_str ( ) ) ; fp << " \n " ; for ( const CircuitPortId & out_port : out_ports ) { for ( const size_t & out_pin : circuit_lib . pins ( out_port ) ) { fp << " \t \t \t \t " ; size_t counter = 0 ; for ( const CircuitPortId & in_port : in_ports ) { for ( const size_t & in_pin : circuit_lib . pins ( in_port ) ) { for ( const auto & timing_edge : circuit_lib . timing_edges_by_model ( model ) ) { CircuitPortId src_port = circuit_lib . timing_edge_src_port ( timing_edge ) ; size_t src_pin = circuit_lib . timing_edge_src_pin ( timing_edge ) ; CircuitPortId sink_port = circuit_lib . timing_edge_sink_port ( timing_edge ) ; size_t sink_pin = circuit_lib . timing_edge_sink_pin ( timing_edge ) ; if ( ( src_port != in_port ) || ( src_pin != in_pin ) || ( sink_port != out_port ) || ( sink_pin != out_pin ) ) { continue ; } if ( 0 < counter ) { fp << std :: string ( " " ) ; } fp << std :: scientific << circuit_lib . timing_edge_delay ( timing_edge , CIRCUIT_MODEL_DELAY_FALL ) ; counter ++ ; } } } fp << " \n " ; } } fp << " \t \t \t " ; fp << " " << " \n " ; }
A writer to output delay matrices of a circuit model to XML format
A writer to output delay matrices of a circuit model to XML format
/* Validate the file stream */ /* Collect the input ports and output ports */ /* For each input port of each edge, build a list of unique ports */ /* For each input port of each edge, build a list of unique ports */ /* Build the string of in_port list */ /* Build the string of out_port list */ /* Output rising edges */ /* Count the numbers of delays in one line */ /* Bypass unwanted edges */ /* This is the edge we want, output the rise delay */ /* One line of delay matrix finished here, output to the file */ /* Output falling edges */ /* Count the numbers of delays in one line */ /* Bypass unwanted edges */ /* This is the edge we want, output the rise delay */ /* One line of delay matrix finished here, output to the file */