src/occ_gpe1/gpe1_dimm_read.c
/*
 * Function Specifications:
 *
 * Name: dimm_write_int_mask
 *
 * Description:  Write the I2C interrupt mask and read I2C status register
 *
 * Inputs:       cmd is a pointer to IPC msg's cmd and cmd_data struct
 *
 * Outputs:      error: sets rc, address, and ffdc in the cmd_data's
 *                      GpeErrorStruct
 *
 * End Function Specification
 */
Function Specifications:
Name: dimm_write_int_mask

Write the I2C interrupt mask and read I2C status register

cmd is a pointer to IPC msg's cmd and cmd_data struct

sets rc, address, and ffdc in the cmd_data's
GpeErrorStruct

End Function Specification
Function Specifications : Name : dimm_write_int_mask Write the I2C interrupt mask and read I2C status register cmd is a pointer to IPC msg ' s cmd and cmd_data struct sets rc address and ffdc in the cmd_data ' s GpeErrorStruct End Function Specification
void dimm_write_int_mask(ipc_msg_t* cmd, void* arg)
{
    int      rc;
    uint32_t scomAddr;
    uint64_t regValue; 
    ipc_async_cmd_t *async_cmd = (ipc_async_cmd_t*)cmd;
    dimm_sm_args_t *args = (dimm_sm_args_t*)async_cmd->cmd_data;
    scomAddr = I2C_INTERRUPT_MASK_REG | SCOM_ENGINE_OFFSET(args->i2cEngine);
    regValue = 0x0000FFC000000000;
    rc = putscom_abs(scomAddr, regValue);
    if(rc)
    {
        PK_TRACE("dimm_write_int_mask: I2C_INTERRUPT_MASK_REG putscom 0x%08X->0x%08X%08X FAILED. rc = 0x%08x",
                 scomAddr, WORD_HIGH(regValue), WORD_LOW(regValue), rc);
        gpe_set_ffdc(&(args->error), scomAddr, GPE_RC_SCOM_PUT_FAILED, rc);
    }
    else
    {
        GPE1_DIMM_DBG("dimm_write_int_mask: putscom(0x%08X,0x%08X%08X) SUCCESS - INT MASK",
                      scomAddr, WORD_HIGH(regValue), WORD_LOW(regValue));
    }
    scomAddr = I2C_STATUS_REG | SCOM_ENGINE_OFFSET(args->i2cEngine);
    rc = getscom_abs(scomAddr, &regValue);
    if(rc)
    {
        PK_TRACE("dimm_write_int_mask: I2C_STATUS_REG getscom 0x%08X FAILED. rc = 0x%08x - STATUS",
                 scomAddr, rc);
        gpe_set_ffdc(&(args->error), scomAddr, GPE_RC_SCOM_GET_FAILED, rc);
    }
    else
    {
        GPE1_DIMM_DBG("dimm_write_int_mask: getscom(0x%08X) returned 0x%08X%08X) - STATUS #1",
                      scomAddr, WORD_HIGH(regValue), WORD_LOW(regValue));
        args->maxPorts = (regValue >> 48) & 0x7F;
        GPE1_DIMM_DBG("dimm_write_int_mask: maxPorts = %d", args->maxPorts);
    }
}
void dimm_write_int_mask ( ipc_msg_t * cmd , void * arg ) { int rc ; uint32_t scomAddr ; uint64_t regValue ; ipc_async_cmd_t * async_cmd = ( ipc_async_cmd_t * ) cmd ; dimm_sm_args_t * args = ( dimm_sm_args_t * ) async_cmd -> cmd_data ; scomAddr = I2C_INTERRUPT_MASK_REG | SCOM_ENGINE_OFFSET ( args -> i2cEngine ) ; regValue = 0x0000FFC000000000 ; rc = putscom_abs ( scomAddr , regValue ) ; if ( rc ) { PK_TRACE ( " " , scomAddr , WORD_HIGH ( regValue ) , WORD_LOW ( regValue ) , rc ) ; gpe_set_ffdc ( & ( args -> error ) , scomAddr , GPE_RC_SCOM_PUT_FAILED , rc ) ; } else { GPE1_DIMM_DBG ( " " , scomAddr , WORD_HIGH ( regValue ) , WORD_LOW ( regValue ) ) ; } scomAddr = I2C_STATUS_REG | SCOM_ENGINE_OFFSET ( args -> i2cEngine ) ; rc = getscom_abs ( scomAddr , & regValue ) ; if ( rc ) { PK_TRACE ( " " , scomAddr , rc ) ; gpe_set_ffdc ( & ( args -> error ) , scomAddr , GPE_RC_SCOM_GET_FAILED , rc ) ; } else { GPE1_DIMM_DBG ( " " , scomAddr , WORD_HIGH ( regValue ) , WORD_LOW ( regValue ) ) ; args -> maxPorts = ( regValue >> 48 ) & 0x7F ; GPE1_DIMM_DBG ( " " , args -> maxPorts ) ; } }
Function Specifications:
 Name: dimm_write_int_mask
Function Specifications : Name : dimm_write_int_mask
// a pointer to hold the putscom_abs register value // Enable the following bit in the interrupt mask: // invalid command, LBUS parity, back end overrun, back end access, // arbitration lost, nack received, data request, command complete, // stop, i2c busy // READ I2C STATUS REGISTER // max_num_of_ports (bits 9:15)