kernels/linux-2.4.0/arch/ia64/sn/io/pci_dma.c
/*
 * sn1 platform specific pci_alloc_consistent()
 *
 * this interface is meant for "command" streams, i.e. called only
 * once for initializing a device, so we don't want prefetching or
 * write gathering turned on, hence the PCIIO_DMA_CMD flag
 */
sn1 platform specific pci_alloc_consistent()
this interface is meant for "command" streams, i.e. called only
once for initializing a device, so we don't want prefetching or
write gathering turned on, hence the PCIIO_DMA_CMD flag
sn1 platform specific pci_alloc_consistent () this interface is meant for " command " streams i . e . called only once for initializing a device so we don ' t want prefetching or write gathering turned on hence the PCIIO_DMA_CMD flag
void *
sn1_pci_alloc_consistent (struct pci_dev *hwdev, size_t size, dma_addr_t *dma_handle)
{
        void *ret;
        int gfp = GFP_ATOMIC;
	devfs_handle_t    vhdl;
	struct sn1_device_sysdata *device_sysdata;
	paddr_t temp_ptr;
	*dma_handle = (dma_addr_t) NULL;
	device_sysdata = (struct sn1_device_sysdata *) hwdev->sysdata;
	vhdl = device_sysdata->vhdl;
        if ( ret = (void *)__get_free_pages(gfp, get_order(size)) ) {
		memset(ret, 0, size);
	} else {
		return(NULL);
	}
	temp_ptr = (paddr_t) __pa(ret);
	if (IS_PCIA64(hwdev)) {
		*dma_handle = pciio_dmatrans_addr(vhdl, NULL, temp_ptr, size,
			PCIBR_BARRIER | PCIIO_BYTE_STREAM | PCIIO_DMA_CMD
			| PCIIO_DMA_A64 );
		return (ret);
	}
	if (IS_PCI32G(hwdev)) {
		*dma_handle = pciio_dmatrans_addr(vhdl, NULL, temp_ptr, size,
			PCIBR_BARRIER | PCIIO_BYTE_STREAM | PCIIO_DMA_CMD);
		if (dma_handle) {
			return (ret);
		} else {
			printk("sn1_pci_alloc_consistent: 32Bits DMA Page Map support not available yet!");
			BUG();
		}
	}
	if (IS_PCI32L(hwdev)) {
		return (NULL);
	}
        return NULL;
}
void * sn1_pci_alloc_consistent ( struct pci_dev * hwdev , size_t size , dma_addr_t * dma_handle ) { void * ret ; int gfp = GFP_ATOMIC ; devfs_handle_t vhdl ; struct sn1_device_sysdata * device_sysdata ; paddr_t temp_ptr ; * dma_handle = ( dma_addr_t ) NULL ; device_sysdata = ( struct sn1_device_sysdata * ) hwdev -> sysdata ; vhdl = device_sysdata -> vhdl ; if ( ret = ( void * ) __get_free_pages ( gfp , get_order ( size ) ) ) { memset ( ret , 0 , size ) ; } else { return ( NULL ) ; } temp_ptr = ( paddr_t ) __pa ( ret ) ; if ( IS_PCIA64 ( hwdev ) ) { * dma_handle = pciio_dmatrans_addr ( vhdl , NULL , temp_ptr , size , PCIBR_BARRIER | PCIIO_BYTE_STREAM | PCIIO_DMA_CMD | PCIIO_DMA_A64 ) ; return ( ret ) ; } if ( IS_PCI32G ( hwdev ) ) { * dma_handle = pciio_dmatrans_addr ( vhdl , NULL , temp_ptr , size , PCIBR_BARRIER | PCIIO_BYTE_STREAM | PCIIO_DMA_CMD ) ; if ( dma_handle ) { return ( ret ) ; } else { printk ( " " ) ; BUG ( ) ; } } if ( IS_PCI32L ( hwdev ) ) { return ( NULL ) ; } return NULL ; }
sn1 platform specific pci_alloc_consistent()
 this interface is meant for "command" streams, i.e.
sn1 platform specific pci_alloc_consistent () this interface is meant for " command " streams i . e .
/*
	 * get vertex for the device
	 */ /*
		 * This device supports 64bits DMA addresses.
		 */ /*
	 * Devices that supports 32 Bits upto 63 Bits DMA Address gets
	 * 32 Bits DMA addresses.
	 *
	 * First try to get 32 Bit Direct Map Support.
	 */ /*
			 * We need to map this request by using ATEs.
			 */ /*
		 * SNIA64 cannot support DMA Addresses smaller than 32 bits.
		 */