FreeBSD/sys/dev/isci/scil/scic_sds_controller.c
/**
 * This method is the SCIC_SDS_CONTROLLER initialize handler for the reset
 * state.
 *    - Currently this function does nothing
 *
 * @param[in] controller This is the SCI_BASE_CONTROLLER object which is cast
 *       into a SCIC_SDS_CONTROLLER object.
 *
 * @return SCI_STATUS
 * @retval SCI_FAILURE
 *
 * @todo This function is not yet implemented and is a valid request from the
 *       reset state.
 */
This method is the SCIC_SDS_CONTROLLER initialize handler for the reset
state.
- Currently this function does nothing

@param[in] controller This is the SCI_BASE_CONTROLLER object which is cast
into a SCIC_SDS_CONTROLLER object.



@todo This function is not yet implemented and is a valid request from the
reset state.
This method is the SCIC_SDS_CONTROLLER initialize handler for the reset state . - Currently this function does nothing @param [ in ] controller This is the SCI_BASE_CONTROLLER object which is cast into a SCIC_SDS_CONTROLLER object . @todo This function is not yet implemented and is a valid request from the reset state .
static
SCI_STATUS scic_sds_controller_reset_state_initialize_handler(
   SCI_BASE_CONTROLLER_T *controller
)
{
   U32 index;
   SCI_STATUS result = SCI_SUCCESS;
   SCIC_SDS_CONTROLLER_T *this_controller;
   this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
   SCIC_LOG_TRACE((
      sci_base_object_get_logger(controller),
      SCIC_LOG_OBJECT_CONTROLLER | SCIC_LOG_OBJECT_INITIALIZATION,
      "scic_sds_controller_reset_state_initialize_handler(0x%x) enter\n",
      controller
   ));
   sci_base_state_machine_change_state(
      scic_sds_controller_get_base_state_machine(this_controller),
      SCI_BASE_CONTROLLER_STATE_INITIALIZING
   );
   this_controller->timeout_timer = scic_cb_timer_create(
      controller,
      scic_sds_controller_timeout_handler,
      controller
   );
   scic_sds_controller_initialize_power_control(this_controller);
   scic_sds_controller_reset_hardware(this_controller);
#if defined(ARLINGTON_BUILD)
   scic_sds_controller_lex_atux_initialization(this_controller);
#elif    defined(PLEASANT_RIDGE_BUILD) \
      || defined(PBG_HBA_A0_BUILD) \
      || defined(PBG_HBA_A2_BUILD)
   scic_sds_controller_afe_initialization(this_controller);
#elif defined(PBG_HBA_BETA_BUILD) || defined(PBG_BUILD)
   scic_sds_controller_afe_initialization(this_controller);
#else  
#endif 
   if (SCI_SUCCESS == result)
   {
      U32 status;
      U32 terminate_loop;
      SMU_SMUSRCR_WRITE(this_controller, 0x00000000);
      result = SCI_FAILURE;
      terminate_loop = 100;
      while (terminate_loop-- && (result != SCI_SUCCESS))
      {
         scic_cb_stall_execution(SCU_CONTEXT_RAM_INIT_STALL_TIME);
         status = SMU_SMUCSR_READ(this_controller);
         if ((status & SCU_RAM_INIT_COMPLETED) == SCU_RAM_INIT_COMPLETED)
         {
            result = SCI_SUCCESS;
         }
      }
   }
#ifdef ARLINGTON_BUILD
   scic_sds_controller_enable_chipwatch(this_controller);
#endif
   if (result == SCI_SUCCESS)
   {
      U32 max_supported_ports;
      U32 max_supported_devices;
      U32 max_supported_io_requests;
      U32 device_context_capacity;
      device_context_capacity = SMU_DCC_READ(this_controller);
      max_supported_ports =
         smu_dcc_get_max_ports(device_context_capacity);
      max_supported_devices =
         smu_dcc_get_max_remote_node_context(device_context_capacity);
      max_supported_io_requests =
         smu_dcc_get_max_task_context(device_context_capacity);
      for (index = 0; index < max_supported_ports; index++)
      {
         scu_register_write(
            this_controller,
            this_controller->scu_registers->peg0.ptsg.protocol_engine[index],
            index
         );
      }
      scic_controller_set_mode(this_controller, SCI_MODE_SPEED);
      this_controller->logical_port_entries =
         MIN(max_supported_ports, this_controller->logical_port_entries);
      this_controller->task_context_entries =
         MIN(max_supported_io_requests, this_controller->task_context_entries);
      this_controller->remote_node_entries =
         MIN(max_supported_devices, this_controller->remote_node_entries);
   }
   if (result == SCI_SUCCESS)
   {
      U32 dma_configuration;
      dma_configuration = SCU_PDMACR_READ(this_controller);
      dma_configuration |= SCU_PDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
      SCU_PDMACR_WRITE(this_controller, dma_configuration);
      dma_configuration = SCU_CDMACR_READ(this_controller);
      dma_configuration |= SCU_CDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
      SCU_CDMACR_WRITE(this_controller, dma_configuration);
   }
   if (result == SCI_SUCCESS)
   {
      for (index = 0;
           (result == SCI_SUCCESS) && (index < SCI_MAX_PHYS);
           index++)
      {
         result = scic_sds_phy_initialize(
            &this_controller->phy_table[index],
            &this_controller->scu_registers->peg0.pe[index].tl,
            &this_controller->scu_registers->peg0.pe[index].ll
         );
      }
   }
   if(result == SCI_SUCCESS)
   {
      scic_sgpio_hardware_initialize(this_controller);
   }
   if (result == SCI_SUCCESS)
   {
      for (index = 0;
              (index < this_controller->logical_port_entries)
           && (result == SCI_SUCCESS);
           index++)
      {
         result = scic_sds_port_initialize(
            &this_controller->port_table[index],
            &this_controller->scu_registers->peg0.ptsg.port[index],
            &this_controller->scu_registers->peg0.ptsg.protocol_engine,
            &this_controller->scu_registers->peg0.viit[index]
         );
      }
   }
   if (SCI_SUCCESS == result)
   {
      result = scic_sds_port_configuration_agent_initialize(
                  this_controller,
                  &this_controller->port_agent
               );
   }
   if (result == SCI_SUCCESS)
   {
      sci_base_state_machine_change_state(
         scic_sds_controller_get_base_state_machine(this_controller),
         SCI_BASE_CONTROLLER_STATE_INITIALIZED
      );
   }
   else
   {
      scic_sds_controller_release_resource(this_controller);
      SCIC_LOG_TRACE((
         sci_base_object_get_logger(controller),
         SCIC_LOG_OBJECT_CONTROLLER | SCIC_LOG_OBJECT_INITIALIZATION,
         "Invalid Port Configuration from scic_sds_controller_reset_state_initialize_handler(0x%x) \n",
         controller
      ));
   }
   return result;
}
static SCI_STATUS scic_sds_controller_reset_state_initialize_handler ( SCI_BASE_CONTROLLER_T * controller ) { U32 index ; SCI_STATUS result = SCI_SUCCESS ; SCIC_SDS_CONTROLLER_T * this_controller ; this_controller = ( SCIC_SDS_CONTROLLER_T * ) controller ; SCIC_LOG_TRACE ( ( sci_base_object_get_logger ( controller ) , SCIC_LOG_OBJECT_CONTROLLER | SCIC_LOG_OBJECT_INITIALIZATION , " \n " , controller ) ) ; sci_base_state_machine_change_state ( scic_sds_controller_get_base_state_machine ( this_controller ) , SCI_BASE_CONTROLLER_STATE_INITIALIZING ) ; this_controller -> timeout_timer = scic_cb_timer_create ( controller , scic_sds_controller_timeout_handler , controller ) ; scic_sds_controller_initialize_power_control ( this_controller ) ; scic_sds_controller_reset_hardware ( this_controller ) ; #if defined ( ARLINGTON_BUILD ) scic_sds_controller_lex_atux_initialization ( this_controller ) ; #elif defined ( PLEASANT_RIDGE_BUILD ) || defined ( PBG_HBA_A0_BUILD ) || defined ( PBG_HBA_A2_BUILD ) scic_sds_controller_afe_initialization ( this_controller ) ; #elif defined ( PBG_HBA_BETA_BUILD ) || defined ( PBG_BUILD ) scic_sds_controller_afe_initialization ( this_controller ) ; #else #endif if ( SCI_SUCCESS == result ) { U32 status ; U32 terminate_loop ; SMU_SMUSRCR_WRITE ( this_controller , 0x00000000 ) ; result = SCI_FAILURE ; terminate_loop = 100 ; while ( terminate_loop -- && ( result != SCI_SUCCESS ) ) { scic_cb_stall_execution ( SCU_CONTEXT_RAM_INIT_STALL_TIME ) ; status = SMU_SMUCSR_READ ( this_controller ) ; if ( ( status & SCU_RAM_INIT_COMPLETED ) == SCU_RAM_INIT_COMPLETED ) { result = SCI_SUCCESS ; } } } #ifdef ARLINGTON_BUILD scic_sds_controller_enable_chipwatch ( this_controller ) ; #endif if ( result == SCI_SUCCESS ) { U32 max_supported_ports ; U32 max_supported_devices ; U32 max_supported_io_requests ; U32 device_context_capacity ; device_context_capacity = SMU_DCC_READ ( this_controller ) ; max_supported_ports = smu_dcc_get_max_ports ( device_context_capacity ) ; max_supported_devices = smu_dcc_get_max_remote_node_context ( device_context_capacity ) ; max_supported_io_requests = smu_dcc_get_max_task_context ( device_context_capacity ) ; for ( index = 0 ; index < max_supported_ports ; index ++ ) { scu_register_write ( this_controller , this_controller -> scu_registers -> peg0 . ptsg . protocol_engine [ index ] , index ) ; } scic_controller_set_mode ( this_controller , SCI_MODE_SPEED ) ; this_controller -> logical_port_entries = MIN ( max_supported_ports , this_controller -> logical_port_entries ) ; this_controller -> task_context_entries = MIN ( max_supported_io_requests , this_controller -> task_context_entries ) ; this_controller -> remote_node_entries = MIN ( max_supported_devices , this_controller -> remote_node_entries ) ; } if ( result == SCI_SUCCESS ) { U32 dma_configuration ; dma_configuration = SCU_PDMACR_READ ( this_controller ) ; dma_configuration |= SCU_PDMACR_GEN_BIT ( PCI_RELAXED_ORDERING_ENABLE ) ; SCU_PDMACR_WRITE ( this_controller , dma_configuration ) ; dma_configuration = SCU_CDMACR_READ ( this_controller ) ; dma_configuration |= SCU_CDMACR_GEN_BIT ( PCI_RELAXED_ORDERING_ENABLE ) ; SCU_CDMACR_WRITE ( this_controller , dma_configuration ) ; } if ( result == SCI_SUCCESS ) { for ( index = 0 ; ( result == SCI_SUCCESS ) && ( index < SCI_MAX_PHYS ) ; index ++ ) { result = scic_sds_phy_initialize ( & this_controller -> phy_table [ index ] , & this_controller -> scu_registers -> peg0 . pe [ index ] . tl , & this_controller -> scu_registers -> peg0 . pe [ index ] . ll ) ; } } if ( result == SCI_SUCCESS ) { scic_sgpio_hardware_initialize ( this_controller ) ; } if ( result == SCI_SUCCESS ) { for ( index = 0 ; ( index < this_controller -> logical_port_entries ) && ( result == SCI_SUCCESS ) ; index ++ ) { result = scic_sds_port_initialize ( & this_controller -> port_table [ index ] , & this_controller -> scu_registers -> peg0 . ptsg . port [ index ] , & this_controller -> scu_registers -> peg0 . ptsg . protocol_engine , & this_controller -> scu_registers -> peg0 . viit [ index ] ) ; } } if ( SCI_SUCCESS == result ) { result = scic_sds_port_configuration_agent_initialize ( this_controller , & this_controller -> port_agent ) ; } if ( result == SCI_SUCCESS ) { sci_base_state_machine_change_state ( scic_sds_controller_get_base_state_machine ( this_controller ) , SCI_BASE_CONTROLLER_STATE_INITIALIZED ) ; } else { scic_sds_controller_release_resource ( this_controller ) ; SCIC_LOG_TRACE ( ( sci_base_object_get_logger ( controller ) , SCIC_LOG_OBJECT_CONTROLLER | SCIC_LOG_OBJECT_INITIALIZATION , " \n " , controller ) ) ; } return result ; }
This method is the SCIC_SDS_CONTROLLER initialize handler for the reset
 state.
This method is the SCIC_SDS_CONTROLLER initialize handler for the reset state .
/// todo: This should really be done in the reset state enter but ///       the controller has not yet been initialized before getting ///       to the reset enter state so the PCI BAR is not yet assigned // There is nothing to do here for B0 since we do not have to // program the AFE registers. /// @todo The AFE settings are supposed to be correct for the B0 but ///       presently they seem to be wrong. // !defined(ARLINGTON_BUILD) && !defined(PLEASANT_RIDGE_BUILD) // What other systems do we want to add here? // !defined(ARLINGTON_BUILD) && !defined(PLEASANT_RIDGE_BUILD) // Take the hardware out of reset /// @todo Provide meaningfull error code for hardware failure //result = SCI_FAILURE_CONTROLLER_HARDWARE; // Loop until the hardware reports success // Determine what are the actaul device capacities that the // hardware will support // Make all PEs that are unassigned match up with the logical ports // Now that we have the correct hardware reported minimum values // build the MDL for the controller.  Default to a performance // configuration. // Record the smaller of the two capacity values // Initialize hardware PCI Relaxed ordering in DMA engines // Configure the payload DMA // Configure the control DMA // Initialize the PHYs before the PORTs because the PHY registers // are accessed during the port initialization. // Initialize the phys //Initialize the SGPIO Unit for HARDWARE controlled SGPIO // Initialize the logical ports // Advance the controller state machine //stay in the same state and release the resource