drivers/arm/gic/arm_gic.c
/*******************************************************************************
 * Global gic distributor setup which will be done by the primary cpu after a
 * cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It
 * then enables the secure GIC distributor interface.
 ******************************************************************************/
Global gic distributor setup which will be done by the primary cpu after a
cold boot. It marks out the secure SPIs, PPIs & SGIs and enables them. It
then enables the secure GIC distributor interface.
Global gic distributor setup which will be done by the primary cpu after a cold boot . It marks out the secure SPIs PPIs & SGIs and enables them . It then enables the secure GIC distributor interface .
static void arm_gic_distif_setup(void)
{
	unsigned int num_ints, ctlr, index, irq_num;
	uint8_t target_cpu;
	assert(g_gicd_base);
	ctlr = gicd_read_ctlr(g_gicd_base);
	ctlr &= ~(ENABLE_GRP0 | ENABLE_GRP1);
	gicd_write_ctlr(g_gicd_base, ctlr);
	num_ints = gicd_read_typer(g_gicd_base) & IT_LINES_NO_MASK;
	num_ints = (num_ints + 1) << 5;
	for (index = MIN_SPI_ID; index < num_ints; index += 32)
		gicd_write_igroupr(g_gicd_base, index, ~0);
	for (index = MIN_SPI_ID; index < num_ints; index += 4) {
		gicd_write_ipriorityr(g_gicd_base, index,
				GICD_IPRIORITYR_DEF_VAL);
	}
	target_cpu = arm_gic_get_cpuif_id();
	assert(g_irq_sec_ptr);
	for (index = 0; index < g_num_irqs; index++) {
		irq_num = g_irq_sec_ptr[index];
		if (irq_num >= MIN_SPI_ID) {
			gicd_clr_igroupr(g_gicd_base, irq_num);
			gicd_set_ipriorityr(g_gicd_base, irq_num,
				GIC_HIGHEST_SEC_PRIORITY);
			gicd_set_itargetsr(g_gicd_base, irq_num, target_cpu);
			gicd_set_isenabler(g_gicd_base, irq_num);
		}
	}
	arm_gic_pcpu_distif_setup();
	gicd_write_ctlr(g_gicd_base, ctlr | ENABLE_GRP0);
}
static void arm_gic_distif_setup ( void ) { unsigned int num_ints , ctlr , index , irq_num ; uint8_t target_cpu ; assert ( g_gicd_base ) ; ctlr = gicd_read_ctlr ( g_gicd_base ) ; ctlr &= ~ ( ENABLE_GRP0 | ENABLE_GRP1 ) ; gicd_write_ctlr ( g_gicd_base , ctlr ) ; num_ints = gicd_read_typer ( g_gicd_base ) & IT_LINES_NO_MASK ; num_ints = ( num_ints + 1 ) << 5 ; for ( index = MIN_SPI_ID ; index < num_ints ; index += 32 ) gicd_write_igroupr ( g_gicd_base , index , ~ 0 ) ; for ( index = MIN_SPI_ID ; index < num_ints ; index += 4 ) { gicd_write_ipriorityr ( g_gicd_base , index , GICD_IPRIORITYR_DEF_VAL ) ; } target_cpu = arm_gic_get_cpuif_id ( ) ; assert ( g_irq_sec_ptr ) ; for ( index = 0 ; index < g_num_irqs ; index ++ ) { irq_num = g_irq_sec_ptr [ index ] ; if ( irq_num >= MIN_SPI_ID ) { gicd_clr_igroupr ( g_gicd_base , irq_num ) ; gicd_set_ipriorityr ( g_gicd_base , irq_num , GIC_HIGHEST_SEC_PRIORITY ) ; gicd_set_itargetsr ( g_gicd_base , irq_num , target_cpu ) ; gicd_set_isenabler ( g_gicd_base , irq_num ) ; } } arm_gic_pcpu_distif_setup ( ) ; gicd_write_ctlr ( g_gicd_base , ctlr | ENABLE_GRP0 ) ; }
Global gic distributor setup which will be done by the primary cpu after a
 cold boot.
Global gic distributor setup which will be done by the primary cpu after a cold boot .
/* Disable the distributor before going further */ /*
	 * Mark out non-secure SPI interrupts. The number of interrupts is
	 * calculated as 32 * (IT_LINES + 1). We do 32 at a time.
	 */ /* Setup SPI priorities doing four at a time */ /* Read the target CPU mask */ /* Configure SPI secure interrupts now */ /* We have an SPI */ /*
	 * Configure the SGI and PPI. This is done in a separated function
	 * because each CPU is responsible for initializing its own private
	 * interrupts.
	 */