boards/library/bsp/stm32f10xfwlib/src/stm32f10x_rcc.c
/**
  * @brief  Returns the frequencies of different on chip clocks.
  * @param  RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
  *         the clocks frequencies.
  * @note   The result of this function could be not correct when using 
  *         fractional value for HSE crystal.  
  * @retval None
  */
@brief  Returns the frequencies of different on chip clocks.
@param  RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
the clocks frequencies.
@note   The result of this function could be not correct when using
fractional value for HSE crystal.
@retval None
@brief Returns the frequencies of different on chip clocks . @param RCC_Clocks : pointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies . @note The result of this function could be not correct when using fractional value for HSE crystal . @retval None
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
{
  uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
#ifdef  STM32F10X_CL
  uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
#endif 
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
  uint32_t prediv1factor = 0;
#endif
  tmp = RCC->CFGR & CFGR_SWS_Mask;
  switch (tmp)
  {
    case 0x00:  
      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
      break;
    case 0x04:  
      RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
      break;
    case 0x08:  
      pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
      pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
#ifndef STM32F10X_CL      
      pllmull = ( pllmull >> 18) + 2;
      if (pllsource == 0x00)
      {
        RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
      }
      else
      {
 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
       prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
       RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull; 
 #else
        if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
        {
          RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
        }
        else
        {
          RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
        }
 #endif
      }
#else
      pllmull = pllmull >> 18;
      if (pllmull != 0x0D)
      {
         pllmull += 2;
      }
      else
      { 
        pllmull = 13 / 2; 
      }
      if (pllsource == 0x00)
      {
        RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
      }
      else
      {
        prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC;
        prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
        if (prediv1source == 0)
        { 
          RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull;          
        }
        else
        {
          prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;
          pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2; 
          RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;                         
        }
      }
#endif  
      break;
    default:
      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
      break;
  }
  tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
  tmp = tmp >> 4;
  presc = APBAHBPrescTable[tmp];
  RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
  tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
  tmp = tmp >> 8;
  presc = APBAHBPrescTable[tmp];
  RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
  tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
  tmp = tmp >> 11;
  presc = APBAHBPrescTable[tmp];
  RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
  tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
  tmp = tmp >> 14;
  presc = ADCPrescTable[tmp];
  RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
}
void RCC_GetClocksFreq ( RCC_ClocksTypeDef * RCC_Clocks ) { uint32_t tmp = 0 , pllmull = 0 , pllsource = 0 , presc = 0 ; #ifdef STM32F10X_CL uint32_t prediv1source = 0 , prediv1factor = 0 , prediv2factor = 0 , pll2mull = 0 ; #endif #if defined ( STM32F10X_LD_VL ) || defined ( STM32F10X_MD_VL ) || defined ( STM32F10X_HD_VL ) uint32_t prediv1factor = 0 ; #endif tmp = RCC -> CFGR & CFGR_SWS_Mask ; switch ( tmp ) { case 0x00 : RCC_Clocks -> SYSCLK_Frequency = HSI_VALUE ; break ; case 0x04 : RCC_Clocks -> SYSCLK_Frequency = HSE_VALUE ; break ; case 0x08 : pllmull = RCC -> CFGR & CFGR_PLLMull_Mask ; pllsource = RCC -> CFGR & CFGR_PLLSRC_Mask ; #ifndef STM32F10X_CL pllmull = ( pllmull >> 18 ) + 2 ; if ( pllsource == 0x00 ) { RCC_Clocks -> SYSCLK_Frequency = ( HSI_VALUE >> 1 ) * pllmull ; } else { #if defined ( STM32F10X_LD_VL ) || defined ( STM32F10X_MD_VL ) || defined ( STM32F10X_HD_VL ) prediv1factor = ( RCC -> CFGR2 & CFGR2_PREDIV1 ) + 1 ; RCC_Clocks -> SYSCLK_Frequency = ( HSE_VALUE / prediv1factor ) * pllmull ; #else if ( ( RCC -> CFGR & CFGR_PLLXTPRE_Mask ) != ( uint32_t ) RESET ) { RCC_Clocks -> SYSCLK_Frequency = ( HSE_VALUE >> 1 ) * pllmull ; } else { RCC_Clocks -> SYSCLK_Frequency = HSE_VALUE * pllmull ; } #endif } #else pllmull = pllmull >> 18 ; if ( pllmull != 0x0D ) { pllmull += 2 ; } else { pllmull = 13 / 2 ; } if ( pllsource == 0x00 ) { RCC_Clocks -> SYSCLK_Frequency = ( HSI_VALUE >> 1 ) * pllmull ; } else { prediv1source = RCC -> CFGR2 & CFGR2_PREDIV1SRC ; prediv1factor = ( RCC -> CFGR2 & CFGR2_PREDIV1 ) + 1 ; if ( prediv1source == 0 ) { RCC_Clocks -> SYSCLK_Frequency = ( HSE_VALUE / prediv1factor ) * pllmull ; } else { prediv2factor = ( ( RCC -> CFGR2 & CFGR2_PREDIV2 ) >> 4 ) + 1 ; pll2mull = ( ( RCC -> CFGR2 & CFGR2_PLL2MUL ) >> 8 ) + 2 ; RCC_Clocks -> SYSCLK_Frequency = ( ( ( HSE_VALUE / prediv2factor ) * pll2mull ) / prediv1factor ) * pllmull ; } } #endif break ; default : RCC_Clocks -> SYSCLK_Frequency = HSI_VALUE ; break ; } tmp = RCC -> CFGR & CFGR_HPRE_Set_Mask ; tmp = tmp >> 4 ; presc = APBAHBPrescTable [ tmp ] ; RCC_Clocks -> HCLK_Frequency = RCC_Clocks -> SYSCLK_Frequency >> presc ; tmp = RCC -> CFGR & CFGR_PPRE1_Set_Mask ; tmp = tmp >> 8 ; presc = APBAHBPrescTable [ tmp ] ; RCC_Clocks -> PCLK1_Frequency = RCC_Clocks -> HCLK_Frequency >> presc ; tmp = RCC -> CFGR & CFGR_PPRE2_Set_Mask ; tmp = tmp >> 11 ; presc = APBAHBPrescTable [ tmp ] ; RCC_Clocks -> PCLK2_Frequency = RCC_Clocks -> HCLK_Frequency >> presc ; tmp = RCC -> CFGR & CFGR_ADCPRE_Set_Mask ; tmp = tmp >> 14 ; presc = ADCPrescTable [ tmp ] ; RCC_Clocks -> ADCCLK_Frequency = RCC_Clocks -> PCLK2_Frequency / presc ; }
@brief  Returns the frequencies of different on chip clocks.
@brief Returns the frequencies of different on chip clocks .
/* STM32F10X_CL */ /* Get SYSCLK source -------------------------------------------------------*/ /* HSI used as system clock */ /* HSE used as system clock */ /* PLL used as system clock */ /* Get PLL clock source and multiplication factor ----------------------*/ /* HSI oscillator clock divided by 2 selected as PLL clock entry */ /* HSE oscillator clock selected as PREDIV1 clock entry */ /* HSE selected as PLL clock entry */ /* HSE oscillator clock divided by 2 */ /* PLL multiplication factor = PLL input clock * 6.5 */ /* HSI oscillator clock divided by 2 selected as PLL clock entry */ /* PREDIV1 selected as PLL clock entry */ /* Get PREDIV1 clock source and division factor */ /* HSE oscillator clock selected as PREDIV1 clock entry */ /* PLL2 clock selected as PREDIV1 clock entry */ /* Get PREDIV2 division factor and PLL2 multiplication factor */ /* STM32F10X_CL */ /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/ /* Get HCLK prescaler */ /* HCLK clock frequency */ /* Get PCLK1 prescaler */ /* PCLK1 clock frequency */ /* Get PCLK2 prescaler */ /* PCLK2 clock frequency */ /* Get ADCCLK prescaler */ /* ADCCLK clock frequency */