FreeBSD/sys/dev/rt/if_rt.c
/*
 * rt_init_locked - Run initialization process having locked mtx.
 */
Run initialization process having locked mtx.
Run initialization process having locked mtx .
static void
rt_init_locked(void *priv)
{
	struct rt_softc *sc;
	struct ifnet *ifp;
#ifdef IF_RT_PHY_SUPPORT
	struct mii_data *mii;
#endif
	int i, ntries;
	uint32_t tmp;
	sc = priv;
	ifp = sc->ifp;
#ifdef IF_RT_PHY_SUPPORT
	mii = device_get_softc(sc->rt_miibus);
#endif
	RT_DPRINTF(sc, RT_DEBUG_ANY, "initializing\n");
	RT_SOFTC_ASSERT_LOCKED(sc);
	if(sc->rt_chipid == RT_CHIPID_RT3050)
	  RT_WRITE(sc, GDMA1_BASE + GDMA_FWD_CFG,
	    (
	    GDM_ICS_EN | 
	    GDM_TCS_EN | 
	    GDM_UCS_EN | 
	    GDM_STRPCRC | 
	    GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | 
	    GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | 
	    GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | 
	    GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT   
	    ));
	RT_WRITE(sc, sc->pdma_glo_cfg, 0);
	RT_WRITE(sc, sc->pdma_rst_idx, 0xffffffff);
	for (ntries = 0; ntries < 100; ntries++) {
		tmp = RT_READ(sc, sc->pdma_glo_cfg);
		if (!(tmp & (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)))
			break;
		DELAY(1000);
	}
	if (ntries == 100) {
		device_printf(sc->dev, "timeout waiting for DMA engine\n");
		goto fail;
	}
	tmp = FE_RST_DRX_IDX0 |
		FE_RST_DTX_IDX3 |
		FE_RST_DTX_IDX2 |
		FE_RST_DTX_IDX1 |
		FE_RST_DTX_IDX0;
	RT_WRITE(sc, sc->pdma_rst_idx, tmp);
	for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++)
		rt_reset_tx_ring(sc, &sc->tx_ring[i]);
	for (i = 0; i < RT_SOFTC_TX_RING_COUNT; i++) {
		RT_WRITE(sc, sc->tx_base_ptr[i],
			sc->tx_ring[i].desc_phys_addr);
		RT_WRITE(sc, sc->tx_max_cnt[i],
			RT_SOFTC_TX_RING_DESC_COUNT);
		RT_WRITE(sc, sc->tx_ctx_idx[i], 0);
	}
	for (i = 0; i < sc->rx_ring_count; i++)
		rt_reset_rx_ring(sc, &sc->rx_ring[i]);
	for (i = 0; i < sc->rx_ring_count; i++) {
		RT_WRITE(sc, sc->rx_base_ptr[i],
			sc->rx_ring[i].desc_phys_addr);
		RT_WRITE(sc, sc->rx_max_cnt[i],
			RT_SOFTC_RX_RING_DATA_COUNT);
		RT_WRITE(sc, sc->rx_calc_idx[i],
			RT_SOFTC_RX_RING_DATA_COUNT - 1);
	}
	tmp = FE_TX_WB_DDONE | FE_DMA_BT_SIZE16 | FE_RX_DMA_EN | FE_TX_DMA_EN;
	if (sc->rt_chipid == RT_CHIPID_MT7620 ||
	    sc->rt_chipid == RT_CHIPID_MT7621)
		tmp |= (1<<31);
	RT_WRITE(sc, sc->pdma_glo_cfg, tmp);
	RT_WRITE(sc, sc->delay_int_cfg, 0);
	RT_WRITE(sc, sc->fe_int_status, 0xffffffff);
	if (sc->rt_chipid == RT_CHIPID_RT5350 ||
	    sc->rt_chipid == RT_CHIPID_MT7620 ||
	    sc->rt_chipid == RT_CHIPID_MT7621)
	  tmp = RT5350_INT_TX_COHERENT |
	  	RT5350_INT_RX_COHERENT |
	  	RT5350_INT_TXQ3_DONE |
	  	RT5350_INT_TXQ2_DONE |
	  	RT5350_INT_TXQ1_DONE |
	  	RT5350_INT_TXQ0_DONE |
	  	RT5350_INT_RXQ1_DONE |
	  	RT5350_INT_RXQ0_DONE;
	else
	  tmp = CNT_PPE_AF |
		CNT_GDM_AF |
		PSE_P2_FC |
		GDM_CRC_DROP |
		PSE_BUF_DROP |
		GDM_OTHER_DROP |
		PSE_P1_FC |
		PSE_P0_FC |
		PSE_FQ_EMPTY |
		INT_TX_COHERENT |
		INT_RX_COHERENT |
		INT_TXQ3_DONE |
		INT_TXQ2_DONE |
		INT_TXQ1_DONE |
		INT_TXQ0_DONE |
		INT_RX_DONE;
	sc->intr_enable_mask = tmp;
	RT_WRITE(sc, sc->fe_int_enable, tmp);
	if (rt_txrx_enable(sc) != 0)
		goto fail;
#ifdef IF_RT_PHY_SUPPORT
	if (mii) mii_mediachg(mii);
#endif 
	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
	ifp->if_drv_flags |= IFF_DRV_RUNNING;
	sc->periodic_round = 0;
	callout_reset(&sc->periodic_ch, hz / 10, rt_periodic, sc);
	return;
fail:
	rt_stop_locked(sc);
}
static void rt_init_locked ( void * priv ) { struct rt_softc * sc ; struct ifnet * ifp ; #ifdef IF_RT_PHY_SUPPORT struct mii_data * mii ; #endif int i , ntries ; uint32_t tmp ; sc = priv ; ifp = sc -> ifp ; #ifdef IF_RT_PHY_SUPPORT mii = device_get_softc ( sc -> rt_miibus ) ; #endif RT_DPRINTF ( sc , RT_DEBUG_ANY , " \n " ) ; RT_SOFTC_ASSERT_LOCKED ( sc ) ; if ( sc -> rt_chipid == RT_CHIPID_RT3050 ) RT_WRITE ( sc , GDMA1_BASE + GDMA_FWD_CFG , ( GDM_ICS_EN | GDM_TCS_EN | GDM_UCS_EN | GDM_STRPCRC | GDM_DST_PORT_CPU << GDM_UFRC_P_SHIFT | GDM_DST_PORT_CPU << GDM_BFRC_P_SHIFT | GDM_DST_PORT_CPU << GDM_MFRC_P_SHIFT | GDM_DST_PORT_CPU << GDM_OFRC_P_SHIFT ) ) ; RT_WRITE ( sc , sc -> pdma_glo_cfg , 0 ) ; RT_WRITE ( sc , sc -> pdma_rst_idx , 0xffffffff ) ; for ( ntries = 0 ; ntries < 100 ; ntries ++ ) { tmp = RT_READ ( sc , sc -> pdma_glo_cfg ) ; if ( ! ( tmp & ( FE_TX_DMA_BUSY | FE_RX_DMA_BUSY ) ) ) break ; DELAY ( 1000 ) ; } if ( ntries == 100 ) { device_printf ( sc -> dev , " \n " ) ; goto fail ; } tmp = FE_RST_DRX_IDX0 | FE_RST_DTX_IDX3 | FE_RST_DTX_IDX2 | FE_RST_DTX_IDX1 | FE_RST_DTX_IDX0 ; RT_WRITE ( sc , sc -> pdma_rst_idx , tmp ) ; for ( i = 0 ; i < RT_SOFTC_TX_RING_COUNT ; i ++ ) rt_reset_tx_ring ( sc , & sc -> tx_ring [ i ] ) ; for ( i = 0 ; i < RT_SOFTC_TX_RING_COUNT ; i ++ ) { RT_WRITE ( sc , sc -> tx_base_ptr [ i ] , sc -> tx_ring [ i ] . desc_phys_addr ) ; RT_WRITE ( sc , sc -> tx_max_cnt [ i ] , RT_SOFTC_TX_RING_DESC_COUNT ) ; RT_WRITE ( sc , sc -> tx_ctx_idx [ i ] , 0 ) ; } for ( i = 0 ; i < sc -> rx_ring_count ; i ++ ) rt_reset_rx_ring ( sc , & sc -> rx_ring [ i ] ) ; for ( i = 0 ; i < sc -> rx_ring_count ; i ++ ) { RT_WRITE ( sc , sc -> rx_base_ptr [ i ] , sc -> rx_ring [ i ] . desc_phys_addr ) ; RT_WRITE ( sc , sc -> rx_max_cnt [ i ] , RT_SOFTC_RX_RING_DATA_COUNT ) ; RT_WRITE ( sc , sc -> rx_calc_idx [ i ] , RT_SOFTC_RX_RING_DATA_COUNT - 1 ) ; } tmp = FE_TX_WB_DDONE | FE_DMA_BT_SIZE16 | FE_RX_DMA_EN | FE_TX_DMA_EN ; if ( sc -> rt_chipid == RT_CHIPID_MT7620 || sc -> rt_chipid == RT_CHIPID_MT7621 ) tmp |= ( 1 << 31 ) ; RT_WRITE ( sc , sc -> pdma_glo_cfg , tmp ) ; RT_WRITE ( sc , sc -> delay_int_cfg , 0 ) ; RT_WRITE ( sc , sc -> fe_int_status , 0xffffffff ) ; if ( sc -> rt_chipid == RT_CHIPID_RT5350 || sc -> rt_chipid == RT_CHIPID_MT7620 || sc -> rt_chipid == RT_CHIPID_MT7621 ) tmp = RT5350_INT_TX_COHERENT | RT5350_INT_RX_COHERENT | RT5350_INT_TXQ3_DONE | RT5350_INT_TXQ2_DONE | RT5350_INT_TXQ1_DONE | RT5350_INT_TXQ0_DONE | RT5350_INT_RXQ1_DONE | RT5350_INT_RXQ0_DONE ; else tmp = CNT_PPE_AF | CNT_GDM_AF | PSE_P2_FC | GDM_CRC_DROP | PSE_BUF_DROP | GDM_OTHER_DROP | PSE_P1_FC | PSE_P0_FC | PSE_FQ_EMPTY | INT_TX_COHERENT | INT_RX_COHERENT | INT_TXQ3_DONE | INT_TXQ2_DONE | INT_TXQ1_DONE | INT_TXQ0_DONE | INT_RX_DONE ; sc -> intr_enable_mask = tmp ; RT_WRITE ( sc , sc -> fe_int_enable , tmp ) ; if ( rt_txrx_enable ( sc ) != 0 ) goto fail ; #ifdef IF_RT_PHY_SUPPORT if ( mii ) mii_mediachg ( mii ) ; #endif ifp -> if_drv_flags &= ~ IFF_DRV_OACTIVE ; ifp -> if_drv_flags |= IFF_DRV_RUNNING ; sc -> periodic_round = 0 ; callout_reset ( & sc -> periodic_ch , hz / 10 , rt_periodic , sc ) ; return ; fail : rt_stop_locked ( sc ) ; }
rt_init_locked - Run initialization process having locked mtx.
rt_init_locked - Run initialization process having locked mtx .
/* hardware reset */ //RT_WRITE(sc, GE_PORT_BASE + FE_RST_GLO, PSE_RESET); //rt305x_sysctl_set(SYSCTL_RSTCTRL, SYSCTL_RSTCTRL_FRENG); /* Fwd to CPU (uni|broad|multi)cast and Unknown */ /* Enable IP Csum */ /* Enable TCP Csum */ /* Enable UDP Csum */ /* Strip CRC from packet */ /* Forward UCast to CPU */ /* Forward BCast to CPU */ /* Forward MCast to CPU */ /* Forward Other to CPU */ /* disable DMA engine */ /* wait while DMA engine is busy */ /* reset Rx and Tx rings */ /* XXX switch set mac address */ /* update TX_BASE_PTRx */ /* init Rx ring */ /* update RX_BASE_PTRx */ /* write back DDONE, 16byte burst enable RX/TX DMA */ /* disable interrupts mitigation */ /* clear pending interrupts */ /* enable interrupts */ /* IF_RT_PHY_SUPPORT */