FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_pint.c
/*!
 * brief	Initialize PINT peripheral.

 * This function initializes the PINT peripheral and enables the clock.
 *
 * param base Base address of the PINT peripheral.
 *
 * retval None.
 */
brief        Initialize PINT peripheral.
This function initializes the PINT peripheral and enables the clock.

param base Base address of the PINT peripheral.

retval None.
brief Initialize PINT peripheral . This function initializes the PINT peripheral and enables the clock . param base Base address of the PINT peripheral . retval None .
void PINT_Init(PINT_Type *base)
{
    uint32_t i;
    uint32_t pmcfg    = 0;
    uint8_t pintcount = 0;
    assert(base != NULL);
    if (base == PINT)
    {
        pintcount = FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS;
        for (i = 0; i < (uint32_t)FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
        {
            s_pintCallback[i] = NULL;
        }
    }
    else
    {
#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
        pintcount = FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS;
        for (i = 0; i < (uint32_t)FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS; i++)
        {
            s_secpintCallback[i] = NULL;
        }
#endif 
    }
    for (i = 0; i < pintcount; i++)
    {
        pmcfg = pmcfg | ((uint32_t)kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U)));
    }
#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1)
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
    CLOCK_EnableClock(kCLOCK_GpioInt);
#endif 
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
    RESET_PeripheralReset(kGPIOINT_RST_N_SHIFT_RSTn);
#endif 
#elif defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0)
    if (base == PINT)
    {
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
        CLOCK_EnableClock(kCLOCK_Gpio0);
#endif 
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
        RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn);
#endif 
    }
    else
    {
#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
        CLOCK_EnableClock(kCLOCK_Gpio_Sec);
#endif 
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
        RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn);
#endif 
#endif 
    }
#else
    if (base == PINT)
    {
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
        CLOCK_EnableClock(kCLOCK_Pint);
#endif 
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
        RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn);
#endif 
    }
    else
    {
#if (defined(FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS)
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
        CLOCK_EnableClock(kCLOCK_Gpio_Sec_Int);
#endif 
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
        RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn);
#endif 
#endif 
    }
#endif 
    base->PMCFG = pmcfg;
}
void PINT_Init ( PINT_Type * base ) { uint32_t i ; uint32_t pmcfg = 0 ; uint8_t pintcount = 0 ; assert ( base != NULL ) ; if ( base == PINT ) { pintcount = FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS ; for ( i = 0 ; i < ( uint32_t ) FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS ; i ++ ) { s_pintCallback [ i ] = NULL ; } } else { #if ( defined ( FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS ) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS ) pintcount = FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS ; for ( i = 0 ; i < ( uint32_t ) FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS ; i ++ ) { s_secpintCallback [ i ] = NULL ; } #endif } for ( i = 0 ; i < pintcount ; i ++ ) { pmcfg = pmcfg | ( ( uint32_t ) kPINT_PatternMatchNever << ( PININT_BITSLICE_CFG_START + ( i * 3U ) ) ) ; } #if defined ( FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE ) && ( FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1 ) #if ! ( defined ( FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL ) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL ) CLOCK_EnableClock ( kCLOCK_GpioInt ) ; #endif #if ! ( defined ( FSL_SDK_DISABLE_DRIVER_RESET_CONTROL ) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL ) RESET_PeripheralReset ( kGPIOINT_RST_N_SHIFT_RSTn ) ; #endif #elif defined ( FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE ) && ( FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 0 ) if ( base == PINT ) { #if ! ( defined ( FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL ) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL ) CLOCK_EnableClock ( kCLOCK_Gpio0 ) ; #endif #if ! ( defined ( FSL_SDK_DISABLE_DRIVER_RESET_CONTROL ) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL ) RESET_PeripheralReset ( kGPIO0_RST_N_SHIFT_RSTn ) ; #endif } else { #if ( defined ( FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS ) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS ) #if ! ( defined ( FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL ) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL ) CLOCK_EnableClock ( kCLOCK_Gpio_Sec ) ; #endif #if ! ( defined ( FSL_SDK_DISABLE_DRIVER_RESET_CONTROL ) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL ) RESET_PeripheralReset ( kGPIOSEC_RST_SHIFT_RSTn ) ; #endif #endif } #else if ( base == PINT ) { #if ! ( defined ( FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL ) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL ) CLOCK_EnableClock ( kCLOCK_Pint ) ; #endif #if ! ( defined ( FSL_SDK_DISABLE_DRIVER_RESET_CONTROL ) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL ) RESET_PeripheralReset ( kPINT_RST_SHIFT_RSTn ) ; #endif } else { #if ( defined ( FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS ) && FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS ) #if ! ( defined ( FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL ) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL ) CLOCK_EnableClock ( kCLOCK_Gpio_Sec_Int ) ; #endif #if ! ( defined ( FSL_SDK_DISABLE_DRIVER_RESET_CONTROL ) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL ) RESET_PeripheralReset ( kGPIOSECINT_RST_SHIFT_RSTn ) ; #endif #endif } #endif base -> PMCFG = pmcfg ; }
brief        Initialize PINT peripheral.
brief Initialize PINT peripheral .
/* clear PINT callback array*/ /* clear SECPINT callback array*/ /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ /* Disable all bit slices for pint*/ /* Enable the clock. */ /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ /* Reset the module. */ /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ /* Enable the clock. */ /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ /* Reset the module. */ /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ /* Enable the clock. */ /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ /* Reset the module. */ /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ /* Enable the clock. */ /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ /* Reset the module. */ /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ /* if need config SECURE PINT device,then enable secure pint interrupt clock */ /* Enable the clock. */ /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ /* Reset the module. */ /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ /* FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS */ /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ /* Disable all pattern match bit slices */