FreeBSD/sys/dev/nxge/xgehal/xgehal-device.c
/*
 * __hal_device_rts_port_configure - Configure RTS steering based on
 * destination or source port number.
 * @hldev: HAL device handle.
 *
 */
Configure RTS steering based on
destination or source port number.
@hldev: HAL device handle.
Configure RTS steering based on destination or source port number . @hldev : HAL device handle .
xge_hal_status_e
__hal_device_rts_port_configure(xge_hal_device_t *hldev)
{
	xge_hal_pci_bar0_t *bar0 = (xge_hal_pci_bar0_t *)(void *)hldev->bar0;
	u64 val64;
	int rnum;
	if (!hldev->config.rts_port_en) {
	    return XGE_HAL_OK;
	}
	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
	                &bar0->rts_ctrl);
	val64 |=  XGE_HAL_RTS_CTRL_ENHANCED_MODE;
	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
	            val64, &bar0->rts_ctrl);
	for (rnum = 0; rnum < XGE_HAL_MAX_RING_NUM; rnum++) {
	    int pnum;
	    xge_hal_ring_queue_t *queue = &hldev->config.ring.queue[rnum];
	    if (!queue->configured || queue->rts_port_en)
	        continue;
	    for (pnum = 0; pnum < XGE_HAL_MAX_STEERABLE_PORTS; pnum++) {
	        xge_hal_rts_port_t *port = &queue->rts_ports[pnum];
	        if (!port->num) {
	            xge_os_pio_mem_write64(hldev->pdev,
	                   hldev->regh0, 0ULL,
	                   &bar0->rts_pn_cam_data);
	            val64 = BIT(7) | BIT(15);
	        } else {
	            val64 = vBIT(port->num,8,16) |
	                vBIT(rnum,37,3) | BIT(63);
	            if (port->src)
	                val64 = BIT(47);
	            if (!port->udp)
	                val64 = BIT(7);
	            xge_os_pio_mem_write64(hldev->pdev,
	                       hldev->regh0, val64,
	                       &bar0->rts_pn_cam_data);
	            val64 = BIT(7) | BIT(15) | vBIT(pnum,24,8);
	        }
	        xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
	                       val64, &bar0->rts_pn_cam_ctrl);
	        if (__hal_device_register_poll(hldev,
	               &bar0->rts_pn_cam_ctrl, 0,
	               XGE_HAL_RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED,
	               XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS) !=
	                            XGE_HAL_OK) {
	            return XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING;
	        }
	    }
	}
	return XGE_HAL_OK;
}
xge_hal_status_e __hal_device_rts_port_configure ( xge_hal_device_t * hldev ) { xge_hal_pci_bar0_t * bar0 = ( xge_hal_pci_bar0_t * ) ( void * ) hldev -> bar0 ; u64 val64 ; int rnum ; if ( ! hldev -> config . rts_port_en ) { return XGE_HAL_OK ; } val64 = xge_os_pio_mem_read64 ( hldev -> pdev , hldev -> regh0 , & bar0 -> rts_ctrl ) ; val64 |= XGE_HAL_RTS_CTRL_ENHANCED_MODE ; xge_os_pio_mem_write64 ( hldev -> pdev , hldev -> regh0 , val64 , & bar0 -> rts_ctrl ) ; for ( rnum = 0 ; rnum < XGE_HAL_MAX_RING_NUM ; rnum ++ ) { int pnum ; xge_hal_ring_queue_t * queue = & hldev -> config . ring . queue [ rnum ] ; if ( ! queue -> configured || queue -> rts_port_en ) continue ; for ( pnum = 0 ; pnum < XGE_HAL_MAX_STEERABLE_PORTS ; pnum ++ ) { xge_hal_rts_port_t * port = & queue -> rts_ports [ pnum ] ; if ( ! port -> num ) { xge_os_pio_mem_write64 ( hldev -> pdev , hldev -> regh0 , 0ULL , & bar0 -> rts_pn_cam_data ) ; val64 = BIT ( 7 ) | BIT ( 15 ) ; } else { val64 = vBIT ( port -> num , 8 , 16 ) | vBIT ( rnum , 37 , 3 ) | BIT ( 63 ) ; if ( port -> src ) val64 = BIT ( 47 ) ; if ( ! port -> udp ) val64 = BIT ( 7 ) ; xge_os_pio_mem_write64 ( hldev -> pdev , hldev -> regh0 , val64 , & bar0 -> rts_pn_cam_data ) ; val64 = BIT ( 7 ) | BIT ( 15 ) | vBIT ( pnum , 24 , 8 ) ; } xge_os_pio_mem_write64 ( hldev -> pdev , hldev -> regh0 , val64 , & bar0 -> rts_pn_cam_ctrl ) ; if ( __hal_device_register_poll ( hldev , & bar0 -> rts_pn_cam_ctrl , 0 , XGE_HAL_RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED , XGE_HAL_DEVICE_CMDMEM_WAIT_MAX_MILLIS ) != XGE_HAL_OK ) { return XGE_HAL_INF_MEM_STROBE_CMD_EXECUTING ; } } } return XGE_HAL_OK ; }
__hal_device_rts_port_configure - Configure RTS steering based on
 destination or source port number.
__hal_device_rts_port_configure - Configure RTS steering based on destination or source port number .
/*
	 * Set the receive traffic steering mode from default(classic)
	 * to enhanced.
	 */ /*
	 * Initiate port steering according to per-ring configuration
	 */ /*
	         * Skip and clear empty ports
	         */ /*
	             * Clear CAM memory
	             */ /*
	             * Assign new Port values according
	             * to configuration
	             */ /* poll until done */ /* upper layer may require to repeat */