src/occ_405/pss/avsbus.c
// AVS Bus setup that must be done once (common between read/write operations)
AVS Bus setup that must be done once (common between read/write operations)
AVS Bus setup that must be done once ( common between read / write operations )
void avsbus_init()
{
    uint32_t value;
    TRAC_INFO("avsbus_init: Vdd=%c Vdn=%c",
              G_avsbus_vdd_monitoring?'Y':'N', G_avsbus_vdn_monitoring?'Y':'N');
    bool bus0_monitoring = FALSE;
    bool bus1_monitoring = FALSE;
    if (G_avsbus_vdd_monitoring)
    {
        if (0 == G_sysConfigData.avsbus_vdd.bus)
        {
            bus0_monitoring = TRUE;
        }
        else
        {
            bus1_monitoring = TRUE;
        }
    }
    if (G_avsbus_vdn_monitoring)
    {
        if (0 == G_sysConfigData.avsbus_vdn.bus)
        {
            bus0_monitoring = TRUE;
        }
        else
        {
            bus1_monitoring = TRUE;
        }
    }
    value = 0x820FC000;
    if (bus0_monitoring)
    {
        DEBUG_OUT32(OCB_O2SCTRLF0B, value, "OCB_O2SCTRLF0B");
        out32(OCB_O2SCTRLF0B, value);
    }
    if (bus1_monitoring)
    {
        DEBUG_OUT32(OCB_O2SCTRLF1B, value, "OCB_O2SCTRLF1B");
        out32(OCB_O2SCTRLF1B, value);
    }
    value = 0x00080000;
    if (bus0_monitoring)
    {
        DEBUG_OUT32(OCB_O2SCTRLS0B, value, "OCB_O2SCTRLS0B");
        out32(OCB_O2SCTRLS0B, value);
    }
    if (bus1_monitoring)
    {
        DEBUG_OUT32(OCB_O2SCTRLS1B, value, "OCB_O2SCTRLS1B");
        out32(OCB_O2SCTRLS1B, value);
    }
    value = 0x90004000;
    const uint32_t divider = (G_nest_frequency_mhz / (AVSBUS_FREQUENCY_MHZ * 8)) - 1;
    value |= (divider << 18);
    if (bus0_monitoring)
    {
        TRAC_INFO("avsbus_init: reg[OCB_O2SCTRL10B] = 0x%08X", value);
        out32(OCB_O2SCTRL10B, value);
    }
    if (bus1_monitoring)
    {
        TRAC_INFO("avsbus_init: reg[OCB_O2SCTRL11B] = 0x%08X", value);
        out32(OCB_O2SCTRL11B, value);
    }
    value = 0x00000000;
    if (bus0_monitoring)
    {
        DEBUG_OUT32(OCB_O2SCTRL20B, value, "OCB_O2SCTRL20B");
        out32(OCB_O2SCTRL20B, value);
    }
    if (bus1_monitoring)
    {
        DEBUG_OUT32(OCB_O2SCTRL21B, value, "OCB_O2SCTRL21B");
        out32(OCB_O2SCTRL21B, value);
    }
    const uint32_t error_mask = AVSBUS_STATUS_OVER_CURRENT_MASK;
    if (bus0_monitoring)
    {
        avsbus_resync(0);
        clear_status_errors(0, error_mask);
    }
    if (bus1_monitoring)
    {
        avsbus_resync(1);
        clear_status_errors(1, error_mask);
    }
}
void avsbus_init ( ) { uint32_t value ; TRAC_INFO ( " " , G_avsbus_vdd_monitoring ? ' ' : ' ' , G_avsbus_vdn_monitoring ? ' ' : ' ' ) ; bool bus0_monitoring = FALSE ; bool bus1_monitoring = FALSE ; if ( G_avsbus_vdd_monitoring ) { if ( 0 == G_sysConfigData . avsbus_vdd . bus ) { bus0_monitoring = TRUE ; } else { bus1_monitoring = TRUE ; } } if ( G_avsbus_vdn_monitoring ) { if ( 0 == G_sysConfigData . avsbus_vdn . bus ) { bus0_monitoring = TRUE ; } else { bus1_monitoring = TRUE ; } } value = 0x820FC000 ; if ( bus0_monitoring ) { DEBUG_OUT32 ( OCB_O2SCTRLF0B , value , " " ) ; out32 ( OCB_O2SCTRLF0B , value ) ; } if ( bus1_monitoring ) { DEBUG_OUT32 ( OCB_O2SCTRLF1B , value , " " ) ; out32 ( OCB_O2SCTRLF1B , value ) ; } value = 0x00080000 ; if ( bus0_monitoring ) { DEBUG_OUT32 ( OCB_O2SCTRLS0B , value , " " ) ; out32 ( OCB_O2SCTRLS0B , value ) ; } if ( bus1_monitoring ) { DEBUG_OUT32 ( OCB_O2SCTRLS1B , value , " " ) ; out32 ( OCB_O2SCTRLS1B , value ) ; } value = 0x90004000 ; const uint32_t divider = ( G_nest_frequency_mhz / ( AVSBUS_FREQUENCY_MHZ * 8 ) ) - 1 ; value |= ( divider << 18 ) ; if ( bus0_monitoring ) { TRAC_INFO ( " " , value ) ; out32 ( OCB_O2SCTRL10B , value ) ; } if ( bus1_monitoring ) { TRAC_INFO ( " " , value ) ; out32 ( OCB_O2SCTRL11B , value ) ; } value = 0x00000000 ; if ( bus0_monitoring ) { DEBUG_OUT32 ( OCB_O2SCTRL20B , value , " " ) ; out32 ( OCB_O2SCTRL20B , value ) ; } if ( bus1_monitoring ) { DEBUG_OUT32 ( OCB_O2SCTRL21B , value , " " ) ; out32 ( OCB_O2SCTRL21B , value ) ; } const uint32_t error_mask = AVSBUS_STATUS_OVER_CURRENT_MASK ; if ( bus0_monitoring ) { avsbus_resync ( 0 ) ; clear_status_errors ( 0 , error_mask ) ; } if ( bus1_monitoring ) { avsbus_resync ( 1 ) ; clear_status_errors ( 1 , error_mask ) ; } }
AVS Bus setup that must be done once (common between read/write operations)
AVS Bus setup that must be done once ( common between read / write operations )
// Write O2SCTRLF_[a][n] //  o2s_frame_size = 0x20 (32d) //  o2s_out_count1 = 0x20 (32d) - 5b header, 8b command type/select,16b info, 3b CRC //  o2s_in_delay1 = 0xFF (long delay - no read data) //  o2s_in_count1 = 0x0 (no read data) // Write O2SCTRLS_[a][n] //  0:5   o2s_out_count2 = 0 (no output) //  6:11  o2s_in_delay2 = 0 (no delay - immediate read data) //  12:17 o2s_in_count2 = 32 (bits captured) // Write O2SCTRL1_[a][n] //  0     o2s_bridge_enable = 1 (make the O2S bridge active if not already) //  1     reserved //  2     o2s_cpol = 0 (positive active clock) //  3     o2s_cpha = 1 (second edge data sample) //  4:13  o2s_clock_divider = set based on the nest frequency for the desired frequency of 10MHz (assumed speed) per O2SCTRL1_[a][n] description. //  14:16 reserved //  17    o2s_nr_of_frames = 1 (2 frames to account for the first and second frames of an AVSBus command) //  18:63 reserved //  1r00DDDD DDDDDDrr r1rrrrrr rrrrrrrrr // calculate o2s_clock_divider based on nest freq and target bus freq // Write O2SCTRL2_[a][n] //  o2s_inter_frame_delay = 0 (Wait 1 SPI clock). The AVSBus spec does not define any inter-frame delay so set this to the smallest value. //  Note: the value 0 is the hardware reset value and, thus, this step can be omitted if the value desired to to be left at 0. // Re-sync AVS bus and clear OC bits in status regs and