FreeBSD/sys/dev/vxge/vxge.c
/*
 * vxge_vpath_config
 * Sets HAL parameter values from kenv
 */
vxge_vpath_config
Sets HAL parameter values from kenv
vxge_vpath_config Sets HAL parameter values from kenv
void
vxge_vpath_config(vxge_dev_t *vdev)
{
	int i;
	u32 no_of_vpath = 0;
	vxge_hal_vp_config_t *vp_config;
	vxge_hal_device_config_t *device_config = vdev->device_config;
	device_config->debug_level = VXGE_TRACE;
	device_config->debug_mask = VXGE_COMPONENT_ALL;
	device_config->device_poll_millis = VXGE_DEFAULT_DEVICE_POLL_MILLIS;
	vdev->config.no_of_vpath =
	    min(vdev->config.no_of_vpath, vdev->max_supported_vpath);
	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
		vp_config = &(device_config->vp_config[i]);
		vp_config->fifo.enable = VXGE_HAL_FIFO_DISABLE;
		vp_config->ring.enable = VXGE_HAL_RING_DISABLE;
	}
	for (i = 0; i < VXGE_HAL_MAX_VIRTUAL_PATHS; i++) {
		if (no_of_vpath >= vdev->config.no_of_vpath)
			break;
		if (!bVAL1(vdev->config.hw_info.vpath_mask, i))
			continue;
		no_of_vpath++;
		vp_config = &(device_config->vp_config[i]);
		vp_config->mtu = VXGE_HAL_DEFAULT_MTU;
		vp_config->ring.enable = VXGE_HAL_RING_ENABLE;
		vp_config->ring.post_mode = VXGE_HAL_RING_POST_MODE_DOORBELL;
		vp_config->ring.buffer_mode = VXGE_HAL_RING_RXD_BUFFER_MODE_1;
		vp_config->ring.ring_length =
		    vxge_ring_length_get(VXGE_HAL_RING_RXD_BUFFER_MODE_1);
		vp_config->ring.scatter_mode = VXGE_HAL_RING_SCATTER_MODE_A;
		vp_config->rpa_all_vid_en = VXGE_DEFAULT_ALL_VID_ENABLE;
		vp_config->rpa_strip_vlan_tag = VXGE_DEFAULT_STRIP_VLAN_TAG;
		vp_config->rpa_ucast_all_addr_en =
		    VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_DISABLE;
		vp_config->rti.intr_enable = VXGE_HAL_TIM_INTR_ENABLE;
		vp_config->rti.txfrm_cnt_en = VXGE_HAL_TXFRM_CNT_EN_ENABLE;
		vp_config->rti.util_sel =
		    VXGE_HAL_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL;
		vp_config->rti.uec_a = VXGE_DEFAULT_RTI_RX_UFC_A;
		vp_config->rti.uec_b = VXGE_DEFAULT_RTI_RX_UFC_B;
		vp_config->rti.uec_c = VXGE_DEFAULT_RTI_RX_UFC_C;
		vp_config->rti.uec_d = VXGE_DEFAULT_RTI_RX_UFC_D;
		vp_config->rti.urange_a = VXGE_DEFAULT_RTI_RX_URANGE_A;
		vp_config->rti.urange_b = VXGE_DEFAULT_RTI_RX_URANGE_B;
		vp_config->rti.urange_c = VXGE_DEFAULT_RTI_RX_URANGE_C;
		vp_config->rti.timer_ac_en = VXGE_HAL_TIM_TIMER_AC_ENABLE;
		vp_config->rti.timer_ci_en = VXGE_HAL_TIM_TIMER_CI_ENABLE;
		vp_config->rti.btimer_val =
		    (VXGE_DEFAULT_RTI_BTIMER_VAL * 1000) / 272;
		vp_config->rti.rtimer_val =
		    (VXGE_DEFAULT_RTI_RTIMER_VAL * 1000) / 272;
		vp_config->rti.ltimer_val =
		    (VXGE_DEFAULT_RTI_LTIMER_VAL * 1000) / 272;
		if ((no_of_vpath > 1) && (VXGE_DEFAULT_CONFIG_MQ_ENABLE == 0))
			continue;
		vp_config->fifo.enable = VXGE_HAL_FIFO_ENABLE;
		vp_config->fifo.max_aligned_frags =
		    VXGE_DEFAULT_FIFO_ALIGNED_FRAGS;
		vp_config->tti.intr_enable = VXGE_HAL_TIM_INTR_ENABLE;
		vp_config->tti.txfrm_cnt_en = VXGE_HAL_TXFRM_CNT_EN_ENABLE;
		vp_config->tti.util_sel =
		    VXGE_HAL_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL;
		vp_config->tti.uec_a = VXGE_DEFAULT_TTI_TX_UFC_A;
		vp_config->tti.uec_b = VXGE_DEFAULT_TTI_TX_UFC_B;
		vp_config->tti.uec_c = VXGE_DEFAULT_TTI_TX_UFC_C;
		vp_config->tti.uec_d = VXGE_DEFAULT_TTI_TX_UFC_D;
		vp_config->tti.urange_a = VXGE_DEFAULT_TTI_TX_URANGE_A;
		vp_config->tti.urange_b = VXGE_DEFAULT_TTI_TX_URANGE_B;
		vp_config->tti.urange_c = VXGE_DEFAULT_TTI_TX_URANGE_C;
		vp_config->tti.timer_ac_en = VXGE_HAL_TIM_TIMER_AC_ENABLE;
		vp_config->tti.timer_ci_en = VXGE_HAL_TIM_TIMER_CI_ENABLE;
		vp_config->tti.btimer_val =
		    (VXGE_DEFAULT_TTI_BTIMER_VAL * 1000) / 272;
		vp_config->tti.rtimer_val =
		    (VXGE_DEFAULT_TTI_RTIMER_VAL * 1000) / 272;
		vp_config->tti.ltimer_val =
		    (VXGE_DEFAULT_TTI_LTIMER_VAL * 1000) / 272;
	}
	vdev->no_of_vpath = no_of_vpath;
	if (vdev->no_of_vpath == 1)
		vdev->config.tx_steering = 0;
	if (vdev->config.rth_enable && (vdev->no_of_vpath > 1)) {
		device_config->rth_en = VXGE_HAL_RTH_ENABLE;
		device_config->rth_it_type = VXGE_HAL_RTH_IT_TYPE_MULTI_IT;
	}
	vdev->config.rth_enable = device_config->rth_en;
}
void vxge_vpath_config ( vxge_dev_t * vdev ) { int i ; u32 no_of_vpath = 0 ; vxge_hal_vp_config_t * vp_config ; vxge_hal_device_config_t * device_config = vdev -> device_config ; device_config -> debug_level = VXGE_TRACE ; device_config -> debug_mask = VXGE_COMPONENT_ALL ; device_config -> device_poll_millis = VXGE_DEFAULT_DEVICE_POLL_MILLIS ; vdev -> config . no_of_vpath = min ( vdev -> config . no_of_vpath , vdev -> max_supported_vpath ) ; for ( i = 0 ; i < VXGE_HAL_MAX_VIRTUAL_PATHS ; i ++ ) { vp_config = & ( device_config -> vp_config [ i ] ) ; vp_config -> fifo . enable = VXGE_HAL_FIFO_DISABLE ; vp_config -> ring . enable = VXGE_HAL_RING_DISABLE ; } for ( i = 0 ; i < VXGE_HAL_MAX_VIRTUAL_PATHS ; i ++ ) { if ( no_of_vpath >= vdev -> config . no_of_vpath ) break ; if ( ! bVAL1 ( vdev -> config . hw_info . vpath_mask , i ) ) continue ; no_of_vpath ++ ; vp_config = & ( device_config -> vp_config [ i ] ) ; vp_config -> mtu = VXGE_HAL_DEFAULT_MTU ; vp_config -> ring . enable = VXGE_HAL_RING_ENABLE ; vp_config -> ring . post_mode = VXGE_HAL_RING_POST_MODE_DOORBELL ; vp_config -> ring . buffer_mode = VXGE_HAL_RING_RXD_BUFFER_MODE_1 ; vp_config -> ring . ring_length = vxge_ring_length_get ( VXGE_HAL_RING_RXD_BUFFER_MODE_1 ) ; vp_config -> ring . scatter_mode = VXGE_HAL_RING_SCATTER_MODE_A ; vp_config -> rpa_all_vid_en = VXGE_DEFAULT_ALL_VID_ENABLE ; vp_config -> rpa_strip_vlan_tag = VXGE_DEFAULT_STRIP_VLAN_TAG ; vp_config -> rpa_ucast_all_addr_en = VXGE_HAL_VPATH_RPA_UCAST_ALL_ADDR_DISABLE ; vp_config -> rti . intr_enable = VXGE_HAL_TIM_INTR_ENABLE ; vp_config -> rti . txfrm_cnt_en = VXGE_HAL_TXFRM_CNT_EN_ENABLE ; vp_config -> rti . util_sel = VXGE_HAL_TIM_UTIL_SEL_LEGACY_RX_NET_UTIL ; vp_config -> rti . uec_a = VXGE_DEFAULT_RTI_RX_UFC_A ; vp_config -> rti . uec_b = VXGE_DEFAULT_RTI_RX_UFC_B ; vp_config -> rti . uec_c = VXGE_DEFAULT_RTI_RX_UFC_C ; vp_config -> rti . uec_d = VXGE_DEFAULT_RTI_RX_UFC_D ; vp_config -> rti . urange_a = VXGE_DEFAULT_RTI_RX_URANGE_A ; vp_config -> rti . urange_b = VXGE_DEFAULT_RTI_RX_URANGE_B ; vp_config -> rti . urange_c = VXGE_DEFAULT_RTI_RX_URANGE_C ; vp_config -> rti . timer_ac_en = VXGE_HAL_TIM_TIMER_AC_ENABLE ; vp_config -> rti . timer_ci_en = VXGE_HAL_TIM_TIMER_CI_ENABLE ; vp_config -> rti . btimer_val = ( VXGE_DEFAULT_RTI_BTIMER_VAL * 1000 ) / 272 ; vp_config -> rti . rtimer_val = ( VXGE_DEFAULT_RTI_RTIMER_VAL * 1000 ) / 272 ; vp_config -> rti . ltimer_val = ( VXGE_DEFAULT_RTI_LTIMER_VAL * 1000 ) / 272 ; if ( ( no_of_vpath > 1 ) && ( VXGE_DEFAULT_CONFIG_MQ_ENABLE == 0 ) ) continue ; vp_config -> fifo . enable = VXGE_HAL_FIFO_ENABLE ; vp_config -> fifo . max_aligned_frags = VXGE_DEFAULT_FIFO_ALIGNED_FRAGS ; vp_config -> tti . intr_enable = VXGE_HAL_TIM_INTR_ENABLE ; vp_config -> tti . txfrm_cnt_en = VXGE_HAL_TXFRM_CNT_EN_ENABLE ; vp_config -> tti . util_sel = VXGE_HAL_TIM_UTIL_SEL_LEGACY_TX_NET_UTIL ; vp_config -> tti . uec_a = VXGE_DEFAULT_TTI_TX_UFC_A ; vp_config -> tti . uec_b = VXGE_DEFAULT_TTI_TX_UFC_B ; vp_config -> tti . uec_c = VXGE_DEFAULT_TTI_TX_UFC_C ; vp_config -> tti . uec_d = VXGE_DEFAULT_TTI_TX_UFC_D ; vp_config -> tti . urange_a = VXGE_DEFAULT_TTI_TX_URANGE_A ; vp_config -> tti . urange_b = VXGE_DEFAULT_TTI_TX_URANGE_B ; vp_config -> tti . urange_c = VXGE_DEFAULT_TTI_TX_URANGE_C ; vp_config -> tti . timer_ac_en = VXGE_HAL_TIM_TIMER_AC_ENABLE ; vp_config -> tti . timer_ci_en = VXGE_HAL_TIM_TIMER_CI_ENABLE ; vp_config -> tti . btimer_val = ( VXGE_DEFAULT_TTI_BTIMER_VAL * 1000 ) / 272 ; vp_config -> tti . rtimer_val = ( VXGE_DEFAULT_TTI_RTIMER_VAL * 1000 ) / 272 ; vp_config -> tti . ltimer_val = ( VXGE_DEFAULT_TTI_LTIMER_VAL * 1000 ) / 272 ; } vdev -> no_of_vpath = no_of_vpath ; if ( vdev -> no_of_vpath == 1 ) vdev -> config . tx_steering = 0 ; if ( vdev -> config . rth_enable && ( vdev -> no_of_vpath > 1 ) ) { device_config -> rth_en = VXGE_HAL_RTH_ENABLE ; device_config -> rth_it_type = VXGE_HAL_RTH_IT_TYPE_MULTI_IT ; } vdev -> config . rth_enable = device_config -> rth_en ; }
vxge_vpath_config
 Sets HAL parameter values from kenv
vxge_vpath_config Sets HAL parameter values from kenv