sys/dev/agp/agp.c
/*
 * This does the enable logic for v3, with the same topology
 * restrictions as in place for v2 -- one bus, one device on the bus.
 */
This does the enable logic for v3, with the same topology
restrictions as in place for v2 -- one bus, one device on the bus.
This does the enable logic for v3 with the same topology restrictions as in place for v2 -- one bus one device on the bus .
static int
agp_v3_enable(device_t dev, device_t mdev, u_int32_t mode)
{
	u_int32_t tstatus, mstatus;
	u_int32_t command;
	int rq, sba, fw, rate, arqsz, cal;
	tstatus = pci_read_config(dev, agp_find_caps(dev) + AGP_STATUS, 4);
	mstatus = pci_read_config(mdev, agp_find_caps(mdev) + AGP_STATUS, 4);
	rq = AGP_MODE_GET_RQ(mode);
	if (AGP_MODE_GET_RQ(tstatus) < rq)
		rq = AGP_MODE_GET_RQ(tstatus);
	if (AGP_MODE_GET_RQ(mstatus) < rq)
		rq = AGP_MODE_GET_RQ(mstatus);
	arqsz = AGP_MODE_GET_ARQSZ(mode);
	if (AGP_MODE_GET_ARQSZ(tstatus) > rq)
		rq = AGP_MODE_GET_ARQSZ(tstatus);
	if (AGP_MODE_GET_ARQSZ(mstatus) > rq)
		rq = AGP_MODE_GET_ARQSZ(mstatus);
	cal = AGP_MODE_GET_CAL(tstatus);
	if (AGP_MODE_GET_CAL(mstatus) < cal)
		cal = AGP_MODE_GET_CAL(mstatus);
	sba = 1;
	fw = (AGP_MODE_GET_FW(tstatus)
	       & AGP_MODE_GET_FW(mstatus)
	       & AGP_MODE_GET_FW(mode));
	rate = (AGP_MODE_GET_RATE(tstatus)
		& AGP_MODE_GET_RATE(mstatus)
		& AGP_MODE_GET_RATE(mode));
	if (rate & AGP_MODE_V3_RATE_8x)
		rate = AGP_MODE_V3_RATE_8x;
	else
		rate = AGP_MODE_V3_RATE_4x;
	if (bootverbose)
		device_printf(dev, "Setting AGP v3 mode %d\n", rate * 4);
	pci_write_config(dev, agp_find_caps(dev) + AGP_COMMAND, 0, 4);
	command = 0;
	command = AGP_MODE_SET_RQ(0, rq);
	command = AGP_MODE_SET_ARQSZ(command, arqsz);
	command = AGP_MODE_SET_CAL(command, cal);
	command = AGP_MODE_SET_SBA(command, sba);
	command = AGP_MODE_SET_FW(command, fw);
	command = AGP_MODE_SET_RATE(command, rate);
	command = AGP_MODE_SET_MODE_3(command, 1);
	command = AGP_MODE_SET_AGP(command, 1);
	pci_write_config(dev, agp_find_caps(dev) + AGP_COMMAND, command, 4);
	pci_write_config(mdev, agp_find_caps(mdev) + AGP_COMMAND, command, 4);
	return 0;
}
static int agp_v3_enable ( device_t dev , device_t mdev , u_int32_t mode ) { u_int32_t tstatus , mstatus ; u_int32_t command ; int rq , sba , fw , rate , arqsz , cal ; tstatus = pci_read_config ( dev , agp_find_caps ( dev ) + AGP_STATUS , 4 ) ; mstatus = pci_read_config ( mdev , agp_find_caps ( mdev ) + AGP_STATUS , 4 ) ; rq = AGP_MODE_GET_RQ ( mode ) ; if ( AGP_MODE_GET_RQ ( tstatus ) < rq ) rq = AGP_MODE_GET_RQ ( tstatus ) ; if ( AGP_MODE_GET_RQ ( mstatus ) < rq ) rq = AGP_MODE_GET_RQ ( mstatus ) ; arqsz = AGP_MODE_GET_ARQSZ ( mode ) ; if ( AGP_MODE_GET_ARQSZ ( tstatus ) > rq ) rq = AGP_MODE_GET_ARQSZ ( tstatus ) ; if ( AGP_MODE_GET_ARQSZ ( mstatus ) > rq ) rq = AGP_MODE_GET_ARQSZ ( mstatus ) ; cal = AGP_MODE_GET_CAL ( tstatus ) ; if ( AGP_MODE_GET_CAL ( mstatus ) < cal ) cal = AGP_MODE_GET_CAL ( mstatus ) ; sba = 1 ; fw = ( AGP_MODE_GET_FW ( tstatus ) & AGP_MODE_GET_FW ( mstatus ) & AGP_MODE_GET_FW ( mode ) ) ; rate = ( AGP_MODE_GET_RATE ( tstatus ) & AGP_MODE_GET_RATE ( mstatus ) & AGP_MODE_GET_RATE ( mode ) ) ; if ( rate & AGP_MODE_V3_RATE_8x ) rate = AGP_MODE_V3_RATE_8x ; else rate = AGP_MODE_V3_RATE_4x ; if ( bootverbose ) device_printf ( dev , " \n " , rate * 4 ) ; pci_write_config ( dev , agp_find_caps ( dev ) + AGP_COMMAND , 0 , 4 ) ; command = 0 ; command = AGP_MODE_SET_RQ ( 0 , rq ) ; command = AGP_MODE_SET_ARQSZ ( command , arqsz ) ; command = AGP_MODE_SET_CAL ( command , cal ) ; command = AGP_MODE_SET_SBA ( command , sba ) ; command = AGP_MODE_SET_FW ( command , fw ) ; command = AGP_MODE_SET_RATE ( command , rate ) ; command = AGP_MODE_SET_MODE_3 ( command , 1 ) ; command = AGP_MODE_SET_AGP ( command , 1 ) ; pci_write_config ( dev , agp_find_caps ( dev ) + AGP_COMMAND , command , 4 ) ; pci_write_config ( mdev , agp_find_caps ( mdev ) + AGP_COMMAND , command , 4 ) ; return 0 ; }
This does the enable logic for v3, with the same topology
 restrictions as in place for v2 -- one bus, one device on the bus.
This does the enable logic for v3 with the same topology restrictions as in place for v2 -- one bus one device on the bus .
/* Set RQ to the min of mode, tstatus and mstatus */ /*
	 * ARQSZ - Set the value to the maximum one.
	 * Don't allow the mode register to override values.
	 */ /* Calibration cycle - don't allow override by mode register */ /* SBA must be supported for AGP v3. */ /* Set FW if all three support it. */ /* Figure out the max rate */ /* Construct the new mode word and tell the hardware */