components/driver/i2s.c
/**
 * @brief   Config I2S source clock and get its frequency
 *
 * @param   i2s_num         I2S device number
 * @param   use_apll        Whether use apll, only take effect when chip supports
 * @param   mclk            module clock
 *
 * @return
 *      - 0                 use I2S_CLK_APLL as clock source, no I2S system clock to set
 *      - I2S_LL_BASE_CLK   use I2S_CLK_D2CLK as clock source, return APB clock frequency
 */
@brief   Config I2S source clock and get its frequency
@param   i2s_num         I2S device number
@param   use_apll        Whether use apll, only take effect when chip supports
@param   mclk            module clock

@return
- 0                 use I2S_CLK_APLL as clock source, no I2S system clock to set
- I2S_LL_BASE_CLK   use I2S_CLK_D2CLK as clock source, return APB clock frequency
@brief Config I2S source clock and get its frequency @param i2s_num I2S device number @param use_apll Whether use apll only take effect when chip supports @param mclk module clock @return - 0 use I2S_CLK_APLL as clock source no I2S system clock to set - I2S_LL_BASE_CLK use I2S_CLK_D2CLK as clock source return APB clock frequency
static uint32_t i2s_config_source_clock(i2s_port_t i2s_num, bool use_apll, uint32_t mclk)
{
#if SOC_I2S_SUPPORTS_APLL
    if (use_apll) {
        int sdm0 = 0;
        int sdm1 = 0;
        int sdm2 = 0;
        int odir = 0;
        if ((mclk / p_i2s[i2s_num]->hal_cfg.chan_bits / p_i2s[i2s_num]->hal_cfg.total_chan) < SOC_I2S_APLL_MIN_RATE) {
            ESP_LOGE(TAG, "mclk is too small");
            return 0;
        }
        i2s_apll_calculate_fi2s(mclk, p_i2s[i2s_num]->hal_cfg.sample_bits, &sdm0, &sdm1, &sdm2, &odir);
        ESP_LOGI(TAG, "APLL Enabled, coefficient: sdm0=%d, sdm1=%d, sdm2=%d, odir=%d", sdm0, sdm1, sdm2, odir);
        rtc_clk_apll_enable(true, sdm0, sdm1, sdm2, odir);
        i2s_hal_set_clock_src(&(p_i2s[i2s_num]->hal), I2S_CLK_APLL);
        return 0;
    }
    i2s_hal_set_clock_src(&(p_i2s[i2s_num]->hal), I2S_CLK_D2CLK);
    return I2S_LL_BASE_CLK;
#else
    if (use_apll) {
        ESP_LOGW(TAG, "APLL not supported on current chip, use I2S_CLK_D2CLK as default clock source");
    }
    i2s_hal_set_clock_src(&(p_i2s[i2s_num]->hal), I2S_CLK_D2CLK);
    return I2S_LL_BASE_CLK;
#endif
}
static uint32_t i2s_config_source_clock ( i2s_port_t i2s_num , bool use_apll , uint32_t mclk ) { #if SOC_I2S_SUPPORTS_APLL if ( use_apll ) { int sdm0 = 0 ; int sdm1 = 0 ; int sdm2 = 0 ; int odir = 0 ; if ( ( mclk / p_i2s [ i2s_num ] -> hal_cfg . chan_bits / p_i2s [ i2s_num ] -> hal_cfg . total_chan ) < SOC_I2S_APLL_MIN_RATE ) { ESP_LOGE ( TAG , " " ) ; return 0 ; } i2s_apll_calculate_fi2s ( mclk , p_i2s [ i2s_num ] -> hal_cfg . sample_bits , & sdm0 , & sdm1 , & sdm2 , & odir ) ; ESP_LOGI ( TAG , " " , sdm0 , sdm1 , sdm2 , odir ) ; rtc_clk_apll_enable ( true , sdm0 , sdm1 , sdm2 , odir ) ; i2s_hal_set_clock_src ( & ( p_i2s [ i2s_num ] -> hal ) , I2S_CLK_APLL ) ; return 0 ; } i2s_hal_set_clock_src ( & ( p_i2s [ i2s_num ] -> hal ) , I2S_CLK_D2CLK ) ; return I2S_LL_BASE_CLK ; #else if ( use_apll ) { ESP_LOGW ( TAG , " " ) ; } i2s_hal_set_clock_src ( & ( p_i2s [ i2s_num ] -> hal ) , I2S_CLK_D2CLK ) ; return I2S_LL_BASE_CLK ; #endif }
@brief   Config I2S source clock and get its frequency
 @param   i2s_num         I2S device number
 @param   use_apll        Whether use apll, only take effect when chip supports
 @param   mclk            module clock
@brief Config I2S source clock and get its frequency @param i2s_num I2S device number @param use_apll Whether use apll only take effect when chip supports @param mclk module clock
/* Set I2S_APLL as I2S module clock source */ /* In APLL mode, there is no sclk but only mclk, so return 0 here to indicate APLL mode */ /* Set I2S_D2CLK (160M) as default I2S module clock source */ /* Set I2S_D2CLK (160M) as I2S module clock source */