Platform/ECM3532/M3/hw/csp/ecm3532/m3/csp/src/eta_csp_i2s.c
/***************************************************************************/
/**
 *
 *  EtaCspI2sConfig - Initialize the I2S module. Meant to be initialized either
 *                    from mailbox command from DSP or locally.
 *
 *  @param cfg encoded configuration value.
 *
 ******************************************************************************/
Initialize the I2S module. Meant to be initialized either
from mailbox command from DSP or locally.

@param cfg encoded configuration value.
Initialize the I2S module . Meant to be initialized either from mailbox command from DSP or locally . @param cfg encoded configuration value .
tI2sConfigRetVal
EtaCspI2sConfig(tI2sConfig i2sConfig)
{
  uint32_t tempdata0 ;
  uint32_t ui32MboxWord;
  ui32MboxWord = i2sConfig.packed_config;
  #ifdef ETA_CSP_I2S_DEBUG_PRINT
  ETA_DIAGS_PRINTF("M3:  packed_config:%x\r\n", i2sConfig.packed_config);
  ETA_DIAGS_PRINTF("M3:  enable_rx       :%x\r\n", i2sConfig.fields.enable_rx        );
  ETA_DIAGS_PRINTF("M3:  enable_tx       :%x\r\n", i2sConfig.fields.enable_tx        );
  ETA_DIAGS_PRINTF("M3:  swap_chan_tx    :%x\r\n", i2sConfig.fields.swap_chan_tx     );
  ETA_DIAGS_PRINTF("M3:  swap_chan_rx    :%x\r\n", i2sConfig.fields.swap_chan_rx     );
  ETA_DIAGS_PRINTF("M3:  mode_64bit      :%x\r\n", i2sConfig.fields.mode_64bit       );
  ETA_DIAGS_PRINTF("M3:  edge_tx_trig    :%x\r\n", i2sConfig.fields.edge_tx_trig     );
  ETA_DIAGS_PRINTF("M3:  edge_rx_trig    :%x\r\n", i2sConfig.fields.edge_rx_trig     );
  ETA_DIAGS_PRINTF("M3:  clock_src       :%x\r\n", i2sConfig.fields.clock_src        );
  ETA_DIAGS_PRINTF("M3:  sample_freq     :%x\r\n", i2sConfig.fields.sample_freq      );
  ETA_DIAGS_PRINTF("M3:  chan_tx_config  :%x\r\n", i2sConfig.fields.chan_tx_config   );
  ETA_DIAGS_PRINTF("M3:  chan_rx_config  :%x\r\n", i2sConfig.fields.chan_rx_config   );
  ETA_DIAGS_PRINTF("M3:  chan_tx_upscale :%x\r\n", i2sConfig.fields.chan_tx_upscale  );
  ETA_DIAGS_PRINTF("M3:  chan_rx_upscale :%x\r\n", i2sConfig.fields.chan_rx_upscale  );
  ETA_DIAGS_PRINTF("M3:  int_mode        :%x\r\n", i2sConfig.fields.int_mode         );
  #endif 
  uint32_t enable_rx       = ((ui32MboxWord & BM_ETA_CSP_COMMON_I2S_RX_ENBLE) >> BP_ETA_CSP_COMMON_I2S_RX_ENBLE);
  uint32_t enable_tx       = ((ui32MboxWord & BM_ETA_CSP_COMMON_I2S_TX_ENBLE) >> BP_ETA_CSP_COMMON_I2S_TX_ENBLE);
  uint32_t mode_64bit      = ((ui32MboxWord & BM_ETA_CSP_COMMON_I2S_64B_MODE) >> BP_ETA_CSP_COMMON_I2S_64B_MODE);
  uint32_t clock_src       = ((ui32MboxWord & BM_ETA_CSP_COMMON_I2S_CLCK_SRC) >> BP_ETA_CSP_COMMON_I2S_CLCK_SRC);
  uint32_t sample_freq     = ((ui32MboxWord & BM_ETA_CSP_COMMON_I2S_SMPL_FRQ) >> BP_ETA_CSP_COMMON_I2S_SMPL_FRQ);
  switch (clock_src)
  {
    case (eI2sClkSrc2MhzXtal):
          REG_M1(RTC_OSC_CSR2,VHFO_PD_N,1);
          REG_GPIO_DEBUG0_READ_ONLY.V = REG_SOCCTRL_PMUXB.V;
          REG_M1(SOCCTRL_CLK_CFG,ADC_CLK_SEL,BFV_SOCCTRL_CLK_CFG_ADC_CLK_SEL_2MHZ_XTAL);
          break;
    case (eI2sClkSrc2MhzHfo):
          REG_M1(SOCCTRL_CLK_CFG,ADC_CLK_SEL,BFV_SOCCTRL_CLK_CFG_ADC_CLK_SEL_2MHZ_HFO);
          break;
    case (eI2sClkSrc1MhzHfo):
          REG_M1(SOCCTRL_CLK_CFG,ADC_CLK_SEL,BFV_SOCCTRL_CLK_CFG_ADC_CLK_SEL_1MHZ_HFO);
          break;
    case (eI2sClkSrcFromPad):
          tempdata0 = REG_SOCCTRL_PMUXB.V;
          tempdata0 &= ~(BM_SOCCTRL_PMUXB_GPIO12 );
          tempdata0 |= ( BFV_SOCCTRL_PMUXB_GPIO12_I2S_ACLK <<BP_SOCCTRL_PMUXB_GPIO12) ;
          REG_SOCCTRL_PMUXB.V = tempdata0;
          REG_GPIO_DEBUG0_READ_ONLY.V = REG_SOCCTRL_PMUXB.V;
          REG_M1(SOCCTRL_CLK_CFG,ADC_CLK_SEL,BFV_SOCCTRL_CLK_CFG_ADC_CLK_SEL_2MHZ_PAD);
          break;
    default:
          return (eI2sConfigInvalidClkSource);
          break;
  }
  if (enable_tx && enable_rx) 
  {
    #ifdef ETA_CSP_I2S_DEBUG_PRINT
    ETA_DIAGS_PRINTF("M3:  Configuring GPIO13,14,15,16 (TX and RX)\r\n");
    #endif 
    tempdata0 = REG_SOCCTRL_PMUXC.V;
    tempdata0 &= ~ BM_SOCCTRL_PMUXC_GPIO16 ;
    tempdata0 |=  BFV_SOCCTRL_PMUXC_GPIO16_I2S_DATA_OUT << BP_SOCCTRL_PMUXC_GPIO16 ;
    REG_SOCCTRL_PMUXC.V = tempdata0;
    tempdata0 = REG_SOCCTRL_PMUXB.V;
    tempdata0 &= ~(BM_SOCCTRL_PMUXB_GPIO15 |
                   BM_SOCCTRL_PMUXB_GPIO14 |
                   BM_SOCCTRL_PMUXB_GPIO13 );
    tempdata0 |= ( BFV_SOCCTRL_PMUXB_GPIO15_I2S_DATA_IN <<BP_SOCCTRL_PMUXB_GPIO15) |
                 ( BFV_SOCCTRL_PMUXB_GPIO14_I2S_LRCLK <<BP_SOCCTRL_PMUXB_GPIO14) |
                 ( BFV_SOCCTRL_PMUXB_GPIO13_I2S_BCLK <<BP_SOCCTRL_PMUXB_GPIO13) ;
    REG_SOCCTRL_PMUXB.V = tempdata0;
  }
  else if (enable_rx) 
  {
    #ifdef ETA_CSP_I2S_DEBUG_PRINT
    ETA_DIAGS_PRINTF("M3:  Configuring GPIO13,14,15 (RX Only)\r\n");
    #endif 
    tempdata0 = REG_SOCCTRL_PMUXB.V;
    tempdata0 &= ~(BM_SOCCTRL_PMUXB_GPIO15 |
                   BM_SOCCTRL_PMUXB_GPIO14 |
                   BM_SOCCTRL_PMUXB_GPIO13 );
    tempdata0 |= ( BFV_SOCCTRL_PMUXB_GPIO15_I2S_DATA_IN <<BP_SOCCTRL_PMUXB_GPIO15) |
                 ( BFV_SOCCTRL_PMUXB_GPIO14_I2S_LRCLK <<BP_SOCCTRL_PMUXB_GPIO14) |
                 ( BFV_SOCCTRL_PMUXB_GPIO13_I2S_BCLK <<BP_SOCCTRL_PMUXB_GPIO13) ;
    REG_SOCCTRL_PMUXB.V = tempdata0;
  }
  else if (enable_tx) 
  {
    #ifdef ETA_CSP_I2S_DEBUG_PRINT
    ETA_DIAGS_PRINTF("M3:  Configuring GPIO13,14,16 (TX Only)\r\n");
    #endif 
    tempdata0 = REG_SOCCTRL_PMUXC.V;
    tempdata0 &= ~ BM_SOCCTRL_PMUXC_GPIO16 ;
    tempdata0 |=  BFV_SOCCTRL_PMUXC_GPIO16_I2S_DATA_OUT << BP_SOCCTRL_PMUXC_GPIO16 ;
    REG_SOCCTRL_PMUXC.V = tempdata0;
    tempdata0 = REG_SOCCTRL_PMUXB.V;
    tempdata0 &= ~(BM_SOCCTRL_PMUXB_GPIO14 |
                   BM_SOCCTRL_PMUXB_GPIO13 );
    tempdata0 |= ( BFV_SOCCTRL_PMUXB_GPIO14_I2S_LRCLK <<BP_SOCCTRL_PMUXB_GPIO14) |
                 ( BFV_SOCCTRL_PMUXB_GPIO13_I2S_BCLK <<BP_SOCCTRL_PMUXB_GPIO13) ;
    REG_SOCCTRL_PMUXB.V = tempdata0;
  }
  REG_GPIO_DEBUG0_READ_ONLY.V = REG_SOCCTRL_PMUXB.V;
  REG_I2S_CSR2.V = (mode_64bit     << BP_I2S_CSR2_BIT64_MODE)  |
                   (sample_freq    << BP_I2S_CSR2_SAMPLE_FREQ) ;
  REG_I2S_CSR.V  = 1  << BP_I2S_CSR_I2S_EN ;
  return eI2sConfigGood;
}
tI2sConfigRetVal EtaCspI2sConfig ( tI2sConfig i2sConfig ) { uint32_t tempdata0 ; uint32_t ui32MboxWord ; ui32MboxWord = i2sConfig . packed_config ; #ifdef ETA_CSP_I2S_DEBUG_PRINT ETA_DIAGS_PRINTF ( " \r \n " , i2sConfig . packed_config ) ; ETA_DIAGS_PRINTF ( " \r \n " , i2sConfig . fields . enable_rx ) ; ETA_DIAGS_PRINTF ( " \r \n " , i2sConfig . fields . enable_tx ) ; ETA_DIAGS_PRINTF ( " \r \n " , i2sConfig . fields . swap_chan_tx ) ; ETA_DIAGS_PRINTF ( " \r \n " , i2sConfig . fields . swap_chan_rx ) ; ETA_DIAGS_PRINTF ( " \r \n " , i2sConfig . fields . mode_64bit ) ; ETA_DIAGS_PRINTF ( " \r \n " , i2sConfig . fields . edge_tx_trig ) ; ETA_DIAGS_PRINTF ( " \r \n " , i2sConfig . fields . edge_rx_trig ) ; ETA_DIAGS_PRINTF ( " \r \n " , i2sConfig . fields . clock_src ) ; ETA_DIAGS_PRINTF ( " \r \n " , i2sConfig . fields . sample_freq ) ; ETA_DIAGS_PRINTF ( " \r \n " , i2sConfig . fields . chan_tx_config ) ; ETA_DIAGS_PRINTF ( " \r \n " , i2sConfig . fields . chan_rx_config ) ; ETA_DIAGS_PRINTF ( " \r \n " , i2sConfig . fields . chan_tx_upscale ) ; ETA_DIAGS_PRINTF ( " \r \n " , i2sConfig . fields . chan_rx_upscale ) ; ETA_DIAGS_PRINTF ( " \r \n " , i2sConfig . fields . int_mode ) ; #endif uint32_t enable_rx = ( ( ui32MboxWord & BM_ETA_CSP_COMMON_I2S_RX_ENBLE ) >> BP_ETA_CSP_COMMON_I2S_RX_ENBLE ) ; uint32_t enable_tx = ( ( ui32MboxWord & BM_ETA_CSP_COMMON_I2S_TX_ENBLE ) >> BP_ETA_CSP_COMMON_I2S_TX_ENBLE ) ; uint32_t mode_64bit = ( ( ui32MboxWord & BM_ETA_CSP_COMMON_I2S_64B_MODE ) >> BP_ETA_CSP_COMMON_I2S_64B_MODE ) ; uint32_t clock_src = ( ( ui32MboxWord & BM_ETA_CSP_COMMON_I2S_CLCK_SRC ) >> BP_ETA_CSP_COMMON_I2S_CLCK_SRC ) ; uint32_t sample_freq = ( ( ui32MboxWord & BM_ETA_CSP_COMMON_I2S_SMPL_FRQ ) >> BP_ETA_CSP_COMMON_I2S_SMPL_FRQ ) ; switch ( clock_src ) { case ( eI2sClkSrc2MhzXtal ) : REG_M1 ( RTC_OSC_CSR2 , VHFO_PD_N , 1 ) ; REG_GPIO_DEBUG0_READ_ONLY . V = REG_SOCCTRL_PMUXB . V ; REG_M1 ( SOCCTRL_CLK_CFG , ADC_CLK_SEL , BFV_SOCCTRL_CLK_CFG_ADC_CLK_SEL_2MHZ_XTAL ) ; break ; case ( eI2sClkSrc2MhzHfo ) : REG_M1 ( SOCCTRL_CLK_CFG , ADC_CLK_SEL , BFV_SOCCTRL_CLK_CFG_ADC_CLK_SEL_2MHZ_HFO ) ; break ; case ( eI2sClkSrc1MhzHfo ) : REG_M1 ( SOCCTRL_CLK_CFG , ADC_CLK_SEL , BFV_SOCCTRL_CLK_CFG_ADC_CLK_SEL_1MHZ_HFO ) ; break ; case ( eI2sClkSrcFromPad ) : tempdata0 = REG_SOCCTRL_PMUXB . V ; tempdata0 &= ~ ( BM_SOCCTRL_PMUXB_GPIO12 ) ; tempdata0 |= ( BFV_SOCCTRL_PMUXB_GPIO12_I2S_ACLK << BP_SOCCTRL_PMUXB_GPIO12 ) ; REG_SOCCTRL_PMUXB . V = tempdata0 ; REG_GPIO_DEBUG0_READ_ONLY . V = REG_SOCCTRL_PMUXB . V ; REG_M1 ( SOCCTRL_CLK_CFG , ADC_CLK_SEL , BFV_SOCCTRL_CLK_CFG_ADC_CLK_SEL_2MHZ_PAD ) ; break ; default : return ( eI2sConfigInvalidClkSource ) ; break ; } if ( enable_tx && enable_rx ) { #ifdef ETA_CSP_I2S_DEBUG_PRINT ETA_DIAGS_PRINTF ( " \r \n " ) ; #endif tempdata0 = REG_SOCCTRL_PMUXC . V ; tempdata0 &= ~ BM_SOCCTRL_PMUXC_GPIO16 ; tempdata0 |= BFV_SOCCTRL_PMUXC_GPIO16_I2S_DATA_OUT << BP_SOCCTRL_PMUXC_GPIO16 ; REG_SOCCTRL_PMUXC . V = tempdata0 ; tempdata0 = REG_SOCCTRL_PMUXB . V ; tempdata0 &= ~ ( BM_SOCCTRL_PMUXB_GPIO15 | BM_SOCCTRL_PMUXB_GPIO14 | BM_SOCCTRL_PMUXB_GPIO13 ) ; tempdata0 |= ( BFV_SOCCTRL_PMUXB_GPIO15_I2S_DATA_IN << BP_SOCCTRL_PMUXB_GPIO15 ) | ( BFV_SOCCTRL_PMUXB_GPIO14_I2S_LRCLK << BP_SOCCTRL_PMUXB_GPIO14 ) | ( BFV_SOCCTRL_PMUXB_GPIO13_I2S_BCLK << BP_SOCCTRL_PMUXB_GPIO13 ) ; REG_SOCCTRL_PMUXB . V = tempdata0 ; } else if ( enable_rx ) { #ifdef ETA_CSP_I2S_DEBUG_PRINT ETA_DIAGS_PRINTF ( " \r \n " ) ; #endif tempdata0 = REG_SOCCTRL_PMUXB . V ; tempdata0 &= ~ ( BM_SOCCTRL_PMUXB_GPIO15 | BM_SOCCTRL_PMUXB_GPIO14 | BM_SOCCTRL_PMUXB_GPIO13 ) ; tempdata0 |= ( BFV_SOCCTRL_PMUXB_GPIO15_I2S_DATA_IN << BP_SOCCTRL_PMUXB_GPIO15 ) | ( BFV_SOCCTRL_PMUXB_GPIO14_I2S_LRCLK << BP_SOCCTRL_PMUXB_GPIO14 ) | ( BFV_SOCCTRL_PMUXB_GPIO13_I2S_BCLK << BP_SOCCTRL_PMUXB_GPIO13 ) ; REG_SOCCTRL_PMUXB . V = tempdata0 ; } else if ( enable_tx ) { #ifdef ETA_CSP_I2S_DEBUG_PRINT ETA_DIAGS_PRINTF ( " \r \n " ) ; #endif tempdata0 = REG_SOCCTRL_PMUXC . V ; tempdata0 &= ~ BM_SOCCTRL_PMUXC_GPIO16 ; tempdata0 |= BFV_SOCCTRL_PMUXC_GPIO16_I2S_DATA_OUT << BP_SOCCTRL_PMUXC_GPIO16 ; REG_SOCCTRL_PMUXC . V = tempdata0 ; tempdata0 = REG_SOCCTRL_PMUXB . V ; tempdata0 &= ~ ( BM_SOCCTRL_PMUXB_GPIO14 | BM_SOCCTRL_PMUXB_GPIO13 ) ; tempdata0 |= ( BFV_SOCCTRL_PMUXB_GPIO14_I2S_LRCLK << BP_SOCCTRL_PMUXB_GPIO14 ) | ( BFV_SOCCTRL_PMUXB_GPIO13_I2S_BCLK << BP_SOCCTRL_PMUXB_GPIO13 ) ; REG_SOCCTRL_PMUXB . V = tempdata0 ; } REG_GPIO_DEBUG0_READ_ONLY . V = REG_SOCCTRL_PMUXB . V ; REG_I2S_CSR2 . V = ( mode_64bit << BP_I2S_CSR2_BIT64_MODE ) | ( sample_freq << BP_I2S_CSR2_SAMPLE_FREQ ) ; REG_I2S_CSR . V = 1 << BP_I2S_CSR_I2S_EN ; return eI2sConfigGood ; }
EtaCspI2sConfig - Initialize the I2S module.
EtaCspI2sConfig - Initialize the I2S module .
// ETA_CSP_I2S_DEBUG_PRINT //uint32_t swap_chan_tx    = ((ui32MboxWord & BM_ETA_CSP_COMMON_I2S_TX_SWP_C) >> BP_ETA_CSP_COMMON_I2S_TX_SWP_C); //uint32_t swap_chan_rx    = ((ui32MboxWord & BM_ETA_CSP_COMMON_I2S_RX_SWP_C) >> BP_ETA_CSP_COMMON_I2S_RX_SWP_C); //uint32_t edge_tx_trig    = ((ui32MboxWord & BM_ETA_CSP_COMMON_I2S_TX_ED_TR) >> BP_ETA_CSP_COMMON_I2S_TX_ED_TR); //uint32_t edge_rx_trig    = ((ui32MboxWord & BM_ETA_CSP_COMMON_I2S_RX_ED_TR) >> BP_ETA_CSP_COMMON_I2S_RX_ED_TR); //uint32_t chan_tx_config  = ((ui32MboxWord & BM_ETA_CSP_COMMON_I2S_TX_CONFG) >> BP_ETA_CSP_COMMON_I2S_TX_CONFG); //uint32_t chan_rx_config  = ((ui32MboxWord & BM_ETA_CSP_COMMON_I2S_RX_CONFG) >> BP_ETA_CSP_COMMON_I2S_RX_CONFG); //uint32_t chan_tx_upscale = ((ui32MboxWord & BM_ETA_CSP_COMMON_I2S_TX_UPSCL) >> BP_ETA_CSP_COMMON_I2S_TX_UPSCL); //uint32_t chan_rx_upscale = ((ui32MboxWord & BM_ETA_CSP_COMMON_I2S_RX_UPSCL) >> BP_ETA_CSP_COMMON_I2S_RX_UPSCL); //uint32_t int_mode        = ((ui32MboxWord & BM_ETA_CSP_COMMON_I2S_INT_MODE) >> BP_ETA_CSP_COMMON_I2S_INT_MODE); /////////////////////////////////////////////// // Setup Clock Source //switch (i2sConfig.fields.clock_src) // Power up the 16MHz oscillator // Fence // Enable ACLK as input // Fence // Select ACLK as clock source // Setup Clock Source /////////////////////////////////////////////// /////////////////////////////////////////////// // Setup Pad Mux //if (i2sConfig.fields.enable_tx && i2sConfig.fields.enable_rx) // Enable BCLK, LRCLK, DATAOUT, DATAIN // Enable BCLK, LRCLK, DATAOUT, DATAIN // ETA_CSP_I2S_DEBUG_PRINT //else if (i2sConfig.fields.enable_rx) // Enable BCLK, LRCLK, DATAIN // Enable BCLK, LRCLK, DATAIN // ETA_CSP_I2S_DEBUG_PRINT //else if (i2sConfig.fields.enable_tx) // Enable BCLK, LRCLK, DATAOUT // Enable BCLK, LRCLK, DATAOUT // ETA_CSP_I2S_DEBUG_PRINT // Fence // Setup Pad Mux /////////////////////////////////////////////// /////////////////////////////////////////////// // Configure Actual I2S //  // Trigger gratuitous Soft Reset //  REG_I2S_CSR2.V = BM_I2S_CSR2_SFTRST ; //  while (REG_I2S_CSR2.V == BM_I2S_CSR2_SFTRST); //REG_I2S_CSR2.V = (i2sConfig.fields.mode_64bit     << BP_I2S_CSR2_BIT64_MODE)  | //                 (i2sConfig.fields.sample_freq    << BP_I2S_CSR2_SAMPLE_FREQ) ; // Configure Actual I2S ///////////////////////////////////////////////