src/dps8/dps8_iom.c
// 'write' means periperal write; i.e. the peripheral is writing to core after
// reading media.
'write' means periperal write; i.e. the peripheral is writing to core after
reading media.
' write ' means periperal write ; i . e . the peripheral is writing to core after reading media .
void iomDirectDataService (uint iomUnitIdx, uint chan, word36 * data,
                           bool write)
  {
    iomChanData_t * p = & iomChanData [iomUnitIdx] [chan];
    uint daddr = p -> DDCW_ADDR;
    switch (p -> chanMode)
      {
        case cm1e:
        case cm2e:
        case cm1:
          daddr |= (uint) p -> ADDR_EXT << 18;
          break;
        case cm2:
        case cm3b:
          {
sim_warn ("iomDirectDataService DCW paged\n");
          }
          break;
        case cm3a:
        case cm4:
        case cm5:
          {
            fetchDDSPTW (iomUnitIdx, (int) chan, daddr);
            daddr = ((uint) getbits36_14 (p -> PTW_DCW, 4) << 10) | (daddr & MASK8);
          }
          break;
      }
    if (write)
      iom_core_write (daddr, * data, __func__);
    else
      iom_core_read (daddr, data, __func__);
  }
void iomDirectDataService ( uint iomUnitIdx , uint chan , word36 * data , bool write ) { iomChanData_t * p = & iomChanData [ iomUnitIdx ] [ chan ] ; uint daddr = p -> DDCW_ADDR ; switch ( p -> chanMode ) { case cm1e : case cm2e : case cm1 : daddr |= ( uint ) p -> ADDR_EXT << 18 ; break ; case cm2 : case cm3b : { sim_warn ( " \n " ) ; } break ; case cm3a : case cm4 : case cm5 : { fetchDDSPTW ( iomUnitIdx , ( int ) chan , daddr ) ; daddr = ( ( uint ) getbits36_14 ( p -> PTW_DCW , 4 ) << 10 ) | ( daddr & MASK8 ) ; } break ; } if ( write ) iom_core_write ( daddr , * data , __func__ ) ; else iom_core_read ( daddr , data , __func__ ) ; }
'write' means periperal write; i.e.
' write ' means periperal write ; i . e .
// DCW EXT //sim_printf ("iomDirectDataService DCW segmented\n");