Src/main.c
/**
  * @brief TIM2 Initialization Function
  * @param None
  * @retval None
  */
@brief TIM2 Initialization Function
@param None
@retval None
@brief TIM2 Initialization Function @param None @retval None
static void MX_TIM2_Init(void)
{
  LL_TIM_InitTypeDef TIM_InitStruct = {0};
  LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2);
  LL_DMA_SetChannelSelection(DMA1, LL_DMA_STREAM_1, LL_DMA_CHANNEL_3);
  LL_DMA_SetDataTransferDirection(DMA1, LL_DMA_STREAM_1, LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
  LL_DMA_SetStreamPriorityLevel(DMA1, LL_DMA_STREAM_1, LL_DMA_PRIORITY_MEDIUM);
  LL_DMA_SetMode(DMA1, LL_DMA_STREAM_1, LL_DMA_MODE_CIRCULAR);
  LL_DMA_SetPeriphIncMode(DMA1, LL_DMA_STREAM_1, LL_DMA_PERIPH_NOINCREMENT);
  LL_DMA_SetMemoryIncMode(DMA1, LL_DMA_STREAM_1, LL_DMA_MEMORY_INCREMENT);
  LL_DMA_SetPeriphSize(DMA1, LL_DMA_STREAM_1, LL_DMA_PDATAALIGN_HALFWORD);
  LL_DMA_SetMemorySize(DMA1, LL_DMA_STREAM_1, LL_DMA_MDATAALIGN_HALFWORD);
  LL_DMA_DisableFifoMode(DMA1, LL_DMA_STREAM_1);
  NVIC_SetPriority(TIM2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),0, 0));
  NVIC_EnableIRQ(TIM2_IRQn);
  TIM_InitStruct.Prescaler = 0;
  TIM_InitStruct.CounterMode = LL_TIM_COUNTERMODE_UP;
  TIM_InitStruct.Autoreload = 1000;
  TIM_InitStruct.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
  LL_TIM_Init(TIM2, &TIM_InitStruct);
  LL_TIM_DisableARRPreload(TIM2);
  LL_TIM_SetClockSource(TIM2, LL_TIM_CLOCKSOURCE_INTERNAL);
  LL_TIM_SetTriggerOutput(TIM2, LL_TIM_TRGO_UPDATE);
  LL_TIM_DisableMasterSlaveMode(TIM2);
	LL_TIM_EnableDMAReq_UPDATE( TIM2 );
	LL_TIM_EnableIT_UPDATE( TIM2 );
}
static void MX_TIM2_Init ( void ) { LL_TIM_InitTypeDef TIM_InitStruct = { 0 } ; LL_APB1_GRP1_EnableClock ( LL_APB1_GRP1_PERIPH_TIM2 ) ; LL_DMA_SetChannelSelection ( DMA1 , LL_DMA_STREAM_1 , LL_DMA_CHANNEL_3 ) ; LL_DMA_SetDataTransferDirection ( DMA1 , LL_DMA_STREAM_1 , LL_DMA_DIRECTION_MEMORY_TO_PERIPH ) ; LL_DMA_SetStreamPriorityLevel ( DMA1 , LL_DMA_STREAM_1 , LL_DMA_PRIORITY_MEDIUM ) ; LL_DMA_SetMode ( DMA1 , LL_DMA_STREAM_1 , LL_DMA_MODE_CIRCULAR ) ; LL_DMA_SetPeriphIncMode ( DMA1 , LL_DMA_STREAM_1 , LL_DMA_PERIPH_NOINCREMENT ) ; LL_DMA_SetMemoryIncMode ( DMA1 , LL_DMA_STREAM_1 , LL_DMA_MEMORY_INCREMENT ) ; LL_DMA_SetPeriphSize ( DMA1 , LL_DMA_STREAM_1 , LL_DMA_PDATAALIGN_HALFWORD ) ; LL_DMA_SetMemorySize ( DMA1 , LL_DMA_STREAM_1 , LL_DMA_MDATAALIGN_HALFWORD ) ; LL_DMA_DisableFifoMode ( DMA1 , LL_DMA_STREAM_1 ) ; NVIC_SetPriority ( TIM2_IRQn , NVIC_EncodePriority ( NVIC_GetPriorityGrouping ( ) , 0 , 0 ) ) ; NVIC_EnableIRQ ( TIM2_IRQn ) ; TIM_InitStruct . Prescaler = 0 ; TIM_InitStruct . CounterMode = LL_TIM_COUNTERMODE_UP ; TIM_InitStruct . Autoreload = 1000 ; TIM_InitStruct . ClockDivision = LL_TIM_CLOCKDIVISION_DIV1 ; LL_TIM_Init ( TIM2 , & TIM_InitStruct ) ; LL_TIM_DisableARRPreload ( TIM2 ) ; LL_TIM_SetClockSource ( TIM2 , LL_TIM_CLOCKSOURCE_INTERNAL ) ; LL_TIM_SetTriggerOutput ( TIM2 , LL_TIM_TRGO_UPDATE ) ; LL_TIM_DisableMasterSlaveMode ( TIM2 ) ; LL_TIM_EnableDMAReq_UPDATE ( TIM2 ) ; LL_TIM_EnableIT_UPDATE ( TIM2 ) ; }
@brief TIM2 Initialization Function
 @param None
 @retval None
@brief TIM2 Initialization Function @param None @retval None
/* USER CODE BEGIN TIM2_Init 0 */ /* USER CODE END TIM2_Init 0 */ /* Peripheral clock enable */ /* TIM2 DMA Init */ /* TIM2_UP_CH3 Init */ /* TIM2 interrupt Init */ /* USER CODE BEGIN TIM2_Init 1 */ /* USER CODE END TIM2_Init 1 */ /* USER CODE BEGIN TIM2_Init 2 */ /* USER CODE END TIM2_Init 2 */