FreeBSD/sys/dev/cxgbe/common/t4_hw.c
/**
 *	t4_wol_pat_enable - enable/disable pattern-based WoL
 *	@adap: the adapter
 *	@port: the physical port index
 *	@map: bitmap of which HW pattern filters to set
 *	@mask0: byte mask for bytes 0-63 of a packet
 *	@mask1: byte mask for bytes 64-127 of a packet
 *	@crc: Ethernet CRC for selected bytes
 *	@enable: enable/disable switch
 *
 *	Sets the pattern filters indicated in @map to mask out the bytes
 *	specified in @mask0/@mask1 in received packets and compare the CRC of
 *	the resulting packet against @crc.  If @enable is %true pattern-based
 *	WoL is enabled, otherwise disabled.
 */


Sets the pattern filters indicated in @map to mask out the bytes
specified in @mask0/@mask1 in received packets and compare the CRC of
the resulting packet against @crc.  If @enable is %true pattern-based
WoL is enabled, otherwise disabled.
Sets the pattern filters indicated in @map to mask out the bytes specified in @mask0 / @mask1 in received packets and compare the CRC of the resulting packet against @crc . If @enable is %true pattern - based WoL is enabled otherwise disabled .
int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
		      u64 mask0, u64 mask1, unsigned int crc, bool enable)
{
	int i;
	u32 port_cfg_reg;
	if (is_t4(adap))
		port_cfg_reg = PORT_REG(port, A_XGMAC_PORT_CFG2);
	else
		port_cfg_reg = T5_PORT_REG(port, A_MAC_PORT_CFG2);
	if (!enable) {
		t4_set_reg_field(adap, port_cfg_reg, F_PATEN, 0);
		return 0;
	}
	if (map > 0xff)
		return -EINVAL;
#define EPIO_REG(name) \
	(is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \
	T5_PORT_REG(port, A_MAC_PORT_EPIO_##name))
	t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32);
	t4_write_reg(adap, EPIO_REG(DATA2), mask1);
	t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32);
	for (i = 0; i < NWOL_PAT; i++, map >>= 1) {
		if (!(map & 1))
			continue;
		t4_write_reg(adap, EPIO_REG(DATA0), mask0);
		t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i) | F_EPIOWR);
		t4_read_reg(adap, EPIO_REG(OP));                
		if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)
			return -ETIMEDOUT;
		t4_write_reg(adap, EPIO_REG(DATA0), crc);
		t4_write_reg(adap, EPIO_REG(OP), V_ADDRESS(i + 32) | F_EPIOWR);
		t4_read_reg(adap, EPIO_REG(OP));                
		if (t4_read_reg(adap, EPIO_REG(OP)) & F_BUSY)
			return -ETIMEDOUT;
	}
#undef EPIO_REG
	t4_set_reg_field(adap, port_cfg_reg, 0, F_PATEN);
	return 0;
}
int t4_wol_pat_enable ( struct adapter * adap , unsigned int port , unsigned int map , u64 mask0 , u64 mask1 , unsigned int crc , bool enable ) { int i ; u32 port_cfg_reg ; if ( is_t4 ( adap ) ) port_cfg_reg = PORT_REG ( port , A_XGMAC_PORT_CFG2 ) ; else port_cfg_reg = T5_PORT_REG ( port , A_MAC_PORT_CFG2 ) ; if ( ! enable ) { t4_set_reg_field ( adap , port_cfg_reg , F_PATEN , 0 ) ; return 0 ; } if ( map > 0xff ) return - EINVAL ; #define EPIO_REG ( name )  \
	(is_t4(adap) ? PORT_REG(port, A_XGMAC_PORT_EPIO_##name) : \
	T5_PORT_REG(port, A_MAC_PORT_EPIO_##name)) t4_write_reg ( adap , EPIO_REG ( DATA1 ) , mask0 >> 32 ) ; t4_write_reg ( adap , EPIO_REG ( DATA2 ) , mask1 ) ; t4_write_reg ( adap , EPIO_REG ( DATA3 ) , mask1 >> 32 ) ; for ( i = 0 ; i < NWOL_PAT ; i ++ , map >>= 1 ) { if ( ! ( map & 1 ) ) continue ; t4_write_reg ( adap , EPIO_REG ( DATA0 ) , mask0 ) ; t4_write_reg ( adap , EPIO_REG ( OP ) , V_ADDRESS ( i ) | F_EPIOWR ) ; t4_read_reg ( adap , EPIO_REG ( OP ) ) ; if ( t4_read_reg ( adap , EPIO_REG ( OP ) ) & F_BUSY ) return - ETIMEDOUT ; t4_write_reg ( adap , EPIO_REG ( DATA0 ) , crc ) ; t4_write_reg ( adap , EPIO_REG ( OP ) , V_ADDRESS ( i + 32 ) | F_EPIOWR ) ; t4_read_reg ( adap , EPIO_REG ( OP ) ) ; if ( t4_read_reg ( adap , EPIO_REG ( OP ) ) & F_BUSY ) return - ETIMEDOUT ; } #undef  EPIO_REG t4_set_reg_field ( adap , port_cfg_reg , 0 , F_PATEN ) ; return 0 ; }
t4_wol_pat_enable - enable/disable pattern-based WoL
      @adap: the adapter
      @port: the physical port index
      @map: bitmap of which HW pattern filters to set
      @mask0: byte mask for bytes 0-63 of a packet
      @mask1: byte mask for bytes 64-127 of a packet
      @crc: Ethernet CRC for selected bytes
      @enable: enable/disable switch
t4_wol_pat_enable - enable / disable pattern - based WoL @adap : the adapter @port : the physical port index @map : bitmap of which HW pattern filters to set @mask0 : byte mask for bytes 0 - 63 of a packet @mask1 : byte mask for bytes 64 - 127 of a packet @crc : Ethernet CRC for selected bytes @enable : enable / disable switch
/* write byte masks */ /* flush */ /* write CRC */ /* flush */