FreeBSD/sys/amd64/vmm/intel/vmx.c
/*
 * vlapic->ops handlers that utilize the APICv hardware assist described in
 * Chapter 29 of the Intel SDM.
 */
vlapic->ops handlers that utilize the APICv hardware assist described in
Chapter 29 of the Intel SDM.
vlapic - > ops handlers that utilize the APICv hardware assist described in Chapter 29 of the Intel SDM .
static int
vmx_set_intr_ready(struct vlapic *vlapic, int vector, bool level)
{
	struct vlapic_vtx *vlapic_vtx;
	struct pir_desc *pir_desc;
	uint64_t mask;
	int idx, notify;
	vlapic_vtx = (struct vlapic_vtx *)vlapic;
	pir_desc = vlapic_vtx->pir_desc;
	idx = vector / 64;
	mask = 1UL << (vector % 64);
	atomic_set_long(&pir_desc->pir[idx], mask);
	notify = atomic_cmpset_long(&pir_desc->pending, 0, 1);
	VMX_CTR_PIR(vlapic->vm, vlapic->vcpuid, pir_desc, notify, vector,
	    level, "vmx_set_intr_ready");
	return (notify);
}
static int vmx_set_intr_ready ( struct vlapic * vlapic , int vector , bool level ) { struct vlapic_vtx * vlapic_vtx ; struct pir_desc * pir_desc ; uint64_t mask ; int idx , notify ; vlapic_vtx = ( struct vlapic_vtx * ) vlapic ; pir_desc = vlapic_vtx -> pir_desc ; idx = vector / 64 ; mask = 1UL << ( vector % 64 ) ; atomic_set_long ( & pir_desc -> pir [ idx ] , mask ) ; notify = atomic_cmpset_long ( & pir_desc -> pending , 0 , 1 ) ; VMX_CTR_PIR ( vlapic -> vm , vlapic -> vcpuid , pir_desc , notify , vector , level , " " ) ; return ( notify ) ; }
vlapic->ops handlers that utilize the APICv hardware assist described in
 Chapter 29 of the Intel SDM.
vlapic - > ops handlers that utilize the APICv hardware assist described in Chapter 29 of the Intel SDM .
/*
	 * Keep track of interrupt requests in the PIR descriptor. This is
	 * because the virtual APIC page pointed to by the VMCS cannot be
	 * modified if the vcpu is running.
	 */