qemu/target/hppa/translate.c
/* Similar, but for unit conditions.  */
Similar, but for unit conditions.
Similar but for unit conditions .
static DisasCond do_unit_cond(unsigned cf, TCGv_reg res,
                              TCGv_reg in1, TCGv_reg in2)
{
    DisasCond cond;
    TCGv_reg tmp, cb = NULL;
    if (cf & 8) {
        cb = tcg_temp_new();
        tmp = tcg_temp_new();
        tcg_gen_or_reg(cb, in1, in2);
        tcg_gen_and_reg(tmp, in1, in2);
        tcg_gen_andc_reg(cb, cb, res);
        tcg_gen_or_reg(cb, cb, tmp);
        tcg_temp_free(tmp);
    }
    switch (cf >> 1) {
    case 0: 
    case 1: 
    case 5: 
        cond = cond_make_f();
        break;
    case 2: 
        tmp = tcg_temp_new();
        tcg_gen_subi_reg(tmp, res, 0x01010101u);
        tcg_gen_andc_reg(tmp, tmp, res);
        tcg_gen_andi_reg(tmp, tmp, 0x80808080u);
        cond = cond_make_0(TCG_COND_NE, tmp);
        tcg_temp_free(tmp);
        break;
    case 3: 
        tmp = tcg_temp_new();
        tcg_gen_subi_reg(tmp, res, 0x00010001u);
        tcg_gen_andc_reg(tmp, tmp, res);
        tcg_gen_andi_reg(tmp, tmp, 0x80008000u);
        cond = cond_make_0(TCG_COND_NE, tmp);
        tcg_temp_free(tmp);
        break;
    case 4: 
        tcg_gen_andi_reg(cb, cb, 0x88888888u);
        cond = cond_make_0(TCG_COND_NE, cb);
        break;
    case 6: 
        tcg_gen_andi_reg(cb, cb, 0x80808080u);
        cond = cond_make_0(TCG_COND_NE, cb);
        break;
    case 7: 
        tcg_gen_andi_reg(cb, cb, 0x80008000u);
        cond = cond_make_0(TCG_COND_NE, cb);
        break;
    default:
        g_assert_not_reached();
    }
    if (cf & 8) {
        tcg_temp_free(cb);
    }
    if (cf & 1) {
        cond.c = tcg_invert_cond(cond.c);
    }
    return cond;
}
static DisasCond do_unit_cond ( unsigned cf , TCGv_reg res , TCGv_reg in1 , TCGv_reg in2 ) { DisasCond cond ; TCGv_reg tmp , cb = NULL ; if ( cf & 8 ) { cb = tcg_temp_new ( ) ; tmp = tcg_temp_new ( ) ; tcg_gen_or_reg ( cb , in1 , in2 ) ; tcg_gen_and_reg ( tmp , in1 , in2 ) ; tcg_gen_andc_reg ( cb , cb , res ) ; tcg_gen_or_reg ( cb , cb , tmp ) ; tcg_temp_free ( tmp ) ; } switch ( cf >> 1 ) { case 0 : case 1 : case 5 : cond = cond_make_f ( ) ; break ; case 2 : tmp = tcg_temp_new ( ) ; tcg_gen_subi_reg ( tmp , res , 0x01010101u ) ; tcg_gen_andc_reg ( tmp , tmp , res ) ; tcg_gen_andi_reg ( tmp , tmp , 0x80808080u ) ; cond = cond_make_0 ( TCG_COND_NE , tmp ) ; tcg_temp_free ( tmp ) ; break ; case 3 : tmp = tcg_temp_new ( ) ; tcg_gen_subi_reg ( tmp , res , 0x00010001u ) ; tcg_gen_andc_reg ( tmp , tmp , res ) ; tcg_gen_andi_reg ( tmp , tmp , 0x80008000u ) ; cond = cond_make_0 ( TCG_COND_NE , tmp ) ; tcg_temp_free ( tmp ) ; break ; case 4 : tcg_gen_andi_reg ( cb , cb , 0x88888888u ) ; cond = cond_make_0 ( TCG_COND_NE , cb ) ; break ; case 6 : tcg_gen_andi_reg ( cb , cb , 0x80808080u ) ; cond = cond_make_0 ( TCG_COND_NE , cb ) ; break ; case 7 : tcg_gen_andi_reg ( cb , cb , 0x80008000u ) ; cond = cond_make_0 ( TCG_COND_NE , cb ) ; break ; default : g_assert_not_reached ( ) ; } if ( cf & 8 ) { tcg_temp_free ( cb ) ; } if ( cf & 1 ) { cond . c = tcg_invert_cond ( cond . c ) ; } return cond ; }
Similar, but for unit conditions.
Similar but for unit conditions .
/* Since we want to test lots of carry-out bits all at once, do not
         * do our normal thing and compute carry-in of bit B+1 since that
         * leaves us with carry bits spread across two words.
         */ /* never / TR */ /* undefined */ /* undefined */ /* SBZ / NBZ */ /* See hasless(v,1) from
         * https://graphics.stanford.edu/~seander/bithacks.html#ZeroInWord
         */ /* SHZ / NHZ */ /* SDC / NDC */ /* SBC / NBC */ /* SHC / NHC */