FreeBSD/sys/sparc64/sparc64/zeus.c
/*
 * CPU-specific initialization for Fujitsu Zeus CPUs
 */
CPU-specific initialization for Fujitsu Zeus CPUs
CPU - specific initialization for Fujitsu Zeus CPUs
void
zeus_init(u_int cpu_impl)
{
	u_long val;
	stxa(AA_DMMU_TSB_PEXT_REG, ASI_DMMU, 0);
	stxa(AA_IMMU_TSB_PEXT_REG, ASI_IMMU, 0);
	membar(Sync);
	stxa(AA_DMMU_TSB_SEXT_REG, ASI_DMMU, 0);
	membar(Sync);
	stxa(AA_DMMU_TSB_NEXT_REG, ASI_DMMU, 0);
	stxa(AA_IMMU_TSB_NEXT_REG, ASI_IMMU, 0);
	membar(Sync);
	val = ldxa(AA_MCNTL, ASI_MCNTL);
	val &= ~MCNTL_JPS1_TSBP;
	val = (val & ~MCNTL_RMD_MASK) | MCNTL_RMD_1024;
	stxa(AA_MCNTL, ASI_MCNTL, val);
}
void zeus_init ( u_int cpu_impl ) { u_long val ; stxa ( AA_DMMU_TSB_PEXT_REG , ASI_DMMU , 0 ) ; stxa ( AA_IMMU_TSB_PEXT_REG , ASI_IMMU , 0 ) ; membar ( Sync ) ; stxa ( AA_DMMU_TSB_SEXT_REG , ASI_DMMU , 0 ) ; membar ( Sync ) ; stxa ( AA_DMMU_TSB_NEXT_REG , ASI_DMMU , 0 ) ; stxa ( AA_IMMU_TSB_NEXT_REG , ASI_IMMU , 0 ) ; membar ( Sync ) ; val = ldxa ( AA_MCNTL , ASI_MCNTL ) ; val &= ~ MCNTL_JPS1_TSBP ; val = ( val & ~ MCNTL_RMD_MASK ) | MCNTL_RMD_1024 ; stxa ( AA_MCNTL , ASI_MCNTL , val ) ; }
CPU-specific initialization for Fujitsu Zeus CPUs
CPU - specific initialization for Fujitsu Zeus CPUs
/* Ensure the TSB Extension Registers hold 0 as TSB_Base. */ /*
	 * NB: the secondary context was removed from the iMMU.
	 */ /* Ensure MCNTL_JPS1_TSBP is 0. */ /*
	 * Ensure 4-Mbyte page entries are stored in the 1024-entry, 2-way set
	 * associative TLB.
	 */