FreeBSD/sys/x86/iommu/intel_utils.c
/*
 * Globally invalidate the context entries cache, busily waiting for
 * the completion.
 */
Globally invalidate the context entries cache, busily waiting for
the completion.
Globally invalidate the context entries cache busily waiting for the completion .
int
dmar_inv_ctx_glob(struct dmar_unit *unit)
{
	DMAR_ASSERT_LOCKED(unit);
	KASSERT(!unit->qi_enabled, ("QI enabled"));
	dmar_write8(unit, DMAR_CCMD_REG, DMAR_CCMD_ICC | DMAR_CCMD_CIRG_GLOB);
	while ((dmar_read4(unit, DMAR_CCMD_REG + 4) & DMAR_CCMD_ICC32) != 0)
		cpu_spinwait();
	return (0);
}
int dmar_inv_ctx_glob ( struct dmar_unit * unit ) { DMAR_ASSERT_LOCKED ( unit ) ; KASSERT ( ! unit -> qi_enabled , ( " " ) ) ; dmar_write8 ( unit , DMAR_CCMD_REG , DMAR_CCMD_ICC | DMAR_CCMD_CIRG_GLOB ) ; while ( ( dmar_read4 ( unit , DMAR_CCMD_REG + 4 ) & DMAR_CCMD_ICC32 ) != 0 ) cpu_spinwait ( ) ; return ( 0 ) ; }
Globally invalidate the context entries cache, busily waiting for
 the completion.
Globally invalidate the context entries cache busily waiting for the completion .
/*
	 * Access to the CCMD register must be serialized while the
	 * command is submitted.
	 */ /*
	 * The DMAR_CCMD_ICC bit in the upper dword should be written
	 * after the low dword write is completed.  Amd64
	 * dmar_write8() does not have this issue, i386 dmar_write8()
	 * writes the upper dword last.
	 */ /* XXXKIB should have a timeout */