FreeBSD/sys/dev/mxge/if_mxge.c
/*
 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
 * when the PCI-E Completion packets are aligned on an 8-byte
 * boundary.  Some PCI-E chip sets always align Completion packets; on
 * the ones that do not, the alignment can be enforced by enabling
 * ECRC generation (if supported).
 *
 * When PCI-E Completion packets are not aligned, it is actually more
 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
 *
 * If the driver can neither enable ECRC nor verify that it has
 * already been enabled, then it must use a firmware image which works
 * around unaligned completion packets (ethp_z8e.dat), and it should
 * also ensure that it never gives the device a Read-DMA which is
 * larger than 2KB by setting the tx_boundary to 2KB.  If ECRC is
 * enabled, then the driver should use the aligned (eth_z8e.dat)
 * firmware image, and set tx_boundary to 4KB.
 */
The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
when the PCI-E Completion packets are aligned on an 8-byte
boundary.  Some PCI-E chip sets always align Completion packets; on
the ones that do not, the alignment can be enforced by enabling
ECRC generation (if supported).

When PCI-E Completion packets are not aligned, it is actually more
efficient to limit Read-DMA transactions to 2KB, rather than 4KB.

If the driver can neither enable ECRC nor verify that it has
already been enabled, then it must use a firmware image which works
around unaligned completion packets (ethp_z8e.dat), and it should
also ensure that it never gives the device a Read-DMA which is
larger than 2KB by setting the tx_boundary to 2KB.  If ECRC is
enabled, then the driver should use the aligned (eth_z8e.dat)
firmware image, and set tx_boundary to 4KB.
The Lanai Z8E PCI - E interface achieves higher Read - DMA throughput when the PCI - E Completion packets are aligned on an 8 - byte boundary . Some PCI - E chip sets always align Completion packets ; on the ones that do not the alignment can be enforced by enabling ECRC generation ( if supported ) . When PCI - E Completion packets are not aligned it is actually more efficient to limit Read - DMA transactions to 2KB rather than 4KB . If the driver can neither enable ECRC nor verify that it has already been enabled then it must use a firmware image which works around unaligned completion packets ( ethp_z8e . dat ) and it should also ensure that it never gives the device a Read - DMA which is larger than 2KB by setting the tx_boundary to 2KB . If ECRC is enabled then the driver should use the aligned ( eth_z8e . dat ) firmware image and set tx_boundary to 4KB .
static int
mxge_firmware_probe(mxge_softc_t *sc)
{
	device_t dev = sc->dev;
	int reg, status;
	uint16_t pectl;
	sc->tx_boundary = 4096;
	if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {
		pectl = pci_read_config(dev, reg + 0x8, 2);
		if ((pectl & (5 << 12)) != (5 << 12)) {
			device_printf(dev, "Max Read Req. size != 4k (0x%x\n",
				      pectl);
			sc->tx_boundary = 2048;
		}
	}
	sc->fw_name = mxge_fw_aligned;
	status = mxge_load_firmware(sc, 1);
	if (status != 0) {
		return status;
	}
	mxge_enable_nvidia_ecrc(sc);
	if (pci_get_revid(sc->dev) >= MXGE_PCI_REV_Z8ES)
		return 0;
	status = mxge_dma_test(sc, MXGEFW_CMD_UNALIGNED_TEST);
	if (status == 0)
		return 0; 
	if (status != E2BIG)
		device_printf(dev, "DMA test failed: %d\n", status);
	if (status == ENOSYS)
		device_printf(dev, "Falling back to ethp! "
			      "Please install up to date fw\n");
	return status;
}
static int mxge_firmware_probe ( mxge_softc_t * sc ) { device_t dev = sc -> dev ; int reg , status ; uint16_t pectl ; sc -> tx_boundary = 4096 ; if ( pci_find_cap ( dev , PCIY_EXPRESS , & reg ) == 0 ) { pectl = pci_read_config ( dev , reg + 0x8 , 2 ) ; if ( ( pectl & ( 5 << 12 ) ) != ( 5 << 12 ) ) { device_printf ( dev , " \n " , pectl ) ; sc -> tx_boundary = 2048 ; } } sc -> fw_name = mxge_fw_aligned ; status = mxge_load_firmware ( sc , 1 ) ; if ( status != 0 ) { return status ; } mxge_enable_nvidia_ecrc ( sc ) ; if ( pci_get_revid ( sc -> dev ) >= MXGE_PCI_REV_Z8ES ) return 0 ; status = mxge_dma_test ( sc , MXGEFW_CMD_UNALIGNED_TEST ) ; if ( status == 0 ) return 0 ; if ( status != E2BIG ) device_printf ( dev , " \n " , status ) ; if ( status == ENOSYS ) device_printf ( dev , " " " \n " ) ; return status ; }
The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
 when the PCI-E Completion packets are aligned on an 8-byte
 boundary.
The Lanai Z8E PCI - E interface achieves higher Read - DMA throughput when the PCI - E Completion packets are aligned on an 8 - byte boundary .
/*
	 * Verify the max read request size was set to 4KB
	 * before trying the test with 4KB.
	 */ /*
	 * load the optimized firmware (which assumes aligned PCIe
	 * completions) in order to see if it works on this host.
	 */ /*
	 * Enable ECRC if possible
	 */ /*
	 * Run a DMA test which watches for unaligned completions and
	 * aborts on the first one seen.  Not required on Z8ES or newer.
	 */ /* keep the aligned firmware */