sys/dev/cxgbe/common/t4_hw.c
/**
 *	t4_edc_read - read from EDC through backdoor accesses
 *	@adap: the adapter
 *	@idx: which EDC to access
 *	@addr: address of first byte requested
 *	@data: 64 bytes of data containing the requested address
 *	@ecc: where to store the corresponding 64-bit ECC word
 *
 *	Read 64 bytes of data from EDC starting at a 64-byte-aligned address
 *	that covers the requested address @addr.  If @parity is not %NULL it
 *	is assigned the 64-bit ECC word for the read data.
 */


Read 64 bytes of data from EDC starting at a 64-byte-aligned address
that covers the requested address @addr.  If @parity is not %NULL it
is assigned the 64-bit ECC word for the read data.
Read 64 bytes of data from EDC starting at a 64 - byte - aligned address that covers the requested address @addr . If @parity is not %NULL it is assigned the 64 - bit ECC word for the read data .
int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
{
	int i;
	u32 edc_bist_cmd_reg, edc_bist_cmd_addr_reg, edc_bist_cmd_len_reg;
	u32 edc_bist_cmd_data_pattern, edc_bist_status_rdata_reg;
	if (is_t4(adap)) {
		edc_bist_cmd_reg = EDC_REG(A_EDC_BIST_CMD, idx);
		edc_bist_cmd_addr_reg = EDC_REG(A_EDC_BIST_CMD_ADDR, idx);
		edc_bist_cmd_len_reg = EDC_REG(A_EDC_BIST_CMD_LEN, idx);
		edc_bist_cmd_data_pattern = EDC_REG(A_EDC_BIST_DATA_PATTERN,
						    idx);
		edc_bist_status_rdata_reg = EDC_REG(A_EDC_BIST_STATUS_RDATA,
						    idx);
	} else {
#define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
#define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
		edc_bist_cmd_reg = EDC_REG_T5(A_EDC_H_BIST_CMD, idx);
		edc_bist_cmd_addr_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_ADDR, idx);
		edc_bist_cmd_len_reg = EDC_REG_T5(A_EDC_H_BIST_CMD_LEN, idx);
		edc_bist_cmd_data_pattern = EDC_REG_T5(A_EDC_H_BIST_DATA_PATTERN,
						    idx);
		edc_bist_status_rdata_reg = EDC_REG_T5(A_EDC_H_BIST_STATUS_RDATA,
						    idx);
#undef EDC_REG_T5
#undef EDC_STRIDE_T5
	}
	if (t4_read_reg(adap, edc_bist_cmd_reg) & F_START_BIST)
		return -EBUSY;
	t4_write_reg(adap, edc_bist_cmd_addr_reg, addr & ~0x3fU);
	t4_write_reg(adap, edc_bist_cmd_len_reg, 64);
	t4_write_reg(adap, edc_bist_cmd_data_pattern, 0xc);
	t4_write_reg(adap, edc_bist_cmd_reg,
		     V_BIST_OPCODE(1) | V_BIST_CMD_GAP(1) | F_START_BIST);
	i = t4_wait_op_done(adap, edc_bist_cmd_reg, F_START_BIST, 0, 10, 1);
	if (i)
		return i;
#define EDC_DATA(i) EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i)
	for (i = 15; i >= 0; i--)
		*data++ = ntohl(t4_read_reg(adap, EDC_DATA(i)));
	if (ecc)
		*ecc = t4_read_reg64(adap, EDC_DATA(16));
#undef EDC_DATA
	return 0;
}
int t4_edc_read ( struct adapter * adap , int idx , u32 addr , __be32 * data , u64 * ecc ) { int i ; u32 edc_bist_cmd_reg , edc_bist_cmd_addr_reg , edc_bist_cmd_len_reg ; u32 edc_bist_cmd_data_pattern , edc_bist_status_rdata_reg ; if ( is_t4 ( adap ) ) { edc_bist_cmd_reg = EDC_REG ( A_EDC_BIST_CMD , idx ) ; edc_bist_cmd_addr_reg = EDC_REG ( A_EDC_BIST_CMD_ADDR , idx ) ; edc_bist_cmd_len_reg = EDC_REG ( A_EDC_BIST_CMD_LEN , idx ) ; edc_bist_cmd_data_pattern = EDC_REG ( A_EDC_BIST_DATA_PATTERN , idx ) ; edc_bist_status_rdata_reg = EDC_REG ( A_EDC_BIST_STATUS_RDATA , idx ) ; } else { #define EDC_STRIDE_T5  (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) #define EDC_REG_T5 ( reg , idx )  (reg + EDC_STRIDE_T5 * idx) edc_bist_cmd_reg = EDC_REG_T5 ( A_EDC_H_BIST_CMD , idx ) ; edc_bist_cmd_addr_reg = EDC_REG_T5 ( A_EDC_H_BIST_CMD_ADDR , idx ) ; edc_bist_cmd_len_reg = EDC_REG_T5 ( A_EDC_H_BIST_CMD_LEN , idx ) ; edc_bist_cmd_data_pattern = EDC_REG_T5 ( A_EDC_H_BIST_DATA_PATTERN , idx ) ; edc_bist_status_rdata_reg = EDC_REG_T5 ( A_EDC_H_BIST_STATUS_RDATA , idx ) ; #undef  EDC_REG_T5 #undef  EDC_STRIDE_T5 } if ( t4_read_reg ( adap , edc_bist_cmd_reg ) & F_START_BIST ) return - EBUSY ; t4_write_reg ( adap , edc_bist_cmd_addr_reg , addr & ~ 0x3fU ) ; t4_write_reg ( adap , edc_bist_cmd_len_reg , 64 ) ; t4_write_reg ( adap , edc_bist_cmd_data_pattern , 0xc ) ; t4_write_reg ( adap , edc_bist_cmd_reg , V_BIST_OPCODE ( 1 ) | V_BIST_CMD_GAP ( 1 ) | F_START_BIST ) ; i = t4_wait_op_done ( adap , edc_bist_cmd_reg , F_START_BIST , 0 , 10 , 1 ) ; if ( i ) return i ; #define EDC_DATA ( i )  EDC_BIST_STATUS_REG(edc_bist_status_rdata_reg, i) for ( i = 15 ; i >= 0 ; i -- ) * data ++ = ntohl ( t4_read_reg ( adap , EDC_DATA ( i ) ) ) ; if ( ecc ) * ecc = t4_read_reg64 ( adap , EDC_DATA ( 16 ) ) ; #undef  EDC_DATA return 0 ; }
t4_edc_read - read from EDC through backdoor accesses
      @adap: the adapter
      @idx: which EDC to access
      @addr: address of first byte requested
      @data: 64 bytes of data containing the requested address
      @ecc: where to store the corresponding 64-bit ECC word
t4_edc_read - read from EDC through backdoor accesses @adap : the adapter @idx : which EDC to access @addr : address of first byte requested @data : 64 bytes of data containing the requested address @ecc : where to store the corresponding 64 - bit ECC word
/*
 * These macro are missing in t4_regs.h file.
 * Added temporarily for testing.
 */