macsim/macsim-seq.c
// Simulate all cores and the periodical interconnect
Simulate all cores and the periodical interconnect
Simulate all cores and the periodical interconnect
void simulation()
{
    rank_t r;
    cycle_t min=CYCLE_T_MAX;
    cycle_t max=0;
    if (nodes[0]->core_type==CT_netrace)
    {
        uint_fast64_t timestamp = get_timestamp();
        while (netrace_inject_messages(nodes)) {
            rank_t r;
            for (r=0; r<conf_max_rank; r++)
                simulate_one_instruction(nodes[r]);
            noc_route_all(nodes, conf_max_rank);
#define LOG_PERIOD 20L
            if ((nodes[0]->cycle & ((1<<LOG_PERIOD)-1))==0) {
                uint_fast64_t now = get_timestamp();
                fprintf(stderr, "%lu cyc/s %lu Mcyc",
                    ((1<<LOG_PERIOD)*1000000000L) / (now-timestamp),
                    nodes[0]->cycle / 1000000L );
netrace_print_context(nodes[0]);
                timestamp = now;
            }
        }
        return;
    }
    for (r=0; r<conf_max_rank; r++)
    {
        if (CS_READY(nodes[r]->state)) {
            cycle_t c = nodes[r]->cycle;
            if (c<min) min=c;
            if (c>max) max=c;
        }
    }
    bool any_ready = 0;
    do {
        simulation_step();
        any_ready = 0;
        for (r=0; r<conf_max_rank; r++) {
            if (CS_READY(nodes[r]->state)) {
                if (nodes[r]->pc == nodes[r]->bp_addr) return;
                any_ready = 1;
            }
        }
    } while (any_ready);
}
void simulation ( ) { rank_t r ; cycle_t min = CYCLE_T_MAX ; cycle_t max = 0 ; if ( nodes [ 0 ] -> core_type == CT_netrace ) { uint_fast64_t timestamp = get_timestamp ( ) ; while ( netrace_inject_messages ( nodes ) ) { rank_t r ; for ( r = 0 ; r < conf_max_rank ; r ++ ) simulate_one_instruction ( nodes [ r ] ) ; noc_route_all ( nodes , conf_max_rank ) ; #define LOG_PERIOD  20L if ( ( nodes [ 0 ] -> cycle & ( ( 1 << LOG_PERIOD ) - 1 ) ) == 0 ) { uint_fast64_t now = get_timestamp ( ) ; fprintf ( stderr , " " , ( ( 1 << LOG_PERIOD ) * 1000000000L ) / ( now - timestamp ) , nodes [ 0 ] -> cycle / 1000000L ) ; netrace_print_context ( nodes [ 0 ] ) ; timestamp = now ; } } return ; } for ( r = 0 ; r < conf_max_rank ; r ++ ) { if ( CS_READY ( nodes [ r ] -> state ) ) { cycle_t c = nodes [ r ] -> cycle ; if ( c < min ) min = c ; if ( c > max ) max = c ; } } bool any_ready = 0 ; do { simulation_step ( ) ; any_ready = 0 ; for ( r = 0 ; r < conf_max_rank ; r ++ ) { if ( CS_READY ( nodes [ r ] -> state ) ) { if ( nodes [ r ] -> pc == nodes [ r ] -> bp_addr ) return ; any_ready = 1 ; } } } while ( any_ready ) ; }
Simulate all cores and the periodical interconnect
Simulate all cores and the periodical interconnect
// special case for fast netrace simulation // determine, which cores are still running // check for breakpoints