linux/drivers/gpu/drm/i915/intel_guc.c
/*
 * This function implements the MMIO based host to GuC interface.
 */
This function implements the MMIO based host to GuC interface.
This function implements the MMIO based host to GuC interface .
int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
			u32 *response_buf, u32 response_buf_size)
{
	struct drm_i915_private *dev_priv = guc_to_i915(guc);
	u32 status;
	int i;
	int ret;
	GEM_BUG_ON(!len);
	GEM_BUG_ON(len > guc->send_regs.count);
	GEM_BUG_ON(*action & ~INTEL_GUC_MSG_CODE_MASK);
	GEM_BUG_ON(HAS_GUC_CT(dev_priv) &&
		*action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER &&
		*action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
	mutex_lock(&guc->send_mutex);
	intel_uncore_forcewake_get(dev_priv, guc->send_regs.fw_domains);
	for (i = 0; i < len; i++)
		I915_WRITE(guc_send_reg(guc, i), action[i]);
	POSTING_READ(guc_send_reg(guc, i - 1));
	intel_guc_notify(guc);
	ret = __intel_wait_for_register_fw(dev_priv,
					   guc_send_reg(guc, 0),
					   INTEL_GUC_MSG_TYPE_MASK,
					   INTEL_GUC_MSG_TYPE_RESPONSE <<
					   INTEL_GUC_MSG_TYPE_SHIFT,
					   10, 10, &status);
	if (!ret && !INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(status))
		ret = -EIO;
	if (ret) {
		DRM_ERROR("MMIO: GuC action %#x failed with error %d %#x\n",
			  action[0], ret, status);
		goto out;
	}
	if (response_buf) {
		int count = min(response_buf_size, guc->send_regs.count - 1);
		for (i = 0; i < count; i++)
			response_buf[i] = I915_READ(guc_send_reg(guc, i + 1));
	}
	ret = INTEL_GUC_MSG_TO_DATA(status);
out:
	intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);
	mutex_unlock(&guc->send_mutex);
	return ret;
}
int intel_guc_send_mmio ( struct intel_guc * guc , const u32 * action , u32 len , u32 * response_buf , u32 response_buf_size ) { struct drm_i915_private * dev_priv = guc_to_i915 ( guc ) ; u32 status ; int i ; int ret ; GEM_BUG_ON ( ! len ) ; GEM_BUG_ON ( len > guc -> send_regs . count ) ; GEM_BUG_ON ( * action & ~ INTEL_GUC_MSG_CODE_MASK ) ; GEM_BUG_ON ( HAS_GUC_CT ( dev_priv ) && * action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER && * action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER ) ; mutex_lock ( & guc -> send_mutex ) ; intel_uncore_forcewake_get ( dev_priv , guc -> send_regs . fw_domains ) ; for ( i = 0 ; i < len ; i ++ ) I915_WRITE ( guc_send_reg ( guc , i ) , action [ i ] ) ; POSTING_READ ( guc_send_reg ( guc , i - 1 ) ) ; intel_guc_notify ( guc ) ; ret = __intel_wait_for_register_fw ( dev_priv , guc_send_reg ( guc , 0 ) , INTEL_GUC_MSG_TYPE_MASK , INTEL_GUC_MSG_TYPE_RESPONSE << INTEL_GUC_MSG_TYPE_SHIFT , 10 , 10 , & status ) ; if ( ! ret && ! INTEL_GUC_MSG_IS_RESPONSE_SUCCESS ( status ) ) ret = - EIO ; if ( ret ) { DRM_ERROR ( " \n " , action [ 0 ] , ret , status ) ; goto out ; } if ( response_buf ) { int count = min ( response_buf_size , guc -> send_regs . count - 1 ) ; for ( i = 0 ; i < count ; i ++ ) response_buf [ i ] = I915_READ ( guc_send_reg ( guc , i + 1 ) ) ; } ret = INTEL_GUC_MSG_TO_DATA ( status ) ; out : intel_uncore_forcewake_put ( dev_priv , guc -> send_regs . fw_domains ) ; mutex_unlock ( & guc -> send_mutex ) ; return ret ; }
This function implements the MMIO based host to GuC interface.
This function implements the MMIO based host to GuC interface .
/* We expect only action code */ /* If CT is available, we expect to use MMIO only during init/fini */ /*
	 * No GuC command should ever take longer than 10ms.
	 * Fast commands should still complete in 10us.
	 */ /* If GuC explicitly returned an error, convert it to -EIO */ /* Use data from the GuC response as our return value */