components/esp_eth/src/esp_eth_mac_dm9051.c
/**
 * @brief default setup for dm9051 internal registers
 */
@brief default setup for dm9051 internal registers
@brief default setup for dm9051 internal registers
static esp_err_t dm9051_setup_default(emac_dm9051_t *emac)
{
    esp_err_t ret = ESP_OK;
    ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_NCR, 0x00), err, TAG, "write NCR failed");
    ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_WCR, 0x00), err, TAG, "write WCR failed");
    ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_TCR, 0x00), err, TAG, "write TCR failed");
    ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_RCR, RCR_DIS_LONG | RCR_DIS_CRC), err, TAG, "write RCR failed");
    ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_TCR2, TCR2_RLCP), err, TAG, "write TCR2 failed");
    ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_ATCR, ATCR_AUTO_TX), err, TAG, "write ATCR failed");
    ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_TCSCR, TCSCR_IPCSE | TCSCR_TCPCSE | TCSCR_UDPCSE), err, TAG, "write TCSCR failed");
    ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_RCSCSR, 0x00), err, TAG, "write RCSCSR failed");
    ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_INTCR, 0x00), err, TAG, "write INTCR failed");
    ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_INTCKCR, 0x00), err, TAG, "write INTCKCR failed");
    ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_RLENCR, 0x00), err, TAG, "write RLENCR failed");
    ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_MEMSCR, 0x00), err, TAG, "write MEMSCR failed");
    ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_MPTRCR, MPTRCR_RST_RX | MPTRCR_RST_TX), err, TAG, "write MPTRCR failed");
    ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END), err, TAG, "write NSR failed");
    ESP_GOTO_ON_ERROR(dm9051_register_write(emac, DM9051_ISR, ISR_CLR_STATUS), err, TAG, "write ISR failed");
    return ESP_OK;
err:
    return ret;
}
static esp_err_t dm9051_setup_default ( emac_dm9051_t * emac ) { esp_err_t ret = ESP_OK ; ESP_GOTO_ON_ERROR ( dm9051_register_write ( emac , DM9051_NCR , 0x00 ) , err , TAG , " " ) ; ESP_GOTO_ON_ERROR ( dm9051_register_write ( emac , DM9051_WCR , 0x00 ) , err , TAG , " " ) ; ESP_GOTO_ON_ERROR ( dm9051_register_write ( emac , DM9051_TCR , 0x00 ) , err , TAG , " " ) ; ESP_GOTO_ON_ERROR ( dm9051_register_write ( emac , DM9051_RCR , RCR_DIS_LONG | RCR_DIS_CRC ) , err , TAG , " " ) ; ESP_GOTO_ON_ERROR ( dm9051_register_write ( emac , DM9051_TCR2 , TCR2_RLCP ) , err , TAG , " " ) ; ESP_GOTO_ON_ERROR ( dm9051_register_write ( emac , DM9051_ATCR , ATCR_AUTO_TX ) , err , TAG , " " ) ; ESP_GOTO_ON_ERROR ( dm9051_register_write ( emac , DM9051_TCSCR , TCSCR_IPCSE | TCSCR_TCPCSE | TCSCR_UDPCSE ) , err , TAG , " " ) ; ESP_GOTO_ON_ERROR ( dm9051_register_write ( emac , DM9051_RCSCSR , 0x00 ) , err , TAG , " " ) ; ESP_GOTO_ON_ERROR ( dm9051_register_write ( emac , DM9051_INTCR , 0x00 ) , err , TAG , " " ) ; ESP_GOTO_ON_ERROR ( dm9051_register_write ( emac , DM9051_INTCKCR , 0x00 ) , err , TAG , " " ) ; ESP_GOTO_ON_ERROR ( dm9051_register_write ( emac , DM9051_RLENCR , 0x00 ) , err , TAG , " " ) ; ESP_GOTO_ON_ERROR ( dm9051_register_write ( emac , DM9051_MEMSCR , 0x00 ) , err , TAG , " " ) ; ESP_GOTO_ON_ERROR ( dm9051_register_write ( emac , DM9051_MPTRCR , MPTRCR_RST_RX | MPTRCR_RST_TX ) , err , TAG , " " ) ; ESP_GOTO_ON_ERROR ( dm9051_register_write ( emac , DM9051_NSR , NSR_WAKEST | NSR_TX2END | NSR_TX1END ) , err , TAG , " " ) ; ESP_GOTO_ON_ERROR ( dm9051_register_write ( emac , DM9051_ISR , ISR_CLR_STATUS ) , err , TAG , " " ) ; return ESP_OK ; err : return ret ; }
@brief default setup for dm9051 internal registers
@brief default setup for dm9051 internal registers
/* disable wakeup */ /* stop transmitting, enable appending pad, crc for packets */ /* stop receiving, no promiscuous mode, no runt packet(size < 64bytes), not all multicast packets*/ /* discard long packet(size > 1522bytes) and crc error packet, enable watchdog */ /* retry late collision packet, at most two transmit command can be issued before transmit complete */ /* enable auto transmit */ /* generate checksum for UDP, TCP and IPv4 packets */ /* disable check sum for receive packets */ /* interrupt pin config: push-pull output, active high */ /* no length limitation for rx packets */ /* 3K-byte for TX and 13K-byte for RX */ /* reset tx and rx memory pointer */ /* clear network status: wakeup event, tx complete */ /* clear interrupt status */