Platform/ECM3532/DSP/hw/csp/ecm3532/src/eta_csp_spi.c
/***************************************************************************/
/**
 *
 * eta_csp_spi_initialize (LEGACY) This is the default SPI initialization
 * routine. 1MHz, CPOL=CPHA=0, msbit is transmitted first. No slave ready. All
 * CS are active low. If RX_FULL fills up, TX stalls. Includes a gratuitous soft
 * reset to make sure the IP is in good shape
 *
 * @return TODO
 *
 ******************************************************************************/
eta_csp_spi_initialize (LEGACY) This is the default SPI initialization
routine. 1MHz, CPOL=CPHA=0, msbit is transmitted first. No slave ready. All
CS are active low. If RX_FULL fills up, TX stalls. Includes a gratuitous soft
reset to make sure the IP is in good shape

@return TODO
eta_csp_spi_initialize ( LEGACY ) This is the default SPI initialization routine . 1MHz CPOL = CPHA = 0 msbit is transmitted first . No slave ready . All CS are active low . If RX_FULL fills up TX stalls . Includes a gratuitous soft reset to make sure the IP is in good shape @return TODO
int
eta_csp_spi_initialize()
{
    volatile int tempdata;
    REG_SPI2_CONFIG = (2 << BP_SPI2_CONFIG_FIFO_LEVEL_TRIG);
#ifdef ETA_CSP_PERIPH_MIN_CLK_FREQ
    REG_SPI2_CLKDIV = (1 << BP_SPI2_CLKDIV_CLKDIV) | (1 << BP_SPI2_CLKDIV_IBG);
#else
    REG_SPI2_CLKDIV = (7 << BP_SPI2_CLKDIV_CLKDIV) | (7 << BP_SPI2_CLKDIV_IBG);
#endif
    REG_SPI2_CONFIG2 = BM_SPI2_CONFIG2_SOFT_RST;
    tempdata = REG_SPI2_CONFIG2;
    REG_SPI2_CONFIG2 = BM_SPI2_CONFIG2_STALL_IF_RXFULL;
#ifdef ETA_CSP_PERIPH_MIN_CLK_FREQ
    REG_SPI2_CONFIG2 &= ~(BM_SPI2_CONFIG2_RX_SAMPLE_TIME);
    REG_SPI2_CONFIG2 |= (1 << BP_SPI2_CONFIG2_RX_SAMPLE_TIME) |
                        (1 << BP_SPI2_CONFIG2_DISABLE_MISO_METAFLOP);
#endif
    return(0);
}
int eta_csp_spi_initialize ( ) { volatile int tempdata ; REG_SPI2_CONFIG = ( 2 << BP_SPI2_CONFIG_FIFO_LEVEL_TRIG ) ; #ifdef ETA_CSP_PERIPH_MIN_CLK_FREQ REG_SPI2_CLKDIV = ( 1 << BP_SPI2_CLKDIV_CLKDIV ) | ( 1 << BP_SPI2_CLKDIV_IBG ) ; #else REG_SPI2_CLKDIV = ( 7 << BP_SPI2_CLKDIV_CLKDIV ) | ( 7 << BP_SPI2_CLKDIV_IBG ) ; #endif REG_SPI2_CONFIG2 = BM_SPI2_CONFIG2_SOFT_RST ; tempdata = REG_SPI2_CONFIG2 ; REG_SPI2_CONFIG2 = BM_SPI2_CONFIG2_STALL_IF_RXFULL ; #ifdef ETA_CSP_PERIPH_MIN_CLK_FREQ REG_SPI2_CONFIG2 &= ~ ( BM_SPI2_CONFIG2_RX_SAMPLE_TIME ) ; REG_SPI2_CONFIG2 |= ( 1 << BP_SPI2_CONFIG2_RX_SAMPLE_TIME ) | ( 1 << BP_SPI2_CONFIG2_DISABLE_MISO_METAFLOP ) ; #endif return ( 0 ) ; }
eta_csp_spi_initialize (LEGACY) This is the default SPI initialization
 routine.
eta_csp_spi_initialize ( LEGACY ) This is the default SPI initialization routine .
// Setup TX/RX FIFO level to be 2 // Set divide by and IBG the same // Set divide by and IBG the same // Perform soft reset of SM and set stall TX if RX FULL // Set divide by and IBG the same