kernels/linux-2.4.0/drivers/net/dmfe.c
/*
   A periodic timer routine
   Dynamic media sense, allocated Rx buffer...
 */
A periodic timer routine
Dynamic media sense, allocated Rx buffer
A periodic timer routine Dynamic media sense allocated Rx buffer
static void dmfe_timer(unsigned long data)
{
	u32 tmp_cr8;
	unsigned char tmp_cr12;
	struct net_device *dev = (struct net_device *) data;
	struct dmfe_board_info *db = (struct dmfe_board_info *) dev->priv;
	DMFE_DBUG(0, "dmfe_timer()", 0);
	if (db->in_reset_state)
		return;
	if ((db->dm910x_chk_mode & 0x1) && (db->stats.rx_packets > MAX_CHECK_PACKET)) {
		db->dm910x_chk_mode = 0x4;
	}
	tmp_cr8 = inl(db->ioaddr + DCR8);
	if ((db->interval_rx_cnt == 0) && (tmp_cr8)) {
		db->wait_reset = 1;
	}
	if (db->interval_rx_cnt > RX_MAX_TRAFFIC)
		db->cr7_data = 0x1a28d;
	else
		db->cr7_data = 0x1a2cd;
	outl(db->cr7_data, db->ioaddr + DCR7);
	db->interval_rx_cnt = 0;
	if (db->wait_reset | (db->tx_packet_cnt &&
			      ((jiffies - dev->trans_start) > DMFE_TX_TIMEOUT)) | (db->rx_error_cnt > 3)) {
		DMFE_DBUG(0, "Warn!! Warn!! Tx/Rx moniotr step1", db->tx_packet_cnt);
		dmfe_dynamic_reset(dev);
		db->timer.expires = DMFE_TIMER_WUT;
		add_timer(&db->timer);
		return;
	}
	db->rx_error_cnt = 0;	
	if (db->chip_id == PCI_DM9132_ID)
		tmp_cr12 = inb(db->ioaddr + DCR9 + 3);	
	else
		tmp_cr12 = inb(db->ioaddr + DCR12);	
	if (((db->chip_id == PCI_DM9102_ID) && (db->chip_revision == 0x02000030)) ||
	    ((db->chip_id == PCI_DM9132_ID) && (db->chip_revision == 0x02000010))) {
		if (tmp_cr12 & 2)
			tmp_cr12 = 0x0;		
		else
			tmp_cr12 = 0x3;		
	}
	if (!(tmp_cr12 & 0x3) && !db->link_failed) {
		DMFE_DBUG(0, "Link Failed", tmp_cr12);
		db->link_failed = 1;
		phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);	
		db->cr6_data |= 0x00040000;	
		db->cr6_data &= ~0x00000200;	
		update_cr6(db->cr6_data, db->ioaddr);
		db->phy_id2 = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
		if (db->phy_id2 == 0xb900)
			phy_write(db->ioaddr, db->phy_addr, 25, 0x7e08, db->chip_id);
	} else if ((tmp_cr12 & 0x3) && db->link_failed) {
		DMFE_DBUG(0, "Link link OK", tmp_cr12);
		db->link_failed = 0;
		db->cr6_data &= ~0x00040000;
		update_cr6(db->cr6_data, db->ioaddr);
		if (db->media_mode & DMFE_AUTO)
			dmfe_sense_speed(db);
		dmfe_process_mode(db);
		update_cr6(db->cr6_data, db->ioaddr);
	}
	if (db->rx_avail_cnt < RX_DESC_CNT)
		allocated_rx_buffer(db);
	db->timer.expires = DMFE_TIMER_WUT;
	add_timer(&db->timer);
}
static void dmfe_timer ( unsigned long data ) { u32 tmp_cr8 ; unsigned char tmp_cr12 ; struct net_device * dev = ( struct net_device * ) data ; struct dmfe_board_info * db = ( struct dmfe_board_info * ) dev -> priv ; DMFE_DBUG ( 0 , " " , 0 ) ; if ( db -> in_reset_state ) return ; if ( ( db -> dm910x_chk_mode & 0x1 ) && ( db -> stats . rx_packets > MAX_CHECK_PACKET ) ) { db -> dm910x_chk_mode = 0x4 ; } tmp_cr8 = inl ( db -> ioaddr + DCR8 ) ; if ( ( db -> interval_rx_cnt == 0 ) && ( tmp_cr8 ) ) { db -> wait_reset = 1 ; } if ( db -> interval_rx_cnt > RX_MAX_TRAFFIC ) db -> cr7_data = 0x1a28d ; else db -> cr7_data = 0x1a2cd ; outl ( db -> cr7_data , db -> ioaddr + DCR7 ) ; db -> interval_rx_cnt = 0 ; if ( db -> wait_reset | ( db -> tx_packet_cnt && ( ( jiffies - dev -> trans_start ) > DMFE_TX_TIMEOUT ) ) | ( db -> rx_error_cnt > 3 ) ) { DMFE_DBUG ( 0 , " " , db -> tx_packet_cnt ) ; dmfe_dynamic_reset ( dev ) ; db -> timer . expires = DMFE_TIMER_WUT ; add_timer ( & db -> timer ) ; return ; } db -> rx_error_cnt = 0 ; if ( db -> chip_id == PCI_DM9132_ID ) tmp_cr12 = inb ( db -> ioaddr + DCR9 + 3 ) ; else tmp_cr12 = inb ( db -> ioaddr + DCR12 ) ; if ( ( ( db -> chip_id == PCI_DM9102_ID ) && ( db -> chip_revision == 0x02000030 ) ) || ( ( db -> chip_id == PCI_DM9132_ID ) && ( db -> chip_revision == 0x02000010 ) ) ) { if ( tmp_cr12 & 2 ) tmp_cr12 = 0x0 ; else tmp_cr12 = 0x3 ; } if ( ! ( tmp_cr12 & 0x3 ) && ! db -> link_failed ) { DMFE_DBUG ( 0 , " " , tmp_cr12 ) ; db -> link_failed = 1 ; phy_write ( db -> ioaddr , db -> phy_addr , 0 , 0x8000 , db -> chip_id ) ; db -> cr6_data |= 0x00040000 ; db -> cr6_data &= ~ 0x00000200 ; update_cr6 ( db -> cr6_data , db -> ioaddr ) ; db -> phy_id2 = phy_read ( db -> ioaddr , db -> phy_addr , 3 , db -> chip_id ) ; if ( db -> phy_id2 == 0xb900 ) phy_write ( db -> ioaddr , db -> phy_addr , 25 , 0x7e08 , db -> chip_id ) ; } else if ( ( tmp_cr12 & 0x3 ) && db -> link_failed ) { DMFE_DBUG ( 0 , " " , tmp_cr12 ) ; db -> link_failed = 0 ; db -> cr6_data &= ~ 0x00040000 ; update_cr6 ( db -> cr6_data , db -> ioaddr ) ; if ( db -> media_mode & DMFE_AUTO ) dmfe_sense_speed ( db ) ; dmfe_process_mode ( db ) ; update_cr6 ( db -> cr6_data , db -> ioaddr ) ; } if ( db -> rx_avail_cnt < RX_DESC_CNT ) allocated_rx_buffer ( db ) ; db -> timer . expires = DMFE_TIMER_WUT ; add_timer ( & db -> timer ) ; }
A periodic timer routine
Dynamic media sense, allocated Rx buffer...
A periodic timer routine Dynamic media sense allocated Rx buffer ...
/* Do reset now */ /* Operating Mode Check */ /* Dynamic reset DM910X : system error or transmit time-out */ /* printk("CR8 %x, Interval Rx %x\n", tmp_cr8, db->interval_rx_cnt); */ /* Receiving Traffic check */ /*
		   printk("wait_reset %x, tx cnt %x, rx err %x, time %x\n", db->wait_reset, db->tx_packet_cnt, db->rx_error_cnt, jiffies-dev->trans_start);
		 */ /* Clear previos counter */ /* Link status check, Dynamic media type change */ /* DM9132 */ /* DM9102/DM9102A */ /* DM9102A Chip */ /* Link failed */ /* Link OK */ /* Link Failed */ /* reset Phy */ /* 10/100M link failed, used 1M Home-Net */ /* CR6 bit18 = 1, select Home-Net */ /* CR6 bit9 =0, half duplex mode */ /* For DM9801 : PHY ID1 0181h, PHY ID2 B900h */ /* CR6 bit18=0, select 10/100M */ /* Auto Sense Speed */ /* SHOW_MEDIA_TYPE(db->op_mode); */ /* reallocated rx descriptor buffer */ /* Timer active again */