plat/nvidia/tegra/common/tegra_fiq_glue.c
/*******************************************************************************
 * Handler to return the NS EL1/EL0 CPU context
 ******************************************************************************/
Handler to return the NS EL1/EL0 CPU context
Handler to return the NS EL1 / EL0 CPU context
int32_t tegra_fiq_get_intr_context(void)
{
	cpu_context_t *ctx = cm_get_context(NON_SECURE);
	gp_regs_t *gpregs_ctx = get_gpregs_ctx(ctx);
	const el1_sys_regs_t *el1state_ctx = get_sysregs_ctx(ctx);
	uint32_t cpu = plat_my_core_pos();
	uint64_t val;
	write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X0), (fiq_state[cpu].elr_el3));
	write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X1), (fiq_state[cpu].spsr_el3));
	val = read_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_SP_EL0));
	write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X2), (val));
	val = read_ctx_reg((el1state_ctx), (uint32_t)(CTX_SP_EL1));
	write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X3), (val));
	return 0;
}
int32_t tegra_fiq_get_intr_context ( void ) { cpu_context_t * ctx = cm_get_context ( NON_SECURE ) ; gp_regs_t * gpregs_ctx = get_gpregs_ctx ( ctx ) ; const el1_sys_regs_t * el1state_ctx = get_sysregs_ctx ( ctx ) ; uint32_t cpu = plat_my_core_pos ( ) ; uint64_t val ; write_ctx_reg ( ( gpregs_ctx ) , ( uint32_t ) ( CTX_GPREG_X0 ) , ( fiq_state [ cpu ] . elr_el3 ) ) ; write_ctx_reg ( ( gpregs_ctx ) , ( uint32_t ) ( CTX_GPREG_X1 ) , ( fiq_state [ cpu ] . spsr_el3 ) ) ; val = read_ctx_reg ( ( gpregs_ctx ) , ( uint32_t ) ( CTX_GPREG_SP_EL0 ) ) ; write_ctx_reg ( ( gpregs_ctx ) , ( uint32_t ) ( CTX_GPREG_X2 ) , ( val ) ) ; val = read_ctx_reg ( ( el1state_ctx ) , ( uint32_t ) ( CTX_SP_EL1 ) ) ; write_ctx_reg ( ( gpregs_ctx ) , ( uint32_t ) ( CTX_GPREG_X3 ) , ( val ) ) ; return 0 ; }
Handler to return the NS EL1/EL0 CPU context
Handler to return the NS EL1 / EL0 CPU context
/*
	 * We store the ELR_EL3, SPSR_EL3, SP_EL0 and SP_EL1 registers so
	 * that el3_exit() sends these values back to the NS world.
	 */