src/occ_gpe0/apss_init.c
// ----------------------------------------------------
// Toggle the output of the APSS RESET pin
// ----------------------------------------------------
Toggle the output of the APSS RESET pin
Toggle the output of the APSS RESET pin
void apss_toggle_hw_reset(ipc_msg_t* cmd, void* arg)
{
    static int g_apss_reset_state = ~(0);
    int rc = 0;
    uint32_t apss_reset_address;
    ipc_async_cmd_t     *async_cmd = (ipc_async_cmd_t*)cmd;
    initGpioArgs_t      *args = (initGpioArgs_t*)async_cmd->cmd_data;
    if(g_apss_reset_state) 
    {
        apss_reset_address = PU_GPIO_OUTPUT_CLR;
    }
    else
    {
        apss_reset_address = PU_GPIO_OUTPUT_OR;
    }
    g_apss_reset_state = ~g_apss_reset_state;
    PK_TRACE("apss_toggle_apss_hw_reset: %d",(uint16_t)g_apss_reset_state);
    rc = putscom_abs(apss_reset_address, APSS_RESET_GPIO);
    if(rc)
    {
        PK_TRACE("apss_toggle_hw_reset: APSS_RESET_GPIO_OUTPUT toggle failed. rc:0x%08x",rc);
        gpe_set_ffdc(&(args->error), 0, GPE_RC_SCOM_PUT_FAILED, rc);
    }
    rc = ipc_send_rsp(cmd, IPC_RC_SUCCESS);
    if(rc)
    {
        PK_TRACE("apss_toggle_hw_reset: Failed to send response back. rc = 0x%08x. Halting GPE0",
                 rc);
        gpe_set_ffdc(&(args->error), 0x00, rc, 0);
        pk_halt();
    }
}
void apss_toggle_hw_reset ( ipc_msg_t * cmd , void * arg ) { static int g_apss_reset_state = ~ ( 0 ) ; int rc = 0 ; uint32_t apss_reset_address ; ipc_async_cmd_t * async_cmd = ( ipc_async_cmd_t * ) cmd ; initGpioArgs_t * args = ( initGpioArgs_t * ) async_cmd -> cmd_data ; if ( g_apss_reset_state ) { apss_reset_address = PU_GPIO_OUTPUT_CLR ; } else { apss_reset_address = PU_GPIO_OUTPUT_OR ; } g_apss_reset_state = ~ g_apss_reset_state ; PK_TRACE ( " " , ( uint16_t ) g_apss_reset_state ) ; rc = putscom_abs ( apss_reset_address , APSS_RESET_GPIO ) ; if ( rc ) { PK_TRACE ( " " , rc ) ; gpe_set_ffdc ( & ( args -> error ) , 0 , GPE_RC_SCOM_PUT_FAILED , rc ) ; } rc = ipc_send_rsp ( cmd , IPC_RC_SUCCESS ) ; if ( rc ) { PK_TRACE ( " " , rc ) ; gpe_set_ffdc ( & ( args -> error ) , 0x00 , rc , 0 ) ; pk_halt ( ) ; } }
Toggle the output of the APSS RESET pin
Toggle the output of the APSS RESET pin
// not in reset // Set/clear GPIO2 output // send back a successful response.  OCC will check rc and ffdc