plat/nvidia/tegra/common/tegra_gic.c
/*******************************************************************************
 * Global gic distributor setup which will be done by the primary cpu after a
 * cold boot. It marks out the non secure SPIs, PPIs & SGIs and enables them.
 * It then enables the secure GIC distributor interface.
 ******************************************************************************/
Global gic distributor setup which will be done by the primary cpu after a
cold boot. It marks out the non secure SPIs, PPIs & SGIs and enables them.
It then enables the secure GIC distributor interface.
Global gic distributor setup which will be done by the primary cpu after a cold boot . It marks out the non secure SPIs PPIs & SGIs and enables them . It then enables the secure GIC distributor interface .
static void tegra_gic_distif_setup(uint32_t gicd_base)
{
	uint32_t index, num_ints, irq_num;
	uint8_t target_cpus;
	uint32_t val;
	num_ints = gicd_read_typer(gicd_base) & IT_LINES_NO_MASK;
	num_ints = (num_ints + 1U) << 5;
	for (index = MIN_SPI_ID; index < num_ints; index += 32U) {
		gicd_write_igroupr(gicd_base, index, 0xFFFFFFFFU);
	}
	for (index = MIN_SPI_ID; index < num_ints; index += 4U) {
		gicd_write_ipriorityr(gicd_base, index,
				GICD_IPRIORITYR_DEF_VAL);
	}
	if (g_irq_sec_ptr != NULL) {
		for (index = 0U; index < g_num_irqs; index++) {
			irq_num = g_irq_sec_ptr[index].irq;
			target_cpus = (uint8_t)g_irq_sec_ptr[index].target_cpus;
			if (irq_num >= MIN_SPI_ID) {
				gicd_clr_igroupr(gicd_base, irq_num);
				mmio_write_8((uint64_t)gicd_base +
					(uint64_t)GICD_IPRIORITYR +
					(uint64_t)irq_num,
					GIC_HIGHEST_SEC_PRIORITY &
					GIC_PRI_MASK);
				val = gicd_read_icfgr(gicd_base, irq_num);
				val |= (3U << ((irq_num & 0xFU) << 1U));
				gicd_write_icfgr(gicd_base, irq_num, val);
				gicd_set_itargetsr(gicd_base, irq_num,
					target_cpus);
				gicd_set_isenabler(gicd_base, irq_num);
			}
		}
	}
	tegra_gic_pcpu_distif_setup(gicd_base);
	gicd_write_ctlr(gicd_base, ENABLE_GRP0 | ENABLE_GRP1);
}
static void tegra_gic_distif_setup ( uint32_t gicd_base ) { uint32_t index , num_ints , irq_num ; uint8_t target_cpus ; uint32_t val ; num_ints = gicd_read_typer ( gicd_base ) & IT_LINES_NO_MASK ; num_ints = ( num_ints + 1U ) << 5 ; for ( index = MIN_SPI_ID ; index < num_ints ; index += 32U ) { gicd_write_igroupr ( gicd_base , index , 0xFFFFFFFFU ) ; } for ( index = MIN_SPI_ID ; index < num_ints ; index += 4U ) { gicd_write_ipriorityr ( gicd_base , index , GICD_IPRIORITYR_DEF_VAL ) ; } if ( g_irq_sec_ptr != NULL ) { for ( index = 0U ; index < g_num_irqs ; index ++ ) { irq_num = g_irq_sec_ptr [ index ] . irq ; target_cpus = ( uint8_t ) g_irq_sec_ptr [ index ] . target_cpus ; if ( irq_num >= MIN_SPI_ID ) { gicd_clr_igroupr ( gicd_base , irq_num ) ; mmio_write_8 ( ( uint64_t ) gicd_base + ( uint64_t ) GICD_IPRIORITYR + ( uint64_t ) irq_num , GIC_HIGHEST_SEC_PRIORITY & GIC_PRI_MASK ) ; val = gicd_read_icfgr ( gicd_base , irq_num ) ; val |= ( 3U << ( ( irq_num & 0xFU ) << 1U ) ) ; gicd_write_icfgr ( gicd_base , irq_num , val ) ; gicd_set_itargetsr ( gicd_base , irq_num , target_cpus ) ; gicd_set_isenabler ( gicd_base , irq_num ) ; } } } tegra_gic_pcpu_distif_setup ( gicd_base ) ; gicd_write_ctlr ( gicd_base , ENABLE_GRP0 | ENABLE_GRP1 ) ; }
Global gic distributor setup which will be done by the primary cpu after a
 cold boot.
Global gic distributor setup which will be done by the primary cpu after a cold boot .
/*
	 * Mark out non-secure interrupts. Calculate number of
	 * IGROUPR registers to consider. Will be equal to the
	 * number of IT_LINES
	 */ /* Setup SPI priorities doing four at a time */ /* Configure SPI secure interrupts now */ /* Configure as a secure interrupt */ /* Configure SPI priority */ /* Configure as level triggered */ /* Route SPI to the target CPUs */ /* Enable this interrupt */ /*
	 * Configure the SGI and PPI. This is done in a separated function
	 * because each CPU is responsible for initializing its own private
	 * interrupts.
	 */ /* enable distributor */