KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c
/**
  * @brief  Resets the RCC clock configuration to the default reset state.
  * @note   The default reset state of the clock configuration is given below:
  *            - HSI ON and used as system clock source
  *            - HSE, PLL1, PLL2 and PLL3 OFF
  *            - AHB, APB Bus pre-scaler set to 1.
  *            - CSS, MCO1 and MCO2 OFF
  *            - All interrupts disabled
  * @note   This function doesn't modify the configuration of the
  *            - Peripheral clocks  
  *            - LSI, LSE and RTC clocks 
  * @retval None
  */
@brief  Resets the RCC clock configuration to the default reset state.
@note   The default reset state of the clock configuration is given below:
- HSI ON and used as system clock source
- HSE, PLL1, PLL2 and PLL3 OFF
- AHB, APB Bus pre-scaler set to 1.
- CSS, MCO1 and MCO2 OFF
- All interrupts disabled
@note   This function doesn't modify the configuration of the
- Peripheral clocks
- LSI, LSE and RTC clocks
@retval None
@brief Resets the RCC clock configuration to the default reset state . @note The default reset state of the clock configuration is given below : - HSI ON and used as system clock source - HSE PLL1 PLL2 and PLL3 OFF - AHB APB Bus pre - scaler set to 1 . - CSS MCO1 and MCO2 OFF - All interrupts disabled @note This function doesn ' t modify the configuration of the - Peripheral clocks - LSI LSE and RTC clocks @retval None
void HAL_RCC_DeInit(void)
{
  SET_BIT(RCC->CR, RCC_CR_HSION);
  CLEAR_REG(RCC->CFGR);
  CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSIKERON| RCC_CR_HSIDIV| RCC_CR_HSIDIVF| RCC_CR_CSION | RCC_CR_CSIKERON |  RCC_CR_HSI48ON  \
  |RCC_CR_CSSHSEON | RCC_CR_PLL1ON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
  CLEAR_REG(RCC->D1CFGR);
  CLEAR_REG(RCC->D2CFGR);
  CLEAR_REG(RCC->D3CFGR);
  CLEAR_REG(RCC->PLLCKSELR);
  CLEAR_REG(RCC->PLLCFGR);
  CLEAR_REG(RCC->PLL1DIVR);
  CLEAR_REG(RCC->PLL1FRACR);
  CLEAR_REG(RCC->PLL2DIVR);
  CLEAR_REG(RCC->PLL2FRACR);
  CLEAR_REG(RCC->PLL3DIVR);
  CLEAR_REG(RCC->PLL3FRACR);
  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
  CLEAR_REG(RCC->CICR);
}
void HAL_RCC_DeInit ( void ) { SET_BIT ( RCC -> CR , RCC_CR_HSION ) ; CLEAR_REG ( RCC -> CFGR ) ; CLEAR_BIT ( RCC -> CR , RCC_CR_HSEON | RCC_CR_HSIKERON | RCC_CR_HSIDIV | RCC_CR_HSIDIVF | RCC_CR_CSION | RCC_CR_CSIKERON | RCC_CR_HSI48ON | RCC_CR_CSSHSEON | RCC_CR_PLL1ON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON ) ; CLEAR_REG ( RCC -> D1CFGR ) ; CLEAR_REG ( RCC -> D2CFGR ) ; CLEAR_REG ( RCC -> D3CFGR ) ; CLEAR_REG ( RCC -> PLLCKSELR ) ; CLEAR_REG ( RCC -> PLLCFGR ) ; CLEAR_REG ( RCC -> PLL1DIVR ) ; CLEAR_REG ( RCC -> PLL1FRACR ) ; CLEAR_REG ( RCC -> PLL2DIVR ) ; CLEAR_REG ( RCC -> PLL2FRACR ) ; CLEAR_REG ( RCC -> PLL3DIVR ) ; CLEAR_REG ( RCC -> PLL3FRACR ) ; CLEAR_BIT ( RCC -> CR , RCC_CR_HSEBYP ) ; CLEAR_REG ( RCC -> CICR ) ; }
@brief  Resets the RCC clock configuration to the default reset state.
@brief Resets the RCC clock configuration to the default reset state .
/* Set HSION bit */ /* Reset CFGR register */ /* Reset CSION , CSIKERON, HSEON, HSI48ON, HSECSSON,HSIDIV, PLL1ON, PLL2ON, PLL3ON bits */ /* Reset D1CFGR register */ /* Reset D2CFGR register */ /* Reset D3CFGR register */ /* Reset PLLCKSELR register */ /* Reset PLLCFGR register */ /* Reset PLL1DIVR register */ /* Reset PLL1FRACR register */ /* Reset PLL2DIVR register */ /* Reset PLL2FRACR register */ /* Reset PLL3DIVR register */ /* Reset PLL3FRACR register */ /* Reset HSEBYP bit */ /* Disable all interrupts */