KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c
/**
  * @brief  Enter a Domain to DSTOP mode.
  * @note   In DStop mode the domain bus matrix clock is stopped.
  * @note   The system D3 domain enters Stop mode only when the CPU subsystem is in CStop mode,
  *         the EXTI wakeup sources are inactive and at least one PDDS_Dn bit in PWR CPU
  *         control register (PWR_CPUCR) for any domain request Stop.
  * @note   In system D3 domain Stop mode, D1 domain and D2 domain are either in DStop and/or
  *         DStandby mode.
  * @note   Before entering DSTOP mode it is recommended to call SCB_CleanDCache function
  *         in order to clean the D-Cache and guarantee the data integrity for the SRAM memories.
  * @note   In System Stop mode, the domain peripherals that use the LSI or LSE clock, and the
  *         peripherals that have a kernel clock request to select HSI or CSI as source,
  *         are still able to operate.
  * @param  Regulator: Specifies the regulator state in Stop mode.
  *          This parameter can be one of the following values:
  *            @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
  *            @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
  * @param  STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
  *          This parameter can be one of the following values:
  *            @arg PWR_STOPENTRY_WFI: Enter DStop mode with WFI instruction
  *            @arg PWR_STOPENTRY_WFE: Enter DStop mode with WFE instruction
  * @param  Domain: Specifies the Domain to enter STOP mode.
  *          This parameter can be one of the following values:
  *            @arg PWR_D1_DOMAIN: Enter D1 Domain to DSTOP mode.
  *            @arg PWR_D2_DOMAIN: Enter D2 Domain to DSTOP mode.
  *            @arg PWR_D3_DOMAIN: Enter D3 Domain to DSTOP mode.
  * @retval None
  */
@brief  Enter a Domain to DSTOP mode.
@note   In DStop mode the domain bus matrix clock is stopped.
@note   The system D3 domain enters Stop mode only when the CPU subsystem is in CStop mode,
the EXTI wakeup sources are inactive and at least one PDDS_Dn bit in PWR CPU
control register (PWR_CPUCR) for any domain request Stop.
@note   In system D3 domain Stop mode, D1 domain and D2 domain are either in DStop and/or
DStandby mode.
@note   Before entering DSTOP mode it is recommended to call SCB_CleanDCache function
in order to clean the D-Cache and guarantee the data integrity for the SRAM memories.
@note   In System Stop mode, the domain peripherals that use the LSI or LSE clock, and the
peripherals that have a kernel clock request to select HSI or CSI as source,
are still able to operate.
@param  Regulator: Specifies the regulator state in Stop mode.
This parameter can be one of the following values:
@arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
@arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
@param  STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
This parameter can be one of the following values:
@arg PWR_STOPENTRY_WFI: Enter DStop mode with WFI instruction
@arg PWR_STOPENTRY_WFE: Enter DStop mode with WFE instruction
@param  Domain: Specifies the Domain to enter STOP mode.
This parameter can be one of the following values:
@arg PWR_D1_DOMAIN: Enter D1 Domain to DSTOP mode.
@arg PWR_D2_DOMAIN: Enter D2 Domain to DSTOP mode.
@arg PWR_D3_DOMAIN: Enter D3 Domain to DSTOP mode.
@retval None
@brief Enter a Domain to DSTOP mode . @note In DStop mode the domain bus matrix clock is stopped . @note The system D3 domain enters Stop mode only when the CPU subsystem is in CStop mode the EXTI wakeup sources are inactive and at least one PDDS_Dn bit in PWR CPU control register ( PWR_CPUCR ) for any domain request Stop . @note In system D3 domain Stop mode D1 domain and D2 domain are either in DStop and / or DStandby mode . @note Before entering DSTOP mode it is recommended to call SCB_CleanDCache function in order to clean the D - Cache and guarantee the data integrity for the SRAM memories . @note In System Stop mode the domain peripherals that use the LSI or LSE clock and the peripherals that have a kernel clock request to select HSI or CSI as source are still able to operate . @param Regulator : Specifies the regulator state in Stop mode . This parameter can be one of the following values : @arg PWR_MAINREGULATOR_ON : Stop mode with regulator ON @arg PWR_LOWPOWERREGULATOR_ON : Stop mode with low power regulator ON @param STOPEntry : Specifies if Stop mode in entered with WFI or WFE instruction . This parameter can be one of the following values : @arg PWR_STOPENTRY_WFI : Enter DStop mode with WFI instruction @arg PWR_STOPENTRY_WFE : Enter DStop mode with WFE instruction @param Domain : Specifies the Domain to enter STOP mode . This parameter can be one of the following values : @arg PWR_D1_DOMAIN : Enter D1 Domain to DSTOP mode . @arg PWR_D2_DOMAIN : Enter D2 Domain to DSTOP mode . @arg PWR_D3_DOMAIN : Enter D3 Domain to DSTOP mode . @retval None
void HAL_PWREx_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain)
{
  assert_param(IS_PWR_REGULATOR(Regulator));
  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
  assert_param(IS_PWR_DOMAIN(Domain));
  MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, Regulator);
  if (Domain == PWR_D1_DOMAIN)
  {
    CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1);
    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
    __DSB();
    __ISB();
    if(STOPEntry == PWR_STOPENTRY_WFI)
    {
      __WFI();
    }
    else
    {
      __SEV();
      __WFE();
      __WFE();
    }
    SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
  }
  else if (Domain == PWR_D2_DOMAIN)
  {
    CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2);
  }
  else
  {
    CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3);
  }
}
void HAL_PWREx_EnterSTOPMode ( uint32_t Regulator , uint8_t STOPEntry , uint32_t Domain ) { assert_param ( IS_PWR_REGULATOR ( Regulator ) ) ; assert_param ( IS_PWR_STOP_ENTRY ( STOPEntry ) ) ; assert_param ( IS_PWR_DOMAIN ( Domain ) ) ; MODIFY_REG ( PWR -> CR1 , PWR_CR1_LPDS , Regulator ) ; if ( Domain == PWR_D1_DOMAIN ) { CLEAR_BIT ( PWR -> CPUCR , PWR_CPUCR_PDDS_D1 ) ; SCB -> SCR |= SCB_SCR_SLEEPDEEP_Msk ; __DSB ( ) ; __ISB ( ) ; if ( STOPEntry == PWR_STOPENTRY_WFI ) { __WFI ( ) ; } else { __SEV ( ) ; __WFE ( ) ; __WFE ( ) ; } SCB -> SCR &= ( uint32_t ) ~ ( ( uint32_t ) SCB_SCR_SLEEPDEEP_Msk ) ; } else if ( Domain == PWR_D2_DOMAIN ) { CLEAR_BIT ( PWR -> CPUCR , PWR_CPUCR_PDDS_D2 ) ; } else { CLEAR_BIT ( PWR -> CPUCR , PWR_CPUCR_PDDS_D3 ) ; } }
@brief  Enter a Domain to DSTOP mode.
@brief Enter a Domain to DSTOP mode .
/* Check the parameters */ /* Select the regulator state in Stop mode */ /* Select the domain Power Down DeepSleep */ /* Keep DSTOP mode when D1 domain enters Deepsleep */ /* Set SLEEPDEEP bit of Cortex System Control Register */ /* Ensure that all instructions done before entering STOP mode */ /* Select Stop mode entry */ /* Request Wait For Interrupt */ /* Request Wait For Event */ /* Reset SLEEPDEEP bit of Cortex System Control Register */ /* Keep DSTOP mode when D2 domain enters Deepsleep */ /* Keep DSTOP mode when D3 domain enters Deepsleep */