FreeBSD/sys/x86/x86/mca.c
/*
 * Initializes per-CPU machine check registers and enables corrected
 * machine check interrupts.
 */
Initializes per-CPU machine check registers and enables corrected
machine check interrupts.
Initializes per - CPU machine check registers and enables corrected machine check interrupts .
static void
_mca_init(int boot)
{
	uint64_t mcg_cap;
	uint64_t ctl, mask;
	int i, skip;
	if (!mca_enabled || !(cpu_feature & CPUID_MCE))
		return;
	if (cpu_feature & CPUID_MCA) {
		if (boot)
			PCPU_SET(cmci_mask, 0);
		mcg_cap = rdmsr(MSR_MCG_CAP);
		if (mcg_cap & MCG_CAP_CTL_P)
			wrmsr(MSR_MCG_CTL, MCG_CTL_ENABLE);
		if (PCPU_GET(cpuid) == 0 && boot)
			mca_setup(mcg_cap);
		if (cpu_vendor_id == CPU_VENDOR_AMD &&
		    CPUID_TO_FAMILY(cpu_id) == 0x10 && !amd10h_L1TP) {
			mask = rdmsr(MSR_MC0_CTL_MASK);
			if ((mask & (1UL << 5)) == 0)
				wrmsr(MSR_MC0_CTL_MASK, mask | (1UL << 5));
		}
		for (i = 0; i < (mcg_cap & MCG_CAP_COUNT); i++) {
			ctl = 0xffffffffffffffffUL;
			skip = 0;
			if (cpu_vendor_id == CPU_VENDOR_INTEL) {
				if (i == 0 && CPUID_TO_FAMILY(cpu_id) == 0x6
				    && CPUID_TO_MODEL(cpu_id) < 0x1a)
					skip = 1;
			} else if (cpu_vendor_id == CPU_VENDOR_AMD) {
				if (i == 4 && CPUID_TO_FAMILY(cpu_id) >= 0xf)
					ctl &= ~(1UL << 10);
			}
			if (!skip)
				wrmsr(MSR_MC_CTL(i), ctl);
#ifdef DEV_APIC
			if (mcg_cap & MCG_CAP_CMCI_P) {
				if (boot)
					cmci_monitor(i);
				else
					cmci_resume(i);
			}
#endif
			wrmsr(MSR_MC_STATUS(i), 0);
		}
#ifdef DEV_APIC
		if (PCPU_GET(cmci_mask) != 0 && boot)
			lapic_enable_cmc();
#endif
	}
	load_cr4(rcr4() | CR4_MCE);
}
static void _mca_init ( int boot ) { uint64_t mcg_cap ; uint64_t ctl , mask ; int i , skip ; if ( ! mca_enabled || ! ( cpu_feature & CPUID_MCE ) ) return ; if ( cpu_feature & CPUID_MCA ) { if ( boot ) PCPU_SET ( cmci_mask , 0 ) ; mcg_cap = rdmsr ( MSR_MCG_CAP ) ; if ( mcg_cap & MCG_CAP_CTL_P ) wrmsr ( MSR_MCG_CTL , MCG_CTL_ENABLE ) ; if ( PCPU_GET ( cpuid ) == 0 && boot ) mca_setup ( mcg_cap ) ; if ( cpu_vendor_id == CPU_VENDOR_AMD && CPUID_TO_FAMILY ( cpu_id ) == 0x10 && ! amd10h_L1TP ) { mask = rdmsr ( MSR_MC0_CTL_MASK ) ; if ( ( mask & ( 1UL << 5 ) ) == 0 ) wrmsr ( MSR_MC0_CTL_MASK , mask | ( 1UL << 5 ) ) ; } for ( i = 0 ; i < ( mcg_cap & MCG_CAP_COUNT ) ; i ++ ) { ctl = 0xffffffffffffffffUL ; skip = 0 ; if ( cpu_vendor_id == CPU_VENDOR_INTEL ) { if ( i == 0 && CPUID_TO_FAMILY ( cpu_id ) == 0x6 && CPUID_TO_MODEL ( cpu_id ) < 0x1a ) skip = 1 ; } else if ( cpu_vendor_id == CPU_VENDOR_AMD ) { if ( i == 4 && CPUID_TO_FAMILY ( cpu_id ) >= 0xf ) ctl &= ~ ( 1UL << 10 ) ; } if ( ! skip ) wrmsr ( MSR_MC_CTL ( i ) , ctl ) ; #ifdef DEV_APIC if ( mcg_cap & MCG_CAP_CMCI_P ) { if ( boot ) cmci_monitor ( i ) ; else cmci_resume ( i ) ; } #endif wrmsr ( MSR_MC_STATUS ( i ) , 0 ) ; } #ifdef DEV_APIC if ( PCPU_GET ( cmci_mask ) != 0 && boot ) lapic_enable_cmc ( ) ; #endif } load_cr4 ( rcr4 ( ) | CR4_MCE ) ; }
Initializes per-CPU machine check registers and enables corrected
 machine check interrupts.
Initializes per - CPU machine check registers and enables corrected machine check interrupts .
/* MCE is required. */ /* Enable MCA features. */ /*
		 * Disable logging of level one TLB parity (L1TP) errors by
		 * the data cache as an alternative workaround for AMD Family
		 * 10h Erratum 383.  Unlike the recommended workaround, there
		 * is no performance penalty to this workaround.  However,
		 * L1TP errors will go unreported.
		 */ /* By default enable logging of all errors. */ /*
				 * For P6 models before Nehalem MC0_CTL is
				 * always enabled and reserved.
				 */ /* BKDG for Family 10h: unset GartTblWkEn. */ /* Clear all errors. */