qemu/target/hppa/translate.c
/* The "normal" usage is SP >= 0, wherein SP == 0 selects the space
   from the top 2 bits of the base register.  There are a few system
   instructions that have a 3-bit space specifier, for which SR0 is
   not special.  To handle this, pass ~SP.  */
The "normal" usage is SP >= 0, wherein SP == 0 selects the space
from the top 2 bits of the base register.  There are a few system
instructions that have a 3-bit space specifier, for which SR0 is
not special.  To handle this, pass ~SP.
The " normal " usage is SP > = 0 wherein SP == 0 selects the space from the top 2 bits of the base register . There are a few system instructions that have a 3 - bit space specifier for which SR0 is not special . To handle this pass ~SP .
static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base)
{
    TCGv_ptr ptr;
    TCGv_reg tmp;
    TCGv_i64 spc;
    if (sp != 0) {
        if (sp < 0) {
            sp = ~sp;
        }
        spc = get_temp_tl(ctx);
        load_spr(ctx, spc, sp);
        return spc;
    }
    if (ctx->tb_flags & TB_FLAG_SR_SAME) {
        return cpu_srH;
    }
    ptr = tcg_temp_new_ptr();
    tmp = tcg_temp_new();
    spc = get_temp_tl(ctx);
    tcg_gen_shri_reg(tmp, base, TARGET_REGISTER_BITS - 5);
    tcg_gen_andi_reg(tmp, tmp, 030);
    tcg_gen_trunc_reg_ptr(ptr, tmp);
    tcg_temp_free(tmp);
    tcg_gen_add_ptr(ptr, ptr, cpu_env);
    tcg_gen_ld_i64(spc, ptr, offsetof(CPUHPPAState, sr[4]));
    tcg_temp_free_ptr(ptr);
    return spc;
}
static TCGv_i64 space_select ( DisasContext * ctx , int sp , TCGv_reg base ) { TCGv_ptr ptr ; TCGv_reg tmp ; TCGv_i64 spc ; if ( sp != 0 ) { if ( sp < 0 ) { sp = ~ sp ; } spc = get_temp_tl ( ctx ) ; load_spr ( ctx , spc , sp ) ; return spc ; } if ( ctx -> tb_flags & TB_FLAG_SR_SAME ) { return cpu_srH ; } ptr = tcg_temp_new_ptr ( ) ; tmp = tcg_temp_new ( ) ; spc = get_temp_tl ( ctx ) ; tcg_gen_shri_reg ( tmp , base , TARGET_REGISTER_BITS - 5 ) ; tcg_gen_andi_reg ( tmp , tmp , 030 ) ; tcg_gen_trunc_reg_ptr ( ptr , tmp ) ; tcg_temp_free ( tmp ) ; tcg_gen_add_ptr ( ptr , ptr , cpu_env ) ; tcg_gen_ld_i64 ( spc , ptr , offsetof ( CPUHPPAState , sr [ 4 ] ) ) ; tcg_temp_free_ptr ( ptr ) ; return spc ; }
The "normal" usage is SP >= 0, wherein SP == 0 selects the space
from the top 2 bits of the base register.
The " normal " usage is SP > = 0 wherein SP == 0 selects the space from the top 2 bits of the base register .