FreeBSD/sys/dev/isci/scil/scic_sds_controller.c
/**
 * @brief This is the method provided to handle an MSIX interrupt message
 *        when there is just a single MSIX message being provided by the
 *        hardware.  This mode of operation is single vector mode.
 *
 * @param[in] controller
 *
 * @return BOOL
 * @retval TRUE if an interrupt is processed
 *         FALSE if no interrupt was processed
 */
@brief This is the method provided to handle an MSIX interrupt message
when there is just a single MSIX message being provided by the
hardware.  This mode of operation is single vector mode.

@param[in] controller

@return BOOL
@retval TRUE if an interrupt is processed
FALSE if no interrupt was processed
@brief This is the method provided to handle an MSIX interrupt message when there is just a single MSIX message being provided by the hardware . This mode of operation is single vector mode . @param [ in ] controller @return BOOL @retval TRUE if an interrupt is processed FALSE if no interrupt was processed
static
BOOL scic_sds_controller_single_vector_interrupt_handler(
   SCI_CONTROLLER_HANDLE_T controller
)
{
   U32 interrupt_status;
   SCIC_SDS_CONTROLLER_T *this_controller;
   this_controller = (SCIC_SDS_CONTROLLER_T *)controller;
   SMU_IMR_WRITE(this_controller, 0xFFFFFFFF);
   interrupt_status = SMU_ISR_READ(this_controller);
   interrupt_status &= (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND);
   if (
           (interrupt_status == 0)
        && scic_sds_controller_completion_queue_has_entries(this_controller)
      )
   {
      SMU_ISR_WRITE(this_controller, SMU_ISR_COMPLETION);
      return TRUE;
   }
   if (interrupt_status != 0)
   {
      return TRUE;
   }
   SMU_ISR_WRITE(this_controller, 0x00000000);
   SMU_IMR_WRITE(this_controller, 0x00000000);
   return FALSE;
}
static BOOL scic_sds_controller_single_vector_interrupt_handler ( SCI_CONTROLLER_HANDLE_T controller ) { U32 interrupt_status ; SCIC_SDS_CONTROLLER_T * this_controller ; this_controller = ( SCIC_SDS_CONTROLLER_T * ) controller ; SMU_IMR_WRITE ( this_controller , 0xFFFFFFFF ) ; interrupt_status = SMU_ISR_READ ( this_controller ) ; interrupt_status &= ( SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND ) ; if ( ( interrupt_status == 0 ) && scic_sds_controller_completion_queue_has_entries ( this_controller ) ) { SMU_ISR_WRITE ( this_controller , SMU_ISR_COMPLETION ) ; return TRUE ; } if ( interrupt_status != 0 ) { return TRUE ; } SMU_ISR_WRITE ( this_controller , 0x00000000 ) ; SMU_IMR_WRITE ( this_controller , 0x00000000 ) ; return FALSE ; }
@brief This is the method provided to handle an MSIX interrupt message
        when there is just a single MSIX message being provided by the
        hardware.
@brief This is the method provided to handle an MSIX interrupt message when there is just a single MSIX message being provided by the hardware .
// Mask the interrupts // There is a race in the hardware that could cause us not to be notified // of an interrupt completion if we do not take this step.  We will unmask // the interrupts in the completion routine. // There is at least one completion queue entry to process so we can // return a success and ignore for now the case of an error interrupt // There is an error interrupt pending so let it through and handle // in the callback // Clear any offending interrupts since we could not find any to handle // and unmask them all