abc/src/aig/gia/giaSim.c
// adds PI pattern to storage; the pattern comes in terms of CiIds
adds PI pattern to storage; the pattern comes in terms of CiIds
adds PI pattern to storage ; the pattern comes in terms of CiIds
int Gia_ManBuiltInSimAddPat( Gia_Man_t * p, Vec_Int_t * vPat )
{
    int Period = 0xF;
    int fOverflow = p->iPatsPi == 64 * p->nSimWords && p->nSimWords == p->nSimWordsMax;
    int k, iLit, iPat = Gia_ManBuiltInSimPack( p, vPat );
    if ( iPat == -1 )
    {
        if ( fOverflow )
        {
            if ( (p->iPastPiMax & Period) == 0 )
                Gia_ManBuiltInSimResimulate( p );
            iPat = p->iPastPiMax;
            p->iPastPiMax = p->iPastPiMax == 64 * p->nSimWordsMax - 1 ? 0 : p->iPastPiMax + 1;
        }
        else
        {
            if ( p->iPatsPi && (p->iPatsPi & Period) == 0 )
                Gia_ManBuiltInSimResimulate( p );
            if ( p->iPatsPi == 64 * p->nSimWords )
            {
                Vec_Wrd_t * vTemp = Vec_WrdAlloc( 2 * Vec_WrdSize(p->vSims) ); 
                word Data; int w, Count = 0, iObj = 0;
                Vec_WrdForEachEntry( p->vSims, Data, w )
                {
                    Vec_WrdPush( vTemp, Data );
                    if ( ++Count == p->nSimWords )
                    {
                        Gia_Obj_t * pObj = Gia_ManObj(p, iObj++);
                        if ( Gia_ObjIsCi(pObj) )
                            Vec_WrdPush( vTemp, Gia_ManRandomW(0) ); 
                        else if ( Gia_ObjIsAnd(pObj) )
                            Vec_WrdPush( vTemp, pObj->fPhase ? ~(word)0 : 0 );
                        else
                            Vec_WrdPush( vTemp, 0 );
                        Count = 0;
                    }
                }
                assert( iObj == Gia_ManObjNum(p) );
                Vec_WrdFree( p->vSims );
                p->vSims = vTemp;
                vTemp = Vec_WrdAlloc( 2 * Vec_WrdSize(p->vSimsPi) ); 
                Count = 0;
                Vec_WrdForEachEntry( p->vSimsPi, Data, w )
                {
                    Vec_WrdPush( vTemp, Data );
                    if ( ++Count == p->nSimWords )
                    {
                        Vec_WrdPush( vTemp, 0 );
                        Count = 0;
                    }
                }
                Vec_WrdFree( p->vSimsPi );
                p->vSimsPi = vTemp;
                p->nSimWords++;
                assert( Vec_WrdSize(p->vSims)   == p->nSimWords * Gia_ManObjNum(p) );
                assert( Vec_WrdSize(p->vSimsPi) == p->nSimWords * Gia_ManCiNum(p)  );
            }
            iPat = p->iPatsPi++;
        }
    }
    assert( iPat >= 0 && iPat < p->iPatsPi );
    if ( fOverflow )
    {
        int iVar;
        Vec_IntForEachEntry( &p->vSuppVars, iVar, k )
            if ( Abc_TtGetBit(Gia_ManBuiltInDataPi(p, iVar), iPat) )
                 Abc_TtXorBit(Gia_ManBuiltInDataPi(p, iVar), iPat);
        Vec_IntForEachEntry( vPat, iLit, k )
        {
            if ( Abc_TtGetBit(Gia_ManBuiltInData(p, 1+Abc_Lit2Var(iLit)), iPat) == Abc_LitIsCompl(iLit) )
            Abc_TtXorBit(Gia_ManBuiltInData(p, 1+Abc_Lit2Var(iLit)), iPat);
            Abc_TtXorBit(Gia_ManBuiltInDataPi(p, Abc_Lit2Var(iLit)), iPat);
        }
    }
    else
    {
        Vec_IntForEachEntry( vPat, iLit, k )
        {
            if ( Abc_TtGetBit(Gia_ManBuiltInDataPi(p, Abc_Lit2Var(iLit)), iPat) )
                assert( Abc_TtGetBit(Gia_ManBuiltInData(p, 1+Abc_Lit2Var(iLit)), iPat) != Abc_LitIsCompl(iLit) );
            else 
            {
                if ( Abc_TtGetBit(Gia_ManBuiltInData(p, 1+Abc_Lit2Var(iLit)), iPat) == Abc_LitIsCompl(iLit) )
                Abc_TtXorBit(Gia_ManBuiltInData(p, 1+Abc_Lit2Var(iLit)), iPat);
                Abc_TtXorBit(Gia_ManBuiltInDataPi(p, Abc_Lit2Var(iLit)), iPat);
            }
        }
    }
    return 1;
}
int Gia_ManBuiltInSimAddPat ( Gia_Man_t * p , Vec_Int_t * vPat ) { int Period = 0xF ; int fOverflow = p -> iPatsPi == 64 * p -> nSimWords && p -> nSimWords == p -> nSimWordsMax ; int k , iLit , iPat = Gia_ManBuiltInSimPack ( p , vPat ) ; if ( iPat == -1 ) { if ( fOverflow ) { if ( ( p -> iPastPiMax & Period ) == 0 ) Gia_ManBuiltInSimResimulate ( p ) ; iPat = p -> iPastPiMax ; p -> iPastPiMax = p -> iPastPiMax == 64 * p -> nSimWordsMax - 1 ? 0 : p -> iPastPiMax + 1 ; } else { if ( p -> iPatsPi && ( p -> iPatsPi & Period ) == 0 ) Gia_ManBuiltInSimResimulate ( p ) ; if ( p -> iPatsPi == 64 * p -> nSimWords ) { Vec_Wrd_t * vTemp = Vec_WrdAlloc ( 2 * Vec_WrdSize ( p -> vSims ) ) ; word Data ; int w , Count = 0 , iObj = 0 ; Vec_WrdForEachEntry ( p -> vSims , Data , w ) { Vec_WrdPush ( vTemp , Data ) ; if ( ++ Count == p -> nSimWords ) { Gia_Obj_t * pObj = Gia_ManObj ( p , iObj ++ ) ; if ( Gia_ObjIsCi ( pObj ) ) Vec_WrdPush ( vTemp , Gia_ManRandomW ( 0 ) ) ; else if ( Gia_ObjIsAnd ( pObj ) ) Vec_WrdPush ( vTemp , pObj -> fPhase ? ~ ( word ) 0 : 0 ) ; else Vec_WrdPush ( vTemp , 0 ) ; Count = 0 ; } } assert ( iObj == Gia_ManObjNum ( p ) ) ; Vec_WrdFree ( p -> vSims ) ; p -> vSims = vTemp ; vTemp = Vec_WrdAlloc ( 2 * Vec_WrdSize ( p -> vSimsPi ) ) ; Count = 0 ; Vec_WrdForEachEntry ( p -> vSimsPi , Data , w ) { Vec_WrdPush ( vTemp , Data ) ; if ( ++ Count == p -> nSimWords ) { Vec_WrdPush ( vTemp , 0 ) ; Count = 0 ; } } Vec_WrdFree ( p -> vSimsPi ) ; p -> vSimsPi = vTemp ; p -> nSimWords ++ ; assert ( Vec_WrdSize ( p -> vSims ) == p -> nSimWords * Gia_ManObjNum ( p ) ) ; assert ( Vec_WrdSize ( p -> vSimsPi ) == p -> nSimWords * Gia_ManCiNum ( p ) ) ; } iPat = p -> iPatsPi ++ ; } } assert ( iPat >= 0 && iPat < p -> iPatsPi ) ; if ( fOverflow ) { int iVar ; Vec_IntForEachEntry ( & p -> vSuppVars , iVar , k ) if ( Abc_TtGetBit ( Gia_ManBuiltInDataPi ( p , iVar ) , iPat ) ) Abc_TtXorBit ( Gia_ManBuiltInDataPi ( p , iVar ) , iPat ) ; Vec_IntForEachEntry ( vPat , iLit , k ) { if ( Abc_TtGetBit ( Gia_ManBuiltInData ( p , 1 + Abc_Lit2Var ( iLit ) ) , iPat ) == Abc_LitIsCompl ( iLit ) ) Abc_TtXorBit ( Gia_ManBuiltInData ( p , 1 + Abc_Lit2Var ( iLit ) ) , iPat ) ; Abc_TtXorBit ( Gia_ManBuiltInDataPi ( p , Abc_Lit2Var ( iLit ) ) , iPat ) ; } } else { Vec_IntForEachEntry ( vPat , iLit , k ) { if ( Abc_TtGetBit ( Gia_ManBuiltInDataPi ( p , Abc_Lit2Var ( iLit ) ) , iPat ) ) assert ( Abc_TtGetBit ( Gia_ManBuiltInData ( p , 1 + Abc_Lit2Var ( iLit ) ) , iPat ) != Abc_LitIsCompl ( iLit ) ) ; else { if ( Abc_TtGetBit ( Gia_ManBuiltInData ( p , 1 + Abc_Lit2Var ( iLit ) ) , iPat ) == Abc_LitIsCompl ( iLit ) ) Abc_TtXorBit ( Gia_ManBuiltInData ( p , 1 + Abc_Lit2Var ( iLit ) ) , iPat ) ; Abc_TtXorBit ( Gia_ManBuiltInDataPi ( p , Abc_Lit2Var ( iLit ) ) , iPat ) ; } } } return 1 ; }
adds PI pattern to storage; the pattern comes in terms of CiIds
adds PI pattern to storage ; the pattern comes in terms of CiIds
//if ( p->iPastPiMax == 64 * p->nSimWordsMax - 1 ) //    printf( "Completed the cycle.\n" ); // Vec_WrdPush( vTemp, 0 ); // update the word count //printf( "Resizing to %d words.\n", p->nSimWords ); // add literals 