Platform/ECM3532/M3/hw/csp/ecm3532/m3/csp/src/eta_csp_spi.c
/***************************************************************************/
/**
 *
 *  EtaCspSpiProcessIntEntry - Entry for Interrupts for Spi
 *
 *  @param iNum the Spi number.
 *
 ******************************************************************************/
Entry for Interrupts for Spi
@param iNum the Spi number.
Entry for Interrupts for Spi @param iNum the Spi number .
tEtaStatus EtaCspSpiProcessIntEntry (tSpiNum iNum)
{
  uint32_t active_interrupt;
  tEtaStatus spiStatus = eEtaSuccess;
  active_interrupt = MEMIO16(REG_SPI_INT_ACT_ADDR (iNum));
  if (active_interrupt & BM_SPI_INT_ACT_TXFIFO_HAS_LEVEL_SPACE_ACT ) spiStatus |= EtaCspSpiProcessIntTxData  (iNum) ;
  if (active_interrupt & BM_SPI_INT_ACT_RX_FIFO_HIT_LEVEL_ACT      ) spiStatus |= EtaCspSpiProcessIntRxData  (iNum) ;
  if (active_interrupt & BM_SPI_INT_ACT_XMIT_COMPLETE_ACT          ) spiStatus |= EtaCspSpiProcessIntXmitDone (iNum) ;
  if (active_interrupt & BM_SPI_INT_ACT_CMD_IS_DONE_ACT            ) spiStatus |= EtaCspSpiProcessIntCmdDone (iNum) ;
  REG_GPIO_DEBUG1_READ_ONLY.V = REG_SPI_CONFIG(iNum).V;
  if (active_interrupt & BM_SPI_INT_ACT_TXFIFO_HAS_LEVEL_SPACE_ACT )  EtaCspSpiProcessIntTxData(instance);
  if (active_interrupt & BM_SPI_INT_ACT_RX_FIFO_HIT_LEVEL_ACT )       EtaCspSpiProcessIntRxData(instance);
  if (active_interrupt & BM_SPI_INT_ACT_CMD_IS_DONE_ACT )             EtaCspSpiProcessIntCmdDone(instance);
   Fence to make sure all writes get flushed
  REG_GPIO_DEBUG1_READ_ONLY.V = REG_SPI_CONFIG(instance).V;
  return spiStatus;
}
tEtaStatus EtaCspSpiProcessIntEntry ( tSpiNum iNum ) { uint32_t active_interrupt ; tEtaStatus spiStatus = eEtaSuccess ; active_interrupt = MEMIO16 ( REG_SPI_INT_ACT_ADDR ( iNum ) ) ; if ( active_interrupt & BM_SPI_INT_ACT_TXFIFO_HAS_LEVEL_SPACE_ACT ) spiStatus |= EtaCspSpiProcessIntTxData ( iNum ) ; if ( active_interrupt & BM_SPI_INT_ACT_RX_FIFO_HIT_LEVEL_ACT ) spiStatus |= EtaCspSpiProcessIntRxData ( iNum ) ; if ( active_interrupt & BM_SPI_INT_ACT_XMIT_COMPLETE_ACT ) spiStatus |= EtaCspSpiProcessIntXmitDone ( iNum ) ; if ( active_interrupt & BM_SPI_INT_ACT_CMD_IS_DONE_ACT ) spiStatus |= EtaCspSpiProcessIntCmdDone ( iNum ) ; REG_GPIO_DEBUG1_READ_ONLY . V = REG_SPI_CONFIG ( iNum ) . V ; return spiStatus ; }
EtaCspSpiProcessIntEntry - Entry for Interrupts for Spi
  @param iNum the Spi number.
EtaCspSpiProcessIntEntry - Entry for Interrupts for Spi @param iNum the Spi number .
// Do one read per interrupt. The INT_ACT field may change during the interrupt // FENCE TO MAKE SURE ALL WRITES GET FLUSHED //  // Do one read per interrupt. The INT_ACT field may change during the interrupt //  if (USE_MEMIO_CALLS) //    active_interrupt = MEMIO16(REG_SPI_INT_ACT_ADDR (instance)); //  else //    active_interrupt = REG_SPI_INT_ACT(instance).V; // //  if (active_interrupt & BM_SPI_INT_ACT_TXFIFO_HAS_LEVEL_SPACE_ACT )  EtaCspSpiProcessIntTxData(instance); //  if (active_interrupt & BM_SPI_INT_ACT_RX_FIFO_HIT_LEVEL_ACT )       EtaCspSpiProcessIntRxData(instance); //  if (active_interrupt & BM_SPI_INT_ACT_CMD_IS_DONE_ACT )             EtaCspSpiProcessIntCmdDone(instance); // //  // Fence to make sure all writes get flushed //  REG_GPIO_DEBUG1_READ_ONLY.V = REG_SPI_CONFIG(instance).V;