FreeBSD/sys/arm/arm/pmap-v6.c
/*
 *  Change pte1 on current pmap.
 *  Note that kernel pte1 must be changed on all pmaps.
 *
 *  According to the architecture reference manual published by ARM,
 *  the behaviour is UNPREDICTABLE when two or more TLB entries map the same VA.
 *  According to this manual, UNPREDICTABLE behaviours must never happen in
 *  a viable system. In contrast, on x86 processors, it is not specified which
 *  TLB entry mapping the virtual address will be used, but the MMU doesn't
 *  generate a bogus translation the way it does on Cortex-A8 rev 2 (Beaglebone
 *  Black).
 *
 *  It's a problem when either promotion or demotion is being done. The pte1
 *  update and appropriate TLB flush must be done atomically in general.
 */
Change pte1 on current pmap.
Note that kernel pte1 must be changed on all pmaps.

According to the architecture reference manual published by ARM,
the behaviour is UNPREDICTABLE when two or more TLB entries map the same VA.
According to this manual, UNPREDICTABLE behaviours must never happen in
a viable system. In contrast, on x86 processors, it is not specified which
TLB entry mapping the virtual address will be used, but the MMU doesn't
generate a bogus translation the way it does on Cortex-A8 rev 2 (Beaglebone
Black).

It's a problem when either promotion or demotion is being done. The pte1
update and appropriate TLB flush must be done atomically in general.
Change pte1 on current pmap . Note that kernel pte1 must be changed on all pmaps . According to the architecture reference manual published by ARM the behaviour is UNPREDICTABLE when two or more TLB entries map the same VA . According to this manual UNPREDICTABLE behaviours must never happen in a viable system . In contrast on x86 processors it is not specified which TLB entry mapping the virtual address will be used but the MMU doesn ' t generate a bogus translation the way it does on Cortex - A8 rev 2 ( Beaglebone Black ) . It ' s a problem when either promotion or demotion is being done . The pte1 update and appropriate TLB flush must be done atomically in general .
static void
pmap_change_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va,
    pt1_entry_t npte1)
{
	if (pmap == kernel_pmap) {
		struct pte1_action act;
		sched_pin();
		act.va = va;
		act.npte1 = npte1;
		act.update = PCPU_GET(cpuid);
		smp_rendezvous_cpus(all_cpus, smp_no_rendevous_barrier,
		    pmap_update_pte1_action, NULL, &act);
		sched_unpin();
	} else {
		register_t cspr;
		cspr = disable_interrupts(PSR_I | PSR_F);
		pte1_clear(pte1p);
		pmap_tlb_flush_pte1(pmap, va, npte1);
		pte1_store(pte1p, npte1);
		restore_interrupts(cspr);
	}
}
static void pmap_change_pte1 ( pmap_t pmap , pt1_entry_t * pte1p , vm_offset_t va , pt1_entry_t npte1 ) { if ( pmap == kernel_pmap ) { struct pte1_action act ; sched_pin ( ) ; act . va = va ; act . npte1 = npte1 ; act . update = PCPU_GET ( cpuid ) ; smp_rendezvous_cpus ( all_cpus , smp_no_rendevous_barrier , pmap_update_pte1_action , NULL , & act ) ; sched_unpin ( ) ; } else { register_t cspr ; cspr = disable_interrupts ( PSR_I | PSR_F ) ; pte1_clear ( pte1p ) ; pmap_tlb_flush_pte1 ( pmap , va , npte1 ) ; pte1_store ( pte1p , npte1 ) ; restore_interrupts ( cspr ) ; } }
Change pte1 on current pmap.
Change pte1 on current pmap .
/*
		 * Use break-before-make approach for changing userland
		 * mappings. It can cause L1 translation aborts on other
		 * cores in SMP case. So, special treatment is implemented
		 * in pmap_fault(). To reduce the likelihood that another core
		 * will be affected by the broken mapping, disable interrupts
		 * until the mapping change is completed.
		 */