sys/dev/drm/i915/intel_overlay.c
/* overlay needs to be disable in OCMD reg */
overlay needs to be disable in OCMD reg
overlay needs to be disable in OCMD reg
static int intel_overlay_on(struct intel_overlay *overlay)
{
	struct drm_i915_private *dev_priv = overlay->i915;
	struct intel_engine_cs *engine = &dev_priv->engine[RCS];
	struct drm_i915_gem_request *req;
	int ret;
	WARN_ON(overlay->active);
	WARN_ON(IS_I830(dev_priv) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE));
	req = i915_gem_request_alloc(engine, NULL);
	if (IS_ERR(req))
		return PTR_ERR(req);
	ret = intel_ring_begin(req, 4);
	if (ret) {
		i915_add_request_no_flush(req);
		return ret;
	}
	overlay->active = true;
	intel_ring_emit(engine, MI_OVERLAY_FLIP | MI_OVERLAY_ON);
	intel_ring_emit(engine, overlay->flip_addr | OFC_UPDATE);
	intel_ring_emit(engine, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
	intel_ring_emit(engine, MI_NOOP);
	intel_ring_advance(engine);
	return intel_overlay_do_wait_request(overlay, req, NULL);
}
static int intel_overlay_on ( struct intel_overlay * overlay ) { struct drm_i915_private * dev_priv = overlay -> i915 ; struct intel_engine_cs * engine = & dev_priv -> engine [ RCS ] ; struct drm_i915_gem_request * req ; int ret ; WARN_ON ( overlay -> active ) ; WARN_ON ( IS_I830 ( dev_priv ) && ! ( dev_priv -> quirks & QUIRK_PIPEA_FORCE ) ) ; req = i915_gem_request_alloc ( engine , NULL ) ; if ( IS_ERR ( req ) ) return PTR_ERR ( req ) ; ret = intel_ring_begin ( req , 4 ) ; if ( ret ) { i915_add_request_no_flush ( req ) ; return ret ; } overlay -> active = true ; intel_ring_emit ( engine , MI_OVERLAY_FLIP | MI_OVERLAY_ON ) ; intel_ring_emit ( engine , overlay -> flip_addr | OFC_UPDATE ) ; intel_ring_emit ( engine , MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP ) ; intel_ring_emit ( engine , MI_NOOP ) ; intel_ring_advance ( engine ) ; return intel_overlay_do_wait_request ( overlay , req , NULL ) ; }
overlay needs to be disable in OCMD reg
overlay needs to be disable in OCMD reg