src/lima/pp_lir/regalloc.c
/*
 * The following implements the graph-coloring register allocator
 * described in "Retargetable Graph-Coloring Register Allocation for Irregular
 * Architectures" by Runeson and Nystrom. In our architecture, we have 4 register
 * classes based upon the size of the virtual register. There are 6 vec4's. Each
 * vec4 has 2 vec3's (.xyz and .yzw), 3 vec2's (.xy, .yz, and .zw), and 4 scalar
 * registers (z, y, z, and w) because each virtual register must be allocated inside
 * a vec4.
 *
 * In addition, for registers used/defined for loads/stores, for which there is no
 * swizzle field and therefore the (virtual) register must be allocated at the
 * beginning of a (physical) register, there are another 4 classes, indicated in
 * the lima_pp_lir_reg_t struct by the "beginning" field. There is only 1 virtual reg
 * per physical reg for each class, for obvious reasons.
 */
The following implements the graph-coloring register allocator
described in "Retargetable Graph-Coloring Register Allocation for Irregular
Architectures" by Runeson and Nystrom. In our architecture, we have 4 register
classes based upon the size of the virtual register. There are 6 vec4's. Each
vec4 has 2 vec3's (.xyz and .yzw), 3 vec2's (.xy, .yz, and .zw), and 4 scalar
registers (z, y, z, and w) because each virtual register must be allocated inside
a vec4.

In addition, for registers used/defined for loads/stores, for which there is no
swizzle field and therefore the (virtual) register must be allocated at the
beginning of a (physical) register, there are another 4 classes, indicated in
the lima_pp_lir_reg_t struct by the "beginning" field. There is only 1 virtual reg
per physical reg for each class, for obvious reasons.
The following implements the graph - coloring register allocator described in " Retargetable Graph - Coloring Register Allocation for Irregular Architectures " by Runeson and Nystrom . In our architecture we have 4 register classes based upon the size of the virtual register . There are 6 vec4 ' s . Each vec4 has 2 vec3 ' s ( . xyz and . yzw ) 3 vec2 ' s ( . xy . yz and . zw ) and 4 scalar registers ( z y z and w ) because each virtual register must be allocated inside a vec4 . In addition for registers used / defined for loads / stores for which there is no swizzle field and therefore the ( virtual ) register must be allocated at the beginning of a ( physical ) register there are another 4 classes indicated in the lima_pp_lir_reg_t struct by the " beginning " field . There is only 1 virtual reg per physical reg for each class for obvious reasons .
static void init_regs(lima_pp_lir_prog_t* prog)
{
	unsigned i, index = 0;
	for (i = 0; i < prog->num_regs; i++)
	{
		lima_pp_lir_reg_t* reg = prog->regs[i];
		if (reg->precolored)
		{
			reg->q_total = prog->reg_alloc + 6;
		}
		else
		{
			reg->q_total = 0; 
			reg->index = index++;
		}
		reg->state = lima_pp_lir_reg_state_initial;
		ptr_vector_clear(&reg->adjacent);
		ptrset_empty(&reg->moves);
	}
	prog->reg_alloc = index;
}
static void init_regs ( lima_pp_lir_prog_t * prog ) { unsigned i , index = 0 ; for ( i = 0 ; i < prog -> num_regs ; i ++ ) { lima_pp_lir_reg_t * reg = prog -> regs [ i ] ; if ( reg -> precolored ) { reg -> q_total = prog -> reg_alloc + 6 ; } else { reg -> q_total = 0 ; reg -> index = index ++ ; } reg -> state = lima_pp_lir_reg_state_initial ; ptr_vector_clear ( & reg -> adjacent ) ; ptrset_empty ( & reg -> moves ) ; } prog -> reg_alloc = index ; }
The following implements the graph-coloring register allocator
 described in "Retargetable Graph-Coloring Register Allocation for Irregular
 Architectures" by Runeson and Nystrom.
The following implements the graph - coloring register allocator described in " Retargetable Graph - Coloring Register Allocation for Irregular Architectures " by Runeson and Nystrom .
//Conservative; this value should never drop below 6 //Initialized in add_edge()