libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/stm32f10x_dma.c
/**
  * @brief  Deinitializes the DMAy Channelx registers to their default reset
  *         values.
  * @param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and
  *   x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
  * @retval None
  */
@brief  Deinitializes the DMAy Channelx registers to their default reset
values.
@param  DMAy_Channelx: where y can be 1 or 2 to select the DMA and
x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
@retval None
@brief Deinitializes the DMAy Channelx registers to their default reset values . @param DMAy_Channelx : where y can be 1 or 2 to select the DMA and x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel . @retval None
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
{
  assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
  DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
  DMAy_Channelx->CCR  = 0;
  DMAy_Channelx->CNDTR = 0;
  DMAy_Channelx->CPAR  = 0;
  DMAy_Channelx->CMAR = 0;
  if (DMAy_Channelx == DMA1_Channel1)
  {
    DMA1->IFCR |= DMA1_Channel1_IT_Mask;
  }
  else if (DMAy_Channelx == DMA1_Channel2)
  {
    DMA1->IFCR |= DMA1_Channel2_IT_Mask;
  }
  else if (DMAy_Channelx == DMA1_Channel3)
  {
    DMA1->IFCR |= DMA1_Channel3_IT_Mask;
  }
  else if (DMAy_Channelx == DMA1_Channel4)
  {
    DMA1->IFCR |= DMA1_Channel4_IT_Mask;
  }
  else if (DMAy_Channelx == DMA1_Channel5)
  {
    DMA1->IFCR |= DMA1_Channel5_IT_Mask;
  }
  else if (DMAy_Channelx == DMA1_Channel6)
  {
    DMA1->IFCR |= DMA1_Channel6_IT_Mask;
  }
  else if (DMAy_Channelx == DMA1_Channel7)
  {
    DMA1->IFCR |= DMA1_Channel7_IT_Mask;
  }
  else if (DMAy_Channelx == DMA2_Channel1)
  {
    DMA2->IFCR |= DMA2_Channel1_IT_Mask;
  }
  else if (DMAy_Channelx == DMA2_Channel2)
  {
    DMA2->IFCR |= DMA2_Channel2_IT_Mask;
  }
  else if (DMAy_Channelx == DMA2_Channel3)
  {
    DMA2->IFCR |= DMA2_Channel3_IT_Mask;
  }
  else if (DMAy_Channelx == DMA2_Channel4)
  {
    DMA2->IFCR |= DMA2_Channel4_IT_Mask;
  }
  else
  { 
    if (DMAy_Channelx == DMA2_Channel5)
    {
      DMA2->IFCR |= DMA2_Channel5_IT_Mask;
    }
  }
}
void DMA_DeInit ( DMA_Channel_TypeDef * DMAy_Channelx ) { assert_param ( IS_DMA_ALL_PERIPH ( DMAy_Channelx ) ) ; DMAy_Channelx -> CCR &= ( uint16_t ) ( ~ DMA_CCR1_EN ) ; DMAy_Channelx -> CCR = 0 ; DMAy_Channelx -> CNDTR = 0 ; DMAy_Channelx -> CPAR = 0 ; DMAy_Channelx -> CMAR = 0 ; if ( DMAy_Channelx == DMA1_Channel1 ) { DMA1 -> IFCR |= DMA1_Channel1_IT_Mask ; } else if ( DMAy_Channelx == DMA1_Channel2 ) { DMA1 -> IFCR |= DMA1_Channel2_IT_Mask ; } else if ( DMAy_Channelx == DMA1_Channel3 ) { DMA1 -> IFCR |= DMA1_Channel3_IT_Mask ; } else if ( DMAy_Channelx == DMA1_Channel4 ) { DMA1 -> IFCR |= DMA1_Channel4_IT_Mask ; } else if ( DMAy_Channelx == DMA1_Channel5 ) { DMA1 -> IFCR |= DMA1_Channel5_IT_Mask ; } else if ( DMAy_Channelx == DMA1_Channel6 ) { DMA1 -> IFCR |= DMA1_Channel6_IT_Mask ; } else if ( DMAy_Channelx == DMA1_Channel7 ) { DMA1 -> IFCR |= DMA1_Channel7_IT_Mask ; } else if ( DMAy_Channelx == DMA2_Channel1 ) { DMA2 -> IFCR |= DMA2_Channel1_IT_Mask ; } else if ( DMAy_Channelx == DMA2_Channel2 ) { DMA2 -> IFCR |= DMA2_Channel2_IT_Mask ; } else if ( DMAy_Channelx == DMA2_Channel3 ) { DMA2 -> IFCR |= DMA2_Channel3_IT_Mask ; } else if ( DMAy_Channelx == DMA2_Channel4 ) { DMA2 -> IFCR |= DMA2_Channel4_IT_Mask ; } else { if ( DMAy_Channelx == DMA2_Channel5 ) { DMA2 -> IFCR |= DMA2_Channel5_IT_Mask ; } } }
@brief  Deinitializes the DMAy Channelx registers to their default reset
         values.
@brief Deinitializes the DMAy Channelx registers to their default reset values .
/* Check the parameters */ /* Disable the selected DMAy Channelx */ /* Reset DMAy Channelx control register */ /* Reset DMAy Channelx remaining bytes register */ /* Reset DMAy Channelx peripheral address register */ /* Reset DMAy Channelx memory address register */ /* Reset interrupt pending bits for DMA1 Channel1 */ /* Reset interrupt pending bits for DMA1 Channel2 */ /* Reset interrupt pending bits for DMA1 Channel3 */ /* Reset interrupt pending bits for DMA1 Channel4 */ /* Reset interrupt pending bits for DMA1 Channel5 */ /* Reset interrupt pending bits for DMA1 Channel6 */ /* Reset interrupt pending bits for DMA1 Channel7 */ /* Reset interrupt pending bits for DMA2 Channel1 */ /* Reset interrupt pending bits for DMA2 Channel2 */ /* Reset interrupt pending bits for DMA2 Channel3 */ /* Reset interrupt pending bits for DMA2 Channel4 */ /* Reset interrupt pending bits for DMA2 Channel5 */