smart_lock_cm33_core1/drivers/fsl_power.c
/**
 * brief    PMC power Down function call
 * return   nothing
 */
brief    PMC power Down function call
return   nothing
brief PMC power Down function call return nothing
void POWER_PowerDown(uint32_t exclude_from_pd,
                     uint32_t sram_retention_ctrl,
                     uint64_t wakeup_interrupts,
                     uint32_t cpu_retention_ctrl)
{
    LPC_LOWPOWER_T lv_low_power_mode_cfg; 
    uint32_t cpu0_nmi_enable;
    uint32_t cpu0_int_enable_0;
    uint32_t cpu0_int_enable_1;
    uint64_t wakeup_src_int;
    memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T));
    lv_low_power_mode_cfg.CFG |= LOWPOWER_CFG_LPMODE_POWERDOWN << LOWPOWER_CFG_LPMODE_INDEX; 
    lv_low_power_mode_cfg.PDCTRL0 =
        (~exclude_from_pd) | kPDRUNCFG_PD_BODVBAT | kPDRUNCFG_PD_FRO1M | kPDRUNCFG_PD_LDODEEPSLEEP;
    lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl;
    if ((sram_retention_ctrl & 0x7FFF) != 0)
    {
        lv_low_power_mode_cfg.PDCTRL0 &= ~kPDRUNCFG_PD_LDOMEM;
    }
    lv_low_power_mode_cfg.VOLTAGE = (V_AO_0P800 << LOWPOWER_VOLTAGE_LDO_PMU_INDEX) |       
                                    (V_AO_0P750 << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX) | 
                                    (V_AO_1P100 << LOWPOWER_VOLTAGE_LDO_MEM_INDEX) |       
                                    (V_AO_1P050 << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX)   
        ;
    lv_low_power_mode_cfg.CPURETCTRL = (cpu_retention_ctrl & 0x1) << LOWPOWER_CPURETCTRL_ENA_INDEX;
    wakeup_src_int = (uint64_t)(WAKEUP_GPIO_GLOBALINT0 | WAKEUP_GPIO_GLOBALINT1 | WAKEUP_FLEXCOMM3 | WAKEUP_ACMP_CAPT |
                                WAKEUP_RTC_LITE_ALARM_WAKEUP | WAKEUP_OS_EVENT_TIMER);
    lv_low_power_mode_cfg.WAKEUPINT = wakeup_interrupts & wakeup_src_int;
    lv_low_power_mode_cfg.WAKEUPSRC = wakeup_interrupts & wakeup_src_int;
    cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; 
    SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK;                 
    cpu0_int_enable_0 = NVIC->ISER[0];
    cpu0_int_enable_1 = NVIC->ISER[1];
    Power_EnterLowPower(&lv_low_power_mode_cfg);
    SYSCON->NMISRC |= cpu0_nmi_enable;
    NVIC->ISER[0] = cpu0_int_enable_0;
    NVIC->ISER[1] = cpu0_int_enable_1;
}
void POWER_PowerDown ( uint32_t exclude_from_pd , uint32_t sram_retention_ctrl , uint64_t wakeup_interrupts , uint32_t cpu_retention_ctrl ) { LPC_LOWPOWER_T lv_low_power_mode_cfg ; uint32_t cpu0_nmi_enable ; uint32_t cpu0_int_enable_0 ; uint32_t cpu0_int_enable_1 ; uint64_t wakeup_src_int ; memset ( & lv_low_power_mode_cfg , 0x0 , sizeof ( LPC_LOWPOWER_T ) ) ; lv_low_power_mode_cfg . CFG |= LOWPOWER_CFG_LPMODE_POWERDOWN << LOWPOWER_CFG_LPMODE_INDEX ; lv_low_power_mode_cfg . PDCTRL0 = ( ~ exclude_from_pd ) | kPDRUNCFG_PD_BODVBAT | kPDRUNCFG_PD_FRO1M | kPDRUNCFG_PD_LDODEEPSLEEP ; lv_low_power_mode_cfg . SRAMRETCTRL = sram_retention_ctrl ; if ( ( sram_retention_ctrl & 0x7FFF ) != 0 ) { lv_low_power_mode_cfg . PDCTRL0 &= ~ kPDRUNCFG_PD_LDOMEM ; } lv_low_power_mode_cfg . VOLTAGE = ( V_AO_0P800 << LOWPOWER_VOLTAGE_LDO_PMU_INDEX ) | ( V_AO_0P750 << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX ) | ( V_AO_1P100 << LOWPOWER_VOLTAGE_LDO_MEM_INDEX ) | ( V_AO_1P050 << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX ) ; lv_low_power_mode_cfg . CPURETCTRL = ( cpu_retention_ctrl & 0x1 ) << LOWPOWER_CPURETCTRL_ENA_INDEX ; wakeup_src_int = ( uint64_t ) ( WAKEUP_GPIO_GLOBALINT0 | WAKEUP_GPIO_GLOBALINT1 | WAKEUP_FLEXCOMM3 | WAKEUP_ACMP_CAPT | WAKEUP_RTC_LITE_ALARM_WAKEUP | WAKEUP_OS_EVENT_TIMER ) ; lv_low_power_mode_cfg . WAKEUPINT = wakeup_interrupts & wakeup_src_int ; lv_low_power_mode_cfg . WAKEUPSRC = wakeup_interrupts & wakeup_src_int ; cpu0_nmi_enable = SYSCON -> NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK ; SYSCON -> NMISRC &= ~ SYSCON_NMISRC_NMIENCPU0_MASK ; cpu0_int_enable_0 = NVIC -> ISER [ 0 ] ; cpu0_int_enable_1 = NVIC -> ISER [ 1 ] ; Power_EnterLowPower ( & lv_low_power_mode_cfg ) ; SYSCON -> NMISRC |= cpu0_nmi_enable ; NVIC -> ISER [ 0 ] = cpu0_int_enable_0 ; NVIC -> ISER [ 1 ] = cpu0_int_enable_1 ; }
brief    PMC power Down function call
 return   nothing
brief PMC power Down function call return nothing
/* Low Power Mode configuration structure */ /* Clear Low Power Mode configuration variable */ /* Configure Low Power Mode configuration variable */ /* POWER DOWN mode */ /* Only FRO32K, XTAL32K, COMP, BIAS and LDO_MEM can be stay powered during POWERDOWN (valid from application point
     * of view; Hardware allows BODVBAT, LDODEEPSLEEP and FRO1M to stay powered, that's why they are excluded below) */ /* SRAM retention control during POWERDOWN */ /* Sanity check: If retention is required for any of SRAM instances, make sure LDO MEM will stay powered */ /* Voltage control in Low Power Modes */ /* TODO :: :: The Memories Voltage settings below are valid for Source Biasing; for voltage scaling, they need to be
     * update */ /* Set to 0.80 V */ /* Set to 0.75 V */ /* Set to 1.10 V */ /* Set to 1.05 V */ /* CPU0 retention Ctrl.
     * For the time being, we do not allow customer to relocate the CPU retention area in SRAMX, meaning that the
     * retention area range is [0x0400_6000 - 0x0400_6600] (beginning of RAMX2)
     * If required by customer, cpu_retention_ctrl[13:1] will be used for that to modify the default retention area
     */ /* CPU Wake up & Interrupt sources control : only WAKEUP_GPIO_GLOBALINT0, WAKEUP_GPIO_GLOBALINT1, WAKEUP_FLEXCOMM3,
     * WAKEUP_ACMP_CAPT, WAKEUP_RTC_LITE_ALARM_WAKEUP, WAKEUP_OS_EVENT_TIMER */ /* Save the configuration of the NMI Register */ /* Disable NMI of CPU0 */ /* Save the configuration of the CPU interrupt enable Registers (because they are overwritten inside the low power
     * API */ /* Enter low power mode */ /*** We'll reach this point in case of POWERDOWN with CPU retention or if the POWERDOWN has not been taken (for
       instance because an interrupt is pending).
        In case of CPU retention, assumption is that the SRAM containing the stack used to call this function shall be
       preserved during low power ***/ /* Restore the configuration of the NMI Register */ /* Restore the configuration of the CPU interrupt enable Registers (because they have been overwritten inside the
     * low power API */