FreeBSD/sys/sparc64/sparc64/cheetah.c
/*
 * Flush all user mappings from the TLBs.
 */
Flush all user mappings from the TLBs.
Flush all user mappings from the TLBs .
void
cheetah_tlb_flush_user(void)
{
	u_long data, tag;
	register_t s;
	u_int i, slot;
	for (i = 0; i < CHEETAH_T16_ENTRIES; i++) {
		slot = TLB_DAR_SLOT(TLB_DAR_T16, i);
		s = intr_disable();
		(void)ldxa(slot, ASI_DTLB_DATA_ACCESS_REG);
		data = ldxa(slot, ASI_DTLB_DATA_ACCESS_REG);
		intr_restore(s);
		tag = ldxa(slot, ASI_DTLB_TAG_READ_REG);
		if ((data & TD_V) != 0 && (data & TD_L) == 0 &&
		    TLB_TAR_CTX(tag) != TLB_CTX_KERNEL)
			stxa_sync(slot, ASI_DTLB_DATA_ACCESS_REG, 0);
		s = intr_disable();
		(void)ldxa(slot, ASI_ITLB_DATA_ACCESS_REG);
		data = ldxa(slot, ASI_ITLB_DATA_ACCESS_REG);
		intr_restore(s);
		tag = ldxa(slot, ASI_ITLB_TAG_READ_REG);
		if ((data & TD_V) != 0 && (data & TD_L) == 0 &&
		    TLB_TAR_CTX(tag) != TLB_CTX_KERNEL)
			stxa_sync(slot, ASI_ITLB_DATA_ACCESS_REG, 0);
	}
	for (i = 0; i < CHEETAH_DT512_ENTRIES; i++) {
		slot = TLB_DAR_SLOT(TLB_DAR_DT512_0, i);
		s = intr_disable();
		(void)ldxa(slot, ASI_DTLB_DATA_ACCESS_REG);
		data = ldxa(slot, ASI_DTLB_DATA_ACCESS_REG);
		intr_restore(s);
		tag = ldxa(slot, ASI_DTLB_TAG_READ_REG);
		if ((data & TD_V) != 0 && TLB_TAR_CTX(tag) != TLB_CTX_KERNEL)
			stxa_sync(slot, ASI_DTLB_DATA_ACCESS_REG, 0);
		slot = TLB_DAR_SLOT(TLB_DAR_DT512_1, i);
		s = intr_disable();
		(void)ldxa(slot, ASI_ITLB_DATA_ACCESS_REG);
		data = ldxa(slot, ASI_DTLB_DATA_ACCESS_REG);
		intr_restore(s);
		tag = ldxa(slot, ASI_DTLB_TAG_READ_REG);
		if ((data & TD_V) != 0 && TLB_TAR_CTX(tag) != TLB_CTX_KERNEL)
			stxa_sync(slot, ASI_DTLB_DATA_ACCESS_REG, 0);
	}
	if (PCPU_GET(impl) == CPU_IMPL_ULTRASPARCIVp) {
		for (i = 0; i < CHEETAH_IT512_ENTRIES; i++) {
			slot = TLB_DAR_SLOT(TLB_DAR_IT512, i);
			s = intr_disable();
			(void)ldxa(slot, ASI_ITLB_DATA_ACCESS_REG);
			data = ldxa(slot, ASI_ITLB_DATA_ACCESS_REG);
			intr_restore(s);
			tag = ldxa(slot, ASI_ITLB_TAG_READ_REG);
			if ((data & TD_V) != 0 &&
			    TLB_TAR_CTX(tag) != TLB_CTX_KERNEL)
				stxa_sync(slot, ASI_ITLB_DATA_ACCESS_REG, 0);
		}
	} else {
		for (i = 0; i < CHEETAH_IT128_ENTRIES; i++) {
			slot = TLB_DAR_SLOT(TLB_DAR_IT128, i);
			s = intr_disable();
			(void)ldxa(slot, ASI_ITLB_DATA_ACCESS_REG);
			data = ldxa(slot, ASI_ITLB_DATA_ACCESS_REG);
			tag = ldxa(slot, ASI_ITLB_TAG_READ_REG);
			intr_restore(s);
			if ((data & TD_V) != 0 &&
			    TLB_TAR_CTX(tag) != TLB_CTX_KERNEL)
				stxa_sync(slot, ASI_ITLB_DATA_ACCESS_REG, 0);
		}
	}
}
void cheetah_tlb_flush_user ( void ) { u_long data , tag ; register_t s ; u_int i , slot ; for ( i = 0 ; i < CHEETAH_T16_ENTRIES ; i ++ ) { slot = TLB_DAR_SLOT ( TLB_DAR_T16 , i ) ; s = intr_disable ( ) ; ( void ) ldxa ( slot , ASI_DTLB_DATA_ACCESS_REG ) ; data = ldxa ( slot , ASI_DTLB_DATA_ACCESS_REG ) ; intr_restore ( s ) ; tag = ldxa ( slot , ASI_DTLB_TAG_READ_REG ) ; if ( ( data & TD_V ) != 0 && ( data & TD_L ) == 0 && TLB_TAR_CTX ( tag ) != TLB_CTX_KERNEL ) stxa_sync ( slot , ASI_DTLB_DATA_ACCESS_REG , 0 ) ; s = intr_disable ( ) ; ( void ) ldxa ( slot , ASI_ITLB_DATA_ACCESS_REG ) ; data = ldxa ( slot , ASI_ITLB_DATA_ACCESS_REG ) ; intr_restore ( s ) ; tag = ldxa ( slot , ASI_ITLB_TAG_READ_REG ) ; if ( ( data & TD_V ) != 0 && ( data & TD_L ) == 0 && TLB_TAR_CTX ( tag ) != TLB_CTX_KERNEL ) stxa_sync ( slot , ASI_ITLB_DATA_ACCESS_REG , 0 ) ; } for ( i = 0 ; i < CHEETAH_DT512_ENTRIES ; i ++ ) { slot = TLB_DAR_SLOT ( TLB_DAR_DT512_0 , i ) ; s = intr_disable ( ) ; ( void ) ldxa ( slot , ASI_DTLB_DATA_ACCESS_REG ) ; data = ldxa ( slot , ASI_DTLB_DATA_ACCESS_REG ) ; intr_restore ( s ) ; tag = ldxa ( slot , ASI_DTLB_TAG_READ_REG ) ; if ( ( data & TD_V ) != 0 && TLB_TAR_CTX ( tag ) != TLB_CTX_KERNEL ) stxa_sync ( slot , ASI_DTLB_DATA_ACCESS_REG , 0 ) ; slot = TLB_DAR_SLOT ( TLB_DAR_DT512_1 , i ) ; s = intr_disable ( ) ; ( void ) ldxa ( slot , ASI_ITLB_DATA_ACCESS_REG ) ; data = ldxa ( slot , ASI_DTLB_DATA_ACCESS_REG ) ; intr_restore ( s ) ; tag = ldxa ( slot , ASI_DTLB_TAG_READ_REG ) ; if ( ( data & TD_V ) != 0 && TLB_TAR_CTX ( tag ) != TLB_CTX_KERNEL ) stxa_sync ( slot , ASI_DTLB_DATA_ACCESS_REG , 0 ) ; } if ( PCPU_GET ( impl ) == CPU_IMPL_ULTRASPARCIVp ) { for ( i = 0 ; i < CHEETAH_IT512_ENTRIES ; i ++ ) { slot = TLB_DAR_SLOT ( TLB_DAR_IT512 , i ) ; s = intr_disable ( ) ; ( void ) ldxa ( slot , ASI_ITLB_DATA_ACCESS_REG ) ; data = ldxa ( slot , ASI_ITLB_DATA_ACCESS_REG ) ; intr_restore ( s ) ; tag = ldxa ( slot , ASI_ITLB_TAG_READ_REG ) ; if ( ( data & TD_V ) != 0 && TLB_TAR_CTX ( tag ) != TLB_CTX_KERNEL ) stxa_sync ( slot , ASI_ITLB_DATA_ACCESS_REG , 0 ) ; } } else { for ( i = 0 ; i < CHEETAH_IT128_ENTRIES ; i ++ ) { slot = TLB_DAR_SLOT ( TLB_DAR_IT128 , i ) ; s = intr_disable ( ) ; ( void ) ldxa ( slot , ASI_ITLB_DATA_ACCESS_REG ) ; data = ldxa ( slot , ASI_ITLB_DATA_ACCESS_REG ) ; tag = ldxa ( slot , ASI_ITLB_TAG_READ_REG ) ; intr_restore ( s ) ; if ( ( data & TD_V ) != 0 && TLB_TAR_CTX ( tag ) != TLB_CTX_KERNEL ) stxa_sync ( slot , ASI_ITLB_DATA_ACCESS_REG , 0 ) ; } } }
Flush all user mappings from the TLBs.
Flush all user mappings from the TLBs .
/*
	 * We read ASI_{D,I}TLB_DATA_ACCESS_REG twice back-to-back in order
	 * to work around errata of USIII and beyond.
	 */