sys/dev/drm/i915/i915_drv.c
/**
 * i915_driver_init_hw - setup state requiring device access
 * @dev_priv: device private
 *
 * Setup state that requires accessing the device, but doesn't require
 * exposing the driver via kernel internal or userspace interfaces.
 */
setup state requiring device access
@dev_priv: device private

Setup state that requires accessing the device, but doesn't require
exposing the driver via kernel internal or userspace interfaces.
setup state requiring device access @dev_priv : device private Setup state that requires accessing the device but doesn ' t require exposing the driver via kernel internal or userspace interfaces .
static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;
	struct i915_ggtt *ggtt = &dev_priv->ggtt;
	uint32_t aperture_size;
	int ret;
	if (i915_inject_load_failure())
		return -ENODEV;
	intel_device_info_runtime_init(dev);
	ret = i915_ggtt_init_hw(dev);
	if (ret)
		return ret;
	ret = i915_ggtt_enable_hw(dev);
	if (ret) {
		DRM_ERROR("failed to enable GGTT\n");
		goto out_ggtt;
	}
	ret = i915_kick_out_firmware_fb(dev_priv);
	if (ret) {
		DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
		goto out_ggtt;
	}
	ret = i915_kick_out_vgacon(dev_priv);
	if (ret) {
		DRM_ERROR("failed to remove conflicting VGA console\n");
		goto out_ggtt;
	}
#if 0
	pci_set_master(dev->pdev);
	if (IS_GEN2(dev)) {
		ret = dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
		if (ret) {
			DRM_ERROR("failed to set DMA mask\n");
			goto out_ggtt;
		}
	}
	if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) {
		ret = dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
		if (ret) {
			DRM_ERROR("failed to set DMA mask\n");
			goto out_ggtt;
		}
	}
#endif
	aperture_size = ggtt->mappable_end;
	ggtt->mappable =
		io_mapping_create_wc(ggtt->mappable_base,
				     aperture_size);
	if (!ggtt->mappable) {
		ret = -EIO;
		goto out_ggtt;
	}
	ggtt->mtrr = arch_phys_wc_add(ggtt->mappable_base,
					      aperture_size);
	pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY,
			   PM_QOS_DEFAULT_VALUE);
	intel_uncore_sanitize(dev_priv);
	intel_opregion_setup(dev_priv);
	i915_gem_load_init_fences(dev_priv);
#if 0
	if (!IS_I945G(dev) && !IS_I945GM(dev)) {
		if (pci_enable_msi(dev->pdev) < 0)
			DRM_DEBUG_DRIVER("can't enable MSI");
	}
#endif
	return 0;
out_ggtt:
	i915_ggtt_cleanup_hw(dev);
	return ret;
}
static int i915_driver_init_hw ( struct drm_i915_private * dev_priv ) { struct drm_device * dev = dev_priv -> dev ; struct i915_ggtt * ggtt = & dev_priv -> ggtt ; uint32_t aperture_size ; int ret ; if ( i915_inject_load_failure ( ) ) return - ENODEV ; intel_device_info_runtime_init ( dev ) ; ret = i915_ggtt_init_hw ( dev ) ; if ( ret ) return ret ; ret = i915_ggtt_enable_hw ( dev ) ; if ( ret ) { DRM_ERROR ( " \n " ) ; goto out_ggtt ; } ret = i915_kick_out_firmware_fb ( dev_priv ) ; if ( ret ) { DRM_ERROR ( " \n " ) ; goto out_ggtt ; } ret = i915_kick_out_vgacon ( dev_priv ) ; if ( ret ) { DRM_ERROR ( " \n " ) ; goto out_ggtt ; } #if 0 pci_set_master ( dev -> pdev ) ; if ( IS_GEN2 ( dev ) ) { ret = dma_set_coherent_mask ( & dev -> pdev -> dev , DMA_BIT_MASK ( 30 ) ) ; if ( ret ) { DRM_ERROR ( " \n " ) ; goto out_ggtt ; } } if ( IS_BROADWATER ( dev ) || IS_CRESTLINE ( dev ) ) { ret = dma_set_coherent_mask ( & dev -> pdev -> dev , DMA_BIT_MASK ( 32 ) ) ; if ( ret ) { DRM_ERROR ( " \n " ) ; goto out_ggtt ; } } #endif aperture_size = ggtt -> mappable_end ; ggtt -> mappable = io_mapping_create_wc ( ggtt -> mappable_base , aperture_size ) ; if ( ! ggtt -> mappable ) { ret = - EIO ; goto out_ggtt ; } ggtt -> mtrr = arch_phys_wc_add ( ggtt -> mappable_base , aperture_size ) ; pm_qos_add_request ( & dev_priv -> pm_qos , PM_QOS_CPU_DMA_LATENCY , PM_QOS_DEFAULT_VALUE ) ; intel_uncore_sanitize ( dev_priv ) ; intel_opregion_setup ( dev_priv ) ; i915_gem_load_init_fences ( dev_priv ) ; #if 0 if ( ! IS_I945G ( dev ) && ! IS_I945GM ( dev ) ) { if ( pci_enable_msi ( dev -> pdev ) < 0 ) DRM_DEBUG_DRIVER ( " " ) ; } #endif return 0 ; out_ggtt : i915_ggtt_cleanup_hw ( dev ) ; return ret ; }
i915_driver_init_hw - setup state requiring device access
 @dev_priv: device private
i915_driver_init_hw - setup state requiring device access @dev_priv : device private
/* WARNING: Apparently we must kick fbdev drivers before vgacon,
	 * otherwise the vga fbdev driver falls over. */ /* overlay on gen2 is broken and can't address above 1G */ /* 965GM sometimes incorrectly writes to hardware status page (HWS)
	 * using 32bit addressing, overwriting memory if HWS is located
	 * above 4GB.
	 *
	 * The documentation also mentions an issue with undefined
	 * behaviour if any general state is accessed within a page above 4GB,
	 * which also needs to be handled carefully.
	 */ /* On the 945G/GM, the chipset reports the MSI capability on the
	 * integrated graphics even though the support isn't actually there
	 * according to the published specs.  It doesn't appear to function
	 * correctly in testing on 945G.
	 * This may be a side effect of MSI having been made available for PEG
	 * and the registers being closely associated.
	 *
	 * According to chipset errata, on the 965GM, MSI interrupts may
	 * be lost or delayed, but we use them anyways to avoid
	 * stuck interrupts on some machines.
	 */