arch/arm/src/stm32/stm32_rtcc.c
/************************************************************************************
 * Name: up_rtcinitialize
 *
 * Description:
 *   Initialize the hardware RTC per the selected configuration.  This function is
 *   called once during the OS initialization sequence
 *
 * Input Parameters:
 *   None
 *
 * Returned Value:
 *   Zero (OK) on success; a negated errno on failure
 *
 ************************************************************************************/
up_rtcinitialize
Description:
Initialize the hardware RTC per the selected configuration.  This function is
called once during the OS initialization sequence

Input Parameters:
None

Returned Value:
Zero (OK) on success; a negated errno on failure
up_rtcinitialize Description : Initialize the hardware RTC per the selected configuration . This function is called once during the OS initialization sequence Input Parameters : None Returned Value : Zero ( OK ) on success ; a negated errno on failure
int up_rtcinitialize(void)
{
  uint32_t regval, clksrc, tr_bkp, dr_bkp;
  int ret;
  int maxretry = 10;
  int nretry = 0;
  rtc_dumpregs("On reset");
  regval = getreg32(RTC_MAGIC_REG);
  (void)stm32_pwr_enablebkp(true);
  if (regval != RTC_MAGIC)
    {
      modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST);
      modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0);
#ifdef CONFIG_RTC_HSECLOCK
      modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_HSE);
#elif defined(CONFIG_RTC_LSICLOCK)
      modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSI);
#elif defined(CONFIG_RTC_LSECLOCK)
      modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSE);
#endif
      modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_RTCEN);
    }
  else 
    {
      clksrc = getreg32(STM32_RCC_XXX);
#if defined(CONFIG_RTC_HSECLOCK)
      if ((clksrc & RCC_XXX_RTCSEL_MASK) != RCC_XXX_RTCSEL_HSE)
#elif defined(CONFIG_RTC_LSICLOCK)
      if ((clksrc & RCC_XXX_RTCSEL_MASK) != RCC_XXX_RTCSEL_LSI)
#elif defined(CONFIG_RTC_LSECLOCK)
      if ((clksrc & RCC_XXX_RTCSEL_MASK) != RCC_XXX_RTCSEL_LSE)
#endif
        {
          tr_bkp = getreg32(STM32_RTC_TR);
          dr_bkp = getreg32(STM32_RTC_DR);
          modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_YYYRST);
          modifyreg32(STM32_RCC_XXX, RCC_XXX_YYYRST, 0);
#if defined(CONFIG_RTC_HSECLOCK)
            modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_HSE);
#elif defined(CONFIG_RTC_LSICLOCK)
            modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSI);
#elif defined(CONFIG_RTC_LSECLOCK)
            modifyreg32(STM32_RCC_XXX, RCC_XXX_RTCSEL_MASK, RCC_XXX_RTCSEL_LSE);
#endif
            putreg32(tr_bkp,STM32_RTC_TR);
            putreg32(dr_bkp,STM32_RTC_DR);
            putreg32(RTC_MAGIC, RTC_MAGIC_REG);
            modifyreg32(STM32_RCC_XXX, 0, RCC_XXX_RTCEN);
        }
    }
  (void)stm32_pwr_enablebkp(false);
  do
    {
      ret = rtc_synchwait();
      switch (ret)
        {
          case OK:
            {
              rtclldbg("rtc_syncwait() okay\n");
              break;
            }
          default:
            {
              rtclldbg("rtc_syncwait() failed (%d)\n", ret);
              break;
            }
        }
    }
  while (ret != OK && ++nretry < maxretry);
  if (regval != RTC_MAGIC)
    {
      rtclldbg("Do setup\n");
      ret = rtc_setup();
      (void)stm32_pwr_enablebkp(true);
      putreg32(RTC_MAGIC, RTC_MAGIC_REG);
    }
  else
    {
      rtclldbg("Do resume\n");
      rtc_resume();
      rtc_dumpregs("Did resume");
    }
  (void)stm32_pwr_enablebkp(false);
  if (ret != OK && nretry > 0)
    {
      rtclldbg("setup/resume ran %d times and failed with %d\n",
                nretry, ret);
      return -ETIMEDOUT;
    }
#ifdef CONFIG_RTC_ALARM
#  warning "Missing EXTI setup logic"
  irq_attach(STM32_IRQ_RTC_WKUP, rtc_interrupt);
  up_enable_irq(STM32_IRQ_RTC_WKUP);
#endif
  g_rtc_enabled = true;
  rtc_dumpregs("After Initialization");
  return OK;
}
int up_rtcinitialize ( void ) { uint32_t regval , clksrc , tr_bkp , dr_bkp ; int ret ; int maxretry = 10 ; int nretry = 0 ; rtc_dumpregs ( " " ) ; regval = getreg32 ( RTC_MAGIC_REG ) ; ( void ) stm32_pwr_enablebkp ( true ) ; if ( regval != RTC_MAGIC ) { modifyreg32 ( STM32_RCC_XXX , 0 , RCC_XXX_YYYRST ) ; modifyreg32 ( STM32_RCC_XXX , RCC_XXX_YYYRST , 0 ) ; #ifdef CONFIG_RTC_HSECLOCK modifyreg32 ( STM32_RCC_XXX , RCC_XXX_RTCSEL_MASK , RCC_XXX_RTCSEL_HSE ) ; #elif defined ( CONFIG_RTC_LSICLOCK ) modifyreg32 ( STM32_RCC_XXX , RCC_XXX_RTCSEL_MASK , RCC_XXX_RTCSEL_LSI ) ; #elif defined ( CONFIG_RTC_LSECLOCK ) modifyreg32 ( STM32_RCC_XXX , RCC_XXX_RTCSEL_MASK , RCC_XXX_RTCSEL_LSE ) ; #endif modifyreg32 ( STM32_RCC_XXX , 0 , RCC_XXX_RTCEN ) ; } else { clksrc = getreg32 ( STM32_RCC_XXX ) ; #if defined ( CONFIG_RTC_HSECLOCK ) if ( ( clksrc & RCC_XXX_RTCSEL_MASK ) != RCC_XXX_RTCSEL_HSE ) #elif defined ( CONFIG_RTC_LSICLOCK ) if ( ( clksrc & RCC_XXX_RTCSEL_MASK ) != RCC_XXX_RTCSEL_LSI ) #elif defined ( CONFIG_RTC_LSECLOCK ) if ( ( clksrc & RCC_XXX_RTCSEL_MASK ) != RCC_XXX_RTCSEL_LSE ) #endif { tr_bkp = getreg32 ( STM32_RTC_TR ) ; dr_bkp = getreg32 ( STM32_RTC_DR ) ; modifyreg32 ( STM32_RCC_XXX , 0 , RCC_XXX_YYYRST ) ; modifyreg32 ( STM32_RCC_XXX , RCC_XXX_YYYRST , 0 ) ; #if defined ( CONFIG_RTC_HSECLOCK ) modifyreg32 ( STM32_RCC_XXX , RCC_XXX_RTCSEL_MASK , RCC_XXX_RTCSEL_HSE ) ; #elif defined ( CONFIG_RTC_LSICLOCK ) modifyreg32 ( STM32_RCC_XXX , RCC_XXX_RTCSEL_MASK , RCC_XXX_RTCSEL_LSI ) ; #elif defined ( CONFIG_RTC_LSECLOCK ) modifyreg32 ( STM32_RCC_XXX , RCC_XXX_RTCSEL_MASK , RCC_XXX_RTCSEL_LSE ) ; #endif putreg32 ( tr_bkp , STM32_RTC_TR ) ; putreg32 ( dr_bkp , STM32_RTC_DR ) ; putreg32 ( RTC_MAGIC , RTC_MAGIC_REG ) ; modifyreg32 ( STM32_RCC_XXX , 0 , RCC_XXX_RTCEN ) ; } } ( void ) stm32_pwr_enablebkp ( false ) ; do { ret = rtc_synchwait ( ) ; switch ( ret ) { case OK : { rtclldbg ( " \n " ) ; break ; } default : { rtclldbg ( " \n " , ret ) ; break ; } } } while ( ret != OK && ++ nretry < maxretry ) ; if ( regval != RTC_MAGIC ) { rtclldbg ( " \n " ) ; ret = rtc_setup ( ) ; ( void ) stm32_pwr_enablebkp ( true ) ; putreg32 ( RTC_MAGIC , RTC_MAGIC_REG ) ; } else { rtclldbg ( " \n " ) ; rtc_resume ( ) ; rtc_dumpregs ( " " ) ; } ( void ) stm32_pwr_enablebkp ( false ) ; if ( ret != OK && nretry > 0 ) { rtclldbg ( " \n " , nretry , ret ) ; return - ETIMEDOUT ; } #ifdef CONFIG_RTC_ALARM #  warning  "Missing EXTI setup logic" irq_attach ( STM32_IRQ_RTC_WKUP , rtc_interrupt ) ; up_enable_irq ( STM32_IRQ_RTC_WKUP ) ; #endif g_rtc_enabled = true ; rtc_dumpregs ( " " ) ; return OK ; }
Name: up_rtcinitialize
 Description:
   Initialize the hardware RTC per the selected configuration.
Name : up_rtcinitialize Description : Initialize the hardware RTC per the selected configuration .
/* Clocking for the PWR block must be provided.  However, this is done
   * unconditionally in stm32f40xxx_rcc.c on power up.  This done unconditionally
   * because the PWR block is also needed to set the internal voltage regulator for
   * maximum performance.
   */ /* Select the clock source */ /* Save the token before losing it when resetting */ /* We might be changing RTCSEL - to ensure such changes work, we must reset the
       * backup domain (having backed up the RTC_MAGIC token)
       */ /* Some boards do not have the external 32khz oscillator installed, for those
       * boards we must fallback to the crummy internal RC clock or the external high
       * rate clock
       */ /* Use the HSE clock as the input to the RTC block */ /* Use the LSI clock as the input to the RTC block */ /* Use the LSE clock as the input to the RTC block */ /* Enable the RTC Clock by setting the RTCEN bit in the RCC register */ /* The RTC is already in use: check if the clock source is changed */ /* Change to the new clock as the input to the RTC block */ /* Remember that the RTC is initialized */ /* Enable the RTC Clock by setting the RTCEN bit in the RCC register */ /* Loop, attempting to initialize/resume the RTC.  This loop is necessary
   * because it seems that occasionally it takes longer to initialize the RTC
   * (the actual failure is in rtc_synchwait()).
   */ /* Wait for the RTC Time and Date registers to be synchronized with RTC APB
       * clock.
       */ /* Check that rtc_syncwait() returned successfully */ /* Check if the one-time initialization of the RTC has already been
   * performed. We can determine this by checking if the magic number
   * has been writing to to back-up date register DR0.
   */ /* Perform the one-time setup of the LSE clocking to the RTC */ /* Enable write access to the backup domain (RTC registers, RTC
       * backup data registers and backup SRAM).
       */ /* Remember that the RTC is initialized */ /* RTC already set-up, just resume normal operation */ /* Disable write access to the backup domain (RTC registers, RTC backup
   * data registers and backup SRAM).
   */ /* Configure RTC interrupt to catch alarm interrupts. All RTC interrupts are
   * connected to the EXTI controller.  To enable the RTC Alarm interrupt, the
   * following sequence is required:
   *
   * 1. Configure and enable the EXTI Line 17 in interrupt mode and select the
   *    rising edge sensitivity.
   * 2. Configure and enable the RTC_Alarm IRQ channel in the NVIC.
   * 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B).
   */ /* Then attach the ALARM interrupt handler */