kernels/linux-2.4.0/arch/mips/mm/r4xx0.c
/*
 * Writeback and invalidate the primary cache dcache before DMA.
 *
 * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
 * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
 * operate correctly if the internal data cache refill buffer is empty.  These
 * CACHE instructions should be separated from any potential data cache miss
 * by a load instruction to an uncached address to empty the response buffer."
 * (Revision 2.0 device errata from IDT available on http://www.idt.com/
 * in .pdf format.)
 */
Writeback and invalidate the primary cache dcache before DMA.
R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
operate correctly if the internal data cache refill buffer is empty.
Writeback and invalidate the primary cache dcache before DMA . R4600 v2 . 0 bug : " The CACHE instructions Hit_Writeback_Inv_D Hit_Writeback_D Hit_Invalidate_D and Create_Dirty_Exclusive_D will only operate correctly if the internal data cache refill buffer is empty .
static void
r4k_dma_cache_wback_inv_pc(unsigned long addr, unsigned long size)
{
	unsigned long end, a;
	unsigned int flags;
	if (size >= dcache_size) {
		flush_cache_all();
	} else {
		save_and_cli(flags);
		*(volatile unsigned long *)KSEG1;
		a = addr & ~(dc_lsize - 1);
		end = (addr + size) & ~(dc_lsize - 1);
		while (1) {
			flush_dcache_line(a); 
			if (a == end) break;
			a += dc_lsize;
		}
		restore_flags(flags);
	}
	bcops->bc_wback_inv(addr, size);
}
static void r4k_dma_cache_wback_inv_pc ( unsigned long addr , unsigned long size ) { unsigned long end , a ; unsigned int flags ; if ( size >= dcache_size ) { flush_cache_all ( ) ; } else { save_and_cli ( flags ) ; * ( volatile unsigned long * ) KSEG1 ; a = addr & ~ ( dc_lsize - 1 ) ; end = ( addr + size ) & ~ ( dc_lsize - 1 ) ; while ( 1 ) { flush_dcache_line ( a ) ; if ( a == end ) break ; a += dc_lsize ; } restore_flags ( flags ) ; } bcops -> bc_wback_inv ( addr , size ) ; }
Writeback and invalidate the primary cache dcache before DMA.
Writeback and invalidate the primary cache dcache before DMA .
/* Workaround for R4600 bug.  See comment above. */ /* Hit_Writeback_Inv_D */