kernels/linux-2.4.0/drivers/net/dmfe.c
/* Initilize DM910X board
   Reset DM910X board
   Initilize TX/Rx descriptor chain structure
   Send the set-up frame
   Enable Tx/Rx machine
 */
Initilize DM910X board
Reset DM910X board
Initilize TX/Rx descriptor chain structure
Send the set-up frame
Enable Tx/Rx machine
Initilize DM910X board Reset DM910X board Initilize TX / Rx descriptor chain structure Send the set - up frame Enable Tx / Rx machine
static void dmfe_init_dm910x(struct net_device *dev)
{
	struct dmfe_board_info *db = dev->priv;
	u32 ioaddr = db->ioaddr;
	DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
	outl(DM910X_RESET, ioaddr + DCR0);	
	DELAY_5US;
	outl(db->cr0_data, ioaddr + DCR0);
	outl(0x180, ioaddr + DCR12);	
	outl(0x80, ioaddr + DCR12);	
	outl(0x0, ioaddr + DCR12);	
	db->phy_addr = 1;
	db->media_mode = dmfe_media_mode;
	if (db->media_mode & DMFE_AUTO)
		dmfe_sense_speed(db);
	else
		db->op_mode = db->media_mode;
	dmfe_process_mode(db);
	dmfe_descriptor_init(db, ioaddr);
	update_cr6(db->cr6_data, ioaddr);
	if (db->chip_id == PCI_DM9132_ID)
		dm9132_id_table(dev, dev->mc_count);	
	else
		send_filter_frame(dev, dev->mc_count);	
	outl(0xffffffff, ioaddr + DCR5);	
	db->cr7_data = CR7_DEFAULT;
	outl(db->cr7_data, ioaddr + DCR7);
	db->cr15_data = CR15_DEFAULT;
	outl(db->cr15_data, ioaddr + DCR15);
	db->cr6_data |= CR6_RXSC | CR6_TXSC;
	update_cr6(db->cr6_data, ioaddr);
}
static void dmfe_init_dm910x ( struct net_device * dev ) { struct dmfe_board_info * db = dev -> priv ; u32 ioaddr = db -> ioaddr ; DMFE_DBUG ( 0 , " " , 0 ) ; outl ( DM910X_RESET , ioaddr + DCR0 ) ; DELAY_5US ; outl ( db -> cr0_data , ioaddr + DCR0 ) ; outl ( 0x180 , ioaddr + DCR12 ) ; outl ( 0x80 , ioaddr + DCR12 ) ; outl ( 0x0 , ioaddr + DCR12 ) ; db -> phy_addr = 1 ; db -> media_mode = dmfe_media_mode ; if ( db -> media_mode & DMFE_AUTO ) dmfe_sense_speed ( db ) ; else db -> op_mode = db -> media_mode ; dmfe_process_mode ( db ) ; dmfe_descriptor_init ( db , ioaddr ) ; update_cr6 ( db -> cr6_data , ioaddr ) ; if ( db -> chip_id == PCI_DM9132_ID ) dm9132_id_table ( dev , dev -> mc_count ) ; else send_filter_frame ( dev , dev -> mc_count ) ; outl ( 0xffffffff , ioaddr + DCR5 ) ; db -> cr7_data = CR7_DEFAULT ; outl ( db -> cr7_data , ioaddr + DCR7 ) ; db -> cr15_data = CR15_DEFAULT ; outl ( db -> cr15_data , ioaddr + DCR15 ) ; db -> cr6_data |= CR6_RXSC | CR6_TXSC ; update_cr6 ( db -> cr6_data , ioaddr ) ; }
Initilize DM910X board
Reset DM910X board
Initilize TX/Rx descriptor chain structure
Send the set-up frame
Enable Tx/Rx machine
Initilize DM910X board Reset DM910X board Initilize TX / Rx descriptor chain structure Send the set - up frame Enable Tx / Rx machine
/* Reset DM910x board : need 32 PCI clock to complete */ /* RESET MAC */ /* Let bit 7 output port */ /* RESET DM9102 phyxcer */ /* Clear RESET signal */ /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */ /* Media Mode Check */ /* Initiliaze Transmit/Receive decriptor and CR3/4 */ /* Init CR6 to program DM910x operation */ /* Send setup frame */ /* DM9132 */ /* DM9102/DM9102A */ /* Init CR5/CR7, interrupt active bit */ /* clear all CR5 status */ /* Init CR15, Tx jabber and Rx watchdog timer */ /* Enable DM910X Tx/Rx function */