Platform/ECM3532/M3/hw/csp/ecm3532/m3/csp/src/eta_csp_spi.c
/***************************************************************************/
/**
 *
 *  EtaCspSpiIntGet - Get interrupts enable bits
 *
 *  @param iNum the SPI number.
 *  @return iSpiInt interrupt structure.
 *
 ******************************************************************************/
Get interrupts enable bits
@param iNum the SPI number.
@return iSpiInt interrupt structure.
Get interrupts enable bits @param iNum the SPI number . @return iSpiInt interrupt structure .
tSpiInt EtaCspSpiIntGet(tSpiNum iNum)
{
    reg_spi_int_en_t reg_spi_int_en;
    reg_spi_int_en.V = MEMIO16(REG_SPI_INT_EN_ADDR(iNum) );
    tSpiInt iSpiIntStatus = {
        .bCmdIsDone      = reg_spi_int_en.BF.CMD_IS_DONE_EN0,
        .bXmitComplete   = reg_spi_int_en.BF.XMIT_COMPLETE_EN0,
        .bRxFifoHitLevel = reg_spi_int_en.BF.RX_FIFO_HIT_LEVEL_EN0,
        .bTxFifoHitLevel = reg_spi_int_en.BF.TXFIFO_HAS_LEVEL_SPACE_EN0,
        .bRxFifoHasData  = reg_spi_int_en.BF.RX_DATA_EN0,
        .bTxFifoHasSpace = reg_spi_int_en.BF.TX_DATA_EN0
    };
    return iSpiIntStatus;
}
tSpiInt EtaCspSpiIntGet ( tSpiNum iNum ) { reg_spi_int_en_t reg_spi_int_en ; reg_spi_int_en . V = MEMIO16 ( REG_SPI_INT_EN_ADDR ( iNum ) ) ; tSpiInt iSpiIntStatus = { . bCmdIsDone = reg_spi_int_en . BF . CMD_IS_DONE_EN0 , . bXmitComplete = reg_spi_int_en . BF . XMIT_COMPLETE_EN0 , . bRxFifoHitLevel = reg_spi_int_en . BF . RX_FIFO_HIT_LEVEL_EN0 , . bTxFifoHitLevel = reg_spi_int_en . BF . TXFIFO_HAS_LEVEL_SPACE_EN0 , . bRxFifoHasData = reg_spi_int_en . BF . RX_DATA_EN0 , . bTxFifoHasSpace = reg_spi_int_en . BF . TX_DATA_EN0 } ; return iSpiIntStatus ; }
EtaCspSpiIntGet - Get interrupts enable bits
  @param iNum the SPI number.
EtaCspSpiIntGet - Get interrupts enable bits @param iNum the SPI number .