FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/platform/mpfs_hal/common/nwc/mss_pll.c
/***************************************************************************/
/**
 * mss_mux_pre_mss_pll_config()
 *
 * Feed through required reference clks to PLL, configure PLL and wait for lock
 ******************************************************************************/
mss_mux_pre_mss_pll_config()
Feed through required reference clks to PLL, configure PLL and wait for lock
mss_mux_pre_mss_pll_config () Feed through required reference clks to PLL configure PLL and wait for lock
static void mss_mux_pre_mss_pll_config(void)
{
    MSS_SCB_CFM_MSS_MUX->PLL_CKMUX = LIBERO_SETTING_MSS_PLL_CKMUX;
    MSS_SCB_CFM_SGMII_MUX->CLK_XCVR         = LIBERO_SETTING_SGMII_CLK_XCVR;
    MSS_SCB_CFM_MSS_MUX->BCLKMUX        =   LIBERO_SETTING_MSS_BCLKMUX;
    MSS_SCB_CFM_MSS_MUX->FMETER_ADDR    =   LIBERO_SETTING_MSS_FMETER_ADDR;
    MSS_SCB_CFM_MSS_MUX->FMETER_DATAW   =   LIBERO_SETTING_MSS_FMETER_DATAW;
    MSS_SCB_CFM_MSS_MUX->FMETER_DATAR   =   LIBERO_SETTING_MSS_FMETER_DATAR;
    volatile uint32_t i;
    for(i = 0U; i < 400U; i++)
    {
        i++;
    }
}
static void mss_mux_pre_mss_pll_config ( void ) { MSS_SCB_CFM_MSS_MUX -> PLL_CKMUX = LIBERO_SETTING_MSS_PLL_CKMUX ; MSS_SCB_CFM_SGMII_MUX -> CLK_XCVR = LIBERO_SETTING_SGMII_CLK_XCVR ; MSS_SCB_CFM_MSS_MUX -> BCLKMUX = LIBERO_SETTING_MSS_BCLKMUX ; MSS_SCB_CFM_MSS_MUX -> FMETER_ADDR = LIBERO_SETTING_MSS_FMETER_ADDR ; MSS_SCB_CFM_MSS_MUX -> FMETER_DATAW = LIBERO_SETTING_MSS_FMETER_DATAW ; MSS_SCB_CFM_MSS_MUX -> FMETER_DATAR = LIBERO_SETTING_MSS_FMETER_DATAR ; volatile uint32_t i ; for ( i = 0U ; i < 400U ; i ++ ) { i ++ ; } }
mss_mux_pre_mss_pll_config()
 Feed through required reference clks to PLL, configure PLL and wait for lock
mss_mux_pre_mss_pll_config () Feed through required reference clks to PLL configure PLL and wait for lock
/*
     * PLL RF clk mux selections
     *  [31:15] Reserved
     *  [14:10] pll1_fdr_sel
     *  [9:8]   pll1_rfclk1_sel
     *  [7:6]   pll1_rfclk0_sel
     *  [5:4]   pll0_rfclk1_sel
     *  [3:2]   pll0_rfclk0_sel
     *  [1:0]   clk_in_mac_tsu_sel
     *
     *  Each mux uses 2 configuration bits. These are decoded as follows:
     *  00  vss
     *  01  refclk_p,refclk_n
     *  10  scb_clk
     *  10  serdes_refclk_crn_mss<0>, serdes_refclk_crn_mss<1>
     *
     *  e.g.
     *  PLL_CKMUX = 0x00000154
     *    pll0_rfclk0_sel = 1 => refclk_p is used for pll0 ref0 and refclk_n is
     *    fed to MSS PLL ref1
     */ /* CFM_MSS 0x3E002000   - 0x08 */ /*
     * MSS Clock mux selections
     *  [31:5]  Reserved
     *  [4]     clk_standby_sel
     *  [3:2]   mssclk_mux_md
     *  step 7: 7)  MSS Processor writes mssclk_mux_sel_int<0>=1 to select the
     *  MSS PLL clock.
     *  [1:0]   mssclk_mux_sel        MSS glitchless mux select
     *                                      00 - msspll_fdr_0=clk_standby
     *                                           msspll_fdr_1=clk_standby
     *                                      01 - msspll_fdr_0=pllout0
     *                                           msspll_fdr_1=clk_standby
     *                                      10 - msspll_fdr_0=clk_standby
     *                                           msspll_fdr_1=pllout1
     *                                      11 - msspll_fdr_0=pllout0
     *                                           msspll_fdr_1=pllout1
     *
     *
     */ /*
     * We will not set as already set to 0, we feed through after we have setup
     * clock
     * MSS_SCB_CFM_MSS_MUX->MSSCLKMUX           = LIBERO_SETTING_MSS_MSSCLKMUX;
     */ /*
     * Clock_Receiver
     *  [13]    en_rdiff
     *  [12]    clkbuf_en_pullup
     *  [11:10] en_rxmode_n
     *  [9:8]   en_term_n
     *  [7]     en_ins_hyst_n
     *  [6]     en_udrive_n
     *  [5:4]   en_rxmode_p
     *  [3:2]   en_term_p
     *  [1]     en_ins_hyst_p
     *  [0]     en_udrive_p
     */ /*
     * 29:25    bclk5_sel
     * 24:20    bclk4_sel
     * 19:15    bclk3_sel
     * 14:10    bclk2_sel
     * 9:5  bclk1_sel
     * 4:0  bclk0_sel
     *
     * From SAC spec:
     * Table 9 1: Each gbim bank clock mux programming in MSS corner
     * The DDRPHY bank clocks bclk_horz<5:0> and bclk_vert<5:0> are driven
     * from mux's gbim<5:0> in the MSS corner. Each mux uses 5 configuration
     * bits.
     *
     * BCLK mux selections
     *  bclk0_sel=0x8 (pll0_out_1k<2> selected)
     *  bclk1_sel=0x10 (pll0_out_1k<3> selected)
     *  bclk2_sel=0x1 (vss selected)
     *  bclk3_sel=0x1 (vss selected)
     *  bclk4_sel=0x1 (vss selected)
     *  bclk5_sel=0x1 (vss selected)
     *
     */ /*  MSS_SCB_CFM_MSS_MUX->SPARE0         =   BCLKMUX_USER_CONFIG;       */ /*
     *
     */