FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/ST_Code/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_utils.c
/**
  * @brief  This function configures system clock at maximum frequency with HSI as clock source of the PLL
  * @note   The application need to ensure that PLL is disabled.
  * @note   Function is based on the following formula:
  *         - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
  *         - PLLM: ensure that the VCO input frequency ranges from 1 to 16 MHz (PLLVCO_input = HSI frequency / PLLM)
  *         - PLLN: ensure that the VCO output frequency is between 150 and 836 MHz or 128 to 560 MHz(*) (PLLVCO_output = PLLVCO_input * PLLN)
  *         - PLLP: ensure that max frequency at 400000000 Hz or 280000000 Hz is reach (PLLVCO_output / PLLP)
  * @param  UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains
  *                             the configuration information for the PLL.
  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
  *                             the configuration information for the BUS prescalers.
  * @retval An ErrorStatus enumeration value:
  *          - SUCCESS: Max frequency configuration done
  *          - ERROR: Max frequency configuration not done
  *
  * (*) : For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.
  *
  */
@brief  This function configures system clock at maximum frequency with HSI as clock source of the PLL
@note   The application need to ensure that PLL is disabled.

(*) : For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.
@brief This function configures system clock at maximum frequency with HSI as clock source of the PLL @note The application need to ensure that PLL is disabled . ( * ) : For stm32h7a3xx stm32h7b3xx and stm32h7b0xx family lines .
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
  ErrorStatus status;
#ifdef  USE_FULL_ASSERT
  uint32_t vcoinput_freq, vcooutput_freq;
#endif
  uint32_t pllfreq, hsi_clk;
  assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM));
  assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN));
  assert_param(IS_LL_UTILS_PLLP_VALUE(UTILS_PLLInitStruct->PLLP));
  assert_param(IS_LL_UTILS_FRACN_VALUE(UTILS_PLLInitStruct->FRACN));
  hsi_clk = (HSI_VALUE >> (LL_RCC_HSI_GetDivider() >> RCC_CR_HSIDIV_Pos));
#ifdef  USE_FULL_ASSERT
  vcoinput_freq = hsi_clk / UTILS_PLLInitStruct->PLLM;
#endif
  assert_param(IS_LL_UTILS_PLLVCO_INPUT(vcoinput_freq, UTILS_PLLInitStruct->VCO_Input));
#ifdef  USE_FULL_ASSERT
  vcooutput_freq = LL_RCC_CalcPLLClockFreq(hsi_clk, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, UTILS_PLLInitStruct->FRACN, 1UL);
#endif
  assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(vcooutput_freq, UTILS_PLLInitStruct->VCO_Output));
  assert_param(IS_LL_UTILS_CHECK_VCO_RANGES(UTILS_PLLInitStruct->VCO_Input, UTILS_PLLInitStruct->VCO_Output));
  if(UTILS_IsPLLsReady() == SUCCESS)
  {
    pllfreq = UTILS_GetPLLOutputFrequency(hsi_clk, UTILS_PLLInitStruct);
    if(LL_RCC_HSI_IsReady() != 1U)
    {
      LL_RCC_HSI_Enable();
      while (LL_RCC_HSI_IsReady() != 1U)
      {
      }
    }
    LL_RCC_PLL1P_Enable();
    LL_RCC_PLL1FRACN_Enable();
    LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSI);
    LL_RCC_PLL1_SetVCOInputRange(UTILS_PLLInitStruct->VCO_Input);
    LL_RCC_PLL1_SetVCOOutputRange(UTILS_PLLInitStruct->VCO_Output);
    LL_RCC_PLL1_SetM(UTILS_PLLInitStruct->PLLM);
    LL_RCC_PLL1_SetN(UTILS_PLLInitStruct->PLLN);
    LL_RCC_PLL1_SetP(UTILS_PLLInitStruct->PLLP);
    LL_RCC_PLL1_SetFRACN(UTILS_PLLInitStruct->FRACN);
    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
  }
  else
  {
    status = ERROR;
  }
  return status;
}
ErrorStatus LL_PLL_ConfigSystemClock_HSI ( LL_UTILS_PLLInitTypeDef * UTILS_PLLInitStruct , LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct ) { ErrorStatus status ; #ifdef USE_FULL_ASSERT uint32_t vcoinput_freq , vcooutput_freq ; #endif uint32_t pllfreq , hsi_clk ; assert_param ( IS_LL_UTILS_PLLM_VALUE ( UTILS_PLLInitStruct -> PLLM ) ) ; assert_param ( IS_LL_UTILS_PLLN_VALUE ( UTILS_PLLInitStruct -> PLLN ) ) ; assert_param ( IS_LL_UTILS_PLLP_VALUE ( UTILS_PLLInitStruct -> PLLP ) ) ; assert_param ( IS_LL_UTILS_FRACN_VALUE ( UTILS_PLLInitStruct -> FRACN ) ) ; hsi_clk = ( HSI_VALUE >> ( LL_RCC_HSI_GetDivider ( ) >> RCC_CR_HSIDIV_Pos ) ) ; #ifdef USE_FULL_ASSERT vcoinput_freq = hsi_clk / UTILS_PLLInitStruct -> PLLM ; #endif assert_param ( IS_LL_UTILS_PLLVCO_INPUT ( vcoinput_freq , UTILS_PLLInitStruct -> VCO_Input ) ) ; #ifdef USE_FULL_ASSERT vcooutput_freq = LL_RCC_CalcPLLClockFreq ( hsi_clk , UTILS_PLLInitStruct -> PLLM , UTILS_PLLInitStruct -> PLLN , UTILS_PLLInitStruct -> FRACN , 1UL ) ; #endif assert_param ( IS_LL_UTILS_PLLVCO_OUTPUT ( vcooutput_freq , UTILS_PLLInitStruct -> VCO_Output ) ) ; assert_param ( IS_LL_UTILS_CHECK_VCO_RANGES ( UTILS_PLLInitStruct -> VCO_Input , UTILS_PLLInitStruct -> VCO_Output ) ) ; if ( UTILS_IsPLLsReady ( ) == SUCCESS ) { pllfreq = UTILS_GetPLLOutputFrequency ( hsi_clk , UTILS_PLLInitStruct ) ; if ( LL_RCC_HSI_IsReady ( ) != 1U ) { LL_RCC_HSI_Enable ( ) ; while ( LL_RCC_HSI_IsReady ( ) != 1U ) { } } LL_RCC_PLL1P_Enable ( ) ; LL_RCC_PLL1FRACN_Enable ( ) ; LL_RCC_PLL_SetSource ( LL_RCC_PLLSOURCE_HSI ) ; LL_RCC_PLL1_SetVCOInputRange ( UTILS_PLLInitStruct -> VCO_Input ) ; LL_RCC_PLL1_SetVCOOutputRange ( UTILS_PLLInitStruct -> VCO_Output ) ; LL_RCC_PLL1_SetM ( UTILS_PLLInitStruct -> PLLM ) ; LL_RCC_PLL1_SetN ( UTILS_PLLInitStruct -> PLLN ) ; LL_RCC_PLL1_SetP ( UTILS_PLLInitStruct -> PLLP ) ; LL_RCC_PLL1_SetFRACN ( UTILS_PLLInitStruct -> FRACN ) ; status = UTILS_EnablePLLAndSwitchSystem ( pllfreq , UTILS_ClkInitStruct ) ; } else { status = ERROR ; } return status ; }
@brief  This function configures system clock at maximum frequency with HSI as clock source of the PLL
 @note   The application need to ensure that PLL is disabled.
@brief This function configures system clock at maximum frequency with HSI as clock source of the PLL @note The application need to ensure that PLL is disabled .
/* Check the parameters */ /* Check VCO Input frequency */ /* Check VCO Output frequency */ /* Check VCO Input ranges */ /* Check if one of the PLL is enabled */ /* Calculate the new PLL output frequency */ /* Enable HSI if not enabled */ /* Wait for HSI ready */ /* Configure PLL */ /* Enable PLL and switch system clock to PLL */ /* Current PLL configuration cannot be modified */