linux/drivers/clocksource/riscv_timer.c
/*
 * All RISC-V systems have a timer attached to every hart.  These timers can be
 * read by the 'rdcycle' pseudo instruction, and can use the SBI to setup
 * events.  In order to abstract the architecture-specific timer reading and
 * setting functions away from the clock event insertion code, we provide
 * function pointers to the clockevent subsystem that perform two basic
 * operations: rdtime() reads the timer on the current CPU, and
 * next_event(delta) sets the next timer event to 'delta' cycles in the future.
 * As the timers are inherently a per-cpu resource, these callbacks perform
 * operations on the current hart.  There is guaranteed to be exactly one timer
 * per hart on all RISC-V systems.
 */
All RISC-V systems have a timer attached to every hart.  These timers can be
read by the 'rdcycle' pseudo instruction, and can use the SBI to setup
events.  In order to abstract the architecture-specific timer reading and
setting functions away from the clock event insertion code, we provide
function pointers to the clockevent subsystem that perform two basic
operations: rdtime() reads the timer on the current CPU, and
next_event(delta) sets the next timer event to 'delta' cycles in the future.
As the timers are inherently a per-cpu resource, these callbacks perform
operations on the current hart.  There is guaranteed to be exactly one timer
per hart on all RISC-V systems.
All RISC - V systems have a timer attached to every hart . These timers can be read by the ' rdcycle ' pseudo instruction and can use the SBI to setup events . In order to abstract the architecture - specific timer reading and setting functions away from the clock event insertion code we provide function pointers to the clockevent subsystem that perform two basic operations : rdtime () reads the timer on the current CPU and next_event ( delta ) sets the next timer event to ' delta ' cycles in the future . As the timers are inherently a per - cpu resource these callbacks perform operations on the current hart . There is guaranteed to be exactly one timer per hart on all RISC - V systems .
static int riscv_clock_next_event(unsigned long delta,
		struct clock_event_device *ce)
{
	csr_set(sie, SIE_STIE);
	sbi_set_timer(get_cycles64() + delta);
	return 0;
}
static int riscv_clock_next_event ( unsigned long delta , struct clock_event_device * ce ) { csr_set ( sie , SIE_STIE ) ; sbi_set_timer ( get_cycles64 ( ) + delta ) ; return 0 ; }
All RISC-V systems have a timer attached to every hart.
All RISC - V systems have a timer attached to every hart .