FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/platform/mpfs_hal/common/nwc/mss_pll.c
/***************************************************************************/
/**
 * mss_mux_post_mss_pll_config(void)
 *
 * Once MSS locked, feed through to MSS
 * We must run this code from RAM, as we need to modify the clock of the eNVM
 * The first thing we do is change the eNVM clock, to prevent L1 cache accessing
 * eNVM as it will do as we approach the return instruction
 * The mb() makes sure order of processing is not changed by the compiler
 ******************************************************************************/
mss_mux_post_mss_pll_config(void)
Once MSS locked, feed through to MSS
We must run this code from RAM, as we need to modify the clock of the eNVM
The first thing we do is change the eNVM clock, to prevent L1 cache accessing
eNVM as it will do as we approach the return instruction
The mb() makes sure order of processing is not changed by the compiler
mss_mux_post_mss_pll_config ( void ) Once MSS locked feed through to MSS We must run this code from RAM as we need to modify the clock of the eNVM The first thing we do is change the eNVM clock to prevent L1 cache accessing eNVM as it will do as we approach the return instruction The mb () makes sure order of processing is not changed by the compiler
__attribute__((section(".ram_codetext"))) \
        static void mss_mux_post_mss_pll_config(void)
{
    SYSREG->ENVM_CR = LIBERO_SETTING_MSS_ENVM_CR;
    mb();  
    volatile uint32_t wait_for_true = 0U;
    while ((SYSREG->ENVM_CR & ENVM_CR_CLOCK_OKAY_MASK) !=\
            ENVM_CR_CLOCK_OKAY_MASK)
    {
#ifdef RENODE_DEBUG
        break;
#endif
        wait_for_true++; 
    }
  SYSREG->CLOCK_CONFIG_CR = LIBERO_SETTING_MSS_CLOCK_CONFIG_CR;
    MSS_SCB_CFM_MSS_MUX->MSSCLKMUX   = LIBERO_SETTING_MSS_MSSCLKMUX;
    set_RTC_divisor();
}
__attribute__ ( ( section ( " " ) ) ) static void mss_mux_post_mss_pll_config ( void ) { SYSREG -> ENVM_CR = LIBERO_SETTING_MSS_ENVM_CR ; mb ( ) ; volatile uint32_t wait_for_true = 0U ; while ( ( SYSREG -> ENVM_CR & ENVM_CR_CLOCK_OKAY_MASK ) != ENVM_CR_CLOCK_OKAY_MASK ) { #ifdef RENODE_DEBUG break ; #endif wait_for_true ++ ; } SYSREG -> CLOCK_CONFIG_CR = LIBERO_SETTING_MSS_CLOCK_CONFIG_CR ; MSS_SCB_CFM_MSS_MUX -> MSSCLKMUX = LIBERO_SETTING_MSS_MSSCLKMUX ; set_RTC_divisor ( ) ; }
mss_mux_post_mss_pll_config(void)
 Once MSS locked, feed through to MSS
 We must run this code from RAM, as we need to modify the clock of the eNVM
 The first thing we do is change the eNVM clock, to prevent L1 cache accessing
 eNVM as it will do as we approach the return instruction
 The mb() makes sure order of processing is not changed by the compiler
mss_mux_post_mss_pll_config ( void ) Once MSS locked feed through to MSS We must run this code from RAM as we need to modify the clock of the eNVM The first thing we do is change the eNVM clock to prevent L1 cache accessing eNVM as it will do as we approach the return instruction The mb () makes sure order of processing is not changed by the compiler
/*
    * Modify the eNVM clock, so it now matches new MSS clock
    *
    * [5:0]
    * Sets the number of AHB cycles used to generate the PNVM clock,.
    * Clock period = (Value+1) * (1000/AHBFREQMHZ)
    * Value must be 1 to 63 (0 defaults to 15)
    * e.g.
    * 7 will generate a 40ns period 25MHz clock if the AHB clock is 200MHz
    * 11 will generate a 40ns period 25MHz clock if the AHB clock is 250MHz
    * 15 will generate a 40ns period 25MHz clock if the AHB clock is 400MHz
    *
    */ /* make sure we change clock in eNVM first so ready by the time we
             leave */ /*
    * When you're changing the eNVM clock frequency, there is a bit
    * (ENVM_CR_clock_okay) in the eNVM_CR which can be polled to check that
    * the frequency change has happened before bumping up the AHB frequency.
    */ /* need something here to stop debugger freezing */ /*
    * Change the MSS clock as required.
    *
    * CLOCK_CONFIG_CR
    * [5:0]
    * Sets the master synchronous clock divider
    * bits [1:0] CPU clock divider
    * bits [3:2] AXI clock divider
    * bits [5:4] AHB/APB clock divider
    * 00=/1 01=/2 10=/4 11=/8 (AHB/APB divider may not be set to /1)
    * Reset = 0x3F
    *
    * SYSREG->CLOCK_CONFIG_CR = (0x0U<<0U) | (0x1U<<2U) | (0x2U<<4U);
    * MSS clk= 80Mhz, implies CPU = 80Mhz, AXI = 40Mhz, AHB/APB = 20Mhz
    * Until we switch in MSS PLL clock (MSS_SCB_CFM_MSS_MUX->MSSCLKMUX = 0x01)
    * e.g. If MSS clk 800Mhz
    * MSS clk= 800Mhz, implies CPU = 800Mhz, AXI = 400Mhz, AHB/APB = 200Mhz
   */ /*
    * Feed clock from MSS PLL to MSS, using glitch-less mux
    *
    * MSS Clock mux selections
    *   [31:5]  Reserved
    *   [4]    clk_standby_sel
    *   [3:2]  mssclk_mux_md
    *   step 7: 7)  MSS Processor writes mssclk_mux_sel_int<0>=1 to select the
    *   MSS PLL clock.
    *   [1:0]  mssclk_mux_sel        MSS glitchless mux select
    *                    00 - msspll_fdr_0=clk_standby
    *                          msspll_fdr_1=clk_standby
    *                    01 - msspll_fdr_0=pllout0
    *                          msspll_fdr_1=clk_standby
    *                    10 - msspll_fdr_0=clk_standby
    *                           msspll_fdr_1=pllout1
    *                    11 - msspll_fdr_0=pllout0
    *                          msspll_fdr_1=pllout1
    *
    *
    */ /*
    * Change the RTC clock divisor, so RTC clock is 1MHz
    */