KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr.c
/**
  * @brief  Enter the system to STANDBY mode.
  * @note   The system enters Standby mode only when the D1, D2 and D3 domains are in DStandby.
  * @note   When the System exit STANDBY mode by issuing an interrupt or a wakeup event,
  *         the HSI RC oscillator is selected as system clock.
  * @retval None.
  */
@brief  Enter the system to STANDBY mode.
@note   The system enters Standby mode only when the D1, D2 and D3 domains are in DStandby.
@note   When the System exit STANDBY mode by issuing an interrupt or a wakeup event,
the HSI RC oscillator is selected as system clock.
@retval None.
@brief Enter the system to STANDBY mode . @note The system enters Standby mode only when the D1 D2 and D3 domains are in DStandby . @note When the System exit STANDBY mode by issuing an interrupt or a wakeup event the HSI RC oscillator is selected as system clock . @retval None .
void HAL_PWR_EnterSTANDBYMode(void)
{
  SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1);
  SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2);
  SET_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3);
  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
#if defined ( __CC_ARM)
  __force_stores();
#endif
  __WFI();
}
void HAL_PWR_EnterSTANDBYMode ( void ) { SET_BIT ( PWR -> CPUCR , PWR_CPUCR_PDDS_D1 ) ; SET_BIT ( PWR -> CPUCR , PWR_CPUCR_PDDS_D2 ) ; SET_BIT ( PWR -> CPUCR , PWR_CPUCR_PDDS_D3 ) ; SCB -> SCR |= SCB_SCR_SLEEPDEEP_Msk ; #if defined ( __CC_ARM ) __force_stores ( ) ; #endif __WFI ( ) ; }
@brief  Enter the system to STANDBY mode.
@brief Enter the system to STANDBY mode .
/* Keep DSTANDBY mode when D1 domain enters Deepsleep */ /* Keep DSTANDBY mode when D2 domain enters Deepsleep */ /* Keep DSTANDBY mode when D3 domain enters Deepsleep */ /* Set SLEEPDEEP bit of Cortex System Control Register */ /* This option is used to ensure that store operations are completed */ /* Request Wait For Interrupt */