arch/arm/src/tiva/common/lm4xx_tm3c_sysctrl.c
/****************************************************************************
 * Name: tiva_clock_reconfigure
 *
 * Description:
 *   Called to change to new clock based on desired rcc and rcc2 settings.
 *   This is use to set up the initial clocking but can be used later to
 *   support slow clocked, low power consumption modes.
 *
 ****************************************************************************/
tiva_clock_reconfigure
Description:
Called to change to new clock based on desired rcc and rcc2 settings.
This is use to set up the initial clocking but can be used later to
support slow clocked, low power consumption modes.
tiva_clock_reconfigure Description : Called to change to new clock based on desired rcc and rcc2 settings . This is use to set up the initial clocking but can be used later to support slow clocked low power consumption modes .
void tiva_clock_reconfigure(uint32_t newrcc, uint32_t newrcc2)
{
  uint32_t rcc;
  uint32_t rcc2;
  rcc  = getreg32(TIVA_SYSCON_RCC);
  rcc2 = getreg32(TIVA_SYSCON_RCC2);
#if defined(LM4F) || defined(TM4C)
  if ((rcc & SYSCON_RCC_MOSCDIS) != 0 && (newrcc & SYSCON_RCC_MOSCDIS) == 0)
    {
      uint32_t dummy;
      rcc  |= SYSCON_RCC_BYPASS;
      rcc  &= ~(SYSCON_RCC_USESYSDIV);
      rcc2 |= SYSCON_RCC2_BYPASS2;
      putreg32(rcc, TIVA_SYSCON_RCC);
      dummy = getreg32(TIVA_SYSCON_RCC);
      UNUSED(dummy);
      putreg32(rcc2, TIVA_SYSCON_RCC2);
      rcc  &= ~RCC_XTALMASK;
      rcc  |= (newrcc & RCC_XTALMASK);
      rcc2 &= ~RCC2_XTALMASK;
      rcc2 |= (newrcc2 & RCC2_XTALMASK);
      putreg32(rcc, TIVA_SYSCON_RCC);
      dummy = getreg32(TIVA_SYSCON_RCC);
      UNUSED(dummy);
      putreg32(rcc2, TIVA_SYSCON_RCC2);
      tiva_delay(16);
      rcc  &= ~RCC_DIVMASK;
      rcc  |= (newrcc & RCC_DIVMASK);
      rcc2 &= ~RCC2_DIVMASK;
      rcc2 |= (newrcc2 & RCC2_DIVMASK);
      putreg32(rcc, TIVA_SYSCON_RCC);
      dummy = getreg32(TIVA_SYSCON_RCC);
      UNUSED(dummy);
      putreg32(rcc2, TIVA_SYSCON_RCC2);
      if ((newrcc & SYSCON_RCC_BYPASS) == 0)
        {
          tiva_pll_lock();
          rcc  &= ~SYSCON_RCC_BYPASS;
          rcc2 &= ~SYSCON_RCC2_BYPASS2;
          putreg32(rcc, TIVA_SYSCON_RCC);
          dummy = getreg32(TIVA_SYSCON_RCC);
          UNUSED(dummy);
          putreg32(rcc2, TIVA_SYSCON_RCC2);
        }
    }
#else
  if (((rcc & SYSCON_RCC_MOSCDIS) != 0 &&
       (newrcc & SYSCON_RCC_MOSCDIS) == 0) ||
      ((rcc & SYSCON_RCC_IOSCDIS) != 0 &&
       (newrcc & SYSCON_RCC_IOSCDIS) == 0))
    {
      rcc |= SYSCON_RCC_BYPASS;
      rcc &= ~(SYSCON_RCC_USESYSDIV);
      putreg32(rcc, TIVA_SYSCON_RCC);
      rcc2 |= SYSCON_RCC2_BYPASS2;
      putreg32(rcc2, TIVA_SYSCON_RCC2);
      rcc &= (~RCC_OSCMASK | (newrcc & RCC_OSCMASK));
      putreg32(rcc, TIVA_SYSCON_RCC);
      tiva_oscdelay(rcc, rcc2);
      rcc  &= ~RCC_XTALMASK;
      rcc  |= (newrcc & RCC_XTALMASK);
      rcc2 &= ~RCC2_XTALMASK;
      rcc2 |= (newrcc2 & RCC2_XTALMASK);
      putreg32(SYSCON_MISC_PLLLMIS, TIVA_SYSCON_MISC);
      putreg32(rcc, TIVA_SYSCON_RCC);
      putreg32(rcc2, TIVA_SYSCON_RCC2);
      tiva_delay(16);
      rcc  &= ~RCC_DIVMASK;
      rcc  |= (newrcc & RCC_DIVMASK);
      rcc2 &= ~RCC2_DIVMASK;
      rcc2 |= (newrcc2 & RCC2_DIVMASK);
      if ((newrcc & SYSCON_RCC_BYPASS) == 0)
        {
          tiva_pll_lock();
          rcc  &= ~SYSCON_RCC_BYPASS;
          rcc2 &= ~SYSCON_RCC2_BYPASS2;
        }
      putreg32(rcc, TIVA_SYSCON_RCC);
      putreg32(rcc2, TIVA_SYSCON_RCC2);
      tiva_delay(6);
    }
#endif
}
void tiva_clock_reconfigure ( uint32_t newrcc , uint32_t newrcc2 ) { uint32_t rcc ; uint32_t rcc2 ; rcc = getreg32 ( TIVA_SYSCON_RCC ) ; rcc2 = getreg32 ( TIVA_SYSCON_RCC2 ) ; #if defined ( LM4F ) || defined ( TM4C ) if ( ( rcc & SYSCON_RCC_MOSCDIS ) != 0 && ( newrcc & SYSCON_RCC_MOSCDIS ) == 0 ) { uint32_t dummy ; rcc |= SYSCON_RCC_BYPASS ; rcc &= ~ ( SYSCON_RCC_USESYSDIV ) ; rcc2 |= SYSCON_RCC2_BYPASS2 ; putreg32 ( rcc , TIVA_SYSCON_RCC ) ; dummy = getreg32 ( TIVA_SYSCON_RCC ) ; UNUSED ( dummy ) ; putreg32 ( rcc2 , TIVA_SYSCON_RCC2 ) ; rcc &= ~ RCC_XTALMASK ; rcc |= ( newrcc & RCC_XTALMASK ) ; rcc2 &= ~ RCC2_XTALMASK ; rcc2 |= ( newrcc2 & RCC2_XTALMASK ) ; putreg32 ( rcc , TIVA_SYSCON_RCC ) ; dummy = getreg32 ( TIVA_SYSCON_RCC ) ; UNUSED ( dummy ) ; putreg32 ( rcc2 , TIVA_SYSCON_RCC2 ) ; tiva_delay ( 16 ) ; rcc &= ~ RCC_DIVMASK ; rcc |= ( newrcc & RCC_DIVMASK ) ; rcc2 &= ~ RCC2_DIVMASK ; rcc2 |= ( newrcc2 & RCC2_DIVMASK ) ; putreg32 ( rcc , TIVA_SYSCON_RCC ) ; dummy = getreg32 ( TIVA_SYSCON_RCC ) ; UNUSED ( dummy ) ; putreg32 ( rcc2 , TIVA_SYSCON_RCC2 ) ; if ( ( newrcc & SYSCON_RCC_BYPASS ) == 0 ) { tiva_pll_lock ( ) ; rcc &= ~ SYSCON_RCC_BYPASS ; rcc2 &= ~ SYSCON_RCC2_BYPASS2 ; putreg32 ( rcc , TIVA_SYSCON_RCC ) ; dummy = getreg32 ( TIVA_SYSCON_RCC ) ; UNUSED ( dummy ) ; putreg32 ( rcc2 , TIVA_SYSCON_RCC2 ) ; } } #else if ( ( ( rcc & SYSCON_RCC_MOSCDIS ) != 0 && ( newrcc & SYSCON_RCC_MOSCDIS ) == 0 ) || ( ( rcc & SYSCON_RCC_IOSCDIS ) != 0 && ( newrcc & SYSCON_RCC_IOSCDIS ) == 0 ) ) { rcc |= SYSCON_RCC_BYPASS ; rcc &= ~ ( SYSCON_RCC_USESYSDIV ) ; putreg32 ( rcc , TIVA_SYSCON_RCC ) ; rcc2 |= SYSCON_RCC2_BYPASS2 ; putreg32 ( rcc2 , TIVA_SYSCON_RCC2 ) ; rcc &= ( ~ RCC_OSCMASK | ( newrcc & RCC_OSCMASK ) ) ; putreg32 ( rcc , TIVA_SYSCON_RCC ) ; tiva_oscdelay ( rcc , rcc2 ) ; rcc &= ~ RCC_XTALMASK ; rcc |= ( newrcc & RCC_XTALMASK ) ; rcc2 &= ~ RCC2_XTALMASK ; rcc2 |= ( newrcc2 & RCC2_XTALMASK ) ; putreg32 ( SYSCON_MISC_PLLLMIS , TIVA_SYSCON_MISC ) ; putreg32 ( rcc , TIVA_SYSCON_RCC ) ; putreg32 ( rcc2 , TIVA_SYSCON_RCC2 ) ; tiva_delay ( 16 ) ; rcc &= ~ RCC_DIVMASK ; rcc |= ( newrcc & RCC_DIVMASK ) ; rcc2 &= ~ RCC2_DIVMASK ; rcc2 |= ( newrcc2 & RCC2_DIVMASK ) ; if ( ( newrcc & SYSCON_RCC_BYPASS ) == 0 ) { tiva_pll_lock ( ) ; rcc &= ~ SYSCON_RCC_BYPASS ; rcc2 &= ~ SYSCON_RCC2_BYPASS2 ; } putreg32 ( rcc , TIVA_SYSCON_RCC ) ; putreg32 ( rcc2 , TIVA_SYSCON_RCC2 ) ; tiva_delay ( 6 ) ; } #endif }
Name: tiva_clock_reconfigure
 Description:
   Called to change to new clock based on desired rcc and rcc2 settings.
Name : tiva_clock_reconfigure Description : Called to change to new clock based on desired rcc and rcc2 settings .
/* We are probably using the main oscillator.  The main oscillator is
   * disabled on reset and so probably must be enabled here.  The internal
   * oscillator is enabled on reset and if that is selected, most likely
   * nothing needs to be done.
   */ /* Get the current values of the RCC and RCC2 registers */ /* According to TM4C123GH6PM datasheet page 231 item 5.3 we must
       * perform the following steps to initialize and configure TM4C123G
       * chip to use a PLL based system clock.
       *
       * 1. Bypass the PLL and system clock divider by setting the BYPASS
       *    bit and clearing the USESYS bit in the RCC register.
       *
       * 2. Select the crystal value (XTAL) and oscillator source (OSCSRC),
       *    and clear the PWRDN bit in RCC/RCC2. Setting the XTAL field
       *    automatically pulls valid PLL configuration data for the
       *    appropriate crystal, and clearing the PWRDN bit powers and
       *    enables the PLL and its output.
       *
       * 3. Select the desired system divider (SYSDIV) in RCC/RCC2 and set
       *    the USESYS bit in RCC. The SYSDIV field determines the system
       *    frequency for the microcontroller.
       *
       * 4. Wait for the PLL to lock by polling the PLLLRIS bit in the Raw
       *    Interrupt Status (RIS) register.
       *
       * 5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2.
       */ /* Step 1 - Temporarily bypass the PLL and system clock dividers */ /* According to TM4C123GH6PM datasheet we must write RCC register prior
       * to writing the RCC2 register.
       */ /* Step 2 - Set the new crystal value, oscillator source and PLL
       * configuration.
       */ /* Write the new RCC/RCC2 values.
       *
       * LM4F120 Data Sheet:  "Write the RCC register prior to writing the
       * RCC2 register. If a subsequent write to the RCC register is
       * required, include another register access after writing the RCC
       * register and before writing the RCC2 register."
       */ /* Wait for the new crystal value and oscillator source to take
       * effect
       */ /* Step 3 - Set the requested system divider and disable the non-
       * selected oscillators.
       */ /* Step 4 - Will the PLL output be used to clock the system? */ /* Yes, wait until the PLL is locked */ /* Step 5 - Then enable the PLL */ /* Temporarily bypass the PLL and system clock dividers */ /* Enable any selected oscillators (but don't disable any yet) */ /* Wait for the newly selected oscillator(s) to settle.  This is
       * tricky because the time that we wait can be significant and is
       * determined by the previous clock setting, not the one that we are
       * configuring.
       */ /* Set the new crystal value, oscillator source and PLL configuration */ /* Clear the PLL lock interrupt */ /* Write the new RCC/RCC2 values.
       *
       * Original LM3S Logic: Order depends upon whether RCC2 or RCC is
       * currently enabled.
       */ /* Wait for the new crystal value and oscillator source to take
       * effect
       */ /* Set the requested system divider and disable the non-selected
       * osciallators
       */ /* Will the PLL output be used to clock the system? */ /* Yes, wait until the PLL is locked */ /* Then enable the PLL */ /* Now we can set the final RCC/RCC2 values */ /* Wait for the system divider to be effective */