FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/platform/mpfs_hal/common/mss_l2_cache.c
/*==============================================================================
 * Reserve a number of cache ways to be used as scratchpad memory.
 *
 * @param nways
 *  Number of ways to be used as scratchpad. One way is 128Kbytes.
 *
 * @param scratchpad_start
 *  Start address within the Zero Device memory range in which the scratchpad
 *  will be located.
 */
Reserve a number of cache ways to be used as scratchpad memory.
@param nways
Number of ways to be used as scratchpad. One way is 128Kbytes.

@param scratchpad_start
Start address within the Zero Device memory range in which the scratchpad
will be located.
Reserve a number of cache ways to be used as scratchpad memory . @param nways Number of ways to be used as scratchpad . One way is 128Kbytes . @param scratchpad_start Start address within the Zero Device memory range in which the scratchpad will be located .
static void reserve_scratchpad_ways(uint8_t nways, uint64_t * scratchpad_start)
{
    uint8_t way_enable;
    uint64_t available_ways = 1;
    uint64_t scratchpad_ways = 0;
    uint64_t non_scratchpad_ways;
    uint32_t inc;
    ASSERT(scratchpad_start >= (uint64_t *)ZERO_DEVICE_BOTTOM);
    ASSERT(scratchpad_start < (uint64_t *)ZERO_DEVICE_TOP);
    way_enable = CACHE_CTRL->WAY_ENABLE;
    ASSERT(nways <= way_enable);
    if(nways <= way_enable)
    {
        for(inc = 0; inc < way_enable; ++inc)
        {
            available_ways = (available_ways << 1) | (uint64_t)0x01;
            if(inc < nways)
            {
                scratchpad_ways = (scratchpad_ways << 1) | (uint64_t)0x01;
            }
        }
        non_scratchpad_ways = available_ways &  ~scratchpad_ways;
        CACHE_CTRL->WAY_MASK_DMA = non_scratchpad_ways;
        CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_0 = non_scratchpad_ways;
        CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_1 = non_scratchpad_ways;
        CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_2 = non_scratchpad_ways;
        CACHE_CTRL->WAY_MASK_AXI4_SLAVE_PORT_3 = non_scratchpad_ways;
        CACHE_CTRL->WAY_MASK_E51_ICACHE = non_scratchpad_ways;
        CACHE_CTRL->WAY_MASK_U54_1_DCACHE = non_scratchpad_ways;
        CACHE_CTRL->WAY_MASK_U54_1_ICACHE = non_scratchpad_ways;
        CACHE_CTRL->WAY_MASK_U54_2_DCACHE = non_scratchpad_ways;
        CACHE_CTRL->WAY_MASK_U54_2_ICACHE = non_scratchpad_ways;
        CACHE_CTRL->WAY_MASK_U54_3_DCACHE = non_scratchpad_ways;
        CACHE_CTRL->WAY_MASK_U54_3_ICACHE = non_scratchpad_ways;
        CACHE_CTRL->WAY_MASK_U54_4_DCACHE = non_scratchpad_ways;
        CACHE_CTRL->WAY_MASK_U54_4_ICACHE = non_scratchpad_ways;
        uint64_t * p_scratchpad = scratchpad_start;
        int ways_inc;
        uint64_t current_way = 1;
        for(ways_inc = 0; ways_inc < nways; ++ways_inc)
        {
            CACHE_CTRL->WAY_MASK_E51_DCACHE = current_way;
            for(inc = 0; inc < (WAY_BYTE_LENGTH / CACHE_BLOCK_BYTE_LENGTH); ++inc)
            {
                *p_scratchpad = g_init_marker + inc;
                p_scratchpad += CACHE_BLOCK_BYTE_LENGTH / UINT64_BYTE_LENGTH;
            }
            current_way = current_way << 1U;
            mb();
        }
        CACHE_CTRL->WAY_MASK_E51_DCACHE = non_scratchpad_ways;
    }
}
static void reserve_scratchpad_ways ( uint8_t nways , uint64_t * scratchpad_start ) { uint8_t way_enable ; uint64_t available_ways = 1 ; uint64_t scratchpad_ways = 0 ; uint64_t non_scratchpad_ways ; uint32_t inc ; ASSERT ( scratchpad_start >= ( uint64_t * ) ZERO_DEVICE_BOTTOM ) ; ASSERT ( scratchpad_start < ( uint64_t * ) ZERO_DEVICE_TOP ) ; way_enable = CACHE_CTRL -> WAY_ENABLE ; ASSERT ( nways <= way_enable ) ; if ( nways <= way_enable ) { for ( inc = 0 ; inc < way_enable ; ++ inc ) { available_ways = ( available_ways << 1 ) | ( uint64_t ) 0x01 ; if ( inc < nways ) { scratchpad_ways = ( scratchpad_ways << 1 ) | ( uint64_t ) 0x01 ; } } non_scratchpad_ways = available_ways & ~ scratchpad_ways ; CACHE_CTRL -> WAY_MASK_DMA = non_scratchpad_ways ; CACHE_CTRL -> WAY_MASK_AXI4_SLAVE_PORT_0 = non_scratchpad_ways ; CACHE_CTRL -> WAY_MASK_AXI4_SLAVE_PORT_1 = non_scratchpad_ways ; CACHE_CTRL -> WAY_MASK_AXI4_SLAVE_PORT_2 = non_scratchpad_ways ; CACHE_CTRL -> WAY_MASK_AXI4_SLAVE_PORT_3 = non_scratchpad_ways ; CACHE_CTRL -> WAY_MASK_E51_ICACHE = non_scratchpad_ways ; CACHE_CTRL -> WAY_MASK_U54_1_DCACHE = non_scratchpad_ways ; CACHE_CTRL -> WAY_MASK_U54_1_ICACHE = non_scratchpad_ways ; CACHE_CTRL -> WAY_MASK_U54_2_DCACHE = non_scratchpad_ways ; CACHE_CTRL -> WAY_MASK_U54_2_ICACHE = non_scratchpad_ways ; CACHE_CTRL -> WAY_MASK_U54_3_DCACHE = non_scratchpad_ways ; CACHE_CTRL -> WAY_MASK_U54_3_ICACHE = non_scratchpad_ways ; CACHE_CTRL -> WAY_MASK_U54_4_DCACHE = non_scratchpad_ways ; CACHE_CTRL -> WAY_MASK_U54_4_ICACHE = non_scratchpad_ways ; uint64_t * p_scratchpad = scratchpad_start ; int ways_inc ; uint64_t current_way = 1 ; for ( ways_inc = 0 ; ways_inc < nways ; ++ ways_inc ) { CACHE_CTRL -> WAY_MASK_E51_DCACHE = current_way ; for ( inc = 0 ; inc < ( WAY_BYTE_LENGTH / CACHE_BLOCK_BYTE_LENGTH ) ; ++ inc ) { * p_scratchpad = g_init_marker + inc ; p_scratchpad += CACHE_BLOCK_BYTE_LENGTH / UINT64_BYTE_LENGTH ; } current_way = current_way << 1U ; mb ( ) ; } CACHE_CTRL -> WAY_MASK_E51_DCACHE = non_scratchpad_ways ; } }
Reserve a number of cache ways to be used as scratchpad memory.
Reserve a number of cache ways to be used as scratchpad memory .
/*
     * Ensure at least one way remains available as cache.
     */ /*
         * Compute the mask used to specify ways that will be used by the
         * scratchpad.
         */ /*
         * Prevent other masters from evicting cache lines from scratchpad ways.
         * Only allow E51 to evict from scratchpad ways.
         */ /*
         * Assign ways to Zero Device
         */ /*
             * Populate the scratchpad memory one way at a time.
             */ /*
             * Write to the first 64-bit location of each cache block.
             */ /*
         * Prevent E51 from evicting from scratchpad ways.
         */