linux/drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c
/**
 * amdgpu_gem_begin_cpu_access - &dma_buf_ops.begin_cpu_access implementation
 * @dma_buf: shared DMA buffer
 * @direction: direction of DMA transfer
 *
 * This is called before CPU access to the shared DMA buffer's memory. If it's
 * a read access, the buffer is moved to the GTT domain if possible, for optimal
 * CPU read performance.
 *
 * Returns:
 * 0 on success or negative error code.
 */
&dma_buf_ops.begin_cpu_access implementation
@dma_buf: shared DMA buffer
@direction: direction of DMA transfer

This is called before CPU access to the shared DMA buffer's memory. If it's
a read access, the buffer is moved to the GTT domain if possible, for optimal
CPU read performance.

0 on success or negative error code.
&dma_buf_ops . begin_cpu_access implementation @dma_buf : shared DMA buffer @direction : direction of DMA transfer This is called before CPU access to the shared DMA buffer ' s memory . If it ' s a read access the buffer is moved to the GTT domain if possible for optimal CPU read performance . 0 on success or negative error code .
static int amdgpu_gem_begin_cpu_access(struct dma_buf *dma_buf,
				       enum dma_data_direction direction)
{
	struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
	struct ttm_operation_ctx ctx = { true, false };
	u32 domain = amdgpu_display_supported_domains(adev);
	int ret;
	bool reads = (direction == DMA_BIDIRECTIONAL ||
		      direction == DMA_FROM_DEVICE);
	if (!reads || !(domain & AMDGPU_GEM_DOMAIN_GTT))
		return 0;
	ret = amdgpu_bo_reserve(bo, false);
	if (unlikely(ret != 0))
		return ret;
	if (!bo->pin_count && (bo->allowed_domains & AMDGPU_GEM_DOMAIN_GTT)) {
		amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
		ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
	}
	amdgpu_bo_unreserve(bo);
	return ret;
}
static int amdgpu_gem_begin_cpu_access ( struct dma_buf * dma_buf , enum dma_data_direction direction ) { struct amdgpu_bo * bo = gem_to_amdgpu_bo ( dma_buf -> priv ) ; struct amdgpu_device * adev = amdgpu_ttm_adev ( bo -> tbo . bdev ) ; struct ttm_operation_ctx ctx = { true , false } ; u32 domain = amdgpu_display_supported_domains ( adev ) ; int ret ; bool reads = ( direction == DMA_BIDIRECTIONAL || direction == DMA_FROM_DEVICE ) ; if ( ! reads || ! ( domain & AMDGPU_GEM_DOMAIN_GTT ) ) return 0 ; ret = amdgpu_bo_reserve ( bo , false ) ; if ( unlikely ( ret != 0 ) ) return ret ; if ( ! bo -> pin_count && ( bo -> allowed_domains & AMDGPU_GEM_DOMAIN_GTT ) ) { amdgpu_bo_placement_from_domain ( bo , AMDGPU_GEM_DOMAIN_GTT ) ; ret = ttm_bo_validate ( & bo -> tbo , & bo -> placement , & ctx ) ; } amdgpu_bo_unreserve ( bo ) ; return ret ; }
amdgpu_gem_begin_cpu_access - &dma_buf_ops.begin_cpu_access implementation
 @dma_buf: shared DMA buffer
 @direction: direction of DMA transfer
amdgpu_gem_begin_cpu_access - &dma_buf_ops . begin_cpu_access implementation @dma_buf : shared DMA buffer @direction : direction of DMA transfer
/* move to gtt */