FreeBSD/sys/dev/fb/vga.c
/*
 * load_state():
 * Set video registers at once.
 * NOTE: this function only updates the standard EGA/VGA registers.
 * any extra/extended registers of SVGA adapters are not changed.
 *
 * EGA/VGA
 */
Set video registers at once.
NOTE: this function only updates the standard EGA/VGA registers.
any extra/extended registers of SVGA adapters are not changed.

EGA/VGA
Set video registers at once . NOTE : this function only updates the standard EGA / VGA registers . any extra / extended registers of SVGA adapters are not changed . EGA / VGA
static int
vga_load_state(video_adapter_t *adp, void *p)
{
    u_char *buf;
    int crtc_addr;
    int s;
    int i;
    prologue(adp, V_ADP_STATELOAD, ENODEV);
    if (((adp_state_t *)p)->sig != V_STATE_SIG)
	return EINVAL;
    buf = ((adp_state_t *)p)->regs;
    crtc_addr = adp->va_crtc_addr;
#if VGA_DEBUG > 1
    dump_buffer(buf, V_MODE_PARAM_SIZE);
#endif
    s = splhigh();
    outb(TSIDX, 0x00); outb(TSREG, 0x01);	
    for (i = 0; i < 4; ++i) {			
	outb(TSIDX, i + 1);
	outb(TSREG, buf[i + 5]);
    }
    outb(MISC, buf[9]);				
    outb(TSIDX, 0x00); outb(TSREG, 0x03);	
    outb(crtc_addr, 0x11);
    outb(crtc_addr + 1, inb(crtc_addr + 1) & 0x7F);
    for (i = 0; i < 25; ++i) {			
	outb(crtc_addr, i);
	outb(crtc_addr + 1, buf[i + 10]);
    }
    inb(crtc_addr+6);				
    for (i = 0; i < 20; ++i) {			
	outb(ATC, i);
	outb(ATC, buf[i + 35]);
    }
    for (i = 0; i < 9; ++i) {			
	outb(GDCIDX, i);
	outb(GDCREG, buf[i + 55]);
    }
    inb(crtc_addr + 6);				
    outb(ATC, 0x20);				
#ifdef notyet 
#ifndef VGA_NO_BIOS
    if (adp->va_unit == V_ADP_PRIMARY) {
	writeb(BIOS_PADDRTOVADDR(0x44a), buf[0]);	
	writeb(BIOS_PADDRTOVADDR(0x484), buf[1] + rows_offset - 1); 
	writeb(BIOS_PADDRTOVADDR(0x485), buf[2]);	
#if 0
	writeb(BIOS_PADDRTOVADDR(0x44c), buf[3]);
	writeb(BIOS_PADDRTOVADDR(0x44d), buf[4]);
#endif
    }
#endif 
#endif 
    splx(s);
    return 0;
}
static int vga_load_state ( video_adapter_t * adp , void * p ) { u_char * buf ; int crtc_addr ; int s ; int i ; prologue ( adp , V_ADP_STATELOAD , ENODEV ) ; if ( ( ( adp_state_t * ) p ) -> sig != V_STATE_SIG ) return EINVAL ; buf = ( ( adp_state_t * ) p ) -> regs ; crtc_addr = adp -> va_crtc_addr ; #if VGA_DEBUG > 1 dump_buffer ( buf , V_MODE_PARAM_SIZE ) ; #endif s = splhigh ( ) ; outb ( TSIDX , 0x00 ) ; outb ( TSREG , 0x01 ) ; for ( i = 0 ; i < 4 ; ++ i ) { outb ( TSIDX , i + 1 ) ; outb ( TSREG , buf [ i + 5 ] ) ; } outb ( MISC , buf [ 9 ] ) ; outb ( TSIDX , 0x00 ) ; outb ( TSREG , 0x03 ) ; outb ( crtc_addr , 0x11 ) ; outb ( crtc_addr + 1 , inb ( crtc_addr + 1 ) & 0x7F ) ; for ( i = 0 ; i < 25 ; ++ i ) { outb ( crtc_addr , i ) ; outb ( crtc_addr + 1 , buf [ i + 10 ] ) ; } inb ( crtc_addr + 6 ) ; for ( i = 0 ; i < 20 ; ++ i ) { outb ( ATC , i ) ; outb ( ATC , buf [ i + 35 ] ) ; } for ( i = 0 ; i < 9 ; ++ i ) { outb ( GDCIDX , i ) ; outb ( GDCREG , buf [ i + 55 ] ) ; } inb ( crtc_addr + 6 ) ; outb ( ATC , 0x20 ) ; #ifdef notyet #ifndef VGA_NO_BIOS if ( adp -> va_unit == V_ADP_PRIMARY ) { writeb ( BIOS_PADDRTOVADDR ( 0x44a ) , buf [ 0 ] ) ; writeb ( BIOS_PADDRTOVADDR ( 0x484 ) , buf [ 1 ] + rows_offset - 1 ) ; writeb ( BIOS_PADDRTOVADDR ( 0x485 ) , buf [ 2 ] ) ; #if 0 writeb ( BIOS_PADDRTOVADDR ( 0x44c ) , buf [ 3 ] ) ; writeb ( BIOS_PADDRTOVADDR ( 0x44d ) , buf [ 4 ] ) ; #endif } #endif #endif splx ( s ) ; return 0 ; }
load_state():
 Set video registers at once.
load_state () : Set video registers at once .
/* stop sequencer */ /* program sequencer */ /* set dot-clock */ /* start sequencer */ /* program crtc */ /* reset flip-flop */ /* program attribute ctrl */ /* program graph data ctrl */ /* reset flip-flop */ /* enable palette */ /* a temporary workaround for kernel panic, XXX */ /* COLS */ /* ROWS */ /* POINTS */ /* VGA_NO_BIOS */ /* notyet */