drivers/arm/gic/arm_gic.c
/*******************************************************************************
 * Place the cpu interface in a state where it can never make a cpu exit wfi as
 * as result of an asserted interrupt. This is critical for powering down a cpu
 ******************************************************************************/
Place the cpu interface in a state where it can never make a cpu exit wfi as
as result of an asserted interrupt. This is critical for powering down a cpu
Place the cpu interface in a state where it can never make a cpu exit wfi as as result of an asserted interrupt . This is critical for powering down a cpu
void arm_gic_cpuif_deactivate(void)
{
	unsigned int val;
	assert(g_gicc_base);
	val = gicc_read_ctlr(g_gicc_base);
	val &= ~(ENABLE_GRP0 | ENABLE_GRP1);
	val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0;
	val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1;
	gicc_write_ctlr(g_gicc_base, val);
	val = gicc_read_iidr(g_gicc_base);
	if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3)
		gicv3_cpuif_deactivate();
}
void arm_gic_cpuif_deactivate ( void ) { unsigned int val ; assert ( g_gicc_base ) ; val = gicc_read_ctlr ( g_gicc_base ) ; val &= ~ ( ENABLE_GRP0 | ENABLE_GRP1 ) ; val |= FIQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP0 ; val |= IRQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP1 ; gicc_write_ctlr ( g_gicc_base , val ) ; val = gicc_read_iidr ( g_gicc_base ) ; if ( ( ( val >> GICC_IIDR_ARCH_SHIFT ) & GICC_IIDR_ARCH_MASK ) >= 3 ) gicv3_cpuif_deactivate ( ) ; }
Place the cpu interface in a state where it can never make a cpu exit wfi as
 as result of an asserted interrupt.
Place the cpu interface in a state where it can never make a cpu exit wfi as as result of an asserted interrupt .
/* Disable secure, non-secure interrupts and disable their bypass */ /*
	 * If GICv3 we need to do a bit of additional setup. Make sure the
	 * RDIST is put to sleep.
	 */