src/qemu/src-pmp/accel/tcg/cputlb.c
/* Probe for whether the specified guest write access is permitted.
 * If it is not permitted then an exception will be taken in the same
 * way as if this were a real write access (and we will not return).
 * Otherwise the function will return, and there will be a valid
 * entry in the TLB for this access.
 */
Probe for whether the specified guest write access is permitted.
If it is not permitted then an exception will be taken in the same
way as if this were a real write access (and we will not return).
Otherwise the function will return, and there will be a valid
entry in the TLB for this access.
Probe for whether the specified guest write access is permitted . If it is not permitted then an exception will be taken in the same way as if this were a real write access ( and we will not return ) . Otherwise the function will return and there will be a valid entry in the TLB for this access .
void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
                 uintptr_t retaddr)
{
    uintptr_t index = tlb_index(env, mmu_idx, addr);
    CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
    if (!tlb_hit(tlb_addr_write(entry), addr)) {
        if (!VICTIM_TLB_HIT(addr_write, addr)) {
            tlb_fill(ENV_GET_CPU(env), addr, size, MMU_DATA_STORE,
                     mmu_idx, retaddr);
        }
    }
}
void probe_write ( CPUArchState * env , target_ulong addr , int size , int mmu_idx , uintptr_t retaddr ) { uintptr_t index = tlb_index ( env , mmu_idx , addr ) ; CPUTLBEntry * entry = tlb_entry ( env , mmu_idx , addr ) ; if ( ! tlb_hit ( tlb_addr_write ( entry ) , addr ) ) { if ( ! VICTIM_TLB_HIT ( addr_write , addr ) ) { tlb_fill ( ENV_GET_CPU ( env ) , addr , size , MMU_DATA_STORE , mmu_idx , retaddr ) ; } } }
Probe for whether the specified guest write access is permitted.
Probe for whether the specified guest write access is permitted .
/* TLB entry is for a different page */