FreeBSD/sys/dev/nxge/xgehal/xgehal-device.c
/*
 * __hal_device_pci_init
 * @hldev: HAL device handle.
 *
 * Initialize certain PCI/PCI-X configuration registers
 * with recommended values. Save config space for future hw resets.
 */
hal_device_pci_init
@hldev: HAL device handle.

Initialize certain PCI/PCI-X configuration registers
with recommended values. Save config space for future hw resets.
hal_device_pci_init @hldev : HAL device handle . Initialize certain PCI / PCI - X configuration registers with recommended values . Save config space for future hw resets .
static void
__hal_device_pci_init(xge_hal_device_t *hldev)
{
	int i, pcisize = 0;
	u16 cmd = 0;
	u8  val;
	xge_os_pci_read16(hldev->pdev,hldev->cfgh,
	        xge_offsetof(xge_hal_pci_config_le_t, device_id),
	        &hldev->device_id);
	xge_os_pci_read8(hldev->pdev,hldev->cfgh,
	        xge_offsetof(xge_hal_pci_config_le_t, revision),
	        &hldev->revision);
	if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_HERC)
	    pcisize = XGE_HAL_PCISIZE_HERC;
	else if (xge_hal_device_check_id(hldev) == XGE_HAL_CARD_XENA)
	    pcisize = XGE_HAL_PCISIZE_XENA;
	for (i = 0; i < pcisize; i++) {
	    xge_os_pci_read32(hldev->pdev, hldev->cfgh, i*4,
	                    (u32*)&hldev->pci_config_space_bios + i);
	}
	xge_os_pci_read16(hldev->pdev, hldev->cfgh,
	        xge_offsetof(xge_hal_pci_config_le_t, command), &cmd);
	cmd |= 0x140;
	xge_os_pci_write16(hldev->pdev, hldev->cfgh,
	         xge_offsetof(xge_hal_pci_config_le_t, command), cmd);
	if (hldev->config.latency_timer &&
	    hldev->config.latency_timer != XGE_HAL_USE_BIOS_DEFAULT_LATENCY) {
	    xge_os_pci_write8(hldev->pdev, hldev->cfgh,
	                 xge_offsetof(xge_hal_pci_config_le_t,
	                 latency_timer),
	         (u8)hldev->config.latency_timer);
	}
	xge_os_pci_read8(hldev->pdev, hldev->cfgh,
	    xge_offsetof(xge_hal_pci_config_le_t, latency_timer), &val);
	hldev->config.latency_timer = val;
	xge_os_pci_read16(hldev->pdev, hldev->cfgh,
	    xge_offsetof(xge_hal_pci_config_le_t, pcix_command), &cmd);
	cmd |= 1;
	xge_os_pci_write16(hldev->pdev, hldev->cfgh,
	     xge_offsetof(xge_hal_pci_config_le_t, pcix_command), cmd);
	if (hldev->config.mmrb_count != XGE_HAL_DEFAULT_BIOS_MMRB_COUNT) {
	    cmd &= 0xFFF3;
	    cmd |= hldev->config.mmrb_count << 2;
	    xge_os_pci_write16(hldev->pdev, hldev->cfgh,
	           xge_offsetof(xge_hal_pci_config_le_t, pcix_command),
	           cmd);
	}
	xge_os_pci_read16(hldev->pdev, hldev->cfgh,
	            xge_offsetof(xge_hal_pci_config_le_t, pcix_command),
	            &cmd);
	cmd &= 0x000C;
	hldev->config.mmrb_count = cmd>>2;
	if (hldev->config.max_splits_trans != XGE_HAL_USE_BIOS_DEFAULT_SPLITS)  {
	    xge_os_pci_read16(hldev->pdev, hldev->cfgh,
	        xge_offsetof(xge_hal_pci_config_le_t, pcix_command),
	        &cmd);
	    cmd &= 0xFF8F;
	    cmd |= hldev->config.max_splits_trans << 4;
	    xge_os_pci_write16(hldev->pdev, hldev->cfgh,
	        xge_offsetof(xge_hal_pci_config_le_t, pcix_command),
	        cmd);
	}
	xge_os_pci_read16(hldev->pdev, hldev->cfgh,
	    xge_offsetof(xge_hal_pci_config_le_t, pcix_command), &cmd);
	cmd &= 0x0070;
	hldev->config.max_splits_trans = cmd>>4;
	xge_os_pci_read16(hldev->pdev, hldev->cfgh,
	    xge_offsetof(xge_hal_pci_config_le_t, pcix_command), &cmd);
	cmd &= 0xFFFD;
	xge_os_pci_write16(hldev->pdev, hldev->cfgh,
	     xge_offsetof(xge_hal_pci_config_le_t, pcix_command), cmd);
	for (i = 0; i < pcisize; i++) {
	    xge_os_pci_read32(hldev->pdev, hldev->cfgh, i*4,
	                    (u32*)&hldev->pci_config_space + i);
	}
}
static void __hal_device_pci_init ( xge_hal_device_t * hldev ) { int i , pcisize = 0 ; u16 cmd = 0 ; u8 val ; xge_os_pci_read16 ( hldev -> pdev , hldev -> cfgh , xge_offsetof ( xge_hal_pci_config_le_t , device_id ) , & hldev -> device_id ) ; xge_os_pci_read8 ( hldev -> pdev , hldev -> cfgh , xge_offsetof ( xge_hal_pci_config_le_t , revision ) , & hldev -> revision ) ; if ( xge_hal_device_check_id ( hldev ) == XGE_HAL_CARD_HERC ) pcisize = XGE_HAL_PCISIZE_HERC ; else if ( xge_hal_device_check_id ( hldev ) == XGE_HAL_CARD_XENA ) pcisize = XGE_HAL_PCISIZE_XENA ; for ( i = 0 ; i < pcisize ; i ++ ) { xge_os_pci_read32 ( hldev -> pdev , hldev -> cfgh , i * 4 , ( u32 * ) & hldev -> pci_config_space_bios + i ) ; } xge_os_pci_read16 ( hldev -> pdev , hldev -> cfgh , xge_offsetof ( xge_hal_pci_config_le_t , command ) , & cmd ) ; cmd |= 0x140 ; xge_os_pci_write16 ( hldev -> pdev , hldev -> cfgh , xge_offsetof ( xge_hal_pci_config_le_t , command ) , cmd ) ; if ( hldev -> config . latency_timer && hldev -> config . latency_timer != XGE_HAL_USE_BIOS_DEFAULT_LATENCY ) { xge_os_pci_write8 ( hldev -> pdev , hldev -> cfgh , xge_offsetof ( xge_hal_pci_config_le_t , latency_timer ) , ( u8 ) hldev -> config . latency_timer ) ; } xge_os_pci_read8 ( hldev -> pdev , hldev -> cfgh , xge_offsetof ( xge_hal_pci_config_le_t , latency_timer ) , & val ) ; hldev -> config . latency_timer = val ; xge_os_pci_read16 ( hldev -> pdev , hldev -> cfgh , xge_offsetof ( xge_hal_pci_config_le_t , pcix_command ) , & cmd ) ; cmd |= 1 ; xge_os_pci_write16 ( hldev -> pdev , hldev -> cfgh , xge_offsetof ( xge_hal_pci_config_le_t , pcix_command ) , cmd ) ; if ( hldev -> config . mmrb_count != XGE_HAL_DEFAULT_BIOS_MMRB_COUNT ) { cmd &= 0xFFF3 ; cmd |= hldev -> config . mmrb_count << 2 ; xge_os_pci_write16 ( hldev -> pdev , hldev -> cfgh , xge_offsetof ( xge_hal_pci_config_le_t , pcix_command ) , cmd ) ; } xge_os_pci_read16 ( hldev -> pdev , hldev -> cfgh , xge_offsetof ( xge_hal_pci_config_le_t , pcix_command ) , & cmd ) ; cmd &= 0x000C ; hldev -> config . mmrb_count = cmd >> 2 ; if ( hldev -> config . max_splits_trans != XGE_HAL_USE_BIOS_DEFAULT_SPLITS ) { xge_os_pci_read16 ( hldev -> pdev , hldev -> cfgh , xge_offsetof ( xge_hal_pci_config_le_t , pcix_command ) , & cmd ) ; cmd &= 0xFF8F ; cmd |= hldev -> config . max_splits_trans << 4 ; xge_os_pci_write16 ( hldev -> pdev , hldev -> cfgh , xge_offsetof ( xge_hal_pci_config_le_t , pcix_command ) , cmd ) ; } xge_os_pci_read16 ( hldev -> pdev , hldev -> cfgh , xge_offsetof ( xge_hal_pci_config_le_t , pcix_command ) , & cmd ) ; cmd &= 0x0070 ; hldev -> config . max_splits_trans = cmd >> 4 ; xge_os_pci_read16 ( hldev -> pdev , hldev -> cfgh , xge_offsetof ( xge_hal_pci_config_le_t , pcix_command ) , & cmd ) ; cmd &= 0xFFFD ; xge_os_pci_write16 ( hldev -> pdev , hldev -> cfgh , xge_offsetof ( xge_hal_pci_config_le_t , pcix_command ) , cmd ) ; for ( i = 0 ; i < pcisize ; i ++ ) { xge_os_pci_read32 ( hldev -> pdev , hldev -> cfgh , i * 4 , ( u32 * ) & hldev -> pci_config_space + i ) ; } }
__hal_device_pci_init
 @hldev: HAL device handle.
__hal_device_pci_init @hldev : HAL device handle .
/* Store PCI device ID and revision for future references where in we
	 * decide Xena revision using PCI sub system ID */ /* save original PCI config space to restore it on device_terminate() */ /* Set the PErr Repconse bit and SERR in PCI command register. */ /* Set user spcecified value for the PCI Latency Timer */ /* Read back latency timer to reflect it into user level */ /* Enable Data Parity Error Recovery in PCI-X command register. */ /* Set MMRB count in PCI-X command register. */ /* Read back MMRB count to reflect it into user level */ /*  Setting Maximum outstanding splits based on system type. */ /* Read back max split trans to reflect it into user level */ /* Forcibly disabling relaxed ordering capability of the card. */ /* save PCI config space for future resets */