FreeBSD/sys/arm/ti/ti_sdma.c
/**
 *	ti_sdma_attach - driver attach function
 *	@dev: dma device handle
 *
 *	Initialises memory mapping/pointers to the DMA register set and requests
 *	IRQs. This is effectively the setup function for the driver.
 *
 *	RETURNS:
 *	0 on success or a negative error code failure.
 */
driver attach function
@dev: dma device handle

Initialises memory mapping/pointers to the DMA register set and requests
IRQs. This is effectively the setup function for the driver.

0 on success or a negative error code failure.
driver attach function @dev : dma device handle Initialises memory mapping / pointers to the DMA register set and requests IRQs . This is effectively the setup function for the driver . 0 on success or a negative error code failure .
static int
ti_sdma_attach(device_t dev)
{
	struct ti_sdma_softc *sc = device_get_softc(dev);
	unsigned int timeout;
	unsigned int i;
	int      rid;
	void    *ihl;
	int      err;
	sc->sc_dev = dev;
	sc->sc_active_channels = 0x00000000;
	TI_SDMA_LOCK_INIT(sc);
	rid = 0;
	sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
	if (sc->sc_mem_res == NULL)
		panic("%s: Cannot map registers", device_get_name(dev));
	ti_prcm_clk_enable(SDMA_CLK);
	sc->sc_hw_rev = ti_sdma_read_4(sc, DMA4_REVISION);
	device_printf(dev, "sDMA revision %08x\n", sc->sc_hw_rev);
	if (!ti_sdma_is_omap4_rev(sc) && !ti_sdma_is_omap3_rev(sc)) {
		device_printf(sc->sc_dev, "error - unknown sDMA H/W revision\n");
		return (EINVAL);
	}
	for (i = 0; i < NUM_DMA_IRQS; i++) {
		ti_sdma_write_4(sc, DMA4_IRQENABLE_L(i), 0x00000000);
	}
	if (ti_sdma_is_omap3_rev(sc)) {
		ti_sdma_write_4(sc, DMA4_OCP_SYSCONFIG, 0x0002);
		timeout = (hz < 10) ? 1 : ((100 * hz) / 1000);
		while ((ti_sdma_read_4(sc, DMA4_SYSSTATUS) & 0x1) == 0x0) {
			pause("DMARESET", 1);
			if (timeout-- == 0) {
				device_printf(sc->sc_dev, "sDMA reset operation timed out\n");
				return (EINVAL);
			}
		}
	}
	rid = 0;
	sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
	    RF_ACTIVE | RF_SHAREABLE);
	if (sc->sc_irq_res == NULL)
		panic("Unable to setup the dma irq handler.\n");
	err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
	    NULL, ti_sdma_intr, NULL, &ihl);
	if (err)
		panic("%s: Cannot register IRQ", device_get_name(dev));
	ti_sdma_sc = sc;
	return (0);
}
static int ti_sdma_attach ( device_t dev ) { struct ti_sdma_softc * sc = device_get_softc ( dev ) ; unsigned int timeout ; unsigned int i ; int rid ; void * ihl ; int err ; sc -> sc_dev = dev ; sc -> sc_active_channels = 0x00000000 ; TI_SDMA_LOCK_INIT ( sc ) ; rid = 0 ; sc -> sc_mem_res = bus_alloc_resource_any ( dev , SYS_RES_MEMORY , & rid , RF_ACTIVE ) ; if ( sc -> sc_mem_res == NULL ) panic ( " " , device_get_name ( dev ) ) ; ti_prcm_clk_enable ( SDMA_CLK ) ; sc -> sc_hw_rev = ti_sdma_read_4 ( sc , DMA4_REVISION ) ; device_printf ( dev , " \n " , sc -> sc_hw_rev ) ; if ( ! ti_sdma_is_omap4_rev ( sc ) && ! ti_sdma_is_omap3_rev ( sc ) ) { device_printf ( sc -> sc_dev , " \n " ) ; return ( EINVAL ) ; } for ( i = 0 ; i < NUM_DMA_IRQS ; i ++ ) { ti_sdma_write_4 ( sc , DMA4_IRQENABLE_L ( i ) , 0x00000000 ) ; } if ( ti_sdma_is_omap3_rev ( sc ) ) { ti_sdma_write_4 ( sc , DMA4_OCP_SYSCONFIG , 0x0002 ) ; timeout = ( hz < 10 ) ? 1 : ( ( 100 * hz ) / 1000 ) ; while ( ( ti_sdma_read_4 ( sc , DMA4_SYSSTATUS ) & 0x1 ) == 0x0 ) { pause ( " " , 1 ) ; if ( timeout -- == 0 ) { device_printf ( sc -> sc_dev , " \n " ) ; return ( EINVAL ) ; } } } rid = 0 ; sc -> sc_irq_res = bus_alloc_resource_any ( dev , SYS_RES_IRQ , & rid , RF_ACTIVE | RF_SHAREABLE ) ; if ( sc -> sc_irq_res == NULL ) panic ( " \n " ) ; err = bus_setup_intr ( dev , sc -> sc_irq_res , INTR_TYPE_MISC | INTR_MPSAFE , NULL , ti_sdma_intr , NULL , & ihl ) ; if ( err ) panic ( " " , device_get_name ( dev ) ) ; ti_sdma_sc = sc ; return ( 0 ) ; }
ti_sdma_attach - driver attach function
      @dev: dma device handle
ti_sdma_attach - driver attach function @dev : dma device handle
/* Setup the basics */ /* No channels active at the moment */ /* Mutex to protect the shared data structures */ /* Get the memory resource for the register mapping */ /* Enable the interface and functional clocks */ /* Read the sDMA revision register and sanity check it's known */ /* Disable all interrupts */ /* Soft-reset is only supported on pre-OMAP44xx devices */ /* Soft-reset */ /* Set the timeout to 100ms*/ /* Wait for DMA reset to complete */ /* Sleep for a tick */ /* 
	 * Install interrupt handlers for the for possible interrupts. Any channel
	 * can trip one of the four IRQs
	 */ /* Store the DMA structure globally ... this driver should never be unloaded */