KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_pwr_ex.c
/**
  * @brief  Enter a Domain to DSTANDBY mode.
  * @note   The DStandby mode is entered when all PDDS_Dn bits in PWR_CPUCR for the Dn domain
  *         select Standby mode. When the system enters Standby mode, the voltage regulator
  *         is disabled.
  * @note   When D2 or D3 domain is in DStandby mode and the CPU sets the domain PDDS_Dn
  *         bit to select Stop mode, the domain remains in DStandby mode. The domain will only
  *         exit DStandby when the CPU allocates a peripheral in the domain.
  * @note   The system D3 domain enters Standby mode only when the D1 and D2 domain are in
  *         DStandby.
  * @note   Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache function
  *         in order to clean the D-Cache and guarantee the data integrity for the SRAM memories.
  * @param  Domain: Specifies the Domain to enter to STANDBY mode.
  *          This parameter can be one of the following values:
  *            @arg PWR_D1_DOMAIN: Enter D1 Domain to DSTANDBY mode.
  *            @arg PWR_D2_DOMAIN: Enter D2 Domain to DSTANDBY mode.
  *            @arg PWR_D3_DOMAIN: Enter D3 Domain to DSTANDBY mode.
  * @retval None
  */
@brief  Enter a Domain to DSTANDBY mode.
@note   The DStandby mode is entered when all PDDS_Dn bits in PWR_CPUCR for the Dn domain
select Standby mode. When the system enters Standby mode, the voltage regulator
is disabled.
@note   When D2 or D3 domain is in DStandby mode and the CPU sets the domain PDDS_Dn
bit to select Stop mode, the domain remains in DStandby mode. The domain will only
exit DStandby when the CPU allocates a peripheral in the domain.
@note   The system D3 domain enters Standby mode only when the D1 and D2 domain are in
DStandby.
@note   Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache function
in order to clean the D-Cache and guarantee the data integrity for the SRAM memories.
@param  Domain: Specifies the Domain to enter to STANDBY mode.
This parameter can be one of the following values:
@arg PWR_D1_DOMAIN: Enter D1 Domain to DSTANDBY mode.
@arg PWR_D2_DOMAIN: Enter D2 Domain to DSTANDBY mode.
@arg PWR_D3_DOMAIN: Enter D3 Domain to DSTANDBY mode.
@retval None
@brief Enter a Domain to DSTANDBY mode . @note The DStandby mode is entered when all PDDS_Dn bits in PWR_CPUCR for the Dn domain select Standby mode . When the system enters Standby mode the voltage regulator is disabled . @note When D2 or D3 domain is in DStandby mode and the CPU sets the domain PDDS_Dn bit to select Stop mode the domain remains in DStandby mode . The domain will only exit DStandby when the CPU allocates a peripheral in the domain . @note The system D3 domain enters Standby mode only when the D1 and D2 domain are in DStandby . @note Before entering DSTANDBY mode it is recommended to call SCB_CleanDCache function in order to clean the D - Cache and guarantee the data integrity for the SRAM memories . @param Domain : Specifies the Domain to enter to STANDBY mode . This parameter can be one of the following values : @arg PWR_D1_DOMAIN : Enter D1 Domain to DSTANDBY mode . @arg PWR_D2_DOMAIN : Enter D2 Domain to DSTANDBY mode . @arg PWR_D3_DOMAIN : Enter D3 Domain to DSTANDBY mode . @retval None
void HAL_PWREx_EnterSTANDBYMode(uint32_t Domain)
{
  assert_param(IS_PWR_DOMAIN(Domain));
  if (Domain == PWR_D1_DOMAIN)
  {
    SET_BIT(PWR-> CPUCR, PWR_CPUCR_PDDS_D1);
    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
#if defined ( __CC_ARM)
    __force_stores();
#endif
    __WFI();
  }
  else if (Domain == PWR_D2_DOMAIN)
  {
    SET_BIT(PWR-> CPUCR, PWR_CPUCR_PDDS_D2);
  }
  else
  {
    SET_BIT(PWR-> CPUCR, PWR_CPUCR_PDDS_D3);
  }
}
void HAL_PWREx_EnterSTANDBYMode ( uint32_t Domain ) { assert_param ( IS_PWR_DOMAIN ( Domain ) ) ; if ( Domain == PWR_D1_DOMAIN ) { SET_BIT ( PWR -> CPUCR , PWR_CPUCR_PDDS_D1 ) ; SCB -> SCR |= SCB_SCR_SLEEPDEEP_Msk ; #if defined ( __CC_ARM ) __force_stores ( ) ; #endif __WFI ( ) ; } else if ( Domain == PWR_D2_DOMAIN ) { SET_BIT ( PWR -> CPUCR , PWR_CPUCR_PDDS_D2 ) ; } else { SET_BIT ( PWR -> CPUCR , PWR_CPUCR_PDDS_D3 ) ; } }
@brief  Enter a Domain to DSTANDBY mode.
@brief Enter a Domain to DSTANDBY mode .
/* Check the parameters */ /* Select the domain Power Down DeepSleep */ /* Allow DSTANDBY mode when D1 domain enters to Deepsleep */ /* Set SLEEPDEEP bit of Cortex System Control Register */ /* This option is used to ensure that store operations are completed */ /* Request Wait For Interrupt */ /* Allow DSTANDBY mode when D2 domain enters to Deepsleep */ /* Allow DSTANDBY mode when D3 domain enters to Deepsleep */