src/occ_gpe1/gpe1_dimm_read.c
/*
 * Function Specifications:
 *
 * Name: gpe_dimm_sm
 *
 * Description:  DIMM I2C State Machine handler in the GPE
 *
 * Inputs:       cmd is a pointer to IPC msg's cmd and cmd_data struct
 *
 * Outputs:      error: sets rc, address, and ffdc in the cmd_data's
 *                      GpeErrorStruct
 *
 * End Function Specification
 */
Function Specifications:
Name: gpe_dimm_sm

DIMM I2C State Machine handler in the GPE

cmd is a pointer to IPC msg's cmd and cmd_data struct

sets rc, address, and ffdc in the cmd_data's
GpeErrorStruct

End Function Specification
Function Specifications : Name : gpe_dimm_sm DIMM I2C State Machine handler in the GPE cmd is a pointer to IPC msg ' s cmd and cmd_data struct sets rc address and ffdc in the cmd_data ' s GpeErrorStruct End Function Specification
void gpe_dimm_sm(ipc_msg_t* cmd, void* arg)
{
    int      rc;
    ipc_async_cmd_t *async_cmd = (ipc_async_cmd_t*)cmd;
    dimm_sm_args_t *args = (dimm_sm_args_t*)async_cmd->cmd_data;
    args->error.error = 0;
    args->error.ffdc = 0;
     Turn off MCR bit will prevent machine check on error on scom readings (MSR bits 1:7)
       rc == 1 resource occupied  (see ppe42_scom.h)   Action: return with rc
       rc == 2 Core is fenced, offline                 Action: return with rc
       rc == 3 partial good
       rc == 4 address error
       rc == 5 clock error
       rc == 6 packet error
       rc == 7 timeout
     Clear: last SIB rc (SIBRC) and rc accumulator (SIMBRCA)
     Set: SIB Error Mask to prevent machine checks for any rcs
    const uint32_t orig_msr = mfmsr();
    const uint32_t msr = (orig_msr & ~(MSR_SIBRC | MSR_SIBRCA)) | MSR_SEM;
    mtmsr(msr);
    switch(args->state)
    {
        case DIMM_STATE_INIT:
            dimm_write_int_mask(cmd, arg);
            break;
             Read DIMM Temperature States
        case DIMM_STATE_WRITE_MODE:
            dimm_write_mode(cmd, arg);
            break;
        case DIMM_STATE_WRITE_ADDR:
            dimm_write_ts_addr(cmd, arg);
            break;
        case DIMM_STATE_INITIATE_READ:
            dimm_initiate_read(cmd, arg);
            break;
        case DIMM_STATE_READ_TEMP:
            dimm_read_temp(cmd, arg);
            break;
             I2C Reset States
        case DIMM_STATE_RESET_MASTER:
            dimm_reset_master(cmd, arg);
            break;
        case DIMM_STATE_RESET_SLAVE_P0:
        case DIMM_STATE_RESET_SLAVE_P1:
            dimm_reset_slave(cmd, arg);
            break;
        case DIMM_STATE_RESET_SLAVE_P0_COMPLETE:
        case DIMM_STATE_RESET_SLAVE_P1_COMPLETE:
            dimm_reset_slave_status(cmd, arg);
            break;
        default:
            PK_TRACE("gpe_dimm_sm: Invalid state (0x%02X) received!", args->state);
            args->error.rc = 0;
            gpe_set_ffdc(&(args->error), 0, GPE_RC_INVALID_STATE, args->state);
            break;
    }
     Send back IPC response of success (IPC operation itself succeeded)
     (if any operation failed, the error (rc/ffdc) will be non-zero
      and can be handled by the 405)
    rc = ipc_send_rsp(cmd, IPC_RC_SUCCESS);
    if(rc)
    {
        PK_TRACE("gpe_dimm_sm: Failed to send response back. Halting GPE1", rc);
        gpe_set_ffdc(&(args->error), 0x00, GPE_RC_IPC_SEND_FAILED, rc);
        pk_halt();
    }
     Restore original MSR and clear SIBRC and SIBRCA
    mtmsr(orig_msr & ~(MSR_SIBRC | MSR_SIBRCA));
}
void gpe_dimm_sm ( ipc_msg_t * cmd , void * arg ) { int rc ; ipc_async_cmd_t * async_cmd = ( ipc_async_cmd_t * ) cmd ; dimm_sm_args_t * args = ( dimm_sm_args_t * ) async_cmd -> cmd_data ; args -> error . error = 0 ; args -> error . ffdc = 0 ; const uint32_t orig_msr = mfmsr ( ) ; const uint32_t msr = ( orig_msr & ~ ( MSR_SIBRC | MSR_SIBRCA ) ) | MSR_SEM ; mtmsr ( msr ) ; switch ( args -> state ) { case DIMM_STATE_INIT : dimm_write_int_mask ( cmd , arg ) ; break ; case DIMM_STATE_WRITE_MODE : dimm_write_mode ( cmd , arg ) ; break ; case DIMM_STATE_WRITE_ADDR : dimm_write_ts_addr ( cmd , arg ) ; break ; case DIMM_STATE_INITIATE_READ : dimm_initiate_read ( cmd , arg ) ; break ; case DIMM_STATE_READ_TEMP : dimm_read_temp ( cmd , arg ) ; break ; case DIMM_STATE_RESET_MASTER : dimm_reset_master ( cmd , arg ) ; break ; case DIMM_STATE_RESET_SLAVE_P0 : case DIMM_STATE_RESET_SLAVE_P1 : dimm_reset_slave ( cmd , arg ) ; break ; case DIMM_STATE_RESET_SLAVE_P0_COMPLETE : case DIMM_STATE_RESET_SLAVE_P1_COMPLETE : dimm_reset_slave_status ( cmd , arg ) ; break ; default : PK_TRACE ( " " , args -> state ) ; args -> error . rc = 0 ; gpe_set_ffdc ( & ( args -> error ) , 0 , GPE_RC_INVALID_STATE , args -> state ) ; break ; } rc = ipc_send_rsp ( cmd , IPC_RC_SUCCESS ) ; if ( rc ) { PK_TRACE ( " " , rc ) ; gpe_set_ffdc ( & ( args -> error ) , 0x00 , GPE_RC_IPC_SEND_FAILED , rc ) ; pk_halt ( ) ; } mtmsr ( orig_msr & ~ ( MSR_SIBRC | MSR_SIBRCA ) ) ; }
Function Specifications:
 Name: gpe_dimm_sm
Function Specifications : Name : gpe_dimm_sm
// Note: arg was set to 0 in ipc func table (ipc_func_tables.c), so don't use it. // the ipc arguments passed through the ipc_msg_t structure, has a pointer // to the G_gpe_start_pwr_meas_read_args struct. // clear error // Need to mask machine checks for I2C master: // // Turn off MCR bit will prevent machine check on error on scom readings (MSR bits 1:7) //   rc == 1 resource occupied  (see ppe42_scom.h)   Action: return with rc //   rc == 2 Core is fenced, offline                 Action: return with rc //   rc == 3 partial good //   rc == 4 address error //   rc == 5 clock error //   rc == 6 packet error //   rc == 7 timeout // // Clear: last SIB rc (SIBRC) and rc accumulator (SIMBRCA) // Set: SIB Error Mask to prevent machine checks for any rcs // Read DIMM Temperature States // I2C Reset States // Send back IPC response of success (IPC operation itself succeeded) // (if any operation failed, the error (rc/ffdc) will be non-zero //  and can be handled by the 405) // Restore original MSR and clear SIBRC and SIBRCA