FreeBSD/sys/dev/bhnd/bhndb/bhndb_pci.c
/*
 * On devices without a SROM, the PCI(e) cores will be initialized with
 * their Power-on-Reset defaults; this can leave two of the BAR0 PCI windows
 * mapped to the wrong core.
 * 
 * This function updates the SROM shadow to point the BAR0 windows at the
 * current PCI core.
 * 
 * Applies to all PCI/PCIe revisions.
 */
On devices without a SROM, the PCI(e) cores will be initialized with
their Power-on-Reset defaults; this can leave two of the BAR0 PCI windows
mapped to the wrong core.

This function updates the SROM shadow to point the BAR0 windows at the
current PCI core.

Applies to all PCI/PCIe revisions.
On devices without a SROM the PCI ( e ) cores will be initialized with their Power - on - Reset defaults ; this can leave two of the BAR0 PCI windows mapped to the wrong core . This function updates the SROM shadow to point the BAR0 windows at the current PCI core . Applies to all PCI / PCIe revisions .
static void
bhndb_init_sromless_pci_config(struct bhndb_pci_softc *sc)
{
	struct bhndb_resources		*bres;
	const struct bhndb_hwcfg	*cfg;
	const struct bhndb_regwin	*win;
	struct resource			*core_regs;
	bus_size_t			 srom_offset;
	u_int				 pci_cidx, sprom_cidx;
	uint16_t			 val;
	bres = sc->bhndb.bus_res;
	cfg = bres->cfg;
	if (bhnd_get_vendor(sc->bhndb.hostb_dev) != BHND_MFGID_BCM)
		return;
	switch (bhnd_get_device(sc->bhndb.hostb_dev)) {
	case BHND_COREID_PCI:
		srom_offset = BHND_PCI_SRSH_PI_OFFSET;
		break;
	case BHND_COREID_PCIE:
		srom_offset = BHND_PCIE_SRSH_PI_OFFSET;
		break;
	default:
		device_printf(sc->dev, "unsupported PCI host bridge device\n");
		return;
	}
	win = bhndb_regwin_find_core(cfg->register_windows, sc->pci_devclass,
	    0, BHND_PORT_DEVICE, 0, 0);
	if (win == NULL) {
		device_printf(sc->dev, "missing PCI core register window\n");
		return;
	}
	core_regs = bhndb_find_regwin_resource(bres, win);
	if (core_regs == NULL) {
		device_printf(sc->dev, "missing PCI core register resource\n");
		return;
	}
	val = bus_read_2(core_regs, win->win_offset + srom_offset);
	sprom_cidx = (val & BHND_PCI_SRSH_PI_MASK) >> BHND_PCI_SRSH_PI_SHIFT;
	pci_cidx = bhnd_get_core_index(sc->bhndb.hostb_dev);
	if (sprom_cidx != pci_cidx) {
		val &= ~BHND_PCI_SRSH_PI_MASK;
		val |= (pci_cidx << BHND_PCI_SRSH_PI_SHIFT);
		bus_write_2(core_regs,
		    win->win_offset + srom_offset, val);
	}
}
static void bhndb_init_sromless_pci_config ( struct bhndb_pci_softc * sc ) { struct bhndb_resources * bres ; const struct bhndb_hwcfg * cfg ; const struct bhndb_regwin * win ; struct resource * core_regs ; bus_size_t srom_offset ; u_int pci_cidx , sprom_cidx ; uint16_t val ; bres = sc -> bhndb . bus_res ; cfg = bres -> cfg ; if ( bhnd_get_vendor ( sc -> bhndb . hostb_dev ) != BHND_MFGID_BCM ) return ; switch ( bhnd_get_device ( sc -> bhndb . hostb_dev ) ) { case BHND_COREID_PCI : srom_offset = BHND_PCI_SRSH_PI_OFFSET ; break ; case BHND_COREID_PCIE : srom_offset = BHND_PCIE_SRSH_PI_OFFSET ; break ; default : device_printf ( sc -> dev , " \n " ) ; return ; } win = bhndb_regwin_find_core ( cfg -> register_windows , sc -> pci_devclass , 0 , BHND_PORT_DEVICE , 0 , 0 ) ; if ( win == NULL ) { device_printf ( sc -> dev , " \n " ) ; return ; } core_regs = bhndb_find_regwin_resource ( bres , win ) ; if ( core_regs == NULL ) { device_printf ( sc -> dev , " \n " ) ; return ; } val = bus_read_2 ( core_regs , win -> win_offset + srom_offset ) ; sprom_cidx = ( val & BHND_PCI_SRSH_PI_MASK ) >> BHND_PCI_SRSH_PI_SHIFT ; pci_cidx = bhnd_get_core_index ( sc -> bhndb . hostb_dev ) ; if ( sprom_cidx != pci_cidx ) { val &= ~ BHND_PCI_SRSH_PI_MASK ; val |= ( pci_cidx << BHND_PCI_SRSH_PI_SHIFT ) ; bus_write_2 ( core_regs , win -> win_offset + srom_offset , val ) ; } }
On devices without a SROM, the PCI(e) cores will be initialized with
 their Power-on-Reset defaults; this can leave two of the BAR0 PCI windows
 mapped to the wrong core.
On devices without a SROM the PCI ( e ) cores will be initialized with their Power - on - Reset defaults ; this can leave two of the BAR0 PCI windows mapped to the wrong core .
/* Locate the static register window mapping the PCI core */ /* Fetch the resource containing the register window */ /* Fetch the SPROM's configured core index */ /* If it doesn't match host bridge's core index, update the index
	 * value */