Platform/ECM3532/DSP/hw/csp/ecm3532/src/eta_csp_i2c.c
/***************************************************************************/
/**
 *
 * EtaCspI2cSpeedConfig - Configure the speed for the I2C module.
 *
 * @param iClockSpeed is the I2C clock speed
 * @param iSrcClockSpeed is the source clock speed
 *
 * > To set an I2C speed greater than 100kHz source clock speed
 *   has to be 4MHz or greater.
 *
 * @return Returns the status.
 *
 ******************************************************************************/
Configure the speed for the I2C module.
@param iClockSpeed is the I2C clock speed
@param iSrcClockSpeed is the source clock speed

> To set an I2C speed greater than 100kHz source clock speed
has to be 4MHz or greater.

@return Returns the status.
Configure the speed for the I2C module . @param iClockSpeed is the I2C clock speed @param iSrcClockSpeed is the source clock speed > To set an I2C speed greater than 100kHz source clock speed has to be 4MHz or greater . @return Returns the status .
tEtaStatus
EtaCspI2cSpeedConfig(tI2cClk iClockSpeed, tI2cSrcClk iSrcClockSpeed)
{
    char CYCLE_TIME;
    char IBG_TIME;
    char PE_TIME;
    char NE_TIME;
    char TX_TIME;
    char RX_TIME;
    char MIN_SCL_HI;
    char SCL_HYSTERSIS_LEVEL;
    char SDA_HYSTERSIS_LEVEL;
    char TEMP_TIME;
     If source clock is less than 4MHz, then I2C speeds greater than 100kHz
     are not allowed.
    if((iSrcClockSpeed < 4000) && (iClockSpeed > 100))
    {
        return eEtaI2cInvalidConfig;
    }
     Use algorithm for lower speed interfaces.
    if(iClockSpeed < 500)
    {
        CYCLE_TIME = (iSrcClockSpeed / iClockSpeed) - 1;  4MHz source clock.
        IBG_TIME = CYCLE_TIME;
        TEMP_TIME = ((400 - iClockSpeed) / 3);
        PE_TIME = 4 + ((TEMP_TIME * (16 - 4))) / 100;
        NE_TIME = 8 + ((TEMP_TIME * (31 - 8))) / 100;
        RX_TIME = 5 + ((TEMP_TIME * (25 - 5))) / 100;
        TX_TIME = 1 + ((TEMP_TIME * (1  - 1))) / 100;
        MIN_SCL_HI = 0 + ((TEMP_TIME * (4 - 0))) / 100;
        SCL_HYSTERSIS_LEVEL = 1 + ((TEMP_TIME * (8 - 1))) / 100;
        SDA_HYSTERSIS_LEVEL = 1 + ((TEMP_TIME * (8 - 1))) / 100;
        if(iSrcClockSpeed==eI2cSrcClk2MHz)
        {
            PE_TIME = (PE_TIME - 1) / 2;
            NE_TIME = (NE_TIME - 1) / 2;
            RX_TIME = (RX_TIME - 1) / 2;
            TX_TIME = (TX_TIME - 1) / 2;
            MIN_SCL_HI = (MIN_SCL_HI - 1) / 2;
            SCL_HYSTERSIS_LEVEL = (SCL_HYSTERSIS_LEVEL - 1) / 2;
            SDA_HYSTERSIS_LEVEL = (SDA_HYSTERSIS_LEVEL - 1) / 2;
        }
        if(iSrcClockSpeed==eI2cSrcClk8MHz)
        {
            PE_TIME = (PE_TIME * 2) + 1;
            NE_TIME = (NE_TIME * 2) + 1;
            RX_TIME = (RX_TIME * 2) + 1;
            TX_TIME = (TX_TIME * 2) + 1;
            MIN_SCL_HI = (MIN_SCL_HI * 2) + 1;
            SCL_HYSTERSIS_LEVEL = (SCL_HYSTERSIS_LEVEL * 2) + 1;
            SDA_HYSTERSIS_LEVEL = (SDA_HYSTERSIS_LEVEL * 2) + 1;
        }
    }
     If (iClockSpeed >= 500) Use prerecorded values.
    else
    {
        CYCLE_TIME = 3;
        IBG_TIME = CYCLE_TIME;
        PE_TIME = 1;
        NE_TIME = 2;
        RX_TIME = 3;
        TX_TIME = 0;
        MIN_SCL_HI = 0;
         Disable Hysteresis.
        SCL_HYSTERSIS_LEVEL = 0;
        SDA_HYSTERSIS_LEVEL = 0;
        if(iSrcClockSpeed==eI2cSrcClk8MHz)
        {
            CYCLE_TIME = (CYCLE_TIME * 2) + 1;
            IBG_TIME = (IBG_TIME * 2) + 1;
            PE_TIME = (PE_TIME * 2) + 1;
            NE_TIME = (NE_TIME * 2) + 1;
            RX_TIME = (RX_TIME * 2) - 1;
            TX_TIME = (TX_TIME * 2) + 1;
            MIN_SCL_HI = (MIN_SCL_HI * 2) + 1;
            SCL_HYSTERSIS_LEVEL = 1;
            SDA_HYSTERSIS_LEVEL = 1;
        }
    }
    REG_I2C2_CLK_CONFIG1 = (IBG_TIME << BP_I2C2_CLK_CONFIG1_IBG_TIME) |
                           (CYCLE_TIME << BP_I2C2_CLK_CONFIG1_CYCLE_TIME);
    REG_I2C2_CLK_CONFIG2 = (TX_TIME << BP_I2C2_CLK_CONFIG2_TX_TIME) |
                           (RX_TIME << BP_I2C2_CLK_CONFIG2_RX_TIME);
    REG_I2C2_CLK_CONFIG3 = (PE_TIME << BP_I2C2_CLK_CONFIG3_PE_TIME) |
                           (NE_TIME << BP_I2C2_CLK_CONFIG3_NE_TIME);
    REG_I2C2_SCL_CONFIG = (MIN_SCL_HI << BP_I2C2_SCL_CONFIG_MIN_SCL_HIGH);
     Enable hysteresis.
    if(SCL_HYSTERSIS_LEVEL > 0)
    {
        REG_I2C2_CONFIG2 =
            (REG_I2C2_CONFIG2 & (~BM_I2C2_CONFIG2_SCL_HYSTERISIS_LEVEL)) |
            ((16 - SCL_HYSTERSIS_LEVEL) <<
                BP_I2C2_CONFIG2_SCL_HYSTERISIS_LEVEL);
        REG_I2C2_CONFIG2 =
            (REG_I2C2_CONFIG2 & (~BM_I2C2_CONFIG2_DISABLE_SCL_HYSTERSIS));
    }
    else
    {
        REG_I2C2_CONFIG2 =
            (REG_I2C2_CONFIG2 & (~BM_I2C2_CONFIG2_DISABLE_SCL_HYSTERSIS)) |
            (1 << BP_I2C2_CONFIG2_DISABLE_SCL_HYSTERSIS);
    }
     Enable hysteresis.
    if(SDA_HYSTERSIS_LEVEL > 0)
    {
        REG_I2C2_CONFIG2 =
            (REG_I2C2_CONFIG2 & (~BM_I2C2_CONFIG2_SDA_HYSTERISIS_LEVEL)) |
            ((16 - SDA_HYSTERSIS_LEVEL) <<
                BP_I2C2_CONFIG2_SDA_HYSTERISIS_LEVEL);
        REG_I2C2_CONFIG2 =
            (REG_I2C2_CONFIG2 & (~BM_I2C2_CONFIG2_DISABLE_SDA_HYSTERSIS));
    }
    else
    {
        REG_I2C2_CONFIG2 =
            (REG_I2C2_CONFIG2 & (~BM_I2C2_CONFIG2_DISABLE_SDA_HYSTERSIS)) |
            (1 << BP_I2C2_CONFIG2_DISABLE_SDA_HYSTERSIS);
    }
    return(eEtaSuccess);
}
tEtaStatus EtaCspI2cSpeedConfig ( tI2cClk iClockSpeed , tI2cSrcClk iSrcClockSpeed ) { char CYCLE_TIME ; char IBG_TIME ; char PE_TIME ; char NE_TIME ; char TX_TIME ; char RX_TIME ; char MIN_SCL_HI ; char SCL_HYSTERSIS_LEVEL ; char SDA_HYSTERSIS_LEVEL ; char TEMP_TIME ; if ( ( iSrcClockSpeed < 4000 ) && ( iClockSpeed > 100 ) ) { return eEtaI2cInvalidConfig ; } if ( iClockSpeed < 500 ) { CYCLE_TIME = ( iSrcClockSpeed / iClockSpeed ) - 1 ; IBG_TIME = CYCLE_TIME ; TEMP_TIME = ( ( 400 - iClockSpeed ) / 3 ) ; PE_TIME = 4 + ( ( TEMP_TIME * ( 16 - 4 ) ) ) / 100 ; NE_TIME = 8 + ( ( TEMP_TIME * ( 31 - 8 ) ) ) / 100 ; RX_TIME = 5 + ( ( TEMP_TIME * ( 25 - 5 ) ) ) / 100 ; TX_TIME = 1 + ( ( TEMP_TIME * ( 1 - 1 ) ) ) / 100 ; MIN_SCL_HI = 0 + ( ( TEMP_TIME * ( 4 - 0 ) ) ) / 100 ; SCL_HYSTERSIS_LEVEL = 1 + ( ( TEMP_TIME * ( 8 - 1 ) ) ) / 100 ; SDA_HYSTERSIS_LEVEL = 1 + ( ( TEMP_TIME * ( 8 - 1 ) ) ) / 100 ; if ( iSrcClockSpeed == eI2cSrcClk2MHz ) { PE_TIME = ( PE_TIME - 1 ) / 2 ; NE_TIME = ( NE_TIME - 1 ) / 2 ; RX_TIME = ( RX_TIME - 1 ) / 2 ; MIN_SCL_HI = ( MIN_SCL_HI - 1 ) / 2 ; SCL_HYSTERSIS_LEVEL = ( SCL_HYSTERSIS_LEVEL - 1 ) / 2 ; SDA_HYSTERSIS_LEVEL = ( SDA_HYSTERSIS_LEVEL - 1 ) / 2 ; } if ( iSrcClockSpeed == eI2cSrcClk8MHz ) { PE_TIME = ( PE_TIME * 2 ) + 1 ; NE_TIME = ( NE_TIME * 2 ) + 1 ; RX_TIME = ( RX_TIME * 2 ) + 1 ; TX_TIME = ( TX_TIME * 2 ) + 1 ; MIN_SCL_HI = ( MIN_SCL_HI * 2 ) + 1 ; SCL_HYSTERSIS_LEVEL = ( SCL_HYSTERSIS_LEVEL * 2 ) + 1 ; SDA_HYSTERSIS_LEVEL = ( SDA_HYSTERSIS_LEVEL * 2 ) + 1 ; } } else { CYCLE_TIME = 3 ; IBG_TIME = CYCLE_TIME ; PE_TIME = 1 ; NE_TIME = 2 ; RX_TIME = 3 ; TX_TIME = 0 ; MIN_SCL_HI = 0 ; SCL_HYSTERSIS_LEVEL = 0 ; SDA_HYSTERSIS_LEVEL = 0 ; if ( iSrcClockSpeed == eI2cSrcClk8MHz ) { CYCLE_TIME = ( CYCLE_TIME * 2 ) + 1 ; IBG_TIME = ( IBG_TIME * 2 ) + 1 ; PE_TIME = ( PE_TIME * 2 ) + 1 ; NE_TIME = ( NE_TIME * 2 ) + 1 ; RX_TIME = ( RX_TIME * 2 ) - 1 ; TX_TIME = ( TX_TIME * 2 ) + 1 ; MIN_SCL_HI = ( MIN_SCL_HI * 2 ) + 1 ; SCL_HYSTERSIS_LEVEL = 1 ; SDA_HYSTERSIS_LEVEL = 1 ; } } REG_I2C2_CLK_CONFIG1 = ( IBG_TIME << BP_I2C2_CLK_CONFIG1_IBG_TIME ) | ( CYCLE_TIME << BP_I2C2_CLK_CONFIG1_CYCLE_TIME ) ; REG_I2C2_CLK_CONFIG2 = ( TX_TIME << BP_I2C2_CLK_CONFIG2_TX_TIME ) | ( RX_TIME << BP_I2C2_CLK_CONFIG2_RX_TIME ) ; REG_I2C2_CLK_CONFIG3 = ( PE_TIME << BP_I2C2_CLK_CONFIG3_PE_TIME ) | ( NE_TIME << BP_I2C2_CLK_CONFIG3_NE_TIME ) ; REG_I2C2_SCL_CONFIG = ( MIN_SCL_HI << BP_I2C2_SCL_CONFIG_MIN_SCL_HIGH ) ; if ( SCL_HYSTERSIS_LEVEL > 0 ) { REG_I2C2_CONFIG2 = ( REG_I2C2_CONFIG2 & ( ~ BM_I2C2_CONFIG2_SCL_HYSTERISIS_LEVEL ) ) | ( ( 16 - SCL_HYSTERSIS_LEVEL ) << BP_I2C2_CONFIG2_SCL_HYSTERISIS_LEVEL ) ; REG_I2C2_CONFIG2 = ( REG_I2C2_CONFIG2 & ( ~ BM_I2C2_CONFIG2_DISABLE_SCL_HYSTERSIS ) ) ; } else { REG_I2C2_CONFIG2 = ( REG_I2C2_CONFIG2 & ( ~ BM_I2C2_CONFIG2_DISABLE_SCL_HYSTERSIS ) ) | ( 1 << BP_I2C2_CONFIG2_DISABLE_SCL_HYSTERSIS ) ; } if ( SDA_HYSTERSIS_LEVEL > 0 ) { REG_I2C2_CONFIG2 = ( REG_I2C2_CONFIG2 & ( ~ BM_I2C2_CONFIG2_SDA_HYSTERISIS_LEVEL ) ) | ( ( 16 - SDA_HYSTERSIS_LEVEL ) << BP_I2C2_CONFIG2_SDA_HYSTERISIS_LEVEL ) ; REG_I2C2_CONFIG2 = ( REG_I2C2_CONFIG2 & ( ~ BM_I2C2_CONFIG2_DISABLE_SDA_HYSTERSIS ) ) ; } else { REG_I2C2_CONFIG2 = ( REG_I2C2_CONFIG2 & ( ~ BM_I2C2_CONFIG2_DISABLE_SDA_HYSTERSIS ) ) | ( 1 << BP_I2C2_CONFIG2_DISABLE_SDA_HYSTERSIS ) ; } return ( eEtaSuccess ) ; }
EtaCspI2cSpeedConfig - Configure the speed for the I2C module.
EtaCspI2cSpeedConfig - Configure the speed for the I2C module .
// // If source clock is less than 4MHz, then I2C speeds greater than 100kHz // are not allowed. // // // Use algorithm for lower speed interfaces. // // 4MHz source clock. //TX_TIME = (TX_TIME - 1) / 2; // // If (iClockSpeed >= 500) Use prerecorded values. // // // Disable Hysteresis. // // // Enable hysteresis. // // // Enable hysteresis. //