src/occ_405/gpu/gpu.c
// Function Specification
//
// Name:  gpu_read_mem_temp_capability_sm
//
// Description: Called from gpu_task_sm to read GPU memory temp capability of G_current_gpu_id
//              This function should only return that complete is TRUE when the capability
//              read is complete (or determined failed) and ready to start reading a different GPU
//
// Pre-Req:  Caller must have G_current_gpu_id set for GPU to read
//
// End Function Specification
Function Specification
Name:  gpu_read_mem_temp_capability_sm

Called from gpu_task_sm to read GPU memory temp capability of G_current_gpu_id
This function should only return that complete is TRUE when the capability
read is complete (or determined failed) and ready to start reading a different GPU

Pre-Req:  Caller must have G_current_gpu_id set for GPU to read

End Function Specification
Function Specification Name : gpu_read_mem_temp_capability_sm Called from gpu_task_sm to read GPU memory temp capability of G_current_gpu_id This function should only return that complete is TRUE when the capability read is complete ( or determined failed ) and ready to start reading a different GPU Pre - Req : Caller must have G_current_gpu_id set for GPU to read End Function Specification
bool gpu_read_mem_temp_capability_sm()
{
    bool l_complete = FALSE;   
    static bool L_scheduled = FALSE;  
    static uint8_t L_read_mem_cap_failure_count[MAX_NUM_GPU_PER_DOMAIN] = {0};
    static uint8_t L_state_failure_count = 0;
    static gpuReadMemTempCapableState_e L_read_cap_state = GPU_STATE_READ_MEM_TEMP_CAPABLE_NEW;
    static bool L_error_logged[MAX_NUM_GPU_PER_DOMAIN] = {FALSE};
    static uint32_t L_num_ticks = 0;
    L_num_ticks++;
    if (async_request_is_idle(&G_gpu_op_request.request))
    {
       if( (L_read_cap_state != GPU_STATE_READ_MEM_TEMP_CAPABLE_NEW) &&
           (!L_scheduled || (GPE_RC_SUCCESS != G_gpu_op_req_args.error.rc)) )
       {
          if(G_gpu_op_req_args.error.rc == GPE_RC_GPU_DRIVER_CHANGE)
          {
             handle_driver_change();
             L_state_failure_count = 0;
             L_read_mem_cap_failure_count[G_current_gpu_id] = 0; 
             L_read_cap_state = GPU_STATE_READ_MEM_TEMP_CAPABLE_NEW;
             return TRUE;  
          }
          else if(L_state_failure_count > MAX_GPU_READ_ATTEMPT)
          {
             if(g_amec->gpu[G_current_gpu_id].status.notReset)
             {
                if(++L_read_mem_cap_failure_count[G_current_gpu_id] > GPU_READ_MEM_CAP_ERROR_COUNT)
                {
                    INTR_TRAC_ERR("gpu_read_mem_temp_capable: Failed to read capability for GPU%d RC: 0x%02X",
                                   G_current_gpu_id,
                                   G_gpu_op_req_args.gpu_rc);
                    g_amec->gpu[G_current_gpu_id].status.checkMemTempSupport = FALSE;
                    L_read_mem_cap_failure_count[G_current_gpu_id] = 0;
                    g_amec->gpu[G_current_gpu_id].status.memTempFailure = true;
                    g_amec->gpu[G_current_gpu_id].status.memTempNotAvailable = true;
                    if(!L_error_logged[G_current_gpu_id])
                    {
                       L_error_logged[G_current_gpu_id] = TRUE;
                       errlHndl_t l_err = createErrl(GPU_MID_GPU_READ_MEM_TEMP_CAPABLE,
                                                     GPU_FAILURE,
                                                     ERC_GPU_READ_MEM_TEMP_CAPABLE_FAILURE,
                                                     ERRL_SEV_PREDICTIVE,
                                                     NULL,
                                                     DEFAULT_TRACE_SIZE,
                                                     G_current_gpu_id,
                                                     G_gpu_op_req_args.gpu_rc);
                       if(G_sysConfigData.gpu_sensor_ids[G_current_gpu_id])
                       {
                          addCalloutToErrl(l_err,
                                           ERRL_CALLOUT_TYPE_GPU_ID,
                                           G_sysConfigData.gpu_sensor_ids[G_current_gpu_id],
                                           ERRL_CALLOUT_PRIORITY_MED);
                       }
                       commitErrl(&l_err);
                    } 
                } 
             } 
             L_read_cap_state = GPU_STATE_READ_MEM_TEMP_CAPABLE_NEW;
             L_state_failure_count = 0;
             return TRUE;  
          } 
          else
          {
             L_state_failure_count++;
          }
       }
       else 
       {
          L_state_failure_count = 0;
          L_read_cap_state++;
       }
       L_scheduled = FALSE;  
       switch (L_read_cap_state)
       {
           case GPU_STATE_READ_MEM_TEMP_CAPABLE_START:
               L_num_ticks = 1;
               L_scheduled = schedule_gpu_req(GPU_REQ_READ_CAPS_START, G_new_gpu_req_args);
               break;
           case GPU_STATE_READ_MEM_TEMP_CAPABLE_2:
               L_scheduled = schedule_gpu_req(GPU_REQ_READ_CAPS_2, G_new_gpu_req_args);
               break;
           case GPU_STATE_READ_MEM_TEMP_CAPABLE_3:
               L_scheduled = schedule_gpu_req(GPU_REQ_READ_CAPS_3, G_new_gpu_req_args);
               break;
           case GPU_STATE_READ_MEM_TEMP_CAPABLE_READ:
               L_scheduled = schedule_gpu_req(GPU_REQ_READ_CAPS_FINISH, G_new_gpu_req_args);
               break;
           case GPU_STATE_READ_MEM_TEMP_CAPABLE_COMPLETE:
               update_gpu_tick_sensor(&G_gpu_tick_times.capabilities[G_current_gpu_id], L_num_ticks);
               g_amec->gpu[G_current_gpu_id].status.memTempSupported = G_gpu_op_req_args.data[0] & 0x01;
               if(g_amec->gpu[G_current_gpu_id].status.memTempSupported)
               {
                  g_amec->gpu[G_current_gpu_id].status.checkMemTempSupport = FALSE;
               }
               else
               {
                  g_amec->gpu[G_current_gpu_id].status.checkMemTempSupport = TRUE;
               }
               L_read_mem_cap_failure_count[G_current_gpu_id] = 0;
               L_read_cap_state = GPU_STATE_READ_MEM_TEMP_CAPABLE_NEW;
               l_complete = TRUE;
               break;
           default:
               INTR_TRAC_ERR("gpu_read_mem_temp_capable: INVALID STATE: 0x%02X", L_read_cap_state);
               L_read_cap_state = GPU_STATE_READ_MEM_TEMP_CAPABLE_NEW;
               l_complete = TRUE;
               break;
       } 
       if(L_scheduled)
       {
          GPU_DBG("gpu_read_mem_temp_capable: Scheduled read temp capability state 0x%02X at tick %d",
                   L_read_cap_state, GPU_TICK);
       }
       else if(!l_complete)  
       {
          INTR_TRAC_ERR("gpu_read_mem_temp_capable: failed to schedule state 0x%02X", L_read_cap_state);
       }
    } 
    else
    {
       INTR_TRAC_ERR("gpu_read_mem_temp_capable: NOT idle for state 0x%02X", L_read_cap_state);
    }
    return l_complete;
}
bool gpu_read_mem_temp_capability_sm ( ) { bool l_complete = FALSE ; static bool L_scheduled = FALSE ; static uint8_t L_read_mem_cap_failure_count [ MAX_NUM_GPU_PER_DOMAIN ] = { 0 } ; static uint8_t L_state_failure_count = 0 ; static gpuReadMemTempCapableState_e L_read_cap_state = GPU_STATE_READ_MEM_TEMP_CAPABLE_NEW ; static bool L_error_logged [ MAX_NUM_GPU_PER_DOMAIN ] = { FALSE } ; static uint32_t L_num_ticks = 0 ; L_num_ticks ++ ; if ( async_request_is_idle ( & G_gpu_op_request . request ) ) { if ( ( L_read_cap_state != GPU_STATE_READ_MEM_TEMP_CAPABLE_NEW ) && ( ! L_scheduled || ( GPE_RC_SUCCESS != G_gpu_op_req_args . error . rc ) ) ) { if ( G_gpu_op_req_args . error . rc == GPE_RC_GPU_DRIVER_CHANGE ) { handle_driver_change ( ) ; L_state_failure_count = 0 ; L_read_mem_cap_failure_count [ G_current_gpu_id ] = 0 ; L_read_cap_state = GPU_STATE_READ_MEM_TEMP_CAPABLE_NEW ; return TRUE ; } else if ( L_state_failure_count > MAX_GPU_READ_ATTEMPT ) { if ( g_amec -> gpu [ G_current_gpu_id ] . status . notReset ) { if ( ++ L_read_mem_cap_failure_count [ G_current_gpu_id ] > GPU_READ_MEM_CAP_ERROR_COUNT ) { INTR_TRAC_ERR ( " " , G_current_gpu_id , G_gpu_op_req_args . gpu_rc ) ; g_amec -> gpu [ G_current_gpu_id ] . status . checkMemTempSupport = FALSE ; L_read_mem_cap_failure_count [ G_current_gpu_id ] = 0 ; g_amec -> gpu [ G_current_gpu_id ] . status . memTempFailure = true ; g_amec -> gpu [ G_current_gpu_id ] . status . memTempNotAvailable = true ; if ( ! L_error_logged [ G_current_gpu_id ] ) { L_error_logged [ G_current_gpu_id ] = TRUE ; errlHndl_t l_err = createErrl ( GPU_MID_GPU_READ_MEM_TEMP_CAPABLE , GPU_FAILURE , ERC_GPU_READ_MEM_TEMP_CAPABLE_FAILURE , ERRL_SEV_PREDICTIVE , NULL , DEFAULT_TRACE_SIZE , G_current_gpu_id , G_gpu_op_req_args . gpu_rc ) ; if ( G_sysConfigData . gpu_sensor_ids [ G_current_gpu_id ] ) { addCalloutToErrl ( l_err , ERRL_CALLOUT_TYPE_GPU_ID , G_sysConfigData . gpu_sensor_ids [ G_current_gpu_id ] , ERRL_CALLOUT_PRIORITY_MED ) ; } commitErrl ( & l_err ) ; } } } L_read_cap_state = GPU_STATE_READ_MEM_TEMP_CAPABLE_NEW ; L_state_failure_count = 0 ; return TRUE ; } else { L_state_failure_count ++ ; } } else { L_state_failure_count = 0 ; L_read_cap_state ++ ; } L_scheduled = FALSE ; switch ( L_read_cap_state ) { case GPU_STATE_READ_MEM_TEMP_CAPABLE_START : L_num_ticks = 1 ; L_scheduled = schedule_gpu_req ( GPU_REQ_READ_CAPS_START , G_new_gpu_req_args ) ; break ; case GPU_STATE_READ_MEM_TEMP_CAPABLE_2 : L_scheduled = schedule_gpu_req ( GPU_REQ_READ_CAPS_2 , G_new_gpu_req_args ) ; break ; case GPU_STATE_READ_MEM_TEMP_CAPABLE_3 : L_scheduled = schedule_gpu_req ( GPU_REQ_READ_CAPS_3 , G_new_gpu_req_args ) ; break ; case GPU_STATE_READ_MEM_TEMP_CAPABLE_READ : L_scheduled = schedule_gpu_req ( GPU_REQ_READ_CAPS_FINISH , G_new_gpu_req_args ) ; break ; case GPU_STATE_READ_MEM_TEMP_CAPABLE_COMPLETE : update_gpu_tick_sensor ( & G_gpu_tick_times . capabilities [ G_current_gpu_id ] , L_num_ticks ) ; g_amec -> gpu [ G_current_gpu_id ] . status . memTempSupported = G_gpu_op_req_args . data [ 0 ] & 0x01 ; if ( g_amec -> gpu [ G_current_gpu_id ] . status . memTempSupported ) { g_amec -> gpu [ G_current_gpu_id ] . status . checkMemTempSupport = FALSE ; } else { g_amec -> gpu [ G_current_gpu_id ] . status . checkMemTempSupport = TRUE ; } L_read_mem_cap_failure_count [ G_current_gpu_id ] = 0 ; L_read_cap_state = GPU_STATE_READ_MEM_TEMP_CAPABLE_NEW ; l_complete = TRUE ; break ; default : INTR_TRAC_ERR ( " " , L_read_cap_state ) ; L_read_cap_state = GPU_STATE_READ_MEM_TEMP_CAPABLE_NEW ; l_complete = TRUE ; break ; } if ( L_scheduled ) { GPU_DBG ( " " , L_read_cap_state , GPU_TICK ) ; } else if ( ! l_complete ) { INTR_TRAC_ERR ( " " , L_read_cap_state ) ; } } else { INTR_TRAC_ERR ( " " , L_read_cap_state ) ; } return l_complete ; }
Function Specification
Name:  gpu_read_mem_temp_capability_sm
Function Specification Name : gpu_read_mem_temp_capability_sm
// only return TRUE when the read is complete or failed // indicates if a GPU GPE request was scheduled // If not starting a new read then need to check status of current state before moving on // stay in current state if the schedule failed or the state isn't finished/failed // Check if failure was due to driver change // Request can't be processed by GPU at this time so we are done with this GPU // setup to start new request // clear failure count since there's a driver change // Done with this GPU, let GPU SM move to next // If reached state retry count give up on this read // if GPU is not in reset then INC error count and check if reached threshold // give up trying to read mem temp capability for this GPU // It will be retried if detected that GPU driver is re-loaded // cannot determine memory temp capability, mark memory temp as failed // log one time error that memory temp capability couldn't be determined // Log error /* @
                        * @errortype
                        * @moduleid    GPU_MID_GPU_READ_MEM_TEMP_CAPABLE
                        * @reasoncode  GPU_FAILURE
                        * @userdata1   GPU ID
                        * @userdata2   GPU RC
                        * @userdata4   ERC_GPU_READ_MEM_TEMP_CAPABLE_FAILURE
                        * @devdesc     Failure to read memory temp capability
                        *
                        */ // Callout the GPU if have sensor ID for it // Commit Error // if error not logged // if reached error count // if notReset // Done with this GPU, let GPU SM move to next // if reached state retry count // INC failure count and retry current state // success on last state go to next state and process it // default nothing scheduled // Update capability // mem temp is supported no need to re-check capability // Need to keep query for mem temp capability to detect if ever changes to capable // Done with this GPU ready to move to new one // switch L_read_cap_state // if not complete there must have been a failure on the schedule // if async_request_is_idle