src/ssx/occhw/occhw_ocb.c
// The interrupt is generated by causing a 0->1 transation on
// OCB_OCCMISC.core_ext_intr. This is implemented here using the WAND/WOR
// forms of the register.
The interrupt is generated by causing a 0->1 transation on
OCB_OCCMISC.core_ext_intr. This is implemented here using the WAND/WOR
forms of the register.
The interrupt is generated by causing a 0 - > 1 transation on OCB_OCCMISC . core_ext_intr . This is implemented here using the WAND / WOR forms of the register .
int
ocb_core_interrupt()
{
    ocb_occmisc_t oo;
    oo.value = 0;
    oo.fields.core_ext_intr = 1;
    out32(OCB_OCCMISC_CLR, oo.value);
    out32(OCB_OCCMISC_OR, oo.value);
    return 0;
}
int ocb_core_interrupt ( ) { ocb_occmisc_t oo ; oo . value = 0 ; oo . fields . core_ext_intr = 1 ; out32 ( OCB_OCCMISC_CLR , oo . value ) ; out32 ( OCB_OCCMISC_OR , oo . value ) ; return 0 ; }
The interrupt is generated by causing a 0->1 transation on
OCB_OCCMISC.core_ext_intr.
The interrupt is generated by causing a 0 - > 1 transation on OCB_OCCMISC . core_ext_intr .