FreeBSD/sys/dev/otus/if_otus.c
/*
 * Update PHY's programming based on vendor-specific data stored in EEPROM.
 * This is for FEM-type devices only.
 */
Update PHY's programming based on vendor-specific data stored in EEPROM.
This is for FEM-type devices only.
Update PHY ' s programming based on vendor - specific data stored in EEPROM . This is for FEM - type devices only .
int
otus_set_board_values(struct otus_softc *sc, struct ieee80211_channel *c)
{
	const struct ModalEepHeader *eep;
	uint32_t tmp, offset;
	if (IEEE80211_IS_CHAN_5GHZ(c))
		eep = &sc->eeprom.modalHeader[0];
	else
		eep = &sc->eeprom.modalHeader[1];
	offset = 2 * 0x1000;
	tmp = le32toh(eep->antCtrlCommon);
	otus_write(sc, AR_PHY_SWITCH_COM, tmp);
	tmp = le32toh(eep->antCtrlChain[0]);
	otus_write(sc, AR_PHY_SWITCH_CHAIN_0, tmp);
	tmp = le32toh(eep->antCtrlChain[1]);
	otus_write(sc, AR_PHY_SWITCH_CHAIN_0 + offset, tmp);
	if (1 ) {
		tmp = otus_phy_get_def(sc, AR_PHY_SETTLING);
		tmp &= ~(0x7f << 7);
		tmp |= (eep->switchSettling & 0x7f) << 7;
		otus_write(sc, AR_PHY_SETTLING, tmp);
	}
	tmp = otus_phy_get_def(sc, AR_PHY_DESIRED_SZ);
	tmp &= ~0xffff;
	tmp |= eep->pgaDesiredSize << 8 | eep->adcDesiredSize;
	otus_write(sc, AR_PHY_DESIRED_SZ, tmp);
	tmp = eep->txEndToXpaOff << 24 | eep->txEndToXpaOff << 16 |
	      eep->txFrameToXpaOn << 8 | eep->txFrameToXpaOn;
	otus_write(sc, AR_PHY_RF_CTL4, tmp);
	tmp = otus_phy_get_def(sc, AR_PHY_RF_CTL3);
	tmp &= ~(0xff << 16);
	tmp |= eep->txEndToRxOn << 16;
	otus_write(sc, AR_PHY_RF_CTL3, tmp);
	tmp = otus_phy_get_def(sc, AR_PHY_CCA);
	tmp &= ~(0x7f << 12);
	tmp |= (eep->thresh62 & 0x7f) << 12;
	otus_write(sc, AR_PHY_CCA, tmp);
	tmp = otus_phy_get_def(sc, AR_PHY_RXGAIN);
	tmp &= ~(0x3f << 12);
	tmp |= (eep->txRxAttenCh[0] & 0x3f) << 12;
	otus_write(sc, AR_PHY_RXGAIN, tmp);
	tmp = otus_phy_get_def(sc, AR_PHY_RXGAIN + offset);
	tmp &= ~(0x3f << 12);
	tmp |= (eep->txRxAttenCh[1] & 0x3f) << 12;
	otus_write(sc, AR_PHY_RXGAIN + offset, tmp);
	tmp = otus_phy_get_def(sc, AR_PHY_GAIN_2GHZ);
	tmp &= ~(0x3f << 18);
	tmp |= (eep->rxTxMarginCh[0] & 0x3f) << 18;
	if (IEEE80211_IS_CHAN_5GHZ(c)) {
		tmp &= ~(0xf << 10);
		tmp |= (eep->bswMargin[0] & 0xf) << 10;
	}
	otus_write(sc, AR_PHY_GAIN_2GHZ, tmp);
	tmp = otus_phy_get_def(sc, AR_PHY_GAIN_2GHZ + offset);
	tmp &= ~(0x3f << 18);
	tmp |= (eep->rxTxMarginCh[1] & 0x3f) << 18;
	otus_write(sc, AR_PHY_GAIN_2GHZ + offset, tmp);
	tmp = otus_phy_get_def(sc, AR_PHY_TIMING_CTRL4);
	tmp &= ~(0x3f << 5 | 0x1f);
	tmp |= (eep->iqCalICh[0] & 0x3f) << 5 | (eep->iqCalQCh[0] & 0x1f);
	otus_write(sc, AR_PHY_TIMING_CTRL4, tmp);
	tmp = otus_phy_get_def(sc, AR_PHY_TIMING_CTRL4 + offset);
	tmp &= ~(0x3f << 5 | 0x1f);
	tmp |= (eep->iqCalICh[1] & 0x3f) << 5 | (eep->iqCalQCh[1] & 0x1f);
	otus_write(sc, AR_PHY_TIMING_CTRL4 + offset, tmp);
	tmp = otus_phy_get_def(sc, AR_PHY_TPCRG1);
	tmp &= ~(0xf << 16);
	tmp |= (eep->xpd & 0xf) << 16;
	otus_write(sc, AR_PHY_TPCRG1, tmp);
	return otus_write_barrier(sc);
}
int otus_set_board_values ( struct otus_softc * sc , struct ieee80211_channel * c ) { const struct ModalEepHeader * eep ; uint32_t tmp , offset ; if ( IEEE80211_IS_CHAN_5GHZ ( c ) ) eep = & sc -> eeprom . modalHeader [ 0 ] ; else eep = & sc -> eeprom . modalHeader [ 1 ] ; offset = 2 * 0x1000 ; tmp = le32toh ( eep -> antCtrlCommon ) ; otus_write ( sc , AR_PHY_SWITCH_COM , tmp ) ; tmp = le32toh ( eep -> antCtrlChain [ 0 ] ) ; otus_write ( sc , AR_PHY_SWITCH_CHAIN_0 , tmp ) ; tmp = le32toh ( eep -> antCtrlChain [ 1 ] ) ; otus_write ( sc , AR_PHY_SWITCH_CHAIN_0 + offset , tmp ) ; if ( 1 ) { tmp = otus_phy_get_def ( sc , AR_PHY_SETTLING ) ; tmp &= ~ ( 0x7f << 7 ) ; tmp |= ( eep -> switchSettling & 0x7f ) << 7 ; otus_write ( sc , AR_PHY_SETTLING , tmp ) ; } tmp = otus_phy_get_def ( sc , AR_PHY_DESIRED_SZ ) ; tmp &= ~ 0xffff ; tmp |= eep -> pgaDesiredSize << 8 | eep -> adcDesiredSize ; otus_write ( sc , AR_PHY_DESIRED_SZ , tmp ) ; tmp = eep -> txEndToXpaOff << 24 | eep -> txEndToXpaOff << 16 | eep -> txFrameToXpaOn << 8 | eep -> txFrameToXpaOn ; otus_write ( sc , AR_PHY_RF_CTL4 , tmp ) ; tmp = otus_phy_get_def ( sc , AR_PHY_RF_CTL3 ) ; tmp &= ~ ( 0xff << 16 ) ; tmp |= eep -> txEndToRxOn << 16 ; otus_write ( sc , AR_PHY_RF_CTL3 , tmp ) ; tmp = otus_phy_get_def ( sc , AR_PHY_CCA ) ; tmp &= ~ ( 0x7f << 12 ) ; tmp |= ( eep -> thresh62 & 0x7f ) << 12 ; otus_write ( sc , AR_PHY_CCA , tmp ) ; tmp = otus_phy_get_def ( sc , AR_PHY_RXGAIN ) ; tmp &= ~ ( 0x3f << 12 ) ; tmp |= ( eep -> txRxAttenCh [ 0 ] & 0x3f ) << 12 ; otus_write ( sc , AR_PHY_RXGAIN , tmp ) ; tmp = otus_phy_get_def ( sc , AR_PHY_RXGAIN + offset ) ; tmp &= ~ ( 0x3f << 12 ) ; tmp |= ( eep -> txRxAttenCh [ 1 ] & 0x3f ) << 12 ; otus_write ( sc , AR_PHY_RXGAIN + offset , tmp ) ; tmp = otus_phy_get_def ( sc , AR_PHY_GAIN_2GHZ ) ; tmp &= ~ ( 0x3f << 18 ) ; tmp |= ( eep -> rxTxMarginCh [ 0 ] & 0x3f ) << 18 ; if ( IEEE80211_IS_CHAN_5GHZ ( c ) ) { tmp &= ~ ( 0xf << 10 ) ; tmp |= ( eep -> bswMargin [ 0 ] & 0xf ) << 10 ; } otus_write ( sc , AR_PHY_GAIN_2GHZ , tmp ) ; tmp = otus_phy_get_def ( sc , AR_PHY_GAIN_2GHZ + offset ) ; tmp &= ~ ( 0x3f << 18 ) ; tmp |= ( eep -> rxTxMarginCh [ 1 ] & 0x3f ) << 18 ; otus_write ( sc , AR_PHY_GAIN_2GHZ + offset , tmp ) ; tmp = otus_phy_get_def ( sc , AR_PHY_TIMING_CTRL4 ) ; tmp &= ~ ( 0x3f << 5 | 0x1f ) ; tmp |= ( eep -> iqCalICh [ 0 ] & 0x3f ) << 5 | ( eep -> iqCalQCh [ 0 ] & 0x1f ) ; otus_write ( sc , AR_PHY_TIMING_CTRL4 , tmp ) ; tmp = otus_phy_get_def ( sc , AR_PHY_TIMING_CTRL4 + offset ) ; tmp &= ~ ( 0x3f << 5 | 0x1f ) ; tmp |= ( eep -> iqCalICh [ 1 ] & 0x3f ) << 5 | ( eep -> iqCalQCh [ 1 ] & 0x1f ) ; otus_write ( sc , AR_PHY_TIMING_CTRL4 + offset , tmp ) ; tmp = otus_phy_get_def ( sc , AR_PHY_TPCRG1 ) ; tmp &= ~ ( 0xf << 16 ) ; tmp |= ( eep -> xpd & 0xf ) << 16 ; otus_write ( sc , AR_PHY_TPCRG1 , tmp ) ; return otus_write_barrier ( sc ) ; }
Update PHY's programming based on vendor-specific data stored in EEPROM.
Update PHY ' s programming based on vendor - specific data stored in EEPROM .
/* Offset of chain 2. */ /* sc->sc_sco == AR_SCO_SCN */