drivers/arm/gic/arm_gic.c
/*******************************************************************************
 * Enable secure interrupts and use FIQs to route them. Disable legacy bypass
 * and set the priority mask register to allow all interrupts to trickle in.
 ******************************************************************************/
Enable secure interrupts and use FIQs to route them. Disable legacy bypass
and set the priority mask register to allow all interrupts to trickle in.
Enable secure interrupts and use FIQs to route them . Disable legacy bypass and set the priority mask register to allow all interrupts to trickle in .
void arm_gic_cpuif_setup(void)
{
	unsigned int val;
	assert(g_gicc_base);
	val = gicc_read_iidr(g_gicc_base);
	if (((val >> GICC_IIDR_ARCH_SHIFT) & GICC_IIDR_ARCH_MASK) >= 3)
		gicv3_cpuif_setup();
	val = ENABLE_GRP0 | FIQ_EN | FIQ_BYP_DIS_GRP0;
	val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
	gicc_write_pmr(g_gicc_base, GIC_PRI_MASK);
	gicc_write_ctlr(g_gicc_base, val);
}
void arm_gic_cpuif_setup ( void ) { unsigned int val ; assert ( g_gicc_base ) ; val = gicc_read_iidr ( g_gicc_base ) ; if ( ( ( val >> GICC_IIDR_ARCH_SHIFT ) & GICC_IIDR_ARCH_MASK ) >= 3 ) gicv3_cpuif_setup ( ) ; val = ENABLE_GRP0 | FIQ_EN | FIQ_BYP_DIS_GRP0 ; val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1 ; gicc_write_pmr ( g_gicc_base , GIC_PRI_MASK ) ; gicc_write_ctlr ( g_gicc_base , val ) ; }
Enable secure interrupts and use FIQs to route them.
Enable secure interrupts and use FIQs to route them .
/*
	 * If GICv3 we need to do a bit of additional setup. We want to
	 * allow default GICv2 behaviour but allow the next stage to
	 * enable full gicv3 features.
	 */