baremetal/polarfire-soc-bare-metal-library/src/platform/mpfs_hal/mss_axiswitch.c
/* Programs the burstiness value for the given master port read/write address channel

burstiness_val: burstiness value to be programmed
NOTE: Burstiness value formula as mentioned in AXISW document is Burstiness = DataReg[23:16] + 1

regulator_en: QoS regulator Enable 1= enable, 0 = disable

* return value: As received form AXI_ERR_BIT in CMD register.
*/
Programs the burstiness value for the given master port read/write address channel
burstiness_val: burstiness value to be programmed
NOTE: Burstiness value formula as mentioned in AXISW document is Burstiness = DataReg[23:16] + 1

QoS regulator Enable 1= enable, 0 = disable

return value: As received form AXI_ERR_BIT in CMD register.
Programs the burstiness value for the given master port read / write address channel burstiness_val : burstiness value to be programmed NOTE : Burstiness value formula as mentioned in AXISW document is Burstiness = DataReg [ 23 : 16 ] + 1 QoS regulator Enable 1 = enable 0 = disable return value : As received form AXI_ERR_BIT in CMD register .
int32_t MSS_AXISW_write_burstiness(mss_axisw_mport_t master_port_num,
                                                  uint32_t burstiness_val,
                                                  uint32_t regulator_en)
{
    while(AXISW->CMD & AXISW_CMD_EN_MASK);  
    if(burstiness_val == 0)
    {
    	return -1;
    }
    else
    {
        AXISW->DATA = ((burstiness_val - 1u) << AXISW_DATA_BURSTI) | (regulator_en & 0x01);
    }
    AXISW->CMD = (AXISW_CMD_RW_MASK |
                 (master_port_num << AXISW_CMD_RWCHAN) |
                 (MSS_AXISW_BURSTINESS_EN) |
                 AXISW_CMD_EN_MASK);
    while(AXISW->CMD & AXISW_CMD_EN_MASK);      
    return ((AXISW->CMD & AXISW_CMD_ERR_MASK) >> AXISW_CMD_ERR);   
}
int32_t MSS_AXISW_write_burstiness ( mss_axisw_mport_t master_port_num , uint32_t burstiness_val , uint32_t regulator_en ) { while ( AXISW -> CMD & AXISW_CMD_EN_MASK ) ; if ( burstiness_val == 0 ) { return -1 ; } else { AXISW -> DATA = ( ( burstiness_val - 1u ) << AXISW_DATA_BURSTI ) | ( regulator_en & 0x01 ) ; } AXISW -> CMD = ( AXISW_CMD_RW_MASK | ( master_port_num << AXISW_CMD_RWCHAN ) | ( MSS_AXISW_BURSTINESS_EN ) | AXISW_CMD_EN_MASK ) ; while ( AXISW -> CMD & AXISW_CMD_EN_MASK ) ; return ( ( AXISW -> CMD & AXISW_CMD_ERR_MASK ) >> AXISW_CMD_ERR ) ; }
Programs the burstiness value for the given master port read/write address channel
burstiness_val: burstiness value to be programmed
NOTE: Burstiness value formula as mentioned in AXISW document is Burstiness = DataReg[23:16] + 1
Programs the burstiness value for the given master port read / write address channel burstiness_val : burstiness value to be programmed NOTE : Burstiness value formula as mentioned in AXISW document is Burstiness = DataReg [ 23 : 16 ] + 1
/*make sure previous command completed*/ /*Write burstiness value and enable burstiness regulator.
     * Burstiness_val=0 is not valid.
    Burstiness value formula as mentioned in AXISW document is Burstiness = DataReg[23:16] + 1*/ /*Wait for command to complete*/ /*return error bit value*/