arch/arm/soc/nxp_lpc176x5x/soc.c
/* Gets a clock divider for a peripheral */
Gets a clock divider for a peripheral
Gets a clock divider for a peripheral
uint32_t Soc_Chip_Clock_GetPCLKDiv(soc_sysctl_pclk_t clk)
{
	uint32_t div = 1, bitIndex, regIndex = ((uint32_t) clk) * 2;
	bitIndex = regIndex % 32;
	regIndex = regIndex / 32;
	div = LPC_SYSCTL->PCLKSEL[regIndex];
	div = (div >> bitIndex) & 0x3;
	if (div == SOC_SYSCTL_CLKDIV_4) {
		div = 4;
	}
	else if (div == SOC_SYSCTL_CLKDIV_1) {
		div = 1;
	}
	else if (div == SOC_SYSCTL_CLKDIV_2) {
		div = 2;
	}
	else {
		if ((clk == SOC_SYSCTL_PCLK_CAN1) || (clk == SOC_SYSCTL_PCLK_CAN2) || (clk == SOC_SYSCTL_PCLK_ACF)) {
			div = 6;
		}
		else {
			div = 8;
		}
	}
	return div;
}
uint32_t Soc_Chip_Clock_GetPCLKDiv ( soc_sysctl_pclk_t clk ) { uint32_t div = 1 , bitIndex , regIndex = ( ( uint32_t ) clk ) * 2 ; bitIndex = regIndex % 32 ; regIndex = regIndex / 32 ; div = LPC_SYSCTL -> PCLKSEL [ regIndex ] ; div = ( div >> bitIndex ) & 0x3 ; if ( div == SOC_SYSCTL_CLKDIV_4 ) { div = 4 ; } else if ( div == SOC_SYSCTL_CLKDIV_1 ) { div = 1 ; } else if ( div == SOC_SYSCTL_CLKDIV_2 ) { div = 2 ; } else { if ( ( clk == SOC_SYSCTL_PCLK_CAN1 ) || ( clk == SOC_SYSCTL_PCLK_CAN2 ) || ( clk == SOC_SYSCTL_PCLK_ACF ) ) { div = 6 ; } else { div = 8 ; } } return div ; }
Gets a clock divider for a peripheral
Gets a clock divider for a peripheral
/* Get register array index and clock index into the register */ /* Mask and update register */ /* Special case for CAN clock divider */