FreeBSD/sys/mips/mips/machdep.c
/*
 * Initialize the hardware exception vectors, and the jump table used to
 * call locore cache and TLB management functions, based on the kind
 * of CPU the kernel is running on.
 */
Initialize the hardware exception vectors, and the jump table used to
call locore cache and TLB management functions, based on the kind
of CPU the kernel is running on.
Initialize the hardware exception vectors and the jump table used to call locore cache and TLB management functions based on the kind of CPU the kernel is running on .
void
mips_vector_init(void)
{
	if (MipsWaitEnd - MipsWaitStart != 16)
		panic("startup: MIPS wait region not correct");
	if (MipsTLBMissEnd - MipsTLBMiss > 0x80)
		panic("startup: UTLB code too large");
	if (MipsCacheEnd - MipsCache > 0x80)
		panic("startup: Cache error code too large");
	bcopy(MipsTLBMiss, (void *)MIPS_UTLB_MISS_EXC_VEC,
	      MipsTLBMissEnd - MipsTLBMiss);
#if defined(__mips_n64) || defined(CPU_RMI) || defined(CPU_NLM) || defined(CPU_BERI)
	bcopy(MipsTLBMiss, (void *)MIPS_XTLB_MISS_EXC_VEC,
	      MipsTLBMissEnd - MipsTLBMiss);
#endif
	bcopy(MipsException, (void *)MIPS_GEN_EXC_VEC,
	      MipsExceptionEnd - MipsException);
	bcopy(MipsCache, (void *)MIPS_CACHE_ERR_EXC_VEC,
	      MipsCacheEnd - MipsCache);
	mips_icache_sync_all();
	mips_dcache_wbinv_all();
	set_intr_mask(0);
	mips_wr_status(mips_rd_status() & ~MIPS_SR_BEV);
}
void mips_vector_init ( void ) { if ( MipsWaitEnd - MipsWaitStart != 16 ) panic ( " " ) ; if ( MipsTLBMissEnd - MipsTLBMiss > 0x80 ) panic ( " " ) ; if ( MipsCacheEnd - MipsCache > 0x80 ) panic ( " " ) ; bcopy ( MipsTLBMiss , ( void * ) MIPS_UTLB_MISS_EXC_VEC , MipsTLBMissEnd - MipsTLBMiss ) ; #if defined ( __mips_n64 ) || defined ( CPU_RMI ) || defined ( CPU_NLM ) || defined ( CPU_BERI ) bcopy ( MipsTLBMiss , ( void * ) MIPS_XTLB_MISS_EXC_VEC , MipsTLBMissEnd - MipsTLBMiss ) ; #endif bcopy ( MipsException , ( void * ) MIPS_GEN_EXC_VEC , MipsExceptionEnd - MipsException ) ; bcopy ( MipsCache , ( void * ) MIPS_CACHE_ERR_EXC_VEC , MipsCacheEnd - MipsCache ) ; mips_icache_sync_all ( ) ; mips_dcache_wbinv_all ( ) ; set_intr_mask ( 0 ) ; mips_wr_status ( mips_rd_status ( ) & ~ MIPS_SR_BEV ) ; }
Initialize the hardware exception vectors, and the jump table used to
 call locore cache and TLB management functions, based on the kind
 of CPU the kernel is running on.
Initialize the hardware exception vectors and the jump table used to call locore cache and TLB management functions based on the kind of CPU the kernel is running on .
/*
	 * Make sure that the Wait region logic is not been 
	 * changed
	 */ /*
	 * Copy down exception vector code.
	 */ /*
	 * XXXRW: Why don't we install the XTLB handler for all 64-bit
	 * architectures?
	 */ /* Fake, but sufficient, for the 32-bit with 64-bit hardware addresses  */ /*
	 * Clear out the I and D caches.
	 */ /* 
	 * Mask all interrupts. Each interrupt will be enabled
	 * when handler is installed for it
	 */ /* Clear BEV in SR so we start handling our own exceptions */