KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c
/**
  * @brief  Configures the RCC_ClkInitStruct according to the internal
  * RCC configuration registers.
  * @param  RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
  * will be configured.
  * @param  pFLatency: Pointer on the Flash Latency.
  * @retval None
  */
@brief  Configures the RCC_ClkInitStruct according to the internal
RCC configuration registers.
@param  RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
will be configured.
@param  pFLatency: Pointer on the Flash Latency.
@retval None
@brief Configures the RCC_ClkInitStruct according to the internal RCC configuration registers . @param RCC_ClkInitStruct : pointer to an RCC_ClkInitTypeDef structure that will be configured . @param pFLatency : Pointer on the Flash Latency . @retval None
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
{
  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 |
                                 RCC_CLOCKTYPE_PCLK2 |  RCC_CLOCKTYPE_D3PCLK1  ;
  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
  RCC_ClkInitStruct->SYSCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1CPRE);
  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_HPRE);
  RCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->D1CFGR & RCC_D1CFGR_D1PPRE);
  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1);
  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2);
  RCC_ClkInitStruct->APB4CLKDivider = (uint32_t)(RCC->D3CFGR & RCC_D3CFGR_D3PPRE);
  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
}
void HAL_RCC_GetClockConfig ( RCC_ClkInitTypeDef * RCC_ClkInitStruct , uint32_t * pFLatency ) { RCC_ClkInitStruct -> ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_D3PCLK1 ; RCC_ClkInitStruct -> SYSCLKSource = ( uint32_t ) ( RCC -> CFGR & RCC_CFGR_SW ) ; RCC_ClkInitStruct -> SYSCLKDivider = ( uint32_t ) ( RCC -> D1CFGR & RCC_D1CFGR_D1CPRE ) ; RCC_ClkInitStruct -> AHBCLKDivider = ( uint32_t ) ( RCC -> D1CFGR & RCC_D1CFGR_HPRE ) ; RCC_ClkInitStruct -> APB3CLKDivider = ( uint32_t ) ( RCC -> D1CFGR & RCC_D1CFGR_D1PPRE ) ; RCC_ClkInitStruct -> APB1CLKDivider = ( uint32_t ) ( RCC -> D2CFGR & RCC_D2CFGR_D2PPRE1 ) ; RCC_ClkInitStruct -> APB2CLKDivider = ( uint32_t ) ( RCC -> D2CFGR & RCC_D2CFGR_D2PPRE2 ) ; RCC_ClkInitStruct -> APB4CLKDivider = ( uint32_t ) ( RCC -> D3CFGR & RCC_D3CFGR_D3PPRE ) ; * pFLatency = ( uint32_t ) ( FLASH -> ACR & FLASH_ACR_LATENCY ) ; }
@brief  Configures the RCC_ClkInitStruct according to the internal
 RCC configuration registers.
@brief Configures the RCC_ClkInitStruct according to the internal RCC configuration registers .
/* Set all possible values for the Clock type parameter --------------------*/ /* Get the SYSCLK configuration --------------------------------------------*/ /* Get the SYSCLK configuration ----------------------------------------------*/ /* Get the D1HCLK configuration ----------------------------------------------*/ /* Get the APB3 configuration ----------------------------------------------*/ /* Get the APB1 configuration ----------------------------------------------*/ /* Get the APB2 configuration ----------------------------------------------*/ /* Get the APB4 configuration ----------------------------------------------*/ /* Get the Flash Wait State (Latency) configuration ------------------------*/