linux/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
/**
 * Setup source pixel format, flip,
 */
Setup source pixel format, flip.
Setup source pixel format flip .
static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx,
		const struct dpu_format *fmt, u32 flags,
		enum dpu_sspp_multirect_index rect_mode)
{
	struct dpu_hw_blk_reg_map *c;
	u32 chroma_samp, unpack, src_format;
	u32 opmode = 0;
	u32 fast_clear = 0;
	u32 op_mode_off, unpack_pat_off, format_off;
	u32 idx;
	if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !fmt)
		return;
	if (rect_mode == DPU_SSPP_RECT_SOLO || rect_mode == DPU_SSPP_RECT_0) {
		op_mode_off = SSPP_SRC_OP_MODE;
		unpack_pat_off = SSPP_SRC_UNPACK_PATTERN;
		format_off = SSPP_SRC_FORMAT;
	} else {
		op_mode_off = SSPP_SRC_OP_MODE_REC1;
		unpack_pat_off = SSPP_SRC_UNPACK_PATTERN_REC1;
		format_off = SSPP_SRC_FORMAT_REC1;
	}
	c = &ctx->hw;
	opmode = DPU_REG_READ(c, op_mode_off + idx);
	opmode &= ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD |
			MDSS_MDP_OP_BWC_EN | MDSS_MDP_OP_PE_OVERRIDE);
	if (flags & DPU_SSPP_FLIP_LR)
		opmode |= MDSS_MDP_OP_FLIP_LR;
	if (flags & DPU_SSPP_FLIP_UD)
		opmode |= MDSS_MDP_OP_FLIP_UD;
	chroma_samp = fmt->chroma_sample;
	if (flags & DPU_SSPP_SOURCE_ROTATED_90) {
		if (chroma_samp == DPU_CHROMA_H2V1)
			chroma_samp = DPU_CHROMA_H1V2;
		else if (chroma_samp == DPU_CHROMA_H1V2)
			chroma_samp = DPU_CHROMA_H2V1;
	}
	src_format = (chroma_samp << 23) | (fmt->fetch_planes << 19) |
		(fmt->bits[C3_ALPHA] << 6) | (fmt->bits[C2_R_Cr] << 4) |
		(fmt->bits[C1_B_Cb] << 2) | (fmt->bits[C0_G_Y] << 0);
	if (flags & DPU_SSPP_ROT_90)
		src_format |= BIT(11); 
	if (fmt->alpha_enable && fmt->fetch_planes == DPU_PLANE_INTERLEAVED)
		src_format |= BIT(8); 
	if (flags & DPU_SSPP_SOLID_FILL)
		src_format |= BIT(22);
	unpack = (fmt->element[3] << 24) | (fmt->element[2] << 16) |
		(fmt->element[1] << 8) | (fmt->element[0] << 0);
	src_format |= ((fmt->unpack_count - 1) << 12) |
		(fmt->unpack_tight << 17) |
		(fmt->unpack_align_msb << 18) |
		((fmt->bpp - 1) << 9);
	if (fmt->fetch_mode != DPU_FETCH_LINEAR) {
		if (DPU_FORMAT_IS_UBWC(fmt))
			opmode |= MDSS_MDP_OP_BWC_EN;
		src_format |= (fmt->fetch_mode & 3) << 30; 
		DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
			DPU_FETCH_CONFIG_RESET_VALUE |
			ctx->mdp->highest_bank_bit << 18);
		if (IS_UBWC_20_SUPPORTED(ctx->catalog->caps->ubwc_version)) {
			fast_clear = fmt->alpha_enable ? BIT(31) : 0;
			DPU_REG_WRITE(c, SSPP_UBWC_STATIC_CTRL,
					fast_clear | (ctx->mdp->ubwc_swizzle) |
					(ctx->mdp->highest_bank_bit << 4));
		}
	}
	opmode |= MDSS_MDP_OP_PE_OVERRIDE;
	if (DPU_FORMAT_IS_YUV(fmt))
		src_format |= BIT(15);
	if (DPU_FORMAT_IS_DX(fmt))
		src_format |= BIT(14);
	if (test_bit(DPU_SSPP_CSC, &ctx->cap->features))
		_sspp_setup_opmode(ctx, VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT,
			DPU_FORMAT_IS_YUV(fmt));
	else if (test_bit(DPU_SSPP_CSC_10BIT, &ctx->cap->features))
		_sspp_setup_csc10_opmode(ctx,
			VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT,
			DPU_FORMAT_IS_YUV(fmt));
	DPU_REG_WRITE(c, format_off + idx, src_format);
	DPU_REG_WRITE(c, unpack_pat_off + idx, unpack);
	DPU_REG_WRITE(c, op_mode_off + idx, opmode);
	DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS + idx, BIT(31));
}
static void dpu_hw_sspp_setup_format ( struct dpu_hw_pipe * ctx , const struct dpu_format * fmt , u32 flags , enum dpu_sspp_multirect_index rect_mode ) { struct dpu_hw_blk_reg_map * c ; u32 chroma_samp , unpack , src_format ; u32 opmode = 0 ; u32 fast_clear = 0 ; u32 op_mode_off , unpack_pat_off , format_off ; u32 idx ; if ( _sspp_subblk_offset ( ctx , DPU_SSPP_SRC , & idx ) || ! fmt ) return ; if ( rect_mode == DPU_SSPP_RECT_SOLO || rect_mode == DPU_SSPP_RECT_0 ) { op_mode_off = SSPP_SRC_OP_MODE ; unpack_pat_off = SSPP_SRC_UNPACK_PATTERN ; format_off = SSPP_SRC_FORMAT ; } else { op_mode_off = SSPP_SRC_OP_MODE_REC1 ; unpack_pat_off = SSPP_SRC_UNPACK_PATTERN_REC1 ; format_off = SSPP_SRC_FORMAT_REC1 ; } c = & ctx -> hw ; opmode = DPU_REG_READ ( c , op_mode_off + idx ) ; opmode &= ~ ( MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD | MDSS_MDP_OP_BWC_EN | MDSS_MDP_OP_PE_OVERRIDE ) ; if ( flags & DPU_SSPP_FLIP_LR ) opmode |= MDSS_MDP_OP_FLIP_LR ; if ( flags & DPU_SSPP_FLIP_UD ) opmode |= MDSS_MDP_OP_FLIP_UD ; chroma_samp = fmt -> chroma_sample ; if ( flags & DPU_SSPP_SOURCE_ROTATED_90 ) { if ( chroma_samp == DPU_CHROMA_H2V1 ) chroma_samp = DPU_CHROMA_H1V2 ; else if ( chroma_samp == DPU_CHROMA_H1V2 ) chroma_samp = DPU_CHROMA_H2V1 ; } src_format = ( chroma_samp << 23 ) | ( fmt -> fetch_planes << 19 ) | ( fmt -> bits [ C3_ALPHA ] << 6 ) | ( fmt -> bits [ C2_R_Cr ] << 4 ) | ( fmt -> bits [ C1_B_Cb ] << 2 ) | ( fmt -> bits [ C0_G_Y ] << 0 ) ; if ( flags & DPU_SSPP_ROT_90 ) src_format |= BIT ( 11 ) ; if ( fmt -> alpha_enable && fmt -> fetch_planes == DPU_PLANE_INTERLEAVED ) src_format |= BIT ( 8 ) ; if ( flags & DPU_SSPP_SOLID_FILL ) src_format |= BIT ( 22 ) ; unpack = ( fmt -> element [ 3 ] << 24 ) | ( fmt -> element [ 2 ] << 16 ) | ( fmt -> element [ 1 ] << 8 ) | ( fmt -> element [ 0 ] << 0 ) ; src_format |= ( ( fmt -> unpack_count - 1 ) << 12 ) | ( fmt -> unpack_tight << 17 ) | ( fmt -> unpack_align_msb << 18 ) | ( ( fmt -> bpp - 1 ) << 9 ) ; if ( fmt -> fetch_mode != DPU_FETCH_LINEAR ) { if ( DPU_FORMAT_IS_UBWC ( fmt ) ) opmode |= MDSS_MDP_OP_BWC_EN ; src_format |= ( fmt -> fetch_mode & 3 ) << 30 ; DPU_REG_WRITE ( c , SSPP_FETCH_CONFIG , DPU_FETCH_CONFIG_RESET_VALUE | ctx -> mdp -> highest_bank_bit << 18 ) ; if ( IS_UBWC_20_SUPPORTED ( ctx -> catalog -> caps -> ubwc_version ) ) { fast_clear = fmt -> alpha_enable ? BIT ( 31 ) : 0 ; DPU_REG_WRITE ( c , SSPP_UBWC_STATIC_CTRL , fast_clear | ( ctx -> mdp -> ubwc_swizzle ) | ( ctx -> mdp -> highest_bank_bit << 4 ) ) ; } } opmode |= MDSS_MDP_OP_PE_OVERRIDE ; if ( DPU_FORMAT_IS_YUV ( fmt ) ) src_format |= BIT ( 15 ) ; if ( DPU_FORMAT_IS_DX ( fmt ) ) src_format |= BIT ( 14 ) ; if ( test_bit ( DPU_SSPP_CSC , & ctx -> cap -> features ) ) _sspp_setup_opmode ( ctx , VIG_OP_CSC_EN | VIG_OP_CSC_SRC_DATAFMT , DPU_FORMAT_IS_YUV ( fmt ) ) ; else if ( test_bit ( DPU_SSPP_CSC_10BIT , & ctx -> cap -> features ) ) _sspp_setup_csc10_opmode ( ctx , VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT , DPU_FORMAT_IS_YUV ( fmt ) ) ; DPU_REG_WRITE ( c , format_off + idx , src_format ) ; DPU_REG_WRITE ( c , unpack_pat_off + idx , unpack ) ; DPU_REG_WRITE ( c , op_mode_off + idx , opmode ) ; DPU_REG_WRITE ( c , SSPP_UBWC_ERROR_STATUS + idx , BIT ( 31 ) ) ; }
Setup source pixel format, flip,
Setup source pixel format flip
/* ROT90 */ /* SRCC3_EN */ /*FRAME_FORMAT */ /* if this is YUV pixel format, enable CSC */ /* update scaler opmode, if appropriate */ /* clear previous UBWC error */