FreeBSD/sys/dev/cxgbe/common/t4_hw.c
/*
 * EDC/MC interrupt handler.
 */
EDC/MC interrupt handler.
EDC / MC interrupt handler .
static void mem_intr_handler(struct adapter *adapter, int idx)
{
	static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
	unsigned int addr, cnt_addr, v;
	if (idx <= MEM_EDC1) {
		addr = EDC_REG(A_EDC_INT_CAUSE, idx);
		cnt_addr = EDC_REG(A_EDC_ECC_STATUS, idx);
	} else if (idx == MEM_MC) {
		if (is_t4(adapter)) {
			addr = A_MC_INT_CAUSE;
			cnt_addr = A_MC_ECC_STATUS;
		} else {
			addr = A_MC_P_INT_CAUSE;
			cnt_addr = A_MC_P_ECC_STATUS;
		}
	} else {
		addr = MC_REG(A_MC_P_INT_CAUSE, 1);
		cnt_addr = MC_REG(A_MC_P_ECC_STATUS, 1);
	}
	v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
	if (v & F_PERR_INT_CAUSE)
		CH_ALERT(adapter, "%s FIFO parity error\n",
			  name[idx]);
	if (v & F_ECC_CE_INT_CAUSE) {
		u32 cnt = G_ECC_CECNT(t4_read_reg(adapter, cnt_addr));
		t4_edc_err_read(adapter, idx);
		t4_write_reg(adapter, cnt_addr, V_ECC_CECNT(M_ECC_CECNT));
		CH_WARN_RATELIMIT(adapter,
				  "%u %s correctable ECC data error%s\n",
				  cnt, name[idx], cnt > 1 ? "s" : "");
	}
	if (v & F_ECC_UE_INT_CAUSE)
		CH_ALERT(adapter,
			 "%s uncorrectable ECC data error\n", name[idx]);
	t4_write_reg(adapter, addr, v);
	if (v & (F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE))
		t4_fatal_err(adapter);
}
static void mem_intr_handler ( struct adapter * adapter , int idx ) { static const char name [ 4 ] [ 7 ] = { " " , " " , " " , " " } ; unsigned int addr , cnt_addr , v ; if ( idx <= MEM_EDC1 ) { addr = EDC_REG ( A_EDC_INT_CAUSE , idx ) ; cnt_addr = EDC_REG ( A_EDC_ECC_STATUS , idx ) ; } else if ( idx == MEM_MC ) { if ( is_t4 ( adapter ) ) { addr = A_MC_INT_CAUSE ; cnt_addr = A_MC_ECC_STATUS ; } else { addr = A_MC_P_INT_CAUSE ; cnt_addr = A_MC_P_ECC_STATUS ; } } else { addr = MC_REG ( A_MC_P_INT_CAUSE , 1 ) ; cnt_addr = MC_REG ( A_MC_P_ECC_STATUS , 1 ) ; } v = t4_read_reg ( adapter , addr ) & MEM_INT_MASK ; if ( v & F_PERR_INT_CAUSE ) CH_ALERT ( adapter , " \n " , name [ idx ] ) ; if ( v & F_ECC_CE_INT_CAUSE ) { u32 cnt = G_ECC_CECNT ( t4_read_reg ( adapter , cnt_addr ) ) ; t4_edc_err_read ( adapter , idx ) ; t4_write_reg ( adapter , cnt_addr , V_ECC_CECNT ( M_ECC_CECNT ) ) ; CH_WARN_RATELIMIT ( adapter , " \n " , cnt , name [ idx ] , cnt > 1 ? " " : " " ) ; } if ( v & F_ECC_UE_INT_CAUSE ) CH_ALERT ( adapter , " \n " , name [ idx ] ) ; t4_write_reg ( adapter , addr , v ) ; if ( v & ( F_PERR_INT_CAUSE | F_ECC_UE_INT_CAUSE ) ) t4_fatal_err ( adapter ) ; }
EDC/MC interrupt handler.
EDC / MC interrupt handler .