Firmware/PeugeotDisplay4245/PeugeotDisplay4245.cydsn/Generated_Source/PSoC4/SPILCD_SCBCLK.c
/*******************************************************************************
* Function Name: SPILCD_SCBCLK_StartEx
********************************************************************************
*
* Summary:
*  Starts the clock, aligned to the specified running clock.
*
* Parameters:
*  alignClkDiv:  The divider to which phase alignment is performed when the
*    clock is started.
*
* Returns:
*  None
*
*******************************************************************************/
Function Name: SPILCD_SCBCLK_StartEx
Summary:
Starts the clock, aligned to the specified running clock.

The divider to which phase alignment is performed when the
clock is started.

None
Function Name : SPILCD_SCBCLK_StartEx Summary : Starts the clock aligned to the specified running clock . The divider to which phase alignment is performed when the clock is started . None
void SPILCD_SCBCLK_StartEx(uint32 alignClkDiv)
{
    while((SPILCD_SCBCLK_CMD_REG & SPILCD_SCBCLK_CMD_ENABLE_MASK) != 0u)
    {
    }
    SPILCD_SCBCLK_CMD_REG =
        ((uint32)SPILCD_SCBCLK__DIV_ID << SPILCD_SCBCLK_CMD_DIV_SHIFT)|
        (alignClkDiv << SPILCD_SCBCLK_CMD_PA_DIV_SHIFT) |
        (uint32)SPILCD_SCBCLK_CMD_ENABLE_MASK;
}
void SPILCD_SCBCLK_StartEx ( uint32 alignClkDiv ) { while ( ( SPILCD_SCBCLK_CMD_REG & SPILCD_SCBCLK_CMD_ENABLE_MASK ) != 0u ) { } SPILCD_SCBCLK_CMD_REG = ( ( uint32 ) SPILCD_SCBCLK__DIV_ID << SPILCD_SCBCLK_CMD_DIV_SHIFT ) | ( alignClkDiv << SPILCD_SCBCLK_CMD_PA_DIV_SHIFT ) | ( uint32 ) SPILCD_SCBCLK_CMD_ENABLE_MASK ; }
Function Name: SPILCD_SCBCLK_StartEx
Summary:
Starts the clock, aligned to the specified running clock.
Function Name : SPILCD_SCBCLK_StartEx Summary : Starts the clock aligned to the specified running clock .
/* Make sure any previous start command has finished. */ /* Specify the target divider and it's alignment divider, and enable. */