drivers/arm/gic/arm_gic.c
/*******************************************************************************
 * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins.
 * The interrupt controller knows which pin/line it uses to signal a type of
 * interrupt. This function provides a common implementation of
 * plat_interrupt_type_to_line() in an ARM GIC environment for optional re-use
 * across platforms. It lets the interrupt management framework determine
 * for a type of interrupt and security state, which line should be used in the
 * SCR_EL3 to control its routing to EL3. The interrupt line is represented as
 * the bit position of the IRQ or FIQ bit in the SCR_EL3.
 ******************************************************************************/
An ARM processor signals interrupt exceptions through the IRQ and FIQ pins.
The interrupt controller knows which pin/line it uses to signal a type of
interrupt. This function provides a common implementation of
plat_interrupt_type_to_line() in an ARM GIC environment for optional re-use
across platforms. It lets the interrupt management framework determine
for a type of interrupt and security state, which line should be used in the
SCR_EL3 to control its routing to EL3. The interrupt line is represented as
the bit position of the IRQ or FIQ bit in the SCR_EL3.
An ARM processor signals interrupt exceptions through the IRQ and FIQ pins . The interrupt controller knows which pin / line it uses to signal a type of interrupt . This function provides a common implementation of plat_interrupt_type_to_line () in an ARM GIC environment for optional re - use across platforms . It lets the interrupt management framework determine for a type of interrupt and security state which line should be used in the SCR_EL3 to control its routing to EL3 . The interrupt line is represented as the bit position of the IRQ or FIQ bit in the SCR_EL3 .
uint32_t arm_gic_interrupt_type_to_line(uint32_t type,
				uint32_t security_state)
{
	assert(type == INTR_TYPE_S_EL1 ||
	       type == INTR_TYPE_EL3 ||
	       type == INTR_TYPE_NS);
	assert(sec_state_is_valid(security_state));
#if ARM_GIC_ARCH == 2
	return gicv2_interrupt_type_to_line(g_gicc_base, type);
#else
#error "Invalid ARM GIC architecture version specified for platform port"
#endif 
}
uint32_t arm_gic_interrupt_type_to_line ( uint32_t type , uint32_t security_state ) { assert ( type == INTR_TYPE_S_EL1 || type == INTR_TYPE_EL3 || type == INTR_TYPE_NS ) ; assert ( sec_state_is_valid ( security_state ) ) ; #if ARM_GIC_ARCH == 2 return gicv2_interrupt_type_to_line ( g_gicc_base , type ) ; #else #error  "Invalid ARM GIC architecture version specified for platform port" #endif }
An ARM processor signals interrupt exceptions through the IRQ and FIQ pins.
An ARM processor signals interrupt exceptions through the IRQ and FIQ pins .
/*
	 * We ignore the security state parameter under the assumption that
	 * both normal and secure worlds are using ARM GICv2. This parameter
	 * will be used when the secure world starts using GICv3.
	 */ /* ARM_GIC_ARCH */