src/qemu/src-pmp/accel/tcg/cputlb.c
/* update the TLB corresponding to virtual page vaddr
   so that it is no longer dirty */
update the TLB corresponding to virtual page vaddr
so that it is no longer dirty
update the TLB corresponding to virtual page vaddr so that it is no longer dirty
void tlb_set_dirty(CPUState *cpu, target_ulong vaddr)
{
    CPUArchState *env = cpu->env_ptr;
    int mmu_idx;
    assert_cpu_is_self(cpu);
    vaddr &= TARGET_PAGE_MASK;
    qemu_spin_lock(&env->tlb_c.lock);
    for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
        tlb_set_dirty1_locked(tlb_entry(env, mmu_idx, vaddr), vaddr);
    }
    for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
        int k;
        for (k = 0; k < CPU_VTLB_SIZE; k++) {
            tlb_set_dirty1_locked(&env->tlb_v_table[mmu_idx][k], vaddr);
        }
    }
    qemu_spin_unlock(&env->tlb_c.lock);
}
void tlb_set_dirty ( CPUState * cpu , target_ulong vaddr ) { CPUArchState * env = cpu -> env_ptr ; int mmu_idx ; assert_cpu_is_self ( cpu ) ; vaddr &= TARGET_PAGE_MASK ; qemu_spin_lock ( & env -> tlb_c . lock ) ; for ( mmu_idx = 0 ; mmu_idx < NB_MMU_MODES ; mmu_idx ++ ) { tlb_set_dirty1_locked ( tlb_entry ( env , mmu_idx , vaddr ) , vaddr ) ; } for ( mmu_idx = 0 ; mmu_idx < NB_MMU_MODES ; mmu_idx ++ ) { int k ; for ( k = 0 ; k < CPU_VTLB_SIZE ; k ++ ) { tlb_set_dirty1_locked ( & env -> tlb_v_table [ mmu_idx ] [ k ] , vaddr ) ; } } qemu_spin_unlock ( & env -> tlb_c . lock ) ; }
update the TLB corresponding to virtual page vaddr
so that it is no longer dirty
update the TLB corresponding to virtual page vaddr so that it is no longer dirty