FreeBSD/sys/dev/cxgbe/common/t4_hw.c
/*
 * Interrupt handler for the PCIE module.
 */
Interrupt handler for the PCIE module.
Interrupt handler for the PCIE module .
static void pcie_intr_handler(struct adapter *adapter)
{
	static const struct intr_info sysbus_intr_info[] = {
		{ F_RNPP, "RXNP array parity error", -1, 1 },
		{ F_RPCP, "RXPC array parity error", -1, 1 },
		{ F_RCIP, "RXCIF array parity error", -1, 1 },
		{ F_RCCP, "Rx completions control array parity error", -1, 1 },
		{ F_RFTP, "RXFT array parity error", -1, 1 },
		{ 0 }
	};
	static const struct intr_info pcie_port_intr_info[] = {
		{ F_TPCP, "TXPC array parity error", -1, 1 },
		{ F_TNPP, "TXNP array parity error", -1, 1 },
		{ F_TFTP, "TXFT array parity error", -1, 1 },
		{ F_TCAP, "TXCA array parity error", -1, 1 },
		{ F_TCIP, "TXCIF array parity error", -1, 1 },
		{ F_RCAP, "RXCA array parity error", -1, 1 },
		{ F_OTDD, "outbound request TLP discarded", -1, 1 },
		{ F_RDPE, "Rx data parity error", -1, 1 },
		{ F_TDUE, "Tx uncorrectable data error", -1, 1 },
		{ 0 }
	};
	static const struct intr_info pcie_intr_info[] = {
		{ F_MSIADDRLPERR, "MSI AddrL parity error", -1, 1 },
		{ F_MSIADDRHPERR, "MSI AddrH parity error", -1, 1 },
		{ F_MSIDATAPERR, "MSI data parity error", -1, 1 },
		{ F_MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
		{ F_MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
		{ F_MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
		{ F_MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
		{ F_PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 },
		{ F_PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 },
		{ F_TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
		{ F_CCNTPERR, "PCI CMD channel count parity error", -1, 1 },
		{ F_CREQPERR, "PCI CMD channel request parity error", -1, 1 },
		{ F_CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
		{ F_DCNTPERR, "PCI DMA channel count parity error", -1, 1 },
		{ F_DREQPERR, "PCI DMA channel request parity error", -1, 1 },
		{ F_DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
		{ F_HCNTPERR, "PCI HMA channel count parity error", -1, 1 },
		{ F_HREQPERR, "PCI HMA channel request parity error", -1, 1 },
		{ F_HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
		{ F_CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
		{ F_FIDPERR, "PCI FID parity error", -1, 1 },
		{ F_INTXCLRPERR, "PCI INTx clear parity error", -1, 1 },
		{ F_MATAGPERR, "PCI MA tag parity error", -1, 1 },
		{ F_PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
		{ F_RXCPLPERR, "PCI Rx completion parity error", -1, 1 },
		{ F_RXWRPERR, "PCI Rx write parity error", -1, 1 },
		{ F_RPLPERR, "PCI replay buffer parity error", -1, 1 },
		{ F_PCIESINT, "PCI core secondary fault", -1, 1 },
		{ F_PCIEPINT, "PCI core primary fault", -1, 1 },
		{ F_UNXSPLCPLERR, "PCI unexpected split completion error", -1,
		  0 },
		{ 0 }
	};
	static const struct intr_info t5_pcie_intr_info[] = {
		{ F_MSTGRPPERR, "Master Response Read Queue parity error",
		  -1, 1 },
		{ F_MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 },
		{ F_MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 },
		{ F_MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
		{ F_MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
		{ F_MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
		{ F_MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
		{ F_PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error",
		  -1, 1 },
		{ F_PIOREQGRPPERR, "PCI PIO request Group FIFO parity error",
		  -1, 1 },
		{ F_TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
		{ F_MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 },
		{ F_CREQPERR, "PCI CMD channel request parity error", -1, 1 },
		{ F_CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
		{ F_DREQWRPERR, "PCI DMA channel write request parity error",
		  -1, 1 },
		{ F_DREQPERR, "PCI DMA channel request parity error", -1, 1 },
		{ F_DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
		{ F_HREQWRPERR, "PCI HMA channel count parity error", -1, 1 },
		{ F_HREQPERR, "PCI HMA channel request parity error", -1, 1 },
		{ F_HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
		{ F_CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
		{ F_FIDPERR, "PCI FID parity error", -1, 1 },
		{ F_VFIDPERR, "PCI INTx clear parity error", -1, 1 },
		{ F_MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 },
		{ F_PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
		{ F_IPRXHDRGRPPERR, "PCI IP Rx header group parity error",
		  -1, 1 },
		{ F_IPRXDATAGRPPERR, "PCI IP Rx data group parity error",
		  -1, 1 },
		{ F_RPLPERR, "PCI IP replay buffer parity error", -1, 1 },
		{ F_IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 },
		{ F_TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 },
		{ F_READRSPERR, "Outbound read error", -1,
		  0 },
		{ 0 }
	};
	int fat;
	if (is_t4(adapter))
		fat = t4_handle_intr_status(adapter,
				A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
				sysbus_intr_info) +
			t4_handle_intr_status(adapter,
					A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
					pcie_port_intr_info) +
			t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE,
					      pcie_intr_info);
	else
		fat = t4_handle_intr_status(adapter, A_PCIE_INT_CAUSE,
					    t5_pcie_intr_info);
	if (fat)
		t4_fatal_err(adapter);
}
static void pcie_intr_handler ( struct adapter * adapter ) { static const struct intr_info sysbus_intr_info [ ] = { { F_RNPP , " " , -1 , 1 } , { F_RPCP , " " , -1 , 1 } , { F_RCIP , " " , -1 , 1 } , { F_RCCP , " " , -1 , 1 } , { F_RFTP , " " , -1 , 1 } , { 0 } } ; static const struct intr_info pcie_port_intr_info [ ] = { { F_TPCP , " " , -1 , 1 } , { F_TNPP , " " , -1 , 1 } , { F_TFTP , " " , -1 , 1 } , { F_TCAP , " " , -1 , 1 } , { F_TCIP , " " , -1 , 1 } , { F_RCAP , " " , -1 , 1 } , { F_OTDD , " " , -1 , 1 } , { F_RDPE , " " , -1 , 1 } , { F_TDUE , " " , -1 , 1 } , { 0 } } ; static const struct intr_info pcie_intr_info [ ] = { { F_MSIADDRLPERR , " " , -1 , 1 } , { F_MSIADDRHPERR , " " , -1 , 1 } , { F_MSIDATAPERR , " " , -1 , 1 } , { F_MSIXADDRLPERR , " " , -1 , 1 } , { F_MSIXADDRHPERR , " " , -1 , 1 } , { F_MSIXDATAPERR , " " , -1 , 1 } , { F_MSIXDIPERR , " " , -1 , 1 } , { F_PIOCPLPERR , " " , -1 , 1 } , { F_PIOREQPERR , " " , -1 , 1 } , { F_TARTAGPERR , " " , -1 , 1 } , { F_CCNTPERR , " " , -1 , 1 } , { F_CREQPERR , " " , -1 , 1 } , { F_CRSPPERR , " " , -1 , 1 } , { F_DCNTPERR , " " , -1 , 1 } , { F_DREQPERR , " " , -1 , 1 } , { F_DRSPPERR , " " , -1 , 1 } , { F_HCNTPERR , " " , -1 , 1 } , { F_HREQPERR , " " , -1 , 1 } , { F_HRSPPERR , " " , -1 , 1 } , { F_CFGSNPPERR , " " , -1 , 1 } , { F_FIDPERR , " " , -1 , 1 } , { F_INTXCLRPERR , " " , -1 , 1 } , { F_MATAGPERR , " " , -1 , 1 } , { F_PIOTAGPERR , " " , -1 , 1 } , { F_RXCPLPERR , " " , -1 , 1 } , { F_RXWRPERR , " " , -1 , 1 } , { F_RPLPERR , " " , -1 , 1 } , { F_PCIESINT , " " , -1 , 1 } , { F_PCIEPINT , " " , -1 , 1 } , { F_UNXSPLCPLERR , " " , -1 , 0 } , { 0 } } ; static const struct intr_info t5_pcie_intr_info [ ] = { { F_MSTGRPPERR , " " , -1 , 1 } , { F_MSTTIMEOUTPERR , " " , -1 , 1 } , { F_MSIXSTIPERR , " " , -1 , 1 } , { F_MSIXADDRLPERR , " " , -1 , 1 } , { F_MSIXADDRHPERR , " " , -1 , 1 } , { F_MSIXDATAPERR , " " , -1 , 1 } , { F_MSIXDIPERR , " " , -1 , 1 } , { F_PIOCPLGRPPERR , " " , -1 , 1 } , { F_PIOREQGRPPERR , " " , -1 , 1 } , { F_TARTAGPERR , " " , -1 , 1 } , { F_MSTTAGQPERR , " " , -1 , 1 } , { F_CREQPERR , " " , -1 , 1 } , { F_CRSPPERR , " " , -1 , 1 } , { F_DREQWRPERR , " " , -1 , 1 } , { F_DREQPERR , " " , -1 , 1 } , { F_DRSPPERR , " " , -1 , 1 } , { F_HREQWRPERR , " " , -1 , 1 } , { F_HREQPERR , " " , -1 , 1 } , { F_HRSPPERR , " " , -1 , 1 } , { F_CFGSNPPERR , " " , -1 , 1 } , { F_FIDPERR , " " , -1 , 1 } , { F_VFIDPERR , " " , -1 , 1 } , { F_MAGRPPERR , " " , -1 , 1 } , { F_PIOTAGPERR , " " , -1 , 1 } , { F_IPRXHDRGRPPERR , " " , -1 , 1 } , { F_IPRXDATAGRPPERR , " " , -1 , 1 } , { F_RPLPERR , " " , -1 , 1 } , { F_IPSOTPERR , " " , -1 , 1 } , { F_TRGT1GRPPERR , " " , -1 , 1 } , { F_READRSPERR , " " , -1 , 0 } , { 0 } } ; int fat ; if ( is_t4 ( adapter ) ) fat = t4_handle_intr_status ( adapter , A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS , sysbus_intr_info ) + t4_handle_intr_status ( adapter , A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS , pcie_port_intr_info ) + t4_handle_intr_status ( adapter , A_PCIE_INT_CAUSE , pcie_intr_info ) ; else fat = t4_handle_intr_status ( adapter , A_PCIE_INT_CAUSE , t5_pcie_intr_info ) ; if ( fat ) t4_fatal_err ( adapter ) ; }
Interrupt handler for the PCIE module.
Interrupt handler for the PCIE module .