src/stlink-usb.c
/* See section C1.6 of the ARMv7-M Architecture Reference Manual */
See section C1.6 of the ARMv7-M Architecture Reference Manual
See section C1 . 6 of the ARMv7 - M Architecture Reference Manual
void _stlink_usb_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, reg *regp) {
    if (r_idx >= 0x1C && r_idx <= 0x1F) { 
        _stlink_usb_read_unsupported_reg(sl, 0x14, regp);
        val = (uint8_t) (val>>24);
        switch (r_idx) {
        case 0x1C:  
            val = (((uint32_t) val) << 24) | (((uint32_t) regp->faultmask) << 16) | (((uint32_t) regp->basepri) << 8) | ((uint32_t) regp->primask);
            break;
        case 0x1D:  
            val = (((uint32_t) regp->control) << 24) | (((uint32_t) val) << 16) | (((uint32_t) regp->basepri) << 8) | ((uint32_t) regp->primask);
            break;
        case 0x1E:  
            val = (((uint32_t) regp->control) << 24) | (((uint32_t) regp->faultmask) << 16) | (((uint32_t) val) << 8) | ((uint32_t) regp->primask);
            break;
        case 0x1F:  
            val = (((uint32_t) regp->control) << 24) | (((uint32_t) regp->faultmask) << 16) | (((uint32_t) regp->basepri) << 8) | ((uint32_t) val);
            break;
        }
        r_idx = 0x14;
    }
    write_uint32(sl->q_buf, val);
    _stlink_usb_write_mem32(sl, DCRDR, 4);
    sl->q_buf[0] = (unsigned char) r_idx;
    sl->q_buf[1] = 0;
    sl->q_buf[2] = 0x01;
    sl->q_buf[3] = 0;
    _stlink_usb_write_mem32(sl, DCRSR, 4);
}
void _stlink_usb_write_unsupported_reg ( stlink_t * sl , uint32_t val , int r_idx , reg * regp ) { if ( r_idx >= 0x1C && r_idx <= 0x1F ) { _stlink_usb_read_unsupported_reg ( sl , 0x14 , regp ) ; val = ( uint8_t ) ( val >> 24 ) ; switch ( r_idx ) { case 0x1C : val = ( ( ( uint32_t ) val ) << 24 ) | ( ( ( uint32_t ) regp -> faultmask ) << 16 ) | ( ( ( uint32_t ) regp -> basepri ) << 8 ) | ( ( uint32_t ) regp -> primask ) ; break ; case 0x1D : val = ( ( ( uint32_t ) regp -> control ) << 24 ) | ( ( ( uint32_t ) val ) << 16 ) | ( ( ( uint32_t ) regp -> basepri ) << 8 ) | ( ( uint32_t ) regp -> primask ) ; break ; case 0x1E : val = ( ( ( uint32_t ) regp -> control ) << 24 ) | ( ( ( uint32_t ) regp -> faultmask ) << 16 ) | ( ( ( uint32_t ) val ) << 8 ) | ( ( uint32_t ) regp -> primask ) ; break ; case 0x1F : val = ( ( ( uint32_t ) regp -> control ) << 24 ) | ( ( ( uint32_t ) regp -> faultmask ) << 16 ) | ( ( ( uint32_t ) regp -> basepri ) << 8 ) | ( ( uint32_t ) val ) ; break ; } r_idx = 0x14 ; } write_uint32 ( sl -> q_buf , val ) ; _stlink_usb_write_mem32 ( sl , DCRDR , 4 ) ; sl -> q_buf [ 0 ] = ( unsigned char ) r_idx ; sl -> q_buf [ 1 ] = 0 ; sl -> q_buf [ 2 ] = 0x01 ; sl -> q_buf [ 3 ] = 0 ; _stlink_usb_write_mem32 ( sl , DCRSR , 4 ) ; }
See section C1.6 of the ARMv7-M Architecture Reference Manual
See section C1 . 6 of the ARMv7 - M Architecture Reference Manual
/* primask, basepri, faultmask, or control */ /* These are held in the same register */ /* control */ /* faultmask */ /* basepri */ /* primask */