FreeBSD/sys/dev/cxgb/common/cxgb_t3_hw.c
/**
 *	t3_intr_enable - enable interrupts
 *	@adapter: the adapter whose interrupts should be enabled
 *
 *	Enable interrupts by setting the interrupt enable registers of the
 *	various HW modules and then enabling the top-level interrupt
 *	concentrator.
 */
enable interrupts
@adapter: the adapter whose interrupts should be enabled

Enable interrupts by setting the interrupt enable registers of the
various HW modules and then enabling the top-level interrupt
concentrator.
enable interrupts @adapter : the adapter whose interrupts should be enabled Enable interrupts by setting the interrupt enable registers of the various HW modules and then enabling the top - level interrupt concentrator .
void t3_intr_enable(adapter_t *adapter)
{
	static struct addr_val_pair intr_en_avp[] = {
		{ A_MC7_INT_ENABLE, MC7_INTR_MASK },
		{ A_MC7_INT_ENABLE - MC7_PMRX_BASE_ADDR + MC7_PMTX_BASE_ADDR,
			MC7_INTR_MASK },
		{ A_MC7_INT_ENABLE - MC7_PMRX_BASE_ADDR + MC7_CM_BASE_ADDR,
			MC7_INTR_MASK },
		{ A_MC5_DB_INT_ENABLE, MC5_INTR_MASK },
		{ A_ULPRX_INT_ENABLE, ULPRX_INTR_MASK },
		{ A_PM1_TX_INT_ENABLE, PMTX_INTR_MASK },
		{ A_PM1_RX_INT_ENABLE, PMRX_INTR_MASK },
		{ A_CIM_HOST_INT_ENABLE, CIM_INTR_MASK },
		{ A_MPS_INT_ENABLE, MPS_INTR_MASK },
	};
	adapter->slow_intr_mask = PL_INTR_MASK;
	t3_write_regs(adapter, intr_en_avp, ARRAY_SIZE(intr_en_avp), 0);
	t3_write_reg(adapter, A_TP_INT_ENABLE,
		     adapter->params.rev >= T3_REV_C ? 0x2bfffff : 0x3bfffff);
	t3_write_reg(adapter, A_SG_INT_ENABLE, SGE_INTR_MASK);
	if (adapter->params.rev > 0) {
		t3_write_reg(adapter, A_CPL_INTR_ENABLE,
			     CPLSW_INTR_MASK | F_CIM_OVFL_ERROR);
		t3_write_reg(adapter, A_ULPTX_INT_ENABLE,
			     ULPTX_INTR_MASK | F_PBL_BOUND_ERR_CH0 |
			     F_PBL_BOUND_ERR_CH1);
	} else {
		t3_write_reg(adapter, A_CPL_INTR_ENABLE, CPLSW_INTR_MASK);
		t3_write_reg(adapter, A_ULPTX_INT_ENABLE, ULPTX_INTR_MASK);
	}
	t3_write_reg(adapter, A_T3DBG_INT_ENABLE, calc_gpio_intr(adapter));
	if (is_pcie(adapter))
		t3_write_reg(adapter, A_PCIE_INT_ENABLE, PCIE_INTR_MASK);
	else
		t3_write_reg(adapter, A_PCIX_INT_ENABLE, PCIX_INTR_MASK);
	t3_write_reg(adapter, A_PL_INT_ENABLE0, adapter->slow_intr_mask);
	(void) t3_read_reg(adapter, A_PL_INT_ENABLE0);          
}
void t3_intr_enable ( adapter_t * adapter ) { static struct addr_val_pair intr_en_avp [ ] = { { A_MC7_INT_ENABLE , MC7_INTR_MASK } , { A_MC7_INT_ENABLE - MC7_PMRX_BASE_ADDR + MC7_PMTX_BASE_ADDR , MC7_INTR_MASK } , { A_MC7_INT_ENABLE - MC7_PMRX_BASE_ADDR + MC7_CM_BASE_ADDR , MC7_INTR_MASK } , { A_MC5_DB_INT_ENABLE , MC5_INTR_MASK } , { A_ULPRX_INT_ENABLE , ULPRX_INTR_MASK } , { A_PM1_TX_INT_ENABLE , PMTX_INTR_MASK } , { A_PM1_RX_INT_ENABLE , PMRX_INTR_MASK } , { A_CIM_HOST_INT_ENABLE , CIM_INTR_MASK } , { A_MPS_INT_ENABLE , MPS_INTR_MASK } , } ; adapter -> slow_intr_mask = PL_INTR_MASK ; t3_write_regs ( adapter , intr_en_avp , ARRAY_SIZE ( intr_en_avp ) , 0 ) ; t3_write_reg ( adapter , A_TP_INT_ENABLE , adapter -> params . rev >= T3_REV_C ? 0x2bfffff : 0x3bfffff ) ; t3_write_reg ( adapter , A_SG_INT_ENABLE , SGE_INTR_MASK ) ; if ( adapter -> params . rev > 0 ) { t3_write_reg ( adapter , A_CPL_INTR_ENABLE , CPLSW_INTR_MASK | F_CIM_OVFL_ERROR ) ; t3_write_reg ( adapter , A_ULPTX_INT_ENABLE , ULPTX_INTR_MASK | F_PBL_BOUND_ERR_CH0 | F_PBL_BOUND_ERR_CH1 ) ; } else { t3_write_reg ( adapter , A_CPL_INTR_ENABLE , CPLSW_INTR_MASK ) ; t3_write_reg ( adapter , A_ULPTX_INT_ENABLE , ULPTX_INTR_MASK ) ; } t3_write_reg ( adapter , A_T3DBG_INT_ENABLE , calc_gpio_intr ( adapter ) ) ; if ( is_pcie ( adapter ) ) t3_write_reg ( adapter , A_PCIE_INT_ENABLE , PCIE_INTR_MASK ) ; else t3_write_reg ( adapter , A_PCIX_INT_ENABLE , PCIX_INTR_MASK ) ; t3_write_reg ( adapter , A_PL_INT_ENABLE0 , adapter -> slow_intr_mask ) ; ( void ) t3_read_reg ( adapter , A_PL_INT_ENABLE0 ) ; }
t3_intr_enable - enable interrupts
      @adapter: the adapter whose interrupts should be enabled
t3_intr_enable - enable interrupts @adapter : the adapter whose interrupts should be enabled
/* flush */