kernels/linux-2.4.0/arch/mips/mm/r4xx0.c
/* If the addresses passed to these routines are valid, they are
 * either:
 *
 * 1) In KSEG0, so we can do a direct flush of the page.
 * 2) In KSEG2, and since every process can translate those
 *    addresses all the time in kernel mode we can do a direct
 *    flush.
 * 3) In KSEG1, no flush necessary.
 */
If the addresses passed to these routines are valid, they are
either.

1) In KSEG0, so we can do a direct flush of the page.
2) In KSEG2, and since every process can translate those
addresses all the time in kernel mode we can do a direct
flush.
3) In KSEG1, no flush necessary.
If the addresses passed to these routines are valid they are either . 1 ) In KSEG0 so we can do a direct flush of the page . 2 ) In KSEG2 and since every process can translate those addresses all the time in kernel mode we can do a direct flush . 3 ) In KSEG1 no flush necessary .
static void r4k_flush_page_to_ram_s16d16i16(struct page * page)
{
	unsigned long addr = (unsigned long) page_address(page) & PAGE_MASK;
	if ((addr >= KSEG0 && addr < KSEG1) || (addr >= KSEG2)) {
#ifdef DEBUG_CACHE
		printk("cram[%08lx]", addr);
#endif
		blast_scache16_page(addr);
	}
}
static void r4k_flush_page_to_ram_s16d16i16 ( struct page * page ) { unsigned long addr = ( unsigned long ) page_address ( page ) & PAGE_MASK ; if ( ( addr >= KSEG0 && addr < KSEG1 ) || ( addr >= KSEG2 ) ) { #ifdef DEBUG_CACHE printk ( " " , addr ) ; #endif blast_scache16_page ( addr ) ; } }
If the addresses passed to these routines are valid, they are
 either:
If the addresses passed to these routines are valid they are either :