kernels/linux-2.4.0/drivers/ieee1394/aic5800.c
/** Initialize the host adapter chip and corresponding data
    structures. We reset the chip, enable transmitter, receiver,
    the physical DMA units, cycle timer, cycle source, reception
    of selfid packets and initialize several other registers. */
Initialize the host adapter chip and corresponding data
structures. We reset the chip, enable transmitter, receiver,
the physical DMA units, cycle timer, cycle source, reception
of selfid packets and initialize several other registers.
Initialize the host adapter chip and corresponding data structures . We reset the chip enable transmitter receiver the physical DMA units cycle timer cycle source reception of selfid packets and initialize several other registers .
static int aic_initialize(struct hpsb_host *host)
{
    int i;
    struct aic5800 *aic = host->hostdata;
    aic->async_queue = NULL;
    spin_lock_init(&aic->async_queue_lock);
    reg_write( aic, misc_Reset, 0x37);
    udelay(10); 
    reg_write( aic, misc_Reset, 0);
    reg_write( aic, misc_Control, 0x82050003);
    reg_set_bits(aic, misc_PacketControl, 0x20);
    reg_write(aic, AT_InterruptSelect, 0x00F0001);
    reg_write(aic, AT_BranchSelect, 0x0100010);
    reg_write(aic, AT_WaitSelect, 0x00F0001);
    reg_write(aic, misc_ATRetries, reg_read(aic, misc_ATRetries) | 0x7);
    reg_write( aic, AR_ChannelControl, 0x80000000);
    i = 0;
    while (reg_read(aic, AR_ChannelStatus) & 0x400) {
	i++;
	if (i>100000) {
	    PRINT(KERN_ERR, aic->id, 
		  "Huh! Can't set AR_ChannelControl... card can not receive!");
	    break;
	}
    }
    (aic->AR_program)->control = ( DMA_CMD_INPUTLAST | DMA_KEY_STREAM0 
				   | DMA_INTR_ALWAYS | DMA_BRANCH_ALWAYS) 
	+ AIC5800_ARFIFO_SIZE;
    (aic->AR_program)->address = virt_to_bus(aic->rcv_page);
    (aic->AR_program)->branchAddress = virt_to_bus(aic->AR_program);
    (aic->AR_program)->status = AIC5800_ARFIFO_SIZE;
    (aic->AR_program+1)->control = DMA_CMD_STOP;
    (aic->AR_program+1)->address = 0;
    (aic->AR_program+1)->branchAddress = 0;
    (aic->AR_program+1)->status = 0;
    reg_write( aic, AR_CommandPtr, (u32) virt_to_bus(aic->AR_program)); 
    reg_write( aic, AR_ChannelControl, 0x80008000);
    reg_write(aic, misc_InterruptClear, 0xFFFFFFFF);
    reg_write(aic, misc_InterruptMask, 0xFFFFFFFF);
    return 1;
}
static int aic_initialize ( struct hpsb_host * host ) { int i ; struct aic5800 * aic = host -> hostdata ; aic -> async_queue = NULL ; spin_lock_init ( & aic -> async_queue_lock ) ; reg_write ( aic , misc_Reset , 0x37 ) ; udelay ( 10 ) ; reg_write ( aic , misc_Reset , 0 ) ; reg_write ( aic , misc_Control , 0x82050003 ) ; reg_set_bits ( aic , misc_PacketControl , 0x20 ) ; reg_write ( aic , AT_InterruptSelect , 0x00F0001 ) ; reg_write ( aic , AT_BranchSelect , 0x0100010 ) ; reg_write ( aic , AT_WaitSelect , 0x00F0001 ) ; reg_write ( aic , misc_ATRetries , reg_read ( aic , misc_ATRetries ) | 0x7 ) ; reg_write ( aic , AR_ChannelControl , 0x80000000 ) ; i = 0 ; while ( reg_read ( aic , AR_ChannelStatus ) & 0x400 ) { i ++ ; if ( i > 100000 ) { PRINT ( KERN_ERR , aic -> id , " " ) ; break ; } } ( aic -> AR_program ) -> control = ( DMA_CMD_INPUTLAST | DMA_KEY_STREAM0 | DMA_INTR_ALWAYS | DMA_BRANCH_ALWAYS ) + AIC5800_ARFIFO_SIZE ; ( aic -> AR_program ) -> address = virt_to_bus ( aic -> rcv_page ) ; ( aic -> AR_program ) -> branchAddress = virt_to_bus ( aic -> AR_program ) ; ( aic -> AR_program ) -> status = AIC5800_ARFIFO_SIZE ; ( aic -> AR_program + 1 ) -> control = DMA_CMD_STOP ; ( aic -> AR_program + 1 ) -> address = 0 ; ( aic -> AR_program + 1 ) -> branchAddress = 0 ; ( aic -> AR_program + 1 ) -> status = 0 ; reg_write ( aic , AR_CommandPtr , ( u32 ) virt_to_bus ( aic -> AR_program ) ) ; reg_write ( aic , AR_ChannelControl , 0x80008000 ) ; reg_write ( aic , misc_InterruptClear , 0xFFFFFFFF ) ; reg_write ( aic , misc_InterruptMask , 0xFFFFFFFF ) ; return 1 ; }
Initialize the host adapter chip and corresponding data
structures.
Initialize the host adapter chip and corresponding data structures .
/* Reset data structures */ /* Reset the chip */ // FIXME /* Enable Transmitter/Receiver, enable physDMA,
     * enable CycleTimer, cycleSource */ /* Enable reception of SelfID packets */ /* initialize AR DMA */ /* unset run bit */ /* here we should have 0 iterations because of the code
       in the DmaAR handler. However, to be sure we do it */ /* Enable Interrupts */ /*reg_write(aic, misc_InterruptMask, 0x00F1F03F);*/