Platform/ECM3532/M3/hw/csp/ecm3532/m3/csp/src/eta_csp_spi.c
/***************************************************************************/
/**
 *
 *  EtaCspSpiTransferInt - Start the SPI using Interrupt
 *
 *  @param instance the SPI number.
 *  @param pui8TxData pointer to TX Data Array
 *  @param ui32TxLen TX Data Length
 *  @param pui8RxData pointer to RX Data Array
 *  @param ui32RxLen RX Data Length
 *  @param chipsel select chip select 0-3.
 *
 ******************************************************************************/
Start the SPI using Interrupt
@param instance the SPI number.
Start the SPI using Interrupt @param instance the SPI number .
tEtaStatus EtaCspSpiTransferInt(tSpiNum iNum, uint8_t * pui8TxData, uint32_t ui32TxLen,
                        uint8_t * pui8RxData, uint32_t ui32RxLen,
                        tSpiChipSel spiChipSel, tSpiSequence iSpiSequence)
{
  tEtaStatus localStatus;
  if (ui32TxLen > (64*1024)-1)
  {
#ifdef ETA_CSP_SPI_DEBUG
    ETA_DIAGS_PRINTF ("ERROR: EtaCspSpiTransferPoll for iNum=%d exceeded max ui32TxLen of (64*1024)-1 with %d", iNum, ui32TxLen);
#endif
    return eEtaSpiInvalidConfig;
  }
  if (ui32RxLen > (64*1024)-1)
  {
#ifdef ETA_CSP_SPI_DEBUG
    ETA_DIAGS_PRINTF ("ERROR: EtaCspSpiTransferPoll for iNum=%d exceeded max ui32RxLen of (64*1024)-1 with %d", iNum, ui32RxLen);
#endif
    return eEtaSpiInvalidConfig;
  }
  if ((iNum == eSpi1) && ((spiChipSel == eSpiChipSel2) || (spiChipSel == eSpiChipSel3)))
  {
#ifdef ETA_CSP_SPI_DEBUG
    ETA_DIAGS_PRINTF ("ERROR: EtaCspSpiTransferPoll for iNum=%d invalid chipselect", iNum, spiChipSel);
#endif
    return eEtaSpiInvalidConfig;
  }
  if (iSpiSequence & eSpiSequenceFirstOnly)
  {
    if ( (localStatus = EtaCspSpiDonePoll(iNum) ) )
      return localStatus;
    REG_SPI_STATUS(iNum).V = BM_SPI_STATUS_START_BUSY | (spiChipSel<<BP_SPI_STATUS_CS_SEL) | BM_SPI_STATUS_HOLD_CS;
  }
  g_pEtaCspSpiCmd[iNum]->pui8TxData = pui8TxData;
  g_pEtaCspSpiCmd[iNum]->pui8RxData = pui8RxData;
  g_pEtaCspSpiCmd[iNum]->ui32TxLen  = ui32TxLen;
  g_pEtaCspSpiCmd[iNum]->ui32RxLen  = ui32RxLen;
  g_pEtaCspSpiCmd[iNum]->ui8RxIntSize = 14;
  g_pEtaCspSpiCmd[iNum]->ui8TxIntSize = 14;
  g_pEtaCspSpiCmd[iNum]->bCmdActive = 1;
  g_pEtaCspSpiCmd[iNum]->iSpiSequence = iSpiSequence;
  g_pEtaCspSpiCmd[iNum]->spiStatus = eEtaFailure;
  if (ui32TxLen) 
  {
    REG_SPI_RXDROP_CNT(iNum).V = ui32TxLen;
    REG_SPI_CONFIG(iNum).BF.FIFO_LEVEL_TRIG = g_pEtaCspSpiCmd[iNum]->ui8TxIntSize;
  }
  else if (ui32RxLen) 
  {
    REG_SPI_TX_DUMMY_BYTE_CNT(iNum).V = ui32RxLen;
    if (iSpiSequence & eSpiSequenceLastOnly)
    {
      REG_SPI_STATUS(iNum).V = 0;
    }
    REG_SPI_CONFIG(iNum).BF.FIFO_LEVEL_TRIG = g_pEtaCspSpiCmd[iNum]->ui8RxIntSize;
  }
  else 
  {
    if (iSpiSequence & eSpiSequenceLastOnly)
    {
      REG_SPI_STATUS(iNum).V = 0;
    }
  }
  REGN_W4(iNum, SPI_INT_EN, TXFIFO_HAS_LEVEL_SPACE_EN0,       (ui32TxLen != 0),
                            RX_FIFO_HIT_LEVEL_EN0,            (ui32RxLen != 0),
                            XMIT_COMPLETE_EN0,                ((iSpiSequence & eSpiSequenceLastOnly) ? 0 : 1) ,
                            CMD_IS_DONE_EN0,                  ((iSpiSequence & eSpiSequenceLastOnly) ? 1 : 0) );
  return eEtaSuccess;
}
tEtaStatus EtaCspSpiTransferInt ( tSpiNum iNum , uint8_t * pui8TxData , uint32_t ui32TxLen , uint8_t * pui8RxData , uint32_t ui32RxLen , tSpiChipSel spiChipSel , tSpiSequence iSpiSequence ) { tEtaStatus localStatus ; if ( ui32TxLen > ( 64 * 1024 ) - 1 ) { #ifdef ETA_CSP_SPI_DEBUG ETA_DIAGS_PRINTF ( " " , iNum , ui32TxLen ) ; #endif return eEtaSpiInvalidConfig ; } if ( ui32RxLen > ( 64 * 1024 ) - 1 ) { #ifdef ETA_CSP_SPI_DEBUG ETA_DIAGS_PRINTF ( " " , iNum , ui32RxLen ) ; #endif return eEtaSpiInvalidConfig ; } if ( ( iNum == eSpi1 ) && ( ( spiChipSel == eSpiChipSel2 ) || ( spiChipSel == eSpiChipSel3 ) ) ) { #ifdef ETA_CSP_SPI_DEBUG ETA_DIAGS_PRINTF ( " " , iNum , spiChipSel ) ; #endif return eEtaSpiInvalidConfig ; } if ( iSpiSequence & eSpiSequenceFirstOnly ) { if ( ( localStatus = EtaCspSpiDonePoll ( iNum ) ) ) return localStatus ; REG_SPI_STATUS ( iNum ) . V = BM_SPI_STATUS_START_BUSY | ( spiChipSel << BP_SPI_STATUS_CS_SEL ) | BM_SPI_STATUS_HOLD_CS ; } g_pEtaCspSpiCmd [ iNum ] -> pui8TxData = pui8TxData ; g_pEtaCspSpiCmd [ iNum ] -> pui8RxData = pui8RxData ; g_pEtaCspSpiCmd [ iNum ] -> ui32TxLen = ui32TxLen ; g_pEtaCspSpiCmd [ iNum ] -> ui32RxLen = ui32RxLen ; g_pEtaCspSpiCmd [ iNum ] -> ui8RxIntSize = 14 ; g_pEtaCspSpiCmd [ iNum ] -> ui8TxIntSize = 14 ; g_pEtaCspSpiCmd [ iNum ] -> bCmdActive = 1 ; g_pEtaCspSpiCmd [ iNum ] -> iSpiSequence = iSpiSequence ; g_pEtaCspSpiCmd [ iNum ] -> spiStatus = eEtaFailure ; if ( ui32TxLen ) { REG_SPI_RXDROP_CNT ( iNum ) . V = ui32TxLen ; REG_SPI_CONFIG ( iNum ) . BF . FIFO_LEVEL_TRIG = g_pEtaCspSpiCmd [ iNum ] -> ui8TxIntSize ; } else if ( ui32RxLen ) { REG_SPI_TX_DUMMY_BYTE_CNT ( iNum ) . V = ui32RxLen ; if ( iSpiSequence & eSpiSequenceLastOnly ) { REG_SPI_STATUS ( iNum ) . V = 0 ; } REG_SPI_CONFIG ( iNum ) . BF . FIFO_LEVEL_TRIG = g_pEtaCspSpiCmd [ iNum ] -> ui8RxIntSize ; } else { if ( iSpiSequence & eSpiSequenceLastOnly ) { REG_SPI_STATUS ( iNum ) . V = 0 ; } } REGN_W4 ( iNum , SPI_INT_EN , TXFIFO_HAS_LEVEL_SPACE_EN0 , ( ui32TxLen != 0 ) , RX_FIFO_HIT_LEVEL_EN0 , ( ui32RxLen != 0 ) , XMIT_COMPLETE_EN0 , ( ( iSpiSequence & eSpiSequenceLastOnly ) ? 0 : 1 ) , CMD_IS_DONE_EN0 , ( ( iSpiSequence & eSpiSequenceLastOnly ) ? 1 : 0 ) ) ; return eEtaSuccess ; }
EtaCspSpiTransferInt - Start the SPI using Interrupt
  @param instance the SPI number.
EtaCspSpiTransferInt - Start the SPI using Interrupt @param instance the SPI number .
// If it is first, start command // Make sure previous command is done (optional) // Start command // Setup global array // If we have TX, lets process it. // Deal with TX first // We'll drop ui32TxLen of data (garbage receive data during TX) // No TX, just RX // If it is Last, end command // At this point, all TX is in the queue. Remove hold // No TX, No RX // If it is Last, end command // At this point, all TX is in the queue. Remove hold // Setup next expected interrupt