FreeBSD/sys/dev/drm2/i915/intel_pm.c
/* Starting with Haswell, we have different power wells for
 * different parts of the GPU. This attempts to enable them all.
 */
Starting with Haswell, we have different power wells for
different parts of the GPU. This attempts to enable them all.
Starting with Haswell we have different power wells for different parts of the GPU . This attempts to enable them all .
void intel_init_power_wells(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	unsigned long power_wells[] = {
		HSW_PWR_WELL_CTL1,
		HSW_PWR_WELL_CTL2,
		HSW_PWR_WELL_CTL4
	};
	int i;
	if (!IS_HASWELL(dev))
		return;
	DRM_LOCK(dev);
	for (i = 0; i < ARRAY_SIZE(power_wells); i++) {
		int well = I915_READ(power_wells[i]);
		if ((well & HSW_PWR_WELL_STATE) == 0) {
			I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
			if (wait_for((I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE), 20))
				DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);
		}
	}
	DRM_UNLOCK(dev);
}
void intel_init_power_wells ( struct drm_device * dev ) { struct drm_i915_private * dev_priv = dev -> dev_private ; unsigned long power_wells [ ] = { HSW_PWR_WELL_CTL1 , HSW_PWR_WELL_CTL2 , HSW_PWR_WELL_CTL4 } ; int i ; if ( ! IS_HASWELL ( dev ) ) return ; DRM_LOCK ( dev ) ; for ( i = 0 ; i < ARRAY_SIZE ( power_wells ) ; i ++ ) { int well = I915_READ ( power_wells [ i ] ) ; if ( ( well & HSW_PWR_WELL_STATE ) == 0 ) { I915_WRITE ( power_wells [ i ] , well & HSW_PWR_WELL_ENABLE ) ; if ( wait_for ( ( I915_READ ( power_wells [ i ] ) & HSW_PWR_WELL_STATE ) , 20 ) ) DRM_ERROR ( " \n " , power_wells [ i ] ) ; } } DRM_UNLOCK ( dev ) ; }
Starting with Haswell, we have different power wells for
 different parts of the GPU.
Starting with Haswell we have different power wells for different parts of the GPU .