qemu/hw/intc/arm_gicv3_kvm.c
/* Read a bitmap register group from the kernel VGIC. */
Read a bitmap register group from the kernel VGIC.
Read a bitmap register group from the kernel VGIC .
static void kvm_dist_getbmp(GICv3State *s, uint32_t offset, uint32_t *bmp)
{
    uint32_t reg;
    int irq;
    offset += (GIC_INTERNAL * 1) / 8;
    for_each_dist_irq_reg(irq, s->num_irq, 1) {
        kvm_gicd_access(s, offset, &reg, false);
        *gic_bmp_ptr32(bmp, irq) = reg;
        offset += 4;
    }
}
static void kvm_dist_getbmp ( GICv3State * s , uint32_t offset , uint32_t * bmp ) { uint32_t reg ; int irq ; offset += ( GIC_INTERNAL * 1 ) / 8 ; for_each_dist_irq_reg ( irq , s -> num_irq , 1 ) { kvm_gicd_access ( s , offset , & reg , false ) ; * gic_bmp_ptr32 ( bmp , irq ) = reg ; offset += 4 ; } }
Read a bitmap register group from the kernel VGIC.
Read a bitmap register group from the kernel VGIC .
/* For the KVM GICv3, affinity routing is always enabled, and the
     * GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/
     * GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding
     * functionality is replaced by the GICR registers. It doesn't need to sync
     * them. So it should increase the offset to skip GIC_INTERNAL irqs.
     * This matches the for_each_dist_irq_reg() macro which also skips the
     * first GIC_INTERNAL irqs.
     */