drivers/arm/gic/arm_gic.c
/*******************************************************************************
 * Per cpu gic distributor setup which will be done by all cpus after a cold
 * boot/hotplug. This marks out the secure interrupts & enables them.
 ******************************************************************************/
Per cpu gic distributor setup which will be done by all cpus after a cold
boot/hotplug. This marks out the secure interrupts & enables them.
Per cpu gic distributor setup which will be done by all cpus after a cold boot / hotplug . This marks out the secure interrupts & enables them .
void arm_gic_pcpu_distif_setup(void)
{
	unsigned int index, irq_num, sec_ppi_sgi_mask;
	assert(g_gicd_base);
	for (index = 0; index < 32; index += 4) {
		gicd_write_ipriorityr(g_gicd_base, index,
				GICD_IPRIORITYR_DEF_VAL);
	}
	assert(g_irq_sec_ptr);
	sec_ppi_sgi_mask = 0;
	gicd_write_igroupr(g_gicd_base, 0, 0);
	for (index = 0; index < g_num_irqs; index++) {
		irq_num = g_irq_sec_ptr[index];
		if (irq_num < MIN_SPI_ID) {
			sec_ppi_sgi_mask |= 1U << irq_num;
			gicd_set_ipriorityr(g_gicd_base, irq_num,
				GIC_HIGHEST_SEC_PRIORITY);
			gicd_set_isenabler(g_gicd_base, irq_num);
		}
	}
	gicd_write_igroupr(g_gicd_base, 0, ~sec_ppi_sgi_mask);
}
void arm_gic_pcpu_distif_setup ( void ) { unsigned int index , irq_num , sec_ppi_sgi_mask ; assert ( g_gicd_base ) ; for ( index = 0 ; index < 32 ; index += 4 ) { gicd_write_ipriorityr ( g_gicd_base , index , GICD_IPRIORITYR_DEF_VAL ) ; } assert ( g_irq_sec_ptr ) ; sec_ppi_sgi_mask = 0 ; gicd_write_igroupr ( g_gicd_base , 0 , 0 ) ; for ( index = 0 ; index < g_num_irqs ; index ++ ) { irq_num = g_irq_sec_ptr [ index ] ; if ( irq_num < MIN_SPI_ID ) { sec_ppi_sgi_mask |= 1U << irq_num ; gicd_set_ipriorityr ( g_gicd_base , irq_num , GIC_HIGHEST_SEC_PRIORITY ) ; gicd_set_isenabler ( g_gicd_base , irq_num ) ; } } gicd_write_igroupr ( g_gicd_base , 0 , ~ sec_ppi_sgi_mask ) ; }
Per cpu gic distributor setup which will be done by all cpus after a cold
 boot/hotplug.
Per cpu gic distributor setup which will be done by all cpus after a cold boot / hotplug .
/* Setup PPI priorities doing four at a time */ /* Ensure all SGIs and PPIs are Group0 to begin with */ /* We have an SGI or a PPI */ /*
	 * Invert the bitmask to create a mask for non-secure PPIs and
	 * SGIs. Program the GICD_IGROUPR0 with this bit mask. This write will
	 * update the GICR_IGROUPR0 as well in case we are running on a GICv3
	 * system. This is critical if GICD_CTLR.ARE_NS=1.
	 */