plat/nvidia/tegra/common/tegra_gic.c
/*******************************************************************************
 * Enable secure interrupts and set the priority mask register to allow all
 * interrupts to trickle in.
 ******************************************************************************/
Enable secure interrupts and set the priority mask register to allow all
interrupts to trickle in.
Enable secure interrupts and set the priority mask register to allow all interrupts to trickle in .
static void tegra_gic_cpuif_setup(uint32_t gicc_base)
{
	uint32_t val;
	val = ENABLE_GRP0 | ENABLE_GRP1 | FIQ_EN | FIQ_BYP_DIS_GRP0;
	val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
	gicc_write_ctlr(gicc_base, val);
	gicc_write_pmr(gicc_base, GIC_PRI_MASK);
}
static void tegra_gic_cpuif_setup ( uint32_t gicc_base ) { uint32_t val ; val = ENABLE_GRP0 | ENABLE_GRP1 | FIQ_EN | FIQ_BYP_DIS_GRP0 ; val |= IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1 ; gicc_write_ctlr ( gicc_base , val ) ; gicc_write_pmr ( gicc_base , GIC_PRI_MASK ) ; }
Enable secure interrupts and set the priority mask register to allow all
 interrupts to trickle in.
Enable secure interrupts and set the priority mask register to allow all interrupts to trickle in .