FreeBSD/sys/dev/cxgbe/common/t4_hw.c
/**
 *	t4_slow_intr_handler - control path interrupt handler
 *	@adapter: the adapter
 *
 *	T4 interrupt handler for non-data global interrupt events, e.g., errors.
 *	The designation 'slow' is because it involves register reads, while
 *	data interrupts typically don't involve any MMIOs.
 */
control path interrupt handler
@adapter: the adapter

T4 interrupt handler for non-data global interrupt events, e.g., errors.
The designation 'slow' is because it involves register reads, while
data interrupts typically don't involve any MMIOs.
control path interrupt handler @adapter : the adapter T4 interrupt handler for non - data global interrupt events e . g . errors . The designation ' slow ' is because it involves register reads while data interrupts typically don ' t involve any MMIOs .
int t4_slow_intr_handler(struct adapter *adapter)
{
	u32 cause = t4_read_reg(adapter, A_PL_INT_CAUSE);
	if (!(cause & GLBL_INTR_MASK))
		return 0;
	if (cause & F_CIM)
		cim_intr_handler(adapter);
	if (cause & F_MPS)
		mps_intr_handler(adapter);
	if (cause & F_NCSI)
		ncsi_intr_handler(adapter);
	if (cause & F_PL)
		pl_intr_handler(adapter);
	if (cause & F_SMB)
		smb_intr_handler(adapter);
	if (cause & F_MAC0)
		xgmac_intr_handler(adapter, 0);
	if (cause & F_MAC1)
		xgmac_intr_handler(adapter, 1);
	if (cause & F_MAC2)
		xgmac_intr_handler(adapter, 2);
	if (cause & F_MAC3)
		xgmac_intr_handler(adapter, 3);
	if (cause & F_PCIE)
		pcie_intr_handler(adapter);
	if (cause & F_MC0)
		mem_intr_handler(adapter, MEM_MC);
	if (is_t5(adapter) && (cause & F_MC1))
		mem_intr_handler(adapter, MEM_MC1);
	if (cause & F_EDC0)
		mem_intr_handler(adapter, MEM_EDC0);
	if (cause & F_EDC1)
		mem_intr_handler(adapter, MEM_EDC1);
	if (cause & F_LE)
		le_intr_handler(adapter);
	if (cause & F_TP)
		tp_intr_handler(adapter);
	if (cause & F_MA)
		ma_intr_handler(adapter);
	if (cause & F_PM_TX)
		pmtx_intr_handler(adapter);
	if (cause & F_PM_RX)
		pmrx_intr_handler(adapter);
	if (cause & F_ULP_RX)
		ulprx_intr_handler(adapter);
	if (cause & F_CPL_SWITCH)
		cplsw_intr_handler(adapter);
	if (cause & F_SGE)
		sge_intr_handler(adapter);
	if (cause & F_ULP_TX)
		ulptx_intr_handler(adapter);
	t4_write_reg(adapter, A_PL_INT_CAUSE, cause & GLBL_INTR_MASK);
	(void)t4_read_reg(adapter, A_PL_INT_CAUSE); 
	return 1;
}
int t4_slow_intr_handler ( struct adapter * adapter ) { u32 cause = t4_read_reg ( adapter , A_PL_INT_CAUSE ) ; if ( ! ( cause & GLBL_INTR_MASK ) ) return 0 ; if ( cause & F_CIM ) cim_intr_handler ( adapter ) ; if ( cause & F_MPS ) mps_intr_handler ( adapter ) ; if ( cause & F_NCSI ) ncsi_intr_handler ( adapter ) ; if ( cause & F_PL ) pl_intr_handler ( adapter ) ; if ( cause & F_SMB ) smb_intr_handler ( adapter ) ; if ( cause & F_MAC0 ) xgmac_intr_handler ( adapter , 0 ) ; if ( cause & F_MAC1 ) xgmac_intr_handler ( adapter , 1 ) ; if ( cause & F_MAC2 ) xgmac_intr_handler ( adapter , 2 ) ; if ( cause & F_MAC3 ) xgmac_intr_handler ( adapter , 3 ) ; if ( cause & F_PCIE ) pcie_intr_handler ( adapter ) ; if ( cause & F_MC0 ) mem_intr_handler ( adapter , MEM_MC ) ; if ( is_t5 ( adapter ) && ( cause & F_MC1 ) ) mem_intr_handler ( adapter , MEM_MC1 ) ; if ( cause & F_EDC0 ) mem_intr_handler ( adapter , MEM_EDC0 ) ; if ( cause & F_EDC1 ) mem_intr_handler ( adapter , MEM_EDC1 ) ; if ( cause & F_LE ) le_intr_handler ( adapter ) ; if ( cause & F_TP ) tp_intr_handler ( adapter ) ; if ( cause & F_MA ) ma_intr_handler ( adapter ) ; if ( cause & F_PM_TX ) pmtx_intr_handler ( adapter ) ; if ( cause & F_PM_RX ) pmrx_intr_handler ( adapter ) ; if ( cause & F_ULP_RX ) ulprx_intr_handler ( adapter ) ; if ( cause & F_CPL_SWITCH ) cplsw_intr_handler ( adapter ) ; if ( cause & F_SGE ) sge_intr_handler ( adapter ) ; if ( cause & F_ULP_TX ) ulptx_intr_handler ( adapter ) ; t4_write_reg ( adapter , A_PL_INT_CAUSE , cause & GLBL_INTR_MASK ) ; ( void ) t4_read_reg ( adapter , A_PL_INT_CAUSE ) ; return 1 ; }
t4_slow_intr_handler - control path interrupt handler
      @adapter: the adapter
t4_slow_intr_handler - control path interrupt handler @adapter : the adapter
/* Clear the interrupts just processed for which we are the master. */ /* flush */