FreeBSD/sys/arm/freescale/imx/imx6_ccm.c
/*
 * Until we have a fully functional ccm driver which implements the fdt_clock
 * interface, use the age-old workaround of unconditionally enabling the clocks
 * for devices we might need to use.  The SoC defaults to most clocks enabled,
 * but the rom boot code and u-boot disable a few of them.  We turn on only
 * what's needed to run the chip plus devices we have drivers for, and turn off
 * devices we don't yet have drivers for.  (Note that USB is not turned on here
 * because that is one we do when the driver asks for it.)
 */
Until we have a fully functional ccm driver which implements the fdt_clock
interface, use the age-old workaround of unconditionally enabling the clocks
for devices we might need to use.  The SoC defaults to most clocks enabled,
but the rom boot code and u-boot disable a few of them.  We turn on only
what's needed to run the chip plus devices we have drivers for, and turn off
devices we don't yet have drivers for.  (Note that USB is not turned on here
because that is one we do when the driver asks for it.)
Until we have a fully functional ccm driver which implements the fdt_clock interface use the age - old workaround of unconditionally enabling the clocks for devices we might need to use . The SoC defaults to most clocks enabled but the rom boot code and u - boot disable a few of them . We turn on only what ' s needed to run the chip plus devices we have drivers for and turn off devices we don ' t yet have drivers for . ( Note that USB is not turned on here because that is one we do when the driver asks for it . )
static void
ccm_init_gates(struct ccm_softc *sc)
{
	uint32_t reg;
	reg = CCGR0_AIPS_TZ1 | CCGR0_AIPS_TZ2 | CCGR0_ABPHDMA;
	WR4(sc, CCM_CCGR0, reg);
	reg = CCGR1_ENET | CCGR1_GPT;
	WR4(sc, CCM_CCGR1, reg);
	reg = CCGR2_I2C1 | CCGR2_I2C2 | CCGR2_I2C3 | CCGR2_IIM |
	    CCGR2_IOMUX_IPT | CCGR2_IPMUX1 | CCGR2_IPMUX2 | CCGR2_IPMUX3 |
	    CCGR2_IPSYNC_IP2APB_TZASC1 | CCGR2_IPSYNC_IP2APB_TZASC2 |
	    CCGR2_IPSYNC_VDOA;
	WR4(sc, CCM_CCGR2, reg);
	reg = CCGR3_OCRAM | CCGR3_MMDC_CORE_IPG |
	    CCGR3_MMDC_CORE_ACLK_FAST | CCGR3_CG11 | CCGR3_CG13;
	WR4(sc, CCM_CCGR3, reg);
	reg = CCGR4_PL301_MX6QFAST1_S133 |
	    CCGR4_PL301_MX6QPER1_BCH | CCGR4_PL301_MX6QPER2_MAIN;
	WR4(sc, CCM_CCGR4, reg);
	reg = CCGR5_SDMA | CCGR5_SSI1 | CCGR5_SSI2 | CCGR5_SSI3 |
	    CCGR5_UART | CCGR5_UART_SERIAL;
	WR4(sc, CCM_CCGR5, reg);
	reg = CCGR6_USBOH3 | CCGR6_USDHC1 | CCGR6_USDHC2 |
	    CCGR6_USDHC3 | CCGR6_USDHC4;
	WR4(sc, CCM_CCGR6, reg);
}
static void ccm_init_gates ( struct ccm_softc * sc ) { uint32_t reg ; reg = CCGR0_AIPS_TZ1 | CCGR0_AIPS_TZ2 | CCGR0_ABPHDMA ; WR4 ( sc , CCM_CCGR0 , reg ) ; reg = CCGR1_ENET | CCGR1_GPT ; WR4 ( sc , CCM_CCGR1 , reg ) ; reg = CCGR2_I2C1 | CCGR2_I2C2 | CCGR2_I2C3 | CCGR2_IIM | CCGR2_IOMUX_IPT | CCGR2_IPMUX1 | CCGR2_IPMUX2 | CCGR2_IPMUX3 | CCGR2_IPSYNC_IP2APB_TZASC1 | CCGR2_IPSYNC_IP2APB_TZASC2 | CCGR2_IPSYNC_VDOA ; WR4 ( sc , CCM_CCGR2 , reg ) ; reg = CCGR3_OCRAM | CCGR3_MMDC_CORE_IPG | CCGR3_MMDC_CORE_ACLK_FAST | CCGR3_CG11 | CCGR3_CG13 ; WR4 ( sc , CCM_CCGR3 , reg ) ; reg = CCGR4_PL301_MX6QFAST1_S133 | CCGR4_PL301_MX6QPER1_BCH | CCGR4_PL301_MX6QPER2_MAIN ; WR4 ( sc , CCM_CCGR4 , reg ) ; reg = CCGR5_SDMA | CCGR5_SSI1 | CCGR5_SSI2 | CCGR5_SSI3 | CCGR5_UART | CCGR5_UART_SERIAL ; WR4 ( sc , CCM_CCGR5 , reg ) ; reg = CCGR6_USBOH3 | CCGR6_USDHC1 | CCGR6_USDHC2 | CCGR6_USDHC3 | CCGR6_USDHC4 ; WR4 ( sc , CCM_CCGR6 , reg ) ; }
Until we have a fully functional ccm driver which implements the fdt_clock
 interface, use the age-old workaround of unconditionally enabling the clocks
 for devices we might need to use.
Until we have a fully functional ccm driver which implements the fdt_clock interface use the age - old workaround of unconditionally enabling the clocks for devices we might need to use .
/* ahpbdma, aipstz 1 & 2 busses */ /* gpt, enet */ /* ipmux & ipsync (bridges), iomux, i2c */ /* DDR memory controller */ /* pl301 bus crossbar */ /* uarts, ssi, sdma */ /* usdhc 1-4, usboh3 */