FreeBSD/sys/sparc64/sparc64/cheetah.c
/*
 * CPU-specific initialization for Sun Cheetah and later CPUs
 */
CPU-specific initialization for Sun Cheetah and later CPUs
CPU - specific initialization for Sun Cheetah and later CPUs
void
cheetah_init(u_int cpu_impl)
{
	u_long val;
	stxa(AA_DMMU_TSB_PEXT_REG, ASI_DMMU, 0);
	stxa(AA_IMMU_TSB_PEXT_REG, ASI_IMMU, 0);
	membar(Sync);
	stxa(AA_DMMU_TSB_SEXT_REG, ASI_DMMU, 0);
	membar(Sync);
	stxa(AA_DMMU_TSB_NEXT_REG, ASI_DMMU, 0);
	stxa(AA_IMMU_TSB_NEXT_REG, ASI_IMMU, 0);
	membar(Sync);
	stxa(TLB_DEMAP_ALL, ASI_DMMU_DEMAP, 0);
	membar(Sync);
	val = (TS_4M << TLB_PCXR_N_PGSZ0_SHIFT) |
	    (TS_8K << TLB_PCXR_N_PGSZ1_SHIFT) |
	    (TS_4M << TLB_PCXR_P_PGSZ0_SHIFT) |
	    (TS_8K << TLB_PCXR_P_PGSZ1_SHIFT);
	if (cpu_impl == CPU_IMPL_ULTRASPARCIVp)
		val |= (TS_8K << TLB_PCXR_N_PGSZ_I_SHIFT) |
		    (TS_8K << TLB_PCXR_P_PGSZ_I_SHIFT);
	stxa(AA_DMMU_PCXR, ASI_DMMU, val);
	val = (TS_4M << TLB_SCXR_S_PGSZ0_SHIFT) |
	    (TS_8K << TLB_SCXR_S_PGSZ1_SHIFT);
	stxa(AA_DMMU_SCXR, ASI_DMMU, val);
	flush(KERNBASE);
	val = rd(asr18) & ~DCR_IFPOE;
	if (cpu_impl == CPU_IMPL_ULTRASPARCIVp) {
		val = (val & ~DCR_BPM_MASK) | DCR_BPM_PC;
		val &= ~DCR_DTPE;
	}
	wr(asr18, val, 0);
}
void cheetah_init ( u_int cpu_impl ) { u_long val ; stxa ( AA_DMMU_TSB_PEXT_REG , ASI_DMMU , 0 ) ; stxa ( AA_IMMU_TSB_PEXT_REG , ASI_IMMU , 0 ) ; membar ( Sync ) ; stxa ( AA_DMMU_TSB_SEXT_REG , ASI_DMMU , 0 ) ; membar ( Sync ) ; stxa ( AA_DMMU_TSB_NEXT_REG , ASI_DMMU , 0 ) ; stxa ( AA_IMMU_TSB_NEXT_REG , ASI_IMMU , 0 ) ; membar ( Sync ) ; stxa ( TLB_DEMAP_ALL , ASI_DMMU_DEMAP , 0 ) ; membar ( Sync ) ; val = ( TS_4M << TLB_PCXR_N_PGSZ0_SHIFT ) | ( TS_8K << TLB_PCXR_N_PGSZ1_SHIFT ) | ( TS_4M << TLB_PCXR_P_PGSZ0_SHIFT ) | ( TS_8K << TLB_PCXR_P_PGSZ1_SHIFT ) ; if ( cpu_impl == CPU_IMPL_ULTRASPARCIVp ) val |= ( TS_8K << TLB_PCXR_N_PGSZ_I_SHIFT ) | ( TS_8K << TLB_PCXR_P_PGSZ_I_SHIFT ) ; stxa ( AA_DMMU_PCXR , ASI_DMMU , val ) ; val = ( TS_4M << TLB_SCXR_S_PGSZ0_SHIFT ) | ( TS_8K << TLB_SCXR_S_PGSZ1_SHIFT ) ; stxa ( AA_DMMU_SCXR , ASI_DMMU , val ) ; flush ( KERNBASE ) ; val = rd ( asr18 ) & ~ DCR_IFPOE ; if ( cpu_impl == CPU_IMPL_ULTRASPARCIVp ) { val = ( val & ~ DCR_BPM_MASK ) | DCR_BPM_PC ; val &= ~ DCR_DTPE ; } wr ( asr18 , val , 0 ) ; }
CPU-specific initialization for Sun Cheetah and later CPUs
CPU - specific initialization for Sun Cheetah and later CPUs
/* Ensure the TSB Extension Registers hold 0 as TSB_Base. */ /*
	 * NB: the secondary context was removed from the iMMU.
	 */ /*
	 * Configure the first large dTLB to hold 4MB pages (e.g. for direct
	 * mappings) for all three contexts and ensure the second one is set
	 * up to hold 8k pages for them.  Note that this is constraint by
	 * US-IV+, whose large dTLBs can only hold entries of certain page
	 * sizes each.
	 * For US-IV+, additionally ensure that the large iTLB is set up to
	 * hold 8k pages for nucleus and primary context (still no secondary
	 * iMMU context.
	 * NB: according to documentation, changing the page size of the same
	 * context requires a context demap before changing the corresponding
	 * page size, but we hardly can flush our locked pages here, so we use
	 * a demap all instead.
	 */ /*
	 * Ensure DCR_IFPOE is disabled as long as we haven't implemented
	 * support for it (if ever) as most if not all firmware versions
	 * apparently turn it on.  Not making use of DCR_IFPOE should also
	 * avoid Cheetah erratum #109.
	 */ /*
		 * Ensure the branch prediction mode is set to PC indexing
		 * in order to work around US-IV+ erratum #2.
		 */ /*
		 * XXX disable dTLB parity error reporting as otherwise we
		 * get seemingly false positives when copying in the user
		 * window by simulating a fill trap on return to usermode in
		 * case single issue is disabled, which thus appears to be
		 * a CPU bug.
		 */