FreeBSD/sys/i386/i386/pmap.c
/*
 * After changing the page size for the specified virtual address in the page
 * table, flush the corresponding entries from the processor's TLB.  Only the
 * calling processor's TLB is affected.
 *
 * The calling thread must be pinned to a processor.
 */
After changing the page size for the specified virtual address in the page
table, flush the corresponding entries from the processor's TLB.  Only the
calling processor's TLB is affected.

The calling thread must be pinned to a processor.
After changing the page size for the specified virtual address in the page table flush the corresponding entries from the processor ' s TLB . Only the calling processor ' s TLB is affected . The calling thread must be pinned to a processor .
static void
pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
{
	u_long cr4;
	if ((newpde & PG_PS) == 0)
		invlpg(va);
	else if ((newpde & PG_G) == 0)
		invltlb();
	else {
		cr4 = rcr4();
		load_cr4(cr4 & ~CR4_PGE);
		load_cr4(cr4 | CR4_PGE);
	}
}
static void pmap_update_pde_invalidate ( vm_offset_t va , pd_entry_t newpde ) { u_long cr4 ; if ( ( newpde & PG_PS ) == 0 ) invlpg ( va ) ; else if ( ( newpde & PG_G ) == 0 ) invltlb ( ) ; else { cr4 = rcr4 ( ) ; load_cr4 ( cr4 & ~ CR4_PGE ) ; load_cr4 ( cr4 | CR4_PGE ) ; } }
After changing the page size for the specified virtual address in the page
 table, flush the corresponding entries from the processor's TLB.
After changing the page size for the specified virtual address in the page table flush the corresponding entries from the processor ' s TLB .
/* Demotion: flush a specific 2MB page mapping. */ /*
		 * Promotion: flush every 4KB page mapping from the TLB
		 * because there are too many to flush individually.
		 */ /*
		 * Promotion: flush every 4KB page mapping from the TLB,
		 * including any global (PG_G) mappings.
		 */ /*
		 * Although preemption at this point could be detrimental to
		 * performance, it would not lead to an error.  PG_G is simply
		 * ignored if CR4.PGE is clear.  Moreover, in case this block
		 * is re-entered, the load_cr4() either above or below will
		 * modify CR4.PGE flushing the TLB.
		 */