linux/arch/x86/kernel/cpu/bugs.c
/*
 * These CPUs all support 44bits physical address space internally in the
 * cache but CPUID can report a smaller number of physical address bits.
 *
 * The L1TF mitigation uses the top most address bit for the inversion of
 * non present PTEs. When the installed memory reaches into the top most
 * address bit due to memory holes, which has been observed on machines
 * which report 36bits physical address bits and have 32G RAM installed,
 * then the mitigation range check in l1tf_select_mitigation() triggers.
 * This is a false positive because the mitigation is still possible due to
 * the fact that the cache uses 44bit internally. Use the cache bits
 * instead of the reported physical bits and adjust them on the affected
 * machines to 44bit if the reported bits are less than 44.
 */
These CPUs all support 44bits physical address space internally in the
cache but CPUID can report a smaller number of physical address bits.

The L1TF mitigation uses the top most address bit for the inversion of
non present PTEs. When the installed memory reaches into the top most
address bit due to memory holes, which has been observed on machines
which report 36bits physical address bits and have 32G RAM installed,
then the mitigation range check in l1tf_select_mitigation() triggers.
This is a false positive because the mitigation is still possible due to
the fact that the cache uses 44bit internally. Use the cache bits
instead of the reported physical bits and adjust them on the affected
machines to 44bit if the reported bits are less than 44.
These CPUs all support 44bits physical address space internally in the cache but CPUID can report a smaller number of physical address bits . The L1TF mitigation uses the top most address bit for the inversion of non present PTEs . When the installed memory reaches into the top most address bit due to memory holes which has been observed on machines which report 36bits physical address bits and have 32G RAM installed then the mitigation range check in l1tf_select_mitigation () triggers . This is a false positive because the mitigation is still possible due to the fact that the cache uses 44bit internally . Use the cache bits instead of the reported physical bits and adjust them on the affected machines to 44bit if the reported bits are less than 44 .
static void override_cache_bits(struct cpuinfo_x86 *c)
{
	if (c->x86 != 6)
		return;
	switch (c->x86_model) {
	case INTEL_FAM6_NEHALEM:
	case INTEL_FAM6_WESTMERE:
	case INTEL_FAM6_SANDYBRIDGE:
	case INTEL_FAM6_IVYBRIDGE:
	case INTEL_FAM6_HASWELL_CORE:
	case INTEL_FAM6_HASWELL_ULT:
	case INTEL_FAM6_HASWELL_GT3E:
	case INTEL_FAM6_BROADWELL_CORE:
	case INTEL_FAM6_BROADWELL_GT3E:
	case INTEL_FAM6_SKYLAKE_MOBILE:
	case INTEL_FAM6_SKYLAKE_DESKTOP:
	case INTEL_FAM6_KABYLAKE_MOBILE:
	case INTEL_FAM6_KABYLAKE_DESKTOP:
		if (c->x86_cache_bits < 44)
			c->x86_cache_bits = 44;
		break;
	}
}
static void override_cache_bits ( struct cpuinfo_x86 * c ) { if ( c -> x86 != 6 ) return ; switch ( c -> x86_model ) { case INTEL_FAM6_NEHALEM : case INTEL_FAM6_WESTMERE : case INTEL_FAM6_SANDYBRIDGE : case INTEL_FAM6_IVYBRIDGE : case INTEL_FAM6_HASWELL_CORE : case INTEL_FAM6_HASWELL_ULT : case INTEL_FAM6_HASWELL_GT3E : case INTEL_FAM6_BROADWELL_CORE : case INTEL_FAM6_BROADWELL_GT3E : case INTEL_FAM6_SKYLAKE_MOBILE : case INTEL_FAM6_SKYLAKE_DESKTOP : case INTEL_FAM6_KABYLAKE_MOBILE : case INTEL_FAM6_KABYLAKE_DESKTOP : if ( c -> x86_cache_bits < 44 ) c -> x86_cache_bits = 44 ; break ; } }
These CPUs all support 44bits physical address space internally in the
 cache but CPUID can report a smaller number of physical address bits.
These CPUs all support 44bits physical address space internally in the cache but CPUID can report a smaller number of physical address bits .