FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/ST_Code/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_ll_utils.c
/**
  * @brief  Function to enable PLL and switch system clock to PLL
  * @param  SYSCLK_Frequency SYSCLK frequency
  * @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
  *                             the configuration information for the BUS prescalers.
  * @retval An ErrorStatus enumeration value:
  *          - SUCCESS: No problem to switch system to PLL
  *          - ERROR: Problem to switch system to PLL
  */
@brief  Function to enable PLL and switch system clock to PLL
@param  SYSCLK_Frequency SYSCLK frequency
@param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
the configuration information for the BUS prescalers.
@retval An ErrorStatus enumeration value:
- SUCCESS: No problem to switch system to PLL
- ERROR: Problem to switch system to PLL
@brief Function to enable PLL and switch system clock to PLL @param SYSCLK_Frequency SYSCLK frequency @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers . @retval An ErrorStatus enumeration value : - SUCCESS : No problem to switch system to PLL - ERROR : Problem to switch system to PLL
static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
{
  ErrorStatus status;
  uint32_t new_hclk_frequency, new_latency;
  assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->SYSCLKDivider));
  assert_param(IS_LL_UTILS_AHB_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
  assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
  assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
  assert_param(IS_LL_UTILS_APB3_DIV(UTILS_ClkInitStruct->APB3CLKDivider));
  assert_param(IS_LL_UTILS_APB4_DIV(UTILS_ClkInitStruct->APB4CLKDivider));
  new_hclk_frequency = LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider);
  status = UTILS_CalculateFlashLatency(new_hclk_frequency, &new_latency);
  if(status == SUCCESS)
  {
    if(LL_FLASH_GetLatency() < new_latency)
    {
      status = UTILS_SetFlashLatency(new_latency);
    }
    if(status == SUCCESS)
    {
      LL_RCC_PLL1_Enable();
      while (LL_RCC_PLL1_IsReady() != 1U)
      {
      }
      LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_16);
      LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_16);
      LL_RCC_SetAPB3Prescaler(LL_RCC_APB3_DIV_16);
      LL_RCC_SetAPB4Prescaler(LL_RCC_APB4_DIV_16);
      LL_RCC_SetSysPrescaler(UTILS_ClkInitStruct->SYSCLKDivider);
      LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
      LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
      while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1)
      {
      }
      LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
      LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
      LL_RCC_SetAPB3Prescaler(UTILS_ClkInitStruct->APB3CLKDivider);
      LL_RCC_SetAPB4Prescaler(UTILS_ClkInitStruct->APB4CLKDivider);
      LL_SetSystemCoreClock(SYSCLK_Frequency);
    }
    if(LL_FLASH_GetLatency() > new_latency)
    {
      status = UTILS_SetFlashLatency(new_latency);
    }
  }
  return status;
}
static ErrorStatus UTILS_EnablePLLAndSwitchSystem ( uint32_t SYSCLK_Frequency , LL_UTILS_ClkInitTypeDef * UTILS_ClkInitStruct ) { ErrorStatus status ; uint32_t new_hclk_frequency , new_latency ; assert_param ( IS_LL_UTILS_SYSCLK_DIV ( UTILS_ClkInitStruct -> SYSCLKDivider ) ) ; assert_param ( IS_LL_UTILS_AHB_DIV ( UTILS_ClkInitStruct -> AHBCLKDivider ) ) ; assert_param ( IS_LL_UTILS_APB1_DIV ( UTILS_ClkInitStruct -> APB1CLKDivider ) ) ; assert_param ( IS_LL_UTILS_APB2_DIV ( UTILS_ClkInitStruct -> APB2CLKDivider ) ) ; assert_param ( IS_LL_UTILS_APB3_DIV ( UTILS_ClkInitStruct -> APB3CLKDivider ) ) ; assert_param ( IS_LL_UTILS_APB4_DIV ( UTILS_ClkInitStruct -> APB4CLKDivider ) ) ; new_hclk_frequency = LL_RCC_CALC_HCLK_FREQ ( SYSCLK_Frequency , UTILS_ClkInitStruct -> AHBCLKDivider ) ; status = UTILS_CalculateFlashLatency ( new_hclk_frequency , & new_latency ) ; if ( status == SUCCESS ) { if ( LL_FLASH_GetLatency ( ) < new_latency ) { status = UTILS_SetFlashLatency ( new_latency ) ; } if ( status == SUCCESS ) { LL_RCC_PLL1_Enable ( ) ; while ( LL_RCC_PLL1_IsReady ( ) != 1U ) { } LL_RCC_SetAPB1Prescaler ( LL_RCC_APB1_DIV_16 ) ; LL_RCC_SetAPB2Prescaler ( LL_RCC_APB2_DIV_16 ) ; LL_RCC_SetAPB3Prescaler ( LL_RCC_APB3_DIV_16 ) ; LL_RCC_SetAPB4Prescaler ( LL_RCC_APB4_DIV_16 ) ; LL_RCC_SetSysPrescaler ( UTILS_ClkInitStruct -> SYSCLKDivider ) ; LL_RCC_SetAHBPrescaler ( UTILS_ClkInitStruct -> AHBCLKDivider ) ; LL_RCC_SetSysClkSource ( LL_RCC_SYS_CLKSOURCE_PLL1 ) ; while ( LL_RCC_GetSysClkSource ( ) != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 ) { } LL_RCC_SetAPB1Prescaler ( UTILS_ClkInitStruct -> APB1CLKDivider ) ; LL_RCC_SetAPB2Prescaler ( UTILS_ClkInitStruct -> APB2CLKDivider ) ; LL_RCC_SetAPB3Prescaler ( UTILS_ClkInitStruct -> APB3CLKDivider ) ; LL_RCC_SetAPB4Prescaler ( UTILS_ClkInitStruct -> APB4CLKDivider ) ; LL_SetSystemCoreClock ( SYSCLK_Frequency ) ; } if ( LL_FLASH_GetLatency ( ) > new_latency ) { status = UTILS_SetFlashLatency ( new_latency ) ; } } return status ; }
@brief  Function to enable PLL and switch system clock to PLL
 @param  SYSCLK_Frequency SYSCLK frequency
 @param  UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains
                             the configuration information for the BUS prescalers.
@brief Function to enable PLL and switch system clock to PLL @param SYSCLK_Frequency SYSCLK frequency @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers .
/* Calculate the new HCLK frequency */ /* Calculate the new FLASH latency according to the new HCLK frequency */ /* Increasing the number of wait states because of higher CPU frequency */ /* Update system clock configuration */ /* Enable PLL */ /* Wait for PLL ready */ /* Set All APBxPrescaler to the Highest Divider */ /* Set SYS prescaler*/ /* Set AHB prescaler*/ /* Sysclk activation on the main PLL */ /* Wait for system clock switch to PLL */ /* Set APBn prescaler*/ /* Update SystemCoreClock variable */ /* Decreasing the number of wait states because of lower CPU frequency */