drivers/arm/gic/arm_gic.c
/*******************************************************************************
 * This function does some minimal GICv3 configuration. The Firmware itself does
 * not fully support GICv3 at this time and relies on GICv2 emulation as
 * provided by GICv3. This function allows software (like Linux) in later stages
 * to use full GICv3 features.
 ******************************************************************************/
This function does some minimal GICv3 configuration. The Firmware itself does
not fully support GICv3 at this time and relies on GICv2 emulation as
provided by GICv3. This function allows software (like Linux) in later stages
to use full GICv3 features.
This function does some minimal GICv3 configuration . The Firmware itself does not fully support GICv3 at this time and relies on GICv2 emulation as provided by GICv3 . This function allows software ( like Linux ) in later stages to use full GICv3 features .
static void gicv3_cpuif_setup(void)
{
	unsigned int val;
	uintptr_t base;
	assert(g_gicr_base);
	base = gicv3_get_rdist(g_gicr_base, read_mpidr());
	if (base == (uintptr_t)NULL) {
		panic();
	}
	val = gicr_read_waker(base);
	val &= ~WAKER_PS;
	gicr_write_waker(base, val);
	dsb();
	val = gicr_read_waker(base);
	while (val & WAKER_CA)
		val = gicr_read_waker(base);
	val = read_icc_sre_el3();
	write_icc_sre_el3(val | ICC_SRE_EN | ICC_SRE_SRE);
	isb();
}
static void gicv3_cpuif_setup ( void ) { unsigned int val ; uintptr_t base ; assert ( g_gicr_base ) ; base = gicv3_get_rdist ( g_gicr_base , read_mpidr ( ) ) ; if ( base == ( uintptr_t ) NULL ) { panic ( ) ; } val = gicr_read_waker ( base ) ; val &= ~ WAKER_PS ; gicr_write_waker ( base , val ) ; dsb ( ) ; val = gicr_read_waker ( base ) ; while ( val & WAKER_CA ) val = gicr_read_waker ( base ) ; val = read_icc_sre_el3 ( ) ; write_icc_sre_el3 ( val | ICC_SRE_EN | ICC_SRE_SRE ) ; isb ( ) ; }
This function does some minimal GICv3 configuration.
This function does some minimal GICv3 configuration .
/*
	 * When CPUs come out of reset they have their GICR_WAKER.ProcessorSleep
	 * bit set. In order to allow interrupts to get routed to the CPU we
	 * need to clear this bit if set and wait for GICR_WAKER.ChildrenAsleep
	 * to clear (GICv3 Architecture specification 5.4.23).
	 * GICR_WAKER is NOT banked per CPU, compute the correct base address
	 * per CPU.
	 */ /* No re-distributor base address. This interface cannot be
		 * configured.
		 */ /* We need to wait for ChildrenAsleep to clear. */