FreeRTOS-Plus/ThirdParty/WolfSSL-FIPS-Ready/wolfcrypt/src/random.c
/* Generate a RNG seed using the hardware RNG on the STM32F427
     * directly, following steps outlined in STM32F4 Reference
     * Manual (Chapter 24) for STM32F4xx family. */
Generate a RNG seed using the hardware RNG on the STM32F427
directly, following steps outlined in STM32F4 Reference
Manual (Chapter 24) for STM32F4xx family.
Generate a RNG seed using the hardware RNG on the STM32F427 directly following steps outlined in STM32F4 Reference Manual ( Chapter 24 ) for STM32F4xx family .
int wc_GenerateSeed(OS_Seed* os, byte* output, word32 sz)
    {
        int ret;
        word32 i;
        (void)os;
        ret = wolfSSL_CryptHwMutexLock();
        if (ret != 0) {
            return ret;
        }
        RCC->AHB2ENR |= RCC_AHB2ENR_RNGEN;
        RNG->CR |= RNG_CR_IE;
        RNG->CR |= RNG_CR_RNGEN;
        if (RNG->SR & (RNG_SR_SECS | RNG_SR_CECS)) {
            wolfSSL_CryptHwMutexUnLock();
            return RNG_FAILURE_E;
        }
        for (i = 0; i < sz; i++) {
            while ((RNG->SR & RNG_SR_DRDY) == 0) { }
            output[i] = RNG->DR;
        }
        wolfSSL_CryptHwMutexUnLock();
        return 0;
    }
int wc_GenerateSeed ( OS_Seed * os , byte * output , word32 sz ) { int ret ; word32 i ; ( void ) os ; ret = wolfSSL_CryptHwMutexLock ( ) ; if ( ret != 0 ) { return ret ; } RCC -> AHB2ENR |= RCC_AHB2ENR_RNGEN ; RNG -> CR |= RNG_CR_IE ; RNG -> CR |= RNG_CR_RNGEN ; if ( RNG -> SR & ( RNG_SR_SECS | RNG_SR_CECS ) ) { wolfSSL_CryptHwMutexUnLock ( ) ; return RNG_FAILURE_E ; } for ( i = 0 ; i < sz ; i ++ ) { while ( ( RNG -> SR & RNG_SR_DRDY ) == 0 ) { } output [ i ] = RNG -> DR ; } wolfSSL_CryptHwMutexUnLock ( ) ; return 0 ; }
Generate a RNG seed using the hardware RNG on the STM32F427
 directly, following steps outlined in STM32F4 Reference
 Manual (Chapter 24) for STM32F4xx family.
Generate a RNG seed using the hardware RNG on the STM32F427 directly following steps outlined in STM32F4 Reference Manual ( Chapter 24 ) for STM32F4xx family .
/* enable RNG peripheral clock */ /* enable RNG interrupt, set IE bit in RNG->CR register */ /* enable RNG, set RNGEN bit in RNG->CR. Activates RNG,
         * RNG_LFSR, and error detector */ /* verify no errors, make sure SEIS and CEIS bits are 0
         * in RNG->SR register */ /* wait until RNG number is ready */ /* get value */