FreeRTOS/Demo/CORTEX_MPU_M7_NUCLEO_H743ZI2_GCC_IAR_Keil/ST_Code/Core/Src/system_stm32h7xx.c
/**
   * @brief  Update SystemCoreClock variable according to Clock Register Values.
  *         The SystemCoreClock variable contains the core clock , it can
  *         be used by the user application to setup the SysTick timer or configure
  *         other parameters.
  *
  * @note   Each time the core clock changes, this function must be called
  *         to update SystemCoreClock variable value. Otherwise, any configuration
  *         based on this variable will be incorrect.
  *
  * @note   - The system frequency computed by this function is not the real
  *           frequency in the chip. It is calculated based on the predefined
  *           constant and the selected clock source:
  *
  *           - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
  *           - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*),
  *             HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors.
  *
  *         (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
  *             4 MHz) but the real value may vary depending on the variations
  *             in voltage and temperature.
  *         (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
  *             64 MHz) but the real value may vary depending on the variations
  *             in voltage and temperature.
  *
  *         (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
  *              frequency of the crystal used. Otherwise, this function may
  *              have wrong result.
  *
  *         - The result of this function could be not correct when using fractional
  *           value for HSE crystal.
  * @param  None
  * @retval None
  */
@brief  Update SystemCoreClock variable according to Clock Register Values.
The SystemCoreClock variable contains the core clock , it can
be used by the user application to setup the SysTick timer or configure
other parameters.

@note   Each time the core clock changes, this function must be called
to update SystemCoreClock variable value. Otherwise, any configuration
based on this variable will be incorrect.

@note   - The system frequency computed by this function is not the real
frequency in the chip. It is calculated based on the predefined
constant and the selected clock source.



(*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
4 MHz) but the real value may vary depending on the variations
in voltage and temperature.
(**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value
64 MHz) but the real value may vary depending on the variations
in voltage and temperature.

(***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value
25 MHz), user has to ensure that HSE_VALUE is same as the real
frequency of the crystal used. Otherwise, this function may
have wrong result.

- The result of this function could be not correct when using fractional
value for HSE crystal.
@param  None
@retval None
@brief Update SystemCoreClock variable according to Clock Register Values . The SystemCoreClock variable contains the core clock it can be used by the user application to setup the SysTick timer or configure other parameters . @note Each time the core clock changes this function must be called to update SystemCoreClock variable value . Otherwise any configuration based on this variable will be incorrect . @note - The system frequency computed by this function is not the real frequency in the chip . It is calculated based on the predefined constant and the selected clock source . ( * ) CSI_VALUE is a constant defined in stm32h7xx_hal . h file ( default value 4 MHz ) but the real value may vary depending on the variations in voltage and temperature . ( ** ) HSI_VALUE is a constant defined in stm32h7xx_hal . h file ( default value 64 MHz ) but the real value may vary depending on the variations in voltage and temperature . ( *** ) HSE_VALUE is a constant defined in stm32h7xx_hal . h file ( default value 25 MHz ) user has to ensure that HSE_VALUE is same as the real frequency of the crystal used . Otherwise this function may have wrong result . - The result of this function could be not correct when using fractional value for HSE crystal . @param None @retval None
void SystemCoreClockUpdate (void)
{
  uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
  float_t fracn1, pllvco;
  switch (RCC->CFGR & RCC_CFGR_SWS)
  {
  case RCC_CFGR_SWS_HSI:  
    SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
    break;
  case RCC_CFGR_SWS_CSI:  
    SystemCoreClock = CSI_VALUE;
    break;
  case RCC_CFGR_SWS_HSE:  
    SystemCoreClock = HSE_VALUE;
    break;
  case RCC_CFGR_SWS_PLL1:  
    pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
    pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4)  ;
    pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
    fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
    if (pllm != 0U)
    {
      switch (pllsource)
      {
        case RCC_PLLCKSELR_PLLSRC_HSI:  
        hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
        pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
        break;
        case RCC_PLLCKSELR_PLLSRC_CSI:  
          pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
        break;
        case RCC_PLLCKSELR_PLLSRC_HSE:  
          pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
        break;
      default:
          pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
        break;
      }
      pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
      SystemCoreClock =  (uint32_t)(float_t)(pllvco/(float_t)pllp);
    }
    else
    {
      SystemCoreClock = 0U;
    }
    break;
  default:
    SystemCoreClock = CSI_VALUE;
    break;
  }
#if defined (RCC_D1CFGR_D1CPRE)
  tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
  SystemCoreClock >>= tmp;
  SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
#else
  tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
  SystemCoreClock >>= tmp;
  SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
#endif
}
void SystemCoreClockUpdate ( void ) { uint32_t pllp , pllsource , pllm , pllfracen , hsivalue , tmp ; float_t fracn1 , pllvco ; switch ( RCC -> CFGR & RCC_CFGR_SWS ) { case RCC_CFGR_SWS_HSI : SystemCoreClock = ( uint32_t ) ( HSI_VALUE >> ( ( RCC -> CR & RCC_CR_HSIDIV ) >> 3 ) ) ; break ; case RCC_CFGR_SWS_CSI : SystemCoreClock = CSI_VALUE ; break ; case RCC_CFGR_SWS_HSE : SystemCoreClock = HSE_VALUE ; break ; case RCC_CFGR_SWS_PLL1 : pllsource = ( RCC -> PLLCKSELR & RCC_PLLCKSELR_PLLSRC ) ; pllm = ( ( RCC -> PLLCKSELR & RCC_PLLCKSELR_DIVM1 ) >> 4 ) ; pllfracen = ( ( RCC -> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN ) >> RCC_PLLCFGR_PLL1FRACEN_Pos ) ; fracn1 = ( float_t ) ( uint32_t ) ( pllfracen * ( ( RCC -> PLL1FRACR & RCC_PLL1FRACR_FRACN1 ) >> 3 ) ) ; if ( pllm != 0U ) { switch ( pllsource ) { case RCC_PLLCKSELR_PLLSRC_HSI : hsivalue = ( HSI_VALUE >> ( ( RCC -> CR & RCC_CR_HSIDIV ) >> 3 ) ) ; pllvco = ( ( float_t ) hsivalue / ( float_t ) pllm ) * ( ( float_t ) ( uint32_t ) ( RCC -> PLL1DIVR & RCC_PLL1DIVR_N1 ) + ( fracn1 / ( float_t ) 0x2000 ) + ( float_t ) 1 ) ; break ; case RCC_PLLCKSELR_PLLSRC_CSI : pllvco = ( ( float_t ) CSI_VALUE / ( float_t ) pllm ) * ( ( float_t ) ( uint32_t ) ( RCC -> PLL1DIVR & RCC_PLL1DIVR_N1 ) + ( fracn1 / ( float_t ) 0x2000 ) + ( float_t ) 1 ) ; break ; case RCC_PLLCKSELR_PLLSRC_HSE : pllvco = ( ( float_t ) HSE_VALUE / ( float_t ) pllm ) * ( ( float_t ) ( uint32_t ) ( RCC -> PLL1DIVR & RCC_PLL1DIVR_N1 ) + ( fracn1 / ( float_t ) 0x2000 ) + ( float_t ) 1 ) ; break ; default : pllvco = ( ( float_t ) CSI_VALUE / ( float_t ) pllm ) * ( ( float_t ) ( uint32_t ) ( RCC -> PLL1DIVR & RCC_PLL1DIVR_N1 ) + ( fracn1 / ( float_t ) 0x2000 ) + ( float_t ) 1 ) ; break ; } pllp = ( ( ( RCC -> PLL1DIVR & RCC_PLL1DIVR_P1 ) >> 9 ) + 1U ) ; SystemCoreClock = ( uint32_t ) ( float_t ) ( pllvco / ( float_t ) pllp ) ; } else { SystemCoreClock = 0U ; } break ; default : SystemCoreClock = CSI_VALUE ; break ; } #if defined ( RCC_D1CFGR_D1CPRE ) tmp = D1CorePrescTable [ ( RCC -> D1CFGR & RCC_D1CFGR_D1CPRE ) >> RCC_D1CFGR_D1CPRE_Pos ] ; SystemCoreClock >>= tmp ; SystemD2Clock = ( SystemCoreClock >> ( ( D1CorePrescTable [ ( RCC -> D1CFGR & RCC_D1CFGR_HPRE ) >> RCC_D1CFGR_HPRE_Pos ] ) & 0x1FU ) ) ; #else tmp = D1CorePrescTable [ ( RCC -> CDCFGR1 & RCC_CDCFGR1_CDCPRE ) >> RCC_CDCFGR1_CDCPRE_Pos ] ; SystemCoreClock >>= tmp ; SystemD2Clock = ( SystemCoreClock >> ( ( D1CorePrescTable [ ( RCC -> CDCFGR1 & RCC_CDCFGR1_HPRE ) >> RCC_CDCFGR1_HPRE_Pos ] ) & 0x1FU ) ) ; #endif }
@brief  Update SystemCoreClock variable according to Clock Register Values.
@brief Update SystemCoreClock variable according to Clock Register Values .
/* Get SYSCLK source -------------------------------------------------------*/ /* HSI used as system clock source */ /* CSI used as system clock  source */ /* HSE used as system clock  source */ /* PLL1 used as system clock  source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
    SYSCLK = PLL_VCO / PLLR
    */ /* HSI used as PLL clock source */ /* CSI used as PLL clock source */ /* HSE used as PLL clock source */ /* Compute SystemClock frequency --------------------------------------------------*/ /* SystemCoreClock frequency : CM7 CPU frequency  */ /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency  */ /* SystemCoreClock frequency : CM7 CPU frequency  */ /* SystemD2Clock frequency : AXI and AHBs Clock frequency  */