plat/nvidia/tegra/common/tegra_gic.c
/*******************************************************************************
 * Per cpu gic distributor setup which will be done by all cpus after a cold
 * boot/hotplug. This marks out the secure interrupts & enables them.
 ******************************************************************************/
Per cpu gic distributor setup which will be done by all cpus after a cold
boot/hotplug. This marks out the secure interrupts & enables them.
Per cpu gic distributor setup which will be done by all cpus after a cold boot / hotplug . This marks out the secure interrupts & enables them .
static void tegra_gic_pcpu_distif_setup(uint32_t gicd_base)
{
	uint32_t index, sec_ppi_sgi_mask = 0;
	assert(gicd_base != 0U);
	for (index = 0U; index < 32U; index += 4U) {
		gicd_write_ipriorityr(gicd_base, index,
				GICD_IPRIORITYR_DEF_VAL);
	}
	gicd_write_igroupr(gicd_base, 0, ~sec_ppi_sgi_mask);
}
static void tegra_gic_pcpu_distif_setup ( uint32_t gicd_base ) { uint32_t index , sec_ppi_sgi_mask = 0 ; assert ( gicd_base != 0U ) ; for ( index = 0U ; index < 32U ; index += 4U ) { gicd_write_ipriorityr ( gicd_base , index , GICD_IPRIORITYR_DEF_VAL ) ; } gicd_write_igroupr ( gicd_base , 0 , ~ sec_ppi_sgi_mask ) ; }
Per cpu gic distributor setup which will be done by all cpus after a cold
 boot/hotplug.
Per cpu gic distributor setup which will be done by all cpus after a cold boot / hotplug .
/* Setup PPI priorities doing four at a time */ /*
	 * Invert the bitmask to create a mask for non-secure PPIs and
	 * SGIs. Program the GICD_IGROUPR0 with this bit mask. This write will
	 * update the GICR_IGROUPR0 as well in case we are running on a GICv3
	 * system. This is critical if GICD_CTLR.ARE_NS=1.
	 */