FreeBSD/sys/dev/mrsas/mrsas.c
/*
 * mrsas_init_adapter:	Initializes the adapter/controller
 * input:				Adapter soft state
 *
 * Prepares for the issuing of the IOC Init cmd to FW for initializing the
 * ROC/controller.  The FW register is read to determined the number of
 * commands that is supported.  All memory allocations for IO is based on
 * max_cmd.  Appropriate calculations are performed in this function.
 */
Initializes the adapter/controller
input:                               Adapter soft state

Prepares for the issuing of the IOC Init cmd to FW for initializing the
ROC/controller.  The FW register is read to determined the number of
commands that is supported.  All memory allocations for IO is based on
max_cmd.  Appropriate calculations are performed in this function.
Initializes the adapter / controller input : Adapter soft state Prepares for the issuing of the IOC Init cmd to FW for initializing the ROC / controller . The FW register is read to determined the number of commands that is supported . All memory allocations for IO is based on max_cmd . Appropriate calculations are performed in this function .
int
mrsas_init_adapter(struct mrsas_softc *sc)
{
	uint32_t status;
	u_int32_t max_cmd, scratch_pad_2;
	int ret;
	int i = 0;
	status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_scratch_pad));
	sc->max_fw_cmds = status & MRSAS_FWSTATE_MAXCMD_MASK;
	sc->max_fw_cmds = sc->max_fw_cmds - 1;
	max_cmd = sc->max_fw_cmds;
	sc->reply_q_depth = ((max_cmd + 1 + 15) / 16 * 16) * 2;
	sc->request_alloc_sz = sizeof(MRSAS_REQUEST_DESCRIPTOR_UNION) * max_cmd;
	sc->reply_alloc_sz = sizeof(MPI2_REPLY_DESCRIPTORS_UNION) * (sc->reply_q_depth);
	sc->io_frames_alloc_sz = MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE + (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE * (max_cmd + 1));
	scratch_pad_2 = mrsas_read_reg(sc, offsetof(mrsas_reg_set,
	    outbound_scratch_pad_2));
	if (scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK)
		sc->max_chain_frame_sz =
		    ((scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_MASK) >> 5)
		    * MEGASAS_1MB_IO;
	else
		sc->max_chain_frame_sz =
		    ((scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_MASK) >> 5)
		    * MEGASAS_256K_IO;
	sc->chain_frames_alloc_sz = sc->max_chain_frame_sz * max_cmd;
	sc->max_sge_in_main_msg = (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE -
	    offsetof(MRSAS_RAID_SCSI_IO_REQUEST, SGL)) / 16;
	sc->max_sge_in_chain = sc->max_chain_frame_sz / sizeof(MPI2_SGE_IO_UNION);
	sc->max_num_sge = sc->max_sge_in_main_msg + sc->max_sge_in_chain - 2;
	mrsas_dprint(sc, MRSAS_INFO, "Avago Debug: MAX sge 0x%X MAX chain frame size 0x%X \n",
	    sc->max_num_sge, sc->max_chain_frame_sz);
	sc->chain_offset_mfi_pthru = offsetof(MRSAS_RAID_SCSI_IO_REQUEST, SGL) / 16;
	sc->chain_offset_io_request = (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE -
	    sizeof(MPI2_SGE_IO_UNION)) / 16;
	int count = sc->msix_vectors > 0 ? sc->msix_vectors : 1;
	for (i = 0; i < count; i++)
		sc->last_reply_idx[i] = 0;
	ret = mrsas_alloc_mem(sc);
	if (ret != SUCCESS)
		return (ret);
	ret = mrsas_alloc_mpt_cmds(sc);
	if (ret != SUCCESS)
		return (ret);
	ret = mrsas_ioc_init(sc);
	if (ret != SUCCESS)
		return (ret);
	return (0);
}
int mrsas_init_adapter ( struct mrsas_softc * sc ) { uint32_t status ; u_int32_t max_cmd , scratch_pad_2 ; int ret ; int i = 0 ; status = mrsas_read_reg ( sc , offsetof ( mrsas_reg_set , outbound_scratch_pad ) ) ; sc -> max_fw_cmds = status & MRSAS_FWSTATE_MAXCMD_MASK ; sc -> max_fw_cmds = sc -> max_fw_cmds - 1 ; max_cmd = sc -> max_fw_cmds ; sc -> reply_q_depth = ( ( max_cmd + 1 + 15 ) / 16 * 16 ) * 2 ; sc -> request_alloc_sz = sizeof ( MRSAS_REQUEST_DESCRIPTOR_UNION ) * max_cmd ; sc -> reply_alloc_sz = sizeof ( MPI2_REPLY_DESCRIPTORS_UNION ) * ( sc -> reply_q_depth ) ; sc -> io_frames_alloc_sz = MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE + ( MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE * ( max_cmd + 1 ) ) ; scratch_pad_2 = mrsas_read_reg ( sc , offsetof ( mrsas_reg_set , outbound_scratch_pad_2 ) ) ; if ( scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK ) sc -> max_chain_frame_sz = ( ( scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_MASK ) >> 5 ) * MEGASAS_1MB_IO ; else sc -> max_chain_frame_sz = ( ( scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_MASK ) >> 5 ) * MEGASAS_256K_IO ; sc -> chain_frames_alloc_sz = sc -> max_chain_frame_sz * max_cmd ; sc -> max_sge_in_main_msg = ( MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE - offsetof ( MRSAS_RAID_SCSI_IO_REQUEST , SGL ) ) / 16 ; sc -> max_sge_in_chain = sc -> max_chain_frame_sz / sizeof ( MPI2_SGE_IO_UNION ) ; sc -> max_num_sge = sc -> max_sge_in_main_msg + sc -> max_sge_in_chain - 2 ; mrsas_dprint ( sc , MRSAS_INFO , " \n " , sc -> max_num_sge , sc -> max_chain_frame_sz ) ; sc -> chain_offset_mfi_pthru = offsetof ( MRSAS_RAID_SCSI_IO_REQUEST , SGL ) / 16 ; sc -> chain_offset_io_request = ( MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE - sizeof ( MPI2_SGE_IO_UNION ) ) / 16 ; int count = sc -> msix_vectors > 0 ? sc -> msix_vectors : 1 ; for ( i = 0 ; i < count ; i ++ ) sc -> last_reply_idx [ i ] = 0 ; ret = mrsas_alloc_mem ( sc ) ; if ( ret != SUCCESS ) return ( ret ) ; ret = mrsas_alloc_mpt_cmds ( sc ) ; if ( ret != SUCCESS ) return ( ret ) ; ret = mrsas_ioc_init ( sc ) ; if ( ret != SUCCESS ) return ( ret ) ; return ( 0 ) ; }
mrsas_init_adapter:  Initializes the adapter/controller
 input:                               Adapter soft state
mrsas_init_adapter : Initializes the adapter / controller input : Adapter soft state
/* Read FW status register */ /* Get operational params from status register */ /* Decrement the max supported by 1, to correlate with FW */ /* Determine allocation size of command frames */ /*
	 * If scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK is set,
	 * Firmware support extended IO chain frame which is 4 time more
	 * than legacy Firmware. Legacy Firmware - Frame size is (8 * 128) =
	 * 1K 1M IO Firmware  - Frame size is (8 * 128 * 4)  = 4K
	 */ /* Used for pass thru MFI frame (DCMD) */