plat/nvidia/tegra/soc/t132/plat_sip_calls.c
/*******************************************************************************
 * This function is responsible for handling all T132 SiP calls
 ******************************************************************************/
This function is responsible for handling all T132 SiP calls
This function is responsible for handling all T132 SiP calls
int plat_sip_handler(uint32_t smc_fid,
		     uint64_t x1,
		     uint64_t x2,
		     uint64_t x3,
		     uint64_t x4,
		     void *cookie,
		     void *handle,
		     uint64_t flags)
{
	switch (smc_fid) {
	case TEGRA_SIP_AARCH_SWITCH:
		x1 = (uint32_t)x1;
		x2 = (uint32_t)x2;
		if (!x1 || x2 > NS_SWITCH_AARCH32) {
			ERROR("%s: invalid parameters\n", __func__);
			return -EINVAL;
		}
		cm_set_elr_spsr_el3(NON_SECURE, x1,
			(x2 == NS_SWITCH_AARCH32) ? SPSR32 : SPSR64);
		cm_write_scr_el3_bit(NON_SECURE, SCR_RW_BITPOS, !x2);
		INFO("CPU switched to AARCH%s mode\n",
			(x2 == NS_SWITCH_AARCH32) ? "32" : "64");
		return 0;
	default:
		ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
		break;
	}
	return -ENOTSUP;
}
int plat_sip_handler ( uint32_t smc_fid , uint64_t x1 , uint64_t x2 , uint64_t x3 , uint64_t x4 , void * cookie , void * handle , uint64_t flags ) { switch ( smc_fid ) { case TEGRA_SIP_AARCH_SWITCH : x1 = ( uint32_t ) x1 ; x2 = ( uint32_t ) x2 ; if ( ! x1 || x2 > NS_SWITCH_AARCH32 ) { ERROR ( " \n " , __func__ ) ; return - EINVAL ; } cm_set_elr_spsr_el3 ( NON_SECURE , x1 , ( x2 == NS_SWITCH_AARCH32 ) ? SPSR32 : SPSR64 ) ; cm_write_scr_el3_bit ( NON_SECURE , SCR_RW_BITPOS , ! x2 ) ; INFO ( " \n " , ( x2 == NS_SWITCH_AARCH32 ) ? " " : " " ) ; return 0 ; default : ERROR ( " \n " , __func__ , smc_fid ) ; break ; } return - ENOTSUP ; }
This function is responsible for handling all T132 SiP calls
This function is responsible for handling all T132 SiP calls
/* clean up the high bits */ /* x1 = ns entry point */ /* switch NS world mode */