FreeBSD/sys/mips/atheros/ar71xx_pci.c
/*
 * Some embedded boards (eg AP94) have the MAC attached via PCI but they
 * don't have the MAC-attached EEPROM.  The register initialisation
 * values and calibration data are stored in the on-board flash.
 * This routine initialises the NIC via the EEPROM register contents
 * before the probe/attach routines get a go at things.
 */
Some embedded boards  have the MAC attached via PCI but they
don't have the MAC-attached EEPROM.  The register initialisation
values and calibration data are stored in the on-board flash.
This routine initialises the NIC via the EEPROM register contents
before the probe/attach routines get a go at things.
Some embedded boards have the MAC attached via PCI but they don ' t have the MAC - attached EEPROM . The register initialisation values and calibration data are stored in the on - board flash . This routine initialises the NIC via the EEPROM register contents before the probe / attach routines get a go at things .
static void
ar71xx_pci_fixup(device_t dev, u_int bus, u_int slot, u_int func,
    long flash_addr, int len)
{
	uint16_t *cal_data = (uint16_t *) MIPS_PHYS_TO_KSEG1(flash_addr);
	uint32_t reg, val, bar0;
	if (bootverbose)
		device_printf(dev, "%s: flash_addr=%lx, cal_data=%p\n",
		    __func__, flash_addr, cal_data);
	bar0 = ar71xx_pci_read_config(dev, bus, slot, func, PCIR_BAR(0), 4);
	ar71xx_pci_write_config(dev, bus, slot, func, PCIR_BAR(0),
	    AR71XX_PCI_MEM_BASE, 4);
	val = ar71xx_pci_read_config(dev, bus, slot, func, PCIR_COMMAND, 2);
	val |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
	ar71xx_pci_write_config(dev, bus, slot, func, PCIR_COMMAND, val, 2); 
	cal_data += 3;
	while (*cal_data != 0xffff) {
		reg = *cal_data++;
		val = *cal_data++;
		val |= (*cal_data++) << 16;
		if (bootverbose)
			printf("  reg: %x, val=%x\n", reg, val);
		ATH_WRITE_REG(AR71XX_PCI_MEM_BASE + reg, val);
		DELAY(100);
	}
	val = ar71xx_pci_read_config(dev, bus, slot, func, PCIR_COMMAND, 2);
	val &= ~(PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
	ar71xx_pci_write_config(dev, bus, slot, func, PCIR_COMMAND, val, 2);
	ar71xx_pci_write_config(dev, bus, slot, func, PCIR_BAR(0), bar0, 4);
}
static void ar71xx_pci_fixup ( device_t dev , u_int bus , u_int slot , u_int func , long flash_addr , int len ) { uint16_t * cal_data = ( uint16_t * ) MIPS_PHYS_TO_KSEG1 ( flash_addr ) ; uint32_t reg , val , bar0 ; if ( bootverbose ) device_printf ( dev , " \n " , __func__ , flash_addr , cal_data ) ; bar0 = ar71xx_pci_read_config ( dev , bus , slot , func , PCIR_BAR ( 0 ) , 4 ) ; ar71xx_pci_write_config ( dev , bus , slot , func , PCIR_BAR ( 0 ) , AR71XX_PCI_MEM_BASE , 4 ) ; val = ar71xx_pci_read_config ( dev , bus , slot , func , PCIR_COMMAND , 2 ) ; val |= ( PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN ) ; ar71xx_pci_write_config ( dev , bus , slot , func , PCIR_COMMAND , val , 2 ) ; cal_data += 3 ; while ( * cal_data != 0xffff ) { reg = * cal_data ++ ; val = * cal_data ++ ; val |= ( * cal_data ++ ) << 16 ; if ( bootverbose ) printf ( " \n " , reg , val ) ; ATH_WRITE_REG ( AR71XX_PCI_MEM_BASE + reg , val ) ; DELAY ( 100 ) ; } val = ar71xx_pci_read_config ( dev , bus , slot , func , PCIR_COMMAND , 2 ) ; val &= ~ ( PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN ) ; ar71xx_pci_write_config ( dev , bus , slot , func , PCIR_COMMAND , val , 2 ) ; ar71xx_pci_write_config ( dev , bus , slot , func , PCIR_BAR ( 0 ) , bar0 , 4 ) ; }
Some embedded boards (eg AP94) have the MAC attached via PCI but they
 don't have the MAC-attached EEPROM.
Some embedded boards ( eg AP94 ) have the MAC attached via PCI but they don ' t have the MAC - attached EEPROM .
/* XXX check 0xa55a */ /* Save bar(0) address - just to flush bar(0) (SoC WAR) ? */ /* Write eeprom fixup data to device memory */ /* Write the saved bar(0) address */