import/chips/p9/procedures/ppe_closed/pgpe/pstate_gpe/p9_pgpe_irq_handlers.c
//
//  p9_pgpe_irq_handler_pcb_type1
//
//  Handler for PCB Type 1 interrupt which is forwarding of Pstates
//  Requests by CME
//
//  Pstate must be active and an onwer for PMSR must be set for any
//  effect. Otherwise, no action is taken
//
p9_pgpe_irq_handler_pcb_type1
Handler for PCB Type 1 interrupt which is forwarding of Pstates
Requests by CME

Pstate must be active and an onwer for PMSR must be set for any
effect. Otherwise, no action is taken
p9_pgpe_irq_handler_pcb_type1 Handler for PCB Type 1 interrupt which is forwarding of Pstates Requests by CME Pstate must be active and an onwer for PMSR must be set for any effect . Otherwise no action is taken
void p9_pgpe_irq_handler_pcb_type1(void* arg, PkIrqId irq)
{
    PK_TRACE_DBG("PCB1: Enter");
    PkMachineContext  ctx;
    ocb_opit1cn_t opit1cn;
    uint32_t c;
    uint32_t opit1pra;
    if(in32(G_OCB_OCCFLG2) & BIT32(OCCFLG2_PGPE_HCODE_PSTATE_REQ_ERR_INJ))
    {
        out32(G_OCB_OCCFLG2_CLR, BIT32(OCCFLG2_PGPE_HCODE_PSTATE_REQ_ERR_INJ));
        PK_TRACE_ERR("PCB TYPE1 ERROR INJECT TRAP");
        PK_PANIC(PGPE_SET_PMCR_TRAP_INJECT);
    }
    if (G_pgpe_pstate_record.pstatesStatus == PSTATE_ACTIVE &&
        (G_pgpe_pstate_record.pmcrOwner == PMCR_OWNER_HOST ||
         G_pgpe_pstate_record.pmcrOwner == PMCR_OWNER_CHAR))
    {
        opit1pra = in32(OCB_OPIT1PRA);
        out32(OCB_OPIT1PRA_CLR, opit1pra);
        for (c = 0; c < MAX_CORES; c++)
        {
            if (opit1pra & CORE_MASK(c))
            {
                opit1cn.value = in32(OCB_OPIT1CN(c));
                G_pgpe_pstate_record.coresPSRequest[c] = opit1cn.value & 0xff;
                PK_TRACE_INF("PCB1: c[%d]=0%x", c, G_pgpe_pstate_record.coresPSRequest[c]);
                G_pgpe_optrace_data.word[0] = (c << 24) | (G_pgpe_pstate_record.psCurr.fields.glb << 16) |
                                              G_pgpe_pstate_record.coresPSRequest[c];
                p9_pgpe_optrace(PRC_PCB_T1);
            }
        }
        p9_pgpe_pstate_do_auction();
        p9_pgpe_pstate_apply_clips();
    }
    else
    {
        opit1pra = in32(OCB_OPIT1PRA);
        out32(OCB_OPIT1PRA_CLR, opit1pra);
        G_pgpe_optrace_data.word[0] = PGPE_OP_PCB_TYPE1_IN_PSTATE_STOPPED;
        p9_pgpe_optrace(UNEXPECTED_ERROR);
    }
#if SIMICS_TUNING
    out32(OCB_OPIT1PRA, 0x00000000); 
    out32(OCB_OISR1_CLR, BIT32(14));
#endif
    pk_irq_vec_restore(&ctx);
    PK_TRACE_DBG("PCB1: Exit");
}
void p9_pgpe_irq_handler_pcb_type1 ( void * arg , PkIrqId irq ) { PK_TRACE_DBG ( " " ) ; PkMachineContext ctx ; ocb_opit1cn_t opit1cn ; uint32_t c ; uint32_t opit1pra ; if ( in32 ( G_OCB_OCCFLG2 ) & BIT32 ( OCCFLG2_PGPE_HCODE_PSTATE_REQ_ERR_INJ ) ) { out32 ( G_OCB_OCCFLG2_CLR , BIT32 ( OCCFLG2_PGPE_HCODE_PSTATE_REQ_ERR_INJ ) ) ; PK_TRACE_ERR ( " " ) ; PK_PANIC ( PGPE_SET_PMCR_TRAP_INJECT ) ; } if ( G_pgpe_pstate_record . pstatesStatus == PSTATE_ACTIVE && ( G_pgpe_pstate_record . pmcrOwner == PMCR_OWNER_HOST || G_pgpe_pstate_record . pmcrOwner == PMCR_OWNER_CHAR ) ) { opit1pra = in32 ( OCB_OPIT1PRA ) ; out32 ( OCB_OPIT1PRA_CLR , opit1pra ) ; for ( c = 0 ; c < MAX_CORES ; c ++ ) { if ( opit1pra & CORE_MASK ( c ) ) { opit1cn . value = in32 ( OCB_OPIT1CN ( c ) ) ; G_pgpe_pstate_record . coresPSRequest [ c ] = opit1cn . value & 0xff ; PK_TRACE_INF ( " " , c , G_pgpe_pstate_record . coresPSRequest [ c ] ) ; G_pgpe_optrace_data . word [ 0 ] = ( c << 24 ) | ( G_pgpe_pstate_record . psCurr . fields . glb << 16 ) | G_pgpe_pstate_record . coresPSRequest [ c ] ; p9_pgpe_optrace ( PRC_PCB_T1 ) ; } } p9_pgpe_pstate_do_auction ( ) ; p9_pgpe_pstate_apply_clips ( ) ; } else { opit1pra = in32 ( OCB_OPIT1PRA ) ; out32 ( OCB_OPIT1PRA_CLR , opit1pra ) ; G_pgpe_optrace_data . word [ 0 ] = PGPE_OP_PCB_TYPE1_IN_PSTATE_STOPPED ; p9_pgpe_optrace ( UNEXPECTED_ERROR ) ; } #if SIMICS_TUNING out32 ( OCB_OPIT1PRA , 0x00000000 ) ; out32 ( OCB_OISR1_CLR , BIT32 ( 14 ) ) ; #endif pk_irq_vec_restore ( & ctx ) ; PK_TRACE_DBG ( " " ) ; }
p9_pgpe_irq_handler_pcb_type1
Handler for PCB Type 1 interrupt which is forwarding of Pstates
Requests by CME
p9_pgpe_irq_handler_pcb_type1 Handler for PCB Type 1 interrupt which is forwarding of Pstates Requests by CME
//If error injection bit is set in OCC Scratch 2, then halt PGPE immediately // Clear the injection so things are not permenently stuck //Read and Clear before data is read //Process pending requests //For each pending bit OPIT1PR[c] (OPIT1PR is 24 bits) //Read payload from OPIT1C[c] register corresponding to the core 'c' //Extract the LowerPState field and store the Pstate request //Do auction, apply clips and generate new targets //If pstates aren't active or PMCR Onwer isn't set, then do nothing //Clear out pending bits //Restore interrupts