FreeBSD/sys/sparc64/sparc64/spitfire.c
/*
 * Flush all user mappings from the TLBs.
 */
Flush all user mappings from the TLBs.
Flush all user mappings from the TLBs .
void
spitfire_tlb_flush_user(void)
{
	u_long data;
	u_long tag;
	u_int i;
	u_int slot;
	for (i = 0; i < SPITFIRE_TLB_ENTRIES; i++) {
		slot = TLB_DAR_SLOT(TLB_DAR_T32, i);
		data = ldxa(slot, ASI_DTLB_DATA_ACCESS_REG);
		tag = ldxa(slot, ASI_DTLB_TAG_READ_REG);
		if ((data & TD_V) != 0 && (data & TD_L) == 0 &&
		    TLB_TAR_CTX(tag) != TLB_CTX_KERNEL)
			stxa_sync(slot, ASI_DTLB_DATA_ACCESS_REG, 0);
		data = ldxa(slot, ASI_ITLB_DATA_ACCESS_REG);
		tag = ldxa(slot, ASI_ITLB_TAG_READ_REG);
		if ((data & TD_V) != 0 && (data & TD_L) == 0 &&
		    TLB_TAR_CTX(tag) != TLB_CTX_KERNEL)
			stxa_sync(slot, ASI_ITLB_DATA_ACCESS_REG, 0);
	}
}
void spitfire_tlb_flush_user ( void ) { u_long data ; u_long tag ; u_int i ; u_int slot ; for ( i = 0 ; i < SPITFIRE_TLB_ENTRIES ; i ++ ) { slot = TLB_DAR_SLOT ( TLB_DAR_T32 , i ) ; data = ldxa ( slot , ASI_DTLB_DATA_ACCESS_REG ) ; tag = ldxa ( slot , ASI_DTLB_TAG_READ_REG ) ; if ( ( data & TD_V ) != 0 && ( data & TD_L ) == 0 && TLB_TAR_CTX ( tag ) != TLB_CTX_KERNEL ) stxa_sync ( slot , ASI_DTLB_DATA_ACCESS_REG , 0 ) ; data = ldxa ( slot , ASI_ITLB_DATA_ACCESS_REG ) ; tag = ldxa ( slot , ASI_ITLB_TAG_READ_REG ) ; if ( ( data & TD_V ) != 0 && ( data & TD_L ) == 0 && TLB_TAR_CTX ( tag ) != TLB_CTX_KERNEL ) stxa_sync ( slot , ASI_ITLB_DATA_ACCESS_REG , 0 ) ; } }
Flush all user mappings from the TLBs.
Flush all user mappings from the TLBs .