FreeBSD/sys/dev/ixl/ixl_pf_main.c
/*
 * Configure for MSI single vector operation 
 */
Configure for MSI single vector operation
Configure for MSI single vector operation
void
ixl_configure_legacy(struct ixl_pf *pf)
{
	struct i40e_hw	*hw = &pf->hw;
	u32		reg;
	wr32(hw, I40E_PFINT_ITR0(0), 0);
	wr32(hw, I40E_PFINT_ITR0(1), 0);
	reg = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK
	    | I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK
	    | I40E_PFINT_ICR0_ENA_GRST_MASK
	    | I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK
	    | I40E_PFINT_ICR0_ENA_GPIO_MASK
	    | I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK
	    | I40E_PFINT_ICR0_ENA_HMC_ERR_MASK
	    | I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK
	    | I40E_PFINT_ICR0_ENA_VFLR_MASK
	    | I40E_PFINT_ICR0_ENA_ADMINQ_MASK
	    ;
	wr32(hw, I40E_PFINT_ICR0_ENA, reg);
	wr32(hw, I40E_PFINT_DYN_CTL0,
	    I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK |
	    I40E_PFINT_DYN_CTLN_INTENA_MSK_MASK);
	wr32(hw, I40E_PFINT_STAT_CTL0, 0);
	wr32(hw, I40E_PFINT_LNKLST0, 0);
	reg = I40E_QINT_RQCTL_CAUSE_ENA_MASK
	    | (IXL_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT)
	    | (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
	wr32(hw, I40E_QINT_RQCTL(0), reg);
	reg = I40E_QINT_TQCTL_CAUSE_ENA_MASK
	    | (IXL_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT)
	    | (IXL_QUEUE_EOL << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
	wr32(hw, I40E_QINT_TQCTL(0), reg);
}
void ixl_configure_legacy ( struct ixl_pf * pf ) { struct i40e_hw * hw = & pf -> hw ; u32 reg ; wr32 ( hw , I40E_PFINT_ITR0 ( 0 ) , 0 ) ; wr32 ( hw , I40E_PFINT_ITR0 ( 1 ) , 0 ) ; reg = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | I40E_PFINT_ICR0_ENA_GRST_MASK | I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | I40E_PFINT_ICR0_ENA_GPIO_MASK | I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | I40E_PFINT_ICR0_ENA_VFLR_MASK | I40E_PFINT_ICR0_ENA_ADMINQ_MASK ; wr32 ( hw , I40E_PFINT_ICR0_ENA , reg ) ; wr32 ( hw , I40E_PFINT_DYN_CTL0 , I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK | I40E_PFINT_DYN_CTLN_INTENA_MSK_MASK ) ; wr32 ( hw , I40E_PFINT_STAT_CTL0 , 0 ) ; wr32 ( hw , I40E_PFINT_LNKLST0 , 0 ) ; reg = I40E_QINT_RQCTL_CAUSE_ENA_MASK | ( IXL_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT ) | ( I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT ) ; wr32 ( hw , I40E_QINT_RQCTL ( 0 ) , reg ) ; reg = I40E_QINT_TQCTL_CAUSE_ENA_MASK | ( IXL_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT ) | ( IXL_QUEUE_EOL << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT ) ; wr32 ( hw , I40E_QINT_TQCTL ( 0 ) , reg ) ; }
Configure for MSI single vector operation
Configure for MSI single vector operation
/* Setup "other" causes */ /* SW_ITR_IDX = 0, but don't change INTENA */ /* SW_ITR_IDX = 0, OTHER_ITR_IDX = 0 */ /* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */ /* Associate the queue pair to the vector and enable the q int */