import/chips/p9/procedures/ppe_closed/sgpe/stop_gpe/p9_sgpe_stop_init.c
// assume ex partial good checked by the caller
// if going to boot cme of the ex and calling this function to prepare
assume ex partial good checked by the caller
if going to boot cme of the ex and calling this function to prepare
assume ex partial good checked by the caller if going to boot cme of the ex and calling this function to prepare
void p9_sgpe_stop_cme_scominit(uint32_t quad, uint32_t cme, uint32_t cme_flags)
{
    uint32_t chtm_mask = 0;
    uint64_t chtm_size = 0;
    data64_t scom_data = {0};
    if (G_sgpe_stop_record.group.quad[VECTOR_BLOCKE] & BIT32(quad))
    {
        cme_flags |= BIT32(CME_FLAGS_BLOCK_ENTRY_STOP11);
    }
    GPE_GETSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_FLAGS,     quad, cme), scom_data.value);
    cme_flags |= (scom_data.words.upper & BIT32(CME_FLAGS_SPWU_CHECK_ENABLE));
    PK_TRACE("Setup CME Flags");
    GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_FLAGS,     quad, cme), ((uint64_t)cme_flags) << 32);
    PK_TRACE("Clear Scratch0/1 Registers");
    GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SRTCH0,    quad, cme), 0);
    GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_SRTCH1,    quad, cme), 0);
    PK_TRACE("Setup CME SRAM Scrub Engine via CSCR[1,47:59]");
    GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_CSCR_CLR,  quad, cme), BITS64(47, 13));
    GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_CSCR_OR,   quad, cme), BIT64(1));
    PK_TRACE("Setup CME FIR Act0/Act1/Mask for CME_LFIR[0,1,2,3,4]");
    GPE_GETSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LFIRACT0, quad, cme), scom_data.value);
    scom_data.value |= BITS64(0, 5);
    GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LFIRACT0, quad, cme), scom_data.value);
    GPE_GETSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LFIRACT1, quad, cme), scom_data.value);
    scom_data.value &= ~BITS64(0, 5);
    GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LFIRACT1, quad, cme), scom_data.value);
    GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_LFIRMASK_AND, quad, cme), ~BITS64(0, 5));
    PK_TRACE("Allow the CME to access the PCB Slave NET_CTRL registers");
    if (cme_flags & 0x2)
    {
        GPE_GETSCOM(GPE_SCOM_ADDR_CORE(C_SLAVE_CONFIG,
                                       ((quad << 2) + (cme << 1))),     scom_data.value);
        scom_data.words.upper &= ~BITS32(6, 2);
        GPE_PUTSCOM(GPE_SCOM_ADDR_CORE(C_SLAVE_CONFIG,
                                       ((quad << 2) + (cme << 1))),     scom_data.value);
    }
    if (cme_flags & 0x1)
    {
        GPE_GETSCOM(GPE_SCOM_ADDR_CORE(C_SLAVE_CONFIG,
                                       ((quad << 2) + (cme << 1) + 1)), scom_data.value);
        scom_data.words.upper &= ~BITS32(6, 2);
        GPE_PUTSCOM(GPE_SCOM_ADDR_CORE(C_SLAVE_CONFIG,
                                       ((quad << 2) + (cme << 1) + 1)), scom_data.value);
    }
     Trace configuration
     CME_LCL_DBG
     0: LCL_EN_DBG
     4: LCL_EN_INTR_ADDR
     5: LCL_EN_TRACE_EXTRA
     6: LCL_EN_TRACE_STALL
     7: LCL_EN_WAIT_CYCLES
     8: LCL_EN_FULL_SPEED
     inst: 3D20C000 | addis r9, 0, 0xC000 | R9 = 0xC0000000
     inst: 3C208F80 | addis r1, 0, 0x8F80 | R1 = 0x8F800000
     HTM mode, if enabled, forces only 64 bits of data
     inst: 38210300 | addi  r1, r1, 0x300 | R1 = 0x8F800300
     inst: 90290120 | stw   r1, 0x120(r9) | 0xC0000120 = R1
     This configures L3 Trace array to receive CME data
     1. The trace array has to be stopped to configure it
     2. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRCTRL_CONFIG
        bit0: store_trig_mode_lt = 1
        bit 11 enh_trace_mode = 1
        bit 14:15 = trace_select_lt = 10 for CME0
     3. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRDATA_CONFIG_0
        Set trace data compare mask to 0  (0:63)
     4. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRDATA_CONFIG_1
        Set trace data compare mask to 0  (64:87)
     5. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRDATA_CONFIG_4
        Clear MSKa, MSKb
     6. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRDATA_CONFIG_5
        Clear MSKc, MSKd
     7. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRDATA_CONFIG_9
         bit 0 = disable compression:
         bit 1 = error_bit_compresion_care_mask
                 (default is zero so should be enabled)
         32  msk_err_q                <= error_mode_lt(0);
         33  pat_err_q                <= error_mode_lt(1);
         34  trig0_err_msk            <= error_mode_lt(2);
         35  trig1_err_msk            <= error_mode_lt(3);
         match_err                    <= (msk_err_q or not pat_err_q)
                                         xor error_stage_lt(0);
         mask = 0 and pattern = 1 and may be trigger 0
    sgpeHeader_t* pSgpeImgHdr = (sgpeHeader_t*)(OCC_SRAM_SGPE_HEADER_ADDR);
    if (pSgpeImgHdr->g_sgpe_reserve_flags & SGPE_ENABLE_CME_TRACE_ARRAY_BIT_POS)
    {
         Stop the trace to configure it
        GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(DEBUG_TRACE_CONTROL, quad), BIT64(1));
        PK_TRACE("Configure and Enable L3 Trace Array to receive CME data");
        GPE_PUTSCOM(GPE_SCOM_ADDR_EX(CME_SCOM_XIRAMEDR, quad, cme), 0x3D20C00000000000);
        GPE_PUTSCOM(GPE_SCOM_ADDR_EX(CME_SCOM_XIRAMEDR, quad, cme), 0x3C20888000000000);
        if (pSgpeImgHdr->g_sgpe_reserve_flags & SGPE_ENABLE_CHTM_TRACE_CME_BIT_POS)
        {
            PK_TRACE("Puttng PPE in 64 bit data mode before enable CHTM");
            GPE_PUTSCOM(GPE_SCOM_ADDR_CME(CME_SCOM_XIRAMEDR, quad, cme), 0x3821030000000000);
        }
        GPE_PUTSCOM(GPE_SCOM_ADDR_EX(CME_SCOM_XIRAMEDR, quad, cme), 0x9029012000000000);
        GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(
                        (L3TRA_TRACE_TRCTRL_CONFIG   | (cme << 7)), quad), (BIT64(0) | BIT64(11) | BIT64(14)));
        GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(
                        (L3TRA_TRACE_TRDATA_CONFIG_0 | (cme << 7)), quad), 0);
        GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(
                        (L3TRA_TRACE_TRDATA_CONFIG_1 | (cme << 7)), quad), 0);
        GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(
                        (L3TRA_TRACE_TRDATA_CONFIG_4 | (cme << 7)), quad), 0);
        GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(
                        (L3TRA_TRACE_TRDATA_CONFIG_5 | (cme << 7)), quad), 0);
        GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(
                        (L3TRA_TRACE_TRDATA_CONFIG_9 | (cme << 7)), quad), BITS64(33, 2));
         Start the trace
        GPE_PUTSCOM(GPE_SCOM_ADDR_QUAD(DEBUG_TRACE_CONTROL, quad), BIT64(0));
    }
     Enable CHTM
     This configures CHTM to receive CME data
     Set up HTM_MODE: [0] = start, [1:2] = 0b10 PPE Trace
     Set up HTM_CTRL
     Clear memory allocated in HTM_MEM
     Allocate memory in HTM_MEM
       allow the user to have full control over size and starting address
     Reset triggers
     Start triggers
    if (pSgpeImgHdr->g_sgpe_reserve_flags & SGPE_ENABLE_CHTM_TRACE_CME_BIT_POS)
    {
        PK_TRACE("Configure and Enable CHTM to receive CME data");
        chtm_mask = (uint32_t)pSgpeImgHdr->g_sgpe_chtm_mem_cfg;
        chtm_mask = chtm_mask & BITS64SH(40, 9) >> SHIFT64SH(48);
        bit[5] size_small = 1, mask base[31:39,9] with size[40:48,9]
        if (pSgpeImgHdr->g_sgpe_chtm_mem_cfg & BIT64(5))
        {
            chtm_size = BIT64(39);  Base of 16M;
        }
        bit[5] size_small = 0, mask base[26:34,9] with size[40:48,9]
        else
        {
            chtm_size = BIT64(34);  Base of 512M
        }
         Note: it isn't 100% because it only uses the # of bits in the mask,
               but it isn't valid to configure the mask other ways
        while (chtm_mask != 0)
        {
            chtm_size = chtm_size << 1;
            chtm_mask = chtm_mask >> 1;
        }
        scom_data.value = BIT64(0) +
                          pSgpeImgHdr->g_sgpe_chtm_mem_cfg +
                          chtm_size * ((quad << 1) + cme);
         CME Trace is routed through CHTM1
        GPE_PUTSCOM(GPE_SCOM_ADDR_EX((EX_CHTM1_MODE_REG), quad, cme), 0xC00F000000000000);
        GPE_PUTSCOM(GPE_SCOM_ADDR_EX((EX_CHTM1_CTRL_REG), quad, cme), 0x7404000000000000);
        GPE_PUTSCOM(GPE_SCOM_ADDR_EX((EX_CHTM1_MEM_REG),  quad, cme), 0);
        GPE_PUTSCOM(GPE_SCOM_ADDR_EX((EX_CHTM1_MEM_REG),  quad, cme), scom_data.value);
        GPE_PUTSCOM(GPE_SCOM_ADDR_EX((EX_CHTM1_TRIG_REG), quad, cme), BIT64(4));
        GPE_PUTSCOM(GPE_SCOM_ADDR_EX((EX_CHTM1_TRIG_REG), quad, cme), BIT64(0));
    }
}
void p9_sgpe_stop_cme_scominit ( uint32_t quad , uint32_t cme , uint32_t cme_flags ) { uint32_t chtm_mask = 0 ; uint64_t chtm_size = 0 ; data64_t scom_data = { 0 } ; if ( G_sgpe_stop_record . group . quad [ VECTOR_BLOCKE ] & BIT32 ( quad ) ) { cme_flags |= BIT32 ( CME_FLAGS_BLOCK_ENTRY_STOP11 ) ; } GPE_GETSCOM ( GPE_SCOM_ADDR_CME ( CME_SCOM_FLAGS , quad , cme ) , scom_data . value ) ; cme_flags |= ( scom_data . words . upper & BIT32 ( CME_FLAGS_SPWU_CHECK_ENABLE ) ) ; PK_TRACE ( " " ) ; GPE_PUTSCOM ( GPE_SCOM_ADDR_CME ( CME_SCOM_FLAGS , quad , cme ) , ( ( uint64_t ) cme_flags ) << 32 ) ; PK_TRACE ( " " ) ; GPE_PUTSCOM ( GPE_SCOM_ADDR_CME ( CME_SCOM_SRTCH0 , quad , cme ) , 0 ) ; GPE_PUTSCOM ( GPE_SCOM_ADDR_CME ( CME_SCOM_SRTCH1 , quad , cme ) , 0 ) ; PK_TRACE ( " " ) ; GPE_PUTSCOM ( GPE_SCOM_ADDR_CME ( CME_SCOM_CSCR_CLR , quad , cme ) , BITS64 ( 47 , 13 ) ) ; GPE_PUTSCOM ( GPE_SCOM_ADDR_CME ( CME_SCOM_CSCR_OR , quad , cme ) , BIT64 ( 1 ) ) ; PK_TRACE ( " " ) ; GPE_GETSCOM ( GPE_SCOM_ADDR_CME ( CME_SCOM_LFIRACT0 , quad , cme ) , scom_data . value ) ; scom_data . value |= BITS64 ( 0 , 5 ) ; GPE_PUTSCOM ( GPE_SCOM_ADDR_CME ( CME_SCOM_LFIRACT0 , quad , cme ) , scom_data . value ) ; GPE_GETSCOM ( GPE_SCOM_ADDR_CME ( CME_SCOM_LFIRACT1 , quad , cme ) , scom_data . value ) ; scom_data . value &= ~ BITS64 ( 0 , 5 ) ; GPE_PUTSCOM ( GPE_SCOM_ADDR_CME ( CME_SCOM_LFIRACT1 , quad , cme ) , scom_data . value ) ; GPE_PUTSCOM ( GPE_SCOM_ADDR_CME ( CME_SCOM_LFIRMASK_AND , quad , cme ) , ~ BITS64 ( 0 , 5 ) ) ; PK_TRACE ( " " ) ; if ( cme_flags & 0x2 ) { GPE_GETSCOM ( GPE_SCOM_ADDR_CORE ( C_SLAVE_CONFIG , ( ( quad << 2 ) + ( cme << 1 ) ) ) , scom_data . value ) ; scom_data . words . upper &= ~ BITS32 ( 6 , 2 ) ; GPE_PUTSCOM ( GPE_SCOM_ADDR_CORE ( C_SLAVE_CONFIG , ( ( quad << 2 ) + ( cme << 1 ) ) ) , scom_data . value ) ; } if ( cme_flags & 0x1 ) { GPE_GETSCOM ( GPE_SCOM_ADDR_CORE ( C_SLAVE_CONFIG , ( ( quad << 2 ) + ( cme << 1 ) + 1 ) ) , scom_data . value ) ; scom_data . words . upper &= ~ BITS32 ( 6 , 2 ) ; GPE_PUTSCOM ( GPE_SCOM_ADDR_CORE ( C_SLAVE_CONFIG , ( ( quad << 2 ) + ( cme << 1 ) + 1 ) ) , scom_data . value ) ; } sgpeHeader_t * pSgpeImgHdr = ( sgpeHeader_t * ) ( OCC_SRAM_SGPE_HEADER_ADDR ) ; if ( pSgpeImgHdr -> g_sgpe_reserve_flags & SGPE_ENABLE_CME_TRACE_ARRAY_BIT_POS ) { GPE_PUTSCOM ( GPE_SCOM_ADDR_QUAD ( DEBUG_TRACE_CONTROL , quad ) , BIT64 ( 1 ) ) ; PK_TRACE ( " " ) ; GPE_PUTSCOM ( GPE_SCOM_ADDR_EX ( CME_SCOM_XIRAMEDR , quad , cme ) , 0x3D20C00000000000 ) ; GPE_PUTSCOM ( GPE_SCOM_ADDR_EX ( CME_SCOM_XIRAMEDR , quad , cme ) , 0x3C20888000000000 ) ; if ( pSgpeImgHdr -> g_sgpe_reserve_flags & SGPE_ENABLE_CHTM_TRACE_CME_BIT_POS ) { PK_TRACE ( " " ) ; GPE_PUTSCOM ( GPE_SCOM_ADDR_CME ( CME_SCOM_XIRAMEDR , quad , cme ) , 0x3821030000000000 ) ; } GPE_PUTSCOM ( GPE_SCOM_ADDR_EX ( CME_SCOM_XIRAMEDR , quad , cme ) , 0x9029012000000000 ) ; GPE_PUTSCOM ( GPE_SCOM_ADDR_QUAD ( ( L3TRA_TRACE_TRCTRL_CONFIG | ( cme << 7 ) ) , quad ) , ( BIT64 ( 0 ) | BIT64 ( 11 ) | BIT64 ( 14 ) ) ) ; GPE_PUTSCOM ( GPE_SCOM_ADDR_QUAD ( ( L3TRA_TRACE_TRDATA_CONFIG_0 | ( cme << 7 ) ) , quad ) , 0 ) ; GPE_PUTSCOM ( GPE_SCOM_ADDR_QUAD ( ( L3TRA_TRACE_TRDATA_CONFIG_1 | ( cme << 7 ) ) , quad ) , 0 ) ; GPE_PUTSCOM ( GPE_SCOM_ADDR_QUAD ( ( L3TRA_TRACE_TRDATA_CONFIG_4 | ( cme << 7 ) ) , quad ) , 0 ) ; GPE_PUTSCOM ( GPE_SCOM_ADDR_QUAD ( ( L3TRA_TRACE_TRDATA_CONFIG_5 | ( cme << 7 ) ) , quad ) , 0 ) ; GPE_PUTSCOM ( GPE_SCOM_ADDR_QUAD ( ( L3TRA_TRACE_TRDATA_CONFIG_9 | ( cme << 7 ) ) , quad ) , BITS64 ( 33 , 2 ) ) ; GPE_PUTSCOM ( GPE_SCOM_ADDR_QUAD ( DEBUG_TRACE_CONTROL , quad ) , BIT64 ( 0 ) ) ; } if ( pSgpeImgHdr -> g_sgpe_reserve_flags & SGPE_ENABLE_CHTM_TRACE_CME_BIT_POS ) { PK_TRACE ( " " ) ; chtm_mask = ( uint32_t ) pSgpeImgHdr -> g_sgpe_chtm_mem_cfg ; chtm_mask = chtm_mask & BITS64SH ( 40 , 9 ) >> SHIFT64SH ( 48 ) ; if ( pSgpeImgHdr -> g_sgpe_chtm_mem_cfg & BIT64 ( 5 ) ) { chtm_size = BIT64 ( 39 ) ; } else { chtm_size = BIT64 ( 34 ) ; } while ( chtm_mask != 0 ) { chtm_size = chtm_size << 1 ; chtm_mask = chtm_mask >> 1 ; } scom_data . value = BIT64 ( 0 ) + pSgpeImgHdr -> g_sgpe_chtm_mem_cfg + chtm_size * ( ( quad << 1 ) + cme ) ; GPE_PUTSCOM ( GPE_SCOM_ADDR_EX ( ( EX_CHTM1_MODE_REG ) , quad , cme ) , 0xC00F000000000000 ) ; GPE_PUTSCOM ( GPE_SCOM_ADDR_EX ( ( EX_CHTM1_CTRL_REG ) , quad , cme ) , 0x7404000000000000 ) ; GPE_PUTSCOM ( GPE_SCOM_ADDR_EX ( ( EX_CHTM1_MEM_REG ) , quad , cme ) , 0 ) ; GPE_PUTSCOM ( GPE_SCOM_ADDR_EX ( ( EX_CHTM1_MEM_REG ) , quad , cme ) , scom_data . value ) ; GPE_PUTSCOM ( GPE_SCOM_ADDR_EX ( ( EX_CHTM1_TRIG_REG ) , quad , cme ) , BIT64 ( 4 ) ) ; GPE_PUTSCOM ( GPE_SCOM_ADDR_EX ( ( EX_CHTM1_TRIG_REG ) , quad , cme ) , BIT64 ( 0 ) ) ; } }
assume ex partial good checked by the caller
if going to boot cme of the ex and calling this function to prepare
assume ex partial good checked by the caller if going to boot cme of the ex and calling this function to prepare
//CME_LFIR[0,1,2,3,4] should generate CME PCB Error Packet(type5 owned by PGPE) //(1,0,0)(Act0,Act1,Mask) = CME PCB Error Packet // check core partial good // enable cme trace array // // Trace configuration // CME_LCL_DBG // 0: LCL_EN_DBG // 4: LCL_EN_INTR_ADDR // 5: LCL_EN_TRACE_EXTRA // 6: LCL_EN_TRACE_STALL // 7: LCL_EN_WAIT_CYCLES // 8: LCL_EN_FULL_SPEED // inst: 3D20C000 | addis r9, 0, 0xC000 | R9 = 0xC0000000 // inst: 3C208F80 | addis r1, 0, 0x8F80 | R1 = 0x8F800000 // HTM mode, if enabled, forces only 64 bits of data // inst: 38210300 | addi  r1, r1, 0x300 | R1 = 0x8F800300 // inst: 90290120 | stw   r1, 0x120(r9) | 0xC0000120 = R1 // // This configures L3 Trace array to receive CME data // 1. The trace array has to be stopped to configure it // 2. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRCTRL_CONFIG //    bit0: store_trig_mode_lt = 1 //    bit 11 enh_trace_mode = 1 //    bit 14:15 = trace_select_lt = 10 for CME0 // 3. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRDATA_CONFIG_0 //    Set trace data compare mask to 0  (0:63) // 4. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRDATA_CONFIG_1 //    Set trace data compare mask to 0  (64:87) // 5. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRDATA_CONFIG_4 //    Clear MSKa, MSKb // 6. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRDATA_CONFIG_5 //    Clear MSKc, MSKd // 7. TP.TCEP03.TPCL3.L3TRA0.TR0.TRACE_TRDATA_CONFIG_9 //     bit 0 = disable compression: //     bit 1 = error_bit_compresion_care_mask //             (default is zero so should be enabled) //     32  msk_err_q                <= error_mode_lt(0); //     33  pat_err_q                <= error_mode_lt(1); //     34  trig0_err_msk            <= error_mode_lt(2); //     35  trig1_err_msk            <= error_mode_lt(3); //     match_err                    <= (msk_err_q or not pat_err_q) //                                     xor error_stage_lt(0); //     mask = 0 and pattern = 1 and may be trigger 0 // Stop the trace to configure it // Start the trace // Enable CHTM // // This configures CHTM to receive CME data // Set up HTM_MODE: [0] = start, [1:2] = 0b10 PPE Trace // Set up HTM_CTRL // Clear memory allocated in HTM_MEM // Allocate memory in HTM_MEM //   allow the user to have full control over size and starting address // Reset triggers // Start triggers //bit[5] size_small = 1, mask base[31:39,9] with size[40:48,9] // Base of 16M; //bit[5] size_small = 0, mask base[26:34,9] with size[40:48,9] // Base of 512M // Note: it isn't 100% because it only uses the # of bits in the mask, //       but it isn't valid to configure the mask other ways // CME Trace is routed through CHTM1