KugleFirmware/Drivers/STM32H7xx_HAL_Driver/Src/stm32h7xx_hal_rcc.c
/**
  * @brief  Initializes the CPU, AHB and APB buses clocks according to the specified 
  *         parameters in the RCC_ClkInitStruct.
  * @param  RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
  *         contains the configuration information for the RCC peripheral.
  * @param  FLatency: FLASH Latency, this parameter depend on device selected
  * 
  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency 
  *         and updated by HAL_InitTick() function called within this function
  *
  * @note   The HSI is used (enabled by hardware) as system clock source after
  *         start-up from Reset, wake-up from STOP and STANDBY mode, or in case
  *         of failure of the HSE used directly or indirectly as system clock
  *         (if the Clock Security System CSS is enabled).
  *           
  * @note   A switch from one clock source to another occurs only if the target
  *         clock source is ready (clock stable after start-up delay or PLL locked). 
  *         If a clock source which is not yet ready is selected, the switch will
  *         occur when the clock source will be ready. 
  *         You can use HAL_RCC_GetClockConfig() function to know which clock is
  *         currently used as system clock source.
  * @note   Depending on the device voltage range, the software has to set correctly
  *         D1CPRE[3:0] bits to ensure that  Domain1 core clock not exceed the maximum allowed frequency
  *         (for more details refer to section above "Initialization/de-initialization functions")
  * @retval None
  */
@brief  Initializes the CPU, AHB and APB buses clocks according to the specified
parameters in the RCC_ClkInitStruct.
@param  RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
contains the configuration information for the RCC peripheral.
@param  FLatency: FLASH Latency, this parameter depend on device selected

@note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
and updated by HAL_InitTick() function called within this function

@note   The HSI is used (enabled by hardware) as system clock source after
start-up from Reset, wake-up from STOP and STANDBY mode, or in case
of failure of the HSE used directly or indirectly as system clock
(if the Clock Security System CSS is enabled).

@note   A switch from one clock source to another occurs only if the target
clock source is ready (clock stable after start-up delay or PLL locked).
If a clock source which is not yet ready is selected, the switch will
occur when the clock source will be ready.
You can use HAL_RCC_GetClockConfig() function to know which clock is
currently used as system clock source.
@note   Depending on the device voltage range, the software has to set correctly
D1CPRE[3:0] bits to ensure that  Domain1 core clock not exceed the maximum allowed frequency
(for more details refer to section above "Initialization/de-initialization functions")
@retval None
@brief Initializes the CPU AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct . @param RCC_ClkInitStruct : pointer to an RCC_OscInitTypeDef structure that contains the configuration information for the RCC peripheral . @param FLatency : FLASH Latency this parameter depend on device selected @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency and updated by HAL_InitTick () function called within this function @note The HSI is used ( enabled by hardware ) as system clock source after start - up from Reset wake - up from STOP and STANDBY mode or in case of failure of the HSE used directly or indirectly as system clock ( if the Clock Security System CSS is enabled ) . @note A switch from one clock source to another occurs only if the target clock source is ready ( clock stable after start - up delay or PLL locked ) . If a clock source which is not yet ready is selected the switch will occur when the clock source will be ready . You can use HAL_RCC_GetClockConfig () function to know which clock is currently used as system clock source . @note Depending on the device voltage range the software has to set correctly D1CPRE [ 3 : 0 ] bits to ensure that Domain1 core clock not exceed the maximum allowed frequency ( for more details refer to section above " Initialization / de - initialization functions " ) @retval None
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
{
  uint32_t tickstart = 0;
  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
  assert_param(IS_FLASH_LATENCY(FLatency));
  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
  {
    __HAL_FLASH_SET_LATENCY(FLatency);
    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
    {
      return HAL_ERROR;
    }
  }
    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
    {
      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
    }
    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
    {
      assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider));
      assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
      MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider);
      if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
      {
        if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
        {
          return HAL_ERROR;
        }
      }
      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
      {
        if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
        {
          return HAL_ERROR;
        }
      }
      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI)
      {
        if(__HAL_RCC_GET_FLAG(RCC_FLAG_CSIRDY) == RESET)
        {
          return HAL_ERROR;
        }
      }
      else
      {
        if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
        {
          return HAL_ERROR;
        }
      }
      MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
      tickstart = HAL_GetTick();
      if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
      {
        while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
        {
          if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
          {
            return HAL_TIMEOUT;
          }
        }
      }
      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
      {
        while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL1)
        {
          if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
          {
            return HAL_TIMEOUT;
          }
        }
      }
      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_CSI)
      {
        while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_CSI)
        {
          if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
          {
            return HAL_TIMEOUT;
          }
        }
      }
      else
      {
        while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
        {
          if((int32_t) (HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
          {
            return HAL_TIMEOUT;
          }
        }
      }
    }
  if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
  {
    __HAL_FLASH_SET_LATENCY(FLatency);
    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
    {
      return HAL_ERROR;
    }
 }
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D1PCLK1) == RCC_CLOCKTYPE_D1PCLK1)
  {
    assert_param(IS_RCC_D1PCLK1(RCC_ClkInitStruct->APB3CLKDivider));
    MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
  }
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
  {
    assert_param(IS_RCC_PCLK1(RCC_ClkInitStruct->APB1CLKDivider));
    MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
  }
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
  {
    assert_param(IS_RCC_PCLK2(RCC_ClkInitStruct->APB2CLKDivider));
    MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
  }
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_D3PCLK1) == RCC_CLOCKTYPE_D3PCLK1)
  {
    assert_param(IS_RCC_D3PCLK1(RCC_ClkInitStruct->APB4CLKDivider));
    MODIFY_REG(RCC->D3CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB4CLKDivider) );
  }
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> POSITION_VAL(RCC_D1CFGR_D1CPRE_0)];
  HAL_InitTick (TICK_INT_PRIORITY);
  return HAL_OK;
}
HAL_StatusTypeDef HAL_RCC_ClockConfig ( RCC_ClkInitTypeDef * RCC_ClkInitStruct , uint32_t FLatency ) { uint32_t tickstart = 0 ; assert_param ( IS_RCC_CLOCKTYPE ( RCC_ClkInitStruct -> ClockType ) ) ; assert_param ( IS_FLASH_LATENCY ( FLatency ) ) ; if ( FLatency > ( FLASH -> ACR & FLASH_ACR_LATENCY ) ) { __HAL_FLASH_SET_LATENCY ( FLatency ) ; if ( ( FLASH -> ACR & FLASH_ACR_LATENCY ) != FLatency ) { return HAL_ERROR ; } } if ( ( ( RCC_ClkInitStruct -> ClockType ) & RCC_CLOCKTYPE_HCLK ) == RCC_CLOCKTYPE_HCLK ) { assert_param ( IS_RCC_HCLK ( RCC_ClkInitStruct -> AHBCLKDivider ) ) ; MODIFY_REG ( RCC -> D1CFGR , RCC_D1CFGR_HPRE , RCC_ClkInitStruct -> AHBCLKDivider ) ; } if ( ( ( RCC_ClkInitStruct -> ClockType ) & RCC_CLOCKTYPE_SYSCLK ) == RCC_CLOCKTYPE_SYSCLK ) { assert_param ( IS_RCC_SYSCLK ( RCC_ClkInitStruct -> SYSCLKDivider ) ) ; assert_param ( IS_RCC_SYSCLKSOURCE ( RCC_ClkInitStruct -> SYSCLKSource ) ) ; MODIFY_REG ( RCC -> D1CFGR , RCC_D1CFGR_D1CPRE , RCC_ClkInitStruct -> SYSCLKDivider ) ; if ( RCC_ClkInitStruct -> SYSCLKSource == RCC_SYSCLKSOURCE_HSE ) { if ( __HAL_RCC_GET_FLAG ( RCC_FLAG_HSERDY ) == RESET ) { return HAL_ERROR ; } } else if ( RCC_ClkInitStruct -> SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK ) { if ( __HAL_RCC_GET_FLAG ( RCC_FLAG_PLLRDY ) == RESET ) { return HAL_ERROR ; } } else if ( RCC_ClkInitStruct -> SYSCLKSource == RCC_SYSCLKSOURCE_CSI ) { if ( __HAL_RCC_GET_FLAG ( RCC_FLAG_CSIRDY ) == RESET ) { return HAL_ERROR ; } } else { if ( __HAL_RCC_GET_FLAG ( RCC_FLAG_HSIRDY ) == RESET ) { return HAL_ERROR ; } } MODIFY_REG ( RCC -> CFGR , RCC_CFGR_SW , RCC_ClkInitStruct -> SYSCLKSource ) ; tickstart = HAL_GetTick ( ) ; if ( RCC_ClkInitStruct -> SYSCLKSource == RCC_SYSCLKSOURCE_HSE ) { while ( __HAL_RCC_GET_SYSCLK_SOURCE ( ) != RCC_CFGR_SWS_HSE ) { if ( ( int32_t ) ( HAL_GetTick ( ) - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE ) { return HAL_TIMEOUT ; } } } else if ( RCC_ClkInitStruct -> SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK ) { while ( __HAL_RCC_GET_SYSCLK_SOURCE ( ) != RCC_CFGR_SWS_PLL1 ) { if ( ( int32_t ) ( HAL_GetTick ( ) - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE ) { return HAL_TIMEOUT ; } } } else if ( RCC_ClkInitStruct -> SYSCLKSource == RCC_SYSCLKSOURCE_CSI ) { while ( __HAL_RCC_GET_SYSCLK_SOURCE ( ) != RCC_CFGR_SWS_CSI ) { if ( ( int32_t ) ( HAL_GetTick ( ) - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE ) { return HAL_TIMEOUT ; } } } else { while ( __HAL_RCC_GET_SYSCLK_SOURCE ( ) != RCC_CFGR_SWS_HSI ) { if ( ( int32_t ) ( HAL_GetTick ( ) - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE ) { return HAL_TIMEOUT ; } } } } if ( FLatency < ( FLASH -> ACR & FLASH_ACR_LATENCY ) ) { __HAL_FLASH_SET_LATENCY ( FLatency ) ; if ( ( FLASH -> ACR & FLASH_ACR_LATENCY ) != FLatency ) { return HAL_ERROR ; } } if ( ( ( RCC_ClkInitStruct -> ClockType ) & RCC_CLOCKTYPE_D1PCLK1 ) == RCC_CLOCKTYPE_D1PCLK1 ) { assert_param ( IS_RCC_D1PCLK1 ( RCC_ClkInitStruct -> APB3CLKDivider ) ) ; MODIFY_REG ( RCC -> D1CFGR , RCC_D1CFGR_D1PPRE , RCC_ClkInitStruct -> APB3CLKDivider ) ; } if ( ( ( RCC_ClkInitStruct -> ClockType ) & RCC_CLOCKTYPE_PCLK1 ) == RCC_CLOCKTYPE_PCLK1 ) { assert_param ( IS_RCC_PCLK1 ( RCC_ClkInitStruct -> APB1CLKDivider ) ) ; MODIFY_REG ( RCC -> D2CFGR , RCC_D2CFGR_D2PPRE1 , ( RCC_ClkInitStruct -> APB1CLKDivider ) ) ; } if ( ( ( RCC_ClkInitStruct -> ClockType ) & RCC_CLOCKTYPE_PCLK2 ) == RCC_CLOCKTYPE_PCLK2 ) { assert_param ( IS_RCC_PCLK2 ( RCC_ClkInitStruct -> APB2CLKDivider ) ) ; MODIFY_REG ( RCC -> D2CFGR , RCC_D2CFGR_D2PPRE2 , ( RCC_ClkInitStruct -> APB2CLKDivider ) ) ; } if ( ( ( RCC_ClkInitStruct -> ClockType ) & RCC_CLOCKTYPE_D3PCLK1 ) == RCC_CLOCKTYPE_D3PCLK1 ) { assert_param ( IS_RCC_D3PCLK1 ( RCC_ClkInitStruct -> APB4CLKDivider ) ) ; MODIFY_REG ( RCC -> D3CFGR , RCC_D2CFGR_D2PPRE1 , ( RCC_ClkInitStruct -> APB4CLKDivider ) ) ; } SystemCoreClock = HAL_RCC_GetSysClockFreq ( ) >> D1CorePrescTable [ ( RCC -> D1CFGR & RCC_D1CFGR_D1CPRE ) >> POSITION_VAL ( RCC_D1CFGR_D1CPRE_0 ) ] ; HAL_InitTick ( TICK_INT_PRIORITY ) ; return HAL_OK ; }
@brief  Initializes the CPU, AHB and APB buses clocks according to the specified
         parameters in the RCC_ClkInitStruct.
@brief Initializes the CPU AHB and APB buses clocks according to the specified parameters in the RCC_ClkInitStruct .
/* Check the parameters */ /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
    must be correctly programmed according to the frequency of the CPU clock
    (HCLK) and the supply voltage of the device. */ /* Increasing the CPU frequency */ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */ /*-------------------------- HCLK Configuration --------------------------*/ /*------------------------- SYSCLK Configuration -------------------------*/ /* HSE is selected as System Clock Source */ /* Check the HSE ready flag */ /* PLL is selected as System Clock Source */ /* Check the PLL ready flag */ /* CSI is selected as System Clock Source */ /* Check the PLL ready flag */ /* HSI is selected as System Clock Source */ /* Check the HSI ready flag */ /* Get Start Tick*/ /* Decreasing the number of wait states because of lower CPU frequency */ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */ /*-------------------------- D1PCLK1 Configuration ---------------------------*/ /*-------------------------- PCLK1 Configuration ---------------------------*/ /*-------------------------- PCLK2 Configuration ---------------------------*/ /*-------------------------- D3PCLK1 Configuration ---------------------------*/ /* Update the SystemCoreClock global variable */ /* Configure the source of time base considering new system clocks settings*/