FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/platform/mpfs_hal/common/mss_axiswitch.c
/* Reads the peak rate and transaction rate value for the given master port
read/write address channel
peak_rate: returns the value of peak rate
xct_rate: returns the value of transaction rate
return value: As received form AXI_ERR_BIT in CMD register.

*/
Reads the peak rate and transaction rate value for the given master port
read/write address channel
peak_rate: returns the value of peak rate
xct_rate: returns the value of transaction rate
return value: As received form AXI_ERR_BIT in CMD register.
Reads the peak rate and transaction rate value for the given master port read / write address channel peak_rate : returns the value of peak rate xct_rate : returns the value of transaction rate return value : As received form AXI_ERR_BIT in CMD register .
uint32_t MSS_AXISW_read_rate(mss_axisw_mport_t master_port_num,
                                          mss_axisw_rate_t* peak_rate,
                                          mss_axisw_rate_t* xct_rate)
{
    uint32_t temp = 0u;
    while(AXISW->CMD & AXISW_CMD_EN_MASK);
    AXISW->CMD &= ~(AXISW_CMD_RW_MASK);  
    AXISW->CMD = ((master_port_num << AXISW_CMD_RWCHAN) |
                 (MSS_AXISW_PEAKRT_XCTRT) |
                 AXISW_CMD_EN_MASK);
    while(AXISW->CMD & AXISW_CMD_EN_MASK);
    temp = AXISW->DATA;
    *peak_rate = (temp & AXISW_DATA_PEAKRT_MASK) >> AXISW_DATA_PEAKRT;
    *xct_rate = (temp & AXISW_DATA_XCTRT_MASK) >> AXISW_DATA_XCTRT;
    return ((AXISW->CMD & AXISW_CMD_ERR_MASK) >> AXISW_CMD_ERR);   
}
uint32_t MSS_AXISW_read_rate ( mss_axisw_mport_t master_port_num , mss_axisw_rate_t * peak_rate , mss_axisw_rate_t * xct_rate ) { uint32_t temp = 0u ; while ( AXISW -> CMD & AXISW_CMD_EN_MASK ) ; AXISW -> CMD &= ~ ( AXISW_CMD_RW_MASK ) ; AXISW -> CMD = ( ( master_port_num << AXISW_CMD_RWCHAN ) | ( MSS_AXISW_PEAKRT_XCTRT ) | AXISW_CMD_EN_MASK ) ; while ( AXISW -> CMD & AXISW_CMD_EN_MASK ) ; temp = AXISW -> DATA ; * peak_rate = ( temp & AXISW_DATA_PEAKRT_MASK ) >> AXISW_DATA_PEAKRT ; * xct_rate = ( temp & AXISW_DATA_XCTRT_MASK ) >> AXISW_DATA_XCTRT ; return ( ( AXISW -> CMD & AXISW_CMD_ERR_MASK ) >> AXISW_CMD_ERR ) ; }
Reads the peak rate and transaction rate value for the given master port
read/write address channel
peak_rate: returns the value of peak rate
xct_rate: returns the value of transaction rate
return value: As received form AXI_ERR_BIT in CMD register.
Reads the peak rate and transaction rate value for the given master port read / write address channel peak_rate : returns the value of peak rate xct_rate : returns the value of transaction rate return value : As received form AXI_ERR_BIT in CMD register .
/*Clear read/write and command EN bit*/ /*return error bit value*/