FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/platform/mpfs_hal/common/nwc/mss_pll.c
/**
 *
 * @param option choose between SCB or RPC and soft reset  update method.
 */
@param option choose between SCB or RPC and soft reset  update method.
@param option choose between SCB or RPC and soft reset update method .
void ddr_pll_config(REG_LOAD_METHOD option)
{
    switch(option)
    {
        default:
        case SCB_UPDATE:   
            MSS_SCB_DDR_PLL->SOFT_RESET       = PLL_INIT_AND_OUT_OF_RESET;
            MSS_SCB_DDR_PLL->PLL_CTRL         = LIBERO_SETTING_DDR_PLL_CTRL & ~(PLL_CTRL_REG_POWERDOWN_B_MASK);
            MSS_SCB_DDR_PLL->PLL_REF_FB    = LIBERO_SETTING_DDR_PLL_REF_FB;
            MSS_SCB_DDR_PLL->PLL_DIV_0_1   = LIBERO_SETTING_DDR_PLL_DIV_0_1;
            MSS_SCB_DDR_PLL->PLL_DIV_2_3   = LIBERO_SETTING_DDR_PLL_DIV_2_3;
            MSS_SCB_DDR_PLL->PLL_CTRL2     = LIBERO_SETTING_DDR_PLL_CTRL2;
            MSS_SCB_DDR_PLL->PLL_FRACN     = LIBERO_SETTING_DDR_PLL_FRACN;
            MSS_SCB_DDR_PLL->SSCG_REG_0    = LIBERO_SETTING_DDR_SSCG_REG_0;
            MSS_SCB_DDR_PLL->SSCG_REG_1    = LIBERO_SETTING_DDR_SSCG_REG_1;
            MSS_SCB_DDR_PLL->SSCG_REG_2    = LIBERO_SETTING_DDR_SSCG_REG_2;
            MSS_SCB_DDR_PLL->SSCG_REG_3    = LIBERO_SETTING_DDR_SSCG_REG_3;
            MSS_SCB_DDR_PLL->PLL_PHADJ     = LIBERO_SETTING_MSS_PLL_PHADJ;
            MSS_SCB_DDR_PLL->PLL_CTRL      = (LIBERO_SETTING_DDR_PLL_CTRL)\
                    | 0x01U;  
            break;
        case RPC_REG_UPDATE:
            CFG_DDR_SGMII_PHY->PLL_CTRL_MAIN.PLL_CTRL_MAIN        =\
                                        LIBERO_SETTING_DDR_PLL_CTRL | 0x01U;
            CFG_DDR_SGMII_PHY->PLL_REF_FB_MAIN.PLL_REF_FB_MAIN      =\
                                                LIBERO_SETTING_DDR_PLL_REF_FB;
            CFG_DDR_SGMII_PHY->PLL_DIV_0_1_MAIN.PLL_DIV_0_1_MAIN    =\
                                                LIBERO_SETTING_DDR_PLL_DIV_0_1;
            CFG_DDR_SGMII_PHY->PLL_DIV_2_3_MAIN.PLL_DIV_2_3_MAIN  =\
                                                LIBERO_SETTING_DDR_PLL_DIV_2_3;
            CFG_DDR_SGMII_PHY->PLL_CTRL2_MAIN.PLL_CTRL2_MAIN      =\
                                                   LIBERO_SETTING_DDR_PLL_CTRL2;
            CFG_DDR_SGMII_PHY->PLL_PHADJ_MAIN.PLL_PHADJ_MAIN      =\
                                                   LIBERO_SETTING_DDR_PLL_PHADJ;
            CFG_DDR_SGMII_PHY->SSCG_REG_2_MAIN.SSCG_REG_2_MAIN       =\
                                                LIBERO_SETTING_DDR_SSCG_REG_2;
            MSS_SCB_DDR_PLL->SOFT_RESET  = PLL_INIT_AND_OUT_OF_RESET;
            break;
    }
}
void ddr_pll_config ( REG_LOAD_METHOD option ) { switch ( option ) { default : case SCB_UPDATE : MSS_SCB_DDR_PLL -> SOFT_RESET = PLL_INIT_AND_OUT_OF_RESET ; MSS_SCB_DDR_PLL -> PLL_CTRL = LIBERO_SETTING_DDR_PLL_CTRL & ~ ( PLL_CTRL_REG_POWERDOWN_B_MASK ) ; MSS_SCB_DDR_PLL -> PLL_REF_FB = LIBERO_SETTING_DDR_PLL_REF_FB ; MSS_SCB_DDR_PLL -> PLL_DIV_0_1 = LIBERO_SETTING_DDR_PLL_DIV_0_1 ; MSS_SCB_DDR_PLL -> PLL_DIV_2_3 = LIBERO_SETTING_DDR_PLL_DIV_2_3 ; MSS_SCB_DDR_PLL -> PLL_CTRL2 = LIBERO_SETTING_DDR_PLL_CTRL2 ; MSS_SCB_DDR_PLL -> PLL_FRACN = LIBERO_SETTING_DDR_PLL_FRACN ; MSS_SCB_DDR_PLL -> SSCG_REG_0 = LIBERO_SETTING_DDR_SSCG_REG_0 ; MSS_SCB_DDR_PLL -> SSCG_REG_1 = LIBERO_SETTING_DDR_SSCG_REG_1 ; MSS_SCB_DDR_PLL -> SSCG_REG_2 = LIBERO_SETTING_DDR_SSCG_REG_2 ; MSS_SCB_DDR_PLL -> SSCG_REG_3 = LIBERO_SETTING_DDR_SSCG_REG_3 ; MSS_SCB_DDR_PLL -> PLL_PHADJ = LIBERO_SETTING_MSS_PLL_PHADJ ; MSS_SCB_DDR_PLL -> PLL_CTRL = ( LIBERO_SETTING_DDR_PLL_CTRL ) | 0x01U ; break ; case RPC_REG_UPDATE : CFG_DDR_SGMII_PHY -> PLL_CTRL_MAIN . PLL_CTRL_MAIN = LIBERO_SETTING_DDR_PLL_CTRL | 0x01U ; CFG_DDR_SGMII_PHY -> PLL_REF_FB_MAIN . PLL_REF_FB_MAIN = LIBERO_SETTING_DDR_PLL_REF_FB ; CFG_DDR_SGMII_PHY -> PLL_DIV_0_1_MAIN . PLL_DIV_0_1_MAIN = LIBERO_SETTING_DDR_PLL_DIV_0_1 ; CFG_DDR_SGMII_PHY -> PLL_DIV_2_3_MAIN . PLL_DIV_2_3_MAIN = LIBERO_SETTING_DDR_PLL_DIV_2_3 ; CFG_DDR_SGMII_PHY -> PLL_CTRL2_MAIN . PLL_CTRL2_MAIN = LIBERO_SETTING_DDR_PLL_CTRL2 ; CFG_DDR_SGMII_PHY -> PLL_PHADJ_MAIN . PLL_PHADJ_MAIN = LIBERO_SETTING_DDR_PLL_PHADJ ; CFG_DDR_SGMII_PHY -> SSCG_REG_2_MAIN . SSCG_REG_2_MAIN = LIBERO_SETTING_DDR_SSCG_REG_2 ; MSS_SCB_DDR_PLL -> SOFT_RESET = PLL_INIT_AND_OUT_OF_RESET ; break ; } }
@param option choose between SCB or RPC and soft reset  update method.
@param option choose between SCB or RPC and soft reset update method .
/* write to   SCB register */ /* PERIPH / periph_reset_b  - This asserts the functional reset of
             * the block. It is asserted at power up. When written is stays
             * asserted until written to 0.
             * First set periph_reset_b, than remove reset. As may be called
             * more than one.
             * */ /* PLL calibration register */ /*
             * PLL calibration register
             * This value is factory set, do not overwrite
             * MSS_SCB_DDR_PLL->PLL_CAL        = LIBERO_SETTING_MSS_PLL_CAL;
             *
             */ /* PLL phase registers */ /* bit 0 == REG_POWERDOWN_B */ /* CFG_DDR_SGMII_PHY->SOFT_RESET_MAIN_PLL; */ /* Read only in RPC
             * CFG_DDR_SGMII_PHY->PLL_FRACN_MAIN.PLL_FRACN_MAIN      =\
             *  LIBERO_SETTING_DDR_PLL_FRACN; */ /* Read only in RPC  todo: verify this is correct
             * CFG_DDR_SGMII_PHY->PLL_CAL_MAIN.PLL_CAL_MAIN  =\
             *                                   LIBERO_SETTING_DDR_PLL_CAL; */ /*__I  CFG_DDR_SGMII_PHY_SSCG_REG_0_MAIN_TypeDef SSCG_REG_0_MAIN; */ /*__I  CFG_DDR_SGMII_PHY_SSCG_REG_1_MAIN_TypeDef SSCG_REG_1_MAIN; */ /*__I  CFG_DDR_SGMII_PHY_SSCG_REG_3_MAIN_TypeDef SSCG_REG_3_MAIN; */ /*
             * set the NV map reset
             * This will load the APB registers, set via SGMII TIP.
             * */ /* bit 0 == REG_POWERDOWN_B */