FreeBSD/sys/dev/esp/ncr53c9x.c
/*
 * This is the generic ncr53c9x reset function.  It does not reset the SCSI
 * bus, only this controller, but kills any on-going commands, and also stops
 * and resets the DMA.
 *
 * After reset, registers are loaded with the defaults from the attach
 * routine above.
 */
This is the generic ncr53c9x reset function.  It does not reset the SCSI
bus, only this controller, but kills any on-going commands, and also stops
and resets the DMA.

After reset, registers are loaded with the defaults from the attach
routine above.
This is the generic ncr53c9x reset function . It does not reset the SCSI bus only this controller but kills any on - going commands and also stops and resets the DMA . After reset registers are loaded with the defaults from the attach routine above .
static void
ncr53c9x_reset(struct ncr53c9x_softc *sc)
{
	NCR_LOCK_ASSERT(sc, MA_OWNED);
	NCRDMA_RESET(sc);
	NCRCMD(sc, NCRCMD_RSTCHIP);
	NCRCMD(sc, NCRCMD_NOP);
	DELAY(500);
	switch (sc->sc_rev) {
	case NCR_VARIANT_ESP406:
	case NCR_VARIANT_FAS408:
		NCR_WRITE_REG(sc, NCR_CFG5, sc->sc_cfg5 | NCRCFG5_SINT);
		NCR_WRITE_REG(sc, NCR_CFG4, sc->sc_cfg4);
	case NCR_VARIANT_AM53C974:
	case NCR_VARIANT_FAS100A:
	case NCR_VARIANT_FAS216:
	case NCR_VARIANT_FAS236:
	case NCR_VARIANT_NCR53C94:
	case NCR_VARIANT_NCR53C96:
	case NCR_VARIANT_ESP200:
		sc->sc_features |= NCR_F_HASCFG3;
		NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
	case NCR_VARIANT_ESP100A:
		sc->sc_features |= NCR_F_SELATN3;
		if ((sc->sc_cfg2 & NCRCFG2_FE) != 0)
			sc->sc_features |= NCR_F_LARGEXFER;
		NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
	case NCR_VARIANT_ESP100:
		NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1);
		NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf);
		NCR_WRITE_REG(sc, NCR_SYNCOFF, 0);
		NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout);
		break;
	case NCR_VARIANT_FAS366:
		sc->sc_features |= NCR_F_HASCFG3 | NCR_F_FASTSCSI |
		    NCR_F_SELATN3 | NCR_F_LARGEXFER;
		sc->sc_cfg3 = NCRFASCFG3_FASTCLK | NCRFASCFG3_OBAUTO;
		if (sc->sc_id > 7)
			sc->sc_cfg3 |= NCRFASCFG3_IDBIT3;
		sc->sc_cfg3_fscsi = NCRFASCFG3_FASTSCSI;
		NCR_WRITE_REG(sc, NCR_CFG3, sc->sc_cfg3);
		sc->sc_cfg2 = NCRCFG2_HMEFE | NCRCFG2_HME32;
		NCR_WRITE_REG(sc, NCR_CFG2, sc->sc_cfg2);
		NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1);
		NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf);
		NCR_WRITE_REG(sc, NCR_SYNCOFF, 0);
		NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout);
		break;
	default:
		device_printf(sc->sc_dev,
		    "unknown revision code, assuming ESP100\n");
		NCR_WRITE_REG(sc, NCR_CFG1, sc->sc_cfg1);
		NCR_WRITE_REG(sc, NCR_CCF, sc->sc_ccf);
		NCR_WRITE_REG(sc, NCR_SYNCOFF, 0);
		NCR_WRITE_REG(sc, NCR_TIMEOUT, sc->sc_timeout);
	}
	if (sc->sc_rev == NCR_VARIANT_AM53C974)
		NCR_WRITE_REG(sc, NCR_AMDCFG4, sc->sc_cfg4);
#if 0
	device_printf(sc->sc_dev, "%s: revision %d\n", __func__, sc->sc_rev);
	device_printf(sc->sc_dev, "%s: cfg1 0x%x, cfg2 0x%x, cfg3 0x%x, ccf "
	    "0x%x, timeout 0x%x\n", __func__, sc->sc_cfg1, sc->sc_cfg2,
	    sc->sc_cfg3, sc->sc_ccf, sc->sc_timeout);
#endif
}
static void ncr53c9x_reset ( struct ncr53c9x_softc * sc ) { NCR_LOCK_ASSERT ( sc , MA_OWNED ) ; NCRDMA_RESET ( sc ) ; NCRCMD ( sc , NCRCMD_RSTCHIP ) ; NCRCMD ( sc , NCRCMD_NOP ) ; DELAY ( 500 ) ; switch ( sc -> sc_rev ) { case NCR_VARIANT_ESP406 : case NCR_VARIANT_FAS408 : NCR_WRITE_REG ( sc , NCR_CFG5 , sc -> sc_cfg5 | NCRCFG5_SINT ) ; NCR_WRITE_REG ( sc , NCR_CFG4 , sc -> sc_cfg4 ) ; case NCR_VARIANT_AM53C974 : case NCR_VARIANT_FAS100A : case NCR_VARIANT_FAS216 : case NCR_VARIANT_FAS236 : case NCR_VARIANT_NCR53C94 : case NCR_VARIANT_NCR53C96 : case NCR_VARIANT_ESP200 : sc -> sc_features |= NCR_F_HASCFG3 ; NCR_WRITE_REG ( sc , NCR_CFG3 , sc -> sc_cfg3 ) ; case NCR_VARIANT_ESP100A : sc -> sc_features |= NCR_F_SELATN3 ; if ( ( sc -> sc_cfg2 & NCRCFG2_FE ) != 0 ) sc -> sc_features |= NCR_F_LARGEXFER ; NCR_WRITE_REG ( sc , NCR_CFG2 , sc -> sc_cfg2 ) ; case NCR_VARIANT_ESP100 : NCR_WRITE_REG ( sc , NCR_CFG1 , sc -> sc_cfg1 ) ; NCR_WRITE_REG ( sc , NCR_CCF , sc -> sc_ccf ) ; NCR_WRITE_REG ( sc , NCR_SYNCOFF , 0 ) ; NCR_WRITE_REG ( sc , NCR_TIMEOUT , sc -> sc_timeout ) ; break ; case NCR_VARIANT_FAS366 : sc -> sc_features |= NCR_F_HASCFG3 | NCR_F_FASTSCSI | NCR_F_SELATN3 | NCR_F_LARGEXFER ; sc -> sc_cfg3 = NCRFASCFG3_FASTCLK | NCRFASCFG3_OBAUTO ; if ( sc -> sc_id > 7 ) sc -> sc_cfg3 |= NCRFASCFG3_IDBIT3 ; sc -> sc_cfg3_fscsi = NCRFASCFG3_FASTSCSI ; NCR_WRITE_REG ( sc , NCR_CFG3 , sc -> sc_cfg3 ) ; sc -> sc_cfg2 = NCRCFG2_HMEFE | NCRCFG2_HME32 ; NCR_WRITE_REG ( sc , NCR_CFG2 , sc -> sc_cfg2 ) ; NCR_WRITE_REG ( sc , NCR_CFG1 , sc -> sc_cfg1 ) ; NCR_WRITE_REG ( sc , NCR_CCF , sc -> sc_ccf ) ; NCR_WRITE_REG ( sc , NCR_SYNCOFF , 0 ) ; NCR_WRITE_REG ( sc , NCR_TIMEOUT , sc -> sc_timeout ) ; break ; default : device_printf ( sc -> sc_dev , " \n " ) ; NCR_WRITE_REG ( sc , NCR_CFG1 , sc -> sc_cfg1 ) ; NCR_WRITE_REG ( sc , NCR_CCF , sc -> sc_ccf ) ; NCR_WRITE_REG ( sc , NCR_SYNCOFF , 0 ) ; NCR_WRITE_REG ( sc , NCR_TIMEOUT , sc -> sc_timeout ) ; } if ( sc -> sc_rev == NCR_VARIANT_AM53C974 ) NCR_WRITE_REG ( sc , NCR_AMDCFG4 , sc -> sc_cfg4 ) ; #if 0 device_printf ( sc -> sc_dev , " \n " , __func__ , sc -> sc_rev ) ; device_printf ( sc -> sc_dev , " " " \n " , __func__ , sc -> sc_cfg1 , sc -> sc_cfg2 , sc -> sc_cfg3 , sc -> sc_ccf , sc -> sc_timeout ) ; #endif }
This is the generic ncr53c9x reset function.
This is the generic ncr53c9x reset function .
/* Reset DMA first. */ /* Reset SCSI chip. */ /* Do these backwards, and fall through. */ /* FALLTHROUGH */ /* FALLTHROUGH */ /* FALLTHROUGH */