qemu/fpu/softfloat-specialize.h
/*----------------------------------------------------------------------------
| Select which NaN to propagate for a three-input operation.
| For the moment we assume that no CPU needs the 'larger significand'
| information.
| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
*----------------------------------------------------------------------------*/
| Select which NaN to propagate for a three-input operation.
| For the moment we assume that no CPU needs the 'larger significand'
| information.
| Select which NaN to propagate for a three - input operation . | For the moment we assume that no CPU needs the ' larger significand ' | information .
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
                         bool infzero, float_status *status)
{
#if defined(TARGET_ARM)
    if (infzero && is_qnan(c_cls)) {
        float_raise(float_flag_invalid, status);
        return 3;
    }
    if (is_snan(c_cls)) {
        return 2;
    } else if (is_snan(a_cls)) {
        return 0;
    } else if (is_snan(b_cls)) {
        return 1;
    } else if (is_qnan(c_cls)) {
        return 2;
    } else if (is_qnan(a_cls)) {
        return 0;
    } else {
        return 1;
    }
#elif defined(TARGET_MIPS)
    if (infzero) {
        float_raise(float_flag_invalid, status);
        return 3;
    }
    if (snan_bit_is_one(status)) {
        if (is_snan(a_cls)) {
            return 0;
        } else if (is_snan(b_cls)) {
            return 1;
        } else if (is_snan(c_cls)) {
            return 2;
        } else if (is_qnan(a_cls)) {
            return 0;
        } else if (is_qnan(b_cls)) {
            return 1;
        } else {
            return 2;
        }
    } else {
        if (is_snan(c_cls)) {
            return 2;
        } else if (is_snan(a_cls)) {
            return 0;
        } else if (is_snan(b_cls)) {
            return 1;
        } else if (is_qnan(c_cls)) {
            return 2;
        } else if (is_qnan(a_cls)) {
            return 0;
        } else {
            return 1;
        }
    }
#elif defined(TARGET_PPC)
    if (infzero) {
        float_raise(float_flag_invalid, status);
        return 2;
    }
    if (is_nan(a_cls)) {
        return 0;
    } else if (is_nan(c_cls)) {
        return 2;
    } else {
        return 1;
    }
#else
    if (is_nan(a_cls)) {
        return 0;
    } else if (is_nan(b_cls)) {
        return 1;
    } else {
        return 2;
    }
#endif
}
static int pickNaNMulAdd ( FloatClass a_cls , FloatClass b_cls , FloatClass c_cls , bool infzero , float_status * status ) { #if defined ( TARGET_ARM ) if ( infzero && is_qnan ( c_cls ) ) { float_raise ( float_flag_invalid , status ) ; return 3 ; } if ( is_snan ( c_cls ) ) { return 2 ; } else if ( is_snan ( a_cls ) ) { return 0 ; } else if ( is_snan ( b_cls ) ) { return 1 ; } else if ( is_qnan ( c_cls ) ) { return 2 ; } else if ( is_qnan ( a_cls ) ) { return 0 ; } else { return 1 ; } #elif defined ( TARGET_MIPS ) if ( infzero ) { float_raise ( float_flag_invalid , status ) ; return 3 ; } if ( snan_bit_is_one ( status ) ) { if ( is_snan ( a_cls ) ) { return 0 ; } else if ( is_snan ( b_cls ) ) { return 1 ; } else if ( is_snan ( c_cls ) ) { return 2 ; } else if ( is_qnan ( a_cls ) ) { return 0 ; } else if ( is_qnan ( b_cls ) ) { return 1 ; } else { return 2 ; } } else { if ( is_snan ( c_cls ) ) { return 2 ; } else if ( is_snan ( a_cls ) ) { return 0 ; } else if ( is_snan ( b_cls ) ) { return 1 ; } else if ( is_qnan ( c_cls ) ) { return 2 ; } else if ( is_qnan ( a_cls ) ) { return 0 ; } else { return 1 ; } } #elif defined ( TARGET_PPC ) if ( infzero ) { float_raise ( float_flag_invalid , status ) ; return 2 ; } if ( is_nan ( a_cls ) ) { return 0 ; } else if ( is_nan ( c_cls ) ) { return 2 ; } else { return 1 ; } #else if ( is_nan ( a_cls ) ) { return 0 ; } else if ( is_nan ( b_cls ) ) { return 1 ; } else { return 2 ; } #endif }
| Select which NaN to propagate for a three-input operation.
| Select which NaN to propagate for a three - input operation .
/* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
     * the default NaN
     */ /* This looks different from the ARM ARM pseudocode, because the ARM ARM
     * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
     */ /* For MIPS, the (inf,zero,qnan) case sets InvalidOp and returns
     * the default NaN
     */ /* Prefer sNaN over qNaN, in the a, b, c order. */ /* Prefer sNaN over qNaN, in the c, a, b order. */ /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
     * to return an input NaN if we have one (ie c) rather than generating
     * a default NaN
     */ /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
     * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
     */ /* A default implementation: prefer a to b to c.
     * This is unlikely to actually match any real implementation.
     */