FreeBSD/lib/libc/sparc64/fpu/fpu.c
/*
 * Implement a move operation for all supported operand types. The additional
 * nand and xor parameters will be applied to the upper 32 bit word of the
 * source operand. This allows to implement fabs and fneg (for fp operands
 * only!) using this functions, too, by passing (1U << 31) for one of the
 * parameters, and 0 for the other.
 */
Implement a move operation for all supported operand types. The additional
nand and xor parameters will be applied to the upper 32 bit word of the
source operand. This allows to implement fabs and fneg (for fp operands
only!) using this functions, too, by passing (1U << 31) for one of the
parameters, and 0 for the other.
Implement a move operation for all supported operand types . The additional nand and xor parameters will be applied to the upper 32 bit word of the source operand . This allows to implement fabs and fneg ( for fp operands only! ) using this functions too by passing ( 1U << 31 ) for one of the parameters and 0 for the other .
static void
__fpu_mov(struct fpemu *fe, int type, int rd, int rs2, u_int32_t nand,
    u_int32_t xor)
{
	if (type == FTYPE_INT || type == FTYPE_SNG)
		__fpu_setreg(rd, (__fpu_getreg(rs2) & ~nand) ^ xor);
	else {
		__fpu_setreg64(rd, (__fpu_getreg64(rs2) &
		    ~((u_int64_t)nand << 32)) ^ ((u_int64_t)xor << 32));
		if (type == FTYPE_EXT)
			__fpu_setreg64(rd + 2, __fpu_getreg64(rs2 + 2));
	}
}
static void __fpu_mov ( struct fpemu * fe , int type , int rd , int rs2 , u_int32_t nand , u_int32_t xor ) { if ( type == FTYPE_INT || type == FTYPE_SNG ) __fpu_setreg ( rd , ( __fpu_getreg ( rs2 ) & ~ nand ) ^ xor ) ; else { __fpu_setreg64 ( rd , ( __fpu_getreg64 ( rs2 ) & ~ ( ( u_int64_t ) nand << 32 ) ) ^ ( ( u_int64_t ) xor << 32 ) ) ; if ( type == FTYPE_EXT ) __fpu_setreg64 ( rd + 2 , __fpu_getreg64 ( rs2 + 2 ) ) ; } }
Implement a move operation for all supported operand types.
Implement a move operation for all supported operand types .
/*
		 * Need to use the double versions to be able to access
		 * the upper 32 fp registers.
		 */