linux/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
/**
 * vmw_kms_check_display_memory - Validates display memory required for a
 * topology
 * @dev: DRM device
 * @num_rects: number of drm_rect in rects
 * @rects: array of drm_rect representing the topology to validate indexed by
 * crtc index.
 *
 * Returns:
 * 0 on success otherwise negative error code
 */
Validates display memory required for a
topology
@dev: DRM device
@num_rects: number of drm_rect in rects
@rects: array of drm_rect representing the topology to validate indexed by
crtc index.

0 on success otherwise negative error code
Validates display memory required for a topology @dev : DRM device @num_rects : number of drm_rect in rects @rects : array of drm_rect representing the topology to validate indexed by crtc index . 0 on success otherwise negative error code
static int vmw_kms_check_display_memory(struct drm_device *dev,
					uint32_t num_rects,
					struct drm_rect *rects)
{
	struct vmw_private *dev_priv = vmw_priv(dev);
	struct drm_rect bounding_box = {0};
	u64 total_pixels = 0, pixel_mem, bb_mem;
	int i;
	for (i = 0; i < num_rects; i++) {
		if (dev_priv->active_display_unit == vmw_du_screen_target &&
		    (drm_rect_width(&rects[i]) > dev_priv->stdu_max_width ||
		     drm_rect_height(&rects[i]) > dev_priv->stdu_max_height)) {
			DRM_ERROR("Screen size not supported.\n");
			return -EINVAL;
		}
		if (rects[i].x2 > bounding_box.x2)
			bounding_box.x2 = rects[i].x2;
		if (rects[i].y2 > bounding_box.y2)
			bounding_box.y2 = rects[i].y2;
		total_pixels += (u64) drm_rect_width(&rects[i]) *
			(u64) drm_rect_height(&rects[i]);
	}
	pixel_mem = total_pixels * 4;
	if (pixel_mem > dev_priv->prim_bb_mem) {
		DRM_ERROR("Combined output size too large.\n");
		return -EINVAL;
	}
	if (dev_priv->active_display_unit != vmw_du_screen_target ||
	    !(dev_priv->capabilities & SVGA_CAP_NO_BB_RESTRICTION)) {
		bb_mem = (u64) bounding_box.x2 * bounding_box.y2 * 4;
		if (bb_mem > dev_priv->prim_bb_mem) {
			DRM_ERROR("Topology is beyond supported limits.\n");
			return -EINVAL;
		}
	}
	return 0;
}
static int vmw_kms_check_display_memory ( struct drm_device * dev , uint32_t num_rects , struct drm_rect * rects ) { struct vmw_private * dev_priv = vmw_priv ( dev ) ; struct drm_rect bounding_box = { 0 } ; u64 total_pixels = 0 , pixel_mem , bb_mem ; int i ; for ( i = 0 ; i < num_rects ; i ++ ) { if ( dev_priv -> active_display_unit == vmw_du_screen_target && ( drm_rect_width ( & rects [ i ] ) > dev_priv -> stdu_max_width || drm_rect_height ( & rects [ i ] ) > dev_priv -> stdu_max_height ) ) { DRM_ERROR ( " \n " ) ; return - EINVAL ; } if ( rects [ i ] . x2 > bounding_box . x2 ) bounding_box . x2 = rects [ i ] . x2 ; if ( rects [ i ] . y2 > bounding_box . y2 ) bounding_box . y2 = rects [ i ] . y2 ; total_pixels += ( u64 ) drm_rect_width ( & rects [ i ] ) * ( u64 ) drm_rect_height ( & rects [ i ] ) ; } pixel_mem = total_pixels * 4 ; if ( pixel_mem > dev_priv -> prim_bb_mem ) { DRM_ERROR ( " \n " ) ; return - EINVAL ; } if ( dev_priv -> active_display_unit != vmw_du_screen_target || ! ( dev_priv -> capabilities & SVGA_CAP_NO_BB_RESTRICTION ) ) { bb_mem = ( u64 ) bounding_box . x2 * bounding_box . y2 * 4 ; if ( bb_mem > dev_priv -> prim_bb_mem ) { DRM_ERROR ( " \n " ) ; return - EINVAL ; } } return 0 ; }
vmw_kms_check_display_memory - Validates display memory required for a
 topology
 @dev: DRM device
 @num_rects: number of drm_rect in rects
 @rects: array of drm_rect representing the topology to validate indexed by
 crtc index.
vmw_kms_check_display_memory - Validates display memory required for a topology @dev : DRM device @num_rects : number of drm_rect in rects @rects : array of drm_rect representing the topology to validate indexed by crtc index .
/*
		 * For STDU only individual screen (screen target) is limited by
		 * SCREENTARGET_MAX_WIDTH/HEIGHT registers.
		 */ /* Bounding box upper left is at (0,0). */ /* Virtual svga device primary limits are always in 32-bpp. */ /*
	 * For HV10 and below prim_bb_mem is vram size. When
	 * SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM is not present vram size is
	 * limit on primary bounding box
	 */ /* SVGA_CAP_NO_BB_RESTRICTION is available for STDU only. */