FreeRTOS/Demo/Safer_Interrupts_M33F_NXP_LPC55S69_MCUXpresso/NXP_Code/drivers/fsl_inputmux.c
/*!
 * brief Enable/disable a signal
 *
 * This function gates the INPUTPMUX clock.
 *
 * param base Base address of the INPUTMUX peripheral.
 * param signal Enable signal register id and bit offset.
 * param enable Selects enable or disable.
 *
 * retval None.
 */
brief Enable/disable a signal

This function gates the INPUTPMUX clock.

param base Base address of the INPUTMUX peripheral.
param signal Enable signal register id and bit offset.
param enable Selects enable or disable.

retval None.
brief Enable / disable a signal This function gates the INPUTPMUX clock . param base Base address of the INPUTMUX peripheral . param signal Enable signal register id and bit offset . param enable Selects enable or disable . retval None .
void INPUTMUX_EnableSignal(INPUTMUX_Type *base, inputmux_signal_t signal, bool enable)
{
    uint32_t ena_id;
    uint32_t ena_id_mask = (1UL << (32U - ENA_SHIFT)) - 1U;
    uint32_t bit_offset;
#if defined(FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX) && FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX
    uint32_t chmux_offset;
    uint32_t chmux_value;
    if (enable && ((((uint32_t)signal) & (1UL << CHMUX_AVL_SHIFT)) != 0U))
    {
        chmux_offset = (((uint32_t)signal) >> CHMUX_OFF_SHIFT) & ((1UL << (CHMUX_AVL_SHIFT - CHMUX_OFF_SHIFT)) - 1UL);
        chmux_value  = (((uint32_t)signal) >> CHMUX_VAL_SHIFT) & ((1UL << (CHMUX_OFF_SHIFT - CHMUX_VAL_SHIFT)) - 1UL);
        *(volatile uint32_t *)(((uint32_t)base) + chmux_offset) = chmux_value;
    }
    ena_id_mask = (1UL << (CHMUX_VAL_SHIFT - ENA_SHIFT)) - 1U;
#endif
    ena_id = (((uint32_t)signal) >> ENA_SHIFT) & ena_id_mask;
    bit_offset = ((uint32_t)signal) & ((1UL << ENA_SHIFT) - 1U);
    if (enable)
    {
        *(volatile uint32_t *)(((uint32_t)base) + ena_id) |= (1UL << bit_offset);
    }
    else
    {
        *(volatile uint32_t *)(((uint32_t)base) + ena_id) &= ~(1UL << bit_offset);
    }
}
void INPUTMUX_EnableSignal ( INPUTMUX_Type * base , inputmux_signal_t signal , bool enable ) { uint32_t ena_id ; uint32_t ena_id_mask = ( 1UL << ( 32U - ENA_SHIFT ) ) - 1U ; uint32_t bit_offset ; #if defined ( FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX ) && FSL_FEATURE_INPUTMUX_HAS_CHANNEL_MUX uint32_t chmux_offset ; uint32_t chmux_value ; if ( enable && ( ( ( ( uint32_t ) signal ) & ( 1UL << CHMUX_AVL_SHIFT ) ) != 0U ) ) { chmux_offset = ( ( ( uint32_t ) signal ) >> CHMUX_OFF_SHIFT ) & ( ( 1UL << ( CHMUX_AVL_SHIFT - CHMUX_OFF_SHIFT ) ) - 1UL ) ; chmux_value = ( ( ( uint32_t ) signal ) >> CHMUX_VAL_SHIFT ) & ( ( 1UL << ( CHMUX_OFF_SHIFT - CHMUX_VAL_SHIFT ) ) - 1UL ) ; * ( volatile uint32_t * ) ( ( ( uint32_t ) base ) + chmux_offset ) = chmux_value ; } ena_id_mask = ( 1UL << ( CHMUX_VAL_SHIFT - ENA_SHIFT ) ) - 1U ; #endif ena_id = ( ( ( uint32_t ) signal ) >> ENA_SHIFT ) & ena_id_mask ; bit_offset = ( ( uint32_t ) signal ) & ( ( 1UL << ENA_SHIFT ) - 1U ) ; if ( enable ) { * ( volatile uint32_t * ) ( ( ( uint32_t ) base ) + ena_id ) |= ( 1UL << bit_offset ) ; } else { * ( volatile uint32_t * ) ( ( ( uint32_t ) base ) + ena_id ) &= ~ ( 1UL << bit_offset ) ; } }
brief Enable/disable a signal
brief Enable / disable a signal
/* Only enable need to update channel mux */ /* extract enable register to be used */ /* extract enable bit offset */ /* set signal */