components/esp_hw_support/port/esp32s3/spiram_psram.c
//Configure PSRAM SPI0 phase related registers here according to the PSRAM chip requirement
Configure PSRAM SPI0 phase related registers here according to the PSRAM chip requirement
Configure PSRAM SPI0 phase related registers here according to the PSRAM chip requirement
static void config_psram_spi_phases(void)
{
    CLEAR_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_DIO_M);       
    SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_SRAM_QIO_M);         
    SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_RCMD_M);  
    SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_CACHE_SRAM_USR_WCMD_M);  
    SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN, 7, SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S);
    SET_PERI_REG_BITS(SPI_MEM_SRAM_DWR_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE, PSRAM_QUAD_WRITE, SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S); 
    SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 7, SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S);
    SET_PERI_REG_BITS(SPI_MEM_SRAM_DRD_CMD_REG(0), SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V, PSRAM_FAST_READ_QUAD, SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S); 
    SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_ADDR_BITLEN_V, 23, SPI_MEM_SRAM_ADDR_BITLEN_S);
    SET_PERI_REG_MASK(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_USR_RD_SRAM_DUMMY_M);    
    SET_PERI_REG_BITS(SPI_MEM_CACHE_SCTRL_REG(0), SPI_MEM_SRAM_RDUMMY_CYCLELEN_V, (PSRAM_FAST_READ_QUAD_DUMMY - 1), SPI_MEM_SRAM_RDUMMY_CYCLELEN_S); 
    CLEAR_PERI_REG_MASK(SPI_MEM_MISC_REG(0), SPI_MEM_CS1_DIS_M); 
}
static void config_psram_spi_phases ( void ) { CLEAR_PERI_REG_MASK ( SPI_MEM_CACHE_SCTRL_REG ( 0 ) , SPI_MEM_USR_SRAM_DIO_M ) ; SET_PERI_REG_MASK ( SPI_MEM_CACHE_SCTRL_REG ( 0 ) , SPI_MEM_USR_SRAM_QIO_M ) ; SET_PERI_REG_MASK ( SPI_MEM_CACHE_SCTRL_REG ( 0 ) , SPI_MEM_CACHE_SRAM_USR_RCMD_M ) ; SET_PERI_REG_MASK ( SPI_MEM_CACHE_SCTRL_REG ( 0 ) , SPI_MEM_CACHE_SRAM_USR_WCMD_M ) ; SET_PERI_REG_BITS ( SPI_MEM_SRAM_DWR_CMD_REG ( 0 ) , SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN , 7 , SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S ) ; SET_PERI_REG_BITS ( SPI_MEM_SRAM_DWR_CMD_REG ( 0 ) , SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE , PSRAM_QUAD_WRITE , SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S ) ; SET_PERI_REG_BITS ( SPI_MEM_SRAM_DRD_CMD_REG ( 0 ) , SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V , 7 , SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S ) ; SET_PERI_REG_BITS ( SPI_MEM_SRAM_DRD_CMD_REG ( 0 ) , SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V , PSRAM_FAST_READ_QUAD , SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S ) ; SET_PERI_REG_BITS ( SPI_MEM_CACHE_SCTRL_REG ( 0 ) , SPI_MEM_SRAM_ADDR_BITLEN_V , 23 , SPI_MEM_SRAM_ADDR_BITLEN_S ) ; SET_PERI_REG_MASK ( SPI_MEM_CACHE_SCTRL_REG ( 0 ) , SPI_MEM_USR_RD_SRAM_DUMMY_M ) ; SET_PERI_REG_BITS ( SPI_MEM_CACHE_SCTRL_REG ( 0 ) , SPI_MEM_SRAM_RDUMMY_CYCLELEN_V , ( PSRAM_FAST_READ_QUAD_DUMMY - 1 ) , SPI_MEM_SRAM_RDUMMY_CYCLELEN_S ) ; CLEAR_PERI_REG_MASK ( SPI_MEM_MISC_REG ( 0 ) , SPI_MEM_CS1_DIS_M ) ; }
Configure PSRAM SPI0 phase related registers here according to the PSRAM chip requirement
Configure PSRAM SPI0 phase related registers here according to the PSRAM chip requirement
//Config CMD phase //disable dio mode for cache command //enable qio mode for cache command //enable cache read command //enable cache write command //0x38 //0xEB //Config ADDR phase //Dummy /**
     * We set the PSRAM chip required dummy here. If timing tuning is needed,
     * the dummy length will be updated in `spi_timing_enter_mspi_high_speed_mode()`
     */ //enable cache read dummy //dummy //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM)