Platform/ECM3532/DSP/hw/csp/ecm3532/src/eta_csp_spi.c
/***************************************************************************/
/**
 *
 *  EtaCspSpiProcessIntTxData - Process SPI Interrupt for TX Space Available
 *
 ******************************************************************************/
Process SPI Interrupt for TX Space Available
Process SPI Interrupt for TX Space Available
tEtaStatus
EtaCspSpiProcessIntTxData()
{
    uint8_t ui8SpaceInFifo;
    if((gsSpiCmd.bCmdActive == 0) ||
       (gsSpiCmd.ui16TxLen == 0))
    {
        return(eEtaSpiCmdSequenceErr);
    }
    if(ETA_CSP_SPI_EN_GREEDY_INT) 
    {
        ui8SpaceInFifo = 16 -
                         (REG_SPI2_TX_FIFO_DEBUG &
                          BM_SPI2_TX_FIFO_DEBUG_ENTRIES);
    }
    else
    {
        ui8SpaceInFifo = gsSpiCmd.ui8TxIntSize; 
    }
    do
    {
        REG_SPI2_TXRX_1BYTE_FIFO_DATA = *gsSpiCmd.pui8TxData++;
        gsSpiCmd.ui16TxLen--;
        if(gsSpiCmd.ui16TxLen == 0)
        {
            break; 
        }
    }
    while(--ui8SpaceInFifo);
    if(gsSpiCmd.ui16TxLen == 0) 
    {
        REG_SPI2_TX_DUMMY_BYTE_CNT = gsSpiCmd.ui16RxLen;
        if(gsSpiCmd.iSpiSequence & eSpiSequenceLastOnly)
        {
            REG_SPI2_STATUS = 0;
        }
        else
        {
            REG_SPI2_INT_EN = REG_SPI2_INT_EN | BM_SPI2_INT_EN_XMIT_COMPLETE_EN0;
        }
         Disable TX fifo has space interrupt.
         Reconfigure interrupt level to desired level for receiving.
        REG_SPI2_INT_EN =
            (REG_SPI2_INT_EN & ~BM_SPI2_INT_EN_TXFIFO_HAS_LEVEL_SPACE_EN0);
        REG_SPI2_CONFIG = (REG_SPI2_CONFIG & ~BM_SPI2_CONFIG_FIFO_LEVEL_TRIG) |
                          (gsSpiCmd.ui8RxIntSize <<
                           BP_SPI2_CONFIG_FIFO_LEVEL_TRIG);
    }
    return(eEtaSuccess);
}
tEtaStatus EtaCspSpiProcessIntTxData ( ) { uint8_t ui8SpaceInFifo ; if ( ( gsSpiCmd . bCmdActive == 0 ) || ( gsSpiCmd . ui16TxLen == 0 ) ) { return ( eEtaSpiCmdSequenceErr ) ; } if ( ETA_CSP_SPI_EN_GREEDY_INT ) { ui8SpaceInFifo = 16 - ( REG_SPI2_TX_FIFO_DEBUG & BM_SPI2_TX_FIFO_DEBUG_ENTRIES ) ; } else { ui8SpaceInFifo = gsSpiCmd . ui8TxIntSize ; } do { REG_SPI2_TXRX_1BYTE_FIFO_DATA = * gsSpiCmd . pui8TxData ++ ; gsSpiCmd . ui16TxLen -- ; if ( gsSpiCmd . ui16TxLen == 0 ) { break ; } } while ( -- ui8SpaceInFifo ) ; if ( gsSpiCmd . ui16TxLen == 0 ) { REG_SPI2_TX_DUMMY_BYTE_CNT = gsSpiCmd . ui16RxLen ; if ( gsSpiCmd . iSpiSequence & eSpiSequenceLastOnly ) { REG_SPI2_STATUS = 0 ; } else { REG_SPI2_INT_EN = REG_SPI2_INT_EN | BM_SPI2_INT_EN_XMIT_COMPLETE_EN0 ; } REG_SPI2_INT_EN = ( REG_SPI2_INT_EN & ~ BM_SPI2_INT_EN_TXFIFO_HAS_LEVEL_SPACE_EN0 ) ; REG_SPI2_CONFIG = ( REG_SPI2_CONFIG & ~ BM_SPI2_CONFIG_FIFO_LEVEL_TRIG ) | ( gsSpiCmd . ui8RxIntSize << BP_SPI2_CONFIG_FIFO_LEVEL_TRIG ) ; } return ( eEtaSuccess ) ; }
EtaCspSpiProcessIntTxData - Process SPI Interrupt for TX Space Available
EtaCspSpiProcessIntTxData - Process SPI Interrupt for TX Space Available
// This allows for burst writes, which is more // efficient, but not requires an extra read. // Do work that // interrupt said we // have space for // Exit loop, we're done. // Just sent last byte. Lets turn off // TX has space interrupt and send // dummy bytes // If it is Last, end command // At this point, all TX is in the queue. Remove hold // // Disable TX fifo has space interrupt. // Reconfigure interrupt level to desired level for receiving. //