plat/marvell/a8k/common/mss/mss_bl2_setup.c
/* Since the scp_bl2 image can contain firmware for cp1 and cp0 coprocessors,
 * the access to cp0 and cp1 need to be provided. More precisely it is
 * required to:
 *  - get the information about device id which is stored in CP0 registers
 *    (to distinguish between cases where we have cp0 and cp1 or standalone cp0)
 *  - get the access to cp which is needed for loading fw for cp0/cp1
 *    coprocessors
 * This function configures ccu windows accordingly.
 *
 * Note: there is no need to restore previous ccu configuration, since in next
 * phase (BL31) the init_ccu will be called (via apn806_init/
 * bl31_plat_arch_setu) and therefore the ccu configuration will be overwritten.
 */
Since the scp_bl2 image can contain firmware for cp1 and cp0 coprocessors,
the access to cp0 and cp1 need to be provided. More precisely it is
required to:
- get the information about device id which is stored in CP0 registers
(to distinguish between cases where we have cp0 and cp1 or standalone cp0)
- get the access to cp which is needed for loading fw for cp0/cp1
coprocessors
This function configures ccu windows accordingly.

there is no need to restore previous ccu configuration, since in next
phase (BL31) the init_ccu will be called (via apn806_init
bl31_plat_arch_setu) and therefore the ccu configuration will be overwritten.
Since the scp_bl2 image can contain firmware for cp1 and cp0 coprocessors the access to cp0 and cp1 need to be provided . More precisely it is required to : - get the information about device id which is stored in CP0 registers ( to distinguish between cases where we have cp0 and cp1 or standalone cp0 ) - get the access to cp which is needed for loading fw for cp0 / cp1 coprocessors This function configures ccu windows accordingly . there is no need to restore previous ccu configuration since in next phase ( BL31 ) the init_ccu will be called ( via apn806_init bl31_plat_arch_setu ) and therefore the ccu configuration will be overwritten .
static int bl2_plat_mmap_init(void)
{
	size_t win_nr, win_id;
	uintptr_t iow_base = MVEBU_IO_WIN_BASE;
	win_nr =  sizeof(mem_map) / sizeof(struct ccu_win);
	if (win_nr > marvell_get_ccu_max_win()) {
		ERROR("BL2: %s: trying to open too many windows\n", __func__);
		return -1;
	}
	for (win_id = 0; win_id < win_nr; win_id++) {
		ccu_win_check(&mem_map[win_id], win_id);
		ccu_enable_win(&mem_map[win_id], win_id);
	}
	mmio_write_32(iow_base + IOW_GCR_OFFSET, PIDI_TID);
	return 0;
}
static int bl2_plat_mmap_init ( void ) { size_t win_nr , win_id ; uintptr_t iow_base = MVEBU_IO_WIN_BASE ; win_nr = sizeof ( mem_map ) / sizeof ( struct ccu_win ) ; if ( win_nr > marvell_get_ccu_max_win ( ) ) { ERROR ( " \n " , __func__ ) ; return -1 ; } for ( win_id = 0 ; win_id < win_nr ; win_id ++ ) { ccu_win_check ( & mem_map [ win_id ] , win_id ) ; ccu_enable_win ( & mem_map [ win_id ] , win_id ) ; } mmio_write_32 ( iow_base + IOW_GCR_OFFSET , PIDI_TID ) ; return 0 ; }
Since the scp_bl2 image can contain firmware for cp1 and cp0 coprocessors,
 the access to cp0 and cp1 need to be provided.
Since the scp_bl2 image can contain firmware for cp1 and cp0 coprocessors the access to cp0 and cp1 need to be provided .
/* Enable required CCU windows */ /* Set the default target id to PIDI */