FreeBSD/sys/dev/cas/if_cas.c
/*
 * MII interface
 *
 * The MII interface supports at least three different operating modes:
 *
 * Bitbang mode is implemented using data, clock and output enable registers.
 *
 * Frame mode is implemented by loading a complete frame into the frame
 * register and polling the valid bit for completion.
 *
 * Polling mode uses the frame register but completion is indicated by
 * an interrupt.
 *
 */
MII interface
The MII interface supports at least three different operating modes.

Bitbang mode is implemented using data, clock and output enable registers.

Frame mode is implemented by loading a complete frame into the frame
register and polling the valid bit for completion.

Polling mode uses the frame register but completion is indicated by
an interrupt.
MII interface The MII interface supports at least three different operating modes . Bitbang mode is implemented using data clock and output enable registers . Frame mode is implemented by loading a complete frame into the frame register and polling the valid bit for completion . Polling mode uses the frame register but completion is indicated by an interrupt .
static int
cas_mii_readreg(device_t dev, int phy, int reg)
{
	struct cas_softc *sc;
	int n;
	uint32_t v;
#ifdef CAS_DEBUG_PHY
	printf("%s: phy %d reg %d\n", __func__, phy, reg);
#endif
	sc = device_get_softc(dev);
	if ((sc->sc_flags & CAS_SERDES) != 0) {
		switch (reg) {
		case MII_BMCR:
			reg = CAS_PCS_CTRL;
			break;
		case MII_BMSR:
			reg = CAS_PCS_STATUS;
			break;
		case MII_PHYIDR1:
		case MII_PHYIDR2:
			return (0);
		case MII_ANAR:
			reg = CAS_PCS_ANAR;
			break;
		case MII_ANLPAR:
			reg = CAS_PCS_ANLPAR;
			break;
		case MII_EXTSR:
			return (EXTSR_1000XFDX | EXTSR_1000XHDX);
		default:
			device_printf(sc->sc_dev,
			    "%s: unhandled register %d\n", __func__, reg);
			return (0);
		}
		return (CAS_READ_4(sc, reg));
	}
	v = CAS_MIF_FRAME_READ |
	    (phy << CAS_MIF_FRAME_PHY_SHFT) |
	    (reg << CAS_MIF_FRAME_REG_SHFT);
	CAS_WRITE_4(sc, CAS_MIF_FRAME, v);
	CAS_BARRIER(sc, CAS_MIF_FRAME, 4,
	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
	for (n = 0; n < 100; n++) {
		DELAY(1);
		v = CAS_READ_4(sc, CAS_MIF_FRAME);
		if (v & CAS_MIF_FRAME_TA_LSB)
			return (v & CAS_MIF_FRAME_DATA);
	}
	device_printf(sc->sc_dev, "%s: timed out\n", __func__);
	return (0);
}
static int cas_mii_readreg ( device_t dev , int phy , int reg ) { struct cas_softc * sc ; int n ; uint32_t v ; #ifdef CAS_DEBUG_PHY printf ( " \n " , __func__ , phy , reg ) ; #endif sc = device_get_softc ( dev ) ; if ( ( sc -> sc_flags & CAS_SERDES ) != 0 ) { switch ( reg ) { case MII_BMCR : reg = CAS_PCS_CTRL ; break ; case MII_BMSR : reg = CAS_PCS_STATUS ; break ; case MII_PHYIDR1 : case MII_PHYIDR2 : return ( 0 ) ; case MII_ANAR : reg = CAS_PCS_ANAR ; break ; case MII_ANLPAR : reg = CAS_PCS_ANLPAR ; break ; case MII_EXTSR : return ( EXTSR_1000XFDX | EXTSR_1000XHDX ) ; default : device_printf ( sc -> sc_dev , " \n " , __func__ , reg ) ; return ( 0 ) ; } return ( CAS_READ_4 ( sc , reg ) ) ; } v = CAS_MIF_FRAME_READ | ( phy << CAS_MIF_FRAME_PHY_SHFT ) | ( reg << CAS_MIF_FRAME_REG_SHFT ) ; CAS_WRITE_4 ( sc , CAS_MIF_FRAME , v ) ; CAS_BARRIER ( sc , CAS_MIF_FRAME , 4 , BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE ) ; for ( n = 0 ; n < 100 ; n ++ ) { DELAY ( 1 ) ; v = CAS_READ_4 ( sc , CAS_MIF_FRAME ) ; if ( v & CAS_MIF_FRAME_TA_LSB ) return ( v & CAS_MIF_FRAME_DATA ) ; } device_printf ( sc -> sc_dev , " \n " , __func__ ) ; return ( 0 ) ; }
MII interface
 The MII interface supports at least three different operating modes:
MII interface The MII interface supports at least three different operating modes :
/* Construct the frame command. */