drivers/pwm/pwm_k64_ftm.c
/**
 * @brief Initial FTM configuration
 *
 * Initialize the FTM hardware based on configuration options.
 *
 * @param dev Device struct
 * @param access_op Access operation (pin or port)
 * @param channel The pwm channel number
 * @param flags Device flags (unused)
 *
 * @return 0 if successful, failed otherwise
 */
@brief Initial FTM configuration
Initialize the FTM hardware based on configuration options.

@param dev Device struct
@param access_op Access operation (pin or port)
@param channel The pwm channel number
@param flags Device flags (unused)

@return 0 if successful, failed otherwise
@brief Initial FTM configuration Initialize the FTM hardware based on configuration options . @param dev Device struct @param access_op Access operation ( pin or port ) @param channel The pwm channel number @param flags Device flags ( unused ) @return 0 if successful failed otherwise
static int pwm_ftm_configure(struct device *dev, int access_op,
			     u32_t channel, int flags)
{
	int return_val = 0;
	u32_t clock_source;
	u32_t prescale;
	u32_t polarity;
	u32_t reg_val;
	SYS_LOG_DBG("...");
	const struct pwm_ftm_config * const config =
		dev->config->config_info;
	ARG_UNUSED(access_op);
	ARG_UNUSED(flags);
	pwm_ftm_clk_enable(config->ftm_num);
	clock_source = (config->clock_source & 0x3) << PWM_K64_FTM_SC_CLKS_SHIFT;
	if (clock_source == 0) {
		SYS_LOG_DBG("Warning: no clock source. PWM is disabled");
	}
	switch (config->prescale) {
	case PWM_K64_FTM_PRESCALE_1:
		prescale = PWM_K64_FTM_SC_PS_D1;
		break;
	case PWM_K64_FTM_PRESCALE_2:
		prescale = PWM_K64_FTM_SC_PS_D2;
		break;
	case PWM_K64_FTM_PRESCALE_4:
		prescale = PWM_K64_FTM_SC_PS_D4;
		break;
	case PWM_K64_FTM_PRESCALE_8:
		prescale = PWM_K64_FTM_SC_PS_D8;
		break;
	case PWM_K64_FTM_PRESCALE_16:
		prescale = PWM_K64_FTM_SC_PS_D16;
		break;
	case PWM_K64_FTM_PRESCALE_32:
		prescale = PWM_K64_FTM_SC_PS_D32;
		break;
	case PWM_K64_FTM_PRESCALE_64:
		prescale = PWM_K64_FTM_SC_PS_D64;
		break;
	case PWM_K64_FTM_PRESCALE_128:
		prescale = PWM_K64_FTM_SC_PS_D128;
		break;
	default:
		prescale = PWM_K64_FTM_SC_PS_D1;
		return_val = -ENOTSUP;
		break;
	}
#ifdef COMBINE_MODE_SUPPORT
	mode_reg_val = sys_read32(PWM_K64_FTM_MODE(config->reg_base));
	mode_reg_val |= PWM_K64_FTM_MODE_FTMEN | PWM_K64_FTM_MODE_INIT;
	SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
	    mode_reg_val, PWM_K64_FTM_MODE(config->reg_base));
	sys_write32(mode_reg_val, PWM_K64_FTM_MODE(config->reg_base));
	SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
		PWM_K64_FTM_SYNCONF_SYNCMODE|PWM_K64_FTM_SYNCONF_CNTINC,
		PWM_K64_FTM_SYNCONF(config->reg_base));
	sys_write32(PWM_K64_FTM_SYNCONF_SYNCMODE|PWM_K64_FTM_SYNCONF_CNTINC,
				PWM_K64_FTM_SYNCONF(config->reg_base));
#endif 
	reg_val = prescale | clock_source;
	SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
	    reg_val, PWM_K64_FTM_SC(config->reg_base));
	sys_write32(reg_val, PWM_K64_FTM_SC(config->reg_base));
	SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
	    config->period, PWM_K64_FTM_MOD(config->reg_base));
	sys_write32(config->period, PWM_K64_FTM_MOD(config->reg_base));
	reg_val = PWM_K64_FTM_CNSC_MSB | PWM_K64_FTM_CNSC_ELSB;
	SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
	    reg_val, PWM_K64_FTM_CNSC(config->reg_base, channel));
	sys_write32(reg_val, PWM_K64_FTM_CNSC(config->reg_base, channel));
	SYS_LOG_DBG("sys_read32 4..");
	polarity = sys_read32(PWM_K64_FTM_POL(config->reg_base));
	polarity &= ~(1<<channel);
	SYS_LOG_DBG("sys_write32(0x%08x, 0x%08x)..",
	    polarity, PWM_K64_FTM_POL(config->reg_base));
	sys_write32(polarity, PWM_K64_FTM_POL(config->reg_base));
	return return_val;
}
static int pwm_ftm_configure ( struct device * dev , int access_op , u32_t channel , int flags ) { int return_val = 0 ; u32_t clock_source ; u32_t prescale ; u32_t polarity ; u32_t reg_val ; SYS_LOG_DBG ( " " ) ; const struct pwm_ftm_config * const config = dev -> config -> config_info ; ARG_UNUSED ( access_op ) ; ARG_UNUSED ( flags ) ; pwm_ftm_clk_enable ( config -> ftm_num ) ; clock_source = ( config -> clock_source & 0x3 ) << PWM_K64_FTM_SC_CLKS_SHIFT ; if ( clock_source == 0 ) { SYS_LOG_DBG ( " " ) ; } switch ( config -> prescale ) { case PWM_K64_FTM_PRESCALE_1 : prescale = PWM_K64_FTM_SC_PS_D1 ; break ; case PWM_K64_FTM_PRESCALE_2 : prescale = PWM_K64_FTM_SC_PS_D2 ; break ; case PWM_K64_FTM_PRESCALE_4 : prescale = PWM_K64_FTM_SC_PS_D4 ; break ; case PWM_K64_FTM_PRESCALE_8 : prescale = PWM_K64_FTM_SC_PS_D8 ; break ; case PWM_K64_FTM_PRESCALE_16 : prescale = PWM_K64_FTM_SC_PS_D16 ; break ; case PWM_K64_FTM_PRESCALE_32 : prescale = PWM_K64_FTM_SC_PS_D32 ; break ; case PWM_K64_FTM_PRESCALE_64 : prescale = PWM_K64_FTM_SC_PS_D64 ; break ; case PWM_K64_FTM_PRESCALE_128 : prescale = PWM_K64_FTM_SC_PS_D128 ; break ; default : prescale = PWM_K64_FTM_SC_PS_D1 ; return_val = - ENOTSUP ; break ; } #ifdef COMBINE_MODE_SUPPORT mode_reg_val = sys_read32 ( PWM_K64_FTM_MODE ( config -> reg_base ) ) ; mode_reg_val |= PWM_K64_FTM_MODE_FTMEN | PWM_K64_FTM_MODE_INIT ; SYS_LOG_DBG ( " " , mode_reg_val , PWM_K64_FTM_MODE ( config -> reg_base ) ) ; sys_write32 ( mode_reg_val , PWM_K64_FTM_MODE ( config -> reg_base ) ) ; SYS_LOG_DBG ( " " , PWM_K64_FTM_SYNCONF_SYNCMODE | PWM_K64_FTM_SYNCONF_CNTINC , PWM_K64_FTM_SYNCONF ( config -> reg_base ) ) ; sys_write32 ( PWM_K64_FTM_SYNCONF_SYNCMODE | PWM_K64_FTM_SYNCONF_CNTINC , PWM_K64_FTM_SYNCONF ( config -> reg_base ) ) ; #endif reg_val = prescale | clock_source ; SYS_LOG_DBG ( " " , reg_val , PWM_K64_FTM_SC ( config -> reg_base ) ) ; sys_write32 ( reg_val , PWM_K64_FTM_SC ( config -> reg_base ) ) ; SYS_LOG_DBG ( " " , config -> period , PWM_K64_FTM_MOD ( config -> reg_base ) ) ; sys_write32 ( config -> period , PWM_K64_FTM_MOD ( config -> reg_base ) ) ; reg_val = PWM_K64_FTM_CNSC_MSB | PWM_K64_FTM_CNSC_ELSB ; SYS_LOG_DBG ( " " , reg_val , PWM_K64_FTM_CNSC ( config -> reg_base , channel ) ) ; sys_write32 ( reg_val , PWM_K64_FTM_CNSC ( config -> reg_base , channel ) ) ; SYS_LOG_DBG ( " " ) ; polarity = sys_read32 ( PWM_K64_FTM_POL ( config -> reg_base ) ) ; polarity &= ~ ( 1 << channel ) ; SYS_LOG_DBG ( " " , polarity , PWM_K64_FTM_POL ( config -> reg_base ) ) ; sys_write32 ( polarity , PWM_K64_FTM_POL ( config -> reg_base ) ) ; return return_val ; }
@brief Initial FTM configuration
 Initialize the FTM hardware based on configuration options.
@brief Initial FTM configuration Initialize the FTM hardware based on configuration options .
/* enable the clock for the FTM subsystem */ /*
	 * Initialize:
	 *  clock source = x (system, fixed, external) from config
	 *  prescaler divide-by x=(1,2,4,8,16,32,64,128) from config
	 *  free-running count-up
	 *  edge-aligned PWM mode
	 *  pair: independent outputs
	 *  polarity +
	 *  no interrupt
	 */ /*
	 * PS[2:0] = prescale
	 * MOD = pulse width
	 */ /* Illegal prescale value. Default to 1. */ /* Enable FTMEN=1 and set outputs to initial value */ /* Enable enhanced synchronization */ /*COMBINE_MODE_SUPPORT*/ /* Configure: PS | CLKS | up-counter | disable TOF intr */ /* set MOD to max */ /* set channel control to edge-aligned */ /* set polarity high for this channel */