libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/stm32f10x_tim.c
/**
  * @brief  Initializes the TIMx Channel1 according to the specified
  *         parameters in the TIM_OCInitStruct.
  * @param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
  *         that contains the configuration information for the specified TIM peripheral.
  * @retval None
  */
@brief  Initializes the TIMx Channel1 according to the specified
parameters in the TIM_OCInitStruct.
@param  TIMx: where x can be  1 to 17 except 6 and 7 to select the TIM peripheral.
@param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
that contains the configuration information for the specified TIM peripheral.
@retval None
@brief Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct . @param TIMx : where x can be 1 to 17 except 6 and 7 to select the TIM peripheral . @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure that contains the configuration information for the specified TIM peripheral . @retval None
void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
{
  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
  assert_param(IS_TIM_LIST8_PERIPH(TIMx));
  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
  TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
  tmpccer = TIMx->CCER;
  tmpcr2 =  TIMx->CR2;
  tmpccmrx = TIMx->CCMR1;
  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
  tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
  tmpccer |= TIM_OCInitStruct->TIM_OutputState;
  if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)||
     (TIMx == TIM16)|| (TIMx == TIM17))
  {
    assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
    assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
    assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));
    tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE));    
    tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));
    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));
    tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
    tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
  }
  TIMx->CR2 = tmpcr2;
  TIMx->CCMR1 = tmpccmrx;
  TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; 
  TIMx->CCER = tmpccer;
}
void TIM_OC1Init ( TIM_TypeDef * TIMx , TIM_OCInitTypeDef * TIM_OCInitStruct ) { uint16_t tmpccmrx = 0 , tmpccer = 0 , tmpcr2 = 0 ; assert_param ( IS_TIM_LIST8_PERIPH ( TIMx ) ) ; assert_param ( IS_TIM_OC_MODE ( TIM_OCInitStruct -> TIM_OCMode ) ) ; assert_param ( IS_TIM_OUTPUT_STATE ( TIM_OCInitStruct -> TIM_OutputState ) ) ; assert_param ( IS_TIM_OC_POLARITY ( TIM_OCInitStruct -> TIM_OCPolarity ) ) ; TIMx -> CCER &= ( uint16_t ) ( ~ ( uint16_t ) TIM_CCER_CC1E ) ; tmpccer = TIMx -> CCER ; tmpcr2 = TIMx -> CR2 ; tmpccmrx = TIMx -> CCMR1 ; tmpccmrx &= ( uint16_t ) ( ~ ( ( uint16_t ) TIM_CCMR1_OC1M ) ) ; tmpccmrx &= ( uint16_t ) ( ~ ( ( uint16_t ) TIM_CCMR1_CC1S ) ) ; tmpccmrx |= TIM_OCInitStruct -> TIM_OCMode ; tmpccer &= ( uint16_t ) ( ~ ( ( uint16_t ) TIM_CCER_CC1P ) ) ; tmpccer |= TIM_OCInitStruct -> TIM_OCPolarity ; tmpccer |= TIM_OCInitStruct -> TIM_OutputState ; if ( ( TIMx == TIM1 ) || ( TIMx == TIM8 ) || ( TIMx == TIM15 ) || ( TIMx == TIM16 ) || ( TIMx == TIM17 ) ) { assert_param ( IS_TIM_OUTPUTN_STATE ( TIM_OCInitStruct -> TIM_OutputNState ) ) ; assert_param ( IS_TIM_OCN_POLARITY ( TIM_OCInitStruct -> TIM_OCNPolarity ) ) ; assert_param ( IS_TIM_OCNIDLE_STATE ( TIM_OCInitStruct -> TIM_OCNIdleState ) ) ; assert_param ( IS_TIM_OCIDLE_STATE ( TIM_OCInitStruct -> TIM_OCIdleState ) ) ; tmpccer &= ( uint16_t ) ( ~ ( ( uint16_t ) TIM_CCER_CC1NP ) ) ; tmpccer |= TIM_OCInitStruct -> TIM_OCNPolarity ; tmpccer &= ( uint16_t ) ( ~ ( ( uint16_t ) TIM_CCER_CC1NE ) ) ; tmpccer |= TIM_OCInitStruct -> TIM_OutputNState ; tmpcr2 &= ( uint16_t ) ( ~ ( ( uint16_t ) TIM_CR2_OIS1 ) ) ; tmpcr2 &= ( uint16_t ) ( ~ ( ( uint16_t ) TIM_CR2_OIS1N ) ) ; tmpcr2 |= TIM_OCInitStruct -> TIM_OCIdleState ; tmpcr2 |= TIM_OCInitStruct -> TIM_OCNIdleState ; } TIMx -> CR2 = tmpcr2 ; TIMx -> CCMR1 = tmpccmrx ; TIMx -> CCR1 = TIM_OCInitStruct -> TIM_Pulse ; TIMx -> CCER = tmpccer ; }
@brief  Initializes the TIMx Channel1 according to the specified
         parameters in the TIM_OCInitStruct.
@brief Initializes the TIMx Channel1 according to the specified parameters in the TIM_OCInitStruct .
/* Check the parameters */ /* Disable the Channel 1: Reset the CC1E Bit */ /* Get the TIMx CCER register value */ /* Get the TIMx CR2 register value */ /* Get the TIMx CCMR1 register value */ /* Reset the Output Compare Mode Bits */ /* Select the Output Compare Mode */ /* Reset the Output Polarity level */ /* Set the Output Compare Polarity */ /* Set the Output State */ /* Reset the Output N Polarity level */ /* Set the Output N Polarity */ /* Reset the Output N State */ /* Set the Output N State */ /* Reset the Output Compare and Output Compare N IDLE State */ /* Set the Output Idle state */ /* Set the Output N Idle state */ /* Write to TIMx CR2 */ /* Write to TIMx CCMR1 */ /* Set the Capture Compare Register value */ /* Write to TIMx CCER */