FreeBSD/sys/dev/cxgb/cxgb_sge.c
/**
 *	t3_sge_init - initialize SGE
 *	@adap: the adapter
 *	@p: the SGE parameters
 *
 *	Performs SGE initialization needed every time after a chip reset.
 *	We do not initialize any of the queue sets here, instead the driver
 *	top-level must request those individually.  We also do not enable DMA
 *	here, that should be done after the queues have been set up.
 */
initialize SGE
@adap: the adapter
@p: the SGE parameters

Performs SGE initialization needed every time after a chip reset.
We do not initialize any of the queue sets here, instead the driver
top-level must request those individually.  We also do not enable DMA
here, that should be done after the queues have been set up.
initialize SGE @adap : the adapter @p : the SGE parameters Performs SGE initialization needed every time after a chip reset . We do not initialize any of the queue sets here instead the driver top - level must request those individually . We also do not enable DMA here that should be done after the queues have been set up .
void
t3_sge_init(adapter_t *adap, struct sge_params *p)
{
	u_int ctrl, ups;
	ups = 0; 
	ctrl = F_DROPPKT | V_PKTSHIFT(2) | F_FLMODE | F_AVOIDCQOVFL |
	       F_CQCRDTCTRL | F_CONGMODE | F_TNLFLMODE | F_FATLPERREN |
	       V_HOSTPAGESIZE(PAGE_SHIFT - 11) | F_BIGENDIANINGRESS |
	       V_USERSPACESIZE(ups ? ups - 1 : 0) | F_ISCSICOALESCING;
#if SGE_NUM_GENBITS == 1
	ctrl |= F_EGRGENCTRL;
#endif
	if (adap->params.rev > 0) {
		if (!(adap->flags & (USING_MSIX | USING_MSI)))
			ctrl |= F_ONEINTMULTQ | F_OPTONEINTMULTQ;
	}
	t3_write_reg(adap, A_SG_CONTROL, ctrl);
	t3_write_reg(adap, A_SG_EGR_RCQ_DRB_THRSH, V_HIRCQDRBTHRSH(512) |
		     V_LORCQDRBTHRSH(512));
	t3_write_reg(adap, A_SG_TIMER_TICK, core_ticks_per_usec(adap) / 10);
	t3_write_reg(adap, A_SG_CMDQ_CREDIT_TH, V_THRESHOLD(32) |
		     V_TIMEOUT(200 * core_ticks_per_usec(adap)));
	t3_write_reg(adap, A_SG_HI_DRB_HI_THRSH,
		     adap->params.rev < T3_REV_C ? 1000 : 500);
	t3_write_reg(adap, A_SG_HI_DRB_LO_THRSH, 256);
	t3_write_reg(adap, A_SG_LO_DRB_HI_THRSH, 1000);
	t3_write_reg(adap, A_SG_LO_DRB_LO_THRSH, 256);
	t3_write_reg(adap, A_SG_OCO_BASE, V_BASE1(0xfff));
	t3_write_reg(adap, A_SG_DRB_PRI_THRESH, 63 * 1024);
}
void t3_sge_init ( adapter_t * adap , struct sge_params * p ) { u_int ctrl , ups ; ups = 0 ; ctrl = F_DROPPKT | V_PKTSHIFT ( 2 ) | F_FLMODE | F_AVOIDCQOVFL | F_CQCRDTCTRL | F_CONGMODE | F_TNLFLMODE | F_FATLPERREN | V_HOSTPAGESIZE ( PAGE_SHIFT - 11 ) | F_BIGENDIANINGRESS | V_USERSPACESIZE ( ups ? ups - 1 : 0 ) | F_ISCSICOALESCING ; #if SGE_NUM_GENBITS == 1 ctrl |= F_EGRGENCTRL ; #endif if ( adap -> params . rev > 0 ) { if ( ! ( adap -> flags & ( USING_MSIX | USING_MSI ) ) ) ctrl |= F_ONEINTMULTQ | F_OPTONEINTMULTQ ; } t3_write_reg ( adap , A_SG_CONTROL , ctrl ) ; t3_write_reg ( adap , A_SG_EGR_RCQ_DRB_THRSH , V_HIRCQDRBTHRSH ( 512 ) | V_LORCQDRBTHRSH ( 512 ) ) ; t3_write_reg ( adap , A_SG_TIMER_TICK , core_ticks_per_usec ( adap ) / 10 ) ; t3_write_reg ( adap , A_SG_CMDQ_CREDIT_TH , V_THRESHOLD ( 32 ) | V_TIMEOUT ( 200 * core_ticks_per_usec ( adap ) ) ) ; t3_write_reg ( adap , A_SG_HI_DRB_HI_THRSH , adap -> params . rev < T3_REV_C ? 1000 : 500 ) ; t3_write_reg ( adap , A_SG_HI_DRB_LO_THRSH , 256 ) ; t3_write_reg ( adap , A_SG_LO_DRB_HI_THRSH , 1000 ) ; t3_write_reg ( adap , A_SG_LO_DRB_LO_THRSH , 256 ) ; t3_write_reg ( adap , A_SG_OCO_BASE , V_BASE1 ( 0xfff ) ) ; t3_write_reg ( adap , A_SG_DRB_PRI_THRESH , 63 * 1024 ) ; }
t3_sge_init - initialize SGE
      @adap: the adapter
      @p: the SGE parameters
t3_sge_init - initialize SGE @adap : the adapter @p : the SGE parameters
/* = ffs(pci_resource_len(adap->pdev, 2) >> 12); */