src/occ_405/gpu/gpu.c
// Schedule a GPE request for GPU operation
Schedule a GPE request for GPU operation
Schedule a GPE request for GPU operation
bool schedule_gpu_req(const gpu_op_req_e i_operation, gpu_sm_args_t i_new_args)
{
    bool l_scheduled = false;
    bool scheduleRequest = true;
    errlHndl_t err = NULL;
    GPU_DBG(">>schedule_gpu_req(op 0x%02X)", i_operation);
    if (!async_request_is_idle(&G_gpu_op_request.request))
    {
        INTR_TRAC_INFO("E>schedule_gpu_req: prior request (op 0x%02X) not idle when scheduling 0x%02X (tick=%d)",
                       G_gpu_op_req_args.operation, i_operation, GPU_TICK);
    }
    else
    {
        G_gpu_op_req_args = i_new_args;
        switch(i_operation)
        {
            case GPU_REQ_INIT:
                break;
            case GPU_REQ_READ_CAPS_START:
            case GPU_REQ_READ_CAPS_2:
            case GPU_REQ_READ_CAPS_3:
            case GPU_REQ_READ_CAPS_FINISH:
                break;
            case GPU_REQ_READ_TEMP_START:
            case GPU_REQ_READ_TEMP_FINISH:
                break;
            case GPU_REQ_READ_MEM_TEMP_START:
            case GPU_REQ_READ_MEM_TEMP_2:
            case GPU_REQ_READ_MEM_TEMP_3:
            case GPU_REQ_READ_MEM_TEMP_FINISH:
                break;
            case GPU_REQ_CHECK_DRIVER_START:
            case GPU_REQ_CHECK_DRIVER_2:
            case GPU_REQ_CHECK_DRIVER_3:
            case GPU_REQ_CHECK_DRIVER_FINISH:
                break;
            case GPU_REQ_GET_PWR_LIMIT_1_START:
            case GPU_REQ_GET_PWR_LIMIT_1_2:
            case GPU_REQ_GET_PWR_LIMIT_1_3:
            case GPU_REQ_GET_PWR_LIMIT_1_FINISH:
            case GPU_REQ_GET_PWR_LIMIT_2_START:
            case GPU_REQ_GET_PWR_LIMIT_2_2:
            case GPU_REQ_GET_PWR_LIMIT_2_FINISH:
            case GPU_REQ_GET_PWR_LIMIT_3_START:
            case GPU_REQ_GET_PWR_LIMIT_3_2:
            case GPU_REQ_GET_PWR_LIMIT_3_3:
            case GPU_REQ_GET_PWR_LIMIT_3_FINISH:
            case GPU_REQ_GET_PWR_LIMIT_4_START:
            case GPU_REQ_GET_PWR_LIMIT_4_2:
            case GPU_REQ_GET_PWR_LIMIT_4_3:
            case GPU_REQ_GET_PWR_LIMIT_4_FINISH:
            case GPU_REQ_GET_PWR_LIMIT_5_START:
            case GPU_REQ_GET_PWR_LIMIT_5_2:
            case GPU_REQ_GET_PWR_LIMIT_5_3:
            case GPU_REQ_GET_PWR_LIMIT_5_FINISH:
                break;
            case GPU_REQ_SET_PWR_LIMIT_1_START:
            case GPU_REQ_SET_PWR_LIMIT_1_2:
            case GPU_REQ_SET_PWR_LIMIT_1_3:
            case GPU_REQ_SET_PWR_LIMIT_1_FINISH:
            case GPU_REQ_SET_PWR_LIMIT_2_START:
            case GPU_REQ_SET_PWR_LIMIT_2_2:
            case GPU_REQ_SET_PWR_LIMIT_2_3:
            case GPU_REQ_SET_PWR_LIMIT_2_FINISH:
            case GPU_REQ_SET_PWR_LIMIT_3_START:
            case GPU_REQ_SET_PWR_LIMIT_3_2:
            case GPU_REQ_SET_PWR_LIMIT_3_3:
            case GPU_REQ_SET_PWR_LIMIT_3_FINISH:
            case GPU_REQ_SET_PWR_LIMIT_4_START:
            case GPU_REQ_SET_PWR_LIMIT_4_2:
            case GPU_REQ_SET_PWR_LIMIT_4_FINISH:
                break;
            case GPU_REQ_RESET:
                break;
            default:
                INTR_TRAC_ERR("schedule_gpu_req: Invalid GPU request operation: 0x%02X", i_operation);
                err = createErrl(GPU_MID_GPU_SCHED_REQ,
                                 GPU_FAILURE,
                                 ERC_GPU_INVALID_GPU_OPERATION,
                                 ERRL_SEV_PREDICTIVE,
                                 NULL,
                                 DEFAULT_TRACE_SIZE,
                                 i_operation,
                                 0);
                commitErrl(&err);
                scheduleRequest = false;
                occ_i2c_lock_release(GPU_I2C_ENGINE);
                G_gpu_monitoring_allowed = FALSE;
                break;
        }
        if (scheduleRequest)
        {
            G_gpu_op_req_args.error.error = 0;
            G_gpu_op_req_args.gpu_rc = 0;
            G_gpu_op_req_args.operation = i_operation;
            G_gpu_op_req_args.gpu_id = G_current_gpu_id;
            GPU_DBG("schedule_gpu_req: Scheduling GPE1 GPU operation 0x%02X (tick %d)", i_operation, GPU_TICK);
            int l_rc = gpe_request_schedule(&G_gpu_op_request);
            if (0 == l_rc)
            {
                l_scheduled = true;
            }
            else
            {
                INTR_TRAC_ERR("schedule_gpu_req: schedule failed w/rc=0x%08X (%d us)",
                              l_rc, (int) ((ssx_timebase_get())/(SSX_TIMEBASE_FREQUENCY_HZ/1000000)));
                err = createErrl(GPU_MID_GPU_SCHED_REQ,
                                 SSX_GENERIC_FAILURE,
                                 ERC_GPU_SCHEDULE_FAILURE,
                                 ERRL_SEV_PREDICTIVE,
                                 NULL,
                                 DEFAULT_TRACE_SIZE,
                                 l_rc,
                                 i_operation);
                commitErrl(&err);
                occ_i2c_lock_release(GPU_I2C_ENGINE);
                G_gpu_monitoring_allowed = FALSE;
            }
        }
    }
    return l_scheduled;
}
bool schedule_gpu_req ( const gpu_op_req_e i_operation , gpu_sm_args_t i_new_args ) { bool l_scheduled = false ; bool scheduleRequest = true ; errlHndl_t err = NULL ; GPU_DBG ( " " , i_operation ) ; if ( ! async_request_is_idle ( & G_gpu_op_request . request ) ) { INTR_TRAC_INFO ( " " , G_gpu_op_req_args . operation , i_operation , GPU_TICK ) ; } else { G_gpu_op_req_args = i_new_args ; switch ( i_operation ) { case GPU_REQ_INIT : break ; case GPU_REQ_READ_CAPS_START : case GPU_REQ_READ_CAPS_2 : case GPU_REQ_READ_CAPS_3 : case GPU_REQ_READ_CAPS_FINISH : break ; case GPU_REQ_READ_TEMP_START : case GPU_REQ_READ_TEMP_FINISH : break ; case GPU_REQ_READ_MEM_TEMP_START : case GPU_REQ_READ_MEM_TEMP_2 : case GPU_REQ_READ_MEM_TEMP_3 : case GPU_REQ_READ_MEM_TEMP_FINISH : break ; case GPU_REQ_CHECK_DRIVER_START : case GPU_REQ_CHECK_DRIVER_2 : case GPU_REQ_CHECK_DRIVER_3 : case GPU_REQ_CHECK_DRIVER_FINISH : break ; case GPU_REQ_GET_PWR_LIMIT_1_START : case GPU_REQ_GET_PWR_LIMIT_1_2 : case GPU_REQ_GET_PWR_LIMIT_1_3 : case GPU_REQ_GET_PWR_LIMIT_1_FINISH : case GPU_REQ_GET_PWR_LIMIT_2_START : case GPU_REQ_GET_PWR_LIMIT_2_2 : case GPU_REQ_GET_PWR_LIMIT_2_FINISH : case GPU_REQ_GET_PWR_LIMIT_3_START : case GPU_REQ_GET_PWR_LIMIT_3_2 : case GPU_REQ_GET_PWR_LIMIT_3_3 : case GPU_REQ_GET_PWR_LIMIT_3_FINISH : case GPU_REQ_GET_PWR_LIMIT_4_START : case GPU_REQ_GET_PWR_LIMIT_4_2 : case GPU_REQ_GET_PWR_LIMIT_4_3 : case GPU_REQ_GET_PWR_LIMIT_4_FINISH : case GPU_REQ_GET_PWR_LIMIT_5_START : case GPU_REQ_GET_PWR_LIMIT_5_2 : case GPU_REQ_GET_PWR_LIMIT_5_3 : case GPU_REQ_GET_PWR_LIMIT_5_FINISH : break ; case GPU_REQ_SET_PWR_LIMIT_1_START : case GPU_REQ_SET_PWR_LIMIT_1_2 : case GPU_REQ_SET_PWR_LIMIT_1_3 : case GPU_REQ_SET_PWR_LIMIT_1_FINISH : case GPU_REQ_SET_PWR_LIMIT_2_START : case GPU_REQ_SET_PWR_LIMIT_2_2 : case GPU_REQ_SET_PWR_LIMIT_2_3 : case GPU_REQ_SET_PWR_LIMIT_2_FINISH : case GPU_REQ_SET_PWR_LIMIT_3_START : case GPU_REQ_SET_PWR_LIMIT_3_2 : case GPU_REQ_SET_PWR_LIMIT_3_3 : case GPU_REQ_SET_PWR_LIMIT_3_FINISH : case GPU_REQ_SET_PWR_LIMIT_4_START : case GPU_REQ_SET_PWR_LIMIT_4_2 : case GPU_REQ_SET_PWR_LIMIT_4_FINISH : break ; case GPU_REQ_RESET : break ; default : INTR_TRAC_ERR ( " " , i_operation ) ; err = createErrl ( GPU_MID_GPU_SCHED_REQ , GPU_FAILURE , ERC_GPU_INVALID_GPU_OPERATION , ERRL_SEV_PREDICTIVE , NULL , DEFAULT_TRACE_SIZE , i_operation , 0 ) ; commitErrl ( & err ) ; scheduleRequest = false ; occ_i2c_lock_release ( GPU_I2C_ENGINE ) ; G_gpu_monitoring_allowed = FALSE ; break ; } if ( scheduleRequest ) { G_gpu_op_req_args . error . error = 0 ; G_gpu_op_req_args . gpu_rc = 0 ; G_gpu_op_req_args . operation = i_operation ; G_gpu_op_req_args . gpu_id = G_current_gpu_id ; GPU_DBG ( " " , i_operation , GPU_TICK ) ; int l_rc = gpe_request_schedule ( & G_gpu_op_request ) ; if ( 0 == l_rc ) { l_scheduled = true ; } else { INTR_TRAC_ERR ( " " , l_rc , ( int ) ( ( ssx_timebase_get ( ) ) / ( SSX_TIMEBASE_FREQUENCY_HZ / 1000000 ) ) ) ; err = createErrl ( GPU_MID_GPU_SCHED_REQ , SSX_GENERIC_FAILURE , ERC_GPU_SCHEDULE_FAILURE , ERRL_SEV_PREDICTIVE , NULL , DEFAULT_TRACE_SIZE , l_rc , i_operation ) ; commitErrl ( & err ) ; occ_i2c_lock_release ( GPU_I2C_ENGINE ) ; G_gpu_monitoring_allowed = FALSE ; } } } return l_scheduled ; }
Schedule a GPE request for GPU operation
Schedule a GPE request for GPU operation
// Ready for next request // Init // Read GPU memory temp capability // Read GPU core temp // Read GPU memory temp // Check if driver is loaded // Read GPU Power Limit // Set GPU Power Limit // I2C reset /*
                 * @errortype
                 * @moduleid    GPU_MID_GPU_SCHED_REQ
                 * @reasoncode  GPU_FAILURE
                 * @userdata1   operation
                 * @userdata2   0
                 * @userdata4   ERC_GPU_INVALID_GPU_OPERATION
                 * @devdesc     Invalid GPU request operation
                 */ // release I2C lock to the host for this engine and stop monitoring // Clear errors and init common arguments for GPE /*
                 * @errortype
                 * @moduleid    GPU_MID_GPU_SCHED_REQ
                 * @reasoncode  SSX_GENERIC_FAILURE
                 * @userdata1   GPE schedule returned code
                 * @userdata2   GPU operation
                 * @userdata4   ERC_GPU_SCHEDULE_FAILURE
                 * @devdesc     Failed to schedule GPU operation request
                 */ // release I2C lock to the host for this engine and stop monitoring