core/minute-ia/interrupts.c
/*
 * Get LAPIC ISR, TMR, or IRR vector bit.
 *
 * LAPIC ISR, TMR, and IRR bit vector registers are laid out in a way that
 * skips 3 32bit word after one 32 bit entry:
 *
 *  ADDR         |  32 vectors   |    +0x4    |   +0x8    |   +0xC
 * --------------+---------------+------------+-----------+------------
 *  BASE         |  0 ~ 31       |    skip 96 bits
 * --------------+---------------+------------+-----------+------------
 *  BASE + 0x10  |  32 ~ 64      |    skip 96 bits
 * --------------+---------------+------------+-----------+------------
 *  BASE + 0x20  |  64 ~ 96      |    skip 96 bits
 * --------------+---------------+------------+-----------+------------
 *  ...
 *
 * From Kernel LAPIC driver:
 * #define VEC_POS(v) ((v) & (32 - 1))
 * #define REG_POS(v) (((v) >> 5) << 4)
 */
Get LAPIC ISR, TMR, or IRR vector bit.
LAPIC ISR, TMR, and IRR bit vector registers are laid out in a way that
skips 3 32bit word after one 32 bit entry.




Get LAPIC ISR TMR or IRR vector bit . LAPIC ISR TMR and IRR bit vector registers are laid out in a way that skips 3 32bit word after one 32 bit entry .
static inline unsigned int lapic_get_vector(uint32_t reg_base, uint32_t vector)
{
	uint32_t reg_pos = (vector >> 5) << 4;
	uint32_t vec_pos = vector & (32 - 1);
	return REG32(reg_base + reg_pos) & (1 << vec_pos);
}
static inline unsigned int lapic_get_vector ( uint32_t reg_base , uint32_t vector ) { uint32_t reg_pos = ( vector >> 5 ) << 4 ; uint32_t vec_pos = vector & ( 32 - 1 ) ; return REG32 ( reg_base + reg_pos ) & ( 1 << vec_pos ) ; }
Get LAPIC ISR, TMR, or IRR vector bit.
Get LAPIC ISR TMR or IRR vector bit .