src/occ_405/gpu/gpu.c
// Function Specification
//
// Name:  gpu_reset_sm
//
// Description: GPU Reset State Machine.  This is not called per GPU if any handling is needed
//               per GPU this function must handle and not indicate that reset is complete
//               until all present GPUs are ready
//
// End Function Specification
Function Specification
Name:  gpu_reset_sm

GPU Reset State Machine.  This is not called per GPU if any handling is needed
per GPU this function must handle and not indicate that reset is complete
until all present GPUs are ready

End Function Specification
Function Specification Name : gpu_reset_sm GPU Reset State Machine . This is not called per GPU if any handling is needed per GPU this function must handle and not indicate that reset is complete until all present GPUs are ready End Function Specification
bool gpu_reset_sm()
{
    bool l_complete = FALSE;   
    static bool L_scheduled = FALSE;  
    static uint8_t L_state_retry_count = 0;
    static uint8_t L_consec_reset_failure_count = 0;
    static gpuResetState_e L_reset_state = GPU_RESET_STATE_NEW;  
    if (async_request_is_idle(&G_gpu_op_request.request))
    {
        if( (L_reset_state != GPU_RESET_STATE_NEW) &&
            (L_reset_state != GPU_RESET_STATE_RESET_SLAVE_WAIT) &&
            (!L_scheduled || (GPE_RC_SUCCESS != G_gpu_op_req_args.error.rc)) )
        {
            if(G_gpu_op_req_args.error.rc == GPE_RC_NO_GPU_SUPPORT)
            {
                INTR_TRAC_ERR("gpu_reset_sm: GPE image doesn't support GPUs!");
                errlHndl_t err = createErrl(GPU_MID_GPU_RESET_SM,
                                         GPU_NO_GPE_SUPPORT,
                                         ERC_GPU_NO_GPE_SUPPORT,
                                         ERRL_SEV_UNRECOVERABLE,
                                         NULL,
                                         DEFAULT_TRACE_SIZE,
                                         0,
                                         0);
                commitErrl(&err);
                disable_all_gpus();
                L_reset_state = GPU_RESET_STATE_NEW;
                return FALSE;  
            }
            else
            {
                if(L_state_retry_count < MAX_GPU_RESET_STATE_RETRY)
                {
                    L_state_retry_count++;
                }
                else  
                {
                    if(L_consec_reset_failure_count > MAX_CONSECUTIVE_GPU_RESETS)
                    {
                        INTR_TRAC_ERR("gpu_reset_sm: Max Resets reached! state[0x%02X] rc[0x%08X] addr[0x%08X] ffdc[0x%08X%08X]",
                                      L_reset_state, G_gpu_op_req_args.error.rc, G_gpu_op_req_args.error.addr,
                                      (uint32_t) (G_gpu_op_req_args.error.ffdc >> 32), (uint32_t) G_gpu_op_req_args.error.ffdc);
                        errlHndl_t err = createErrl(GPU_MID_GPU_RESET_SM,
                                               GPU_FAILURE,
                                               ERC_GPU_RESET_FAILURE,
                                               ERRL_SEV_UNRECOVERABLE,
                                               NULL,
                                               DEFAULT_TRACE_SIZE,
                                               L_reset_state,
                                               G_gpu_op_req_args.error.rc);
                        commitErrl(&err);
                        disable_all_gpus();
                        L_reset_state = GPU_RESET_STATE_NEW;
                        return FALSE;  
                    }
                    else  
                    {
                        L_consec_reset_failure_count++;
                        L_state_retry_count = 0;
                        L_reset_state = GPU_RESET_STATE_INIT_BUS;
                    }
                }  
            }  
        }
        else 
        {
            L_state_retry_count = 0;
            L_reset_state++;
        }
        L_scheduled = FALSE;  
        switch (L_reset_state)
        {
            case GPU_RESET_STATE_INIT_BUS:
                L_scheduled = schedule_gpu_req(GPU_REQ_INIT, G_new_gpu_req_args);
                break;
            case GPU_RESET_STATE_RESET_MASTER:
                G_new_gpu_req_args.data[0] = GPU_RESET_REQ_MASTER;
                L_scheduled = schedule_gpu_req(GPU_REQ_RESET, G_new_gpu_req_args);
                break;
            case GPU_RESET_STATE_RESET_SLAVE:
                G_new_gpu_req_args.data[0] = GPU_RESET_REQ_SLV;
                L_scheduled = schedule_gpu_req(GPU_REQ_RESET, G_new_gpu_req_args);
                break;
            case GPU_RESET_STATE_RESET_SLAVE_WAIT:
                GPU_DBG("gpu_reset_sm: waiting during slave port 4 reset");
                break;
            case GPU_RESET_STATE_RESET_SLAVE_COMPLETE:
                G_new_gpu_req_args.data[0] = GPU_RESET_REQ_SLV_COMPLETE;
                L_scheduled = schedule_gpu_req(GPU_REQ_RESET, G_new_gpu_req_args);
                break;
            case GPU_RESET_STATE_RESET_FINISH:
                l_complete = TRUE;
                L_consec_reset_failure_count = 0;
                L_reset_state = GPU_RESET_STATE_NEW;
                break;
           default:
               INTR_TRAC_ERR("gpu_reset_sm: INVALID STATE: 0x%02X when reset is required", L_reset_state);
               L_reset_state = GPU_RESET_STATE_NEW;
               break;
       } 
        if(L_scheduled)
        {
            GPU_DBG("gpu_reset_sm: Scheduled reset state 0x%02X", L_reset_state);
        }
        else if( (L_reset_state != GPU_RESET_STATE_NEW) &&
                 (L_reset_state != GPU_RESET_STATE_RESET_SLAVE_WAIT) )
        {
            INTR_TRAC_ERR("gpu_reset_sm: failed to schedule state 0x%02X", L_reset_state);
        }
    } 
    else
    {
        INTR_TRAC_ERR("gpu_reset_sm: NOT idle for state 0x%02X", L_reset_state);
    }
    return l_complete;
}
bool gpu_reset_sm ( ) { bool l_complete = FALSE ; static bool L_scheduled = FALSE ; static uint8_t L_state_retry_count = 0 ; static uint8_t L_consec_reset_failure_count = 0 ; static gpuResetState_e L_reset_state = GPU_RESET_STATE_NEW ; if ( async_request_is_idle ( & G_gpu_op_request . request ) ) { if ( ( L_reset_state != GPU_RESET_STATE_NEW ) && ( L_reset_state != GPU_RESET_STATE_RESET_SLAVE_WAIT ) && ( ! L_scheduled || ( GPE_RC_SUCCESS != G_gpu_op_req_args . error . rc ) ) ) { if ( G_gpu_op_req_args . error . rc == GPE_RC_NO_GPU_SUPPORT ) { INTR_TRAC_ERR ( " " ) ; errlHndl_t err = createErrl ( GPU_MID_GPU_RESET_SM , GPU_NO_GPE_SUPPORT , ERC_GPU_NO_GPE_SUPPORT , ERRL_SEV_UNRECOVERABLE , NULL , DEFAULT_TRACE_SIZE , 0 , 0 ) ; commitErrl ( & err ) ; disable_all_gpus ( ) ; L_reset_state = GPU_RESET_STATE_NEW ; return FALSE ; } else { if ( L_state_retry_count < MAX_GPU_RESET_STATE_RETRY ) { L_state_retry_count ++ ; } else { if ( L_consec_reset_failure_count > MAX_CONSECUTIVE_GPU_RESETS ) { INTR_TRAC_ERR ( " " , L_reset_state , G_gpu_op_req_args . error . rc , G_gpu_op_req_args . error . addr , ( uint32_t ) ( G_gpu_op_req_args . error . ffdc >> 32 ) , ( uint32_t ) G_gpu_op_req_args . error . ffdc ) ; errlHndl_t err = createErrl ( GPU_MID_GPU_RESET_SM , GPU_FAILURE , ERC_GPU_RESET_FAILURE , ERRL_SEV_UNRECOVERABLE , NULL , DEFAULT_TRACE_SIZE , L_reset_state , G_gpu_op_req_args . error . rc ) ; commitErrl ( & err ) ; disable_all_gpus ( ) ; L_reset_state = GPU_RESET_STATE_NEW ; return FALSE ; } else { L_consec_reset_failure_count ++ ; L_state_retry_count = 0 ; L_reset_state = GPU_RESET_STATE_INIT_BUS ; } } } } else { L_state_retry_count = 0 ; L_reset_state ++ ; } L_scheduled = FALSE ; switch ( L_reset_state ) { case GPU_RESET_STATE_INIT_BUS : L_scheduled = schedule_gpu_req ( GPU_REQ_INIT , G_new_gpu_req_args ) ; break ; case GPU_RESET_STATE_RESET_MASTER : G_new_gpu_req_args . data [ 0 ] = GPU_RESET_REQ_MASTER ; L_scheduled = schedule_gpu_req ( GPU_REQ_RESET , G_new_gpu_req_args ) ; break ; case GPU_RESET_STATE_RESET_SLAVE : G_new_gpu_req_args . data [ 0 ] = GPU_RESET_REQ_SLV ; L_scheduled = schedule_gpu_req ( GPU_REQ_RESET , G_new_gpu_req_args ) ; break ; case GPU_RESET_STATE_RESET_SLAVE_WAIT : GPU_DBG ( " " ) ; break ; case GPU_RESET_STATE_RESET_SLAVE_COMPLETE : G_new_gpu_req_args . data [ 0 ] = GPU_RESET_REQ_SLV_COMPLETE ; L_scheduled = schedule_gpu_req ( GPU_REQ_RESET , G_new_gpu_req_args ) ; break ; case GPU_RESET_STATE_RESET_FINISH : l_complete = TRUE ; L_consec_reset_failure_count = 0 ; L_reset_state = GPU_RESET_STATE_NEW ; break ; default : INTR_TRAC_ERR ( " " , L_reset_state ) ; L_reset_state = GPU_RESET_STATE_NEW ; break ; } if ( L_scheduled ) { GPU_DBG ( " " , L_reset_state ) ; } else if ( ( L_reset_state != GPU_RESET_STATE_NEW ) && ( L_reset_state != GPU_RESET_STATE_RESET_SLAVE_WAIT ) ) { INTR_TRAC_ERR ( " " , L_reset_state ) ; } } else { INTR_TRAC_ERR ( " " , L_reset_state ) ; } return l_complete ; }
Function Specification
Name:  gpu_reset_sm
Function Specification Name : gpu_reset_sm
// only return TRUE when the reset AND initialization is complete // indicates if a GPU GPE request was scheduled // 1st state for a reset // check if the previous state was successfully scheduled and success/done // Check if failure was due to GPE image not having GPU support // No GPU Support, log error and disable all GPUs /*
                 * @errortype
                 * @moduleid    GPU_MID_GPU_RESET_SM
                 * @reasoncode  GPU_NO_GPE_SUPPORT
                 * @userdata1   0
                 * @userdata2   0
                 * @userdata4   ERC_GPU_NO_GPE_SUPPORT
                 * @devdesc     GPE1 image doesn't support GPU communication
                 */ // GPUs are not ready for communication // Stay in current state if haven't reached state retry count // INC state retry count and retry current state // this reset attempt failed // Stop trying if reached max resets /*
                         * @errortype
                         * @moduleid    GPU_MID_GPU_RESET_SM
                         * @reasoncode  GPU_FAILURE
                         * @userdata1   GPU reset state
                         * @userdata2   GPE failure RC
                         * @userdata4   ERC_GPU_RESET_FAILURE
                         * @devdesc     Failure resetting GPU interface
                         */ // GPUs are not ready for communication // try the reset again from the beginning // else reset attempt failed // else GPE supports GPU // if previous state failed // success on last state go to next state and process it // default nothing scheduled // Setup I2C Interrupt Mask Register // Delay to allow reset to complete // Reset and init is complete ready to start sending commands to the GPUs // next time this is called will be to start a new reset // switch L_reset_state // check if the state was expected to have a schedule. Only new and slave wait // don't schedule for all other states the schedule must have failed // if async_request_is_idle