dz80/dissz80.c
/* ED00 - ED3F are currently only Z180 instructions */
ED3F are currently only Z180 instructions
ED3F are currently only Z180 instructions
int DisED00to3F(DISZ80 *d)
{
	int 	r, bb;
	if (d->cpuType < DCPU_Z180)
		return FALSE;
	bb = d->op & 7;
	r = (d->op >> 3) & 7;
	switch (bb)
		{
		case 0: 	
			AddToDisTab(d, "in0");
			AddToDis(d, Reg8Idx[r]);
			AddToDis(d, ",(");
			AddToDis8BitAbs(d, FALSE);
			AddToDis(d, ")");
			AddToDisCommentZ180(d);
			return TRUE;
		case 1: 	
			AddToDisTab(d, "out0");
			AddToDis(d, "(");
			AddToDis8BitAbs(d, FALSE);
			AddToDis(d, "),");
			AddToDis(d, Reg8Idx[r]);
			AddToDisCommentZ180(d);
			return TRUE;
		case 4: 	
			AddToDisTab(d, "tst");
			AddToDis(d, Reg8Idx[r]);
			AddToDisCommentZ180(d);
			return TRUE;
		}
	return FALSE;
}
int DisED00to3F ( DISZ80 * d ) { int r , bb ; if ( d -> cpuType < DCPU_Z180 ) return FALSE ; bb = d -> op & 7 ; r = ( d -> op >> 3 ) & 7 ; switch ( bb ) { case 0 : AddToDisTab ( d , " " ) ; AddToDis ( d , Reg8Idx [ r ] ) ; AddToDis ( d , " " ) ; AddToDis8BitAbs ( d , FALSE ) ; AddToDis ( d , " " ) ; AddToDisCommentZ180 ( d ) ; return TRUE ; case 1 : AddToDisTab ( d , " " ) ; AddToDis ( d , " " ) ; AddToDis8BitAbs ( d , FALSE ) ; AddToDis ( d , " " ) ; AddToDis ( d , Reg8Idx [ r ] ) ; AddToDisCommentZ180 ( d ) ; return TRUE ; case 4 : AddToDisTab ( d , " " ) ; AddToDis ( d , Reg8Idx [ r ] ) ; AddToDisCommentZ180 ( d ) ; return TRUE ; } return FALSE ; }
ED00 - ED3F are currently only Z180 instructions
ED00 - ED3F are currently only Z180 instructions
/* ED 0x00 - 0x38 */ /* ED 0x01 - 0x39 */ /* ED 0x04 - 0x3c */