FreeBSD/sys/mips/cavium/octeon_machdep.c
/*
 * octeon_ciu_reset
 *
 * Shutdown all CIU to IP2, IP3 mappings
 */
octeon_ciu_reset
Shutdown all CIU to IP2, IP3 mappings
octeon_ciu_reset Shutdown all CIU to IP2 IP3 mappings
void
octeon_ciu_reset(void)
{
	uint64_t cvmctl;
	cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), 0);
	cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 0);
	cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), 0);
	cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2+1), 0);
#ifdef SMP
	cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1),
		       (1ull << (OCTEON_IRQ_MBOX0 - 8)) |
		       (1ull << (OCTEON_IRQ_MBOX1 - 8)));
#endif
	cvmctl = mips_rd_cvmctl();
	cvmctl &= ~(7 << 7);
	cvmctl |= (OCTEON_PMC_IRQ + 2) << 7;
	mips_wr_cvmctl(cvmctl);
}
void octeon_ciu_reset ( void ) { uint64_t cvmctl ; cvmx_write_csr ( CVMX_CIU_INTX_EN0 ( cvmx_get_core_num ( ) * 2 ) , 0 ) ; cvmx_write_csr ( CVMX_CIU_INTX_EN0 ( cvmx_get_core_num ( ) * 2 + 1 ) , 0 ) ; cvmx_write_csr ( CVMX_CIU_INTX_EN1 ( cvmx_get_core_num ( ) * 2 ) , 0 ) ; cvmx_write_csr ( CVMX_CIU_INTX_EN1 ( cvmx_get_core_num ( ) * 2 + 1 ) , 0 ) ; #ifdef SMP cvmx_write_csr ( CVMX_CIU_INTX_EN0 ( cvmx_get_core_num ( ) * 2 + 1 ) , ( 1ull << ( OCTEON_IRQ_MBOX0 - 8 ) ) | ( 1ull << ( OCTEON_IRQ_MBOX1 - 8 ) ) ) ; #endif cvmctl = mips_rd_cvmctl ( ) ; cvmctl &= ~ ( 7 << 7 ) ; cvmctl |= ( OCTEON_PMC_IRQ + 2 ) << 7 ; mips_wr_cvmctl ( cvmctl ) ; }
octeon_ciu_reset
 Shutdown all CIU to IP2, IP3 mappings
octeon_ciu_reset Shutdown all CIU to IP2 IP3 mappings
/* Disable all CIU interrupts by default */ /* Enable the MBOX interrupts.  */ /* 
	 * Move the Performance Counter interrupt to OCTEON_PMC_IRQ
	 */