qemu/target/hppa/translate.c
/* The parisc documentation describes only the general interpretation of
   the conditions, without describing their exact implementation.  The
   interpretations do not stand up well when considering ADD,C and SUB,B.
   However, considering the Addition, Subtraction and Logical conditions
   as a whole it would appear that these relations are similar to what
   a traditional NZCV set of flags would produce.  */
The parisc documentation describes only the general interpretation of
the conditions, without describing their exact implementation.  The
interpretations do not stand up well when considering ADD,C and SUB,B.
However, considering the Addition, Subtraction and Logical conditions
as a whole it would appear that these relations are similar to what
a traditional NZCV set of flags would produce.
The parisc documentation describes only the general interpretation of the conditions without describing their exact implementation . The interpretations do not stand up well when considering ADD C and SUB B . However considering the Addition Subtraction and Logical conditions as a whole it would appear that these relations are similar to what a traditional NZCV set of flags would produce .
static DisasCond do_cond(unsigned cf, TCGv_reg res,
                         TCGv_reg cb_msb, TCGv_reg sv)
{
    DisasCond cond;
    TCGv_reg tmp;
    switch (cf >> 1) {
    case 0: 
        cond = cond_make_f();
        break;
    case 1: 
        cond = cond_make_0(TCG_COND_EQ, res);
        break;
    case 2: 
        cond = cond_make_0(TCG_COND_LT, res);
        break;
    case 3: 
        cond = cond_make_0(TCG_COND_LE, res);
        break;
    case 4: 
        cond = cond_make_0(TCG_COND_EQ, cb_msb);
        break;
    case 5: 
        tmp = tcg_temp_new();
        tcg_gen_neg_reg(tmp, cb_msb);
        tcg_gen_and_reg(tmp, tmp, res);
        cond = cond_make_0(TCG_COND_EQ, tmp);
        tcg_temp_free(tmp);
        break;
    case 6: 
        cond = cond_make_0(TCG_COND_LT, sv);
        break;
    case 7: 
        tmp = tcg_temp_new();
        tcg_gen_andi_reg(tmp, res, 1);
        cond = cond_make_0(TCG_COND_NE, tmp);
        tcg_temp_free(tmp);
        break;
    default:
        g_assert_not_reached();
    }
    if (cf & 1) {
        cond.c = tcg_invert_cond(cond.c);
    }
    return cond;
}
static DisasCond do_cond ( unsigned cf , TCGv_reg res , TCGv_reg cb_msb , TCGv_reg sv ) { DisasCond cond ; TCGv_reg tmp ; switch ( cf >> 1 ) { case 0 : cond = cond_make_f ( ) ; break ; case 1 : cond = cond_make_0 ( TCG_COND_EQ , res ) ; break ; case 2 : cond = cond_make_0 ( TCG_COND_LT , res ) ; break ; case 3 : cond = cond_make_0 ( TCG_COND_LE , res ) ; break ; case 4 : cond = cond_make_0 ( TCG_COND_EQ , cb_msb ) ; break ; case 5 : tmp = tcg_temp_new ( ) ; tcg_gen_neg_reg ( tmp , cb_msb ) ; tcg_gen_and_reg ( tmp , tmp , res ) ; cond = cond_make_0 ( TCG_COND_EQ , tmp ) ; tcg_temp_free ( tmp ) ; break ; case 6 : cond = cond_make_0 ( TCG_COND_LT , sv ) ; break ; case 7 : tmp = tcg_temp_new ( ) ; tcg_gen_andi_reg ( tmp , res , 1 ) ; cond = cond_make_0 ( TCG_COND_NE , tmp ) ; tcg_temp_free ( tmp ) ; break ; default : g_assert_not_reached ( ) ; } if ( cf & 1 ) { cond . c = tcg_invert_cond ( cond . c ) ; } return cond ; }
The parisc documentation describes only the general interpretation of
the conditions, without describing their exact implementation.
The parisc documentation describes only the general interpretation of the conditions without describing their exact implementation .
/* Never / TR */ /* = / <>        (Z / !Z) */ /* < / >=        (N / !N) */ /* <= / >        (N | Z / !N & !Z) */ /* NUV / UV      (!C / C) */ /* ZNV / VNZ     (!C | Z / C & !Z) */ /* SV / NSV      (V / !V) */ /* OD / EV */