components/driver/i2s.c
/**
 * @brief   I2S calculate clock for built-in ADC/DAC mode
 *
 * @param   i2s_num         I2S device number
 * @param   clk_cfg         Struct to restore clock confiuration
 * @return
 *      - ESP_OK                Get clock success
 *      - ESP_ERR_INVALID_ARG   Invalid args
 */
@brief   I2S calculate clock for built-in ADC/DAC mode
@param   i2s_num         I2S device number
@param   clk_cfg         Struct to restore clock confiuration
@return
- ESP_OK                Get clock success
- ESP_ERR_INVALID_ARG   Invalid args
@brief I2S calculate clock for built - in ADC / DAC mode @param i2s_num I2S device number @param clk_cfg Struct to restore clock confiuration @return - ESP_OK Get clock success - ESP_ERR_INVALID_ARG Invalid args
static esp_err_t i2s_calculate_adc_dac_clock(int i2s_num, i2s_hal_clock_cfg_t *clk_cfg)
{
    ESP_RETURN_ON_FALSE(clk_cfg, ESP_ERR_INVALID_ARG, TAG, "input clk_cfg is NULL");
    ESP_RETURN_ON_FALSE(p_i2s[i2s_num]->hal_cfg.mode & (I2S_MODE_DAC_BUILT_IN | I2S_MODE_ADC_BUILT_IN), ESP_ERR_INVALID_ARG, TAG, "current mode is not built-in ADC/DAC");
    clk_cfg->bclk = p_i2s[i2s_num]->hal_cfg.sample_rate * I2S_LL_AD_BCK_FACTOR * 2;
    clk_cfg->bclk_div = I2S_LL_AD_BCK_FACTOR;
    clk_cfg->mclk = (p_i2s[i2s_num]->use_apll && p_i2s[i2s_num]->fixed_mclk) ?
                    p_i2s[i2s_num]->fixed_mclk : clk_cfg->bclk * clk_cfg->bclk_div;
    clk_cfg->bclk_div = clk_cfg->mclk / clk_cfg->bclk;
    clk_cfg->sclk = i2s_config_source_clock(i2s_num, p_i2s[i2s_num]->use_apll, clk_cfg->mclk);
    clk_cfg->mclk_div = clk_cfg->sclk / clk_cfg->mclk;
    ESP_RETURN_ON_FALSE(!clk_cfg->sclk || clk_cfg->mclk <= clk_cfg->sclk, ESP_ERR_INVALID_ARG, TAG, "sample rate is too large");
    return ESP_OK;
}
static esp_err_t i2s_calculate_adc_dac_clock ( int i2s_num , i2s_hal_clock_cfg_t * clk_cfg ) { ESP_RETURN_ON_FALSE ( clk_cfg , ESP_ERR_INVALID_ARG , TAG , " " ) ; ESP_RETURN_ON_FALSE ( p_i2s [ i2s_num ] -> hal_cfg . mode & ( I2S_MODE_DAC_BUILT_IN | I2S_MODE_ADC_BUILT_IN ) , ESP_ERR_INVALID_ARG , TAG , " " ) ; clk_cfg -> bclk = p_i2s [ i2s_num ] -> hal_cfg . sample_rate * I2S_LL_AD_BCK_FACTOR * 2 ; clk_cfg -> bclk_div = I2S_LL_AD_BCK_FACTOR ; clk_cfg -> mclk = ( p_i2s [ i2s_num ] -> use_apll && p_i2s [ i2s_num ] -> fixed_mclk ) ? p_i2s [ i2s_num ] -> fixed_mclk : clk_cfg -> bclk * clk_cfg -> bclk_div ; clk_cfg -> bclk_div = clk_cfg -> mclk / clk_cfg -> bclk ; clk_cfg -> sclk = i2s_config_source_clock ( i2s_num , p_i2s [ i2s_num ] -> use_apll , clk_cfg -> mclk ) ; clk_cfg -> mclk_div = clk_cfg -> sclk / clk_cfg -> mclk ; ESP_RETURN_ON_FALSE ( ! clk_cfg -> sclk || clk_cfg -> mclk <= clk_cfg -> sclk , ESP_ERR_INVALID_ARG , TAG , " " ) ; return ESP_OK ; }
@brief   I2S calculate clock for built-in ADC/DAC mode
 @param   i2s_num         I2S device number
 @param   clk_cfg         Struct to restore clock confiuration
 @return
      - ESP_OK                Get clock success
      - ESP_ERR_INVALID_ARG   Invalid args
@brief I2S calculate clock for built - in ADC / DAC mode @param i2s_num I2S device number @param clk_cfg Struct to restore clock confiuration @return - ESP_OK Get clock success - ESP_ERR_INVALID_ARG Invalid args
/* Set I2S bit clock */ /* Set I2S bit clock default division */ /* If fixed_mclk and use_apll are set, use fixed_mclk as mclk frequency, otherwise calculate by mclk = sample_rate * multiple */ /* Calculate bclk_div = mclk / bclk */ /* Get I2S system clock by config source clock */ /* Get I2S master clock rough division, later will calculate the fine division parameters in HAL */ /* Check if the configuration is correct */