modules/lpc4337_m4/board/src/board_sysinit.c
/* Set up and initialize clocking prior to call to main */
Set up and initialize clocking prior to call to main
Set up and initialize clocking prior to call to main
void Board_SetupClocking(void)
{
	int i;
	Chip_SetupCoreClock(CLKIN_CRYSTAL, MAX_CLOCK_FREQ, true);
	LPC_CREG->CREG0 &= ~((1 << 3) | (1 << 2));
	LPC_CREG->CREG0 |= (1 << 1) | (1 << 0);
#if (MAX_CLOCK_FREQ > 180000000)
	Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 5);
#else
	Chip_Clock_SetDivider(CLK_IDIV_E, CLKIN_MAINPLL, 4);
#endif
	Chip_Clock_SetBaseClock(CLK_BASE_SPIFI, CLKIN_IDIVE, true, false);
	for (i = 0; i < (sizeof(InitClkStates) / sizeof(InitClkStates[0])); i++) {
		Chip_Clock_SetBaseClock(InitClkStates[i].clk, InitClkStates[i].clkin,
								InitClkStates[i].autoblock_enab, InitClkStates[i].powerdn);
	}
}
void Board_SetupClocking ( void ) { int i ; Chip_SetupCoreClock ( CLKIN_CRYSTAL , MAX_CLOCK_FREQ , true ) ; LPC_CREG -> CREG0 &= ~ ( ( 1 << 3 ) | ( 1 << 2 ) ) ; LPC_CREG -> CREG0 |= ( 1 << 1 ) | ( 1 << 0 ) ; #if ( MAX_CLOCK_FREQ > 180000000 ) Chip_Clock_SetDivider ( CLK_IDIV_E , CLKIN_MAINPLL , 5 ) ; #else Chip_Clock_SetDivider ( CLK_IDIV_E , CLKIN_MAINPLL , 4 ) ; #endif Chip_Clock_SetBaseClock ( CLK_BASE_SPIFI , CLKIN_IDIVE , true , false ) ; for ( i = 0 ; i < ( sizeof ( InitClkStates ) / sizeof ( InitClkStates [ 0 ] ) ) ; i ++ ) { Chip_Clock_SetBaseClock ( InitClkStates [ i ] . clk , InitClkStates [ i ] . clkin , InitClkStates [ i ] . autoblock_enab , InitClkStates [ i ] . powerdn ) ; } }
Set up and initialize clocking prior to call to main
Set up and initialize clocking prior to call to main
/* Reset and enable 32Khz oscillator */ /* Setup a divider E for main PLL clock switch SPIFI clock to that divider.
	   Divide rate is based on CPU speed and speed of SPI FLASH part. */ /* Setup system base clocks and initial states. This won't enable and
	   disable individual clocks, but sets up the base clock sources for
	   each individual peripheral clock. */