FreeBSD/sys/dev/nxge/xgehal/xgehal-device.c
/*
 * __hal_device_handle_mc - Handle MC interrupt reason
 * @hldev: HAL device handle.
 * @reason: interrupt reason
 */
Handle MC interrupt reason
@hldev: HAL device handle.
@reason: interrupt reason
Handle MC interrupt reason @hldev : HAL device handle . @reason : interrupt reason
xge_hal_status_e
__hal_device_handle_mc(xge_hal_device_t *hldev, u64 reason)
{
	xge_hal_pci_bar0_t *isrbar0 =
	        (xge_hal_pci_bar0_t *)(void *)hldev->isrbar0;
	u64 val64;
	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
	            &isrbar0->mc_int_status);
	if (!(val64 & XGE_HAL_MC_INT_STATUS_MC_INT))
	    return XGE_HAL_OK;
	val64 = xge_os_pio_mem_read64(hldev->pdev, hldev->regh0,
	            &isrbar0->mc_err_reg);
	xge_os_pio_mem_write64(hldev->pdev, hldev->regh0,
	            val64, &isrbar0->mc_err_reg);
	if (val64 & XGE_HAL_MC_ERR_REG_ETQ_ECC_SG_ERR_L ||
	    val64 & XGE_HAL_MC_ERR_REG_ETQ_ECC_SG_ERR_U ||
	    val64 & XGE_HAL_MC_ERR_REG_MIRI_ECC_SG_ERR_0 ||
	    val64 & XGE_HAL_MC_ERR_REG_MIRI_ECC_SG_ERR_1 ||
	    (xge_hal_device_check_id(hldev) != XGE_HAL_CARD_XENA &&
	     (val64 & XGE_HAL_MC_ERR_REG_ITQ_ECC_SG_ERR_L ||
	      val64 & XGE_HAL_MC_ERR_REG_ITQ_ECC_SG_ERR_U ||
	      val64 & XGE_HAL_MC_ERR_REG_RLD_ECC_SG_ERR_L ||
	      val64 & XGE_HAL_MC_ERR_REG_RLD_ECC_SG_ERR_U))) {
	    hldev->stats.sw_dev_err_stats.single_ecc_err_cnt++;
	    hldev->stats.sw_dev_err_stats.ecc_err_cnt++;
	}
	if (val64 & XGE_HAL_MC_ERR_REG_ETQ_ECC_DB_ERR_L ||
	    val64 & XGE_HAL_MC_ERR_REG_ETQ_ECC_DB_ERR_U ||
	    val64 & XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_0 ||
	    val64 & XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_1 ||
	    (xge_hal_device_check_id(hldev) != XGE_HAL_CARD_XENA &&
	     (val64 & XGE_HAL_MC_ERR_REG_ITQ_ECC_DB_ERR_L ||
	      val64 & XGE_HAL_MC_ERR_REG_ITQ_ECC_DB_ERR_U ||
	      val64 & XGE_HAL_MC_ERR_REG_RLD_ECC_DB_ERR_L ||
	      val64 & XGE_HAL_MC_ERR_REG_RLD_ECC_DB_ERR_U))) {
	    hldev->stats.sw_dev_err_stats.double_ecc_err_cnt++;
	    hldev->stats.sw_dev_err_stats.ecc_err_cnt++;
	}
	if (val64 & XGE_HAL_MC_ERR_REG_SM_ERR) {
	    hldev->stats.sw_dev_err_stats.sm_err_cnt++;
	}
	if (val64 & XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_0 ||
	    val64 & XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_1) {
	            __hal_device_handle_eccerr(hldev, "mc_err_reg", val64);
	    return XGE_HAL_ERR_CRITICAL;
	}
	return XGE_HAL_OK;
}
xge_hal_status_e __hal_device_handle_mc ( xge_hal_device_t * hldev , u64 reason ) { xge_hal_pci_bar0_t * isrbar0 = ( xge_hal_pci_bar0_t * ) ( void * ) hldev -> isrbar0 ; u64 val64 ; val64 = xge_os_pio_mem_read64 ( hldev -> pdev , hldev -> regh0 , & isrbar0 -> mc_int_status ) ; if ( ! ( val64 & XGE_HAL_MC_INT_STATUS_MC_INT ) ) return XGE_HAL_OK ; val64 = xge_os_pio_mem_read64 ( hldev -> pdev , hldev -> regh0 , & isrbar0 -> mc_err_reg ) ; xge_os_pio_mem_write64 ( hldev -> pdev , hldev -> regh0 , val64 , & isrbar0 -> mc_err_reg ) ; if ( val64 & XGE_HAL_MC_ERR_REG_ETQ_ECC_SG_ERR_L || val64 & XGE_HAL_MC_ERR_REG_ETQ_ECC_SG_ERR_U || val64 & XGE_HAL_MC_ERR_REG_MIRI_ECC_SG_ERR_0 || val64 & XGE_HAL_MC_ERR_REG_MIRI_ECC_SG_ERR_1 || ( xge_hal_device_check_id ( hldev ) != XGE_HAL_CARD_XENA && ( val64 & XGE_HAL_MC_ERR_REG_ITQ_ECC_SG_ERR_L || val64 & XGE_HAL_MC_ERR_REG_ITQ_ECC_SG_ERR_U || val64 & XGE_HAL_MC_ERR_REG_RLD_ECC_SG_ERR_L || val64 & XGE_HAL_MC_ERR_REG_RLD_ECC_SG_ERR_U ) ) ) { hldev -> stats . sw_dev_err_stats . single_ecc_err_cnt ++ ; hldev -> stats . sw_dev_err_stats . ecc_err_cnt ++ ; } if ( val64 & XGE_HAL_MC_ERR_REG_ETQ_ECC_DB_ERR_L || val64 & XGE_HAL_MC_ERR_REG_ETQ_ECC_DB_ERR_U || val64 & XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_0 || val64 & XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_1 || ( xge_hal_device_check_id ( hldev ) != XGE_HAL_CARD_XENA && ( val64 & XGE_HAL_MC_ERR_REG_ITQ_ECC_DB_ERR_L || val64 & XGE_HAL_MC_ERR_REG_ITQ_ECC_DB_ERR_U || val64 & XGE_HAL_MC_ERR_REG_RLD_ECC_DB_ERR_L || val64 & XGE_HAL_MC_ERR_REG_RLD_ECC_DB_ERR_U ) ) ) { hldev -> stats . sw_dev_err_stats . double_ecc_err_cnt ++ ; hldev -> stats . sw_dev_err_stats . ecc_err_cnt ++ ; } if ( val64 & XGE_HAL_MC_ERR_REG_SM_ERR ) { hldev -> stats . sw_dev_err_stats . sm_err_cnt ++ ; } if ( val64 & XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_0 || val64 & XGE_HAL_MC_ERR_REG_MIRI_ECC_DB_ERR_1 ) { __hal_device_handle_eccerr ( hldev , " " , val64 ) ; return XGE_HAL_ERR_CRITICAL ; } return XGE_HAL_OK ; }
__hal_device_handle_mc - Handle MC interrupt reason
 @hldev: HAL device handle.
__hal_device_handle_mc - Handle MC interrupt reason @hldev : HAL device handle .
/* those two should result in device reset */