arch/dev/radio/dw1000/glossy/glossy.c
/*---------------------------------------------------------------------------*/
/**
 * Mutual exclusive ISR, call the first ISR based on the
 * triggered IRQs
 */
Mutual exclusive ISR, call the first ISR based on the
triggered IRQs
Mutual exclusive ISR call the first ISR based on the triggered IRQs
static void glossy_isr(void) {
    uint32 status = pdw1000local->cbData.status = dwt_read32bitreg(SYS_STATUS_ID); 
    if(status & SYS_STATUS_TXFRS) {
        dwt_write32bitreg(SYS_STATUS_ID, (SYS_STATUS_ALL_TX | SYS_STATUS_ALL_RX_ERR | SYS_STATUS_ALL_RX_TO | SYS_STATUS_ALL_RX_GOOD));
        if((status & SYS_STATUS_AAT) && pdw1000local->wait4resp)
        {
            dwt_forcetrxoff(); 
            dwt_rxreset(); 
        }
        if(pdw1000local->cbTxDone != NULL)
        {
            pdw1000local->cbTxDone(&pdw1000local->cbData);
        }
    }
    else if(status & SYS_STATUS_ALL_RX_TO) {
        dwt_write32bitreg(SYS_STATUS_ID, (SYS_STATUS_ALL_TX | SYS_STATUS_ALL_RX_ERR | SYS_STATUS_ALL_RX_TO | SYS_STATUS_ALL_RX_GOOD));
        pdw1000local->wait4resp = 0;
        dwt_forcetrxoff();
        dwt_rxreset();
        if(pdw1000local->cbRxTo != NULL)
        {
            pdw1000local->cbRxTo(&pdw1000local->cbData);
        }
    }
    else if(status & SYS_STATUS_ALL_RX_ERR) {
        dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_RXRFTO); 
        pdw1000local->wait4resp = 0;
        dwt_forcetrxoff();
        dwt_rxreset();
        if(pdw1000local->cbRxErr != NULL)
        {
            pdw1000local->cbRxErr(&pdw1000local->cbData);
        }
    }
    else if(status & SYS_STATUS_RXFCG) {
        uint16 finfo16;
        uint16 len;
        dwt_write32bitreg(SYS_STATUS_ID, (SYS_STATUS_ALL_TX | SYS_STATUS_ALL_RX_ERR | SYS_STATUS_ALL_RX_TO | SYS_STATUS_ALL_RX_GOOD));
        pdw1000local->cbData.rx_flags = 0;
        finfo16 = dwt_read16bitoffsetreg(RX_FINFO_ID, RX_FINFO_OFFSET);
        len = finfo16 & RX_FINFO_RXFL_MASK_1023;
        if(pdw1000local->longFrames == 0)
        {
            len &= RX_FINFO_RXFLEN_MASK;
        }
        pdw1000local->cbData.datalength = len;
        if(finfo16 & RX_FINFO_RNG)
        {
            pdw1000local->cbData.rx_flags |= DWT_CB_DATA_RX_FLAG_RNG;
        }
        dwt_readfromdevice(RX_BUFFER_ID, 0, FCTRL_LEN_MAX, pdw1000local->cbData.fctrl);
        if((status & SYS_STATUS_AAT) && ((pdw1000local->cbData.fctrl[0] & FCTRL_ACK_REQ_MASK) == 0))
        {
            dwt_write32bitreg(SYS_STATUS_ID, SYS_STATUS_AAT); 
            pdw1000local->cbData.status &= ~SYS_STATUS_AAT; 
            pdw1000local->wait4resp = 0;
        }
        if(pdw1000local->cbRxOk != NULL)
        {
            pdw1000local->cbRxOk(&pdw1000local->cbData);
        }
        if (pdw1000local->dblbuffon)
        {
            dwt_write8bitoffsetreg(SYS_CTRL_ID, SYS_CTRL_HRBT_OFFSET, 1);
        }
    }
}
static void glossy_isr ( void ) { uint32 status = pdw1000local -> cbData . status = dwt_read32bitreg ( SYS_STATUS_ID ) ; if ( status & SYS_STATUS_TXFRS ) { dwt_write32bitreg ( SYS_STATUS_ID , ( SYS_STATUS_ALL_TX | SYS_STATUS_ALL_RX_ERR | SYS_STATUS_ALL_RX_TO | SYS_STATUS_ALL_RX_GOOD ) ) ; if ( ( status & SYS_STATUS_AAT ) && pdw1000local -> wait4resp ) { dwt_forcetrxoff ( ) ; dwt_rxreset ( ) ; } if ( pdw1000local -> cbTxDone != NULL ) { pdw1000local -> cbTxDone ( & pdw1000local -> cbData ) ; } } else if ( status & SYS_STATUS_ALL_RX_TO ) { dwt_write32bitreg ( SYS_STATUS_ID , ( SYS_STATUS_ALL_TX | SYS_STATUS_ALL_RX_ERR | SYS_STATUS_ALL_RX_TO | SYS_STATUS_ALL_RX_GOOD ) ) ; pdw1000local -> wait4resp = 0 ; dwt_forcetrxoff ( ) ; dwt_rxreset ( ) ; if ( pdw1000local -> cbRxTo != NULL ) { pdw1000local -> cbRxTo ( & pdw1000local -> cbData ) ; } } else if ( status & SYS_STATUS_ALL_RX_ERR ) { dwt_write32bitreg ( SYS_STATUS_ID , SYS_STATUS_RXRFTO ) ; pdw1000local -> wait4resp = 0 ; dwt_forcetrxoff ( ) ; dwt_rxreset ( ) ; if ( pdw1000local -> cbRxErr != NULL ) { pdw1000local -> cbRxErr ( & pdw1000local -> cbData ) ; } } else if ( status & SYS_STATUS_RXFCG ) { uint16 finfo16 ; uint16 len ; dwt_write32bitreg ( SYS_STATUS_ID , ( SYS_STATUS_ALL_TX | SYS_STATUS_ALL_RX_ERR | SYS_STATUS_ALL_RX_TO | SYS_STATUS_ALL_RX_GOOD ) ) ; pdw1000local -> cbData . rx_flags = 0 ; finfo16 = dwt_read16bitoffsetreg ( RX_FINFO_ID , RX_FINFO_OFFSET ) ; len = finfo16 & RX_FINFO_RXFL_MASK_1023 ; if ( pdw1000local -> longFrames == 0 ) { len &= RX_FINFO_RXFLEN_MASK ; } pdw1000local -> cbData . datalength = len ; if ( finfo16 & RX_FINFO_RNG ) { pdw1000local -> cbData . rx_flags |= DWT_CB_DATA_RX_FLAG_RNG ; } dwt_readfromdevice ( RX_BUFFER_ID , 0 , FCTRL_LEN_MAX , pdw1000local -> cbData . fctrl ) ; if ( ( status & SYS_STATUS_AAT ) && ( ( pdw1000local -> cbData . fctrl [ 0 ] & FCTRL_ACK_REQ_MASK ) == 0 ) ) { dwt_write32bitreg ( SYS_STATUS_ID , SYS_STATUS_AAT ) ; pdw1000local -> cbData . status &= ~ SYS_STATUS_AAT ; pdw1000local -> wait4resp = 0 ; } if ( pdw1000local -> cbRxOk != NULL ) { pdw1000local -> cbRxOk ( & pdw1000local -> cbData ) ; } if ( pdw1000local -> dblbuffon ) { dwt_write8bitoffsetreg ( SYS_CTRL_ID , SYS_CTRL_HRBT_OFFSET , 1 ) ; } } }
Mutual exclusive ISR, call the first ISR based on the
 triggered IRQs
Mutual exclusive ISR call the first ISR based on the triggered IRQs
// Read status register low 32bits // Handle TX confirmation event // In the case where this TXFRS interrupt is due to the automatic transmission of an ACK solicited by a response (with ACK request bit set) // that we receive through using wait4resp to a previous TX (and assuming that the IRQ processing of that TX has already been handled), then // we need to handle the IC issue which turns on the RX again in this situation (i.e. because it is wrongly applying the wait4resp after the // ACK TX). // See section "Transmit and automatically wait for response" in DW1000 User Manual // Turn the RX off // Reset in case we were late and a frame was already being received // Call the corresponding callback if present // Handle frame reception/preamble detect timeout events // Because of an issue with receiver restart after error conditions, an RX reset must be applied after any error or timeout event to ensure // the next good frame's timestamp is computed correctly. // See section "RX Message timestamp" in DW1000 User Manual. // Call the corresponding callback if present // Handle RX errors events // Clear RX timeout event bits // Because of an issue with receiver restart after error conditions, an RX reset must be applied after any error or timeout event to ensure // the next good frame's timestamp is computed correctly. // See section "RX Message timestamp" in DW1000 User Manual. // Call the corresponding callback if present // Handle RX good frame event. // This event has lowest priority because if any error has occured then // it's likely that the SFD (which Glossy heavily relies on) is not available. // Read frame info - Only the first two bytes of the register are used here. // Report frame length - Standard frame length up to 127, extended frame length up to 1023 bytes // Report ranging bit // Report frame control - First bytes of the received frame. // Because of a previous frame not being received properly, AAT bit can be set upon the proper reception of a frame not requesting for // acknowledgement (ACK frame is not actually sent though). If the AAT bit is set, check ACK request bit in frame control to confirm (this // implementation works only for IEEE802.15.4-2011 compliant frames). // This issue is not documented at the time of writing this code. It should be in next release of DW1000 User Manual (v2.09, from July 2016). // Clear AAT status bit in register // Clear AAT status bit in callback data register copy // Call the corresponding callback if present // Toggle the Host side Receive Buffer Pointer