FreeBSD/sys/arm64/arm64/pmap.c
/*
 *	Clear the wired attribute from the mappings for the specified range of
 *	addresses in the given pmap.  Every valid mapping within that range
 *	must have the wired attribute set.  In contrast, invalid mappings
 *	cannot have the wired attribute set, so they are ignored.
 *
 *	The wired attribute of the page table entry is not a hardware feature,
 *	so there is no need to invalidate any TLB entries.
 */
Clear the wired attribute from the mappings for the specified range of
addresses in the given pmap.  Every valid mapping within that range
must have the wired attribute set.  In contrast, invalid mappings
cannot have the wired attribute set, so they are ignored.

The wired attribute of the page table entry is not a hardware feature,
so there is no need to invalidate any TLB entries.
Clear the wired attribute from the mappings for the specified range of addresses in the given pmap . Every valid mapping within that range must have the wired attribute set . In contrast invalid mappings cannot have the wired attribute set so they are ignored . The wired attribute of the page table entry is not a hardware feature so there is no need to invalidate any TLB entries .
void
pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
{
	vm_offset_t va_next;
	pd_entry_t *l0, *l1, *l2;
	pt_entry_t *l3;
	boolean_t pv_lists_locked;
	pv_lists_locked = FALSE;
	PMAP_LOCK(pmap);
	for (; sva < eva; sva = va_next) {
		l0 = pmap_l0(pmap, sva);
		if (pmap_load(l0) == 0) {
			va_next = (sva + L0_SIZE) & ~L0_OFFSET;
			if (va_next < sva)
				va_next = eva;
			continue;
		}
		l1 = pmap_l0_to_l1(l0, sva);
		if (pmap_load(l1) == 0) {
			va_next = (sva + L1_SIZE) & ~L1_OFFSET;
			if (va_next < sva)
				va_next = eva;
			continue;
		}
		va_next = (sva + L2_SIZE) & ~L2_OFFSET;
		if (va_next < sva)
			va_next = eva;
		l2 = pmap_l1_to_l2(l1, sva);
		if (pmap_load(l2) == 0)
			continue;
		if (va_next > eva)
			va_next = eva;
		for (l3 = pmap_l2_to_l3(l2, sva); sva != va_next; l3++,
		    sva += L3_SIZE) {
			if (pmap_load(l3) == 0)
				continue;
			if ((pmap_load(l3) & ATTR_SW_WIRED) == 0)
				panic("pmap_unwire: l3 %#jx is missing "
				    "ATTR_SW_WIRED", (uintmax_t)pmap_load(l3));
			atomic_clear_long(l3, ATTR_SW_WIRED);
			pmap->pm_stats.wired_count--;
		}
	}
	if (pv_lists_locked)
		rw_runlock(&pvh_global_lock);
	PMAP_UNLOCK(pmap);
}
void pmap_unwire ( pmap_t pmap , vm_offset_t sva , vm_offset_t eva ) { vm_offset_t va_next ; pd_entry_t * l0 , * l1 , * l2 ; pt_entry_t * l3 ; boolean_t pv_lists_locked ; pv_lists_locked = FALSE ; PMAP_LOCK ( pmap ) ; for ( ; sva < eva ; sva = va_next ) { l0 = pmap_l0 ( pmap , sva ) ; if ( pmap_load ( l0 ) == 0 ) { va_next = ( sva + L0_SIZE ) & ~ L0_OFFSET ; if ( va_next < sva ) va_next = eva ; continue ; } l1 = pmap_l0_to_l1 ( l0 , sva ) ; if ( pmap_load ( l1 ) == 0 ) { va_next = ( sva + L1_SIZE ) & ~ L1_OFFSET ; if ( va_next < sva ) va_next = eva ; continue ; } va_next = ( sva + L2_SIZE ) & ~ L2_OFFSET ; if ( va_next < sva ) va_next = eva ; l2 = pmap_l1_to_l2 ( l1 , sva ) ; if ( pmap_load ( l2 ) == 0 ) continue ; if ( va_next > eva ) va_next = eva ; for ( l3 = pmap_l2_to_l3 ( l2 , sva ) ; sva != va_next ; l3 ++ , sva += L3_SIZE ) { if ( pmap_load ( l3 ) == 0 ) continue ; if ( ( pmap_load ( l3 ) & ATTR_SW_WIRED ) == 0 ) panic ( " " " " , ( uintmax_t ) pmap_load ( l3 ) ) ; atomic_clear_long ( l3 , ATTR_SW_WIRED ) ; pmap -> pm_stats . wired_count -- ; } } if ( pv_lists_locked ) rw_runlock ( & pvh_global_lock ) ; PMAP_UNLOCK ( pmap ) ; }
Clear the wired attribute from the mappings for the specified range of
      addresses in the given pmap.
Clear the wired attribute from the mappings for the specified range of addresses in the given pmap .
/*
			 * PG_W must be cleared atomically.  Although the pmap
			 * lock synchronizes access to PG_W, another processor
			 * could be setting PG_M and/or PG_A concurrently.
			 */