linux/drivers/gpu/drm/i915/intel_guc.c
/*
 * Initialise the GuC parameter block before starting the firmware
 * transfer. These parameters are read by the firmware on startup
 * and cannot be changed thereafter.
 */
Initialise the GuC parameter block before starting the firmware
transfer. These parameters are read by the firmware on startup
and cannot be changed thereafter.
Initialise the GuC parameter block before starting the firmware transfer . These parameters are read by the firmware on startup and cannot be changed thereafter .
void intel_guc_init_params(struct intel_guc *guc)
{
	struct drm_i915_private *dev_priv = guc_to_i915(guc);
	u32 params[GUC_CTL_MAX_DWORDS];
	int i;
	memset(params, 0, sizeof(params));
	params[GUC_CTL_ARAT_HIGH] = 0;
	params[GUC_CTL_ARAT_LOW] = 100000000;
	params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
	params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc);
	params[GUC_CTL_LOG_PARAMS]  = guc_ctl_log_params_flags(guc);
	params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc);
	params[GUC_CTL_CTXINFO] = guc_ctl_ctxinfo_flags(guc);
	for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
		DRM_DEBUG_DRIVER("param[%2d] = %#x\n", i, params[i]);
	intel_uncore_forcewake_get(dev_priv, FORCEWAKE_BLITTER);
	I915_WRITE(SOFT_SCRATCH(0), 0);
	for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
		I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
	intel_uncore_forcewake_put(dev_priv, FORCEWAKE_BLITTER);
}
void intel_guc_init_params ( struct intel_guc * guc ) { struct drm_i915_private * dev_priv = guc_to_i915 ( guc ) ; u32 params [ GUC_CTL_MAX_DWORDS ] ; int i ; memset ( params , 0 , sizeof ( params ) ) ; params [ GUC_CTL_ARAT_HIGH ] = 0 ; params [ GUC_CTL_ARAT_LOW ] = 100000000 ; params [ GUC_CTL_WA ] |= GUC_CTL_WA_UK_BY_DRIVER ; params [ GUC_CTL_FEATURE ] = guc_ctl_feature_flags ( guc ) ; params [ GUC_CTL_LOG_PARAMS ] = guc_ctl_log_params_flags ( guc ) ; params [ GUC_CTL_DEBUG ] = guc_ctl_debug_flags ( guc ) ; params [ GUC_CTL_CTXINFO ] = guc_ctl_ctxinfo_flags ( guc ) ; for ( i = 0 ; i < GUC_CTL_MAX_DWORDS ; i ++ ) DRM_DEBUG_DRIVER ( " \n " , i , params [ i ] ) ; intel_uncore_forcewake_get ( dev_priv , FORCEWAKE_BLITTER ) ; I915_WRITE ( SOFT_SCRATCH ( 0 ) , 0 ) ; for ( i = 0 ; i < GUC_CTL_MAX_DWORDS ; i ++ ) I915_WRITE ( SOFT_SCRATCH ( 1 + i ) , params [ i ] ) ; intel_uncore_forcewake_put ( dev_priv , FORCEWAKE_BLITTER ) ; }
Initialise the GuC parameter block before starting the firmware
 transfer.
Initialise the GuC parameter block before starting the firmware transfer .
/*
	 * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
	 * second. This ARAR is calculated by:
	 * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
	 */ /*
	 * All SOFT_SCRATCH registers are in FORCEWAKE_BLITTER domain and
	 * they are power context saved so it's ok to release forcewake
	 * when we are done here and take it again at xfer time.
	 */