Platform/ECM3532/DSP/hw/csp/ecm3532/src/eta_csp_spi.c
/***************************************************************************/
/**
 *
 *  EtaCspSpiTransferInt - Start the SPI using Interrupt
 *
 *  @param pui8TxData is the pointer to TX Data Array.
 *  @param ui16TxLen is the TX Data Array length.
 *  @param pui8RxData is the pointer to RX Data Array.
 *  @param ui16RxLen is the RX Data Array length.
 *  @param spiChipSel is the chip select (0-3).
 *  @param iSpiSequence is the SPI command sequence.
 *
 * > eSpiSequenceMiddle is not a valid SPI command sequence when using the
 *   interrupt mode.
 *
 ******************************************************************************/
Start the SPI using Interrupt
@param pui8TxData is the pointer to TX Data Array.
@param ui16TxLen is the TX Data Array length.
@param pui8RxData is the pointer to RX Data Array.
@param ui16RxLen is the RX Data Array length.
@param spiChipSel is the chip select (0-3).
@param iSpiSequence is the SPI command sequence.

> eSpiSequenceMiddle is not a valid SPI command sequence when using the
interrupt mode.
Start the SPI using Interrupt @param pui8TxData is the pointer to TX Data Array . @param ui16TxLen is the TX Data Array length . @param pui8RxData is the pointer to RX Data Array . @param ui16RxLen is the RX Data Array length . @param spiChipSel is the chip select ( 0 - 3 ) . @param iSpiSequence is the SPI command sequence . > eSpiSequenceMiddle is not a valid SPI command sequence when using the interrupt mode .
tEtaStatus
EtaCspSpiTransferInt(uint8_t *pui8TxData, uint16_t ui16TxLen,
                     uint8_t *pui8RxData, uint16_t ui16RxLen,
                     tSpiChipSel spiChipSel, tSpiSequence iSpiSequence)
{
    tEtaStatus localStatus;
    uint32_t ui32Timeout;
    uint8_t lastcmd;
 if (ui32RxLen > (64*1024)-1)
 etaPrintf ("ERROR: EtaCspSpiTransferPoll exceeded max ui32RxLen of
 (64*1024)-1 with %d", ui32RxLen);
    if(iSpiSequence == eSpiSequenceMiddle)
    {
         return eEtaSpiInvalidConfig;
    }
     If it is first, start command
    if(iSpiSequence & eSpiSequenceFirstOnly)
    {
         Make sure previous command is done (optional)
        if(localStatus = EtaCspSpiDonePoll())
        {
            return(localStatus);
        }
         Start command
        REG_SPI2_STATUS = BM_SPI2_STATUS_START_BUSY |
                          (spiChipSel << BP_SPI2_STATUS_CS_SEL) |
                          BM_SPI2_STATUS_HOLD_CS;
    }
     If this is not the start of the command wait till
     dummy bytes registers are 0. If this is the start
     of the command these are 0 anyway.
    if(ui16TxLen)
    {
        while(REG_SPI2_RXDROP_CNT)
        {
        }
    }
    else if(ui16RxLen)
    {
        while(REG_SPI2_TX_DUMMY_BYTE_CNT)
        {
        }
    }
     Setup global array
    gsSpiCmd.pui8TxData = pui8TxData;
    gsSpiCmd.pui8RxData = pui8RxData;
    gsSpiCmd.ui16TxLen = ui16TxLen;
    gsSpiCmd.ui16RxLen = ui16RxLen;
    gsSpiCmd.ui8RxIntSize = 14;
    gsSpiCmd.ui8TxIntSize = 14;
    gsSpiCmd.bCmdActive = 1;
    gsSpiCmd.iSpiSequence = iSpiSequence;
    gsSpiCmd.spiStatus = eEtaFailure;
    if(iSpiSequence & eSpiSequenceLastOnly)
    {
        lastcmd = 1;
    }
    else
    {
        lastcmd = 0;
    }
    if(ui16TxLen)  If we have TX, lets process it.
    {
         Deal with TX first
         We'll drop ui16TxLen of data (garbage receive data during TX)
        REG_SPI2_RXDROP_CNT = ui16TxLen;
        REG_SPI2_CONFIG = (REG_SPI2_CONFIG & ~BM_SPI2_CONFIG_FIFO_LEVEL_TRIG) |
                          (gsSpiCmd.ui8TxIntSize <<
                           BP_SPI2_CONFIG_FIFO_LEVEL_TRIG);
    }
    else if(ui16RxLen)  No TX, just RX
    {
        REG_SPI2_TX_DUMMY_BYTE_CNT = ui16RxLen;
         If it is Last, end command
        if(iSpiSequence & eSpiSequenceLastOnly)
        {
             At this point, all TX is in the queue. Remove hold
            REG_SPI2_STATUS = 0;
        }
        else
        {
            REG_SPI2_INT_EN = REG_SPI2_INT_EN | BM_SPI2_INT_EN_XMIT_COMPLETE_EN0;
        }
        REG_SPI2_CONFIG = (REG_SPI2_CONFIG & ~BM_SPI2_CONFIG_FIFO_LEVEL_TRIG) |
                          (gsSpiCmd.ui8RxIntSize <<
                           BP_SPI2_CONFIG_FIFO_LEVEL_TRIG);
    }
    else  No TX, No RX
    {
         If it is Last, end command
        if(iSpiSequence & eSpiSequenceLastOnly)
        {
             At this point, all TX is in the queue. Remove hold
            REG_SPI2_STATUS = 0;
        }
    }
     Setup next expected interrupt
    REG_SPI2_INT_EN =
        ((ui16TxLen != 0) ? BM_SPI2_INT_EN_TXFIFO_HAS_LEVEL_SPACE_EN0 : 0)               |
        ((ui16RxLen != 0) ? BM_SPI2_INT_EN_RX_FIFO_HIT_LEVEL_EN0 : 0)                    |
        ((iSpiSequence & eSpiSequenceLastOnly) ? 0 : BM_SPI2_INT_EN_XMIT_COMPLETE_EN0)   |
        ((iSpiSequence & eSpiSequenceLastOnly) ? BM_SPI2_INT_EN_CMD_IS_DONE_EN0 : 0);
 orig
 REGN_W4(iNum, SPI_INT_EN, TXFIFO_HAS_LEVEL_SPACE_EN0,       (ui16TxLen != 0),
 RX_FIFO_HIT_LEVEL_EN0,            (ui16RxLen != 0),
 XMIT_COMPLETE_EN0,                ((iSpiSequence & eSpiSequenceLastOnly) ? 0
 : 1) ,
 CMD_IS_DONE_EN0,                  ((iSpiSequence & eSpiSequenceLastOnly) ? 1
 : 0) );
    return(eEtaSuccess);
}
tEtaStatus EtaCspSpiTransferInt ( uint8_t * pui8TxData , uint16_t ui16TxLen , uint8_t * pui8RxData , uint16_t ui16RxLen , tSpiChipSel spiChipSel , tSpiSequence iSpiSequence ) { tEtaStatus localStatus ; uint32_t ui32Timeout ; uint8_t lastcmd ; if ( iSpiSequence == eSpiSequenceMiddle ) { return eEtaSpiInvalidConfig ; } if ( iSpiSequence & eSpiSequenceFirstOnly ) { if ( localStatus = EtaCspSpiDonePoll ( ) ) { return ( localStatus ) ; } REG_SPI2_STATUS = BM_SPI2_STATUS_START_BUSY | ( spiChipSel << BP_SPI2_STATUS_CS_SEL ) | BM_SPI2_STATUS_HOLD_CS ; } if ( ui16TxLen ) { while ( REG_SPI2_RXDROP_CNT ) { } } gsSpiCmd . pui8TxData = pui8TxData ; gsSpiCmd . pui8RxData = pui8RxData ; gsSpiCmd . ui16TxLen = ui16TxLen ; gsSpiCmd . ui16RxLen = ui16RxLen ; gsSpiCmd . ui8RxIntSize = 14 ; gsSpiCmd . ui8TxIntSize = 14 ; gsSpiCmd . bCmdActive = 1 ; gsSpiCmd . iSpiSequence = iSpiSequence ; gsSpiCmd . spiStatus = eEtaFailure ; if ( iSpiSequence & eSpiSequenceLastOnly ) { lastcmd = 1 ; } else { lastcmd = 0 ; } if ( ui16TxLen ) { REG_SPI2_RXDROP_CNT = ui16TxLen ; REG_SPI2_CONFIG = ( REG_SPI2_CONFIG & ~ BM_SPI2_CONFIG_FIFO_LEVEL_TRIG ) | ( gsSpiCmd . ui8TxIntSize << BP_SPI2_CONFIG_FIFO_LEVEL_TRIG ) ; } else if ( ui16RxLen ) { REG_SPI2_TX_DUMMY_BYTE_CNT = ui16RxLen ; if ( iSpiSequence & eSpiSequenceLastOnly ) { REG_SPI2_STATUS = 0 ; } else { REG_SPI2_INT_EN = REG_SPI2_INT_EN | BM_SPI2_INT_EN_XMIT_COMPLETE_EN0 ; } REG_SPI2_CONFIG = ( REG_SPI2_CONFIG & ~ BM_SPI2_CONFIG_FIFO_LEVEL_TRIG ) | ( gsSpiCmd . ui8RxIntSize << BP_SPI2_CONFIG_FIFO_LEVEL_TRIG ) ; } else { if ( iSpiSequence & eSpiSequenceLastOnly ) { REG_SPI2_STATUS = 0 ; } } REG_SPI2_INT_EN = ( ( ui16TxLen != 0 ) ? BM_SPI2_INT_EN_TXFIFO_HAS_LEVEL_SPACE_EN0 : 0 ) | ( ( ui16RxLen != 0 ) ? BM_SPI2_INT_EN_RX_FIFO_HIT_LEVEL_EN0 : 0 ) | ( ( iSpiSequence & eSpiSequenceLastOnly ) ? BM_SPI2_INT_EN_CMD_IS_DONE_EN0 : 0 ) ; return ( eEtaSuccess ) ; }
EtaCspSpiTransferInt - Start the SPI using Interrupt
  @param pui8TxData is the pointer to TX Data Array.
EtaCspSpiTransferInt - Start the SPI using Interrupt @param pui8TxData is the pointer to TX Data Array .
// Impossible if we use 16 bit lengths... // but keep incase we standardize to 32 bit lengths. // if (ui32TxLen > (64*1024)-1) // { // #ifdef ETA_CSP_SPI_DEBUG // etaPrintf ("ERROR: EtaCspSpiTransferPoll exceeded max ui32TxLen of // (64*1024)-1 with %d", ui32TxLen); // #endif // return eEtaSpiInvalidConfig; // } // // if (ui32RxLen > (64*1024)-1) // { // #ifdef ETA_CSP_SPI_DEBUG // etaPrintf ("ERROR: EtaCspSpiTransferPoll exceeded max ui32RxLen of // (64*1024)-1 with %d", ui32RxLen); // #endif // return eEtaSpiInvalidConfig; // } // If it is first, start command // Make sure previous command is done (optional) // Start command // // If this is not the start of the command wait till // dummy bytes registers are 0. If this is the start // of the command these are 0 anyway. // //    else if(ui16RxLen) //    { //        while(REG_SPI2_TX_DUMMY_BYTE_CNT) //        { //        } //    } // Setup global array // If we have TX, lets process it. // Deal with TX first // We'll drop ui16TxLen of data (garbage receive data during TX) // No TX, just RX // If it is Last, end command // At this point, all TX is in the queue. Remove hold // No TX, No RX // If it is Last, end command // At this point, all TX is in the queue. Remove hold // Setup next expected interrupt //((iSpiSequence & eSpiSequenceLastOnly) ? 0 : BM_SPI2_INT_EN_XMIT_COMPLETE_EN0)   | // orig // REGN_W4(iNum, SPI_INT_EN, TXFIFO_HAS_LEVEL_SPACE_EN0,       (ui16TxLen != 0), // RX_FIFO_HIT_LEVEL_EN0,            (ui16RxLen != 0), // XMIT_COMPLETE_EN0,                ((iSpiSequence & eSpiSequenceLastOnly) ? 0 // : 1) , // CMD_IS_DONE_EN0,                  ((iSpiSequence & eSpiSequenceLastOnly) ? 1 // : 0) );