target/linux/at91/image/dfboot/src/include/lib_AT91RM9200.h
//*----------------------------------------------------------------------------
//* \fn    AT91F_PMC_GetProcessorClock
//* \brief Return processor clock in Hz (for AT91RM3400 and AT91RM9200)
//*----------------------------------------------------------------------------
\fn    AT91F_PMC_GetProcessorClock
\brief Return processor clock in Hz (for AT91RM3400 and AT91RM9200)
\ fn AT91F_PMC_GetProcessorClock \ brief Return processor clock in Hz ( for AT91RM3400 and AT91RM9200 )
static inline unsigned int AT91F_PMC_GetProcessorClock (
	AT91PS_PMC pPMC, 
	AT91PS_CKGR pCKGR, 
	unsigned int slowClock)  
{
	unsigned int reg = pPMC->PMC_MCKR;
	unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
	unsigned int pllDivider, pllMultiplier;
	switch (reg & AT91C_PMC_CSS) {
		case AT91C_PMC_CSS_SLOW_CLK: 
			return slowClock / prescaler;
		case AT91C_PMC_CSS_MAIN_CLK: 
			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
		case AT91C_PMC_CSS_PLLA_CLK: 
			reg = pCKGR->CKGR_PLLAR;
			pllDivider    = (reg  & AT91C_CKGR_DIVA);
			pllMultiplier = ((reg  & AT91C_CKGR_MULA) >> 16) + 1;
			if (reg & AT91C_CKGR_SRCA) 
				return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
			else                       
				return slowClock / pllDivider * pllMultiplier / prescaler;
		case AT91C_PMC_CSS_PLLB_CLK: 
			reg = pCKGR->CKGR_PLLBR;
			pllDivider    = (reg  & AT91C_CKGR_DIVB);
			pllMultiplier = ((reg  & AT91C_CKGR_MULB) >> 16) + 1;
			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
	}
	return 0;
}
static inline unsigned int AT91F_PMC_GetProcessorClock ( AT91PS_PMC pPMC , AT91PS_CKGR pCKGR , unsigned int slowClock ) { unsigned int reg = pPMC -> PMC_MCKR ; unsigned int prescaler = ( 1 << ( ( reg & AT91C_PMC_PRES ) >> 2 ) ) ; unsigned int pllDivider , pllMultiplier ; switch ( reg & AT91C_PMC_CSS ) { case AT91C_PMC_CSS_SLOW_CLK : return slowClock / prescaler ; case AT91C_PMC_CSS_MAIN_CLK : return AT91F_CKGR_GetMainClock ( pCKGR , slowClock ) / prescaler ; case AT91C_PMC_CSS_PLLA_CLK : reg = pCKGR -> CKGR_PLLAR ; pllDivider = ( reg & AT91C_CKGR_DIVA ) ; pllMultiplier = ( ( reg & AT91C_CKGR_MULA ) >> 16 ) + 1 ; if ( reg & AT91C_CKGR_SRCA ) return AT91F_CKGR_GetMainClock ( pCKGR , slowClock ) / pllDivider * pllMultiplier / prescaler ; else return slowClock / pllDivider * pllMultiplier / prescaler ; case AT91C_PMC_CSS_PLLB_CLK : reg = pCKGR -> CKGR_PLLBR ; pllDivider = ( reg & AT91C_CKGR_DIVB ) ; pllMultiplier = ( ( reg & AT91C_CKGR_MULB ) >> 16 ) + 1 ; return AT91F_CKGR_GetMainClock ( pCKGR , slowClock ) / pllDivider * pllMultiplier / prescaler ; } return 0 ; }
\fn    AT91F_PMC_GetProcessorClock
\brief Return processor clock in Hz (for AT91RM3400 and AT91RM9200)
\ fn AT91F_PMC_GetProcessorClock \ brief Return processor clock in Hz ( for AT91RM3400 and AT91RM9200 )
// \arg pointer to PMC controller // \arg pointer to CKGR controller // \arg slowClock in Hz // Slow clock selected // Main clock is selected // PLLA clock is selected // Source is Main clock // Source is Slow clock // PLLB clock is selected