smart_lock_cm33_core1/drivers/fsl_power.c
/**
 * brief    PMC Deep Sleep Power Down function call
 * return   nothing
 */
brief    PMC Deep Sleep Power Down function call
return   nothing
brief PMC Deep Sleep Power Down function call return nothing
void POWER_DeepPowerDown(uint32_t exclude_from_pd,
                         uint32_t sram_retention_ctrl,
                         uint64_t wakeup_interrupts,
                         uint32_t wakeup_io_ctrl)
{
    LPC_LOWPOWER_T lv_low_power_mode_cfg; 
    uint32_t cpu0_nmi_enable;
    uint32_t cpu0_int_enable_0;
    uint32_t cpu0_int_enable_1;
    memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T));
    lv_low_power_mode_cfg.CFG |= LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN
                                 << LOWPOWER_CFG_LPMODE_INDEX; 
    lv_low_power_mode_cfg.PDCTRL0 =
        (~exclude_from_pd) | kPDRUNCFG_PD_BIAS | kPDRUNCFG_PD_BODVBAT | kPDRUNCFG_PD_FRO1M | kPDRUNCFG_PD_COMP;
    lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl;
    if ((sram_retention_ctrl & 0x7FFF) != 0)
    {
        lv_low_power_mode_cfg.PDCTRL0 &= ~kPDRUNCFG_PD_LDOMEM;
    }
    lv_low_power_mode_cfg.VOLTAGE = (V_AO_0P800 << LOWPOWER_VOLTAGE_LDO_PMU_INDEX) |       
                                    (V_AO_0P750 << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX) | 
                                    (V_AO_1P100 << LOWPOWER_VOLTAGE_LDO_MEM_INDEX) |       
                                    (V_AO_1P050 << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX)   
        ;
    lv_low_power_mode_cfg.WAKEUPINT =
        wakeup_interrupts & (WAKEUP_RTC_LITE_ALARM_WAKEUP | WAKEUP_OS_EVENT_TIMER); 
    lv_low_power_mode_cfg.WAKEUPSRC =
        wakeup_interrupts & (WAKEUP_RTC_LITE_ALARM_WAKEUP | WAKEUP_OS_EVENT_TIMER |
                             WAKEUP_ALLWAKEUPIOS); 
    lv_low_power_mode_cfg.WAKEUPIOSRC = wakeup_io_ctrl;
    cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; 
    SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK;                 
    cpu0_int_enable_0 = NVIC->ISER[0];
    cpu0_int_enable_1 = NVIC->ISER[1];
    Power_EnterLowPower(&lv_low_power_mode_cfg);
    SYSCON->NMISRC |= cpu0_nmi_enable;
    NVIC->ISER[0] = cpu0_int_enable_0;
    NVIC->ISER[1] = cpu0_int_enable_1;
}
void POWER_DeepPowerDown ( uint32_t exclude_from_pd , uint32_t sram_retention_ctrl , uint64_t wakeup_interrupts , uint32_t wakeup_io_ctrl ) { LPC_LOWPOWER_T lv_low_power_mode_cfg ; uint32_t cpu0_nmi_enable ; uint32_t cpu0_int_enable_0 ; uint32_t cpu0_int_enable_1 ; memset ( & lv_low_power_mode_cfg , 0x0 , sizeof ( LPC_LOWPOWER_T ) ) ; lv_low_power_mode_cfg . CFG |= LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN << LOWPOWER_CFG_LPMODE_INDEX ; lv_low_power_mode_cfg . PDCTRL0 = ( ~ exclude_from_pd ) | kPDRUNCFG_PD_BIAS | kPDRUNCFG_PD_BODVBAT | kPDRUNCFG_PD_FRO1M | kPDRUNCFG_PD_COMP ; lv_low_power_mode_cfg . SRAMRETCTRL = sram_retention_ctrl ; if ( ( sram_retention_ctrl & 0x7FFF ) != 0 ) { lv_low_power_mode_cfg . PDCTRL0 &= ~ kPDRUNCFG_PD_LDOMEM ; } lv_low_power_mode_cfg . VOLTAGE = ( V_AO_0P800 << LOWPOWER_VOLTAGE_LDO_PMU_INDEX ) | ( V_AO_0P750 << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX ) | ( V_AO_1P100 << LOWPOWER_VOLTAGE_LDO_MEM_INDEX ) | ( V_AO_1P050 << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX ) ; lv_low_power_mode_cfg . WAKEUPINT = wakeup_interrupts & ( WAKEUP_RTC_LITE_ALARM_WAKEUP | WAKEUP_OS_EVENT_TIMER ) ; lv_low_power_mode_cfg . WAKEUPSRC = wakeup_interrupts & ( WAKEUP_RTC_LITE_ALARM_WAKEUP | WAKEUP_OS_EVENT_TIMER | WAKEUP_ALLWAKEUPIOS ) ; lv_low_power_mode_cfg . WAKEUPIOSRC = wakeup_io_ctrl ; cpu0_nmi_enable = SYSCON -> NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK ; SYSCON -> NMISRC &= ~ SYSCON_NMISRC_NMIENCPU0_MASK ; cpu0_int_enable_0 = NVIC -> ISER [ 0 ] ; cpu0_int_enable_1 = NVIC -> ISER [ 1 ] ; Power_EnterLowPower ( & lv_low_power_mode_cfg ) ; SYSCON -> NMISRC |= cpu0_nmi_enable ; NVIC -> ISER [ 0 ] = cpu0_int_enable_0 ; NVIC -> ISER [ 1 ] = cpu0_int_enable_1 ; }
brief    PMC Deep Sleep Power Down function call
 return   nothing
brief PMC Deep Sleep Power Down function call return nothing
/* Low Power Mode configuration structure */ /* Clear Low Power Mode configuration variable */ /* Configure Low Power Mode configuration variable */ /* DEEP POWER DOWN mode */ /* Only FRO32K, XTAL32K and LDO_MEM can be stay powered during DEEPPOWERDOWN (valid from application point of view;
     * Hardware allows BODVBAT, BIAS FRO1M and COMP to stay powered, that's why they are excluded below) */ /* SRAM retention control during DEEPPOWERDOWN */ /* Sanity check: If retention is required for any of SRAM instances, make sure LDO MEM will stay powered */ /* Voltage control in Low Power Modes */ /* TODO :: :: The Memories Voltage settings below are valid for Source Biasing; for voltage scaling, they need to be
     * update */ /* Set to 0.80 V */ /* Set to 0.75 V */ /* Set to 1.10 V */ /* Set to 1.05 V */ /* CPU Wake up sources control :
                                                                                       only
                                                                                       WAKEUP_RTC_LITE_ALARM_WAKEUP,
                                                                                       WAKEUP_OS_EVENT_TIMER */ /*!< Hardware Wake up sources control: : only
                                                      WAKEUP_RTC_LITE_ALARM_WAKEUP, WAKEUP_OS_EVENT_TIMER and
                                                      WAKEUP_ALLWAKEUPIOS */ /* Wake up I/O sources */ /* Save the configuration of the NMI Register */ /* Disable NMI of CPU0 */ /* Save the configuration of the CPU interrupt enable Registers (because they are overwritten inside the low power
     * API */ /* Enter low power mode */ /*** We'll reach this point ONLY and ONLY if the DEEPPOWERDOWN has not been taken (for instance because an RTC or
     * OSTIMER interrupt is pending) ***/ /* Restore the configuration of the NMI Register */ /* Restore the configuration of the CPU interrupt enable Registers (because they have been overwritten inside the
     * low power API */