src/occ_405/pss/avsbus.c
// Clear bits i_status_mask in status reg for i_bus
Clear bits i_status_mask in status reg for i_bus
Clear bits i_status_mask in status reg for i_bus
uint32_t clear_status_errors(const uint8_t i_bus, const uint32_t i_status_mask)
{
    uint32_t value = 0x40000000;
    DEBUG_OUT32(OCB_O2SCMDxB[i_bus], value, "OCB_O2SCMDxB");
    out32(OCB_O2SCMDxB[i_bus], value);
    uint32_t cmd_data = i_status_mask;
    value = 0x47780000 | (cmd_data << 3);
    value |= avs_crc_calculate(value);
    DEBUG_OUT32(OCB_O2SWDxB[i_bus], value, "OCB_O2SWDxB");
    out32(OCB_O2SWDxB[i_bus], value);
    const uint32_t l_status = wait_for_complete(i_bus);
    return l_status;
}
uint32_t clear_status_errors ( const uint8_t i_bus , const uint32_t i_status_mask ) { uint32_t value = 0x40000000 ; DEBUG_OUT32 ( OCB_O2SCMDxB [ i_bus ] , value , " " ) ; out32 ( OCB_O2SCMDxB [ i_bus ] , value ) ; uint32_t cmd_data = i_status_mask ; value = 0x47780000 | ( cmd_data << 3 ) ; value |= avs_crc_calculate ( value ) ; DEBUG_OUT32 ( OCB_O2SWDxB [ i_bus ] , value , " " ) ; out32 ( OCB_O2SWDxB [ i_bus ] , value ) ; const uint32_t l_status = wait_for_complete ( i_bus ) ; return l_status ; }
Clear bits i_status_mask in status reg for i_bus
Clear bits i_status_mask in status reg for i_bus
// Write O2SCMD[a][n] //   o2s_clear_sticky_bits = 1 // To clear status bits write the status bits you wish to clear with a 1. (in CmdData) // AVS Bus command (write status): //   0:1   StartCode = 0b01 //   2:3   Cmd = 0b00 (write+commit) //   4     CmdGroup = 0b0 (AVSBus) //   5:8   CmdDataType (STATUS = 01110b) //   9:12  Select (All rails / broadcast = 01111b ) //   13:28 CmdData (status bits to clear) //   29:31 CRC //   01000DDD DRRRRXXX XXXXXXXX XXXXXCCC //   01000111 01111--- -------- -----CCC // Calculate/add CRC // Wait for operation to complete (clear ongoing) // return the last read status