star/star.c
/*
** Routine that flushes pending interrupts (with correct priority).
** Assumes "live" registers, including EDI and EBP.
**
** Does not rebase the PC.  In fact, it will un-base the PC even if there
** aren't any pending interrupts.
**
** s680x0flushInterrupts() is actually a wrapper for this.
*/
Routine that flushes pending interrupts (with correct priority).
Assumes "live" registers, including EDI and EBP.

Does not rebase the PC.  In fact, it will un-base the PC even if there
aren't any pending interrupts.

s680x0flushInterrupts() is actually a wrapper for this.
Routine that flushes pending interrupts ( with correct priority ) . Assumes " live " registers including EDI and EBP . Does not rebase the PC . In fact it will un - base the PC even if there aren ' t any pending interrupts . s680x0flushInterrupts () is actually a wrapper for this .
static void gen_flush_interrupts(void) {
	int cycles = (cputype == 68010) ? 46 : 44;
	align(16);
	emit("flush_interrupts:\n");
	emit("sub esi,ebp\n");
	emit("xor ebp,ebp\n");
	emit("mov edx,7\n");
	emit("mov cl,80h\n");
	emit("mov ch,[__sr+1]\n"); 
	emit("and ch,7\n");
	emit(".loop:\n");
	emit("test [__interrupts],cl\n");
	emit("jz short .noint\n");
emit("mov [save_01], dl\n");			
	emit("mov dl,[__interrupts+edx]\n");
	emit("not cl\n");
	emit("and [__interrupts],cl\n");
	emit("shl edx,2\n");
	emit("call group_1_exception\n");
emit("and [__sr + 1], byte 0xF8\n");	
emit("mov dl, [save_01]\n");			
	emit("sub edi,byte %d\n", cycles);
emit("or [__sr + 1], dl\n");			
	emit("mov ecx,[__inthandler]\n");
	emit("or ecx,ecx\n");
	emit("jz short .intdone\n");
	airlock_exit();
	emit("call ecx\n");
	airlock_enter();
	emit("jmp short .intdone\n");
	emit(".noint:\n");
	emit("dec edx\n");
	emit("jz short .intdone\n");
	emit("shr cl,1\n");
	emit("cmp dl,ch\n");
	emit("jg short .loop\n");
	emit(".intdone:\n");
	emit("ret\n");
}
static void gen_flush_interrupts ( void ) { int cycles = ( cputype == 68010 ) ? 46 : 44 ; align ( 16 ) ; emit ( " \n " ) ; emit ( " \n " ) ; emit ( " \n " ) ; emit ( " \n " ) ; emit ( " \n " ) ; emit ( " \n " ) ; emit ( " \n " ) ; emit ( " \n " ) ; emit ( " \n " ) ; emit ( " \n " ) ; emit ( " \n " ) ; emit ( " \n " ) ; emit ( " \n " ) ; emit ( " \n " ) ; emit ( " \n " ) ; emit ( " \n " ) ; emit ( " \n " ) ; emit ( " \n " ) ; emit ( " \n " , cycles ) ; emit ( " \n " ) ; emit ( " \n " ) ; emit ( " \n " ) ; emit ( " \n " ) ; airlock_exit ( ) ; emit ( " \n " ) ; airlock_enter ( ) ; emit ( " \n " ) ; emit ( " \n " ) ; emit ( " \n " ) ; emit ( " \n " ) ; emit ( " \n " ) ; emit ( " \n " ) ; emit ( " \n " ) ; emit ( " \n " ) ; emit ( " \n " ) ; }
Routine that flushes pending interrupts (with correct priority).
Routine that flushes pending interrupts ( with correct priority ) .
/* Unbase PC */ /* This loop is intentionally post-tested because interrupt level 7
	** is non-maskable. */ /* current PPL */ // Stef Fix (Gens) // Stef Fix (Gens) // Stef Fix (Gens) // Stef Fix (Gens)