libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/stm32f10x_tim.c
/**
  * @brief  Deinitializes the TIMx peripheral registers to their default reset values.
  * @param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
  * @retval None
  */
@brief  Deinitializes the TIMx peripheral registers to their default reset values.
@param  TIMx: where x can be 1 to 17 to select the TIM peripheral.
@retval None
@brief Deinitializes the TIMx peripheral registers to their default reset values . @param TIMx : where x can be 1 to 17 to select the TIM peripheral . @retval None
void TIM_DeInit(TIM_TypeDef* TIMx)
{
  assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
  if (TIMx == TIM1)
  {
    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);  
  }     
  else if (TIMx == TIM2)
  {
    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
  }
  else if (TIMx == TIM3)
  {
    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
  }
  else if (TIMx == TIM4)
  {
    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
  } 
  else if (TIMx == TIM5)
  {
    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
  } 
  else if (TIMx == TIM6)
  {
    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
  } 
  else if (TIMx == TIM7)
  {
    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
  } 
  else if (TIMx == TIM8)
  {
    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
  }
  else if (TIMx == TIM9)
  {      
    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);  
   }  
  else if (TIMx == TIM10)
  {      
    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);  
  }  
  else if (TIMx == TIM11) 
  {     
    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);  
  }  
  else if (TIMx == TIM12)
  {      
    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);  
  }  
  else if (TIMx == TIM13) 
  {       
    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);  
  }
  else if (TIMx == TIM14) 
  {       
    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);  
  }        
  else if (TIMx == TIM15)
  {
    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);
    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);
  } 
  else if (TIMx == TIM16)
  {
    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);
    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);
  } 
  else
  {
    if (TIMx == TIM17)
    {
      RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);
      RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);
    }  
  }
}
void TIM_DeInit ( TIM_TypeDef * TIMx ) { assert_param ( IS_TIM_ALL_PERIPH ( TIMx ) ) ; if ( TIMx == TIM1 ) { RCC_APB2PeriphResetCmd ( RCC_APB2Periph_TIM1 , ENABLE ) ; RCC_APB2PeriphResetCmd ( RCC_APB2Periph_TIM1 , DISABLE ) ; } else if ( TIMx == TIM2 ) { RCC_APB1PeriphResetCmd ( RCC_APB1Periph_TIM2 , ENABLE ) ; RCC_APB1PeriphResetCmd ( RCC_APB1Periph_TIM2 , DISABLE ) ; } else if ( TIMx == TIM3 ) { RCC_APB1PeriphResetCmd ( RCC_APB1Periph_TIM3 , ENABLE ) ; RCC_APB1PeriphResetCmd ( RCC_APB1Periph_TIM3 , DISABLE ) ; } else if ( TIMx == TIM4 ) { RCC_APB1PeriphResetCmd ( RCC_APB1Periph_TIM4 , ENABLE ) ; RCC_APB1PeriphResetCmd ( RCC_APB1Periph_TIM4 , DISABLE ) ; } else if ( TIMx == TIM5 ) { RCC_APB1PeriphResetCmd ( RCC_APB1Periph_TIM5 , ENABLE ) ; RCC_APB1PeriphResetCmd ( RCC_APB1Periph_TIM5 , DISABLE ) ; } else if ( TIMx == TIM6 ) { RCC_APB1PeriphResetCmd ( RCC_APB1Periph_TIM6 , ENABLE ) ; RCC_APB1PeriphResetCmd ( RCC_APB1Periph_TIM6 , DISABLE ) ; } else if ( TIMx == TIM7 ) { RCC_APB1PeriphResetCmd ( RCC_APB1Periph_TIM7 , ENABLE ) ; RCC_APB1PeriphResetCmd ( RCC_APB1Periph_TIM7 , DISABLE ) ; } else if ( TIMx == TIM8 ) { RCC_APB2PeriphResetCmd ( RCC_APB2Periph_TIM8 , ENABLE ) ; RCC_APB2PeriphResetCmd ( RCC_APB2Periph_TIM8 , DISABLE ) ; } else if ( TIMx == TIM9 ) { RCC_APB2PeriphResetCmd ( RCC_APB2Periph_TIM9 , ENABLE ) ; RCC_APB2PeriphResetCmd ( RCC_APB2Periph_TIM9 , DISABLE ) ; } else if ( TIMx == TIM10 ) { RCC_APB2PeriphResetCmd ( RCC_APB2Periph_TIM10 , ENABLE ) ; RCC_APB2PeriphResetCmd ( RCC_APB2Periph_TIM10 , DISABLE ) ; } else if ( TIMx == TIM11 ) { RCC_APB2PeriphResetCmd ( RCC_APB2Periph_TIM11 , ENABLE ) ; RCC_APB2PeriphResetCmd ( RCC_APB2Periph_TIM11 , DISABLE ) ; } else if ( TIMx == TIM12 ) { RCC_APB1PeriphResetCmd ( RCC_APB1Periph_TIM12 , ENABLE ) ; RCC_APB1PeriphResetCmd ( RCC_APB1Periph_TIM12 , DISABLE ) ; } else if ( TIMx == TIM13 ) { RCC_APB1PeriphResetCmd ( RCC_APB1Periph_TIM13 , ENABLE ) ; RCC_APB1PeriphResetCmd ( RCC_APB1Periph_TIM13 , DISABLE ) ; } else if ( TIMx == TIM14 ) { RCC_APB1PeriphResetCmd ( RCC_APB1Periph_TIM14 , ENABLE ) ; RCC_APB1PeriphResetCmd ( RCC_APB1Periph_TIM14 , DISABLE ) ; } else if ( TIMx == TIM15 ) { RCC_APB2PeriphResetCmd ( RCC_APB2Periph_TIM15 , ENABLE ) ; RCC_APB2PeriphResetCmd ( RCC_APB2Periph_TIM15 , DISABLE ) ; } else if ( TIMx == TIM16 ) { RCC_APB2PeriphResetCmd ( RCC_APB2Periph_TIM16 , ENABLE ) ; RCC_APB2PeriphResetCmd ( RCC_APB2Periph_TIM16 , DISABLE ) ; } else { if ( TIMx == TIM17 ) { RCC_APB2PeriphResetCmd ( RCC_APB2Periph_TIM17 , ENABLE ) ; RCC_APB2PeriphResetCmd ( RCC_APB2Periph_TIM17 , DISABLE ) ; } } }
@brief  Deinitializes the TIMx peripheral registers to their default reset values.
@brief Deinitializes the TIMx peripheral registers to their default reset values .
/* Check the parameters */