qemu/target/arm/cpu64.c
/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
 * otherwise, a CPU with as many features enabled as our emulation supports.
 * The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
 * this only needs to handle 64 bits.
 */
cpu max: if KVM is enabled, like -cpu host (best possible with this host);
otherwise, a CPU with as many features enabled as our emulation supports.
The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
this only needs to handle 64 bits.
cpu max : if KVM is enabled like - cpu host ( best possible with this host ) ; otherwise a CPU with as many features enabled as our emulation supports . The version of ' - cpu max ' for qemu - system - arm is defined in cpu . c ; this only needs to handle 64 bits .
static void aarch64_max_initfn(Object *obj)
{
    ARMCPU *cpu = ARM_CPU(obj);
    if (kvm_enabled()) {
        kvm_arm_set_cpu_features_from_host(cpu);
    } else {
        uint64_t t;
        uint32_t u;
        aarch64_a57_initfn(obj);
        t = cpu->isar.id_aa64isar0;
        t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); 
        t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
        t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); 
        t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
        t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
        t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
        t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
        t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
        t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
        t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
        cpu->isar.id_aa64isar0 = t;
        t = cpu->isar.id_aa64isar1;
        t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
        cpu->isar.id_aa64isar1 = t;
        t = cpu->isar.id_aa64pfr0;
        t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
        t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
        t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
        cpu->isar.id_aa64pfr0 = t;
        u = cpu->isar.id_isar5;
        u = FIELD_DP32(u, ID_ISAR5, AES, 2); 
        u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
        u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
        u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
        u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
        u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
        cpu->isar.id_isar5 = u;
        u = cpu->isar.id_isar6;
        u = FIELD_DP32(u, ID_ISAR6, DP, 1);
        cpu->isar.id_isar6 = u;
#ifdef CONFIG_USER_ONLY
        cpu->ctr = 0x80038003; 
        cpu->dcz_blocksize = 7; 
#endif
        cpu->sve_max_vq = ARM_MAX_VQ;
        object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_vq,
                            cpu_max_set_sve_vq, NULL, NULL, &error_fatal);
    }
}
static void aarch64_max_initfn ( Object * obj ) { ARMCPU * cpu = ARM_CPU ( obj ) ; if ( kvm_enabled ( ) ) { kvm_arm_set_cpu_features_from_host ( cpu ) ; } else { uint64_t t ; uint32_t u ; aarch64_a57_initfn ( obj ) ; t = cpu -> isar . id_aa64isar0 ; t = FIELD_DP64 ( t , ID_AA64ISAR0 , AES , 2 ) ; t = FIELD_DP64 ( t , ID_AA64ISAR0 , SHA1 , 1 ) ; t = FIELD_DP64 ( t , ID_AA64ISAR0 , SHA2 , 2 ) ; t = FIELD_DP64 ( t , ID_AA64ISAR0 , CRC32 , 1 ) ; t = FIELD_DP64 ( t , ID_AA64ISAR0 , ATOMIC , 2 ) ; t = FIELD_DP64 ( t , ID_AA64ISAR0 , RDM , 1 ) ; t = FIELD_DP64 ( t , ID_AA64ISAR0 , SHA3 , 1 ) ; t = FIELD_DP64 ( t , ID_AA64ISAR0 , SM3 , 1 ) ; t = FIELD_DP64 ( t , ID_AA64ISAR0 , SM4 , 1 ) ; t = FIELD_DP64 ( t , ID_AA64ISAR0 , DP , 1 ) ; cpu -> isar . id_aa64isar0 = t ; t = cpu -> isar . id_aa64isar1 ; t = FIELD_DP64 ( t , ID_AA64ISAR1 , FCMA , 1 ) ; cpu -> isar . id_aa64isar1 = t ; t = cpu -> isar . id_aa64pfr0 ; t = FIELD_DP64 ( t , ID_AA64PFR0 , SVE , 1 ) ; t = FIELD_DP64 ( t , ID_AA64PFR0 , FP , 1 ) ; t = FIELD_DP64 ( t , ID_AA64PFR0 , ADVSIMD , 1 ) ; cpu -> isar . id_aa64pfr0 = t ; u = cpu -> isar . id_isar5 ; u = FIELD_DP32 ( u , ID_ISAR5 , AES , 2 ) ; u = FIELD_DP32 ( u , ID_ISAR5 , SHA1 , 1 ) ; u = FIELD_DP32 ( u , ID_ISAR5 , SHA2 , 1 ) ; u = FIELD_DP32 ( u , ID_ISAR5 , CRC32 , 1 ) ; u = FIELD_DP32 ( u , ID_ISAR5 , RDM , 1 ) ; u = FIELD_DP32 ( u , ID_ISAR5 , VCMA , 1 ) ; cpu -> isar . id_isar5 = u ; u = cpu -> isar . id_isar6 ; u = FIELD_DP32 ( u , ID_ISAR6 , DP , 1 ) ; cpu -> isar . id_isar6 = u ; #ifdef CONFIG_USER_ONLY cpu -> ctr = 0x80038003 ; cpu -> dcz_blocksize = 7 ; #endif cpu -> sve_max_vq = ARM_MAX_VQ ; object_property_add ( obj , " " , " " , cpu_max_get_sve_vq , cpu_max_set_sve_vq , NULL , NULL , & error_fatal ) ; } }
cpu max: if KVM is enabled, like -cpu host (best possible with this host);
 otherwise, a CPU with as many features enabled as our emulation supports.
cpu max : if KVM is enabled like - cpu host ( best possible with this host ) ; otherwise a CPU with as many features enabled as our emulation supports .
/* AES + PMULL */ /* SHA512 */ /* Replicate the same data to the 32-bit id registers.  */ /* AES + PMULL */ /*
         * FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet,
         * so do not set MVFR1.FPHP.  Strictly speaking this is not legal,
         * but it is also not legal to enable SVE without support for FP16,
         * and enabling SVE in system mode is more useful in the short term.
         */ /* For usermode -cpu max we can use a larger and more efficient DCZ
         * blocksize since we don't have to follow what the hardware does.
         */ /* 32 byte I and D cacheline size, VIPT icache */ /*  512 bytes */