Firmware/PeugeotDisplay4245/PeugeotDisplay4245.cydsn/Generated_Source/PSoC4/SPILCD_SCBCLK.c
/*******************************************************************************
* Function Name: SPILCD_SCBCLK_Stop
********************************************************************************
*
* Summary:
*  Stops the clock and returns immediately. This API does not require the
*  source clock to be running but may return before the hardware is actually
*  disabled.
*
* Parameters:
*  None
*
* Returns:
*  None
*
*******************************************************************************/
Function Name: SPILCD_SCBCLK_Stop
Summary:
Stops the clock and returns immediately. This API does not require the
source clock to be running but may return before the hardware is actually
disabled.

None

None
Function Name : SPILCD_SCBCLK_Stop Summary : Stops the clock and returns immediately . This API does not require the source clock to be running but may return before the hardware is actually disabled . None None
void SPILCD_SCBCLK_Stop(void)
{
#if defined CYREG_PERI_DIV_CMD
    while((SPILCD_SCBCLK_CMD_REG & SPILCD_SCBCLK_CMD_ENABLE_MASK) != 0u)
    {
    }
    SPILCD_SCBCLK_CMD_REG =
        ((uint32)SPILCD_SCBCLK__DIV_ID << SPILCD_SCBCLK_CMD_DIV_SHIFT)|
        ((uint32)SPILCD_SCBCLK_CMD_DISABLE_MASK);
#else
    SPILCD_SCBCLK_ENABLE_REG &= (uint32)(~SPILCD_SCBCLK__ENABLE_MASK);
#endif 
}
void SPILCD_SCBCLK_Stop ( void ) { #if defined CYREG_PERI_DIV_CMD while ( ( SPILCD_SCBCLK_CMD_REG & SPILCD_SCBCLK_CMD_ENABLE_MASK ) != 0u ) { } SPILCD_SCBCLK_CMD_REG = ( ( uint32 ) SPILCD_SCBCLK__DIV_ID << SPILCD_SCBCLK_CMD_DIV_SHIFT ) | ( ( uint32 ) SPILCD_SCBCLK_CMD_DISABLE_MASK ) ; #else SPILCD_SCBCLK_ENABLE_REG &= ( uint32 ) ( ~ SPILCD_SCBCLK__ENABLE_MASK ) ; #endif }
Function Name: SPILCD_SCBCLK_Stop
Summary:
Stops the clock and returns immediately.
Function Name : SPILCD_SCBCLK_Stop Summary : Stops the clock and returns immediately .
/* Make sure any previous start command has finished. */ /* Specify the target divider and it's alignment divider, and disable. */ /* Clear the bit to disable the clock. */ /* CYREG_PERI_DIV_CMD */