FreeBSD/sys/dev/qlxgb/qla_hw.c
/*
 * Name: qla_issue_cmd
 * Function: Issues commands on the CDRP interface and returns responses.
 */
qla_issue_cmd
Function: Issues commands on the CDRP interface and returns responses.
qla_issue_cmd Function : Issues commands on the CDRP interface and returns responses .
static int
qla_issue_cmd(qla_host_t *ha, qla_cdrp_t *cdrp)
{
	int	ret = 0;
	uint32_t signature;
	uint32_t count = 400; 
	uint32_t data;
	device_t dev;
	dev = ha->pci_dev;
	signature = 0xcafe0000 | 0x0100 | ha->pci_func;
	ret = qla_sem_lock(ha, Q8_SEM5_LOCK, 0, (uint32_t)ha->pci_func);
	if (ret) {
		device_printf(dev, "%s: SEM5_LOCK lock failed\n", __func__);
		return (ret);
	}
	WRITE_OFFSET32(ha, Q8_NX_CDRP_SIGNATURE, signature);
	WRITE_OFFSET32(ha, Q8_NX_CDRP_ARG1, (cdrp->cmd_arg1));
	WRITE_OFFSET32(ha, Q8_NX_CDRP_ARG2, (cdrp->cmd_arg2));
	WRITE_OFFSET32(ha, Q8_NX_CDRP_ARG3, (cdrp->cmd_arg3));
	WRITE_OFFSET32(ha, Q8_NX_CDRP_CMD_RSP, cdrp->cmd);
	while (count) {
		qla_mdelay(__func__, 10);
		data = READ_REG32(ha, Q8_NX_CDRP_CMD_RSP);
		if ((!(data & 0x80000000)))
			break;
		count--;
	}
	if ((!count) || (data != 1))
		ret = -1;
	cdrp->rsp = READ_REG32(ha, Q8_NX_CDRP_CMD_RSP);
	cdrp->rsp_arg1 = READ_REG32(ha, Q8_NX_CDRP_ARG1);
	cdrp->rsp_arg2 = READ_REG32(ha, Q8_NX_CDRP_ARG2);
	cdrp->rsp_arg3 = READ_REG32(ha, Q8_NX_CDRP_ARG3);
	qla_sem_unlock(ha, Q8_SEM5_UNLOCK);
	if (ret) {
		device_printf(dev, "%s: "
			"cmd[0x%08x] = 0x%08x\n"
			"\tsig[0x%08x] = 0x%08x\n"
			"\targ1[0x%08x] = 0x%08x\n"
			"\targ2[0x%08x] = 0x%08x\n"
			"\targ3[0x%08x] = 0x%08x\n",
			__func__, Q8_NX_CDRP_CMD_RSP, cdrp->cmd,
			Q8_NX_CDRP_SIGNATURE, signature,
			Q8_NX_CDRP_ARG1, cdrp->cmd_arg1,
			Q8_NX_CDRP_ARG2, cdrp->cmd_arg2,
			Q8_NX_CDRP_ARG3, cdrp->cmd_arg3);
		device_printf(dev, "%s: exit (ret = 0x%x)\n"
			"\t\t rsp = 0x%08x\n"
			"\t\t arg1 = 0x%08x\n"
			"\t\t arg2 = 0x%08x\n"
			"\t\t arg3 = 0x%08x\n",
			__func__, ret, cdrp->rsp,
			cdrp->rsp_arg1, cdrp->rsp_arg2, cdrp->rsp_arg3);
	}
	return (ret);
}
static int qla_issue_cmd ( qla_host_t * ha , qla_cdrp_t * cdrp ) { int ret = 0 ; uint32_t signature ; uint32_t count = 400 ; uint32_t data ; device_t dev ; dev = ha -> pci_dev ; signature = 0xcafe0000 | 0x0100 | ha -> pci_func ; ret = qla_sem_lock ( ha , Q8_SEM5_LOCK , 0 , ( uint32_t ) ha -> pci_func ) ; if ( ret ) { device_printf ( dev , " \n " , __func__ ) ; return ( ret ) ; } WRITE_OFFSET32 ( ha , Q8_NX_CDRP_SIGNATURE , signature ) ; WRITE_OFFSET32 ( ha , Q8_NX_CDRP_ARG1 , ( cdrp -> cmd_arg1 ) ) ; WRITE_OFFSET32 ( ha , Q8_NX_CDRP_ARG2 , ( cdrp -> cmd_arg2 ) ) ; WRITE_OFFSET32 ( ha , Q8_NX_CDRP_ARG3 , ( cdrp -> cmd_arg3 ) ) ; WRITE_OFFSET32 ( ha , Q8_NX_CDRP_CMD_RSP , cdrp -> cmd ) ; while ( count ) { qla_mdelay ( __func__ , 10 ) ; data = READ_REG32 ( ha , Q8_NX_CDRP_CMD_RSP ) ; if ( ( ! ( data & 0x80000000 ) ) ) break ; count -- ; } if ( ( ! count ) || ( data != 1 ) ) ret = -1 ; cdrp -> rsp = READ_REG32 ( ha , Q8_NX_CDRP_CMD_RSP ) ; cdrp -> rsp_arg1 = READ_REG32 ( ha , Q8_NX_CDRP_ARG1 ) ; cdrp -> rsp_arg2 = READ_REG32 ( ha , Q8_NX_CDRP_ARG2 ) ; cdrp -> rsp_arg3 = READ_REG32 ( ha , Q8_NX_CDRP_ARG3 ) ; qla_sem_unlock ( ha , Q8_SEM5_UNLOCK ) ; if ( ret ) { device_printf ( dev , " " " \n " " \t \n " " \t \n " " \t \n " " \t \n " , __func__ , Q8_NX_CDRP_CMD_RSP , cdrp -> cmd , Q8_NX_CDRP_SIGNATURE , signature , Q8_NX_CDRP_ARG1 , cdrp -> cmd_arg1 , Q8_NX_CDRP_ARG2 , cdrp -> cmd_arg2 , Q8_NX_CDRP_ARG3 , cdrp -> cmd_arg3 ) ; device_printf ( dev , " \n " " \t \t \n " " \t \t \n " " \t \t \n " " \t \t \n " , __func__ , ret , cdrp -> rsp , cdrp -> rsp_arg1 , cdrp -> rsp_arg2 , cdrp -> rsp_arg3 ) ; } return ( ret ) ; }
Name: qla_issue_cmd
 Function: Issues commands on the CDRP interface and returns responses.
Name : qla_issue_cmd Function : Issues commands on the CDRP interface and returns responses .
/* 4 seconds or 400 10ms intervals */