FreeBSD/sys/dev/drm2/radeon/r600.c
/* We doesn't check that the GPU really needs a reset we simply do the
 * reset, it's up to the caller to determine if the GPU needs one. We
 * might add an helper function to check that.
 */
We doesn't check that the GPU really needs a reset we simply do the
reset, it's up to the caller to determine if the GPU needs one. We
might add an helper function to check that.
We doesn ' t check that the GPU really needs a reset we simply do the reset it ' s up to the caller to determine if the GPU needs one . We might add an helper function to check that .
static void r600_gpu_soft_reset_gfx(struct radeon_device *rdev)
{
	u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
				S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
				S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
				S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
				S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
				S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
				S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
				S_008010_GUI_ACTIVE(1);
	u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
			S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
			S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
			S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
			S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
			S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
			S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
			S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
	u32 tmp;
	if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
		return;
	dev_info(rdev->dev, "  R_008010_GRBM_STATUS      = 0x%08X\n",
		RREG32(R_008010_GRBM_STATUS));
	dev_info(rdev->dev, "  R_008014_GRBM_STATUS2     = 0x%08X\n",
		RREG32(R_008014_GRBM_STATUS2));
	dev_info(rdev->dev, "  R_000E50_SRBM_STATUS      = 0x%08X\n",
		RREG32(R_000E50_SRBM_STATUS));
	dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
		RREG32(CP_STALLED_STAT1));
	dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
		RREG32(CP_STALLED_STAT2));
	dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
		RREG32(CP_BUSY_STAT));
	dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
		RREG32(CP_STAT));
	WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
	if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
	    (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
		tmp = S_008020_SOFT_RESET_CR(1) |
			S_008020_SOFT_RESET_DB(1) |
			S_008020_SOFT_RESET_CB(1) |
			S_008020_SOFT_RESET_PA(1) |
			S_008020_SOFT_RESET_SC(1) |
			S_008020_SOFT_RESET_SMX(1) |
			S_008020_SOFT_RESET_SPI(1) |
			S_008020_SOFT_RESET_SX(1) |
			S_008020_SOFT_RESET_SH(1) |
			S_008020_SOFT_RESET_TC(1) |
			S_008020_SOFT_RESET_TA(1) |
			S_008020_SOFT_RESET_VC(1) |
			S_008020_SOFT_RESET_VGT(1);
		dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
		WREG32(R_008020_GRBM_SOFT_RESET, tmp);
		RREG32(R_008020_GRBM_SOFT_RESET);
		mdelay(15);
		WREG32(R_008020_GRBM_SOFT_RESET, 0);
	}
	tmp = S_008020_SOFT_RESET_CP(1);
	dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
	WREG32(R_008020_GRBM_SOFT_RESET, tmp);
	RREG32(R_008020_GRBM_SOFT_RESET);
	mdelay(15);
	WREG32(R_008020_GRBM_SOFT_RESET, 0);
	dev_info(rdev->dev, "  R_008010_GRBM_STATUS      = 0x%08X\n",
		RREG32(R_008010_GRBM_STATUS));
	dev_info(rdev->dev, "  R_008014_GRBM_STATUS2     = 0x%08X\n",
		RREG32(R_008014_GRBM_STATUS2));
	dev_info(rdev->dev, "  R_000E50_SRBM_STATUS      = 0x%08X\n",
		RREG32(R_000E50_SRBM_STATUS));
	dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
		RREG32(CP_STALLED_STAT1));
	dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
		RREG32(CP_STALLED_STAT2));
	dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
		RREG32(CP_BUSY_STAT));
	dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
		RREG32(CP_STAT));
}
static void r600_gpu_soft_reset_gfx ( struct radeon_device * rdev ) { u32 grbm_busy_mask = S_008010_VC_BUSY ( 1 ) | S_008010_VGT_BUSY_NO_DMA ( 1 ) | S_008010_VGT_BUSY ( 1 ) | S_008010_TA03_BUSY ( 1 ) | S_008010_TC_BUSY ( 1 ) | S_008010_SX_BUSY ( 1 ) | S_008010_SH_BUSY ( 1 ) | S_008010_SPI03_BUSY ( 1 ) | S_008010_SMX_BUSY ( 1 ) | S_008010_SC_BUSY ( 1 ) | S_008010_PA_BUSY ( 1 ) | S_008010_DB03_BUSY ( 1 ) | S_008010_CR_BUSY ( 1 ) | S_008010_CB03_BUSY ( 1 ) | S_008010_GUI_ACTIVE ( 1 ) ; u32 grbm2_busy_mask = S_008014_SPI0_BUSY ( 1 ) | S_008014_SPI1_BUSY ( 1 ) | S_008014_SPI2_BUSY ( 1 ) | S_008014_SPI3_BUSY ( 1 ) | S_008014_TA0_BUSY ( 1 ) | S_008014_TA1_BUSY ( 1 ) | S_008014_TA2_BUSY ( 1 ) | S_008014_TA3_BUSY ( 1 ) | S_008014_DB0_BUSY ( 1 ) | S_008014_DB1_BUSY ( 1 ) | S_008014_DB2_BUSY ( 1 ) | S_008014_DB3_BUSY ( 1 ) | S_008014_CB0_BUSY ( 1 ) | S_008014_CB1_BUSY ( 1 ) | S_008014_CB2_BUSY ( 1 ) | S_008014_CB3_BUSY ( 1 ) ; u32 tmp ; if ( ! ( RREG32 ( GRBM_STATUS ) & GUI_ACTIVE ) ) return ; dev_info ( rdev -> dev , " \n " , RREG32 ( R_008010_GRBM_STATUS ) ) ; dev_info ( rdev -> dev , " \n " , RREG32 ( R_008014_GRBM_STATUS2 ) ) ; dev_info ( rdev -> dev , " \n " , RREG32 ( R_000E50_SRBM_STATUS ) ) ; dev_info ( rdev -> dev , " \n " , RREG32 ( CP_STALLED_STAT1 ) ) ; dev_info ( rdev -> dev , " \n " , RREG32 ( CP_STALLED_STAT2 ) ) ; dev_info ( rdev -> dev , " \n " , RREG32 ( CP_BUSY_STAT ) ) ; dev_info ( rdev -> dev , " \n " , RREG32 ( CP_STAT ) ) ; WREG32 ( R_0086D8_CP_ME_CNTL , S_0086D8_CP_ME_HALT ( 1 ) ) ; if ( ( RREG32 ( R_008010_GRBM_STATUS ) & grbm_busy_mask ) || ( RREG32 ( R_008014_GRBM_STATUS2 ) & grbm2_busy_mask ) ) { tmp = S_008020_SOFT_RESET_CR ( 1 ) | S_008020_SOFT_RESET_DB ( 1 ) | S_008020_SOFT_RESET_CB ( 1 ) | S_008020_SOFT_RESET_PA ( 1 ) | S_008020_SOFT_RESET_SC ( 1 ) | S_008020_SOFT_RESET_SMX ( 1 ) | S_008020_SOFT_RESET_SPI ( 1 ) | S_008020_SOFT_RESET_SX ( 1 ) | S_008020_SOFT_RESET_SH ( 1 ) | S_008020_SOFT_RESET_TC ( 1 ) | S_008020_SOFT_RESET_TA ( 1 ) | S_008020_SOFT_RESET_VC ( 1 ) | S_008020_SOFT_RESET_VGT ( 1 ) ; dev_info ( rdev -> dev , " \n " , tmp ) ; WREG32 ( R_008020_GRBM_SOFT_RESET , tmp ) ; RREG32 ( R_008020_GRBM_SOFT_RESET ) ; mdelay ( 15 ) ; WREG32 ( R_008020_GRBM_SOFT_RESET , 0 ) ; } tmp = S_008020_SOFT_RESET_CP ( 1 ) ; dev_info ( rdev -> dev , " \n " , tmp ) ; WREG32 ( R_008020_GRBM_SOFT_RESET , tmp ) ; RREG32 ( R_008020_GRBM_SOFT_RESET ) ; mdelay ( 15 ) ; WREG32 ( R_008020_GRBM_SOFT_RESET , 0 ) ; dev_info ( rdev -> dev , " \n " , RREG32 ( R_008010_GRBM_STATUS ) ) ; dev_info ( rdev -> dev , " \n " , RREG32 ( R_008014_GRBM_STATUS2 ) ) ; dev_info ( rdev -> dev , " \n " , RREG32 ( R_000E50_SRBM_STATUS ) ) ; dev_info ( rdev -> dev , " \n " , RREG32 ( CP_STALLED_STAT1 ) ) ; dev_info ( rdev -> dev , " \n " , RREG32 ( CP_STALLED_STAT2 ) ) ; dev_info ( rdev -> dev , " \n " , RREG32 ( CP_BUSY_STAT ) ) ; dev_info ( rdev -> dev , " \n " , RREG32 ( CP_STAT ) ) ; }
We doesn't check that the GPU really needs a reset we simply do the
 reset, it's up to the caller to determine if the GPU needs one.
We doesn ' t check that the GPU really needs a reset we simply do the reset it ' s up to the caller to determine if the GPU needs one .
/* Disable CP parsing/prefetching */ /* Check if any of the rendering block is busy and reset it */ /* Reset CP (we always reset CP) */