vscode_embedded/vscode_stm32f1_test/hal/STM32F10x_StdPeriph_Driver/src/stm32f10x_tim.c
/**
  * @brief  Initializes the TIMx Channel3 according to the specified
  *         parameters in the TIM_OCInitStruct.
  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
  *         that contains the configuration information for the specified TIM peripheral.
  * @retval None
  */
@brief  Initializes the TIMx Channel3 according to the specified
parameters in the TIM_OCInitStruct.
@param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
@param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
that contains the configuration information for the specified TIM peripheral.
@retval None
@brief Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct . @param TIMx : where x can be 1 2 3 4 5 or 8 to select the TIM peripheral . @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure that contains the configuration information for the specified TIM peripheral . @retval None
void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
{
  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
  assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
  TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
  tmpccer = TIMx->CCER;
  tmpcr2 =  TIMx->CR2;
  tmpccmrx = TIMx->CCMR2;
  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
  tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S));  
  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
  tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
  if((TIMx == TIM1) || (TIMx == TIM8))
  {
    assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
    assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
    assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));
    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
    tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));
    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));
    tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));
    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
  }
  TIMx->CR2 = tmpcr2;
  TIMx->CCMR2 = tmpccmrx;
  TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
  TIMx->CCER = tmpccer;
}
void TIM_OC3Init ( TIM_TypeDef * TIMx , TIM_OCInitTypeDef * TIM_OCInitStruct ) { uint16_t tmpccmrx = 0 , tmpccer = 0 , tmpcr2 = 0 ; assert_param ( IS_TIM_LIST3_PERIPH ( TIMx ) ) ; assert_param ( IS_TIM_OC_MODE ( TIM_OCInitStruct -> TIM_OCMode ) ) ; assert_param ( IS_TIM_OUTPUT_STATE ( TIM_OCInitStruct -> TIM_OutputState ) ) ; assert_param ( IS_TIM_OC_POLARITY ( TIM_OCInitStruct -> TIM_OCPolarity ) ) ; TIMx -> CCER &= ( uint16_t ) ( ~ ( ( uint16_t ) TIM_CCER_CC3E ) ) ; tmpccer = TIMx -> CCER ; tmpcr2 = TIMx -> CR2 ; tmpccmrx = TIMx -> CCMR2 ; tmpccmrx &= ( uint16_t ) ( ~ ( ( uint16_t ) TIM_CCMR2_OC3M ) ) ; tmpccmrx &= ( uint16_t ) ( ~ ( ( uint16_t ) TIM_CCMR2_CC3S ) ) ; tmpccmrx |= TIM_OCInitStruct -> TIM_OCMode ; tmpccer &= ( uint16_t ) ( ~ ( ( uint16_t ) TIM_CCER_CC3P ) ) ; tmpccer |= ( uint16_t ) ( TIM_OCInitStruct -> TIM_OCPolarity << 8 ) ; tmpccer |= ( uint16_t ) ( TIM_OCInitStruct -> TIM_OutputState << 8 ) ; if ( ( TIMx == TIM1 ) || ( TIMx == TIM8 ) ) { assert_param ( IS_TIM_OUTPUTN_STATE ( TIM_OCInitStruct -> TIM_OutputNState ) ) ; assert_param ( IS_TIM_OCN_POLARITY ( TIM_OCInitStruct -> TIM_OCNPolarity ) ) ; assert_param ( IS_TIM_OCNIDLE_STATE ( TIM_OCInitStruct -> TIM_OCNIdleState ) ) ; assert_param ( IS_TIM_OCIDLE_STATE ( TIM_OCInitStruct -> TIM_OCIdleState ) ) ; tmpccer &= ( uint16_t ) ( ~ ( ( uint16_t ) TIM_CCER_CC3NP ) ) ; tmpccer |= ( uint16_t ) ( TIM_OCInitStruct -> TIM_OCNPolarity << 8 ) ; tmpccer &= ( uint16_t ) ( ~ ( ( uint16_t ) TIM_CCER_CC3NE ) ) ; tmpccer |= ( uint16_t ) ( TIM_OCInitStruct -> TIM_OutputNState << 8 ) ; tmpcr2 &= ( uint16_t ) ( ~ ( ( uint16_t ) TIM_CR2_OIS3 ) ) ; tmpcr2 &= ( uint16_t ) ( ~ ( ( uint16_t ) TIM_CR2_OIS3N ) ) ; tmpcr2 |= ( uint16_t ) ( TIM_OCInitStruct -> TIM_OCIdleState << 4 ) ; tmpcr2 |= ( uint16_t ) ( TIM_OCInitStruct -> TIM_OCNIdleState << 4 ) ; } TIMx -> CR2 = tmpcr2 ; TIMx -> CCMR2 = tmpccmrx ; TIMx -> CCR3 = TIM_OCInitStruct -> TIM_Pulse ; TIMx -> CCER = tmpccer ; }
@brief  Initializes the TIMx Channel3 according to the specified
         parameters in the TIM_OCInitStruct.
@brief Initializes the TIMx Channel3 according to the specified parameters in the TIM_OCInitStruct .
/* Check the parameters */ /* Disable the Channel 2: Reset the CC2E Bit */ /* Get the TIMx CCER register value */ /* Get the TIMx CR2 register value */ /* Get the TIMx CCMR2 register value */ /* Reset the Output Compare mode and Capture/Compare selection Bits */ /* Select the Output Compare Mode */ /* Reset the Output Polarity level */ /* Set the Output Compare Polarity */ /* Set the Output State */ /* Reset the Output N Polarity level */ /* Set the Output N Polarity */ /* Reset the Output N State */ /* Set the Output N State */ /* Reset the Output Compare and Output Compare N IDLE State */ /* Set the Output Idle state */ /* Set the Output N Idle state */ /* Write to TIMx CR2 */ /* Write to TIMx CCMR2 */ /* Set the Capture Compare Register value */ /* Write to TIMx CCER */