smart_lock_cm33_core1/drivers/fsl_power.c
/**
 * brief    PMC Deep Sleep function call
 * return   nothing
 */
brief    PMC Deep Sleep function call
return   nothing
brief PMC Deep Sleep function call return nothing
void POWER_DeepSleep(uint32_t exclude_from_pd,
                     uint32_t sram_retention_ctrl,
                     uint64_t wakeup_interrupts,
                     uint32_t hardware_wake_ctrl)
{
    LPC_LOWPOWER_T lv_low_power_mode_cfg; 
    uint32_t cpu0_nmi_enable;
    uint32_t cpu0_int_enable_0;
    uint32_t cpu0_int_enable_1;
    uint32_t core_supply; 
    uint32_t dcdc_voltage;
    memset(&lv_low_power_mode_cfg, 0x0, sizeof(LPC_LOWPOWER_T));
    lv_low_power_mode_cfg.CFG |= LOWPOWER_CFG_LPMODE_DEEPSLEEP << LOWPOWER_CFG_LPMODE_INDEX; 
    lf_get_deepsleep_core_supply_cfg(exclude_from_pd, &core_supply, &dcdc_voltage);
    if (core_supply == 1)
    {
        lv_low_power_mode_cfg.PDCTRL0 =
            (~exclude_from_pd & ~kPDRUNCFG_PD_DCDC & ~kPDRUNCFG_PD_LDOMEM & ~kPDRUNCFG_PD_BIAS) |
            kPDRUNCFG_PD_LDODEEPSLEEP;
    }
    else
    {
        lv_low_power_mode_cfg.PDCTRL0 =
            (~exclude_from_pd & ~kPDRUNCFG_PD_LDODEEPSLEEP & ~kPDRUNCFG_PD_LDOMEM & ~kPDRUNCFG_PD_BIAS) |
            kPDRUNCFG_PD_DCDC;
    }
    lv_low_power_mode_cfg.PDCTRL0 |= kPDRUNCFG_PD_ROM;
    lv_low_power_mode_cfg.VOLTAGE = (V_AO_0P900 << LOWPOWER_VOLTAGE_LDO_PMU_INDEX) |       
                                    (V_AO_0P800 << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX) | 
                                    (V_AO_1P100 << LOWPOWER_VOLTAGE_LDO_MEM_INDEX) |       
                                    (V_AO_0P800 << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX) | 
                                    (V_DEEPSLEEP_0P900 << LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX) | 
                                    (dcdc_voltage << LOWPOWER_VOLTAGE_DCDC_INDEX)                  
        ;
    lv_low_power_mode_cfg.SRAMRETCTRL = sram_retention_ctrl;
    lv_low_power_mode_cfg.WAKEUPINT = wakeup_interrupts;
    lv_low_power_mode_cfg.WAKEUPSRC = wakeup_interrupts;
    lv_low_power_mode_cfg.HWWAKE = hardware_wake_ctrl;
    cpu0_nmi_enable = SYSCON->NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK; 
    SYSCON->NMISRC &= ~SYSCON_NMISRC_NMIENCPU0_MASK;                 
    cpu0_int_enable_0 = NVIC->ISER[0];
    cpu0_int_enable_1 = NVIC->ISER[1];
    Power_EnterLowPower(&lv_low_power_mode_cfg);
    SYSCON->NMISRC |= cpu0_nmi_enable;
    NVIC->ISER[0] = cpu0_int_enable_0;
    NVIC->ISER[1] = cpu0_int_enable_1;
}
void POWER_DeepSleep ( uint32_t exclude_from_pd , uint32_t sram_retention_ctrl , uint64_t wakeup_interrupts , uint32_t hardware_wake_ctrl ) { LPC_LOWPOWER_T lv_low_power_mode_cfg ; uint32_t cpu0_nmi_enable ; uint32_t cpu0_int_enable_0 ; uint32_t cpu0_int_enable_1 ; uint32_t core_supply ; uint32_t dcdc_voltage ; memset ( & lv_low_power_mode_cfg , 0x0 , sizeof ( LPC_LOWPOWER_T ) ) ; lv_low_power_mode_cfg . CFG |= LOWPOWER_CFG_LPMODE_DEEPSLEEP << LOWPOWER_CFG_LPMODE_INDEX ; lf_get_deepsleep_core_supply_cfg ( exclude_from_pd , & core_supply , & dcdc_voltage ) ; if ( core_supply == 1 ) { lv_low_power_mode_cfg . PDCTRL0 = ( ~ exclude_from_pd & ~ kPDRUNCFG_PD_DCDC & ~ kPDRUNCFG_PD_LDOMEM & ~ kPDRUNCFG_PD_BIAS ) | kPDRUNCFG_PD_LDODEEPSLEEP ; } else { lv_low_power_mode_cfg . PDCTRL0 = ( ~ exclude_from_pd & ~ kPDRUNCFG_PD_LDODEEPSLEEP & ~ kPDRUNCFG_PD_LDOMEM & ~ kPDRUNCFG_PD_BIAS ) | kPDRUNCFG_PD_DCDC ; } lv_low_power_mode_cfg . PDCTRL0 |= kPDRUNCFG_PD_ROM ; lv_low_power_mode_cfg . VOLTAGE = ( V_AO_0P900 << LOWPOWER_VOLTAGE_LDO_PMU_INDEX ) | ( V_AO_0P800 << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX ) | ( V_AO_1P100 << LOWPOWER_VOLTAGE_LDO_MEM_INDEX ) | ( V_AO_0P800 << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX ) | ( V_DEEPSLEEP_0P900 << LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX ) | ( dcdc_voltage << LOWPOWER_VOLTAGE_DCDC_INDEX ) ; lv_low_power_mode_cfg . SRAMRETCTRL = sram_retention_ctrl ; lv_low_power_mode_cfg . WAKEUPINT = wakeup_interrupts ; lv_low_power_mode_cfg . WAKEUPSRC = wakeup_interrupts ; lv_low_power_mode_cfg . HWWAKE = hardware_wake_ctrl ; cpu0_nmi_enable = SYSCON -> NMISRC & SYSCON_NMISRC_NMIENCPU0_MASK ; SYSCON -> NMISRC &= ~ SYSCON_NMISRC_NMIENCPU0_MASK ; cpu0_int_enable_0 = NVIC -> ISER [ 0 ] ; cpu0_int_enable_1 = NVIC -> ISER [ 1 ] ; Power_EnterLowPower ( & lv_low_power_mode_cfg ) ; SYSCON -> NMISRC |= cpu0_nmi_enable ; NVIC -> ISER [ 0 ] = cpu0_int_enable_0 ; NVIC -> ISER [ 1 ] = cpu0_int_enable_1 ; }
brief    PMC Deep Sleep function call
 return   nothing
brief PMC Deep Sleep function call return nothing
/* Low Power Mode configuration structure */ /* 0 = LDO DEEPSLEEP / 1 = DCDC */ /* Clear Low Power Mode configuration variable */ /* Configure Low Power Mode configuration variable */ /* DEEPSLEEP mode */ /* DCDC will be used during Deep Sleep (instead of LDO Deep Sleep); Make sure LDO MEM & Analog references will
         * stay powered */ /* LDO DEEPSLEEP will be used during Deep Sleep (instead of DCDC); Make sure LDO MEM & Analog references will
         * stay powered */ /* Shut down ROM */ /* Voltage control in DeepSleep Low Power Modes */ /* TODO :: :: The Memories Voltage settings below are valid for Source Biasing; for voltage scaling, they need to be
     * update */ /* Should be set to 0.9 V */ /* Should be set to 0.8 V  */ /* Should be set to 1.1V */ /* Should be set to 0.8V  */ /* Set to 0.90 V */ /* */ /* SRAM retention control during POWERDOWN */ /* CPU Wake up & Interrupt sources control */ /* Interrupts that allow DMA transfers with Flexcomm without waking up the Processor */ /* Save the configuration of the NMI Register */ /* Disable NMI of CPU0 */ /* Save the configuration of the CPU interrupt enable Registers (because they are overwritten inside the low power
     * API */ /* TODO :: :: Shall BOD Core be disabled ???? */ /* Enter low power mode */ /* TODO :: :: Shall BOD Core be re-enabled ???? */ /* Restore the configuration of the NMI Register */ /* Restore the configuration of the CPU interrupt enable Registers (because they have been overwritten inside the
     * low power API */