FreeRTOS/Demo/RISC-V_RV64_PolarFire_SoftConsole/polarfire_hal/platform/mpfs_hal/common/nwc/mss_pll.c
/***************************************************************************/
/**
 *
 * On startup, MSS supplied with 80MHz SCB clock

  9.2  Power on procedure for the MSS PLL clock

  During POR:
  Keep PLL in power down mode. powerdown_int_b=0

  After POR, Power-On steps:
  1)  mssclk_mux_sel_int<0>=0 & powerdown_int_b=0 & clk_standby_sel=0
  MSS PLL is powered down and selects clk_standby=scb_clk
  2)  PFC Processor writes powerdown_int_b=1 & divq0_int_en=1
  MSS PLL powers up, then lock asserts when locked.
  3)  PFC Processor switches mssclk_mux_sel_int<0>=1
  MSS PLL clock is now sent to MSS.
  4)  When BOOT authentication is complete
  a.  PFC processor writes mssclk_mux_sel_int<0>=0 to select clk_standby.
  b.  PFC Processor writes powerdown_int_b=0 to power down the PLL
  >>>>>>>> G5 Soc User code >>>>>>>>>>>>>>
  c.  MSS Processor writes new parameters to the MSS PLL
  5)  MSS Processor writes powerdown_int_b=1
  Start up the PLL with NEW parameters.
  Wait for LOCK
  6)  MSS Processor enables all 4 PLL outputs.
  7)  MSS Processor writes mssclk_mux_sel_int<0>=1 to select the MSS PLL
      clock.
 *
 ******************************************************************************/
On startup, MSS supplied with 80MHz SCB clock
9.2  Power on procedure for the MSS PLL clock

During POR:
Keep PLL in power down mode.


On startup MSS supplied with 80MHz SCB clock 9 . 2 Power on procedure for the MSS PLL clock During POR : Keep PLL in power down mode .
void mss_pll_config(void)
{
    copy_switch_code(); 
    MSS_SCB_DDR_PLL->SOFT_RESET     = PLL_INIT_AND_OUT_OF_RESET;
    MSS_SCB_MSS_PLL->SOFT_RESET     = PLL_INIT_AND_OUT_OF_RESET;
    MSS_SCB_MSS_PLL->PLL_CTRL       = LIBERO_SETTING_MSS_PLL_CTRL & ~(PLL_CTRL_REG_POWERDOWN_B_MASK);
    MSS_SCB_MSS_PLL->PLL_REF_FB     = LIBERO_SETTING_MSS_PLL_REF_FB;
    MSS_SCB_MSS_PLL->PLL_DIV_0_1    = LIBERO_SETTING_MSS_PLL_DIV_0_1;
    MSS_SCB_MSS_PLL->PLL_DIV_2_3    = LIBERO_SETTING_MSS_PLL_DIV_2_3;
    MSS_SCB_MSS_PLL->PLL_CTRL2      = LIBERO_SETTING_MSS_PLL_CTRL2;
    MSS_SCB_MSS_PLL->PLL_FRACN      = LIBERO_SETTING_MSS_PLL_FRACN;
    MSS_SCB_MSS_PLL->SSCG_REG_0     = LIBERO_SETTING_MSS_SSCG_REG_0;
    MSS_SCB_MSS_PLL->SSCG_REG_1     = LIBERO_SETTING_MSS_SSCG_REG_1;
    MSS_SCB_MSS_PLL->SSCG_REG_2     = LIBERO_SETTING_MSS_SSCG_REG_2;
    MSS_SCB_MSS_PLL->SSCG_REG_3     = LIBERO_SETTING_MSS_SSCG_REG_3;
    MSS_SCB_MSS_PLL->PLL_PHADJ      = LIBERO_SETTING_MSS_PLL_PHADJ;
    mss_mux_pre_mss_pll_config(); 
    MSS_SCB_MSS_PLL->PLL_CTRL       = (LIBERO_SETTING_MSS_PLL_CTRL) | 0x01U;
    volatile uint32_t timer_out=0x000000FFU;
    while((MSS_SCB_MSS_PLL->PLL_CTRL & PLL_CTRL_LOCK_BIT) == 0U)
    {
#ifdef RENODE_DEBUG
        break;
#endif
        if (timer_out != 0U)
        {
            timer_out--;
        }
        else
        {
        }
    }
    mss_mux_post_mss_pll_config();
}
void mss_pll_config ( void ) { copy_switch_code ( ) ; MSS_SCB_DDR_PLL -> SOFT_RESET = PLL_INIT_AND_OUT_OF_RESET ; MSS_SCB_MSS_PLL -> SOFT_RESET = PLL_INIT_AND_OUT_OF_RESET ; MSS_SCB_MSS_PLL -> PLL_CTRL = LIBERO_SETTING_MSS_PLL_CTRL & ~ ( PLL_CTRL_REG_POWERDOWN_B_MASK ) ; MSS_SCB_MSS_PLL -> PLL_REF_FB = LIBERO_SETTING_MSS_PLL_REF_FB ; MSS_SCB_MSS_PLL -> PLL_DIV_0_1 = LIBERO_SETTING_MSS_PLL_DIV_0_1 ; MSS_SCB_MSS_PLL -> PLL_DIV_2_3 = LIBERO_SETTING_MSS_PLL_DIV_2_3 ; MSS_SCB_MSS_PLL -> PLL_CTRL2 = LIBERO_SETTING_MSS_PLL_CTRL2 ; MSS_SCB_MSS_PLL -> PLL_FRACN = LIBERO_SETTING_MSS_PLL_FRACN ; MSS_SCB_MSS_PLL -> SSCG_REG_0 = LIBERO_SETTING_MSS_SSCG_REG_0 ; MSS_SCB_MSS_PLL -> SSCG_REG_1 = LIBERO_SETTING_MSS_SSCG_REG_1 ; MSS_SCB_MSS_PLL -> SSCG_REG_2 = LIBERO_SETTING_MSS_SSCG_REG_2 ; MSS_SCB_MSS_PLL -> SSCG_REG_3 = LIBERO_SETTING_MSS_SSCG_REG_3 ; MSS_SCB_MSS_PLL -> PLL_PHADJ = LIBERO_SETTING_MSS_PLL_PHADJ ; mss_mux_pre_mss_pll_config ( ) ; MSS_SCB_MSS_PLL -> PLL_CTRL = ( LIBERO_SETTING_MSS_PLL_CTRL ) | 0x01U ; volatile uint32_t timer_out = 0x000000FFU ; while ( ( MSS_SCB_MSS_PLL -> PLL_CTRL & PLL_CTRL_LOCK_BIT ) == 0U ) { #ifdef RENODE_DEBUG break ; #endif if ( timer_out != 0U ) { timer_out -- ; } else { } } mss_mux_post_mss_pll_config ( ) ; }
On startup, MSS supplied with 80MHz SCB clock
9.2  Power on procedure for the MSS PLL clock
On startup MSS supplied with 80MHz SCB clock 9 . 2 Power on procedure for the MSS PLL clock
/* copy switch code to RAM */ /*
        Enable the PLL by removing the reset-
        PERIPH / periph_reset_b  - This asserts the functional reset of the
            block.
        It is asserted at power up. When written is stays asserted until written
        to 0.
    */ /*
     * 4. c.    MSS Processor writes new parameters to the MSS PLL
     */ /*
     *  [0] REG_BYPASS_GO_B
     *  [0] BYPCK_SEL
     *  [0] RESETONLOCK
     *  [0] REG_RFCLK_SEL
     *  [0] REG_DIVQ3_EN
     *  [0] REG_DIVQ2_EN
     *  [0] REG_DIVQ1_EN
     *  [0] REG_DIVQ0_EN
     *  [0] REG_RFDIV_EN
     *  [0] REG_POWERDOWN_B
     */ /*
     * PLL calibration register
     * This value is factory set, do not overwrite
     * MSS_SCB_MSS_PLL->PLL_CAL        = LIBERO_SETTING_MSS_PLL_CAL;
     *
     */ /* PLL phase registers */ /*
     * 5)   MSS Processor writes powerdown_int_b=1
     *      Start up the PLL with NEW parameters.
            Wait for LOCK
     */ /* feed required inputs */ /* bit 0 == REG_POWERDOWN_B */ /*
     * Start up the PLL with NEW parameters.
     * Wait for LOCK
     *  todo: make wait clock based
     */ //todo: add failure mode /*
     * 6)   MSS Processor enables all 4 PLL outputs.
     * 7)   MSS Processor writes mssclk_mux_sel_int<0>=1 to select the MSS PLL
     *      clock.
     */