libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F103RB/stm32f10x_rcc.c
/**
  * @brief  Resets the RCC clock configuration to the default reset state.
  * @param  None
  * @retval None
  */
@brief  Resets the RCC clock configuration to the default reset state.
@param  None
@retval None
@brief Resets the RCC clock configuration to the default reset state . @param None @retval None
void RCC_DeInit(void)
{
  RCC->CR |= (uint32_t)0x00000001;
#ifndef STM32F10X_CL
  RCC->CFGR &= (uint32_t)0xF8FF0000;
#else
  RCC->CFGR &= (uint32_t)0xF0FF0000;
#endif    
  RCC->CR &= (uint32_t)0xFEF6FFFF;
  RCC->CR &= (uint32_t)0xFFFBFFFF;
  RCC->CFGR &= (uint32_t)0xFF80FFFF;
#ifdef STM32F10X_CL
  RCC->CR &= (uint32_t)0xEBFFFFFF;
  RCC->CIR = 0x00FF0000;
  RCC->CFGR2 = 0x00000000;
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
  RCC->CIR = 0x009F0000;
  RCC->CFGR2 = 0x00000000;      
#else
  RCC->CIR = 0x009F0000;
#endif 
}
void RCC_DeInit ( void ) { RCC -> CR |= ( uint32_t ) 0x00000001 ; #ifndef STM32F10X_CL RCC -> CFGR &= ( uint32_t ) 0xF8FF0000 ; #else RCC -> CFGR &= ( uint32_t ) 0xF0FF0000 ; #endif RCC -> CR &= ( uint32_t ) 0xFEF6FFFF ; RCC -> CR &= ( uint32_t ) 0xFFFBFFFF ; RCC -> CFGR &= ( uint32_t ) 0xFF80FFFF ; #ifdef STM32F10X_CL RCC -> CR &= ( uint32_t ) 0xEBFFFFFF ; RCC -> CIR = 0x00FF0000 ; RCC -> CFGR2 = 0x00000000 ; #elif defined ( STM32F10X_LD_VL ) || defined ( STM32F10X_MD_VL ) || defined ( STM32F10X_HD_VL ) RCC -> CIR = 0x009F0000 ; RCC -> CFGR2 = 0x00000000 ; #else RCC -> CIR = 0x009F0000 ; #endif }
@brief  Resets the RCC clock configuration to the default reset state.
@brief Resets the RCC clock configuration to the default reset state .
/* Set HSION bit */ /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ /* STM32F10X_CL */ /* Reset HSEON, CSSON and PLLON bits */ /* Reset HSEBYP bit */ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ /* Reset PLL2ON and PLL3ON bits */ /* Disable all interrupts and clear pending bits  */ /* Reset CFGR2 register */ /* Disable all interrupts and clear pending bits  */ /* Reset CFGR2 register */ /* Disable all interrupts and clear pending bits  */ /* STM32F10X_CL */