src/qemu/src-pmp/accel/tcg/cputlb.c
/* Our TLB does not support large pages, so remember the area covered by
   large pages and trigger a full TLB flush if these are invalidated.  */
Our TLB does not support large pages, so remember the area covered by
large pages and trigger a full TLB flush if these are invalidated.
Our TLB does not support large pages so remember the area covered by large pages and trigger a full TLB flush if these are invalidated .
static void tlb_add_large_page(CPUArchState *env, int mmu_idx,
                               target_ulong vaddr, target_ulong size)
{
    target_ulong lp_addr = env->tlb_d[mmu_idx].large_page_addr;
    target_ulong lp_mask = ~(size - 1);
    if (lp_addr == (target_ulong)-1) {
        lp_addr = vaddr;
    } else {
        lp_mask &= env->tlb_d[mmu_idx].large_page_mask;
        while (((lp_addr ^ vaddr) & lp_mask) != 0) {
            lp_mask <<= 1;
        }
    }
    env->tlb_d[mmu_idx].large_page_addr = lp_addr & lp_mask;
    env->tlb_d[mmu_idx].large_page_mask = lp_mask;
}
static void tlb_add_large_page ( CPUArchState * env , int mmu_idx , target_ulong vaddr , target_ulong size ) { target_ulong lp_addr = env -> tlb_d [ mmu_idx ] . large_page_addr ; target_ulong lp_mask = ~ ( size - 1 ) ; if ( lp_addr == ( target_ulong ) - 1 ) { lp_addr = vaddr ; } else { lp_mask &= env -> tlb_d [ mmu_idx ] . large_page_mask ; while ( ( ( lp_addr ^ vaddr ) & lp_mask ) != 0 ) { lp_mask <<= 1 ; } } env -> tlb_d [ mmu_idx ] . large_page_addr = lp_addr & lp_mask ; env -> tlb_d [ mmu_idx ] . large_page_mask = lp_mask ; }
Our TLB does not support large pages, so remember the area covered by
large pages and trigger a full TLB flush if these are invalidated.
Our TLB does not support large pages so remember the area covered by large pages and trigger a full TLB flush if these are invalidated .
/* No previous large page.  */ /* Extend the existing region to include the new page.
           This is a compromise between unnecessary flushes and
           the cost of maintaining a full variable size TLB.  */