kernels/linux-2.4.0/arch/mips/mm/r4xx0.c
/* We will need multiple versions of update_mmu_cache(), one that just
 * updates the TLB with the new pte(s), and another which also checks
 * for the R4k "end of page" hardware bug and does the needy.
 */
We will need multiple versions of update_mmu_cache(), one that just
updates the TLB with the new pte(s), and another which also checks
for the R4k "end of page" hardware bug and does the needy.
We will need multiple versions of update_mmu_cache () one that just updates the TLB with the new pte ( s ) and another which also checks for the R4k " end of page " hardware bug and does the needy .
void update_mmu_cache(struct vm_area_struct * vma,
				 unsigned long address, pte_t pte)
{
	unsigned long flags;
	pgd_t *pgdp;
	pmd_t *pmdp;
	pte_t *ptep;
	int idx, pid;
	if (current->active_mm != vma->vm_mm)
		return;
	pid = get_entryhi() & 0xff;
#ifdef DEBUG_TLB
	if((pid != (vma->vm_mm->context & 0xff)) || (vma->vm_mm->context == 0)) {
		printk("update_mmu_cache: Wheee, bogus tlbpid mmpid=%d tlbpid=%d\n",
		       (int) (vma->vm_mm->context & 0xff), pid);
	}
#endif
	save_and_cli(flags);
	address &= (PAGE_MASK << 1);
	set_entryhi(address | (pid));
	pgdp = pgd_offset(vma->vm_mm, address);
	BARRIER;
	tlb_probe();
	BARRIER;
	pmdp = pmd_offset(pgdp, address);
	idx = get_index();
	ptep = pte_offset(pmdp, address);
	BARRIER;
	set_entrylo0(pte_val(*ptep++) >> 6);
	set_entrylo1(pte_val(*ptep) >> 6);
	set_entryhi(address | (pid));
	BARRIER;
	if(idx < 0) {
		tlb_write_random();
	} else {
		tlb_write_indexed();
	}
	BARRIER;
	set_entryhi(pid);
	BARRIER;
	restore_flags(flags);
}
void update_mmu_cache ( struct vm_area_struct * vma , unsigned long address , pte_t pte ) { unsigned long flags ; pgd_t * pgdp ; pmd_t * pmdp ; pte_t * ptep ; int idx , pid ; if ( current -> active_mm != vma -> vm_mm ) return ; pid = get_entryhi ( ) & 0xff ; #ifdef DEBUG_TLB if ( ( pid != ( vma -> vm_mm -> context & 0xff ) ) || ( vma -> vm_mm -> context == 0 ) ) { printk ( " \n " , ( int ) ( vma -> vm_mm -> context & 0xff ) , pid ) ; } #endif save_and_cli ( flags ) ; address &= ( PAGE_MASK << 1 ) ; set_entryhi ( address | ( pid ) ) ; pgdp = pgd_offset ( vma -> vm_mm , address ) ; BARRIER ; tlb_probe ( ) ; BARRIER ; pmdp = pmd_offset ( pgdp , address ) ; idx = get_index ( ) ; ptep = pte_offset ( pmdp , address ) ; BARRIER ; set_entrylo0 ( pte_val ( * ptep ++ ) >> 6 ) ; set_entrylo1 ( pte_val ( * ptep ) >> 6 ) ; set_entryhi ( address | ( pid ) ) ; BARRIER ; if ( idx < 0 ) { tlb_write_random ( ) ; } else { tlb_write_indexed ( ) ; } BARRIER ; set_entryhi ( pid ) ; BARRIER ; restore_flags ( flags ) ; }
We will need multiple versions of update_mmu_cache(), one that just
 updates the TLB with the new pte(s), and another which also checks
 for the R4k "end of page" hardware bug and does the needy.
We will need multiple versions of update_mmu_cache () one that just updates the TLB with the new pte ( s ) and another which also checks for the R4k " end of page " hardware bug and does the needy .
/*
	 * Handle debugger faulting in for debugee.
	 */