Opcode:
```
0xe28fc600
```
It should be:
```
ADR r12, #0
```
Another opcode:
```
0xe28cca24
```
Should be:
```
ADD r12, r12, #0x24000
```
But I got an unexpected imm op[3], which seems not be expanded (rotr op[2] by op[3]).:
```
echo "0x24,0xca,0x8c,0xe2,0x00,0xc6,0x8f,0xe2" | llvm-mc-19 --triple=arm --disassemble
	.text
	add	r12, r12, #36, #20
	add	r12, pc, #0, #12
```

Origin post: https://github.com/capstone-engine/capstone/issues/2373
ARM32 instruction disassemble wrong on ADD
This is a GitHub Issue
repo:llvm-project
owner:llvm
Title : ARM32 instruction disassemble wrong on ADD
Issue date:

--- start body ---
Opcode:
```
0xe28fc600
```
It should be:
```
ADR r12, #0
```
Another opcode:
```
0xe28cca24
```
Should be:
```
ADD r12, r12, #0x24000
```
But I got an unexpected imm op[3], which seems not be expanded (rotr op[2] by op[3]).:
```
echo "0x24,0xca,0x8c,0xe2,0x00,0xc6,0x8f,0xe2" | llvm-mc-19 --triple=arm --disassemble
	.text
	add	r12, r12, #36, #20
	add	r12, pc, #0, #12
```

Origin post: https://github.com/capstone-engine/capstone/issues/2373
--- end body ---
