A way of building an XOR gate from only NAND gates, using the expression A⋅B¯+A¯⋅B{\displaystyle A\cdot {\overline {B}}+{\overline {A}}\cdot B}. This construction has a propagation delay 3 times that of a single gate and uses 5 gates. This is worse than an equivalent design using 4 gates.
This file was derived from:

 XOR from NOR.svg
XNOR from NAND.svg
Officer781