The physical layout of a hypothetical CMOS AND circuit. The larger regions of N-type diffusion and P-type diffusion are part of the transistors; the green forms the transistor gates.  The two smaller regions on the left are taps, to prevent latchup.
In actual circuits, NAND logic is used instead of this layout, because to make this AND the transistor gates need to be driven at slightly higher voltage to make the transistors fully switch on.
CMOS_NAND_Layout.svg
Orion Lawlor

derivative work, original by Jamesm76