Datasets:
File size: 897 Bytes
2ac7363 |
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 |
---
dataset_info:
features:
- name: instruction
dtype: string
- name: input
dtype: string
- name: output
dtype: string
- name: metadata
dtype: string
task_categories:
- text-generation
language:
- en
tags:
- verilog
- hardware-design
- hdl
- fpga
- asic
size_categories:
- 1K<n<10K
---
# Verilog and hardware design training data collection
## Contents
- **cvdp_expert_problems.json**: CVDP expert-level problems
- **cvdp_memory_problems.json**: CVDP memory-focused problems
- **cvdp_processor_problems.json**: CVDP processor design problems
## Usage
```python
from datasets import load_dataset
dataset = load_dataset('AbiralArch/verilog-training-data')
```
## Statistics
- **Files**: 3
- **Total Size**: 10.1 MB
- **Uploaded**: 2025-07-31 20:40:12
## Files Available
- `cvdp_expert_problems.json`
- `cvdp_memory_problems.json`
- `cvdp_processor_problems.json`
|