hwt/synthesizer/vectorUtils.py
def iterBits(sigOrVal: Union[RtlSignal, Value], bitsInOne: int=1,
             skipPadding: bool=True, fillup: bool=False):
    """
    Iterate over bits in vector

    :param sigOrVal: signal or value to iterate over
    :param bitsInOne: number of bits in one part
    :param skipPadding: if true padding is skipped in dense types
    """
    bw = BitWalker(sigOrVal, skipPadding, fillup)
    for _ in range(ceil(sigOrVal._dtype.bit_length() / bitsInOne)):
        yield bw.get(bitsInOne)

    bw.assertIsOnEnd()
def iterBits(sigOrVal: Union[RtlSignal, Value], bitsInOne: int=1,
             skipPadding: bool=True, fillup: bool=False):
    bw = BitWalker(sigOrVal, skipPadding, fillup)
    for _ in range(ceil(sigOrVal._dtype.bit_length() / bitsInOne)):
        yield bw.get(bitsInOne)

    bw.assertIsOnEnd()
def iterBits ( sigOrVal : Union [ RtlSignal , Value ] , bitsInOne : int = 1 , skipPadding : bool = True , fillup : bool = False ) : bw = BitWalker ( sigOrVal , skipPadding , fillup ) for _ in range ( ceil ( sigOrVal . _dtype . bit_length ( ) / bitsInOne ) ) : yield bw . get ( bitsInOne ) bw . assertIsOnEnd ( )
Iterate over bits in vector

    :param sigOrVal: signal or value to iterate over
    :param bitsInOne: number of bits in one part
    :param skipPadding: if true padding is skipped in dense types
Iterate over bits in vector