hwt/serializer/resourceAnalyzer/analyzer.py
def HWProcess(cls, proc: HWProcess, ctx: ResourceContext) -> None:
        """
        Gues resource usage by HWProcess
        """
        seen = ctx.seen
        for stm in proc.statements:
            encl = stm._enclosed_for
            full_ev_dep = stm._is_completly_event_dependent
            now_ev_dep = stm._now_is_event_dependent
            ev_dep = full_ev_dep or now_ev_dep

            out_mux_dim = count_mux_inputs_for_outputs(stm)
            for o in stm._outputs:
                if o in seen:
                    continue

                i = out_mux_dim[o]
                if isinstance(o._dtype, HArray):
                    assert i == 1, (o, i, " only one ram port per HWProcess")
                    for a in walk_assignments(stm, o):
                        assert len(a.indexes) == 1, "one address per RAM port"
                        addr = a.indexes[0]
                    ctx.registerRAM_write_port(o, addr, ev_dep)
                elif ev_dep:
                    ctx.registerFF(o)
                    if i > 1:
                        ctx.registerMUX(stm, o, i)
                elif o not in encl:
                    ctx.registerLatch(o)
                    if i > 1:
                        ctx.registerMUX(stm, o, i)
                elif i > 1:
                    ctx.registerMUX(stm, o, i)
                else:
                    # just a connection
                    continue

            if isinstance(stm, SwitchContainer):
                caseEqs = set([stm.switchOn._eq(c[0]) for c in stm.cases])
                inputs = chain(
                    [sig for sig in stm._inputs if sig not in caseEqs], [stm.switchOn])
            else:
                inputs = stm._inputs

            for i in inputs:
                # discover only internal signals in this statements for
                # operators
                if not i.hidden or i in seen:
                    continue

                cls.HWProcess_operators(i, ctx, ev_dep)
def HWProcess(cls, proc: HWProcess, ctx: ResourceContext) -> None:
        seen = ctx.seen
        for stm in proc.statements:
            encl = stm._enclosed_for
            full_ev_dep = stm._is_completly_event_dependent
            now_ev_dep = stm._now_is_event_dependent
            ev_dep = full_ev_dep or now_ev_dep

            out_mux_dim = count_mux_inputs_for_outputs(stm)
            for o in stm._outputs:
                if o in seen:
                    continue

                i = out_mux_dim[o]
                if isinstance(o._dtype, HArray):
                    assert i == 1, (o, i, " only one ram port per HWProcess")
                    for a in walk_assignments(stm, o):
                        assert len(a.indexes) == 1, "one address per RAM port"
                        addr = a.indexes[0]
                    ctx.registerRAM_write_port(o, addr, ev_dep)
                elif ev_dep:
                    ctx.registerFF(o)
                    if i > 1:
                        ctx.registerMUX(stm, o, i)
                elif o not in encl:
                    ctx.registerLatch(o)
                    if i > 1:
                        ctx.registerMUX(stm, o, i)
                elif i > 1:
                    ctx.registerMUX(stm, o, i)
                else:
                    # just a connection
                    continue

            if isinstance(stm, SwitchContainer):
                caseEqs = set([stm.switchOn._eq(c[0]) for c in stm.cases])
                inputs = chain(
                    [sig for sig in stm._inputs if sig not in caseEqs], [stm.switchOn])
            else:
                inputs = stm._inputs

            for i in inputs:
                # discover only internal signals in this statements for
                # operators
                if not i.hidden or i in seen:
                    continue

                cls.HWProcess_operators(i, ctx, ev_dep)
def HWProcess ( cls , proc : HWProcess , ctx : ResourceContext ) -> None : seen = ctx . seen for stm in proc . statements : encl = stm . _enclosed_for full_ev_dep = stm . _is_completly_event_dependent now_ev_dep = stm . _now_is_event_dependent ev_dep = full_ev_dep or now_ev_dep out_mux_dim = count_mux_inputs_for_outputs ( stm ) for o in stm . _outputs : if o in seen : continue i = out_mux_dim [ o ] if isinstance ( o . _dtype , HArray ) : assert i == 1 , ( o , i , " only one ram port per HWProcess" ) for a in walk_assignments ( stm , o ) : assert len ( a . indexes ) == 1 , "one address per RAM port" addr = a . indexes [ 0 ] ctx . registerRAM_write_port ( o , addr , ev_dep ) elif ev_dep : ctx . registerFF ( o ) if i > 1 : ctx . registerMUX ( stm , o , i ) elif o not in encl : ctx . registerLatch ( o ) if i > 1 : ctx . registerMUX ( stm , o , i ) elif i > 1 : ctx . registerMUX ( stm , o , i ) else : # just a connection continue if isinstance ( stm , SwitchContainer ) : caseEqs = set ( [ stm . switchOn . _eq ( c [ 0 ] ) for c in stm . cases ] ) inputs = chain ( [ sig for sig in stm . _inputs if sig not in caseEqs ] , [ stm . switchOn ] ) else : inputs = stm . _inputs for i in inputs : # discover only internal signals in this statements for # operators if not i . hidden or i in seen : continue cls . HWProcess_operators ( i , ctx , ev_dep )
Gues resource usage by HWProcess
Gues resource usage by HWProcess