hwt/synthesizer/rtlLevel/netlist.py
def synthesize(self, name, interfaces, targetPlatform):
        """
        Build Entity and Architecture instance out of netlist representation
        """
        ent = Entity(name)
        ent._name = name + "_inst"  # instance name

        # create generics
        for _, v in self.params.items():
            ent.generics.append(v)

        # interface set for faster lookup
        if isinstance(interfaces, set):
            intfSet = interfaces
        else:
            intfSet = set(interfaces)

        # create ports
        for s in interfaces:
            pi = portItemfromSignal(s, ent)
            pi.registerInternSig(s)
            ent.ports.append(pi)
            s.hidden = False

        removeUnconnectedSignals(self)
        markVisibilityOfSignals(self, name, self.signals, intfSet)

        for proc in targetPlatform.beforeHdlArchGeneration:
            proc(self)

        arch = Architecture(ent)
        for p in statements_to_HWProcesses(self.statements):
            arch.processes.append(p)

        # add signals, variables etc. in architecture
        for s in self.signals:
            if s not in intfSet and not s.hidden:
                arch.variables.append(s)

        # instantiate subUnits in architecture
        for u in self.subUnits:
            arch.componentInstances.append(u)

        # add components in architecture
        for su in distinctBy(self.subUnits, lambda x: x.name):
            arch.components.append(su)

        self.synthesised = True

        return [ent, arch]
def synthesize(self, name, interfaces, targetPlatform):
        ent = Entity(name)
        ent._name = name + "_inst"  # instance name

        # create generics
        for _, v in self.params.items():
            ent.generics.append(v)

        # interface set for faster lookup
        if isinstance(interfaces, set):
            intfSet = interfaces
        else:
            intfSet = set(interfaces)

        # create ports
        for s in interfaces:
            pi = portItemfromSignal(s, ent)
            pi.registerInternSig(s)
            ent.ports.append(pi)
            s.hidden = False

        removeUnconnectedSignals(self)
        markVisibilityOfSignals(self, name, self.signals, intfSet)

        for proc in targetPlatform.beforeHdlArchGeneration:
            proc(self)

        arch = Architecture(ent)
        for p in statements_to_HWProcesses(self.statements):
            arch.processes.append(p)

        # add signals, variables etc. in architecture
        for s in self.signals:
            if s not in intfSet and not s.hidden:
                arch.variables.append(s)

        # instantiate subUnits in architecture
        for u in self.subUnits:
            arch.componentInstances.append(u)

        # add components in architecture
        for su in distinctBy(self.subUnits, lambda x: x.name):
            arch.components.append(su)

        self.synthesised = True

        return [ent, arch]
def synthesize ( self , name , interfaces , targetPlatform ) : ent = Entity ( name ) ent . _name = name + "_inst" # instance name # create generics for _ , v in self . params . items ( ) : ent . generics . append ( v ) # interface set for faster lookup if isinstance ( interfaces , set ) : intfSet = interfaces else : intfSet = set ( interfaces ) # create ports for s in interfaces : pi = portItemfromSignal ( s , ent ) pi . registerInternSig ( s ) ent . ports . append ( pi ) s . hidden = False removeUnconnectedSignals ( self ) markVisibilityOfSignals ( self , name , self . signals , intfSet ) for proc in targetPlatform . beforeHdlArchGeneration : proc ( self ) arch = Architecture ( ent ) for p in statements_to_HWProcesses ( self . statements ) : arch . processes . append ( p ) # add signals, variables etc. in architecture for s in self . signals : if s not in intfSet and not s . hidden : arch . variables . append ( s ) # instantiate subUnits in architecture for u in self . subUnits : arch . componentInstances . append ( u ) # add components in architecture for su in distinctBy ( self . subUnits , lambda x : x . name ) : arch . components . append ( su ) self . synthesised = True return [ ent , arch ]
Build Entity and Architecture instance out of netlist representation
Build Entity and Architecture instance out of netlist representation