<s> from __future__ import print_function <EOL> import re <EOL> import os <EOL> import sys <EOL> import inspect <EOL> import collections <EOL> from ... model . metaclasses import MetaCollectArgs <EOL> from pymtl import * <EOL> from . . translation . verilog_structural import ( <EOL> mangle_name , tab , endl , port_delim , pretty_align , <EOL> title_bar , header , start_mod , port_declarations , end_mod , <EOL> start_param , end_param , start_ports , end_ports , connection , <EOL> ) <EOL> class VerilogImportError ( Exception ) : <EOL> pass <EOL> class SomeMeta ( MetaCollectArgs ) : <EOL> def __call__ ( self , * args , ** kwargs ) : <EOL> inst = super ( SomeMeta , self ) . __call__ ( * args , ** kwargs ) <EOL> from . . translation . verilator_sim import TranslationTool <EOL> inst . vcd_file = '<STR_LIT>' <EOL> new_inst = TranslationTool ( inst , lint = True ) <EOL> new_inst . vcd_file = None <EOL> new_inst . __class__ . __name__ = inst . __class__ . __name__ <EOL> new_inst . __class__ . __bases__ = ( VerilogModel , ) <EOL> new_inst . _args = inst . _args <EOL> new_inst . vprefix = inst . vprefix <EOL> new_inst . modulename = inst . modulename <EOL> new_inst . sourcefile = inst . sourcefile <EOL> new_inst . vlinetrace = inst . vlinetrace <EOL> new_inst . _param_dict = inst . _param_dict <EOL> new_inst . _port_dict = inst . _port_dict <EOL> try : <EOL> new_inst . __class__ . line_trace = inst . __class__ . __dict__ [ '<STR_LIT>' ] <EOL> if inst . vlinetrace : <EOL> raise VerilogImportError ( "<STR_LIT>" <EOL> "<STR_LIT>" <EOL> "<STR_LIT>" ) <EOL> except KeyError : <EOL> pass <EOL> return new_inst <EOL> class VerilogModel ( Model ) : <EOL> """<STR_LIT>""" <EOL> __metaclass__ = SomeMeta <EOL> modulename = None <EOL> sourcefile = None <EOL> vprefix = None <EOL> vlinetrace = False <EOL> _param_dict = None <EOL> _port_dict = None <EOL> def set_params ( self , param_dict ) : <EOL> """<STR_LIT>""" <EOL> self . _param_dict = collections . OrderedDict ( sorted ( param_dict . items ( ) ) ) <EOL> def set_ports ( self , port_dict ) : <EOL> """<STR_LIT>""" <EOL> self . _port_dict = collections . OrderedDict ( sorted ( port_dict . items ( ) ) ) <EOL> def _auto_init ( self ) : <EOL> """<STR_LIT>""" <EOL> if not self . modulename : <EOL> self . modulename = self . __class__ . __name__ <EOL> if not self . sourcefile : <EOL> file_ = inspect . getfile ( self . __class__ ) <EOL> self . sourcefile = os . path . join ( os . path . dirname ( file_ ) , <EOL> self . modulename + '<STR_LIT>' ) <EOL> if self . vprefix and not self . modulename . startswith ( self . vprefix ) : <EOL> self . modulename = self . vprefix + "<STR_LIT:_>" + self . modulename <EOL> if not self . _param_dict : <EOL> self . _param_dict = self . _args <EOL> if not self . _port_dict : <EOL> self . _port_dict = { port . name : port for port in self . get_ports ( ) } <EOL> def import_module ( model , o ) : <EOL> """<STR_LIT>""" <EOL> symtab = [ ( ) ] * <NUM_LIT:4> <EOL> print ( header ( model , symtab ) , file = o , end = '<STR_LIT>' ) <EOL> print ( start_mod . format ( model . class_name ) , file = o , ) <EOL> print ( port_declarations ( model , symtab ) , file = o , end = '<STR_LIT>' ) <EOL> print ( _instantiate_verilog ( model ) , file = o ) <EOL> print ( end_mod . format ( model . class_name ) , file = o ) <EOL> print ( file = o ) <EOL> return model . sourcefile <EOL> include_re = re . compile ( r'<STR_LIT>' ) <EOL> def output_verilog_file ( fout , include_path , verilog_file ) : <EOL> with open ( verilog_file , '<STR_LIT:r>' ) as fp : <EOL> short_verilog_file = verilog_file <EOL> if verilog_file . startswith ( include_path + "<STR_LIT:/>" ) : <EOL> short_verilog_file = verilog_file [ len ( include_path + "<STR_LIT:/>" ) : ] <EOL> fout . write ( '<STR_LIT>' . format ( short_verilog_file ) ) <EOL> line_num = <NUM_LIT:0> <EOL> for line in fp : <EOL> line_num += <NUM_LIT:1> <EOL> if '<STR_LIT>' in line : <EOL> filename = include_re . search ( line ) . group ( '<STR_LIT:filename>' ) <EOL> fullname = os . path . join ( include_path , filename ) <EOL> output_verilog_file ( fout , include_path , fullname ) <EOL> fout . write ( '<STR_LIT:\n>' ) <EOL> fout . write ( '<STR_LIT>' . format ( line_num + <NUM_LIT:1> , short_verilog_file ) ) <EOL> else : <EOL> fout . write ( line ) <EOL> def import_sources ( source_list , o ) : <EOL> """<STR_LIT>""" <EOL> if not source_list : <EOL> return <EOL> top_verilog_file = source_list [ <NUM_LIT:0> ] <EOL> _path = os . path . dirname ( top_verilog_file ) <EOL> special_file_found = False <EOL> include_path = os . path . dirname ( os . path . abspath ( top_verilog_file ) ) <EOL> while include_path != "<STR_LIT:/>" : <EOL> if os . path . exists ( include_path + os . path . sep + "<STR_LIT>" ) : <EOL> special_file_found = True <EOL> sys . path . insert ( <NUM_LIT:0> , include_path ) <EOL> break <EOL> include_path = os . path . dirname ( include_path ) <EOL> if not special_file_found : <EOL> include_path = os . path . dirname ( os . path . abspath ( top_verilog_file ) ) <EOL> include_re = re . compile ( r'<STR_LIT>' ) <EOL> output_verilog_file ( o , include_path , source_list [ <NUM_LIT:0> ] ) <EOL> def _instantiate_verilog ( model ) : <EOL> model . _auto_init ( ) <EOL> params = [ connection . format ( k , v ) for k , v in model . _param_dict . items ( ) ] <EOL> connections = [ ] <EOL> for verilog_portname , port in model . _port_dict . items ( ) : <EOL> pymtl_port = mangle_name ( port . name ) <EOL> connections . append ( connection . format ( verilog_portname , pymtl_port ) ) <EOL> connections = pretty_align ( connections , '<STR_LIT:(>' ) <EOL> s = tab + '<STR_LIT>' + endl <EOL> s += tab + '<STR_LIT>' . format ( model . sourcefile ) + endl <EOL> s += endl <EOL> s += tab + model . modulename + start_param + endl <EOL> s += port_delim . join ( params ) + endl <EOL> s += tab + end_param + tab + '<STR_LIT>' + endl <EOL> s += tab + start_ports + endl <EOL> s += port_delim . join ( connections ) + endl <EOL> s += tab + end_ports + endl <EOL> return s </s>
