<s> from __future__ import absolute_import <EOL> from __future__ import print_function <EOL> import os <EOL> import sys <EOL> from pyverilog . dataflow . dataflow_analyzer import VerilogDataflowAnalyzer <EOL> codedir = os . path . dirname ( os . path . dirname ( os . path . dirname ( os . path . abspath ( __file__ ) ) ) ) + '<STR_LIT>' <EOL> expected = """<STR_LIT>""" <EOL> def test ( ) : <EOL> filelist = [ codedir + '<STR_LIT>' ] <EOL> topmodule = '<STR_LIT>' <EOL> noreorder = False <EOL> nobind = False <EOL> include = None <EOL> define = None <EOL> analyzer = VerilogDataflowAnalyzer ( filelist , topmodule , <EOL> noreorder = noreorder , <EOL> nobind = nobind , <EOL> preprocess_include = include , <EOL> preprocess_define = define ) <EOL> analyzer . generate ( ) <EOL> directives = analyzer . get_directives ( ) <EOL> instances = analyzer . getInstances ( ) <EOL> terms = analyzer . getTerms ( ) <EOL> binddict = analyzer . getBinddict ( ) <EOL> output = [ ] <EOL> for bk , bv in sorted ( binddict . items ( ) , key = lambda x : str ( x [ <NUM_LIT:0> ] ) ) : <EOL> for bvi in bv : <EOL> output . append ( bvi . tostr ( ) ) <EOL> output . append ( '<STR_LIT:\n>' ) <EOL> rslt = '<STR_LIT>' . join ( output ) <EOL> print ( rslt ) <EOL> assert ( expected == rslt ) <EOL> if __name__ == '<STR_LIT:__main__>' : <EOL> test ( ) </s>
