<s> from __future__ import absolute_import <EOL> from __future__ import print_function <EOL> import sys <EOL> import os <EOL> sys . path . insert ( <NUM_LIT:0> , os . path . dirname ( os . path . dirname ( os . path . dirname ( os . path . dirname ( os . path . dirname ( os . path . abspath ( __file__ ) ) ) ) ) ) ) <EOL> from veriloggen import * <EOL> def mkLed ( ) : <EOL> m = Module ( '<STR_LIT>' ) <EOL> clk = m . Input ( '<STR_LIT>' ) <EOL> rst = m . Input ( '<STR_LIT>' ) <EOL> valid = m . OutputReg ( '<STR_LIT>' , initval = <NUM_LIT:0> ) <EOL> count = m . Reg ( '<STR_LIT:count>' , width = <NUM_LIT:32> , initval = <NUM_LIT:0> ) <EOL> up = m . Wire ( '<STR_LIT>' ) <EOL> down = m . Wire ( '<STR_LIT>' ) <EOL> m . Assign ( up ( <NUM_LIT:1> ) ) <EOL> m . Assign ( down ( <NUM_LIT:0> ) ) <EOL> fsm = FSM ( m , '<STR_LIT>' , clk , rst ) <EOL> for i in range ( <NUM_LIT:4> ) : <EOL> fsm . goto_next ( ) <EOL> c = count >= <NUM_LIT:16> <EOL> fsm . add ( valid ( up ) , cond = c , keep = <NUM_LIT:3> , eager_val = True , lazy_cond = True ) <EOL> fsm . add ( valid ( down ) , cond = c , delay = <NUM_LIT:3> , eager_val = True , lazy_cond = True ) <EOL> fsm . goto_next ( cond = c ) <EOL> for i in range ( <NUM_LIT:8> ) : <EOL> fsm . goto_next ( ) <EOL> c = count >= <NUM_LIT:32> <EOL> for i in range ( <NUM_LIT:8> ) : <EOL> fsm . add ( valid ( up ) , cond = c , delay = <NUM_LIT:1> , keep = <NUM_LIT:3> , eager_val = True , lazy_cond = True ) <EOL> fsm . add ( valid ( down ) , cond = c , delay = <NUM_LIT:4> , eager_val = True , lazy_cond = True ) <EOL> fsm . goto_next ( cond = c ) <EOL> fsm . make_always ( reset = [ count . reset ( ) ] , body = [ count ( count + <NUM_LIT:1> ) ] ) <EOL> return m <EOL> def mkTest ( ) : <EOL> m = Module ( '<STR_LIT:test>' ) <EOL> clk = m . Reg ( '<STR_LIT>' ) <EOL> rst = m . Reg ( '<STR_LIT>' ) <EOL> valid = m . Wire ( '<STR_LIT>' ) <EOL> uut = m . Instance ( mkLed ( ) , '<STR_LIT>' , <EOL> ports = ( ( '<STR_LIT>' , clk ) , ( '<STR_LIT>' , rst ) , ( '<STR_LIT>' , valid ) ) ) <EOL> simulation . setup_waveform ( m , uut ) <EOL> simulation . setup_clock ( m , clk , hperiod = <NUM_LIT:5> ) <EOL> init = simulation . setup_reset ( m , rst , period = <NUM_LIT:100> ) <EOL> init . add ( <EOL> Delay ( <NUM_LIT:1000> ) , <EOL> Systask ( '<STR_LIT>' ) , <EOL> ) <EOL> return m <EOL> if __name__ == '<STR_LIT:__main__>' : <EOL> test = mkTest ( ) <EOL> verilog = test . to_verilog ( '<STR_LIT>' ) <EOL> print ( verilog ) </s>
