<s> """<STR_LIT>""" <EOL> from functools import partial <EOL> from ctypes import Structure , c_ulong , string_at , byref , sizeof <EOL> from struct import pack , unpack <EOL> import inspect <EOL> import ast <EOL> import numbers <EOL> import numpy <EOL> class _partialmethod ( partial ) : <EOL> '<STR_LIT>' <EOL> def __get__ ( self , obj , type ) : <EOL> return partial ( self . func , obj , <EOL> * ( self . args or ( ) ) , ** ( self . keywords or { } ) ) <EOL> class AssembleError ( Exception ) : <EOL> '<STR_LIT>' <EOL> _SIGNAL = { <EOL> name : code <EOL> for code , name in enumerate ( [ <EOL> '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , <EOL> '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , <EOL> '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , <EOL> '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , <EOL> '<STR_LIT>' <EOL> ] ) } <EOL> _ADD_INSN = { <EOL> name : code <EOL> for code , name in enumerate ( [ <EOL> '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , <EOL> '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , <EOL> '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , <EOL> '<STR_LIT>' , '<STR_LIT>' <EOL> ] ) if name <EOL> } <EOL> _MUL_INSN = { <EOL> name : code <EOL> for code , name in enumerate ( [ <EOL> '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' <EOL> ] ) } <EOL> _BRANCH_INSN = { <EOL> name : code <EOL> for code , name in enumerate ( [ <EOL> '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , <EOL> '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' <EOL> ] ) if name <EOL> } <EOL> _SMALL_IMM = { <EOL> value : code <EOL> for code , value in enumerate ( <EOL> [ repr ( i ) for i in range ( <NUM_LIT:16> ) ] + <EOL> [ repr ( i ) for i in range ( - <NUM_LIT:16> , <NUM_LIT:0> ) ] + <EOL> [ repr ( <NUM_LIT> ** i ) for i in range ( <NUM_LIT:8> ) ] + <EOL> [ repr ( <NUM_LIT> ** i ) for i in range ( - <NUM_LIT:8> , <NUM_LIT:0> ) ] <EOL> ) } <EOL> _SMALL_IMM [ '<STR_LIT>' ] = <NUM_LIT:0> <EOL> _COND = { <EOL> name : code <EOL> for code , name in enumerate ( [ <EOL> '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' <EOL> ] ) } <EOL> _INPUT_MUXES = { <EOL> '<STR_LIT>' : <NUM_LIT:0> , '<STR_LIT>' : <NUM_LIT:1> , '<STR_LIT>' : <NUM_LIT:2> , '<STR_LIT>' : <NUM_LIT:3> , '<STR_LIT>' : <NUM_LIT:4> , '<STR_LIT>' : <NUM_LIT:5> , '<STR_LIT:A>' : <NUM_LIT:6> , '<STR_LIT:B>' : <NUM_LIT:7> <EOL> } <EOL> _PACK = { <EOL> op : code <EOL> for code , op in enumerate ( [ <EOL> '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , <EOL> '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , <EOL> '<STR_LIT>' <EOL> ] ) } <EOL> _UNPACK = { <EOL> op : code <EOL> for code , op in enumerate ( [ <EOL> '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' <EOL> ] ) } <EOL> _MUL_PACK = { <EOL> '<STR_LIT>' : <NUM_LIT:0> , <EOL> '<STR_LIT>' : <NUM_LIT:3> , <EOL> '<STR_LIT>' : <NUM_LIT:4> , <EOL> '<STR_LIT>' : <NUM_LIT:5> , <EOL> '<STR_LIT>' : <NUM_LIT:6> , <EOL> '<STR_LIT>' : <NUM_LIT:7> <EOL> } <EOL> _REG_AR = <NUM_LIT:1> << <NUM_LIT:3> <EOL> _REG_BR = <NUM_LIT:1> << <NUM_LIT:2> <EOL> _REG_AW = <NUM_LIT:1> << <NUM_LIT:1> <EOL> _REG_BW = <NUM_LIT:1> << <NUM_LIT:0> <EOL> class Register ( object ) : <EOL> """<STR_LIT>""" <EOL> def __init__ ( self , name , addr , spec , pack = <NUM_LIT:0> , unpack = <NUM_LIT:0> , pm = False ) : <EOL> self . name = name <EOL> self . addr = addr <EOL> self . spec = spec <EOL> self . pack_bits = pack <EOL> self . unpack_bits = unpack <EOL> self . pm_bit = pm <EOL> def __str__ ( self ) : <EOL> return self . name <EOL> def pack ( self , op ) : <EOL> """<STR_LIT>""" <EOL> if ( self . name in [ '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' , '<STR_LIT>' ] or <EOL> not ( self . spec & _REG_AW ) ) : <EOL> raise AssembleError ( <EOL> '<STR_LIT>' <EOL> ) <EOL> return Register ( self . name , self . addr , _REG_AW , pack = _PACK [ op ] , pm = <NUM_LIT:0> ) <EOL> def unpack ( self , op ) : <EOL> """<STR_LIT>""" <EOL> if self . name != '<STR_LIT>' and not ( self . spec & _REG_AR ) : <EOL> raise AssembleError ( <EOL> '<STR_LIT>' <EOL> '<STR_LIT>' <EOL> ) <EOL> if self . name == '<STR_LIT>' : <EOL> spec = self . spec <EOL> pm = <NUM_LIT:1> <EOL> else : <EOL> spec = _REG_AR <EOL> pm = <NUM_LIT:0> <EOL> return Register ( self . name , self . addr , spec , unpack = _UNPACK [ op ] , pm = pm ) <EOL> GENERAL_PURPOSE_REGISTERS = { <EOL> name : Register ( <EOL> name , addr , <EOL> { '<STR_LIT:a>' : _REG_AR | _REG_AW , '<STR_LIT:b>' : _REG_BR | _REG_BW } [ regfile ] <EOL> ) <EOL> for regfile in [ '<STR_LIT:a>' , '<STR_LIT:b>' ] <EOL> for addr in range ( <NUM_LIT:32> ) <EOL> for name in [ '<STR_LIT:r>' + regfile + str ( addr ) ] <EOL> } <EOL> IO_REGISTERS = { <EOL> name : Register ( name , addr , spec ) <EOL> for name , addr , spec in [ <EOL> ( '<STR_LIT>' , <NUM_LIT:32> , _REG_AR | _REG_BR ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AR | _REG_BR ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AW | _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AW | _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AR ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_BR ) , <EOL> ( '<STR_LIT:null>' , <NUM_LIT> , _REG_AR | _REG_BR | _REG_AW | _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AW | _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AR ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_BR ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AR | _REG_AW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_BR | _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AW | _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AW | _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AW | _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AW | _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AW | _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AR | _REG_BR | _REG_AW | _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AR ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_BR ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT:50> , _REG_AR ) , <EOL> ( '<STR_LIT>' , <NUM_LIT:50> , _REG_BR ) , <EOL> ( '<STR_LIT>' , <NUM_LIT:50> , _REG_AW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT:50> , _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AR | _REG_BR | _REG_AW | _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AW | _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AW | _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AW | _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AW | _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AW | _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AW | _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AW | _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AW | _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AW | _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AW | _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AW | _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AW | _REG_BW ) <EOL> ] } <EOL> ACCUMULATORS = { <EOL> name : Register ( name , addr , spec ) <EOL> for name , addr , spec in [ <EOL> ( '<STR_LIT>' , <NUM_LIT:32> , _REG_AW | _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AW | _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AW | _REG_BW ) , <EOL> ( '<STR_LIT>' , <NUM_LIT> , _REG_AW | _REG_BW ) , <EOL> ( '<STR_LIT>' , - <NUM_LIT:1> , <NUM_LIT:0> ) , <EOL> ( '<STR_LIT>' , - <NUM_LIT:1> , <NUM_LIT:0> ) , <EOL> ] } <EOL> REGISTERS = { } <EOL> REGISTERS . update ( GENERAL_PURPOSE_REGISTERS ) <EOL> REGISTERS . update ( IO_REGISTERS ) <EOL> REGISTERS . update ( ACCUMULATORS ) <EOL> class Insn ( Structure ) : <EOL> '<STR_LIT>' <EOL> def to_bytes ( self ) : <EOL> '<STR_LIT>' <EOL> return string_at ( byref ( self ) , sizeof ( self ) ) <EOL> @ classmethod <EOL> def from_bytes ( self , buf ) : <EOL> '<STR_LIT>' <EOL> bytes , = unpack ( '<STR_LIT>' , buf ) <EOL> sig = bytes >> <NUM_LIT> <EOL> if sig == _SIGNAL [ '<STR_LIT>' ] : <EOL> return BranchInsn . from_buffer_copy ( buf ) <EOL> elif sig == _SIGNAL [ '<STR_LIT>' ] : <EOL> if ( bytes >> <NUM_LIT> ) & <NUM_LIT> == <NUM_LIT:4> : <EOL> return SemaInsn . from_buffer_copy ( buf ) <EOL> else : <EOL> return LoadInsn . from_buffer_copy ( buf ) <EOL> else : <EOL> return AluInsn . from_buffer_copy ( buf ) <EOL> def __eq__ ( self , other ) : <EOL> return ( <EOL> self . __class__ == other . __class__ and <EOL> all ( getattr ( self , f ) == getattr ( other , f ) <EOL> for f , _ , _ in self . _fields_ if f != '<STR_LIT>' <EOL> ) ) <EOL> def __ne__ ( self , other ) : <EOL> return not ( self == other ) <EOL> def __repr__ ( self ) : <EOL> return '<STR_LIT>' . format ( <EOL> class_name = self . __class__ . __name__ , <EOL> fields = '<STR_LIT:U+002CU+0020>' . join ( <EOL> f + '<STR_LIT:=>' + hex ( getattr ( self , f ) ) <EOL> for f , _ , _ in reversed ( self . _fields_ ) if f != '<STR_LIT>' <EOL> ) ) <EOL> class AluInsn ( Insn ) : <EOL> _fields_ = [ ( f , c_ulong , n ) for f , n in [ <EOL> ( '<STR_LIT>' , <NUM_LIT:3> ) , ( '<STR_LIT>' , <NUM_LIT:3> ) , ( '<STR_LIT>' , <NUM_LIT:3> ) , ( '<STR_LIT>' , <NUM_LIT:3> ) , ( '<STR_LIT>' , <NUM_LIT:6> ) , <EOL> ( '<STR_LIT>' , <NUM_LIT:6> ) , ( '<STR_LIT>' , <NUM_LIT:5> ) , ( '<STR_LIT>' , <NUM_LIT:3> ) , ( '<STR_LIT>' , <NUM_LIT:6> ) , <EOL> ( '<STR_LIT>' , <NUM_LIT:6> ) , ( '<STR_LIT>' , <NUM_LIT:1> ) , ( '<STR_LIT>' , <NUM_LIT:1> ) , ( '<STR_LIT>' , <NUM_LIT:3> ) , <EOL> ( '<STR_LIT>' , <NUM_LIT:3> ) , ( '<STR_LIT>' , <NUM_LIT:4> ) , ( '<STR_LIT>' , <NUM_LIT:1> ) , ( '<STR_LIT>' , <NUM_LIT:3> ) , ( '<STR_LIT>' , <NUM_LIT:4> ) <EOL> ] ] <EOL> class BranchInsn ( Insn ) : <EOL> _fields_ = [ ( f , c_ulong , n ) for f , n in [ <EOL> ( '<STR_LIT>' , <NUM_LIT:32> ) , ( '<STR_LIT>' , <NUM_LIT:6> ) , ( '<STR_LIT>' , <NUM_LIT:6> ) , ( '<STR_LIT>' , <NUM_LIT:1> ) , <EOL> ( '<STR_LIT>' , <NUM_LIT:5> ) , ( '<STR_LIT>' , <NUM_LIT:1> ) , ( '<STR_LIT>' , <NUM_LIT:1> ) , ( '<STR_LIT>' , <NUM_LIT:4> ) , <EOL> ( '<STR_LIT>' , <NUM_LIT:4> ) , ( '<STR_LIT>' , <NUM_LIT:4> ) <EOL> ] ] <EOL> class LoadInsn ( Insn ) : <EOL> _fields_ = [ ( f , c_ulong , n ) for f , n in [ <EOL> ( '<STR_LIT>' , <NUM_LIT:32> ) , ( '<STR_LIT>' , <NUM_LIT:6> ) , ( '<STR_LIT>' , <NUM_LIT:6> ) , ( '<STR_LIT>' , <NUM_LIT:1> ) , <EOL> ( '<STR_LIT>' , <NUM_LIT:1> ) , ( '<STR_LIT>' , <NUM_LIT:3> ) , ( '<STR_LIT>' , <NUM_LIT:3> ) , ( '<STR_LIT>' , <NUM_LIT:4> ) , ( '<STR_LIT>' , <NUM_LIT:1> ) , <EOL> ( '<STR_LIT>' , <NUM_LIT:3> ) , ( '<STR_LIT>' , <NUM_LIT:4> ) <EOL> ] ] <EOL> class SemaInsn ( Insn ) : <EOL> _fields_ = [ ( f , c_ulong , n ) for f , n in [ <EOL> ( '<STR_LIT>' , <NUM_LIT:4> ) , ( '<STR_LIT>' , <NUM_LIT:1> ) , ( '<STR_LIT>' , <NUM_LIT> ) , ( '<STR_LIT>' , <NUM_LIT:6> ) , <EOL> ( '<STR_LIT>' , <NUM_LIT:6> ) , ( '<STR_LIT>' , <NUM_LIT:1> ) , ( '<STR_LIT>' , <NUM_LIT:1> ) , ( '<STR_LIT>' , <NUM_LIT:3> ) , <EOL> ( '<STR_LIT>' , <NUM_LIT:3> ) , ( '<STR_LIT>' , <NUM_LIT:4> ) , ( '<STR_LIT>' , <NUM_LIT:1> ) , ( '<STR_LIT>' , <NUM_LIT:3> ) , ( '<STR_LIT>' , <NUM_LIT:4> ) <EOL> ] ] <EOL> class Emitter ( object ) : <EOL> '<STR_LIT>' <EOL> def __init__ ( self , asm ) : <EOL> self . asm = asm <EOL> def _encode_write_operands ( self , <EOL> add_dst = REGISTERS [ '<STR_LIT:null>' ] , mul_dst = REGISTERS [ '<STR_LIT:null>' ] ) : <EOL> """<STR_LIT>""" <EOL> assert ( add_dst . unpack_bits == <NUM_LIT:0> ) <EOL> assert ( mul_dst . unpack_bits == <NUM_LIT:0> ) <EOL> if add_dst . pack_bits != <NUM_LIT:0> and mul_dst . pack_bits != <NUM_LIT:0> : <EOL> raise AssembleError ( <EOL> '<STR_LIT>' . format ( <EOL> add_dst , mul_dst ) ) <EOL> pack_bits = add_dst . pack_bits or mul_dst . pack_bits <EOL> if add_dst . spec & _REG_AW and mul_dst . spec & _REG_BW : <EOL> return add_dst . addr , mul_dst . addr , False , pack_bits <EOL> elif mul_dst . spec & _REG_AW and add_dst . spec & _REG_BW : <EOL> return add_dst . addr , mul_dst . addr , True , pack_bits <EOL> raise AssembleError ( <EOL> '<STR_LIT>' . format ( <EOL> add_dst , mul_dst ) ) <EOL> def _encode_read_operands ( self , <EOL> add_a = REGISTERS [ '<STR_LIT>' ] , add_b = REGISTERS [ '<STR_LIT>' ] , <EOL> mul_a = REGISTERS [ '<STR_LIT>' ] , mul_b = REGISTERS [ '<STR_LIT>' ] ) : <EOL> """<STR_LIT>""" <EOL> operands = [ add_a , add_b , mul_a , mul_b ] <EOL> muxes = [ None , None , None , None ] <EOL> unpack_bits = <NUM_LIT:0> <EOL> pm_bit = <NUM_LIT:0> <EOL> raddr_a = None <EOL> raddr_b = None <EOL> small_imm = None <EOL> for opd in operands : <EOL> if not isinstance ( opd , Register ) : <EOL> continue <EOL> if opd . unpack_bits : <EOL> if unpack_bits == <NUM_LIT:0> : <EOL> unpack_bits = opd . unpack_bits <EOL> pm_bit = opd . pm_bit <EOL> elif ( opd . unpack_bits != unpack_bits or opd . pm_bit != pm_bit ) : <EOL> raise AssembleError ( '<STR_LIT>' ) <EOL> for i , opd in enumerate ( operands ) : <EOL> if isinstance ( opd , Register ) and opd . name in ACCUMULATORS : <EOL> muxes [ i ] = _INPUT_MUXES [ opd . name ] <EOL> if all ( m is not None for m in muxes ) : <EOL> null_addr = REGISTERS [ '<STR_LIT:null>' ] . addr <EOL> return [ muxes , null_addr , null_addr , False , unpack_bits , pm_bit ] <EOL> for i , opd in enumerate ( operands ) : <EOL> if muxes [ i ] is not None or not isinstance ( opd , Register ) : <EOL> continue <EOL> if opd . spec & _REG_BR and not ( opd . spec & _REG_AR ) : <EOL> if raddr_b is None : <EOL> raddr_b = opd . addr <EOL> muxes [ i ] = _INPUT_MUXES [ '<STR_LIT:B>' ] <EOL> elif raddr_b == opd . addr : <EOL> muxes [ i ] = _INPUT_MUXES [ '<STR_LIT:B>' ] <EOL> else : <EOL> raise AssembleError ( '<STR_LIT>' ) <EOL> for i , opd in enumerate ( operands ) : <EOL> if muxes [ i ] is not None or isinstance ( opd , Register ) : <EOL> continue <EOL> imm = _SMALL_IMM [ repr ( opd ) ] <EOL> if small_imm is None : <EOL> small_imm = imm <EOL> muxes [ i ] = _INPUT_MUXES [ '<STR_LIT:B>' ] <EOL> elif small_imm == imm : <EOL> muxes [ i ] = _INPUT_MUXES [ '<STR_LIT:B>' ] <EOL> else : <EOL> raise AssembleError ( '<STR_LIT>' ) <EOL> if small_imm is not None and raddr_b is not None : <EOL> raise AssembleError ( <EOL> '<STR_LIT>' <EOL> ) <EOL> if small_imm is not None : <EOL> raddr_b = small_imm <EOL> for i , opd in enumerate ( operands ) : <EOL> if muxes [ i ] is not None : <EOL> continue <EOL> if opd . spec & _REG_AR and not ( opd . spec & _REG_BR ) : <EOL> if raddr_a is None : <EOL> raddr_a = opd . addr <EOL> muxes [ i ] = _INPUT_MUXES [ '<STR_LIT:A>' ] <EOL> elif raddr_a == opd . addr : <EOL> muxes [ i ] = _INPUT_MUXES [ '<STR_LIT:A>' ] <EOL> else : <EOL> raise AssembleError ( '<STR_LIT>' ) <EOL> for i , opd in enumerate ( operands ) : <EOL> if muxes [ i ] is not None : continue <EOL> if not ( opd . spec & ( _REG_AR | _REG_BR ) ) : <EOL> raise AssembleError ( '<STR_LIT>' . format ( opd ) ) <EOL> if raddr_a is None : <EOL> raddr_a = opd . addr <EOL> muxes [ i ] = _INPUT_MUXES [ '<STR_LIT:A>' ] <EOL> elif small_imm is None and raddr_b is None : <EOL> raddr_b = opd . addr <EOL> muxes [ i ] = _INPUT_MUXES [ '<STR_LIT:B>' ] <EOL> else : <EOL> raise AssembleError ( '<STR_LIT>' . format ( opd ) ) <EOL> if raddr_a is None : <EOL> raddr_a = REGISTERS [ '<STR_LIT:null>' ] . addr <EOL> if raddr_b is None : <EOL> raddr_b = REGISTERS [ '<STR_LIT:null>' ] . addr <EOL> use_small_imm = ( small_imm is not None ) <EOL> return [ muxes , raddr_a , raddr_b , use_small_imm , unpack_bits , pm_bit ] <EOL> class AddEmitter ( Emitter ) : <EOL> '<STR_LIT>' <EOL> def _emit ( self , op_add , dst = REGISTERS [ '<STR_LIT:null>' ] , opd1 = REGISTERS [ '<STR_LIT>' ] , <EOL> opd2 = REGISTERS [ '<STR_LIT>' ] , sig = '<STR_LIT>' , set_flags = True , ** kwargs ) : <EOL> muxes , raddr_a , raddr_b , use_imm , unpack , read_pm = self . _encode_read_operands ( opd1 , opd2 ) <EOL> if use_imm : <EOL> if sig != '<STR_LIT>' and sig != '<STR_LIT>' : <EOL> raise AssembleError ( <EOL> '<STR_LIT>' . format ( sig ) ) <EOL> sig = '<STR_LIT>' <EOL> sig_bits = _SIGNAL [ sig ] <EOL> if op_add == _ADD_INSN [ '<STR_LIT>' ] : <EOL> set_flags = False <EOL> waddr_add , waddr_mul , write_swap , pack = self . _encode_write_operands ( dst ) <EOL> pm = <NUM_LIT:0> <EOL> if unpack and pack : <EOL> if read_pm != <NUM_LIT:0> : <EOL> raise AssembleError ( '<STR_LIT>' ) <EOL> pm = read_pm <EOL> elif unpack and not pack : <EOL> pm = read_pm <EOL> elif pack and not unpack : <EOL> pm = <NUM_LIT:0> <EOL> cond_add = _COND [ kwargs . get ( '<STR_LIT>' , '<STR_LIT>' ) ] <EOL> cond_mul = _COND [ '<STR_LIT>' ] <EOL> insn = AluInsn ( <EOL> sig = sig_bits , unpack = unpack , pm = pm , pack = pack , <EOL> sf = set_flags , ws = write_swap , cond_add = cond_add , <EOL> cond_mul = cond_mul , op_add = op_add , op_mul = _MUL_INSN [ '<STR_LIT>' ] , <EOL> waddr_add = waddr_add , waddr_mul = waddr_mul , raddr_a = raddr_a , <EOL> raddr_b = raddr_b , add_a = muxes [ <NUM_LIT:0> ] , add_b = muxes [ <NUM_LIT:1> ] , <EOL> mul_a = muxes [ <NUM_LIT:2> ] , mul_b = muxes [ <NUM_LIT:3> ] <EOL> ) <EOL> self . asm . _emit ( insn ) <EOL> return MulEmitter ( <EOL> self . asm , op_add = op_add , add_dst = dst , add_opd1 = opd1 , <EOL> add_opd2 = opd2 , cond_add = cond_add , sig = sig , set_flags = set_flags , <EOL> increment = False ) <EOL> class MulEmitter ( Emitter ) : <EOL> """<STR_LIT>""" <EOL> def __init__ ( self , asm , op_add = _ADD_INSN [ '<STR_LIT>' ] , add_dst = REGISTERS [ '<STR_LIT:null>' ] , <EOL> add_opd1 = REGISTERS [ '<STR_LIT>' ] , add_opd2 = REGISTERS [ '<STR_LIT>' ] , <EOL> cond_add = _COND [ '<STR_LIT>' ] , sig = '<STR_LIT>' , set_flags = False , <EOL> increment = True ) : <EOL> self . asm = asm <EOL> self . op_add = op_add <EOL> self . add_dst = add_dst <EOL> self . add_opd1 = add_opd1 <EOL> self . add_opd2 = add_opd2 <EOL> self . cond_add = cond_add <EOL> self . sig = sig <EOL> self . set_flags = set_flags <EOL> self . increment = increment <EOL> def _emit ( self , op_mul , mul_dst = REGISTERS [ '<STR_LIT:null>' ] , mul_opd1 = REGISTERS [ '<STR_LIT>' ] , <EOL> mul_opd2 = REGISTERS [ '<STR_LIT>' ] , rotate = <NUM_LIT:0> , pack = '<STR_LIT>' , ** kwargs ) : <EOL> mul_pack = _MUL_PACK [ pack ] <EOL> muxes , raddr_a , raddr_b , use_imm , unpack , read_pm = self . _encode_read_operands ( self . add_opd1 , self . add_opd2 , <EOL> mul_opd1 , mul_opd2 ) <EOL> waddr_add , waddr_mul , write_swap , regA_pack = self . _encode_write_operands ( self . add_dst , mul_dst ) <EOL> if mul_pack and regA_pack : <EOL> raise AssembleError ( '<STR_LIT>' ) <EOL> write_pm = ( mul_pack != <NUM_LIT:0> ) <EOL> pack = mul_pack or regA_pack <EOL> pm = <NUM_LIT:0> <EOL> if unpack and pack : <EOL> if read_pm != write_pm : <EOL> raise AssembleError ( '<STR_LIT>' ) <EOL> pm = read_pm <EOL> elif unpack and not pack : <EOL> pm = read_pm <EOL> elif pack and not unpack : <EOL> pm = write_pm <EOL> sig = kwargs . get ( '<STR_LIT>' , '<STR_LIT>' ) <EOL> if self . sig != '<STR_LIT>' : <EOL> if sig != '<STR_LIT>' : <EOL> raise AssembleError ( '<STR_LIT>' ) <EOL> sig = self . sig <EOL> if use_imm or rotate : <EOL> if sig != '<STR_LIT>' and sig != '<STR_LIT>' : <EOL> raise AssembleError ( <EOL> '<STR_LIT>' . format ( sig ) ) <EOL> sig = '<STR_LIT>' <EOL> sig_bits = _SIGNAL [ sig ] <EOL> if rotate : <EOL> if not ( <NUM_LIT:0> <= muxes [ <NUM_LIT:2> ] and muxes [ <NUM_LIT:2> ] < <NUM_LIT:3> and <NUM_LIT:0> <= muxes [ <NUM_LIT:3> ] and muxes [ <NUM_LIT:3> ] < <NUM_LIT:3> ) : <EOL> raise AssembleError ( '<STR_LIT>' <EOL> '<STR_LIT>' ) <EOL> if rotate == REGISTERS [ '<STR_LIT>' ] : <EOL> raddr_b = <NUM_LIT> <EOL> else : <EOL> raddr_b = <NUM_LIT> + rotate % <NUM_LIT:16> <EOL> cond_add = self . cond_add <EOL> cond_mul = _COND [ kwargs . get ( '<STR_LIT>' , '<STR_LIT>' ) ] <EOL> insn = AluInsn ( <EOL> sig = sig_bits , unpack = unpack , pm = pm , pack = pack , <EOL> sf = self . set_flags , ws = write_swap , cond_add = cond_add , <EOL> cond_mul = cond_mul , op_add = self . op_add , op_mul = op_mul , <EOL> waddr_add = waddr_add , waddr_mul = waddr_mul , raddr_a = raddr_a , <EOL> raddr_b = raddr_b , add_a = muxes [ <NUM_LIT:0> ] , add_b = muxes [ <NUM_LIT:1> ] , <EOL> mul_a = muxes [ <NUM_LIT:2> ] , mul_b = muxes [ <NUM_LIT:3> ] <EOL> ) <EOL> self . asm . _emit ( insn , increment = self . increment ) <EOL> class LoadEmitter ( Emitter ) : <EOL> '<STR_LIT>' <EOL> def _encode_imm ( self , val ) : <EOL> if isinstance ( val , float ) : <EOL> return unpack ( '<STR_LIT:L>' , pack ( '<STR_LIT:f>' , val ) ) [ <NUM_LIT:0> ] , <NUM_LIT:0> <EOL> elif isinstance ( val , numbers . Number ) : <EOL> fmt = '<STR_LIT:l>' if val < <NUM_LIT:0> else '<STR_LIT:L>' <EOL> return unpack ( '<STR_LIT:L>' , pack ( fmt , val ) ) [ <NUM_LIT:0> ] , <NUM_LIT:0> <EOL> elif isinstance ( val , ( list , tuple , numpy . ndarray ) ) : <EOL> return self . _encode_per_element_imm ( list ( val ) ) <EOL> raise AssembleError ( '<STR_LIT>' . format ( val ) ) <EOL> def _encode_per_element_imm ( self , values ) : <EOL> if len ( values ) > <NUM_LIT:16> : <EOL> raise AssembleError ( '<STR_LIT>' . format ( values ) ) <EOL> values . extend ( [ <NUM_LIT:0> ] * ( <NUM_LIT:16> - len ( values ) ) ) <EOL> unsigned = all ( map ( lambda x : x >= <NUM_LIT:0> , values ) ) <EOL> high = <NUM_LIT:0> <EOL> low = <NUM_LIT:0> <EOL> for i in reversed ( range ( <NUM_LIT:16> ) ) : <EOL> high <<= <NUM_LIT:1> <EOL> low <<= <NUM_LIT:1> <EOL> v = values [ i ] <EOL> if ( not unsigned and ( v >= <NUM_LIT:2> or v < - <NUM_LIT:2> ) ) or ( unsigned and v >= <NUM_LIT:4> ) : <EOL> raise AssembleError ( '<STR_LIT>' . format ( <EOL> v , [ '<STR_LIT>' , '<STR_LIT>' ] [ unsigned ] ) ) <EOL> high |= ( v & <NUM_LIT> ) >> <NUM_LIT:1> <EOL> low |= v & <NUM_LIT> <EOL> return ( high << <NUM_LIT:16> ) | low , <NUM_LIT:2> * unsigned + <NUM_LIT:1> <EOL> def _emit ( self , * args , ** kwargs ) : <EOL> """<STR_LIT>""" <EOL> reg1 = args [ <NUM_LIT:0> ] <EOL> if len ( args ) == <NUM_LIT:2> : <EOL> reg2 = REGISTERS [ '<STR_LIT:null>' ] <EOL> imm = args [ <NUM_LIT:1> ] <EOL> else : <EOL> reg2 = args [ <NUM_LIT:1> ] <EOL> imm = args [ <NUM_LIT:2> ] <EOL> waddr_add , waddr_mul , write_swap , pack = self . _encode_write_operands ( reg1 , reg2 ) <EOL> imm , unpack = self . _encode_imm ( imm ) <EOL> cond_add = cond_mul = _COND [ kwargs . get ( '<STR_LIT>' , '<STR_LIT>' ) ] <EOL> set_flags = kwargs . get ( '<STR_LIT>' , False ) <EOL> insn = LoadInsn ( <EOL> sig = <NUM_LIT> , unpack = unpack , pm = <NUM_LIT:0> , pack = pack , cond_add = cond_add , <EOL> cond_mul = cond_mul , sf = set_flags , ws = write_swap , <EOL> waddr_add = waddr_add , waddr_mul = waddr_mul , immediate = imm <EOL> ) <EOL> self . asm . _emit ( insn ) <EOL> class Label ( object ) : <EOL> def __init__ ( self , asm , name ) : <EOL> self . name = name <EOL> self . pinned = True <EOL> class LabelEmitter ( Emitter ) : <EOL> '<STR_LIT>' <EOL> def __getitem__ ( self , name ) : <EOL> label = Label ( self . asm , name ) <EOL> self . asm . _add_label ( label ) <EOL> return label <EOL> def __getattr__ ( self , name ) : <EOL> return self [ name ] <EOL> class BranchEmitter ( Emitter ) : <EOL> '<STR_LIT>' <EOL> def _emit ( self , cond_br , target = None , reg = None , absolute = False , <EOL> link = REGISTERS [ '<STR_LIT:null>' ] ) : <EOL> if target is None : <EOL> imm = <NUM_LIT:0> <EOL> elif isinstance ( target , Label ) : <EOL> target . pinned = False <EOL> self . asm . _add_backpatch_item ( target . name ) <EOL> imm = <NUM_LIT:0> <EOL> elif isinstance ( target , int ) : <EOL> imm = target <EOL> else : <EOL> raise AssembleError ( '<STR_LIT>' . format ( target ) ) <EOL> if reg : <EOL> if ( not ( reg . spec & _REG_AR ) or <EOL> reg . name not in GENERAL_PURPOSE_REGISTERS ) : <EOL> raise AssembleError ( <EOL> '<STR_LIT>' . format ( reg ) <EOL> ) <EOL> assert ( reg . addr < <NUM_LIT:32> ) <EOL> raddr_a = reg . addr <EOL> use_reg = True <EOL> else : <EOL> raddr_a = <NUM_LIT:0> <EOL> use_reg = False <EOL> waddr_add , waddr_mul , write_swap , pack = self . _encode_write_operands ( link ) <EOL> if pack : <EOL> raise AssembleError ( '<STR_LIT>' ) <EOL> insn = BranchInsn ( <EOL> sig = <NUM_LIT> , cond_br = cond_br , rel = not absolute , reg = use_reg , <EOL> raddr_a = raddr_a , ws = write_swap , waddr_add = waddr_add , <EOL> waddr_mul = waddr_mul , immediate = imm <EOL> ) <EOL> self . asm . _emit ( insn ) <EOL> class SemaEmitter ( Emitter ) : <EOL> '<STR_LIT>' <EOL> def _emit ( self , sa , sema_id ) : <EOL> if not ( <NUM_LIT:0> <= sema_id and sema_id <= <NUM_LIT:15> ) : <EOL> raise AssembleError ( '<STR_LIT>' ) <EOL> null_addr = REGISTERS [ '<STR_LIT:null>' ] . addr <EOL> insn = SemaInsn ( <EOL> sig = <NUM_LIT> , unpack = <NUM_LIT:4> , pm = <NUM_LIT:0> , pack = <NUM_LIT:0> , cond_add = <NUM_LIT:1> , cond_mul = <NUM_LIT:1> , sf = <NUM_LIT:0> , <EOL> ws = <NUM_LIT:0> , waddr_add = null_addr , waddr_mul = null_addr , sa = sa , <EOL> semaphore = sema_id ) <EOL> self . asm . _emit ( insn ) <EOL> class Assembler ( object ) : <EOL> '<STR_LIT>' <EOL> _REGISTERS = REGISTERS <EOL> def __init__ ( self ) : <EOL> self . _instructions = [ ] <EOL> self . _program_counter = <NUM_LIT:0> <EOL> self . _labels = [ ] <EOL> self . _backpatch_list = [ ] <EOL> self . _add = AddEmitter ( self ) <EOL> self . _mul = MulEmitter ( self ) <EOL> self . _load = LoadEmitter ( self ) <EOL> self . _branch = BranchEmitter ( self ) <EOL> self . _sema = SemaEmitter ( self ) <EOL> self . L = LabelEmitter ( self ) <EOL> def _emit ( self , insn , increment = True ) : <EOL> """<STR_LIT>""" <EOL> if increment : <EOL> self . _instructions . append ( insn ) <EOL> self . _program_counter += <NUM_LIT:8> <EOL> else : <EOL> self . _instructions [ - <NUM_LIT:1> ] = insn <EOL> def _emit_add ( self , * args , ** kwargs ) : <EOL> return self . _add . _emit ( * args , ** kwargs ) <EOL> def _emit_mul ( self , * args , ** kwargs ) : <EOL> return self . _mul . _emit ( * args , ** kwargs ) <EOL> def _emit_load ( self , * args , ** kwargs ) : <EOL> return self . _load . _emit ( * args , ** kwargs ) <EOL> def _emit_branch ( self , * args , ** kwargs ) : <EOL> return self . _branch . _emit ( * args , ** kwargs ) <EOL> def _emit_sema ( self , * args , ** kwargs ) : <EOL> return self . _sema . _emit ( * args , ** kwargs ) <EOL> def _add_label ( self , label ) : <EOL> self . _labels . append ( ( label , self . _program_counter ) ) <EOL> def _fix_labels ( self ) : <EOL> new_labels = [ ] <EOL> label_dict = { } <EOL> for label , pc in self . _labels : <EOL> if not label . pinned : <EOL> continue <EOL> if label . name in label_dict : <EOL> raise AssembleError ( '<STR_LIT>' . format ( label . name ) ) <EOL> label_dict [ label . name ] = pc <EOL> new_labels . append ( ( label , pc ) ) <EOL> self . _labels = new_labels <EOL> return label_dict <EOL> def _backpatch ( self ) : <EOL> '<STR_LIT>' <EOL> labels = self . _fix_labels ( ) <EOL> for i , label in self . _backpatch_list : <EOL> if label not in labels : <EOL> raise AssembleError ( '<STR_LIT>' . format ( label ) ) <EOL> insn = self . _instructions [ i ] <EOL> assert ( isinstance ( insn , BranchInsn ) ) <EOL> assert ( insn . rel ) <EOL> insn . immediate = labels [ label ] - <NUM_LIT:8> * ( i + <NUM_LIT:4> ) <EOL> self . _backpatch_list = [ ] <EOL> def _add_backpatch_item ( self , target ) : <EOL> self . _backpatch_list . append ( ( len ( self . _instructions ) , target ) ) <EOL> def _get_code ( self ) : <EOL> '<STR_LIT>' <EOL> self . _backpatch ( ) <EOL> return b'<STR_LIT>' . join ( insn . to_bytes ( ) for insn in self . _instructions ) <EOL> def alias ( f ) : <EOL> setattr ( Assembler , f . __name__ , f ) <EOL> for name , code in _ADD_INSN . items ( ) : <EOL> setattr ( Assembler , name , _partialmethod ( Assembler . _emit_add , code ) ) <EOL> for name , code in _MUL_INSN . items ( ) : <EOL> if name not in _ADD_INSN : <EOL> setattr ( Assembler , name , _partialmethod ( Assembler . _emit_mul , code ) ) <EOL> setattr ( MulEmitter , name , _partialmethod ( MulEmitter . _emit , code ) ) <EOL> for name , code in _BRANCH_INSN . items ( ) : <EOL> setattr ( Assembler , name , _partialmethod ( Assembler . _emit_branch , code ) ) <EOL> Assembler . ldi = Assembler . _emit_load <EOL> @ alias <EOL> def rotate ( asm , dst , src , shift , ** kwargs ) : <EOL> return asm . v8min ( dst , src , src , rotate = shift , ** kwargs ) <EOL> def mul_rotate ( self , dst , src , shift , ** kwargs ) : <EOL> return self . v8min ( dst , src , src , rotate = shift , ** kwargs ) <EOL> MulEmitter . rotate = mul_rotate <EOL> @ alias <EOL> def mov ( asm , dst , src , ** kwargs ) : <EOL> set_flags = kwargs . pop ( '<STR_LIT>' , False ) <EOL> return asm . bor ( dst , src , src , set_flags = set_flags , ** kwargs ) <EOL> def mul_mov ( self , dst , src , ** kwargs ) : <EOL> return self . v8min ( dst , src , src , ** kwargs ) <EOL> MulEmitter . mov = mul_mov <EOL> @ alias <EOL> def mutex_acquire ( asm ) : <EOL> return asm . mov ( REGISTERS [ '<STR_LIT:null>' ] , REGISTERS [ '<STR_LIT>' ] ) <EOL> @ alias <EOL> def mutex_release ( asm ) : <EOL> return asm . mov ( REGISTERS [ '<STR_LIT>' ] , REGISTERS [ '<STR_LIT:null>' ] ) <EOL> @ alias <EOL> def setup_vpm_read ( asm , nrows , mode = '<STR_LIT>' , Y = <NUM_LIT:0> , stride = <NUM_LIT:1> , <EOL> ** kwargs ) : <EOL> modes = mode . split ( ) <EOL> size = { '<STR_LIT>' : <NUM_LIT:0> , '<STR_LIT>' : <NUM_LIT:1> , '<STR_LIT>' : <NUM_LIT:2> } [ modes . pop ( <NUM_LIT:0> ) ] <EOL> laned = { '<STR_LIT>' : <NUM_LIT:0> , '<STR_LIT>' : <NUM_LIT:1> } [ modes . pop ( <NUM_LIT:0> ) ] if size != <NUM_LIT:2> else <NUM_LIT:0> <EOL> horizontal = { '<STR_LIT>' : <NUM_LIT:0> , '<STR_LIT>' : <NUM_LIT:1> } [ modes . pop ( <NUM_LIT:0> ) ] <EOL> if horizontal : <EOL> addr = ( <EOL> Y << <NUM_LIT:2> | kwargs . get ( '<STR_LIT:B>' , <NUM_LIT:0> ) if size == <NUM_LIT:0> else <EOL> Y << <NUM_LIT:1> | kwargs . get ( '<STR_LIT:H>' , <NUM_LIT:0> ) if size == <NUM_LIT:1> else <EOL> Y <EOL> ) <EOL> else : <EOL> X = kwargs [ '<STR_LIT:X>' ] <EOL> addr = ( <EOL> ( Y & <NUM_LIT> ) << <NUM_LIT:2> | X << <NUM_LIT:2> | kwargs . get ( '<STR_LIT:B>' , <NUM_LIT:0> ) if size == <NUM_LIT:0> else <EOL> ( Y & <NUM_LIT> ) << <NUM_LIT:1> | X << <NUM_LIT:1> | kwargs . get ( '<STR_LIT:H>' , <NUM_LIT:0> ) if size == <NUM_LIT:1> else <EOL> ( Y & <NUM_LIT> ) | X <EOL> ) <EOL> asm . ldi ( REGISTERS [ '<STR_LIT>' ] , <EOL> ( nrows & <NUM_LIT> ) << <NUM_LIT:20> | stride << <NUM_LIT:12> | horizontal << <NUM_LIT:11> | laned << <NUM_LIT:10> | size << <NUM_LIT:8> | addr ) <EOL> @ alias <EOL> def setup_vpm_write ( asm , mode = '<STR_LIT>' , stride = <NUM_LIT:1> , Y = <NUM_LIT:0> , ** kwargs ) : <EOL> modes = mode . split ( ) <EOL> size = { '<STR_LIT>' : <NUM_LIT:0> , '<STR_LIT>' : <NUM_LIT:1> , '<STR_LIT>' : <NUM_LIT:2> } [ modes . pop ( <NUM_LIT:0> ) ] <EOL> laned = { '<STR_LIT>' : <NUM_LIT:0> , '<STR_LIT>' : <NUM_LIT:1> } [ modes . pop ( <NUM_LIT:0> ) ] if size != <NUM_LIT:2> else <NUM_LIT:0> <EOL> horizontal = { '<STR_LIT>' : <NUM_LIT:0> , '<STR_LIT>' : <NUM_LIT:1> } [ modes . pop ( <NUM_LIT:0> ) ] <EOL> if horizontal : <EOL> addr = ( <EOL> Y << <NUM_LIT:2> | kwargs . get ( '<STR_LIT:B>' , <NUM_LIT:0> ) if size == <NUM_LIT:0> else <EOL> Y << <NUM_LIT:1> | kwargs . get ( '<STR_LIT:H>' , <NUM_LIT:0> ) if size == <NUM_LIT:1> else <EOL> Y <EOL> ) <EOL> else : <EOL> X = kwargs . get ( '<STR_LIT:X>' , <NUM_LIT:0> ) <EOL> addr = ( <EOL> ( Y & <NUM_LIT> ) << <NUM_LIT:2> | X << <NUM_LIT:2> | kwargs . get ( '<STR_LIT:B>' , <NUM_LIT:0> ) if size == <NUM_LIT:0> else <EOL> ( Y & <NUM_LIT> ) << <NUM_LIT:1> | X << <NUM_LIT:1> | kwargs . get ( '<STR_LIT:H>' , <NUM_LIT:0> ) if size == <NUM_LIT:1> else <EOL> ( Y & <NUM_LIT> ) | X <EOL> ) <EOL> asm . ldi ( REGISTERS [ '<STR_LIT>' ] , <EOL> stride << <NUM_LIT:12> | horizontal << <NUM_LIT:11> | laned << <NUM_LIT:10> | size << <NUM_LIT:8> | addr ) <EOL> @ alias <EOL> def setup_dma_load_stride ( asm , val , tmp_reg = REGISTERS [ '<STR_LIT>' ] ) : <EOL> if not isinstance ( val , int ) and val . name == tmp_reg . name : <EOL> raise AssembleError ( '<STR_LIT>' <EOL> . format ( tmp_reg . name ) ) <EOL> if isinstance ( val , int ) : <EOL> return asm . ldi ( REGISTERS [ '<STR_LIT>' ] , ( <NUM_LIT:9> << <NUM_LIT> ) | val ) <EOL> else : <EOL> asm . ldi ( tmp_reg , <NUM_LIT:9> << <NUM_LIT> ) <EOL> return asm . bor ( REGISTERS [ '<STR_LIT>' ] , tmp_reg , val ) <EOL> @ alias <EOL> def setup_dma_load ( asm , nrows = <NUM_LIT:1> , ncols = <NUM_LIT:16> , mode = '<STR_LIT>' , Y = <NUM_LIT:0> , X = <NUM_LIT:0> , <EOL> offset = <NUM_LIT:0> , vpitch = <NUM_LIT:1> , mpitch = <NUM_LIT:3> ) : <EOL> modes = mode . split ( ) <EOL> modew = ( <EOL> <NUM_LIT> | offset if modes [ <NUM_LIT:0> ] == '<STR_LIT>' else <EOL> <NUM_LIT> | offset if modes [ <NUM_LIT:0> ] == '<STR_LIT>' else <EOL> <NUM_LIT:0> <EOL> ) <EOL> vertical = { '<STR_LIT>' : <NUM_LIT:0> , '<STR_LIT>' : <NUM_LIT:1> } [ modes [ <NUM_LIT:1> ] ] <EOL> asm . ldi ( REGISTERS [ '<STR_LIT>' ] , <EOL> <NUM_LIT> | modew << <NUM_LIT> | mpitch << <NUM_LIT> | ( ncols & <NUM_LIT> ) << <NUM_LIT:20> | ( nrows & <NUM_LIT> ) << <NUM_LIT:16> | <EOL> vpitch << <NUM_LIT:12> | vertical << <NUM_LIT:11> | Y << <NUM_LIT:4> | X ) <EOL> @ alias <EOL> def start_dma_load ( asm , reg , rot = <NUM_LIT:0> ) : <EOL> if rot == <NUM_LIT:0> : <EOL> return asm . mov ( REGISTERS [ '<STR_LIT>' ] , reg ) <EOL> else : <EOL> return asm . rotate ( REGISTERS [ '<STR_LIT>' ] , reg , rot ) <EOL> @ alias <EOL> def wait_dma_load ( asm ) : <EOL> return asm . mov ( REGISTERS [ '<STR_LIT:null>' ] , REGISTERS [ '<STR_LIT>' ] ) <EOL> @ alias <EOL> def setup_dma_store ( asm , nrows = <NUM_LIT:1> , ncols = <NUM_LIT:16> , mode = '<STR_LIT>' , Y = <NUM_LIT:0> , X = <NUM_LIT:0> , <EOL> offset = <NUM_LIT:0> ) : <EOL> modes = mode . split ( ) <EOL> modew = ( <EOL> <NUM_LIT> | offset if modes [ <NUM_LIT:0> ] == '<STR_LIT>' else <EOL> <NUM_LIT> | offset if modes [ <NUM_LIT:0> ] == '<STR_LIT>' else <EOL> <NUM_LIT:0> <EOL> ) <EOL> horizontal = { '<STR_LIT>' : <NUM_LIT:1> , '<STR_LIT>' : <NUM_LIT:0> } [ modes [ <NUM_LIT:1> ] ] <EOL> asm . ldi ( REGISTERS [ '<STR_LIT>' ] , <EOL> <NUM_LIT> | ( nrows & <NUM_LIT> ) << <NUM_LIT> | ( ncols & <NUM_LIT> ) << <NUM_LIT:16> | horizontal << <NUM_LIT> | Y << <NUM_LIT:7> | <EOL> X << <NUM_LIT:3> | modew ) <EOL> @ alias <EOL> def setup_dma_store_stride ( asm , val , blockmode = False , tmp_reg = REGISTERS [ '<STR_LIT>' ] ) : <EOL> if not isinstance ( val , int ) and val . name == tmp_reg . name : <EOL> raise AssembleError ( '<STR_LIT>' <EOL> . format ( tmp_reg . name ) ) <EOL> if isinstance ( val , int ) : <EOL> asm . ldi ( REGISTERS [ '<STR_LIT>' ] , ( <NUM_LIT:3> << <NUM_LIT:30> ) | ( blockmode << <NUM_LIT:16> ) | val ) <EOL> else : <EOL> asm . ldi ( tmp_reg , ( <NUM_LIT:3> << <NUM_LIT:30> ) | ( blockmode << <NUM_LIT:16> ) ) <EOL> asm . bor ( REGISTERS [ '<STR_LIT>' ] , tmp_reg , val ) <EOL> @ alias <EOL> def start_dma_store ( asm , reg , rot = <NUM_LIT:0> ) : <EOL> if rot == <NUM_LIT:0> : <EOL> return asm . mov ( REGISTERS [ '<STR_LIT>' ] , reg ) <EOL> else : <EOL> return asm . rotate ( REGISTERS [ '<STR_LIT>' ] , reg , rot ) <EOL> @ alias <EOL> def wait_dma_store ( asm ) : <EOL> return asm . mov ( REGISTERS [ '<STR_LIT:null>' ] , REGISTERS [ '<STR_LIT>' ] ) <EOL> @ alias <EOL> def interrupt ( asm ) : <EOL> return asm . mov ( REGISTERS [ '<STR_LIT>' ] , <NUM_LIT:1> ) <EOL> @ alias <EOL> def exit ( asm , interrupt = True ) : <EOL> if interrupt : <EOL> asm . interrupt ( ) <EOL> asm . mov ( <EOL> REGISTERS [ '<STR_LIT>' ] , REGISTERS [ '<STR_LIT>' ] , sig = '<STR_LIT>' <EOL> ) . mov ( <EOL> REGISTERS [ '<STR_LIT>' ] , REGISTERS [ '<STR_LIT>' ] <EOL> ) <EOL> asm . nop ( ) <EOL> asm . nop ( ) <EOL> @ alias <EOL> def sema_up ( asm , sema_id ) : <EOL> asm . _emit_sema ( <NUM_LIT:0> , sema_id ) <EOL> @ alias <EOL> def sema_down ( asm , sema_id ) : <EOL> asm . _emit_sema ( <NUM_LIT:1> , sema_id ) <EOL> REGISTER_ALIASES = '<STR_LIT:\n>' . join ( <EOL> '<STR_LIT>' . format ( reg ) <EOL> for reg in Assembler . _REGISTERS <EOL> ) <EOL> INSTRUCTION_ALIASES = '<STR_LIT:\n>' . join ( <EOL> '<STR_LIT>' . format ( f ) <EOL> for f in dir ( Assembler ) <EOL> if f [ <NUM_LIT:0> ] != '<STR_LIT:_>' <EOL> ) <EOL> SETUP_ASM_ALIASES = ast . parse ( """<STR_LIT>""" . format ( <EOL> register_aliases = REGISTER_ALIASES , <EOL> instruction_aliases = INSTRUCTION_ALIASES <EOL> ) ) <EOL> def qpu ( f ) : <EOL> """<STR_LIT>""" <EOL> args , _ , _ , _ = inspect . getargspec ( f ) <EOL> if '<STR_LIT>' not in args : <EOL> raise AssembleError ( '<STR_LIT>' ) <EOL> tree = ast . parse ( inspect . getsource ( f ) ) <EOL> fundef = tree . body [ <NUM_LIT:0> ] <EOL> fundef . body = SETUP_ASM_ALIASES . body + fundef . body <EOL> fundef . decorator_list = [ ] <EOL> code = compile ( tree , '<STR_LIT>' , '<STR_LIT>' ) <EOL> scope = { } <EOL> exec ( code , f . __globals__ , scope ) <EOL> return scope [ f . __name__ ] <EOL> def assemble ( f , * args , ** kwargs ) : <EOL> '<STR_LIT>' <EOL> asm = Assembler ( ) <EOL> f ( asm , * args , ** kwargs ) <EOL> return asm . _get_code ( ) </s>
