<s> from migen . build . generic_platform import * <EOL> from migen . build . xilinx import XilinxPlatform <EOL> _ios = [ <EOL> ( "<STR_LIT>" , <NUM_LIT:0> , Pins ( "<STR_LIT>" ) , IOStandard ( "<STR_LIT>" ) ) , <EOL> ( "<STR_LIT>" , <NUM_LIT:0> , Pins ( "<STR_LIT>" ) , IOStandard ( "<STR_LIT>" ) ) , <EOL> ( "<STR_LIT>" , <NUM_LIT:0> , Pins ( "<STR_LIT>" ) , IOStandard ( "<STR_LIT>" ) ) , <EOL> ( "<STR_LIT>" , <NUM_LIT:0> , Pins ( "<STR_LIT>" ) , IOStandard ( "<STR_LIT>" ) ) , <EOL> ( "<STR_LIT>" , <NUM_LIT:0> , <EOL> Subsignal ( "<STR_LIT>" , Pins ( "<STR_LIT>" ) ) , <EOL> Subsignal ( "<STR_LIT>" , Pins ( "<STR_LIT>" ) ) , <EOL> Subsignal ( "<STR_LIT>" , Pins ( "<STR_LIT>" ) ) , <EOL> Subsignal ( "<STR_LIT>" , Pins ( "<STR_LIT>" ) ) , <EOL> Subsignal ( "<STR_LIT>" , Pins ( "<STR_LIT>" ) ) , <EOL> Subsignal ( "<STR_LIT>" , Pins ( "<STR_LIT>" ) ) , <EOL> Subsignal ( "<STR_LIT>" , Pins ( "<STR_LIT>" ) ) , <EOL> Subsignal ( "<STR_LIT>" , Pins ( "<STR_LIT>" ) ) , <EOL> Subsignal ( "<STR_LIT>" , Pins ( "<STR_LIT>" ) ) , <EOL> Subsignal ( "<STR_LIT>" , Pins ( "<STR_LIT>" ) ) , <EOL> Subsignal ( "<STR_LIT>" , Pins ( "<STR_LIT>" ) ) , <EOL> IOStandard ( "<STR_LIT>" ) <EOL> ) <EOL> ] <EOL> _connectors = [ <EOL> ( "<STR_LIT>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" , <EOL> "<STR_LIT:None>" ) <EOL> ] <EOL> class Platform ( XilinxPlatform ) : <EOL> default_clk_name = "<STR_LIT>" <EOL> default_clk_period = <NUM_LIT> <EOL> def __init__ ( self ) : <EOL> XilinxPlatform . __init__ ( self , "<STR_LIT>" , _ios , _connectors ) </s>
