<s> from __future__ import absolute_import <EOL> from __future__ import print_function <EOL> import sys <EOL> import os <EOL> sys . path . insert ( <NUM_LIT:0> , os . path . dirname ( os . path . dirname ( os . path . dirname ( os . path . dirname ( os . path . abspath ( __file__ ) ) ) ) ) ) <EOL> from veriloggen import * <EOL> prim_mux = None <EOL> def mkPrimMux ( ) : <EOL> global prim_mux <EOL> if prim_mux is not None : <EOL> return prim_mux <EOL> m = Module ( '<STR_LIT>' ) <EOL> width = m . Parameter ( '<STR_LIT>' , <NUM_LIT:1> ) <EOL> sel = m . Input ( '<STR_LIT>' ) <EOL> ina = m . Input ( '<STR_LIT>' , width = width ) <EOL> inb = m . Input ( '<STR_LIT>' , width = width ) <EOL> out = m . Output ( '<STR_LIT>' , width = width ) <EOL> m . Assign ( out ( Mux ( sel , ina , inb ) ) ) <EOL> prim_mux = m <EOL> return m <EOL> def Pmux ( m , cond , true_value , false_value , width = <NUM_LIT:32> ) : <EOL> mux = mkPrimMux ( ) <EOL> sel = m . TmpWire ( ) <EOL> ina = m . TmpWire ( width = width ) <EOL> inb = m . TmpWire ( width = width ) <EOL> out = m . TmpWire ( width = width ) <EOL> m . Assign ( sel ( cond ) ) <EOL> m . Assign ( ina ( true_value ) ) <EOL> m . Assign ( inb ( false_value ) ) <EOL> m . Instance ( mux , '<STR_LIT:_>' . join ( [ '<STR_LIT>' , mux . name , out . name ] ) , <EOL> params = [ ( '<STR_LIT>' , width ) ] , <EOL> ports = [ sel , ina , inb , out ] ) <EOL> return out <EOL> def mkLed ( ) : <EOL> m = Module ( '<STR_LIT>' ) <EOL> width = m . Parameter ( '<STR_LIT>' , <NUM_LIT:8> ) <EOL> clk = m . Input ( '<STR_LIT>' ) <EOL> rst = m . Input ( '<STR_LIT>' ) <EOL> led = m . OutputReg ( '<STR_LIT>' , width ) <EOL> count = m . Reg ( '<STR_LIT:count>' , <NUM_LIT:32> ) <EOL> m . Always ( Posedge ( clk ) ) ( <EOL> If ( rst ) ( <EOL> count ( <NUM_LIT:0> ) <EOL> ) . Else ( <EOL> count ( Pmux ( m , count == <NUM_LIT> , <NUM_LIT:0> , count + <NUM_LIT:1> , width = <NUM_LIT:32> ) ) <EOL> ) ) <EOL> m . Always ( Posedge ( clk ) ) ( <EOL> If ( rst ) ( <EOL> led ( <NUM_LIT:0> ) <EOL> ) . Else ( <EOL> led ( Pmux ( m , count == <NUM_LIT> - <NUM_LIT:1> , led + <NUM_LIT:1> , led , width = width ) ) <EOL> ) ) <EOL> return m <EOL> if __name__ == '<STR_LIT:__main__>' : <EOL> led = mkLed ( ) <EOL> verilog = led . to_verilog ( '<STR_LIT>' ) <EOL> print ( verilog ) </s>
