<s> import pytest <EOL> import functools <EOL> from verilator_sim import TranslationTool <EOL> from exceptions import VerilogTranslationError , VerilatorCompileError <EOL> from . . simulation . SimulationTool_seq_test import * <EOL> from . . simulation . SimulationTool_comb_test import * <EOL> from . . simulation . SimulationTool_mix_test import * <EOL> from . . simulation . SimulationTool_transl_test import * <EOL> pytestmark = requires_verilator <EOL> [ pytest . mark . xfail ( reason = x , raises = z ) ( y ) for x , y , z in [ <EOL> ( '<STR_LIT>' <EOL> '<STR_LIT>' <EOL> '<STR_LIT>' , <EOL> test_ListOfMixedUseWires , None ) , <EOL> ( '<STR_LIT>' , <EOL> test_ListOfSubmodPortBundles , VerilatorCompileError ) , <EOL> ( '<STR_LIT>' , <EOL> test_SliceTempWriteCheck , VerilogTranslationError ) , <EOL> ( '<STR_LIT>' , <EOL> test_translation_slices03 , VerilogTranslationError ) , <EOL> ( '<STR_LIT>' , <EOL> test_translation_slices04 , VerilogTranslationError ) , <EOL> ( '<STR_LIT>' , <EOL> test_translation_slices11 , VerilogTranslationError ) , <EOL> ( '<STR_LIT>' , <EOL> test_translation_slices13 , VerilogTranslationError ) , <EOL> ( '<STR_LIT>' , <EOL> test_translation_slices14 , None ) , <EOL> ( '<STR_LIT>' , <EOL> test_translation_slices15 , VerilogTranslationError ) , <EOL> ( '<STR_LIT>' , <EOL> test_translation_bad_decorator , None ) , <EOL> ( '<STR_LIT>' , <EOL> test_translation_loopvar_port_name_conflict , VerilatorCompileError ) , <EOL> ( '<STR_LIT>' , <EOL> test_translation_inf_func_not_int , VerilogTranslationError ) , <EOL> ( '<STR_LIT>' , <EOL> test_translation_list_slice_temp , Exception ) , <EOL> ( '<STR_LIT>' , <EOL> test_translation_multiple_lhs_tuple , VerilogTranslationError ) , <EOL> ( '<STR_LIT>' , <EOL> test_translation_multiple_lhs_targets , VerilogTranslationError ) , <EOL> ( '<STR_LIT>' , <EOL> test_translation_multiple_decorators , VerilogTranslationError ) , <EOL> ( '<STR_LIT>' , <EOL> test_translation_for_loop_enumerate , VerilogTranslationError ) , <EOL> ( '<STR_LIT>' , <EOL> test_translation_bad_comparison , VerilogTranslationError ) , <EOL> ( '<STR_LIT>' , <EOL> test_translation_list_slice_step , VerilogTranslationError ) , <EOL> ( '<STR_LIT>' , <EOL> test_translation_unsupported_func , VerilogTranslationError ) , <EOL> ( '<STR_LIT>' , <EOL> test_translation_func_not_int , VerilogTranslationError ) , <EOL> ( '<STR_LIT>' , <EOL> test_translation_iter_unsupported_step , VerilogTranslationError ) , <EOL> ( '<STR_LIT>' , <EOL> test_translation_keyword_args , VerilogTranslationError ) , <EOL> ( '<STR_LIT>' , <EOL> test_translation_issue_123 , VerilogTranslationError ) , <EOL> ] ] <EOL> [ pytest . mark . skipif ( True , reason = x ) ( y ) for x , y in [ <EOL> ( '<STR_LIT>' , <EOL> test_RaiseException , ) , <EOL> ( '<STR_LIT>' , <EOL> test_ValueInSequentialBlock , ) , <EOL> ( '<STR_LIT>' , <EOL> test_MissingNextInSequentialBlock , ) , <EOL> ( '<STR_LIT>' , <EOL> test_MissingListNextInSequentialBlock , ) , <EOL> ( '<STR_LIT>' , <EOL> test_NextInCombinationalBlock , ) , <EOL> ( '<STR_LIT>' , <EOL> test_MissingValueInCombinationalBlock , ) , <EOL> ( '<STR_LIT>' , <EOL> test_MissingListValueInCombinationalBlock , ) , <EOL> ] ] <EOL> def local_setup_sim ( model ) : <EOL> model = TranslationTool ( model ) <EOL> model . elaborate ( ) <EOL> sim = SimulationTool ( model ) <EOL> return model , sim </s>
