<s> import smbus <EOL> pass <EOL> pass <EOL> class PyComms : <EOL> def __init__ ( self , address , bus = smbus . SMBus ( <NUM_LIT:0> ) ) : <EOL> self . address = address <EOL> self . bus = bus <EOL> def reverseByteOrder ( self , data ) : <EOL> dstr = hex ( data ) [ <NUM_LIT:2> : ] . replace ( '<STR_LIT:L>' , '<STR_LIT>' ) <EOL> byteCount = len ( dstr [ : : <NUM_LIT:2> ] ) <EOL> val = <NUM_LIT:0> <EOL> for i , n in enumerate ( range ( byteCount ) ) : <EOL> d = data & <NUM_LIT> <EOL> val |= ( d << ( <NUM_LIT:8> * ( byteCount - i - <NUM_LIT:1> ) ) ) <EOL> data >>= <NUM_LIT:8> <EOL> return val <EOL> def readBit ( self , reg , bitNum ) : <EOL> b = self . readU8 ( reg ) <EOL> data = b & ( <NUM_LIT:1> << bitNum ) <EOL> return data <EOL> def writeBit ( self , reg , bitNum , data ) : <EOL> b = self . readU8 ( reg ) <EOL> if data != <NUM_LIT:0> : <EOL> b = ( b | ( <NUM_LIT:1> << bitNum ) ) <EOL> else : <EOL> b = ( b & ~ ( <NUM_LIT:1> << bitNum ) ) <EOL> return self . write8 ( reg , b ) <EOL> def readBits ( self , reg , bitStart , length ) : <EOL> b = self . readU8 ( reg ) <EOL> mask = ( ( <NUM_LIT:1> << length ) - <NUM_LIT:1> ) << ( bitStart - length + <NUM_LIT:1> ) <EOL> b &= mask <EOL> b >>= ( bitStart - length + <NUM_LIT:1> ) <EOL> return b <EOL> def writeBits ( self , reg , bitStart , length , data ) : <EOL> b = self . readU8 ( reg ) <EOL> mask = ( ( <NUM_LIT:1> << length ) - <NUM_LIT:1> ) << ( bitStart - length + <NUM_LIT:1> ) <EOL> data <<= ( bitStart - length + <NUM_LIT:1> ) <EOL> data &= mask <EOL> b &= ~ ( mask ) <EOL> b |= data <EOL> return self . write8 ( reg , b ) <EOL> def readBytes ( self , reg , length ) : <EOL> output = [ ] <EOL> i = <NUM_LIT:0> <EOL> while i < length : <EOL> output . append ( self . readU8 ( reg ) ) <EOL> i += <NUM_LIT:1> <EOL> return output <EOL> def readBytesListU ( self , reg , length ) : <EOL> output = [ ] <EOL> i = <NUM_LIT:0> <EOL> while i < length : <EOL> output . append ( self . readU8 ( reg + i ) ) <EOL> i += <NUM_LIT:1> <EOL> return output <EOL> def readBytesListS ( self , reg , length ) : <EOL> output = [ ] <EOL> i = <NUM_LIT:0> <EOL> while i < length : <EOL> output . append ( self . readS8 ( reg + i ) ) <EOL> i += <NUM_LIT:1> <EOL> return output <EOL> def writeList ( self , reg , list ) : <EOL> try : <EOL> self . bus . write_i2c_block_data ( self . address , reg , list ) <EOL> except ( IOError ) : <EOL> print ( "<STR_LIT>" % self . address ) <EOL> return - <NUM_LIT:1> <EOL> def write8 ( self , reg , value ) : <EOL> try : <EOL> self . bus . write_byte_data ( self . address , reg , value ) <EOL> except ( IOError ) : <EOL> print ( "<STR_LIT>" % self . address ) <EOL> return - <NUM_LIT:1> <EOL> def readU8 ( self , reg ) : <EOL> try : <EOL> result = self . bus . read_byte_data ( self . address , reg ) <EOL> return result <EOL> except ( IOError ) : <EOL> print ( "<STR_LIT>" % self . address ) <EOL> return - <NUM_LIT:1> <EOL> def readS8 ( self , reg ) : <EOL> try : <EOL> result = self . bus . read_byte_data ( self . address , reg ) <EOL> if result > <NUM_LIT> : <EOL> return result - <NUM_LIT> <EOL> else : <EOL> return result <EOL> except ( IOError ) : <EOL> print ( "<STR_LIT>" % self . address ) <EOL> return - <NUM_LIT:1> <EOL> def readU16 ( self , reg ) : <EOL> try : <EOL> hibyte = self . bus . read_byte_data ( self . address , reg ) <EOL> result = ( hibyte << <NUM_LIT:8> ) + self . bus . read_byte_data ( self . address , reg + <NUM_LIT:1> ) <EOL> return result <EOL> except ( IOError ) : <EOL> print ( "<STR_LIT>" % self . address ) <EOL> return - <NUM_LIT:1> <EOL> def readS16 ( self , reg ) : <EOL> try : <EOL> hibyte = self . bus . read_byte_data ( self . address , reg ) <EOL> if hibyte > <NUM_LIT> : <EOL> hibyte -= <NUM_LIT> <EOL> result = ( hibyte << <NUM_LIT:8> ) + self . bus . read_byte_data ( self . address , reg + <NUM_LIT:1> ) <EOL> return result <EOL> except ( IOError ) : <EOL> print ( "<STR_LIT>" % self . address ) <EOL> return - <NUM_LIT:1> </s>
