<s> from __future__ import absolute_import <EOL> from __future__ import print_function <EOL> import sys <EOL> import os <EOL> sys . path . insert ( <NUM_LIT:0> , os . path . dirname ( os . path . dirname ( os . path . dirname ( os . path . dirname ( os . path . dirname ( os . path . abspath ( __file__ ) ) ) ) ) ) ) <EOL> from veriloggen import * <EOL> def mkLed ( ) : <EOL> m = Module ( '<STR_LIT>' ) <EOL> width = m . Parameter ( '<STR_LIT>' , <NUM_LIT:8> ) <EOL> clk = m . Input ( '<STR_LIT>' ) <EOL> rst = m . Input ( '<STR_LIT>' ) <EOL> led = m . OutputReg ( '<STR_LIT>' , width , initval = <NUM_LIT:0> ) <EOL> count = m . Reg ( '<STR_LIT:count>' , <NUM_LIT:32> , initval = <NUM_LIT:0> ) <EOL> seq = Seq ( m , '<STR_LIT>' , clk , rst ) <EOL> seq . add ( count . inc ( ) , cond = ( count < <NUM_LIT> - <NUM_LIT:1> ) ) <EOL> seq . add ( count ( <NUM_LIT:0> ) , cond = ( count >= <NUM_LIT> - <NUM_LIT:1> ) ) <EOL> seq . add ( led . inc ( ) , cond = ( count >= <NUM_LIT> - <NUM_LIT:1> ) ) <EOL> m . add_hook ( seq . make_always , args = ( ) , kwargs = { } ) <EOL> return m <EOL> def mkTop ( ) : <EOL> m = Module ( '<STR_LIT>' ) <EOL> led = mkLed ( ) <EOL> params = m . copy_params ( led ) <EOL> ports = m . copy_ports ( led ) <EOL> m . Instance ( led , '<STR_LIT>' + led . name , <EOL> connect_same_name ( * params . values ( ) ) , <EOL> connect_same_name ( * ports . values ( ) ) ) <EOL> return m <EOL> if __name__ == '<STR_LIT:__main__>' : <EOL> top = mkTop ( ) <EOL> dummy = top . to_verilog ( ) <EOL> verilog = top . to_verilog ( ) <EOL> print ( verilog ) </s>
