<s> from __future__ import absolute_import <EOL> from __future__ import print_function <EOL> import sys <EOL> import os <EOL> sys . path . insert ( <NUM_LIT:0> , os . path . dirname ( os . path . dirname ( os . path . dirname ( os . path . dirname ( os . path . dirname ( os . path . abspath ( __file__ ) ) ) ) ) ) ) <EOL> from veriloggen import * <EOL> def mkLed ( ) : <EOL> m = Module ( '<STR_LIT>' ) <EOL> width = m . Parameter ( '<STR_LIT>' , <NUM_LIT:8> ) <EOL> clk = m . Input ( '<STR_LIT>' ) <EOL> rst = m . Input ( '<STR_LIT>' ) <EOL> led = m . OutputReg ( '<STR_LIT>' , width , initval = <NUM_LIT:0> ) <EOL> count = m . Reg ( '<STR_LIT:count>' , <NUM_LIT:32> , initval = <NUM_LIT:0> ) <EOL> """<STR_LIT>""" <EOL> fsm = FSM ( m , '<STR_LIT>' , clk , rst ) <EOL> fsm . add ( led ( <NUM_LIT:0> ) ) <EOL> fsm . goto_next ( ) <EOL> init = fsm . current ( ) <EOL> fsm . add ( count ( <NUM_LIT:0> ) ) <EOL> fsm . goto_next ( ) <EOL> head = fsm . current ( ) <EOL> cond = count < <NUM_LIT> <EOL> fsm . goto_next ( cond = cond ) <EOL> fsm . add ( count . inc ( ) ) <EOL> fsm . goto_next ( ) <EOL> fsm . add ( count . inc ( ) ) <EOL> fsm . goto ( head ) <EOL> fsm . inc ( ) <EOL> tail = fsm . current ( ) <EOL> fsm . goto_from ( head , tail , cond = Not ( cond ) ) <EOL> fsm . add ( led . inc ( ) ) <EOL> fsm . goto ( init ) <EOL> m . add_hook ( fsm . make_always , args = ( ) , kwargs = { } ) <EOL> return m <EOL> if __name__ == '<STR_LIT:__main__>' : <EOL> led = mkLed ( ) <EOL> dummy = led . to_verilog ( ) <EOL> verilog = led . to_verilog ( ) <EOL> print ( verilog ) </s>
