<s> from migen . fhdl . module import Module <EOL> from migen . fhdl . specials import Instance <EOL> from migen . genlib . io import * <EOL> from migen . genlib . resetsync import AsyncResetSynchronizer <EOL> class LatticeAsyncResetSynchronizerImpl ( Module ) : <EOL> def __init__ ( self , cd , async_reset ) : <EOL> rst1 = Signal ( ) <EOL> self . specials += [ <EOL> Instance ( "<STR_LIT>" , i_D = <NUM_LIT:0> , i_PD = async_reset , <EOL> i_CK = cd . clk , o_Q = rst1 ) , <EOL> Instance ( "<STR_LIT>" , i_D = rst1 , i_PD = async_reset , <EOL> i_CK = cd . clk , o_Q = cd . rst ) <EOL> ] <EOL> class LatticeAsyncResetSynchronizer : <EOL> @ staticmethod <EOL> def lower ( dr ) : <EOL> return LatticeAsyncResetSynchronizerImpl ( dr . cd , dr . async_reset ) <EOL> class LatticeDDROutputImpl ( Module ) : <EOL> def __init__ ( self , i1 , i2 , o , clk ) : <EOL> self . specials += Instance ( "<STR_LIT>" , <EOL> synthesis_directive = "<STR_LIT>" , <EOL> i_SCLK = clk , <EOL> i_DA = i1 , i_DB = i2 , o_Q = o , <EOL> ) <EOL> class LatticeDDROutput : <EOL> @ staticmethod <EOL> def lower ( dr ) : <EOL> return LatticeDDROutputImpl ( dr . i1 , dr . i2 , dr . o , dr . clk ) <EOL> lattice_special_overrides = { <EOL> AsyncResetSynchronizer : LatticeAsyncResetSynchronizer , <EOL> DDROutput : LatticeDDROutput <EOL> } </s>
