<s> from __future__ import absolute_import <EOL> from __future__ import print_function <EOL> import sys <EOL> import os <EOL> sys . path . insert ( <NUM_LIT:0> , os . path . dirname ( os . path . dirname ( os . path . dirname ( os . path . dirname ( os . path . dirname ( os . path . abspath ( __file__ ) ) ) ) ) ) ) <EOL> from veriloggen import * <EOL> import veriloggen . dataflow as dataflow <EOL> def mkMain ( ) : <EOL> x = dataflow . Variable ( '<STR_LIT>' ) <EOL> z = x <EOL> z . output ( '<STR_LIT>' ) <EOL> df = dataflow . Dataflow ( z ) <EOL> m = df . to_module ( '<STR_LIT>' ) <EOL> return m <EOL> def mkTest ( numports = <NUM_LIT:8> ) : <EOL> m = Module ( '<STR_LIT:test>' ) <EOL> main = mkMain ( ) <EOL> params = m . copy_params ( main ) <EOL> ports = m . copy_sim_ports ( main ) <EOL> clk = ports [ '<STR_LIT>' ] <EOL> rst = ports [ '<STR_LIT>' ] <EOL> xdata = ports [ '<STR_LIT>' ] <EOL> xvalid = m . Reg ( '<STR_LIT>' ) <EOL> xready = m . Wire ( '<STR_LIT>' ) <EOL> m . Assign ( xready ( <NUM_LIT:1> ) ) <EOL> zdata = ports [ '<STR_LIT>' ] <EOL> zvalid = m . Wire ( '<STR_LIT>' ) <EOL> zready = m . Reg ( '<STR_LIT>' ) <EOL> m . Assign ( zvalid ( <NUM_LIT:1> ) ) <EOL> uut = m . Instance ( main , '<STR_LIT>' , <EOL> params = m . connect_params ( main ) , <EOL> ports = m . connect_ports ( main ) ) <EOL> reset_done = m . Reg ( '<STR_LIT>' , initval = <NUM_LIT:0> ) <EOL> reset_stmt = [ ] <EOL> reset_stmt . append ( reset_done ( <NUM_LIT:0> ) ) <EOL> reset_stmt . append ( xdata ( <NUM_LIT:0> ) ) <EOL> reset_stmt . append ( xvalid ( <NUM_LIT:0> ) ) <EOL> reset_stmt . append ( zready ( <NUM_LIT:0> ) ) <EOL> simulation . setup_waveform ( m , uut ) <EOL> simulation . setup_clock ( m , clk , hperiod = <NUM_LIT:5> ) <EOL> init = simulation . setup_reset ( m , rst , reset_stmt , period = <NUM_LIT:100> ) <EOL> nclk = simulation . next_clock <EOL> init . add ( <EOL> Delay ( <NUM_LIT:1000> ) , <EOL> reset_done ( <NUM_LIT:1> ) , <EOL> nclk ( clk ) , <EOL> Delay ( <NUM_LIT> ) , <EOL> Systask ( '<STR_LIT>' ) , <EOL> ) <EOL> def send ( name , data , valid , ready , step = <NUM_LIT:1> , waitnum = <NUM_LIT:10> ) : <EOL> fsm = FSM ( m , name + '<STR_LIT>' , clk , rst ) <EOL> count = m . TmpReg ( <NUM_LIT:32> , initval = <NUM_LIT:0> ) <EOL> fsm . add ( valid ( <NUM_LIT:0> ) ) <EOL> fsm . goto_next ( cond = reset_done ) <EOL> fsm . add ( valid ( <NUM_LIT:1> ) ) <EOL> fsm . goto_next ( ) <EOL> fsm . add ( data ( data + step ) , cond = ready ) <EOL> fsm . add ( count . inc ( ) , cond = ready ) <EOL> fsm . goto_next ( cond = AndList ( count == <NUM_LIT:5> , ready ) ) <EOL> fsm . add ( data ( data + step ) , cond = ready ) <EOL> fsm . add ( count . inc ( ) , cond = ready ) <EOL> fsm . goto_next ( cond = AndList ( count == <NUM_LIT:10> , ready ) ) <EOL> fsm . make_always ( ) <EOL> def receive ( name , data , valid , ready , waitnum = <NUM_LIT:10> ) : <EOL> fsm = FSM ( m , name + '<STR_LIT>' , clk , rst ) <EOL> fsm . add ( ready ( <NUM_LIT:0> ) ) <EOL> fsm . goto_next ( cond = reset_done ) <EOL> fsm . goto_next ( ) <EOL> yinit = fsm . current ( ) <EOL> fsm . add ( ready ( <NUM_LIT:1> ) , cond = valid ) <EOL> fsm . make_always ( ) <EOL> send ( '<STR_LIT:x>' , xdata , xvalid , xready , step = <NUM_LIT:1> , waitnum = <NUM_LIT:10> ) <EOL> receive ( '<STR_LIT:z>' , zdata , zvalid , zready , waitnum = <NUM_LIT:5> ) <EOL> m . Always ( Posedge ( clk ) ) ( <EOL> If ( reset_done ) ( <EOL> Systask ( '<STR_LIT>' , '<STR_LIT>' , xdata ) , <EOL> Systask ( '<STR_LIT>' , '<STR_LIT>' , zdata ) <EOL> ) <EOL> ) <EOL> return m <EOL> if __name__ == '<STR_LIT:__main__>' : <EOL> test = mkTest ( ) <EOL> verilog = test . to_verilog ( '<STR_LIT>' ) <EOL> print ( verilog ) <EOL> sim = simulation . Simulator ( test ) <EOL> rslt = sim . run ( ) <EOL> print ( rslt ) </s>
