<s> import base64 <EOL> import tempfile <EOL> import traceback <EOL> import SimpleXMLRPCServer <EOL> import sys , os <EOL> sys . path . append ( os . sep . join ( ( '<STR_LIT:..>' , '<STR_LIT:..>' , '<STR_LIT:..>' , '<STR_LIT:..>' , '<STR_LIT:..>' ) ) ) <EOL> import voodoo . configuration as CM <EOL> import weblab . experiment . devices . xilinx_impact . devices as XilinxDevices <EOL> import weblab . experiment . devices . xilinx_impact . impact as XilinxImpact <EOL> class FpgaProgrammer ( object ) : <EOL> def program ( self , serialized_content ) : <EOL> print "<STR_LIT>" <EOL> content = base64 . decodestring ( serialized_content ) <EOL> fd , file_name = tempfile . mkstemp ( prefix = '<STR_LIT>' , suffix = '<STR_LIT>' ) <EOL> try : <EOL> os . write ( fd , content ) <EOL> os . close ( fd ) <EOL> print "<STR_LIT>" % file_name <EOL> impact . program_device ( file_name ) <EOL> print "<STR_LIT>" <EOL> return "<STR_LIT>" <EOL> except : <EOL> traceback . print_exc ( ) <EOL> raise <EOL> finally : <EOL> os . remove ( file_name ) <EOL> if __name__ == '<STR_LIT:__main__>' : <EOL> cfg_manager = CM . ConfigurationManager ( ) <EOL> cfg_manager . append_path ( "<STR_LIT>" ) <EOL> impact = XilinxImpact . create ( XilinxDevices . FPGA , cfg_manager ) <EOL> server = SimpleXMLRPCServer . SimpleXMLRPCServer ( ( '<STR_LIT>' , cfg_manager . get_value ( "<STR_LIT:port>" ) ) ) <EOL> server . register_instance ( FpgaProgrammer ( ) ) <EOL> server . serve_forever ( ) </s>
