<s> from __future__ import absolute_import <EOL> from __future__ import print_function <EOL> import sys <EOL> import os <EOL> sys . path . insert ( <NUM_LIT:0> , os . path . dirname ( os . path . dirname ( os . path . dirname ( os . path . dirname ( os . path . dirname ( os . path . abspath ( __file__ ) ) ) ) ) ) ) <EOL> from veriloggen import * <EOL> def mkLed ( ) : <EOL> m = Module ( '<STR_LIT>' ) <EOL> clk = m . Input ( '<STR_LIT>' ) <EOL> rst = m . Input ( '<STR_LIT>' ) <EOL> x = m . Input ( '<STR_LIT:x>' , <NUM_LIT:32> ) <EOL> vx = m . Input ( '<STR_LIT>' ) <EOL> rx = m . Output ( '<STR_LIT>' ) <EOL> y = m . Input ( '<STR_LIT:y>' , <NUM_LIT:32> ) <EOL> vy = m . Input ( '<STR_LIT>' ) <EOL> ry = m . Output ( '<STR_LIT>' ) <EOL> z = m . Output ( '<STR_LIT:z>' , <NUM_LIT:32> ) <EOL> vz = m . Output ( '<STR_LIT>' ) <EOL> rz = m . Input ( '<STR_LIT>' ) <EOL> df = Pipeline ( m , '<STR_LIT>' , clk , rst ) <EOL> px = df . input ( x , valid = vx , ready = rx ) <EOL> py = df . input ( y , valid = vy , ready = ry ) <EOL> pz = df ( Cond ( px > py , px , py ) ) <EOL> pz . output ( z , valid = vz , ready = rz ) <EOL> df . make_always ( ) <EOL> try : <EOL> df . draw_graph ( ) <EOL> except : <EOL> print ( '<STR_LIT>' , file = sys . stderr ) <EOL> return m <EOL> def mkTest ( numports = <NUM_LIT:8> ) : <EOL> m = Module ( '<STR_LIT:test>' ) <EOL> led = mkLed ( ) <EOL> params = m . copy_params ( led ) <EOL> ports = m . copy_sim_ports ( led ) <EOL> clk = ports [ '<STR_LIT>' ] <EOL> rst = ports [ '<STR_LIT>' ] <EOL> x = ports [ '<STR_LIT:x>' ] <EOL> vx = ports [ '<STR_LIT>' ] <EOL> rx = ports [ '<STR_LIT>' ] <EOL> y = ports [ '<STR_LIT:y>' ] <EOL> vy = ports [ '<STR_LIT>' ] <EOL> ry = ports [ '<STR_LIT>' ] <EOL> z = ports [ '<STR_LIT:z>' ] <EOL> vz = ports [ '<STR_LIT>' ] <EOL> rz = ports [ '<STR_LIT>' ] <EOL> uut = m . Instance ( led , '<STR_LIT>' , <EOL> params = m . connect_params ( led ) , <EOL> ports = m . connect_ports ( led ) ) <EOL> reset_done = m . Reg ( '<STR_LIT>' , initval = <NUM_LIT:0> ) <EOL> reset_stmt = [ ] <EOL> reset_stmt . append ( reset_done ( <NUM_LIT:0> ) ) <EOL> reset_stmt . append ( x ( <NUM_LIT:11> ) ) <EOL> reset_stmt . append ( y ( <NUM_LIT:0> ) ) <EOL> reset_stmt . append ( vx ( <NUM_LIT:0> ) ) <EOL> reset_stmt . append ( vy ( <NUM_LIT:0> ) ) <EOL> reset_stmt . append ( rz ( <NUM_LIT:0> ) ) <EOL> simulation . setup_waveform ( m , uut ) <EOL> simulation . setup_clock ( m , clk , hperiod = <NUM_LIT:5> ) <EOL> init = simulation . setup_reset ( m , rst , reset_stmt , period = <NUM_LIT:100> ) <EOL> nclk = simulation . next_clock <EOL> init . add ( <EOL> Delay ( <NUM_LIT:1000> ) , <EOL> reset_done ( <NUM_LIT:1> ) , <EOL> nclk ( clk ) , <EOL> Delay ( <NUM_LIT> ) , <EOL> Systask ( '<STR_LIT>' ) , <EOL> ) <EOL> x_count = m . TmpReg ( <NUM_LIT:32> , initval = <NUM_LIT:0> ) <EOL> y_count = m . TmpReg ( <NUM_LIT:32> , initval = <NUM_LIT:0> ) <EOL> z_count = m . TmpReg ( <NUM_LIT:32> , initval = <NUM_LIT:0> ) <EOL> xfsm = FSM ( m , '<STR_LIT>' , clk , rst ) <EOL> xfsm . add ( vx ( <NUM_LIT:0> ) ) <EOL> xfsm . goto_next ( cond = reset_done ) <EOL> xfsm . add ( vx ( <NUM_LIT:1> ) ) <EOL> xfsm . add ( x . dec ( ) , cond = rx ) <EOL> xfsm . add ( x_count . inc ( ) , cond = rx ) <EOL> xfsm . goto_next ( cond = AndList ( x_count == <NUM_LIT:10> , rx ) ) <EOL> xfsm . add ( vx ( <NUM_LIT:0> ) ) <EOL> xfsm . make_always ( ) <EOL> yfsm = FSM ( m , '<STR_LIT>' , clk , rst ) <EOL> yfsm . add ( vy ( <NUM_LIT:0> ) ) <EOL> yfsm . goto_next ( cond = reset_done ) <EOL> for _ in range ( <NUM_LIT:10> ) : <EOL> yfsm . goto_next ( ) <EOL> yfsm . add ( vy ( <NUM_LIT:1> ) ) <EOL> yfsm . goto_next ( ) <EOL> yfsm . add ( y . inc ( ) , cond = ry ) <EOL> yfsm . add ( y_count . inc ( ) , cond = ry ) <EOL> yfsm . goto_next ( cond = AndList ( y_count == <NUM_LIT:10> , ry ) ) <EOL> yfsm . add ( vy ( <NUM_LIT:0> ) ) <EOL> yfsm . make_always ( ) <EOL> zfsm = FSM ( m , '<STR_LIT>' , clk , rst ) <EOL> zfsm . add ( rz ( <NUM_LIT:0> ) ) <EOL> zfsm . goto_next ( cond = reset_done ) <EOL> zfsm . goto_next ( ) <EOL> zinit = zfsm . current ( ) <EOL> zfsm . add ( rz ( <NUM_LIT:1> ) , cond = vz ) <EOL> zfsm . goto_next ( cond = vz ) <EOL> for i in range ( <NUM_LIT:10> ) : <EOL> zfsm . add ( rz ( <NUM_LIT:0> ) ) <EOL> zfsm . goto_next ( ) <EOL> zfsm . goto ( zinit ) <EOL> zfsm . make_always ( ) <EOL> m . Always ( Posedge ( clk ) ) ( <EOL> If ( reset_done ) ( <EOL> If ( AndList ( vx , rx ) ) ( <EOL> Systask ( '<STR_LIT>' , '<STR_LIT>' , x ) <EOL> ) , <EOL> If ( AndList ( vy , ry ) ) ( <EOL> Systask ( '<STR_LIT>' , '<STR_LIT>' , y ) <EOL> ) , <EOL> If ( AndList ( vz , rz ) ) ( <EOL> Systask ( '<STR_LIT>' , '<STR_LIT>' , z ) <EOL> ) <EOL> ) <EOL> ) <EOL> return m <EOL> if __name__ == '<STR_LIT:__main__>' : <EOL> test = mkTest ( ) <EOL> verilog = test . to_verilog ( '<STR_LIT>' ) <EOL> print ( verilog ) <EOL> sim = simulation . Simulator ( test ) <EOL> rslt = sim . run ( ) <EOL> print ( rslt ) </s>
