<s> from __future__ import absolute_import <EOL> from __future__ import print_function <EOL> import sys <EOL> import os <EOL> import collections <EOL> sys . path . insert ( <NUM_LIT:0> , os . path . dirname ( os . path . dirname ( os . path . dirname ( os . path . dirname ( os . path . dirname ( os . path . abspath ( __file__ ) ) ) ) ) ) ) <EOL> from veriloggen import * <EOL> def mkLed ( ) : <EOL> m = Module ( '<STR_LIT>' ) <EOL> width = m . Parameter ( '<STR_LIT>' , <NUM_LIT:8> ) <EOL> clk = m . Input ( '<STR_LIT>' ) <EOL> rst = m . Input ( '<STR_LIT>' ) <EOL> led = m . OutputReg ( '<STR_LIT>' , width ) <EOL> count = m . Reg ( '<STR_LIT:count>' , <NUM_LIT:32> ) <EOL> m . Always ( Posedge ( clk ) ) ( <EOL> If ( rst ) ( <EOL> count ( <NUM_LIT:0> ) <EOL> ) . Else ( <EOL> If ( count == <NUM_LIT> ) ( <EOL> count ( <NUM_LIT:0> ) <EOL> ) . Else ( <EOL> count ( count + <NUM_LIT:1> ) <EOL> ) <EOL> ) ) <EOL> m . Always ( Posedge ( clk ) ) ( <EOL> If ( rst ) ( <EOL> led ( <NUM_LIT:0> ) <EOL> ) . Else ( <EOL> If ( count == <NUM_LIT> ) ( <EOL> led ( led + <NUM_LIT:1> ) <EOL> ) <EOL> ) ) <EOL> return m <EOL> def mkTop ( ) : <EOL> m = Module ( '<STR_LIT>' ) <EOL> led = mkLed ( ) <EOL> clk = m . Input ( '<STR_LIT>' ) <EOL> rst = m . Input ( '<STR_LIT>' ) <EOL> params = m . copy_params ( led , prefix = '<STR_LIT>' ) <EOL> ports = m . copy_ports ( led , prefix = '<STR_LIT>' , exclude = ( '<STR_LIT>' , '<STR_LIT>' ) ) <EOL> params = m . copy_params ( led , prefix = '<STR_LIT>' ) <EOL> ports = m . copy_ports ( led , prefix = '<STR_LIT>' , exclude = ( '<STR_LIT>' , '<STR_LIT>' ) ) <EOL> m . Instance ( led , '<STR_LIT>' , <EOL> m . connect_params ( led , prefix = '<STR_LIT>' ) , <EOL> m . connect_ports ( led , prefix = '<STR_LIT>' ) + m . connect_ports ( led , prefix = '<STR_LIT>' ) ) <EOL> m . Instance ( led , '<STR_LIT>' , <EOL> m . connect_params ( led , prefix = '<STR_LIT>' ) , <EOL> m . connect_ports ( led , prefix = '<STR_LIT>' ) + m . connect_ports ( led , prefix = '<STR_LIT>' ) ) <EOL> return m <EOL> if __name__ == '<STR_LIT:__main__>' : <EOL> top = mkTop ( ) <EOL> verilog = top . to_verilog ( ) <EOL> print ( verilog ) </s>
