<s> from migen . build . generic_platform import * <EOL> from migen . build . xilinx import XilinxPlatform <EOL> from migen . build . xilinx . programmer import XC3SProg <EOL> _io = [ <EOL> ( "<STR_LIT>" , <NUM_LIT:0> , Pins ( "<STR_LIT>" ) , IOStandard ( "<STR_LIT>" ) , Drive ( <NUM_LIT> ) , Misc ( "<STR_LIT>" ) ) , <EOL> ( "<STR_LIT>" , <NUM_LIT:0> , Pins ( "<STR_LIT>" ) , IOStandard ( "<STR_LIT>" ) ) , <EOL> ( "<STR_LIT>" , <NUM_LIT:0> , <EOL> Subsignal ( "<STR_LIT>" , Pins ( "<STR_LIT>" ) , IOStandard ( "<STR_LIT>" ) , Misc ( "<STR_LIT>" ) ) , <EOL> Subsignal ( "<STR_LIT>" , Pins ( "<STR_LIT>" ) , IOStandard ( "<STR_LIT>" ) , Misc ( "<STR_LIT>" ) ) <EOL> ) , <EOL> ( "<STR_LIT>" , <NUM_LIT:0> , <EOL> Subsignal ( "<STR_LIT>" , Pins ( "<STR_LIT>" ) ) , <EOL> Subsignal ( "<STR_LIT>" , Pins ( "<STR_LIT>" ) ) , <EOL> Subsignal ( "<STR_LIT>" , Pins ( "<STR_LIT>" ) ) , <EOL> Subsignal ( "<STR_LIT>" , Pins ( "<STR_LIT>" ) , Misc ( "<STR_LIT>" ) ) , <EOL> IOStandard ( "<STR_LIT>" ) , Misc ( "<STR_LIT>" ) <EOL> ) , <EOL> ( "<STR_LIT>" , <NUM_LIT:0> , <EOL> Subsignal ( "<STR_LIT>" , Pins ( "<STR_LIT>" ) ) , <EOL> Subsignal ( "<STR_LIT>" , Pins ( "<STR_LIT>" ) ) , <EOL> Subsignal ( "<STR_LIT>" , Pins ( "<STR_LIT>" , "<STR_LIT>" ) ) , <EOL> IOStandard ( "<STR_LIT>" ) , Misc ( "<STR_LIT>" ) <EOL> ) , <EOL> ( "<STR_LIT>" , <NUM_LIT:0> , Pins ( "<STR_LIT>" ) , IOStandard ( "<STR_LIT>" ) , Misc ( "<STR_LIT>" ) ) , <EOL> ( "<STR_LIT>" , <NUM_LIT:0> , <EOL> Subsignal ( "<STR_LIT:a>" , Pins ( "<STR_LIT>" , <EOL> "<STR_LIT>" ) ) , <EOL> Subsignal ( "<STR_LIT>" , Pins ( "<STR_LIT>" ) ) , <EOL> Subsignal ( "<STR_LIT>" , Pins ( "<STR_LIT>" ) ) , <EOL> Subsignal ( "<STR_LIT>" , Pins ( "<STR_LIT>" ) ) , <EOL> Subsignal ( "<STR_LIT>" , Pins ( "<STR_LIT>" ) ) , <EOL> Subsignal ( "<STR_LIT>" , Pins ( "<STR_LIT>" ) ) , <EOL> Subsignal ( "<STR_LIT>" , Pins ( "<STR_LIT>" ) ) , <EOL> Subsignal ( "<STR_LIT>" , Pins ( "<STR_LIT>" ) ) , <EOL> Subsignal ( "<STR_LIT>" , Pins ( "<STR_LIT>" ) ) , <EOL> IOStandard ( "<STR_LIT>" ) , Misc ( "<STR_LIT>" ) <EOL> ) <EOL> ] <EOL> _connectors = [ <EOL> ( "<STR_LIT:A>" , "<STR_LIT>" ) , <EOL> ( "<STR_LIT:B>" , "<STR_LIT>" ) , <EOL> ( "<STR_LIT:C>" , "<STR_LIT>" ) <EOL> ] <EOL> class Platform ( XilinxPlatform ) : <EOL> default_clk_name = "<STR_LIT>" <EOL> default_clk_period = <NUM_LIT> <EOL> def __init__ ( self ) : <EOL> XilinxPlatform . __init__ ( self , "<STR_LIT>" , _io , _connectors ) <EOL> def create_programmer ( self ) : <EOL> return XC3SProg ( "<STR_LIT>" , "<STR_LIT>" ) </s>
