<s> from __future__ import absolute_import <EOL> from __future__ import print_function <EOL> import veriloggen . core . vtypes as vtypes <EOL> import veriloggen . core . module as module <EOL> def mkMultiplierCore ( index , lwidth = <NUM_LIT:32> , rwidth = <NUM_LIT:32> , lsigned = True , rsigned = True , depth = <NUM_LIT:6> ) : <EOL> retwidth = lwidth + rwidth <EOL> m = module . Module ( '<STR_LIT>' % index ) <EOL> clk = m . Input ( '<STR_LIT>' ) <EOL> update = m . Input ( '<STR_LIT>' ) <EOL> a = m . Input ( '<STR_LIT:a>' , lwidth ) <EOL> b = m . Input ( '<STR_LIT:b>' , rwidth ) <EOL> c = m . Output ( '<STR_LIT:c>' , retwidth ) <EOL> _a = m . Reg ( '<STR_LIT>' , lwidth , signed = lsigned ) <EOL> _b = m . Reg ( '<STR_LIT>' , rwidth , signed = rsigned ) <EOL> tmpval = [ m . Reg ( '<STR_LIT>' % i , retwidth , signed = True ) for i in range ( depth - <NUM_LIT:1> ) ] <EOL> rslt = m . Wire ( '<STR_LIT>' , retwidth , signed = True ) <EOL> __a = _a <EOL> __b = _b <EOL> if not lsigned : <EOL> __a = vtypes . SystemTask ( '<STR_LIT>' , vtypes . Cat ( vtypes . Int ( <NUM_LIT:0> , width = <NUM_LIT:1> ) , _a ) ) <EOL> if not rsigned : <EOL> __b = vtypes . SystemTask ( '<STR_LIT>' , vtypes . Cat ( vtypes . Int ( <NUM_LIT:0> , width = <NUM_LIT:1> ) , _b ) ) <EOL> m . Assign ( rslt ( __a * __b ) ) <EOL> m . Assign ( c ( tmpval [ depth - <NUM_LIT:2> ] ) ) <EOL> m . Always ( vtypes . Posedge ( clk ) ) ( <EOL> vtypes . If ( update ) ( <EOL> _a ( a ) , <EOL> _b ( b ) , <EOL> tmpval [ <NUM_LIT:0> ] ( rslt ) , <EOL> [ tmpval [ i ] ( tmpval [ i - <NUM_LIT:1> ] ) for i in range ( <NUM_LIT:1> , depth - <NUM_LIT:1> ) ] <EOL> ) ) <EOL> return m <EOL> def mkMultiplier ( index , lwidth = <NUM_LIT:32> , rwidth = <NUM_LIT:32> , lsigned = True , rsigned = True , depth = <NUM_LIT:6> ) : <EOL> if lwidth < <NUM_LIT:0> : raise ValueError ( "<STR_LIT>" ) <EOL> if rwidth < <NUM_LIT:0> : raise ValueError ( "<STR_LIT>" ) <EOL> if depth < <NUM_LIT:2> : raise ValueError ( "<STR_LIT>" ) <EOL> retwidth = lwidth + rwidth <EOL> mult = mkMultiplierCore ( index , lwidth , rwidth , lsigned , rsigned , depth ) <EOL> m = module . Module ( '<STR_LIT>' % index ) <EOL> clk = m . Input ( '<STR_LIT>' ) <EOL> rst = m . Input ( '<STR_LIT>' ) <EOL> update = m . Input ( '<STR_LIT>' ) <EOL> enable = m . Input ( '<STR_LIT>' ) <EOL> valid = m . Output ( '<STR_LIT>' ) <EOL> a = m . Input ( '<STR_LIT:a>' , lwidth ) <EOL> b = m . Input ( '<STR_LIT:b>' , rwidth ) <EOL> c = m . Output ( '<STR_LIT:c>' , retwidth ) <EOL> valid_reg = [ m . Reg ( '<STR_LIT>' % i ) for i in range ( depth ) ] <EOL> m . Assign ( valid ( valid_reg [ depth - <NUM_LIT:1> ] ) ) <EOL> m . Always ( vtypes . Posedge ( clk ) ) ( <EOL> vtypes . If ( rst ) ( <EOL> [ valid_reg [ i ] ( <NUM_LIT:0> ) for i in range ( depth ) ] <EOL> ) . Else ( <EOL> vtypes . If ( update ) ( <EOL> valid_reg [ <NUM_LIT:0> ] ( enable ) , <EOL> [ valid_reg [ i ] ( valid_reg [ i - <NUM_LIT:1> ] ) for i in range ( <NUM_LIT:1> , depth ) ] <EOL> ) <EOL> ) ) <EOL> ports = [ ( '<STR_LIT>' , clk ) , ( '<STR_LIT>' , update ) , ( '<STR_LIT:a>' , a ) , ( '<STR_LIT:b>' , b ) , ( '<STR_LIT:c>' , c ) ] <EOL> m . Instance ( mult , '<STR_LIT>' , ports = ports ) <EOL> return m <EOL> index_count = <NUM_LIT:0> <EOL> def get_mul ( lwidth = <NUM_LIT:32> , rwidth = <NUM_LIT:32> , lsigned = True , rsigned = True , depth = <NUM_LIT:6> ) : <EOL> global index_count <EOL> mul = mkMultiplier ( index_count , lwidth , rwidth , lsigned , rsigned , depth ) <EOL> index_count += <NUM_LIT:1> <EOL> return mul <EOL> def reset ( ) : <EOL> global index_count <EOL> index_count = <NUM_LIT:0> </s>
