<s> from __future__ import absolute_import <EOL> from __future__ import print_function <EOL> import sys <EOL> import os <EOL> from veriloggen import * <EOL> def mkLed ( ) : <EOL> m = Module ( '<STR_LIT>' ) <EOL> width = m . Parameter ( '<STR_LIT>' , <NUM_LIT:8> ) <EOL> clk = m . Input ( '<STR_LIT>' ) <EOL> rst = m . Input ( '<STR_LIT>' ) <EOL> led = m . OutputReg ( '<STR_LIT>' , width ) <EOL> count = m . Reg ( '<STR_LIT:count>' , <NUM_LIT:32> ) <EOL> m . Always ( Posedge ( clk ) ) ( <EOL> If ( rst ) ( <EOL> count ( <NUM_LIT:0> ) <EOL> ) . Else ( <EOL> If ( count == <NUM_LIT> ) ( <EOL> count ( <NUM_LIT:0> ) <EOL> ) . Else ( <EOL> count ( count + <NUM_LIT:1> ) <EOL> ) <EOL> ) ) <EOL> m . Always ( Posedge ( clk ) ) ( <EOL> If ( rst ) ( <EOL> led ( <NUM_LIT:0> ) <EOL> ) . Else ( <EOL> If ( count == <NUM_LIT> - <NUM_LIT:1> ) ( <EOL> led ( led + <NUM_LIT:1> ) <EOL> ) <EOL> ) ) <EOL> m . Always ( Posedge ( clk ) ) ( <EOL> If ( rst ) ( <EOL> ) . Else ( <EOL> Systask ( '<STR_LIT>' , "<STR_LIT>" , led , count ) <EOL> ) ) <EOL> return m <EOL> def mkTest ( ) : <EOL> m = Module ( '<STR_LIT:test>' ) <EOL> led = mkLed ( ) <EOL> params = m . copy_params ( led ) <EOL> ports = m . copy_sim_ports ( led ) <EOL> clk = ports [ '<STR_LIT>' ] <EOL> rst = ports [ '<STR_LIT>' ] <EOL> uut = m . Instance ( led , '<STR_LIT>' , <EOL> params = m . connect_params ( led ) , <EOL> ports = m . connect_ports ( led ) ) <EOL> simulation . setup_waveform ( m , uut , m . get_vars ( ) ) <EOL> simulation . setup_clock ( m , clk , hperiod = <NUM_LIT:5> ) <EOL> init = simulation . setup_reset ( m , rst , m . make_reset ( ) , period = <NUM_LIT:100> ) <EOL> init . add ( <EOL> Delay ( <NUM_LIT:1000> * <NUM_LIT:100> ) , <EOL> Systask ( '<STR_LIT>' ) , <EOL> ) <EOL> return m <EOL> if __name__ == '<STR_LIT:__main__>' : <EOL> test = mkTest ( ) <EOL> verilog = test . to_verilog ( filename = '<STR_LIT>' ) <EOL> print ( verilog ) <EOL> sim = simulation . Simulator ( test ) <EOL> rslt = sim . run ( ) <EOL> print ( rslt ) </s>
