<s> import pytest <EOL> import pymtl . model . ConnectionEdge <EOL> from random import randrange <EOL> from pymtl import * <EOL> from SimulationTool_comb_test import verify_bit_blast , set_ports <EOL> from SimulationTool_seq_test import setup_sim , local_setup_sim <EOL> def is_translated ( model ) : <EOL> return hasattr ( model , '<STR_LIT>' ) <EOL> def passthrough_tester ( setup_sim , model_type ) : <EOL> model = model_type ( <NUM_LIT:16> ) <EOL> model , sim = setup_sim ( model ) <EOL> model . in_ . v = <NUM_LIT:8> <EOL> transl = is_translated ( model ) <EOL> if transl : sim . eval_combinational ( ) <EOL> assert model . out == <NUM_LIT:8> <EOL> assert model . out . v == <NUM_LIT:8> <EOL> model . in_ . v = <NUM_LIT:9> <EOL> model . in_ . v = <NUM_LIT:10> <EOL> if transl : sim . eval_combinational ( ) <EOL> assert model . out == <NUM_LIT:10> <EOL> class PassThroughStruct ( Model ) : <EOL> def __init__ ( s , nbits ) : <EOL> s . in_ = InPort ( nbits ) <EOL> s . out = OutPort ( nbits ) <EOL> def elaborate_logic ( s ) : <EOL> s . connect ( s . in_ , s . out ) <EOL> def test_PassThrough ( setup_sim ) : <EOL> passthrough_tester ( setup_sim , PassThroughStruct ) <EOL> class PassThroughBitsStruct ( Model ) : <EOL> def __init__ ( s , nbits ) : <EOL> s . in_ = InPort ( Bits ( nbits ) ) <EOL> s . out = OutPort ( Bits ( nbits ) ) <EOL> def elaborate_logic ( s ) : <EOL> s . connect ( s . in_ , s . out ) <EOL> def test_PassThroughBits ( setup_sim ) : <EOL> passthrough_tester ( setup_sim , PassThroughBitsStruct ) <EOL> class PassThroughList ( Model ) : <EOL> def __init__ ( s , nbits , nports ) : <EOL> s . nports = nports <EOL> s . in_ = [ InPort ( nbits ) for x in range ( nports ) ] <EOL> s . out = [ OutPort ( nbits ) for x in range ( nports ) ] <EOL> def elaborate_logic ( s ) : <EOL> for i in range ( s . nports ) : <EOL> s . connect ( s . in_ [ i ] , s . out [ i ] ) <EOL> def test_PassThroughList ( setup_sim ) : <EOL> model = PassThroughList ( <NUM_LIT:16> , <NUM_LIT:4> ) <EOL> model , sim = setup_sim ( model ) <EOL> transl = is_translated ( model ) <EOL> for i in range ( <NUM_LIT:4> ) : <EOL> model . in_ [ i ] . v = i <EOL> if transl : sim . eval_combinational ( ) <EOL> for i in range ( <NUM_LIT:4> ) : <EOL> assert model . out [ i ] == i <EOL> model . in_ [ <NUM_LIT:2> ] . v = <NUM_LIT:9> <EOL> model . in_ [ <NUM_LIT:2> ] . v = <NUM_LIT:10> <EOL> if transl : sim . eval_combinational ( ) <EOL> assert model . out [ <NUM_LIT:2> ] == <NUM_LIT:10> <EOL> class PassThroughListWire ( Model ) : <EOL> def __init__ ( s , nbits , nports ) : <EOL> s . nports = nports <EOL> s . nbits = nbits <EOL> s . in_ = [ InPort ( nbits ) for x in range ( nports ) ] <EOL> s . out = [ OutPort ( nbits ) for x in range ( nports ) ] <EOL> def elaborate_logic ( s ) : <EOL> s . wire = [ Wire ( s . nbits ) for x in range ( s . nports ) ] <EOL> for i in range ( s . nports ) : <EOL> s . connect ( s . in_ [ i ] , s . wire [ i ] ) <EOL> s . connect ( s . wire [ i ] , s . out [ i ] ) <EOL> def test_PassThroughListWire ( setup_sim ) : <EOL> model = PassThroughListWire ( <NUM_LIT:16> , <NUM_LIT:4> ) <EOL> model , sim = setup_sim ( model ) <EOL> transl = is_translated ( model ) <EOL> for i in range ( <NUM_LIT:4> ) : <EOL> model . in_ [ i ] . v = i <EOL> if transl : sim . eval_combinational ( ) <EOL> for i in range ( <NUM_LIT:4> ) : <EOL> assert model . out [ i ] == i <EOL> model . in_ [ <NUM_LIT:2> ] . v = <NUM_LIT:9> <EOL> model . in_ [ <NUM_LIT:2> ] . v = <NUM_LIT:10> <EOL> if transl : sim . eval_combinational ( ) <EOL> assert model . out [ <NUM_LIT:2> ] == <NUM_LIT:10> <EOL> class PassThroughWrapped ( Model ) : <EOL> def __init__ ( s , nbits ) : <EOL> s . nbits = nbits <EOL> s . in_ = InPort ( nbits ) <EOL> s . out = OutPort ( nbits ) <EOL> def elaborate_logic ( s ) : <EOL> s . pt = PassThroughStruct ( s . nbits ) <EOL> s . connect ( s . in_ , s . pt . in_ ) <EOL> s . connect ( s . out , s . pt . out ) <EOL> def test_PassThroughWrapped ( setup_sim ) : <EOL> passthrough_tester ( setup_sim , PassThroughWrapped ) <EOL> class PassThroughWrappedChain ( Model ) : <EOL> def __init__ ( s , nbits ) : <EOL> s . nbits = nbits <EOL> s . in_ = InPort ( nbits ) <EOL> s . out = OutPort ( nbits ) <EOL> def elaborate_logic ( s ) : <EOL> s . pt0 = PassThroughStruct ( s . nbits ) <EOL> s . pt1 = PassThroughStruct ( s . nbits ) <EOL> s . connect ( s . in_ , s . pt0 . in_ ) <EOL> s . connect ( s . pt0 . out , s . pt1 . in_ ) <EOL> s . connect ( s . out , s . pt1 . out ) <EOL> def test_PassThroughWrappedChain ( setup_sim ) : <EOL> passthrough_tester ( setup_sim , PassThroughWrappedChain ) <EOL> def splitter_tester ( setup_sim , model_type ) : <EOL> model = model_type ( <NUM_LIT:16> ) <EOL> model , sim = setup_sim ( model ) <EOL> transl = is_translated ( model ) <EOL> model . in_ . v = <NUM_LIT:8> <EOL> if transl : sim . eval_combinational ( ) <EOL> assert model . out0 == <NUM_LIT:8> <EOL> assert model . out0 . v == <NUM_LIT:8> <EOL> assert model . out1 == <NUM_LIT:8> <EOL> assert model . out1 . v == <NUM_LIT:8> <EOL> model . in_ . v = <NUM_LIT:9> <EOL> model . in_ . v = <NUM_LIT:10> <EOL> if transl : sim . eval_combinational ( ) <EOL> assert model . out0 == <NUM_LIT:10> <EOL> assert model . out1 == <NUM_LIT:10> <EOL> class Splitter ( Model ) : <EOL> def __init__ ( s , nbits ) : <EOL> s . in_ = InPort ( nbits ) <EOL> s . out0 = OutPort ( nbits ) <EOL> s . out1 = OutPort ( nbits ) <EOL> def elaborate_logic ( s ) : <EOL> s . connect ( s . in_ , s . out0 ) <EOL> s . connect ( s . in_ , s . out1 ) <EOL> def test_Splitter ( setup_sim ) : <EOL> splitter_tester ( setup_sim , Splitter ) <EOL> class SplitterWires ( Model ) : <EOL> def __init__ ( s , nbits ) : <EOL> s . nbits = nbits <EOL> s . in_ = InPort ( nbits ) <EOL> s . out0 = OutPort ( nbits ) <EOL> s . out1 = OutPort ( nbits ) <EOL> def elaborate_logic ( s ) : <EOL> s . wire0 = Wire ( s . nbits ) <EOL> s . wire1 = Wire ( s . nbits ) <EOL> s . connect ( s . in_ , s . wire0 ) <EOL> s . connect ( s . in_ , s . wire1 ) <EOL> s . connect ( s . wire0 , s . out0 ) <EOL> s . connect ( s . wire1 , s . out1 ) <EOL> def test_SplitterWires ( setup_sim ) : <EOL> splitter_tester ( setup_sim , SplitterWires ) <EOL> class SplitterWrapped ( Model ) : <EOL> def __init__ ( s , nbits ) : <EOL> s . nbits = nbits <EOL> s . in_ = InPort ( nbits ) <EOL> s . out0 = OutPort ( nbits ) <EOL> s . out1 = OutPort ( nbits ) <EOL> def elaborate_logic ( s ) : <EOL> s . spl = Splitter ( s . nbits ) <EOL> s . connect ( s . in_ , s . spl . in_ ) <EOL> s . connect ( s . out0 , s . spl . out0 ) <EOL> s . connect ( s . out1 , s . spl . out1 ) <EOL> def test_SplitterWrapped ( setup_sim ) : <EOL> splitter_tester ( setup_sim , SplitterWrapped ) <EOL> class SplitterPT_1 ( Model ) : <EOL> def __init__ ( s , nbits ) : <EOL> s . nbits = nbits <EOL> s . in_ = InPort ( nbits ) <EOL> s . out0 = OutPort ( nbits ) <EOL> s . out1 = OutPort ( nbits ) <EOL> def elaborate_logic ( s ) : <EOL> s . pt0 = PassThroughStruct ( s . nbits ) <EOL> s . pt1 = PassThroughStruct ( s . nbits ) <EOL> s . connect ( s . in_ , s . pt0 . in_ ) <EOL> s . connect ( s . in_ , s . pt1 . in_ ) <EOL> s . connect ( s . out0 , s . pt0 . out ) <EOL> s . connect ( s . out1 , s . pt1 . out ) <EOL> def test_SplitterPT_1 ( setup_sim ) : <EOL> splitter_tester ( setup_sim , SplitterPT_1 ) <EOL> class SplitterPT_2 ( Model ) : <EOL> def __init__ ( s , nbits ) : <EOL> s . nbits = nbits <EOL> s . in_ = InPort ( nbits ) <EOL> s . out0 = OutPort ( nbits ) <EOL> s . out1 = OutPort ( nbits ) <EOL> def elaborate_logic ( s ) : <EOL> s . pt0 = PassThroughStruct ( s . nbits ) <EOL> s . connect ( s . in_ , s . pt0 . in_ ) <EOL> s . connect ( s . out0 , s . pt0 . out ) <EOL> s . connect ( s . in_ , s . out1 ) <EOL> def test_SplitterPT_2 ( setup_sim ) : <EOL> splitter_tester ( setup_sim , SplitterPT_2 ) <EOL> class SplitterPT_3 ( Model ) : <EOL> def __init__ ( s , nbits ) : <EOL> s . nbits = nbits <EOL> s . in_ = InPort ( nbits ) <EOL> s . out0 = OutPort ( nbits ) <EOL> s . out1 = OutPort ( nbits ) <EOL> def elaborate_logic ( s ) : <EOL> s . pt0 = PassThroughStruct ( s . nbits ) <EOL> s . connect ( s . in_ , s . pt0 . in_ ) <EOL> s . connect ( s . in_ , s . out0 ) <EOL> s . connect ( s . out1 , s . pt0 . out ) <EOL> def test_SplitterPT_3 ( setup_sim ) : <EOL> splitter_tester ( setup_sim , SplitterPT_3 ) <EOL> class SplitterPT_4 ( Model ) : <EOL> def __init__ ( s , nbits ) : <EOL> s . nbits = nbits <EOL> s . in_ = InPort ( nbits ) <EOL> s . out0 = OutPort ( nbits ) <EOL> s . out1 = OutPort ( nbits ) <EOL> def elaborate_logic ( s ) : <EOL> s . spl = Splitter ( s . nbits ) <EOL> s . pt0 = PassThroughStruct ( s . nbits ) <EOL> s . pt1 = PassThroughStruct ( s . nbits ) <EOL> s . connect ( s . in_ , s . spl . in_ ) <EOL> s . connect ( s . spl . out0 , s . pt0 . in_ ) <EOL> s . connect ( s . spl . out1 , s . pt1 . in_ ) <EOL> s . connect ( s . out0 , s . pt0 . out ) <EOL> s . connect ( s . out1 , s . pt1 . out ) <EOL> def test_SplitterPT_4 ( setup_sim ) : <EOL> splitter_tester ( setup_sim , SplitterPT_4 ) <EOL> class SplitterPT_5 ( Model ) : <EOL> def __init__ ( s , nbits ) : <EOL> s . nbits = nbits <EOL> s . in_ = InPort ( nbits ) <EOL> s . out0 = OutPort ( nbits ) <EOL> s . out1 = OutPort ( nbits ) <EOL> def elaborate_logic ( s ) : <EOL> s . spl = Splitter ( s . nbits ) <EOL> s . pt0 = PassThroughStruct ( s . nbits ) <EOL> s . pt1 = PassThroughStruct ( s . nbits ) <EOL> s . pt2 = PassThroughStruct ( s . nbits ) <EOL> s . pt3 = PassThroughStruct ( s . nbits ) <EOL> s . connect ( s . in_ , s . spl . in_ ) <EOL> s . connect ( s . spl . out0 , s . pt0 . in_ ) <EOL> s . connect ( s . spl . out1 , s . pt1 . in_ ) <EOL> s . connect ( s . pt0 . out , s . pt2 . in_ ) <EOL> s . connect ( s . pt1 . out , s . pt3 . in_ ) <EOL> s . connect ( s . out0 , s . pt2 . out ) <EOL> s . connect ( s . out1 , s . pt3 . out ) <EOL> def test_SplitterPT_5 ( setup_sim ) : <EOL> splitter_tester ( setup_sim , SplitterPT_5 ) <EOL> def setup_bit_blast ( setup_sim , nbits , groups = None ) : <EOL> if not groups : <EOL> model = SimpleBitBlastStruct ( nbits ) <EOL> else : <EOL> model = ComplexBitBlastStruct ( nbits , groups ) <EOL> model , sim = setup_sim ( model ) <EOL> return model , sim <EOL> class SimpleBitBlastStruct ( Model ) : <EOL> def __init__ ( s , nbits ) : <EOL> s . nbits = nbits <EOL> s . in_ = InPort ( nbits ) <EOL> s . out = [ OutPort ( <NUM_LIT:1> ) for x in xrange ( nbits ) ] <EOL> def elaborate_logic ( s ) : <EOL> for i in range ( s . nbits ) : <EOL> s . connect ( s . out [ i ] , s . in_ [ i ] ) <EOL> def test_SimpleBitBlast_8_to_8x1 ( setup_sim ) : <EOL> model , sim = setup_bit_blast ( setup_sim , <NUM_LIT:8> ) <EOL> model . in_ . v = <NUM_LIT> <EOL> sim . eval_combinational ( ) <EOL> verify_bit_blast ( model . out , <NUM_LIT> ) <EOL> model . in_ . value = <NUM_LIT> <EOL> sim . eval_combinational ( ) <EOL> verify_bit_blast ( model . out , <NUM_LIT> ) <EOL> def test_SimpleBitBlast_16_to_16x1 ( setup_sim ) : <EOL> model , sim = setup_bit_blast ( setup_sim , <NUM_LIT:16> ) <EOL> model . in_ . v = <NUM_LIT> <EOL> sim . eval_combinational ( ) <EOL> verify_bit_blast ( model . out , <NUM_LIT> ) <EOL> model . in_ . v = <NUM_LIT> <EOL> sim . eval_combinational ( ) <EOL> verify_bit_blast ( model . out , <NUM_LIT> ) <EOL> class ComplexBitBlastStruct ( Model ) : <EOL> def __init__ ( s , nbits , groupings ) : <EOL> s . nbits = nbits <EOL> s . groupings = groupings <EOL> s . in_ = InPort ( nbits ) <EOL> s . out = [ OutPort ( groupings ) for x in <EOL> xrange ( <NUM_LIT:0> , nbits , groupings ) ] <EOL> def elaborate_logic ( s ) : <EOL> outport_num = <NUM_LIT:0> <EOL> for i in range ( <NUM_LIT:0> , s . nbits , s . groupings ) : <EOL> s . connect ( s . out [ outport_num ] , s . in_ [ i : i + s . groupings ] ) <EOL> outport_num += <NUM_LIT:1> <EOL> def test_ComplexBitBlast_8_to_8x1 ( setup_sim ) : <EOL> model , sim = setup_bit_blast ( setup_sim , <NUM_LIT:8> , <NUM_LIT:1> ) <EOL> model . in_ . value = <NUM_LIT> <EOL> sim . eval_combinational ( ) <EOL> verify_bit_blast ( model . out , <NUM_LIT> ) <EOL> model . in_ . value = <NUM_LIT> <EOL> sim . eval_combinational ( ) <EOL> verify_bit_blast ( model . out , <NUM_LIT> ) <EOL> def test_ComplexBitBlast_8_to_4x2 ( setup_sim ) : <EOL> model , sim = setup_bit_blast ( setup_sim , <NUM_LIT:8> , <NUM_LIT:2> ) <EOL> model . in_ . value = <NUM_LIT> <EOL> sim . eval_combinational ( ) <EOL> verify_bit_blast ( model . out , <NUM_LIT> ) <EOL> model . in_ . value = <NUM_LIT> <EOL> sim . eval_combinational ( ) <EOL> verify_bit_blast ( model . out , <NUM_LIT> ) <EOL> def test_ComplexBitBlast_8_to_2x4 ( setup_sim ) : <EOL> model , sim = setup_bit_blast ( setup_sim , <NUM_LIT:8> , <NUM_LIT:4> ) <EOL> model . in_ . value = <NUM_LIT> <EOL> sim . eval_combinational ( ) <EOL> verify_bit_blast ( model . out , <NUM_LIT> ) <EOL> model . in_ . value = <NUM_LIT> <EOL> sim . eval_combinational ( ) <EOL> verify_bit_blast ( model . out , <NUM_LIT> ) <EOL> def test_ComplexBitBlast_8_to_1x8 ( setup_sim ) : <EOL> model , sim = setup_bit_blast ( setup_sim , <NUM_LIT:8> , <NUM_LIT:8> ) <EOL> model . in_ . value = <NUM_LIT> <EOL> sim . eval_combinational ( ) <EOL> verify_bit_blast ( model . out , <NUM_LIT> ) <EOL> model . in_ . value = <NUM_LIT> <EOL> sim . eval_combinational ( ) <EOL> verify_bit_blast ( model . out , <NUM_LIT> ) <EOL> def setup_bit_merge ( setup_sim , nbits , groups = None ) : <EOL> if not groups : <EOL> model = SimpleBitMergeStruct ( nbits ) <EOL> else : <EOL> model = ComplexBitMergeStruct ( nbits , groups ) <EOL> model , sim = setup_sim ( model ) <EOL> return model , sim <EOL> class SimpleBitMergeStruct ( Model ) : <EOL> def __init__ ( s , nbits ) : <EOL> s . nbits = nbits <EOL> s . in_ = [ InPort ( <NUM_LIT:1> ) for x in xrange ( nbits ) ] <EOL> s . out = OutPort ( nbits ) <EOL> def elaborate_logic ( s ) : <EOL> for i in range ( s . nbits ) : <EOL> s . connect ( s . out [ i ] , s . in_ [ i ] ) <EOL> def test_SimpleBitMerge_8x1_to_8 ( setup_sim ) : <EOL> model , sim = setup_bit_merge ( setup_sim , <NUM_LIT:8> ) <EOL> set_ports ( model . in_ , <NUM_LIT> ) <EOL> sim . eval_combinational ( ) <EOL> assert model . out . value == <NUM_LIT> <EOL> set_ports ( model . in_ , <NUM_LIT> ) <EOL> sim . eval_combinational ( ) <EOL> assert model . out . value == <NUM_LIT> <EOL> model . in_ [ <NUM_LIT:0> ] . value = <NUM_LIT:0> <EOL> sim . eval_combinational ( ) <EOL> assert model . out . value == <NUM_LIT> <EOL> model . in_ [ <NUM_LIT:7> ] . value = <NUM_LIT:1> <EOL> sim . eval_combinational ( ) <EOL> assert model . out . value == <NUM_LIT> <EOL> def test_SimpleBitMerge_16x1_to_16 ( setup_sim ) : <EOL> model , sim = setup_bit_merge ( setup_sim , <NUM_LIT:16> ) <EOL> set_ports ( model . in_ , <NUM_LIT> ) <EOL> sim . eval_combinational ( ) <EOL> assert model . out . value == <NUM_LIT> <EOL> set_ports ( model . in_ , <NUM_LIT> ) <EOL> sim . eval_combinational ( ) <EOL> assert model . out . value == <NUM_LIT> <EOL> model . in_ [ <NUM_LIT:0> ] . value = <NUM_LIT:1> <EOL> sim . eval_combinational ( ) <EOL> assert model . out . value == <NUM_LIT> <EOL> model . in_ [ <NUM_LIT:15> ] . value = <NUM_LIT:0> <EOL> sim . eval_combinational ( ) <EOL> assert model . out . value == <NUM_LIT> <EOL> class ComplexBitMergeStruct ( Model ) : <EOL> def __init__ ( s , nbits , groupings ) : <EOL> s . nbits = nbits <EOL> s . groupings = groupings <EOL> s . in_ = [ InPort ( groupings ) for x in <EOL> xrange ( <NUM_LIT:0> , nbits , groupings ) ] <EOL> s . out = OutPort ( nbits ) <EOL> def elaborate_logic ( s ) : <EOL> inport_num = <NUM_LIT:0> <EOL> for i in range ( <NUM_LIT:0> , s . nbits , s . groupings ) : <EOL> s . connect ( s . out [ i : i + s . groupings ] , s . in_ [ inport_num ] ) <EOL> inport_num += <NUM_LIT:1> <EOL> def test_ComplexBitMerge_8x1_to_8 ( setup_sim ) : <EOL> model , sim = setup_bit_merge ( setup_sim , <NUM_LIT:8> , <NUM_LIT:1> ) <EOL> set_ports ( model . in_ , <NUM_LIT> ) <EOL> sim . eval_combinational ( ) <EOL> assert model . out . v == <NUM_LIT> <EOL> set_ports ( model . in_ , <NUM_LIT> ) <EOL> sim . eval_combinational ( ) <EOL> assert model . out . value == <NUM_LIT> <EOL> def test_ComplexBitMerge_4x2_to_8 ( setup_sim ) : <EOL> model , sim = setup_bit_merge ( setup_sim , <NUM_LIT:8> , <NUM_LIT:2> ) <EOL> set_ports ( model . in_ , <NUM_LIT> ) <EOL> sim . eval_combinational ( ) <EOL> assert model . out . v == <NUM_LIT> <EOL> set_ports ( model . in_ , <NUM_LIT> ) <EOL> sim . eval_combinational ( ) <EOL> assert model . out . value == <NUM_LIT> <EOL> def test_ComplexBitMerge_2x4_to_8 ( setup_sim ) : <EOL> model , sim = setup_bit_merge ( setup_sim , <NUM_LIT:8> , <NUM_LIT:4> ) <EOL> set_ports ( model . in_ , <NUM_LIT> ) <EOL> sim . eval_combinational ( ) <EOL> assert model . out . v == <NUM_LIT> <EOL> set_ports ( model . in_ , <NUM_LIT> ) <EOL> sim . eval_combinational ( ) <EOL> assert model . out . value == <NUM_LIT> <EOL> def test_ComplexBitMerge_1x8_to_8 ( setup_sim ) : <EOL> model , sim = setup_bit_merge ( setup_sim , <NUM_LIT:8> , <NUM_LIT:8> ) <EOL> set_ports ( model . in_ , <NUM_LIT> ) <EOL> sim . eval_combinational ( ) <EOL> assert model . out . v == <NUM_LIT> <EOL> set_ports ( model . in_ , <NUM_LIT> ) <EOL> sim . eval_combinational ( ) <EOL> assert model . out . value == <NUM_LIT> <EOL> class ConstantPort ( Model ) : <EOL> def __init__ ( s ) : <EOL> s . out = OutPort ( <NUM_LIT:32> ) <EOL> def elaborate_logic ( s ) : <EOL> s . connect ( s . out , <NUM_LIT:4> ) <EOL> def test_ConstantPort ( setup_sim ) : <EOL> model = ConstantPort ( ) <EOL> model , sim = setup_sim ( model ) <EOL> if is_translated ( model ) : <EOL> sim . eval_combinational ( ) <EOL> assert model . out == <NUM_LIT:4> <EOL> sim . cycle ( ) <EOL> assert model . out == <NUM_LIT:4> <EOL> class ConstantSlice ( Model ) : <EOL> def __init__ ( s ) : <EOL> s . out = OutPort ( <NUM_LIT:32> ) <EOL> def elaborate_logic ( s ) : <EOL> s . connect ( s . out [ <NUM_LIT:0> : <NUM_LIT:16> ] , <NUM_LIT:4> ) <EOL> s . connect ( s . out [ <NUM_LIT:16> : <NUM_LIT:32> ] , <NUM_LIT:8> ) <EOL> def test_ConstantSlice ( setup_sim ) : <EOL> model = ConstantSlice ( ) <EOL> model , sim = setup_sim ( model ) <EOL> if is_translated ( model ) : <EOL> sim . eval_combinational ( ) <EOL> assert model . out . v [ <NUM_LIT:0> : <NUM_LIT:16> ] == <NUM_LIT:4> <EOL> assert model . out . v [ <NUM_LIT:16> : <NUM_LIT:32> ] == <NUM_LIT:8> <EOL> sim . cycle ( ) <EOL> assert model . out . v [ <NUM_LIT:0> : <NUM_LIT:16> ] == <NUM_LIT:4> <EOL> assert model . out . v [ <NUM_LIT:16> : <NUM_LIT:32> ] == <NUM_LIT:8> <EOL> class Shifter ( Model ) : <EOL> def __init__ ( s , inout_nbits = <NUM_LIT:1> , shamt_nbits = <NUM_LIT:1> ) : <EOL> s . in_ = InPort ( inout_nbits ) <EOL> s . shamt = InPort ( shamt_nbits ) <EOL> s . out = OutPort ( inout_nbits ) <EOL> def elaborate_logic ( s ) : <EOL> @ s . combinational <EOL> def comb_logic ( ) : <EOL> s . out . v = s . in_ << s . shamt <EOL> class ConstantModule ( Model ) : <EOL> def __init__ ( s ) : <EOL> s . in_ = InPort ( <NUM_LIT:8> ) <EOL> s . out = OutPort ( <NUM_LIT:8> ) <EOL> def elaborate_logic ( s ) : <EOL> s . shift = m = Shifter ( <NUM_LIT:8> , <NUM_LIT:2> ) <EOL> s . connect_dict ( { <EOL> m . in_ : s . in_ , <EOL> m . shamt : <NUM_LIT:2> , <EOL> m . out : s . out , <EOL> } ) <EOL> def test_ConstantModule ( setup_sim ) : <EOL> model = ConstantModule ( ) <EOL> model , sim = setup_sim ( model ) <EOL> sim . reset ( ) <EOL> model . in_ . v = <NUM_LIT> <EOL> sim . eval_combinational ( ) <EOL> assert model . out == <NUM_LIT> <EOL> sim . cycle ( ) <EOL> model . in_ . v = <NUM_LIT> <EOL> sim . cycle ( ) <EOL> assert model . out == <NUM_LIT> <EOL> model . in_ . v = <NUM_LIT> <EOL> sim . cycle ( ) <EOL> assert model . out == <NUM_LIT> <EOL> sim . cycle ( ) <EOL> from ... model . PortBundle_test import InValRdyBundle , OutValRdyBundle <EOL> def test_ListOfPortBundles ( setup_sim ) : <EOL> class ListOfPortBundlesStruct ( Model ) : <EOL> def __init__ ( s ) : <EOL> s . in_ = [ InValRdyBundle ( <NUM_LIT:8> ) for x in range ( <NUM_LIT:4> ) ] <EOL> s . out = [ OutValRdyBundle ( <NUM_LIT:8> ) for x in range ( <NUM_LIT:4> ) ] <EOL> for i in range ( <NUM_LIT:4> ) : <EOL> s . connect ( s . in_ [ i ] , s . out [ i ] ) <EOL> model = ListOfPortBundlesStruct ( ) <EOL> model , sim = setup_sim ( model ) <EOL> sim . reset ( ) <EOL> for i in range ( <NUM_LIT:4> ) : <EOL> model . in_ [ i ] . msg . v = i <EOL> if is_translated ( model ) : <EOL> sim . eval_combinational ( ) <EOL> for i in range ( <NUM_LIT:4> ) : <EOL> assert model . out [ i ] . msg . v == i <EOL> def test_ConnectPairs ( setup_sim ) : <EOL> class ConnectPairs ( Model ) : <EOL> def __init__ ( s , config ) : <EOL> s . a = InPort [ <NUM_LIT:4> ] ( <NUM_LIT:8> ) <EOL> s . b = OutPort [ <NUM_LIT:4> ] ( <NUM_LIT:8> ) <EOL> if config == '<STR_LIT>' : <EOL> s . connect_pairs ( <EOL> s . a [ <NUM_LIT:0> ] , s . b [ <NUM_LIT:0> ] , <EOL> s . a [ <NUM_LIT:1> ] , s . b [ <NUM_LIT:1> ] , <EOL> s . a [ <NUM_LIT:2> ] , s . b [ <NUM_LIT:2> ] , <EOL> s . a [ <NUM_LIT:3> ] , s . b [ <NUM_LIT:3> ] , <EOL> ) <EOL> elif config == '<STR_LIT>' : <EOL> s . connect_pairs ( <EOL> s . a [ <NUM_LIT:0> ] , s . b [ <NUM_LIT:0> ] , <EOL> s . a [ <NUM_LIT:1> ] , s . b [ <NUM_LIT:1> ] , <EOL> s . a [ <NUM_LIT:2> ] , s . b [ <NUM_LIT:2> ] , <EOL> s . a [ <NUM_LIT:3> ] , <EOL> ) <EOL> with pytest . raises ( pymtl . model . ConnectionEdge . PyMTLConnectError ) : <EOL> model = ConnectPairs ( '<STR_LIT>' ) <EOL> model = ConnectPairs ( '<STR_LIT>' ) <EOL> model , sim = setup_sim ( model ) <EOL> sim . reset ( ) <EOL> for i in range ( <NUM_LIT:5> ) : <EOL> for j in range ( <NUM_LIT:4> ) : model . a [ j ] . value = i + j <EOL> sim . cycle ( ) <EOL> for j in range ( <NUM_LIT:4> ) : model . b [ j ] == i + j <EOL> class BitStructGlobal ( BitStructDefinition ) : <EOL> def __init__ ( s , src_nbits , dest_nbits ) : <EOL> s . src = BitField ( src_nbits ) <EOL> s . dest = BitField ( dest_nbits ) <EOL> class BitStructConnect ( Model ) : <EOL> def __init__ ( s , MsgType ) : <EOL> s . in_ = InPort ( MsgType ) <EOL> s . out = OutPort ( MsgType ) <EOL> s . connect ( s . in_ . src , s . out . dest ) <EOL> s . connect ( s . in_ . dest , s . out . src ) <EOL> def bitstruct_verifier ( model , sim , src , dest ) : <EOL> max_ = <NUM_LIT:2> ** src <EOL> for i in range ( <NUM_LIT:10> ) : <EOL> src , dest = randrange ( <NUM_LIT:0> , max_ ) , randrange ( <NUM_LIT:0> , max_ ) <EOL> model . in_ . src . value = src <EOL> model . in_ . dest . value = dest <EOL> sim . cycle ( ) <EOL> print model . in_ . src , model . out . src , src <EOL> print model . in_ . dest , model . out . dest , dest <EOL> assert model . out . src == dest <EOL> assert model . out . dest == src <EOL> @ pytest . mark . parametrize ( '<STR_LIT>' , [ ( <NUM_LIT:8> , <NUM_LIT:8> ) , ( <NUM_LIT:16> , <NUM_LIT:16> ) ] ) <EOL> def test_BitStructGlobal ( setup_sim , src , dest ) : <EOL> model = BitStructConnect ( BitStructGlobal ( src , dest ) ) <EOL> model , sim = setup_sim ( model ) <EOL> bitstruct_verifier ( model , sim , src , dest ) <EOL> @ pytest . mark . parametrize ( '<STR_LIT>' , [ ( <NUM_LIT:8> , <NUM_LIT:8> ) , ( <NUM_LIT:16> , <NUM_LIT:16> ) ] ) <EOL> def test_BitStructLocal ( setup_sim , src , dest ) : <EOL> class BitStructLocal ( BitStructDefinition ) : <EOL> def __init__ ( s , src_nbits , dest_nbits ) : <EOL> s . src = BitField ( src_nbits ) <EOL> s . dest = BitField ( dest_nbits ) <EOL> model = BitStructConnect ( BitStructLocal ( src , dest ) ) <EOL> model , sim = setup_sim ( model ) <EOL> bitstruct_verifier ( model , sim , src , dest ) </s>
