<s> from migen import * <EOL> from migen . fhdl import verilog <EOL> class SimCase : <EOL> def setUp ( self , * args , ** kwargs ) : <EOL> self . tb = self . TestBench ( * args , ** kwargs ) <EOL> def test_to_verilog ( self ) : <EOL> verilog . convert ( self . tb ) <EOL> def run_with ( self , generator ) : <EOL> run_simulation ( self . tb , generator ) </s>
