<s> from __future__ import absolute_import <EOL> from __future__ import print_function <EOL> import sys <EOL> import os <EOL> import math <EOL> sys . path . insert ( <NUM_LIT:0> , os . path . dirname ( os . path . dirname ( os . path . dirname ( os . path . dirname ( os . path . dirname ( os . path . abspath ( __file__ ) ) ) ) ) ) ) <EOL> from veriloggen import * <EOL> def mkLed ( numports = <NUM_LIT:8> , delay_amount = <NUM_LIT:2> ) : <EOL> m = Module ( '<STR_LIT>' ) <EOL> clk = m . Input ( '<STR_LIT>' ) <EOL> rst = m . Input ( '<STR_LIT>' ) <EOL> led = [ m . OutputReg ( '<STR_LIT>' + str ( i ) , initval = <NUM_LIT:0> ) for i in range ( numports ) ] <EOL> up = m . Wire ( '<STR_LIT>' ) <EOL> down = m . Wire ( '<STR_LIT>' ) <EOL> m . Assign ( up ( <NUM_LIT:1> ) ) <EOL> m . Assign ( down ( <NUM_LIT:0> ) ) <EOL> seq = Seq ( m , '<STR_LIT>' , clk , rst ) <EOL> count = m . Reg ( '<STR_LIT:count>' , ( numports - <NUM_LIT:1> ) . bit_length ( ) , initval = <NUM_LIT:0> ) <EOL> seq . add ( count . inc ( ) ) <EOL> for i in range ( numports ) : <EOL> seq . add ( led [ i ] ( up ) , cond = ( count == i ) , eager_val = True ) <EOL> seq . add ( led [ i ] ( down ) , cond = ( count == i ) , delay = delay_amount , eager_val = True ) <EOL> if i > <NUM_LIT:1> : <EOL> seq . add ( led [ i ] ( up ) , cond = ( count == <NUM_LIT:0> ) , delay = delay_amount , eager_val = True ) <EOL> seq . make_always ( ) <EOL> return m <EOL> def mkTest ( ) : <EOL> m = Module ( '<STR_LIT:test>' ) <EOL> led = mkLed ( ) <EOL> params = m . copy_params ( led ) <EOL> ports = m . copy_sim_ports ( led ) <EOL> clk = ports [ '<STR_LIT>' ] <EOL> rst = ports [ '<STR_LIT>' ] <EOL> uut = m . Instance ( led , '<STR_LIT>' , <EOL> params = m . connect_params ( led ) , <EOL> ports = m . connect_ports ( led ) ) <EOL> simulation . setup_waveform ( m , uut ) <EOL> simulation . setup_clock ( m , clk , hperiod = <NUM_LIT:5> ) <EOL> init = simulation . setup_reset ( m , rst , period = <NUM_LIT:100> ) <EOL> nclk = simulation . next_clock <EOL> init . add ( <EOL> Delay ( <NUM_LIT:1000> ) , <EOL> Systask ( '<STR_LIT>' ) , <EOL> ) <EOL> return m <EOL> if __name__ == '<STR_LIT:__main__>' : <EOL> test = mkTest ( ) <EOL> verilog = test . to_verilog ( '<STR_LIT>' ) <EOL> print ( verilog ) </s>
