<s> from __future__ import absolute_import <EOL> from __future__ import print_function <EOL> import simulation_simulator <EOL> from veriloggen import * <EOL> expected_verilog = """<STR_LIT>""" <EOL> expected_rslt = """<STR_LIT>""" <EOL> def test ( ) : <EOL> test_module = simulation_simulator . mkTest ( ) <EOL> code = test_module . to_verilog ( ) <EOL> from pyverilog . vparser . parser import VerilogParser <EOL> from pyverilog . ast_code_generator . codegen import ASTCodeGenerator <EOL> parser = VerilogParser ( ) <EOL> expected_ast = parser . parse ( expected_verilog ) <EOL> codegen = ASTCodeGenerator ( ) <EOL> expected_code = codegen . visit ( expected_ast ) <EOL> assert ( expected_code == code ) <EOL> sim = simulation . Simulator ( test_module ) <EOL> rslt = sim . run ( ) <EOL> assert ( expected_rslt == rslt ) </s>
