<s> from migen import * <EOL> from migen . fhdl import verilog <EOL> from migen . genlib . divider import Divider <EOL> class CDM ( Module ) : <EOL> def __init__ ( self ) : <EOL> self . submodules . divider = Divider ( <NUM_LIT:5> ) <EOL> self . clock_domains . cd_sys = ClockDomain ( reset_less = True ) <EOL> class MultiMod ( Module ) : <EOL> def __init__ ( self ) : <EOL> self . submodules . foo = CDM ( ) <EOL> self . submodules . bar = CDM ( ) <EOL> if __name__ == "<STR_LIT:__main__>" : <EOL> mm = MultiMod ( ) <EOL> print ( verilog . convert ( mm , { mm . foo . cd_sys . clk , mm . bar . cd_sys . clk } ) ) </s>
