<s> import os , glob , cape_manager , bbio <EOL> from config import UART , DEC , BIN , OCT , HEX <EOL> try : <EOL> import serial <EOL> except : <EOL> print "<STR_LIT>" <EOL> def uartInit ( uart ) : <EOL> """<STR_LIT>""" <EOL> port , overlay = UART [ uart ] <EOL> if os . path . exists ( port ) : return True <EOL> cape_manager . load ( overlay , auto_unload = False ) <EOL> if os . path . exists ( port ) : return True <EOL> for i in range ( <NUM_LIT:5> ) : <EOL> bbio . delay ( <NUM_LIT:100> ) <EOL> if os . path . exists ( port ) : return True <EOL> return False <EOL> class _UART_PORT ( object ) : <EOL> def __init__ ( self , uart ) : <EOL> assert uart in UART , "<STR_LIT>" % uart <EOL> self . config = uart <EOL> self . baud = <NUM_LIT:0> <EOL> self . open = False <EOL> self . ser_port = None <EOL> self . peek_char = '<STR_LIT>' <EOL> def begin ( self , baud , timeout = <NUM_LIT:1> , ** kwargs ) : <EOL> """<STR_LIT>""" <EOL> if self . open : return <EOL> if not uartInit ( self . config ) : <EOL> print "<STR_LIT>" % self . config <EOL> self . ser_port = None <EOL> return <EOL> port = UART [ self . config ] [ <NUM_LIT:0> ] <EOL> self . baud = baud <EOL> self . ser_port = serial . Serial ( port , baud , timeout = timeout , ** kwargs ) <EOL> self . open = True <EOL> def end ( self ) : <EOL> """<STR_LIT>""" <EOL> if not ( self . open ) : return <EOL> self . flush ( ) <EOL> self . ser_port . close ( ) <EOL> self . ser_port = None <EOL> self . baud = <NUM_LIT:0> <EOL> self . open = False <EOL> def available ( self ) : <EOL> """<STR_LIT>""" <EOL> return self . ser_port . inWaiting ( ) + len ( self . peek_char ) <EOL> def read ( self ) : <EOL> """<STR_LIT>""" <EOL> if ( self . peek_char ) : <EOL> c = self . peek_char <EOL> self . peek_char = '<STR_LIT>' <EOL> return c <EOL> byte = self . ser_port . read ( <NUM_LIT:1> ) <EOL> return - <NUM_LIT:1> if ( byte == None ) else byte <EOL> def peek ( self ) : <EOL> """<STR_LIT>""" <EOL> if ( self . peek_char ) : <EOL> return self . peek_char <EOL> if self . available ( ) : <EOL> self . peek_char = self . ser_port . read ( <NUM_LIT:1> ) <EOL> return self . peek_char <EOL> return - <NUM_LIT:1> <EOL> def flush ( self ) : <EOL> """<STR_LIT>""" <EOL> self . ser_port . flush ( ) <EOL> self . peek_char = '<STR_LIT>' <EOL> def prints ( self , data , base = None ) : <EOL> """<STR_LIT>""" <EOL> return self . write ( self . _process ( data , base ) ) <EOL> def println ( self , data , base = None ) : <EOL> """<STR_LIT>""" <EOL> return self . write ( self . _process ( data , base ) + "<STR_LIT:\r\n>" ) <EOL> def write ( self , data ) : <EOL> """<STR_LIT>""" <EOL> assert self . open , "<STR_LIT>" % UART [ self . config ] [ <NUM_LIT:0> ] <EOL> if ( type ( data ) == float ) : data = int ( data ) <EOL> if ( type ( data ) == int ) : data = chr ( data & <NUM_LIT> ) <EOL> elif ( ( type ( data ) == list ) or ( type ( data ) == tuple ) ) : <EOL> bytes_written = <NUM_LIT:0> <EOL> for i in data : <EOL> bytes_written += self . write ( i ) <EOL> return bytes_written <EOL> elif ( type ( data ) != str ) : <EOL> return <NUM_LIT:0> <EOL> written = self . ser_port . write ( data ) <EOL> return written if written else <NUM_LIT:0> <EOL> def _process ( self , data , base ) : <EOL> """<STR_LIT>""" <EOL> if ( type ( data ) == str ) : <EOL> return data <EOL> if ( type ( data ) is int ) : <EOL> if not ( base ) : base = DEC <EOL> if ( base == DEC ) : <EOL> return str ( data ) <EOL> if ( base == BIN ) : <EOL> return bin ( data ) [ <NUM_LIT:2> : ] <EOL> if ( base == OCT ) : <EOL> return oct ( data ) [ <NUM_LIT:1> : ] <EOL> if ( base == HEX ) : <EOL> return hex ( data ) [ <NUM_LIT:2> : ] <EOL> elif ( type ( data ) is float ) : <EOL> if not ( base ) : base = <NUM_LIT:2> <EOL> if ( ( base == <NUM_LIT:0> ) ) : <EOL> return str ( int ( data ) ) <EOL> if ( ( type ( base ) == int ) and ( base > <NUM_LIT:0> ) ) : <EOL> return ( "<STR_LIT>" + ( "<STR_LIT>" % base ) + "<STR_LIT:f>" ) % data <EOL> return str ( data ) <EOL> Serial1 = _UART_PORT ( '<STR_LIT>' ) <EOL> Serial2 = _UART_PORT ( '<STR_LIT>' ) <EOL> Serial4 = _UART_PORT ( '<STR_LIT>' ) <EOL> Serial5 = _UART_PORT ( '<STR_LIT>' ) <EOL> def serial_cleanup ( ) : <EOL> """<STR_LIT>""" <EOL> for port in ( Serial1 , Serial2 , Serial4 , Serial5 ) : <EOL> port . end ( ) </s>
