<s> """<STR_LIT>""" <EOL> import core . modules <EOL> import core . modules . module_registry <EOL> from core . modules . vistrails_module import Module , ModuleError <EOL> import TetGen <EOL> import CreateTestSurf <EOL> identifier = '<STR_LIT>' <EOL> version = '<STR_LIT>' <EOL> name = '<STR_LIT>' <EOL> class tetgenio_wrapper ( Module ) : <EOL> def __init__ ( self ) : <EOL> self . data = TetGen . tetgenio ( ) <EOL> class tetrahedralize ( Module ) : <EOL> """<STR_LIT>""" <EOL> def __init__ ( self ) : <EOL> Module . __init__ ( self ) <EOL> def compute ( self ) : <EOL> switches = None <EOL> if self . has_input ( "<STR_LIT>" ) : <EOL> switches = self . get_input ( "<STR_LIT>" ) <EOL> print switches <EOL> if self . has_input ( "<STR_LIT>" ) : <EOL> tgio_in = self . get_input ( "<STR_LIT>" ) . data <EOL> print "<STR_LIT>" % tgio_in . numberofpoints <EOL> tgio_in . save_nodes ( "<STR_LIT>" ) <EOL> tgio_in . save_poly ( "<STR_LIT>" ) <EOL> out = tetgenio_wrapper ( ) <EOL> TetGen . tetrahedralize ( switches , tgio_in , out . data ) <EOL> print "<STR_LIT>" <EOL> self . set_output ( "<STR_LIT>" , out ) <EOL> def initialize ( * args , ** keywords ) : <EOL> reg = core . modules . module_registry <EOL> reg . add_module ( tetrahedralize ) <EOL> reg . add_input_port ( tetrahedralize , "<STR_LIT>" , <EOL> ( core . modules . basic_modules . String , '<STR_LIT>' ) ) <EOL> reg . add_input_port ( tetrahedralize , "<STR_LIT>" , <EOL> ( tetgenio_wrapper , '<STR_LIT>' ) ) <EOL> reg . add_output_port ( tetrahedralize , "<STR_LIT>" , <EOL> ( tetgenio_wrapper , '<STR_LIT>' ) ) <EOL> reg . add_module ( tetgenio_wrapper ) <EOL> CreateTestSurf . initialize ( reg ) </s>
