<s> from __future__ import division <EOL> from vistrails . core . modules . vistrails_module import Module , ModuleError <EOL> from vistrails . core . modules . config import IPort , OPort <EOL> class PythonCalc ( Module ) : <EOL> """<STR_LIT>""" <EOL> _input_ports = [ IPort ( name = "<STR_LIT>" , signature = "<STR_LIT>" ) , <EOL> IPort ( name = "<STR_LIT>" , signature = "<STR_LIT>" ) , <EOL> IPort ( name = "<STR_LIT>" , signature = "<STR_LIT>" , <EOL> entry_type = "<STR_LIT>" , values = [ "<STR_LIT:+>" , "<STR_LIT:->" , "<STR_LIT:*>" , "<STR_LIT:/>" ] ) ] <EOL> _output_ports = [ OPort ( name = "<STR_LIT:value>" , signature = "<STR_LIT>" ) ] <EOL> def __init__ ( self ) : <EOL> Module . __init__ ( self ) <EOL> def compute ( self ) : <EOL> v1 = self . get_input ( "<STR_LIT>" ) <EOL> v2 = self . get_input ( "<STR_LIT>" ) <EOL> self . set_output ( "<STR_LIT:value>" , self . op ( v1 , v2 ) ) <EOL> def op ( self , v1 , v2 ) : <EOL> op = self . get_input ( "<STR_LIT>" ) <EOL> if op == '<STR_LIT:+>' : <EOL> return v1 + v2 <EOL> elif op == '<STR_LIT:->' : <EOL> return v1 - v2 <EOL> elif op == '<STR_LIT:*>' : <EOL> return v1 * v2 <EOL> elif op == '<STR_LIT:/>' : <EOL> return v1 / v2 <EOL> raise ModuleError ( self , "<STR_LIT>" % op ) <EOL> _modules = [ PythonCalc , ] </s>
