Question: The access matrix approach to protection has the difficulty that

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: The access matrix approach to protection has the difficulty that
 A. the matrix, if stored directly, is large and can be clumsy to manage
 B. it is not capable of expressing complex protection requirements
 C. deciding whether a process has access to a resource is undecidable
 D. there is no way to express who has rights to change the access matrix itself
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: The access matrix approach to protection has the difficulty that
 A. the matrix, if stored directly, is large and can be clumsy to manage
 B. it is not capable of expressing complex protection requirements
 C. deciding whether a process has access to a resource is undecidable
 D. there is no way to express who has rights to change the access matrix itself
Answer:


Question: The access matrix approach to protection has the difficulty that

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: The access matrix approach to protection has the difficulty that
 A. the matrix, if stored directly, is large and can be clumsy to manage
 B. it is not capable of expressing complex protection requirements
 C. deciding whether a process has access to a resource is undecidable
 D. there is no way to express who has rights to change the access matrix itself
Answer:


Question: The access matrix approach to protection has the difficulty that

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: The access matrix approach to protection has the difficulty that
 A. the matrix, if stored directly, is large and can be clumsy to manage
 B. it is not capable of expressing complex protection requirements
 C. deciding whether a process has access to a resource is undecidable
 D. there is no way to express who has rights to change the access matrix itself
Answer:


Question: The access matrix approach to protection has the difficulty that

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: The access matrix approach to protection has the difficulty that
 A. the matrix, if stored directly, is large and can be clumsy to manage
 B. it is not capable of expressing complex protection requirements
 C. deciding whether a process has access to a resource is undecidable
 D. there is no way to express who has rights to change the access matrix itself
Answer:


Question: An integer c is a common divisor of two integers x and y if and only if c is a divisor of x and c is a divisor of y. Which of the following sets of integers could possibly be the set of all common divisors of two integers?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: An integer c is a common divisor of two integers x and y if and only if c is a divisor of x and c is a divisor of y. Which of the following sets of integers could possibly be the set of all common divisors of two integers?
 A. {-6,-2, -1, 1, 2, 6}
 B. {-6, -2, -1, 0, 1, 2, 6}
 C. {-6, -3, -2, -1, 1, 2, 3, 6}
 D. {-6, -3, -2, -1, 0, 1, 2, 3, 6}
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: An integer c is a common divisor of two integers x and y if and only if c is a divisor of x and c is a divisor of y. Which of the following sets of integers could possibly be the set of all common divisors of two integers?
 A. {-6,-2, -1, 1, 2, 6}
 B. {-6, -2, -1, 0, 1, 2, 6}
 C. {-6, -3, -2, -1, 1, 2, 3, 6}
 D. {-6, -3, -2, -1, 0, 1, 2, 3, 6}
Answer:


Question: An integer c is a common divisor of two integers x and y if and only if c is a divisor of x and c is a divisor of y. Which of the following sets of integers could possibly be the set of all common divisors of two integers?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: An integer c is a common divisor of two integers x and y if and only if c is a divisor of x and c is a divisor of y. Which of the following sets of integers could possibly be the set of all common divisors of two integers?
 A. {-6,-2, -1, 1, 2, 6}
 B. {-6, -2, -1, 0, 1, 2, 6}
 C. {-6, -3, -2, -1, 1, 2, 3, 6}
 D. {-6, -3, -2, -1, 0, 1, 2, 3, 6}
Answer:


Question: An integer c is a common divisor of two integers x and y if and only if c is a divisor of x and c is a divisor of y. Which of the following sets of integers could possibly be the set of all common divisors of two integers?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: An integer c is a common divisor of two integers x and y if and only if c is a divisor of x and c is a divisor of y. Which of the following sets of integers could possibly be the set of all common divisors of two integers?
 A. {-6,-2, -1, 1, 2, 6}
 B. {-6, -2, -1, 0, 1, 2, 6}
 C. {-6, -3, -2, -1, 1, 2, 3, 6}
 D. {-6, -3, -2, -1, 0, 1, 2, 3, 6}
Answer:


Question: An integer c is a common divisor of two integers x and y if and only if c is a divisor of x and c is a divisor of y. Which of the following sets of integers could possibly be the set of all common divisors of two integers?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: An integer c is a common divisor of two integers x and y if and only if c is a divisor of x and c is a divisor of y. Which of the following sets of integers could possibly be the set of all common divisors of two integers?
 A. {-6,-2, -1, 1, 2, 6}
 B. {-6, -2, -1, 0, 1, 2, 6}
 C. {-6, -3, -2, -1, 1, 2, 3, 6}
 D. {-6, -3, -2, -1, 0, 1, 2, 3, 6}
Answer:


Question:
In the NoNicks operating system, the time required by a single file-read operation has four nonoverlapping components:
disk seek time-25 msec
disk latency time-8 msec
disk transfer time- 1 msec per 1,000 bytes
operating system overhead-1 msec per 1,000 bytes + 10 msec
In version 1 of the system, the file read retrieved blocks of 1,000 bytes. In version 2, the file read (along with the underlying layout on disk) was modified to retrieve blocks of 4,000 bytes. The ratio of-the time required to read a large file under version 2 to the time required to read the same large file under version 1 is approximately

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: In the NoNicks operating system, the time required by a single file-read operation has four nonoverlapping components:
disk seek time-25 msec
disk latency time-8 msec
disk transfer time- 1 msec per 1,000 bytes
operating system overhead-1 msec per 1,000 bytes + 10 msec
In version 1 of the system, the file read retrieved blocks of 1,000 bytes. In version 2, the file read (along with the underlying layout on disk) was modified to retrieve blocks of 4,000 bytes. The ratio of-the time required to read a large file under version 2 to the time required to read the same large file under version 1 is approximately
 A. 1:4
 B. 1:3.5
 C. 1:1
 D. 1.1:1
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: In the NoNicks operating system, the time required by a single file-read operation has four nonoverlapping components:
disk seek time-25 msec
disk latency time-8 msec
disk transfer time- 1 msec per 1,000 bytes
operating system overhead-1 msec per 1,000 bytes + 10 msec
In version 1 of the system, the file read retrieved blocks of 1,000 bytes. In version 2, the file read (along with the underlying layout on disk) was modified to retrieve blocks of 4,000 bytes. The ratio of-the time required to read a large file under version 2 to the time required to read the same large file under version 1 is approximately
 A. 1:4
 B. 1:3.5
 C. 1:1
 D. 1.1:1
Answer:


Question:
In the NoNicks operating system, the time required by a single file-read operation has four nonoverlapping components:
disk seek time-25 msec
disk latency time-8 msec
disk transfer time- 1 msec per 1,000 bytes
operating system overhead-1 msec per 1,000 bytes + 10 msec
In version 1 of the system, the file read retrieved blocks of 1,000 bytes. In version 2, the file read (along with the underlying layout on disk) was modified to retrieve blocks of 4,000 bytes. The ratio of-the time required to read a large file under version 2 to the time required to read the same large file under version 1 is approximately

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: In the NoNicks operating system, the time required by a single file-read operation has four nonoverlapping components:
disk seek time-25 msec
disk latency time-8 msec
disk transfer time- 1 msec per 1,000 bytes
operating system overhead-1 msec per 1,000 bytes + 10 msec
In version 1 of the system, the file read retrieved blocks of 1,000 bytes. In version 2, the file read (along with the underlying layout on disk) was modified to retrieve blocks of 4,000 bytes. The ratio of-the time required to read a large file under version 2 to the time required to read the same large file under version 1 is approximately
 A. 1:4
 B. 1:3.5
 C. 1:1
 D. 1.1:1
Answer:


Question:
In the NoNicks operating system, the time required by a single file-read operation has four nonoverlapping components:
disk seek time-25 msec
disk latency time-8 msec
disk transfer time- 1 msec per 1,000 bytes
operating system overhead-1 msec per 1,000 bytes + 10 msec
In version 1 of the system, the file read retrieved blocks of 1,000 bytes. In version 2, the file read (along with the underlying layout on disk) was modified to retrieve blocks of 4,000 bytes. The ratio of-the time required to read a large file under version 2 to the time required to read the same large file under version 1 is approximately

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: In the NoNicks operating system, the time required by a single file-read operation has four nonoverlapping components:
disk seek time-25 msec
disk latency time-8 msec
disk transfer time- 1 msec per 1,000 bytes
operating system overhead-1 msec per 1,000 bytes + 10 msec
In version 1 of the system, the file read retrieved blocks of 1,000 bytes. In version 2, the file read (along with the underlying layout on disk) was modified to retrieve blocks of 4,000 bytes. The ratio of-the time required to read a large file under version 2 to the time required to read the same large file under version 1 is approximately
 A. 1:4
 B. 1:3.5
 C. 1:1
 D. 1.1:1
Answer:


Question:
In the NoNicks operating system, the time required by a single file-read operation has four nonoverlapping components:
disk seek time-25 msec
disk latency time-8 msec
disk transfer time- 1 msec per 1,000 bytes
operating system overhead-1 msec per 1,000 bytes + 10 msec
In version 1 of the system, the file read retrieved blocks of 1,000 bytes. In version 2, the file read (along with the underlying layout on disk) was modified to retrieve blocks of 4,000 bytes. The ratio of-the time required to read a large file under version 2 to the time required to read the same large file under version 1 is approximately

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: In the NoNicks operating system, the time required by a single file-read operation has four nonoverlapping components:
disk seek time-25 msec
disk latency time-8 msec
disk transfer time- 1 msec per 1,000 bytes
operating system overhead-1 msec per 1,000 bytes + 10 msec
In version 1 of the system, the file read retrieved blocks of 1,000 bytes. In version 2, the file read (along with the underlying layout on disk) was modified to retrieve blocks of 4,000 bytes. The ratio of-the time required to read a large file under version 2 to the time required to read the same large file under version 1 is approximately
 A. 1:4
 B. 1:3.5
 C. 1:1
 D. 1.1:1
Answer:


Question: You want to cluster 7 points into 3 clusters using the k-Means Clustering algorithm. Suppose after the first iteration, clusters C1, C2 and C3 contain the following two-dimensional points: C1 contains the 2 points: {(0,6), (6,0)} C2 contains the 3 points: {(2,2), (4,4), (6,6)} C3 contains the 2 points: {(5,5), (7,7)} What are the cluster centers computed for these 3 clusters?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: You want to cluster 7 points into 3 clusters using the k-Means Clustering algorithm. Suppose after the first iteration, clusters C1, C2 and C3 contain the following two-dimensional points: C1 contains the 2 points: {(0,6), (6,0)} C2 contains the 3 points: {(2,2), (4,4), (6,6)} C3 contains the 2 points: {(5,5), (7,7)} What are the cluster centers computed for these 3 clusters?
 A. C1: (3,3), C2: (4,4), C3: (6,6)
 B. C1: (3,3), C2: (6,6), C3: (12,12)
 C. C1: (6,6), C2: (12,12), C3: (12,12)
 D. C1: (0,0), C2: (48,48), C3: (35,35)
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: You want to cluster 7 points into 3 clusters using the k-Means Clustering algorithm. Suppose after the first iteration, clusters C1, C2 and C3 contain the following two-dimensional points: C1 contains the 2 points: {(0,6), (6,0)} C2 contains the 3 points: {(2,2), (4,4), (6,6)} C3 contains the 2 points: {(5,5), (7,7)} What are the cluster centers computed for these 3 clusters?
 A. C1: (3,3), C2: (4,4), C3: (6,6)
 B. C1: (3,3), C2: (6,6), C3: (12,12)
 C. C1: (6,6), C2: (12,12), C3: (12,12)
 D. C1: (0,0), C2: (48,48), C3: (35,35)
Answer:


Question: You want to cluster 7 points into 3 clusters using the k-Means Clustering algorithm. Suppose after the first iteration, clusters C1, C2 and C3 contain the following two-dimensional points: C1 contains the 2 points: {(0,6), (6,0)} C2 contains the 3 points: {(2,2), (4,4), (6,6)} C3 contains the 2 points: {(5,5), (7,7)} What are the cluster centers computed for these 3 clusters?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: You want to cluster 7 points into 3 clusters using the k-Means Clustering algorithm. Suppose after the first iteration, clusters C1, C2 and C3 contain the following two-dimensional points: C1 contains the 2 points: {(0,6), (6,0)} C2 contains the 3 points: {(2,2), (4,4), (6,6)} C3 contains the 2 points: {(5,5), (7,7)} What are the cluster centers computed for these 3 clusters?
 A. C1: (3,3), C2: (4,4), C3: (6,6)
 B. C1: (3,3), C2: (6,6), C3: (12,12)
 C. C1: (6,6), C2: (12,12), C3: (12,12)
 D. C1: (0,0), C2: (48,48), C3: (35,35)
Answer:


Question: You want to cluster 7 points into 3 clusters using the k-Means Clustering algorithm. Suppose after the first iteration, clusters C1, C2 and C3 contain the following two-dimensional points: C1 contains the 2 points: {(0,6), (6,0)} C2 contains the 3 points: {(2,2), (4,4), (6,6)} C3 contains the 2 points: {(5,5), (7,7)} What are the cluster centers computed for these 3 clusters?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: You want to cluster 7 points into 3 clusters using the k-Means Clustering algorithm. Suppose after the first iteration, clusters C1, C2 and C3 contain the following two-dimensional points: C1 contains the 2 points: {(0,6), (6,0)} C2 contains the 3 points: {(2,2), (4,4), (6,6)} C3 contains the 2 points: {(5,5), (7,7)} What are the cluster centers computed for these 3 clusters?
 A. C1: (3,3), C2: (4,4), C3: (6,6)
 B. C1: (3,3), C2: (6,6), C3: (12,12)
 C. C1: (6,6), C2: (12,12), C3: (12,12)
 D. C1: (0,0), C2: (48,48), C3: (35,35)
Answer:


Question: You want to cluster 7 points into 3 clusters using the k-Means Clustering algorithm. Suppose after the first iteration, clusters C1, C2 and C3 contain the following two-dimensional points: C1 contains the 2 points: {(0,6), (6,0)} C2 contains the 3 points: {(2,2), (4,4), (6,6)} C3 contains the 2 points: {(5,5), (7,7)} What are the cluster centers computed for these 3 clusters?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: You want to cluster 7 points into 3 clusters using the k-Means Clustering algorithm. Suppose after the first iteration, clusters C1, C2 and C3 contain the following two-dimensional points: C1 contains the 2 points: {(0,6), (6,0)} C2 contains the 3 points: {(2,2), (4,4), (6,6)} C3 contains the 2 points: {(5,5), (7,7)} What are the cluster centers computed for these 3 clusters?
 A. C1: (3,3), C2: (4,4), C3: (6,6)
 B. C1: (3,3), C2: (6,6), C3: (12,12)
 C. C1: (6,6), C2: (12,12), C3: (12,12)
 D. C1: (0,0), C2: (48,48), C3: (35,35)
Answer:


Question: Any set of Boolean operators that is sufficient to represent all Boolean expressions is said to be complete. Which of the following is NOT complete?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Any set of Boolean operators that is sufficient to represent all Boolean expressions is said to be complete. Which of the following is NOT complete?
 A. {AND, NOT}
 B. {NOT, OR}
 C. {AND, OR}
 D. {NAND}
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Any set of Boolean operators that is sufficient to represent all Boolean expressions is said to be complete. Which of the following is NOT complete?
 A. {AND, NOT}
 B. {NOT, OR}
 C. {AND, OR}
 D. {NAND}
Answer:


Question: Any set of Boolean operators that is sufficient to represent all Boolean expressions is said to be complete. Which of the following is NOT complete?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Any set of Boolean operators that is sufficient to represent all Boolean expressions is said to be complete. Which of the following is NOT complete?
 A. {AND, NOT}
 B. {NOT, OR}
 C. {AND, OR}
 D. {NAND}
Answer:


Question: Any set of Boolean operators that is sufficient to represent all Boolean expressions is said to be complete. Which of the following is NOT complete?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Any set of Boolean operators that is sufficient to represent all Boolean expressions is said to be complete. Which of the following is NOT complete?
 A. {AND, NOT}
 B. {NOT, OR}
 C. {AND, OR}
 D. {NAND}
Answer:


Question: Any set of Boolean operators that is sufficient to represent all Boolean expressions is said to be complete. Which of the following is NOT complete?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Any set of Boolean operators that is sufficient to represent all Boolean expressions is said to be complete. Which of the following is NOT complete?
 A. {AND, NOT}
 B. {NOT, OR}
 C. {AND, OR}
 D. {NAND}
Answer:


Question: Consider the collection of all undirected graphs with 10 nodes and 6 edges. Let M and m, respectively, be the maximum and minimum number of connected components in any graph in the collection. If a graph has no selfloops and there is at most one edge between any pair of nodes, which of the following is true?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Consider the collection of all undirected graphs with 10 nodes and 6 edges. Let M and m, respectively, be the maximum and minimum number of connected components in any graph in the collection. If a graph has no selfloops and there is at most one edge between any pair of nodes, which of the following is true?
 A. M = 10, m = 10
 B. M = 10, m = 1
 C. M = 7, m = 4
 D. M = 6, m = 4
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Consider the collection of all undirected graphs with 10 nodes and 6 edges. Let M and m, respectively, be the maximum and minimum number of connected components in any graph in the collection. If a graph has no selfloops and there is at most one edge between any pair of nodes, which of the following is true?
 A. M = 10, m = 10
 B. M = 10, m = 1
 C. M = 7, m = 4
 D. M = 6, m = 4
Answer:


Question: Consider the collection of all undirected graphs with 10 nodes and 6 edges. Let M and m, respectively, be the maximum and minimum number of connected components in any graph in the collection. If a graph has no selfloops and there is at most one edge between any pair of nodes, which of the following is true?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Consider the collection of all undirected graphs with 10 nodes and 6 edges. Let M and m, respectively, be the maximum and minimum number of connected components in any graph in the collection. If a graph has no selfloops and there is at most one edge between any pair of nodes, which of the following is true?
 A. M = 10, m = 10
 B. M = 10, m = 1
 C. M = 7, m = 4
 D. M = 6, m = 4
Answer:


Question: Consider the collection of all undirected graphs with 10 nodes and 6 edges. Let M and m, respectively, be the maximum and minimum number of connected components in any graph in the collection. If a graph has no selfloops and there is at most one edge between any pair of nodes, which of the following is true?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Consider the collection of all undirected graphs with 10 nodes and 6 edges. Let M and m, respectively, be the maximum and minimum number of connected components in any graph in the collection. If a graph has no selfloops and there is at most one edge between any pair of nodes, which of the following is true?
 A. M = 10, m = 10
 B. M = 10, m = 1
 C. M = 7, m = 4
 D. M = 6, m = 4
Answer:


Question: Consider the collection of all undirected graphs with 10 nodes and 6 edges. Let M and m, respectively, be the maximum and minimum number of connected components in any graph in the collection. If a graph has no selfloops and there is at most one edge between any pair of nodes, which of the following is true?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Consider the collection of all undirected graphs with 10 nodes and 6 edges. Let M and m, respectively, be the maximum and minimum number of connected components in any graph in the collection. If a graph has no selfloops and there is at most one edge between any pair of nodes, which of the following is true?
 A. M = 10, m = 10
 B. M = 10, m = 1
 C. M = 7, m = 4
 D. M = 6, m = 4
Answer:


Question:
Resolution theorem proving for showing that a formula of propositional logic is not satisfiable has which of the following properties?
I. It is a sound proof system in the sense that there does not exist a proof of the unsatisfiability of a satisfiable formula of propositional logic.
II. It is a complete proof system in the sense that there is a proof of unsatisfiability for every unsa tisfiable formula of propositional logic.
III. It is a succinct proof system in the sense that whenever an unsatisfiable formula F of propositional logic has a resolution proof, F also has a proof whose length is polynomial in the length of F.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Resolution theorem proving for showing that a formula of propositional logic is not satisfiable has which of the following properties?
I. It is a sound proof system in the sense that there does not exist a proof of the unsatisfiability of a satisfiable formula of propositional logic.
II. It is a complete proof system in the sense that there is a proof of unsatisfiability for every unsa tisfiable formula of propositional logic.
III. It is a succinct proof system in the sense that whenever an unsatisfiable formula F of propositional logic has a resolution proof, F also has a proof whose length is polynomial in the length of F.
 A. I only
 B. III only
 C. I and II only
 D. I and III only
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Resolution theorem proving for showing that a formula of propositional logic is not satisfiable has which of the following properties?
I. It is a sound proof system in the sense that there does not exist a proof of the unsatisfiability of a satisfiable formula of propositional logic.
II. It is a complete proof system in the sense that there is a proof of unsatisfiability for every unsa tisfiable formula of propositional logic.
III. It is a succinct proof system in the sense that whenever an unsatisfiable formula F of propositional logic has a resolution proof, F also has a proof whose length is polynomial in the length of F.
 A. I only
 B. III only
 C. I and II only
 D. I and III only
Answer:


Question:
Resolution theorem proving for showing that a formula of propositional logic is not satisfiable has which of the following properties?
I. It is a sound proof system in the sense that there does not exist a proof of the unsatisfiability of a satisfiable formula of propositional logic.
II. It is a complete proof system in the sense that there is a proof of unsatisfiability for every unsa tisfiable formula of propositional logic.
III. It is a succinct proof system in the sense that whenever an unsatisfiable formula F of propositional logic has a resolution proof, F also has a proof whose length is polynomial in the length of F.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Resolution theorem proving for showing that a formula of propositional logic is not satisfiable has which of the following properties?
I. It is a sound proof system in the sense that there does not exist a proof of the unsatisfiability of a satisfiable formula of propositional logic.
II. It is a complete proof system in the sense that there is a proof of unsatisfiability for every unsa tisfiable formula of propositional logic.
III. It is a succinct proof system in the sense that whenever an unsatisfiable formula F of propositional logic has a resolution proof, F also has a proof whose length is polynomial in the length of F.
 A. I only
 B. III only
 C. I and II only
 D. I and III only
Answer:


Question:
Resolution theorem proving for showing that a formula of propositional logic is not satisfiable has which of the following properties?
I. It is a sound proof system in the sense that there does not exist a proof of the unsatisfiability of a satisfiable formula of propositional logic.
II. It is a complete proof system in the sense that there is a proof of unsatisfiability for every unsa tisfiable formula of propositional logic.
III. It is a succinct proof system in the sense that whenever an unsatisfiable formula F of propositional logic has a resolution proof, F also has a proof whose length is polynomial in the length of F.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Resolution theorem proving for showing that a formula of propositional logic is not satisfiable has which of the following properties?
I. It is a sound proof system in the sense that there does not exist a proof of the unsatisfiability of a satisfiable formula of propositional logic.
II. It is a complete proof system in the sense that there is a proof of unsatisfiability for every unsa tisfiable formula of propositional logic.
III. It is a succinct proof system in the sense that whenever an unsatisfiable formula F of propositional logic has a resolution proof, F also has a proof whose length is polynomial in the length of F.
 A. I only
 B. III only
 C. I and II only
 D. I and III only
Answer:


Question:
Resolution theorem proving for showing that a formula of propositional logic is not satisfiable has which of the following properties?
I. It is a sound proof system in the sense that there does not exist a proof of the unsatisfiability of a satisfiable formula of propositional logic.
II. It is a complete proof system in the sense that there is a proof of unsatisfiability for every unsa tisfiable formula of propositional logic.
III. It is a succinct proof system in the sense that whenever an unsatisfiable formula F of propositional logic has a resolution proof, F also has a proof whose length is polynomial in the length of F.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Resolution theorem proving for showing that a formula of propositional logic is not satisfiable has which of the following properties?
I. It is a sound proof system in the sense that there does not exist a proof of the unsatisfiability of a satisfiable formula of propositional logic.
II. It is a complete proof system in the sense that there is a proof of unsatisfiability for every unsa tisfiable formula of propositional logic.
III. It is a succinct proof system in the sense that whenever an unsatisfiable formula F of propositional logic has a resolution proof, F also has a proof whose length is polynomial in the length of F.
 A. I only
 B. III only
 C. I and II only
 D. I and III only
Answer:


Question:
Which of the following statements describe(s) properties of a purely segmented memory system?
I. It divides memory into units of equal size.
II. It permits implementation of virtual memory.
III. It suffers from internal fragmentation.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following statements describe(s) properties of a purely segmented memory system?
I. It divides memory into units of equal size.
II. It permits implementation of virtual memory.
III. It suffers from internal fragmentation.
 A. I only
 B. II only
 C. III only
 D. I and III
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Which of the following statements describe(s) properties of a purely segmented memory system?
I. It divides memory into units of equal size.
II. It permits implementation of virtual memory.
III. It suffers from internal fragmentation.
 A. I only
 B. II only
 C. III only
 D. I and III
Answer:


Question:
Which of the following statements describe(s) properties of a purely segmented memory system?
I. It divides memory into units of equal size.
II. It permits implementation of virtual memory.
III. It suffers from internal fragmentation.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following statements describe(s) properties of a purely segmented memory system?
I. It divides memory into units of equal size.
II. It permits implementation of virtual memory.
III. It suffers from internal fragmentation.
 A. I only
 B. II only
 C. III only
 D. I and III
Answer:


Question:
Which of the following statements describe(s) properties of a purely segmented memory system?
I. It divides memory into units of equal size.
II. It permits implementation of virtual memory.
III. It suffers from internal fragmentation.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following statements describe(s) properties of a purely segmented memory system?
I. It divides memory into units of equal size.
II. It permits implementation of virtual memory.
III. It suffers from internal fragmentation.
 A. I only
 B. II only
 C. III only
 D. I and III
Answer:


Question:
Which of the following statements describe(s) properties of a purely segmented memory system?
I. It divides memory into units of equal size.
II. It permits implementation of virtual memory.
III. It suffers from internal fragmentation.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following statements describe(s) properties of a purely segmented memory system?
I. It divides memory into units of equal size.
II. It permits implementation of virtual memory.
III. It suffers from internal fragmentation.
 A. I only
 B. II only
 C. III only
 D. I and III
Answer:


Question: Which of the following statements about floating-point arithmetic is NOT true?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following statements about floating-point arithmetic is NOT true?
 A. It is inherently nonassociative because some numbers have no exact representation.
 B. It is inherently nonassociative because there have to be upper and lower bounds on the size of numbers.
 C. Associativity can be achieved with appropriate roundoff conventions.
 D. Some rational numbers have no exact representation.
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Which of the following statements about floating-point arithmetic is NOT true?
 A. It is inherently nonassociative because some numbers have no exact representation.
 B. It is inherently nonassociative because there have to be upper and lower bounds on the size of numbers.
 C. Associativity can be achieved with appropriate roundoff conventions.
 D. Some rational numbers have no exact representation.
Answer:


Question: Which of the following statements about floating-point arithmetic is NOT true?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following statements about floating-point arithmetic is NOT true?
 A. It is inherently nonassociative because some numbers have no exact representation.
 B. It is inherently nonassociative because there have to be upper and lower bounds on the size of numbers.
 C. Associativity can be achieved with appropriate roundoff conventions.
 D. Some rational numbers have no exact representation.
Answer:


Question: Which of the following statements about floating-point arithmetic is NOT true?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following statements about floating-point arithmetic is NOT true?
 A. It is inherently nonassociative because some numbers have no exact representation.
 B. It is inherently nonassociative because there have to be upper and lower bounds on the size of numbers.
 C. Associativity can be achieved with appropriate roundoff conventions.
 D. Some rational numbers have no exact representation.
Answer:


Question: Which of the following statements about floating-point arithmetic is NOT true?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following statements about floating-point arithmetic is NOT true?
 A. It is inherently nonassociative because some numbers have no exact representation.
 B. It is inherently nonassociative because there have to be upper and lower bounds on the size of numbers.
 C. Associativity can be achieved with appropriate roundoff conventions.
 D. Some rational numbers have no exact representation.
Answer:


Question: Suppose sharing of tiles in a multilevel directory structure is achieved with directory entries that are links pointing to a node containing information about a shared file. Information in this node includes (1) the owner of the file, (2) a count of the number of links to the tile, and (3) the disk block numbers of the file. What is a primary drawback to this approach to sharing?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Suppose sharing of tiles in a multilevel directory structure is achieved with directory entries that are links pointing to a node containing information about a shared file. Information in this node includes (1) the owner of the file, (2) a count of the number of links to the tile, and (3) the disk block numbers of the file. What is a primary drawback to this approach to sharing?
 A. If the owner modifies the file, another user who does not share will see the changes.
 B. If the owner renames the file, other users will not be able to access it.
 C. If the owner is allowed to delete a file, dangling links may result.
 D. If any user who shares the file appends to it, others who share it will not be able to access the new disk blocks.
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Suppose sharing of tiles in a multilevel directory structure is achieved with directory entries that are links pointing to a node containing information about a shared file. Information in this node includes (1) the owner of the file, (2) a count of the number of links to the tile, and (3) the disk block numbers of the file. What is a primary drawback to this approach to sharing?
 A. If the owner modifies the file, another user who does not share will see the changes.
 B. If the owner renames the file, other users will not be able to access it.
 C. If the owner is allowed to delete a file, dangling links may result.
 D. If any user who shares the file appends to it, others who share it will not be able to access the new disk blocks.
Answer:


Question: Suppose sharing of tiles in a multilevel directory structure is achieved with directory entries that are links pointing to a node containing information about a shared file. Information in this node includes (1) the owner of the file, (2) a count of the number of links to the tile, and (3) the disk block numbers of the file. What is a primary drawback to this approach to sharing?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Suppose sharing of tiles in a multilevel directory structure is achieved with directory entries that are links pointing to a node containing information about a shared file. Information in this node includes (1) the owner of the file, (2) a count of the number of links to the tile, and (3) the disk block numbers of the file. What is a primary drawback to this approach to sharing?
 A. If the owner modifies the file, another user who does not share will see the changes.
 B. If the owner renames the file, other users will not be able to access it.
 C. If the owner is allowed to delete a file, dangling links may result.
 D. If any user who shares the file appends to it, others who share it will not be able to access the new disk blocks.
Answer:


Question: Suppose sharing of tiles in a multilevel directory structure is achieved with directory entries that are links pointing to a node containing information about a shared file. Information in this node includes (1) the owner of the file, (2) a count of the number of links to the tile, and (3) the disk block numbers of the file. What is a primary drawback to this approach to sharing?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Suppose sharing of tiles in a multilevel directory structure is achieved with directory entries that are links pointing to a node containing information about a shared file. Information in this node includes (1) the owner of the file, (2) a count of the number of links to the tile, and (3) the disk block numbers of the file. What is a primary drawback to this approach to sharing?
 A. If the owner modifies the file, another user who does not share will see the changes.
 B. If the owner renames the file, other users will not be able to access it.
 C. If the owner is allowed to delete a file, dangling links may result.
 D. If any user who shares the file appends to it, others who share it will not be able to access the new disk blocks.
Answer:


Question: Suppose sharing of tiles in a multilevel directory structure is achieved with directory entries that are links pointing to a node containing information about a shared file. Information in this node includes (1) the owner of the file, (2) a count of the number of links to the tile, and (3) the disk block numbers of the file. What is a primary drawback to this approach to sharing?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Suppose sharing of tiles in a multilevel directory structure is achieved with directory entries that are links pointing to a node containing information about a shared file. Information in this node includes (1) the owner of the file, (2) a count of the number of links to the tile, and (3) the disk block numbers of the file. What is a primary drawback to this approach to sharing?
 A. If the owner modifies the file, another user who does not share will see the changes.
 B. If the owner renames the file, other users will not be able to access it.
 C. If the owner is allowed to delete a file, dangling links may result.
 D. If any user who shares the file appends to it, others who share it will not be able to access the new disk blocks.
Answer:


Question:
Mergesort works by splitting a list of n numbers in half, sorting each half recursively, and merging the two halves. Which of the following data structures will allow mergesort to work in O(n log n) time?
I. A singly linked list
II. A doubly linked list
III. An array

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Mergesort works by splitting a list of n numbers in half, sorting each half recursively, and merging the two halves. Which of the following data structures will allow mergesort to work in O(n log n) time?
I. A singly linked list
II. A doubly linked list
III. An array
 A. None
 B. III only
 C. I and II only
 D. I, II, and III
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Mergesort works by splitting a list of n numbers in half, sorting each half recursively, and merging the two halves. Which of the following data structures will allow mergesort to work in O(n log n) time?
I. A singly linked list
II. A doubly linked list
III. An array
 A. None
 B. III only
 C. I and II only
 D. I, II, and III
Answer:


Question:
Mergesort works by splitting a list of n numbers in half, sorting each half recursively, and merging the two halves. Which of the following data structures will allow mergesort to work in O(n log n) time?
I. A singly linked list
II. A doubly linked list
III. An array

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Mergesort works by splitting a list of n numbers in half, sorting each half recursively, and merging the two halves. Which of the following data structures will allow mergesort to work in O(n log n) time?
I. A singly linked list
II. A doubly linked list
III. An array
 A. None
 B. III only
 C. I and II only
 D. I, II, and III
Answer:


Question:
Mergesort works by splitting a list of n numbers in half, sorting each half recursively, and merging the two halves. Which of the following data structures will allow mergesort to work in O(n log n) time?
I. A singly linked list
II. A doubly linked list
III. An array

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Mergesort works by splitting a list of n numbers in half, sorting each half recursively, and merging the two halves. Which of the following data structures will allow mergesort to work in O(n log n) time?
I. A singly linked list
II. A doubly linked list
III. An array
 A. None
 B. III only
 C. I and II only
 D. I, II, and III
Answer:


Question:
Mergesort works by splitting a list of n numbers in half, sorting each half recursively, and merging the two halves. Which of the following data structures will allow mergesort to work in O(n log n) time?
I. A singly linked list
II. A doubly linked list
III. An array

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Mergesort works by splitting a list of n numbers in half, sorting each half recursively, and merging the two halves. Which of the following data structures will allow mergesort to work in O(n log n) time?
I. A singly linked list
II. A doubly linked list
III. An array
 A. None
 B. III only
 C. I and II only
 D. I, II, and III
Answer:


Question: If p(x) is the minimal-degree interpolating polynomial for the real-valued function f(x) at the n + 1 distinct real numbers x0, .... xn what is the maximum possible degree of p(x)?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: If p(x) is the minimal-degree interpolating polynomial for the real-valued function f(x) at the n + 1 distinct real numbers x0, .... xn what is the maximum possible degree of p(x)?
 A. n
 B. n + 1
 C. n + 2
 D. 2n
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: If p(x) is the minimal-degree interpolating polynomial for the real-valued function f(x) at the n + 1 distinct real numbers x0, .... xn what is the maximum possible degree of p(x)?
 A. n
 B. n + 1
 C. n + 2
 D. 2n
Answer:


Question: If p(x) is the minimal-degree interpolating polynomial for the real-valued function f(x) at the n + 1 distinct real numbers x0, .... xn what is the maximum possible degree of p(x)?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: If p(x) is the minimal-degree interpolating polynomial for the real-valued function f(x) at the n + 1 distinct real numbers x0, .... xn what is the maximum possible degree of p(x)?
 A. n
 B. n + 1
 C. n + 2
 D. 2n
Answer:


Question: If p(x) is the minimal-degree interpolating polynomial for the real-valued function f(x) at the n + 1 distinct real numbers x0, .... xn what is the maximum possible degree of p(x)?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: If p(x) is the minimal-degree interpolating polynomial for the real-valued function f(x) at the n + 1 distinct real numbers x0, .... xn what is the maximum possible degree of p(x)?
 A. n
 B. n + 1
 C. n + 2
 D. 2n
Answer:


Question: If p(x) is the minimal-degree interpolating polynomial for the real-valued function f(x) at the n + 1 distinct real numbers x0, .... xn what is the maximum possible degree of p(x)?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: If p(x) is the minimal-degree interpolating polynomial for the real-valued function f(x) at the n + 1 distinct real numbers x0, .... xn what is the maximum possible degree of p(x)?
 A. n
 B. n + 1
 C. n + 2
 D. 2n
Answer:


Question: An internal hash table has 5 buckets, numbered 0, 1, 2, 3, 4. Keys are integers, and the hash function h(i) = i mod 5 is used, with linear resolution of collisions (i.e., if bucket h(i) is filled, the buckets h(i) + 1, h(i) + 2, ... are tried successively with all bucket numbers computed modulo 5). If elements with keys 13, 8, 24, 10, and 3 are inserted, m that order, into an initially blank hash table, then the content of the bucket numbered 2 is

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: An internal hash table has 5 buckets, numbered 0, 1, 2, 3, 4. Keys are integers, and the hash function h(i) = i mod 5 is used, with linear resolution of collisions (i.e., if bucket h(i) is filled, the buckets h(i) + 1, h(i) + 2, ... are tried successively with all bucket numbers computed modulo 5). If elements with keys 13, 8, 24, 10, and 3 are inserted, m that order, into an initially blank hash table, then the content of the bucket numbered 2 is
 A. 3
 B. 8
 C. 10
 D. 13
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: An internal hash table has 5 buckets, numbered 0, 1, 2, 3, 4. Keys are integers, and the hash function h(i) = i mod 5 is used, with linear resolution of collisions (i.e., if bucket h(i) is filled, the buckets h(i) + 1, h(i) + 2, ... are tried successively with all bucket numbers computed modulo 5). If elements with keys 13, 8, 24, 10, and 3 are inserted, m that order, into an initially blank hash table, then the content of the bucket numbered 2 is
 A. 3
 B. 8
 C. 10
 D. 13
Answer:


Question: An internal hash table has 5 buckets, numbered 0, 1, 2, 3, 4. Keys are integers, and the hash function h(i) = i mod 5 is used, with linear resolution of collisions (i.e., if bucket h(i) is filled, the buckets h(i) + 1, h(i) + 2, ... are tried successively with all bucket numbers computed modulo 5). If elements with keys 13, 8, 24, 10, and 3 are inserted, m that order, into an initially blank hash table, then the content of the bucket numbered 2 is

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: An internal hash table has 5 buckets, numbered 0, 1, 2, 3, 4. Keys are integers, and the hash function h(i) = i mod 5 is used, with linear resolution of collisions (i.e., if bucket h(i) is filled, the buckets h(i) + 1, h(i) + 2, ... are tried successively with all bucket numbers computed modulo 5). If elements with keys 13, 8, 24, 10, and 3 are inserted, m that order, into an initially blank hash table, then the content of the bucket numbered 2 is
 A. 3
 B. 8
 C. 10
 D. 13
Answer:


Question: An internal hash table has 5 buckets, numbered 0, 1, 2, 3, 4. Keys are integers, and the hash function h(i) = i mod 5 is used, with linear resolution of collisions (i.e., if bucket h(i) is filled, the buckets h(i) + 1, h(i) + 2, ... are tried successively with all bucket numbers computed modulo 5). If elements with keys 13, 8, 24, 10, and 3 are inserted, m that order, into an initially blank hash table, then the content of the bucket numbered 2 is

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: An internal hash table has 5 buckets, numbered 0, 1, 2, 3, 4. Keys are integers, and the hash function h(i) = i mod 5 is used, with linear resolution of collisions (i.e., if bucket h(i) is filled, the buckets h(i) + 1, h(i) + 2, ... are tried successively with all bucket numbers computed modulo 5). If elements with keys 13, 8, 24, 10, and 3 are inserted, m that order, into an initially blank hash table, then the content of the bucket numbered 2 is
 A. 3
 B. 8
 C. 10
 D. 13
Answer:


Question: An internal hash table has 5 buckets, numbered 0, 1, 2, 3, 4. Keys are integers, and the hash function h(i) = i mod 5 is used, with linear resolution of collisions (i.e., if bucket h(i) is filled, the buckets h(i) + 1, h(i) + 2, ... are tried successively with all bucket numbers computed modulo 5). If elements with keys 13, 8, 24, 10, and 3 are inserted, m that order, into an initially blank hash table, then the content of the bucket numbered 2 is

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: An internal hash table has 5 buckets, numbered 0, 1, 2, 3, 4. Keys are integers, and the hash function h(i) = i mod 5 is used, with linear resolution of collisions (i.e., if bucket h(i) is filled, the buckets h(i) + 1, h(i) + 2, ... are tried successively with all bucket numbers computed modulo 5). If elements with keys 13, 8, 24, 10, and 3 are inserted, m that order, into an initially blank hash table, then the content of the bucket numbered 2 is
 A. 3
 B. 8
 C. 10
 D. 13
Answer:


Question: TCP protocol is responsible (among other things) for

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: TCP protocol is responsible (among other things) for
 A. Routing packets through the network
 B. Reliable delivery of packets between directly connected machines
 C. Reliable delivery of large (multi-packet) messages between machines that are not necessarily directly connected
 D. Dealing with differences among operating system architectures
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: TCP protocol is responsible (among other things) for
 A. Routing packets through the network
 B. Reliable delivery of packets between directly connected machines
 C. Reliable delivery of large (multi-packet) messages between machines that are not necessarily directly connected
 D. Dealing with differences among operating system architectures
Answer:


Question: TCP protocol is responsible (among other things) for

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: TCP protocol is responsible (among other things) for
 A. Routing packets through the network
 B. Reliable delivery of packets between directly connected machines
 C. Reliable delivery of large (multi-packet) messages between machines that are not necessarily directly connected
 D. Dealing with differences among operating system architectures
Answer:


Question: TCP protocol is responsible (among other things) for

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: TCP protocol is responsible (among other things) for
 A. Routing packets through the network
 B. Reliable delivery of packets between directly connected machines
 C. Reliable delivery of large (multi-packet) messages between machines that are not necessarily directly connected
 D. Dealing with differences among operating system architectures
Answer:


Question: TCP protocol is responsible (among other things) for

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: TCP protocol is responsible (among other things) for
 A. Routing packets through the network
 B. Reliable delivery of packets between directly connected machines
 C. Reliable delivery of large (multi-packet) messages between machines that are not necessarily directly connected
 D. Dealing with differences among operating system architectures
Answer:


Question:
Let A and B be two sets of words (strings) from Σ*, for some alphabet of symbols Σ. Suppose that B is a subset of A. Which of the following statements must always be true of A and B ?
I. If A is finite, then B is finite.
II. If A is regular, then B is regular.
III. If A is context-free, then B is context-free.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let A and B be two sets of words (strings) from Σ*, for some alphabet of symbols Σ. Suppose that B is a subset of A. Which of the following statements must always be true of A and B ?
I. If A is finite, then B is finite.
II. If A is regular, then B is regular.
III. If A is context-free, then B is context-free.
 A. I only
 B. II only
 C. III only
 D. I and II only
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Let A and B be two sets of words (strings) from Σ*, for some alphabet of symbols Σ. Suppose that B is a subset of A. Which of the following statements must always be true of A and B ?
I. If A is finite, then B is finite.
II. If A is regular, then B is regular.
III. If A is context-free, then B is context-free.
 A. I only
 B. II only
 C. III only
 D. I and II only
Answer:


Question:
Let A and B be two sets of words (strings) from Σ*, for some alphabet of symbols Σ. Suppose that B is a subset of A. Which of the following statements must always be true of A and B ?
I. If A is finite, then B is finite.
II. If A is regular, then B is regular.
III. If A is context-free, then B is context-free.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let A and B be two sets of words (strings) from Σ*, for some alphabet of symbols Σ. Suppose that B is a subset of A. Which of the following statements must always be true of A and B ?
I. If A is finite, then B is finite.
II. If A is regular, then B is regular.
III. If A is context-free, then B is context-free.
 A. I only
 B. II only
 C. III only
 D. I and II only
Answer:


Question:
Let A and B be two sets of words (strings) from Σ*, for some alphabet of symbols Σ. Suppose that B is a subset of A. Which of the following statements must always be true of A and B ?
I. If A is finite, then B is finite.
II. If A is regular, then B is regular.
III. If A is context-free, then B is context-free.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let A and B be two sets of words (strings) from Σ*, for some alphabet of symbols Σ. Suppose that B is a subset of A. Which of the following statements must always be true of A and B ?
I. If A is finite, then B is finite.
II. If A is regular, then B is regular.
III. If A is context-free, then B is context-free.
 A. I only
 B. II only
 C. III only
 D. I and II only
Answer:


Question:
Let A and B be two sets of words (strings) from Σ*, for some alphabet of symbols Σ. Suppose that B is a subset of A. Which of the following statements must always be true of A and B ?
I. If A is finite, then B is finite.
II. If A is regular, then B is regular.
III. If A is context-free, then B is context-free.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let A and B be two sets of words (strings) from Σ*, for some alphabet of symbols Σ. Suppose that B is a subset of A. Which of the following statements must always be true of A and B ?
I. If A is finite, then B is finite.
II. If A is regular, then B is regular.
III. If A is context-free, then B is context-free.
 A. I only
 B. II only
 C. III only
 D. I and II only
Answer: