Question:
For all strings x, the function x^M is defined recursively as follows.
e^M= e, and
if w is a string and a is a string with length 1, then
(aw)^M = aw^Ma.
Let a be a string with length 1, and let x and y be arbitrary strings. Which of the following is true?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: For all strings x, the function x^M is defined recursively as follows.
e^M= e, and
if w is a string and a is a string with length 1, then
(aw)^M = aw^Ma.
Let a be a string with length 1, and let x and y be arbitrary strings. Which of the following is true?
 A. a^M = a
 B. (ax)^M = (xa)^M
 C. (xy)^M = y^Mx^M
 D. None of the above
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: For all strings x, the function x^M is defined recursively as follows.
e^M= e, and
if w is a string and a is a string with length 1, then
(aw)^M = aw^Ma.
Let a be a string with length 1, and let x and y be arbitrary strings. Which of the following is true?
 A. a^M = a
 B. (ax)^M = (xa)^M
 C. (xy)^M = y^Mx^M
 D. None of the above
Answer:


Question:
For all strings x, the function x^M is defined recursively as follows.
e^M= e, and
if w is a string and a is a string with length 1, then
(aw)^M = aw^Ma.
Let a be a string with length 1, and let x and y be arbitrary strings. Which of the following is true?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: For all strings x, the function x^M is defined recursively as follows.
e^M= e, and
if w is a string and a is a string with length 1, then
(aw)^M = aw^Ma.
Let a be a string with length 1, and let x and y be arbitrary strings. Which of the following is true?
 A. a^M = a
 B. (ax)^M = (xa)^M
 C. (xy)^M = y^Mx^M
 D. None of the above
Answer:


Question:
For all strings x, the function x^M is defined recursively as follows.
e^M= e, and
if w is a string and a is a string with length 1, then
(aw)^M = aw^Ma.
Let a be a string with length 1, and let x and y be arbitrary strings. Which of the following is true?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: For all strings x, the function x^M is defined recursively as follows.
e^M= e, and
if w is a string and a is a string with length 1, then
(aw)^M = aw^Ma.
Let a be a string with length 1, and let x and y be arbitrary strings. Which of the following is true?
 A. a^M = a
 B. (ax)^M = (xa)^M
 C. (xy)^M = y^Mx^M
 D. None of the above
Answer:


Question:
For all strings x, the function x^M is defined recursively as follows.
e^M= e, and
if w is a string and a is a string with length 1, then
(aw)^M = aw^Ma.
Let a be a string with length 1, and let x and y be arbitrary strings. Which of the following is true?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: For all strings x, the function x^M is defined recursively as follows.
e^M= e, and
if w is a string and a is a string with length 1, then
(aw)^M = aw^Ma.
Let a be a string with length 1, and let x and y be arbitrary strings. Which of the following is true?
 A. a^M = a
 B. (ax)^M = (xa)^M
 C. (xy)^M = y^Mx^M
 D. None of the above
Answer:


Question: Which of the following is NOT a reasonable justification for choosing to busy-wait on an asynchronous event?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following is NOT a reasonable justification for choosing to busy-wait on an asynchronous event?
 A. The wait is expected to be short.
 B. A busy-wait loop is easier to code than an interrupt handler.
 C. There is no other work for the processor to do.
 D. The program executes on a time-sharing system.
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Which of the following is NOT a reasonable justification for choosing to busy-wait on an asynchronous event?
 A. The wait is expected to be short.
 B. A busy-wait loop is easier to code than an interrupt handler.
 C. There is no other work for the processor to do.
 D. The program executes on a time-sharing system.
Answer:


Question: Which of the following is NOT a reasonable justification for choosing to busy-wait on an asynchronous event?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following is NOT a reasonable justification for choosing to busy-wait on an asynchronous event?
 A. The wait is expected to be short.
 B. A busy-wait loop is easier to code than an interrupt handler.
 C. There is no other work for the processor to do.
 D. The program executes on a time-sharing system.
Answer:


Question: Which of the following is NOT a reasonable justification for choosing to busy-wait on an asynchronous event?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following is NOT a reasonable justification for choosing to busy-wait on an asynchronous event?
 A. The wait is expected to be short.
 B. A busy-wait loop is easier to code than an interrupt handler.
 C. There is no other work for the processor to do.
 D. The program executes on a time-sharing system.
Answer:


Question: Which of the following is NOT a reasonable justification for choosing to busy-wait on an asynchronous event?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following is NOT a reasonable justification for choosing to busy-wait on an asynchronous event?
 A. The wait is expected to be short.
 B. A busy-wait loop is easier to code than an interrupt handler.
 C. There is no other work for the processor to do.
 D. The program executes on a time-sharing system.
Answer:


Question: The language {ww | w in (0 + 1)*} is

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: The language {ww | w in (0 + 1)*} is
 A. not accepted by any Turing machine
 B. accepted by some Turing machine, but by no pushdown automaton
 C. accepted by some pushdown automaton, but not context-free
 D. context-free, but not regular
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: The language {ww | w in (0 + 1)*} is
 A. not accepted by any Turing machine
 B. accepted by some Turing machine, but by no pushdown automaton
 C. accepted by some pushdown automaton, but not context-free
 D. context-free, but not regular
Answer:


Question: The language {ww | w in (0 + 1)*} is

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: The language {ww | w in (0 + 1)*} is
 A. not accepted by any Turing machine
 B. accepted by some Turing machine, but by no pushdown automaton
 C. accepted by some pushdown automaton, but not context-free
 D. context-free, but not regular
Answer:


Question: The language {ww | w in (0 + 1)*} is

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: The language {ww | w in (0 + 1)*} is
 A. not accepted by any Turing machine
 B. accepted by some Turing machine, but by no pushdown automaton
 C. accepted by some pushdown automaton, but not context-free
 D. context-free, but not regular
Answer:


Question: The language {ww | w in (0 + 1)*} is

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: The language {ww | w in (0 + 1)*} is
 A. not accepted by any Turing machine
 B. accepted by some Turing machine, but by no pushdown automaton
 C. accepted by some pushdown automaton, but not context-free
 D. context-free, but not regular
Answer:


Question: Which of the following statements about Ethernets is typically FALSE?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following statements about Ethernets is typically FALSE?
 A. Ethernets use circuit switching to send messages.
 B. Ethernets use buses with multiple masters.
 C. Ethernet protocols use a collision-detection method to ensure that messages are transmitted properly.
 D. Networks connected by Ethernets are limited in length to a few hundred meters.
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Which of the following statements about Ethernets is typically FALSE?
 A. Ethernets use circuit switching to send messages.
 B. Ethernets use buses with multiple masters.
 C. Ethernet protocols use a collision-detection method to ensure that messages are transmitted properly.
 D. Networks connected by Ethernets are limited in length to a few hundred meters.
Answer:


Question: Which of the following statements about Ethernets is typically FALSE?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following statements about Ethernets is typically FALSE?
 A. Ethernets use circuit switching to send messages.
 B. Ethernets use buses with multiple masters.
 C. Ethernet protocols use a collision-detection method to ensure that messages are transmitted properly.
 D. Networks connected by Ethernets are limited in length to a few hundred meters.
Answer:


Question: Which of the following statements about Ethernets is typically FALSE?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following statements about Ethernets is typically FALSE?
 A. Ethernets use circuit switching to send messages.
 B. Ethernets use buses with multiple masters.
 C. Ethernet protocols use a collision-detection method to ensure that messages are transmitted properly.
 D. Networks connected by Ethernets are limited in length to a few hundred meters.
Answer:


Question: Which of the following statements about Ethernets is typically FALSE?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following statements about Ethernets is typically FALSE?
 A. Ethernets use circuit switching to send messages.
 B. Ethernets use buses with multiple masters.
 C. Ethernet protocols use a collision-detection method to ensure that messages are transmitted properly.
 D. Networks connected by Ethernets are limited in length to a few hundred meters.
Answer:


Question:
Let P be a procedure that for some inputs calls itself (i.e., is recursive). If P is guaranteed to terminate, which of the following statements must be true?
I. P has a local variable.
II. P has an execution path where it does not call itself.
III. P either refers to a global variable or has at least one parameter.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let P be a procedure that for some inputs calls itself (i.e., is recursive). If P is guaranteed to terminate, which of the following statements must be true?
I. P has a local variable.
II. P has an execution path where it does not call itself.
III. P either refers to a global variable or has at least one parameter.
 A. I only
 B. II only
 C. I and II only
 D. II and III only
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Let P be a procedure that for some inputs calls itself (i.e., is recursive). If P is guaranteed to terminate, which of the following statements must be true?
I. P has a local variable.
II. P has an execution path where it does not call itself.
III. P either refers to a global variable or has at least one parameter.
 A. I only
 B. II only
 C. I and II only
 D. II and III only
Answer:


Question:
Let P be a procedure that for some inputs calls itself (i.e., is recursive). If P is guaranteed to terminate, which of the following statements must be true?
I. P has a local variable.
II. P has an execution path where it does not call itself.
III. P either refers to a global variable or has at least one parameter.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let P be a procedure that for some inputs calls itself (i.e., is recursive). If P is guaranteed to terminate, which of the following statements must be true?
I. P has a local variable.
II. P has an execution path where it does not call itself.
III. P either refers to a global variable or has at least one parameter.
 A. I only
 B. II only
 C. I and II only
 D. II and III only
Answer:


Question:
Let P be a procedure that for some inputs calls itself (i.e., is recursive). If P is guaranteed to terminate, which of the following statements must be true?
I. P has a local variable.
II. P has an execution path where it does not call itself.
III. P either refers to a global variable or has at least one parameter.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let P be a procedure that for some inputs calls itself (i.e., is recursive). If P is guaranteed to terminate, which of the following statements must be true?
I. P has a local variable.
II. P has an execution path where it does not call itself.
III. P either refers to a global variable or has at least one parameter.
 A. I only
 B. II only
 C. I and II only
 D. II and III only
Answer:


Question:
Let P be a procedure that for some inputs calls itself (i.e., is recursive). If P is guaranteed to terminate, which of the following statements must be true?
I. P has a local variable.
II. P has an execution path where it does not call itself.
III. P either refers to a global variable or has at least one parameter.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let P be a procedure that for some inputs calls itself (i.e., is recursive). If P is guaranteed to terminate, which of the following statements must be true?
I. P has a local variable.
II. P has an execution path where it does not call itself.
III. P either refers to a global variable or has at least one parameter.
 A. I only
 B. II only
 C. I and II only
 D. II and III only
Answer:


Question: Which of the following comes closest to being a perfectly secure encryption scheme?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following comes closest to being a perfectly secure encryption scheme?
 A. The Caesar Cipher, a substitution cipher
 B. DES (Data Encryption Standard), a symmetric-key algorithm
 C. Enigma, a transposition cipher
 D. One-time pad
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Which of the following comes closest to being a perfectly secure encryption scheme?
 A. The Caesar Cipher, a substitution cipher
 B. DES (Data Encryption Standard), a symmetric-key algorithm
 C. Enigma, a transposition cipher
 D. One-time pad
Answer:


Question: Which of the following comes closest to being a perfectly secure encryption scheme?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following comes closest to being a perfectly secure encryption scheme?
 A. The Caesar Cipher, a substitution cipher
 B. DES (Data Encryption Standard), a symmetric-key algorithm
 C. Enigma, a transposition cipher
 D. One-time pad
Answer:


Question: Which of the following comes closest to being a perfectly secure encryption scheme?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following comes closest to being a perfectly secure encryption scheme?
 A. The Caesar Cipher, a substitution cipher
 B. DES (Data Encryption Standard), a symmetric-key algorithm
 C. Enigma, a transposition cipher
 D. One-time pad
Answer:


Question: Which of the following comes closest to being a perfectly secure encryption scheme?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following comes closest to being a perfectly secure encryption scheme?
 A. The Caesar Cipher, a substitution cipher
 B. DES (Data Encryption Standard), a symmetric-key algorithm
 C. Enigma, a transposition cipher
 D. One-time pad
Answer:


Question: Of the following problems concerning a given undirected graph G, which is currently known to be solvable in polynomial time?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Of the following problems concerning a given undirected graph G, which is currently known to be solvable in polynomial time?
 A. Finding a longest simple cycle in G
 B. Finding a shortest cycle in G
 C. Finding ALL spanning trees of G
 D. Finding a largest clique in G
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Of the following problems concerning a given undirected graph G, which is currently known to be solvable in polynomial time?
 A. Finding a longest simple cycle in G
 B. Finding a shortest cycle in G
 C. Finding ALL spanning trees of G
 D. Finding a largest clique in G
Answer:


Question: Of the following problems concerning a given undirected graph G, which is currently known to be solvable in polynomial time?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Of the following problems concerning a given undirected graph G, which is currently known to be solvable in polynomial time?
 A. Finding a longest simple cycle in G
 B. Finding a shortest cycle in G
 C. Finding ALL spanning trees of G
 D. Finding a largest clique in G
Answer:


Question: Of the following problems concerning a given undirected graph G, which is currently known to be solvable in polynomial time?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Of the following problems concerning a given undirected graph G, which is currently known to be solvable in polynomial time?
 A. Finding a longest simple cycle in G
 B. Finding a shortest cycle in G
 C. Finding ALL spanning trees of G
 D. Finding a largest clique in G
Answer:


Question: Of the following problems concerning a given undirected graph G, which is currently known to be solvable in polynomial time?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Of the following problems concerning a given undirected graph G, which is currently known to be solvable in polynomial time?
 A. Finding a longest simple cycle in G
 B. Finding a shortest cycle in G
 C. Finding ALL spanning trees of G
 D. Finding a largest clique in G
Answer:


Question: The IP protocol is primarily concerned with

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: The IP protocol is primarily concerned with
 A. Routing packets through the network
 B. Reliable delivery of packets between directly connected machines
 C. Reliable delivery of large (multi-packet) messages between machines that are not necessarily directly connected
 D. Dealing with differences among operating system architectures
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: The IP protocol is primarily concerned with
 A. Routing packets through the network
 B. Reliable delivery of packets between directly connected machines
 C. Reliable delivery of large (multi-packet) messages between machines that are not necessarily directly connected
 D. Dealing with differences among operating system architectures
Answer:


Question: The IP protocol is primarily concerned with

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: The IP protocol is primarily concerned with
 A. Routing packets through the network
 B. Reliable delivery of packets between directly connected machines
 C. Reliable delivery of large (multi-packet) messages between machines that are not necessarily directly connected
 D. Dealing with differences among operating system architectures
Answer:


Question: The IP protocol is primarily concerned with

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: The IP protocol is primarily concerned with
 A. Routing packets through the network
 B. Reliable delivery of packets between directly connected machines
 C. Reliable delivery of large (multi-packet) messages between machines that are not necessarily directly connected
 D. Dealing with differences among operating system architectures
Answer:


Question: The IP protocol is primarily concerned with

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: The IP protocol is primarily concerned with
 A. Routing packets through the network
 B. Reliable delivery of packets between directly connected machines
 C. Reliable delivery of large (multi-packet) messages between machines that are not necessarily directly connected
 D. Dealing with differences among operating system architectures
Answer:


Question: Of the following, which best approximates the ratio of the number of nonterminal nodes to the total number of nodes in a complete K-ary tree of depth N?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Of the following, which best approximates the ratio of the number of nonterminal nodes to the total number of nodes in a complete K-ary tree of depth N?
 A. 1/K
 B. K-1/K
 C. log_10 (1/N)
 D. N-1/m
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Of the following, which best approximates the ratio of the number of nonterminal nodes to the total number of nodes in a complete K-ary tree of depth N?
 A. 1/K
 B. K-1/K
 C. log_10 (1/N)
 D. N-1/m
Answer:


Question: Of the following, which best approximates the ratio of the number of nonterminal nodes to the total number of nodes in a complete K-ary tree of depth N?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Of the following, which best approximates the ratio of the number of nonterminal nodes to the total number of nodes in a complete K-ary tree of depth N?
 A. 1/K
 B. K-1/K
 C. log_10 (1/N)
 D. N-1/m
Answer:


Question: Of the following, which best approximates the ratio of the number of nonterminal nodes to the total number of nodes in a complete K-ary tree of depth N?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Of the following, which best approximates the ratio of the number of nonterminal nodes to the total number of nodes in a complete K-ary tree of depth N?
 A. 1/K
 B. K-1/K
 C. log_10 (1/N)
 D. N-1/m
Answer:


Question: Of the following, which best approximates the ratio of the number of nonterminal nodes to the total number of nodes in a complete K-ary tree of depth N?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Of the following, which best approximates the ratio of the number of nonterminal nodes to the total number of nodes in a complete K-ary tree of depth N?
 A. 1/K
 B. K-1/K
 C. log_10 (1/N)
 D. N-1/m
Answer:


Question: Consider a computer system in which processes can request and release one or more resources. Once a process has been granted a resource, the process has exclusive use of that resource until it is released. If a process requests a resource that is already in use, the process enters a queue for that resource, waiting until the resource is available. Which of the following will NOT deal effectively with the problem of deadlock?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Consider a computer system in which processes can request and release one or more resources. Once a process has been granted a resource, the process has exclusive use of that resource until it is released. If a process requests a resource that is already in use, the process enters a queue for that resource, waiting until the resource is available. Which of the following will NOT deal effectively with the problem of deadlock?
 A. Giving priorities to processes and ordering the wait queues by priority
 B. Having a process request all its required resources when it first begins, and restarting if it cannot obtain them all
 C. Numbering the resources and requiring that processes request resources in order of increasing number
 D. Having processes time out and restart after a random interval of waiting
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Consider a computer system in which processes can request and release one or more resources. Once a process has been granted a resource, the process has exclusive use of that resource until it is released. If a process requests a resource that is already in use, the process enters a queue for that resource, waiting until the resource is available. Which of the following will NOT deal effectively with the problem of deadlock?
 A. Giving priorities to processes and ordering the wait queues by priority
 B. Having a process request all its required resources when it first begins, and restarting if it cannot obtain them all
 C. Numbering the resources and requiring that processes request resources in order of increasing number
 D. Having processes time out and restart after a random interval of waiting
Answer:


Question: Consider a computer system in which processes can request and release one or more resources. Once a process has been granted a resource, the process has exclusive use of that resource until it is released. If a process requests a resource that is already in use, the process enters a queue for that resource, waiting until the resource is available. Which of the following will NOT deal effectively with the problem of deadlock?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Consider a computer system in which processes can request and release one or more resources. Once a process has been granted a resource, the process has exclusive use of that resource until it is released. If a process requests a resource that is already in use, the process enters a queue for that resource, waiting until the resource is available. Which of the following will NOT deal effectively with the problem of deadlock?
 A. Giving priorities to processes and ordering the wait queues by priority
 B. Having a process request all its required resources when it first begins, and restarting if it cannot obtain them all
 C. Numbering the resources and requiring that processes request resources in order of increasing number
 D. Having processes time out and restart after a random interval of waiting
Answer:


Question: Consider a computer system in which processes can request and release one or more resources. Once a process has been granted a resource, the process has exclusive use of that resource until it is released. If a process requests a resource that is already in use, the process enters a queue for that resource, waiting until the resource is available. Which of the following will NOT deal effectively with the problem of deadlock?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Consider a computer system in which processes can request and release one or more resources. Once a process has been granted a resource, the process has exclusive use of that resource until it is released. If a process requests a resource that is already in use, the process enters a queue for that resource, waiting until the resource is available. Which of the following will NOT deal effectively with the problem of deadlock?
 A. Giving priorities to processes and ordering the wait queues by priority
 B. Having a process request all its required resources when it first begins, and restarting if it cannot obtain them all
 C. Numbering the resources and requiring that processes request resources in order of increasing number
 D. Having processes time out and restart after a random interval of waiting
Answer:


Question: Consider a computer system in which processes can request and release one or more resources. Once a process has been granted a resource, the process has exclusive use of that resource until it is released. If a process requests a resource that is already in use, the process enters a queue for that resource, waiting until the resource is available. Which of the following will NOT deal effectively with the problem of deadlock?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Consider a computer system in which processes can request and release one or more resources. Once a process has been granted a resource, the process has exclusive use of that resource until it is released. If a process requests a resource that is already in use, the process enters a queue for that resource, waiting until the resource is available. Which of the following will NOT deal effectively with the problem of deadlock?
 A. Giving priorities to processes and ordering the wait queues by priority
 B. Having a process request all its required resources when it first begins, and restarting if it cannot obtain them all
 C. Numbering the resources and requiring that processes request resources in order of increasing number
 D. Having processes time out and restart after a random interval of waiting
Answer:


Question:
"Magic memory"' has two operations: Read and Clear. Both are indivisible and mutually exclusive. Clear sets the magic memory to zero. Read returns a value that represents the number of Read operations since the last Clear operation. Which of the following is (are) true of "Magic memory"?
I. It can provide the functionality of an atomic Test-and-Set.
II. It can be used to coordinate processes running on a shared-memory multiprocessor.
III. It is only useful on a multiprocessor.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: "Magic memory"' has two operations: Read and Clear. Both are indivisible and mutually exclusive. Clear sets the magic memory to zero. Read returns a value that represents the number of Read operations since the last Clear operation. Which of the following is (are) true of "Magic memory"?
I. It can provide the functionality of an atomic Test-and-Set.
II. It can be used to coordinate processes running on a shared-memory multiprocessor.
III. It is only useful on a multiprocessor.
 A. I only
 B. II only
 C. III only
 D. I and II
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: "Magic memory"' has two operations: Read and Clear. Both are indivisible and mutually exclusive. Clear sets the magic memory to zero. Read returns a value that represents the number of Read operations since the last Clear operation. Which of the following is (are) true of "Magic memory"?
I. It can provide the functionality of an atomic Test-and-Set.
II. It can be used to coordinate processes running on a shared-memory multiprocessor.
III. It is only useful on a multiprocessor.
 A. I only
 B. II only
 C. III only
 D. I and II
Answer:


Question:
"Magic memory"' has two operations: Read and Clear. Both are indivisible and mutually exclusive. Clear sets the magic memory to zero. Read returns a value that represents the number of Read operations since the last Clear operation. Which of the following is (are) true of "Magic memory"?
I. It can provide the functionality of an atomic Test-and-Set.
II. It can be used to coordinate processes running on a shared-memory multiprocessor.
III. It is only useful on a multiprocessor.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: "Magic memory"' has two operations: Read and Clear. Both are indivisible and mutually exclusive. Clear sets the magic memory to zero. Read returns a value that represents the number of Read operations since the last Clear operation. Which of the following is (are) true of "Magic memory"?
I. It can provide the functionality of an atomic Test-and-Set.
II. It can be used to coordinate processes running on a shared-memory multiprocessor.
III. It is only useful on a multiprocessor.
 A. I only
 B. II only
 C. III only
 D. I and II
Answer:


Question:
"Magic memory"' has two operations: Read and Clear. Both are indivisible and mutually exclusive. Clear sets the magic memory to zero. Read returns a value that represents the number of Read operations since the last Clear operation. Which of the following is (are) true of "Magic memory"?
I. It can provide the functionality of an atomic Test-and-Set.
II. It can be used to coordinate processes running on a shared-memory multiprocessor.
III. It is only useful on a multiprocessor.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: "Magic memory"' has two operations: Read and Clear. Both are indivisible and mutually exclusive. Clear sets the magic memory to zero. Read returns a value that represents the number of Read operations since the last Clear operation. Which of the following is (are) true of "Magic memory"?
I. It can provide the functionality of an atomic Test-and-Set.
II. It can be used to coordinate processes running on a shared-memory multiprocessor.
III. It is only useful on a multiprocessor.
 A. I only
 B. II only
 C. III only
 D. I and II
Answer:


Question:
"Magic memory"' has two operations: Read and Clear. Both are indivisible and mutually exclusive. Clear sets the magic memory to zero. Read returns a value that represents the number of Read operations since the last Clear operation. Which of the following is (are) true of "Magic memory"?
I. It can provide the functionality of an atomic Test-and-Set.
II. It can be used to coordinate processes running on a shared-memory multiprocessor.
III. It is only useful on a multiprocessor.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: "Magic memory"' has two operations: Read and Clear. Both are indivisible and mutually exclusive. Clear sets the magic memory to zero. Read returns a value that represents the number of Read operations since the last Clear operation. Which of the following is (are) true of "Magic memory"?
I. It can provide the functionality of an atomic Test-and-Set.
II. It can be used to coordinate processes running on a shared-memory multiprocessor.
III. It is only useful on a multiprocessor.
 A. I only
 B. II only
 C. III only
 D. I and II
Answer:


Question: Which of the following is the name of the data structure in a compiler that is responsible for managing information about variables and their attributes?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following is the name of the data structure in a compiler that is responsible for managing information about variables and their attributes?
 A. Abstract Syntax Tree (AST)
 B. Attribute Grammar
 C. Symbol Table
 D. Semantic Stack
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Which of the following is the name of the data structure in a compiler that is responsible for managing information about variables and their attributes?
 A. Abstract Syntax Tree (AST)
 B. Attribute Grammar
 C. Symbol Table
 D. Semantic Stack
Answer:


Question: Which of the following is the name of the data structure in a compiler that is responsible for managing information about variables and their attributes?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following is the name of the data structure in a compiler that is responsible for managing information about variables and their attributes?
 A. Abstract Syntax Tree (AST)
 B. Attribute Grammar
 C. Symbol Table
 D. Semantic Stack
Answer:


Question: Which of the following is the name of the data structure in a compiler that is responsible for managing information about variables and their attributes?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following is the name of the data structure in a compiler that is responsible for managing information about variables and their attributes?
 A. Abstract Syntax Tree (AST)
 B. Attribute Grammar
 C. Symbol Table
 D. Semantic Stack
Answer:


Question: Which of the following is the name of the data structure in a compiler that is responsible for managing information about variables and their attributes?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following is the name of the data structure in a compiler that is responsible for managing information about variables and their attributes?
 A. Abstract Syntax Tree (AST)
 B. Attribute Grammar
 C. Symbol Table
 D. Semantic Stack
Answer:


Question: Which of the following algorithms has running time Θ(n^2) in the worst case but Θ(n log n) on average?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following algorithms has running time Θ(n^2) in the worst case but Θ(n log n) on average?
 A. Bubblesort
 B. Mergesort
 C. Heapsort
 D. Quicksort
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Which of the following algorithms has running time Θ(n^2) in the worst case but Θ(n log n) on average?
 A. Bubblesort
 B. Mergesort
 C. Heapsort
 D. Quicksort
Answer:


Question: Which of the following algorithms has running time Θ(n^2) in the worst case but Θ(n log n) on average?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following algorithms has running time Θ(n^2) in the worst case but Θ(n log n) on average?
 A. Bubblesort
 B. Mergesort
 C. Heapsort
 D. Quicksort
Answer:


Question: Which of the following algorithms has running time Θ(n^2) in the worst case but Θ(n log n) on average?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following algorithms has running time Θ(n^2) in the worst case but Θ(n log n) on average?
 A. Bubblesort
 B. Mergesort
 C. Heapsort
 D. Quicksort
Answer:


Question: Which of the following algorithms has running time Θ(n^2) in the worst case but Θ(n log n) on average?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following algorithms has running time Θ(n^2) in the worst case but Θ(n log n) on average?
 A. Bubblesort
 B. Mergesort
 C. Heapsort
 D. Quicksort
Answer:


Question:
Languages with a structure that implements abstract data types (e.g., a C++ class) can prevent access to components of this structure by all operations except those that are part of this structure. However, definitions of such a structure often contain declarations of components of the structure (e.g., the header file for a C++ class may contain declarations of its private components). For such a language, an object's name could be bound at run time to stack storage for its component values (direct representation) or to a stack pointer referencing heap storage for its component values (indirect representation). Which of the following statements about comparisons between direct and indirect representations is (are) true?
I. Indirect representation noticeably increases compilation time.
II. Direct representation decreases the time needed to access components of a variable.
III. When the storage size of some private component of a variable changes, indirect representation minimizes the number of recompilations of source modules that must be performed.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Languages with a structure that implements abstract data types (e.g., a C++ class) can prevent access to components of this structure by all operations except those that are part of this structure. However, definitions of such a structure often contain declarations of components of the structure (e.g., the header file for a C++ class may contain declarations of its private components). For such a language, an object's name could be bound at run time to stack storage for its component values (direct representation) or to a stack pointer referencing heap storage for its component values (indirect representation). Which of the following statements about comparisons between direct and indirect representations is (are) true?
I. Indirect representation noticeably increases compilation time.
II. Direct representation decreases the time needed to access components of a variable.
III. When the storage size of some private component of a variable changes, indirect representation minimizes the number of recompilations of source modules that must be performed.
 A. I only
 B. III only
 C. I and II only
 D. II and III only
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Languages with a structure that implements abstract data types (e.g., a C++ class) can prevent access to components of this structure by all operations except those that are part of this structure. However, definitions of such a structure often contain declarations of components of the structure (e.g., the header file for a C++ class may contain declarations of its private components). For such a language, an object's name could be bound at run time to stack storage for its component values (direct representation) or to a stack pointer referencing heap storage for its component values (indirect representation). Which of the following statements about comparisons between direct and indirect representations is (are) true?
I. Indirect representation noticeably increases compilation time.
II. Direct representation decreases the time needed to access components of a variable.
III. When the storage size of some private component of a variable changes, indirect representation minimizes the number of recompilations of source modules that must be performed.
 A. I only
 B. III only
 C. I and II only
 D. II and III only
Answer:


Question:
Languages with a structure that implements abstract data types (e.g., a C++ class) can prevent access to components of this structure by all operations except those that are part of this structure. However, definitions of such a structure often contain declarations of components of the structure (e.g., the header file for a C++ class may contain declarations of its private components). For such a language, an object's name could be bound at run time to stack storage for its component values (direct representation) or to a stack pointer referencing heap storage for its component values (indirect representation). Which of the following statements about comparisons between direct and indirect representations is (are) true?
I. Indirect representation noticeably increases compilation time.
II. Direct representation decreases the time needed to access components of a variable.
III. When the storage size of some private component of a variable changes, indirect representation minimizes the number of recompilations of source modules that must be performed.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Languages with a structure that implements abstract data types (e.g., a C++ class) can prevent access to components of this structure by all operations except those that are part of this structure. However, definitions of such a structure often contain declarations of components of the structure (e.g., the header file for a C++ class may contain declarations of its private components). For such a language, an object's name could be bound at run time to stack storage for its component values (direct representation) or to a stack pointer referencing heap storage for its component values (indirect representation). Which of the following statements about comparisons between direct and indirect representations is (are) true?
I. Indirect representation noticeably increases compilation time.
II. Direct representation decreases the time needed to access components of a variable.
III. When the storage size of some private component of a variable changes, indirect representation minimizes the number of recompilations of source modules that must be performed.
 A. I only
 B. III only
 C. I and II only
 D. II and III only
Answer:


Question:
Languages with a structure that implements abstract data types (e.g., a C++ class) can prevent access to components of this structure by all operations except those that are part of this structure. However, definitions of such a structure often contain declarations of components of the structure (e.g., the header file for a C++ class may contain declarations of its private components). For such a language, an object's name could be bound at run time to stack storage for its component values (direct representation) or to a stack pointer referencing heap storage for its component values (indirect representation). Which of the following statements about comparisons between direct and indirect representations is (are) true?
I. Indirect representation noticeably increases compilation time.
II. Direct representation decreases the time needed to access components of a variable.
III. When the storage size of some private component of a variable changes, indirect representation minimizes the number of recompilations of source modules that must be performed.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Languages with a structure that implements abstract data types (e.g., a C++ class) can prevent access to components of this structure by all operations except those that are part of this structure. However, definitions of such a structure often contain declarations of components of the structure (e.g., the header file for a C++ class may contain declarations of its private components). For such a language, an object's name could be bound at run time to stack storage for its component values (direct representation) or to a stack pointer referencing heap storage for its component values (indirect representation). Which of the following statements about comparisons between direct and indirect representations is (are) true?
I. Indirect representation noticeably increases compilation time.
II. Direct representation decreases the time needed to access components of a variable.
III. When the storage size of some private component of a variable changes, indirect representation minimizes the number of recompilations of source modules that must be performed.
 A. I only
 B. III only
 C. I and II only
 D. II and III only
Answer:


Question:
Languages with a structure that implements abstract data types (e.g., a C++ class) can prevent access to components of this structure by all operations except those that are part of this structure. However, definitions of such a structure often contain declarations of components of the structure (e.g., the header file for a C++ class may contain declarations of its private components). For such a language, an object's name could be bound at run time to stack storage for its component values (direct representation) or to a stack pointer referencing heap storage for its component values (indirect representation). Which of the following statements about comparisons between direct and indirect representations is (are) true?
I. Indirect representation noticeably increases compilation time.
II. Direct representation decreases the time needed to access components of a variable.
III. When the storage size of some private component of a variable changes, indirect representation minimizes the number of recompilations of source modules that must be performed.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Languages with a structure that implements abstract data types (e.g., a C++ class) can prevent access to components of this structure by all operations except those that are part of this structure. However, definitions of such a structure often contain declarations of components of the structure (e.g., the header file for a C++ class may contain declarations of its private components). For such a language, an object's name could be bound at run time to stack storage for its component values (direct representation) or to a stack pointer referencing heap storage for its component values (indirect representation). Which of the following statements about comparisons between direct and indirect representations is (are) true?
I. Indirect representation noticeably increases compilation time.
II. Direct representation decreases the time needed to access components of a variable.
III. When the storage size of some private component of a variable changes, indirect representation minimizes the number of recompilations of source modules that must be performed.
 A. I only
 B. III only
 C. I and II only
 D. II and III only
Answer:


Question: Which of the following is NOT a property of bitmap graphics?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following is NOT a property of bitmap graphics?
 A. Fast hardware exists to move blocks of pixels efficiently.
 B. Realistic lighting and shading can be done.
 C. All line segments can be displayed as straight.
 D. Polygons can be filled with solid colors and textures.
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Which of the following is NOT a property of bitmap graphics?
 A. Fast hardware exists to move blocks of pixels efficiently.
 B. Realistic lighting and shading can be done.
 C. All line segments can be displayed as straight.
 D. Polygons can be filled with solid colors and textures.
Answer:


Question: Which of the following is NOT a property of bitmap graphics?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following is NOT a property of bitmap graphics?
 A. Fast hardware exists to move blocks of pixels efficiently.
 B. Realistic lighting and shading can be done.
 C. All line segments can be displayed as straight.
 D. Polygons can be filled with solid colors and textures.
Answer:


Question: Which of the following is NOT a property of bitmap graphics?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following is NOT a property of bitmap graphics?
 A. Fast hardware exists to move blocks of pixels efficiently.
 B. Realistic lighting and shading can be done.
 C. All line segments can be displayed as straight.
 D. Polygons can be filled with solid colors and textures.
Answer:


Question: Which of the following is NOT a property of bitmap graphics?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following is NOT a property of bitmap graphics?
 A. Fast hardware exists to move blocks of pixels efficiently.
 B. Realistic lighting and shading can be done.
 C. All line segments can be displayed as straight.
 D. Polygons can be filled with solid colors and textures.
Answer:


Question: Which of the following is true of interrupts?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following is true of interrupts?
 A. They are generated when memory cycles are "stolen".
 B. They are used in place of data channels.
 C. They can indicate completion of an I/O operation.
 D. They cannot be generated by arithmetic operations.
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Which of the following is true of interrupts?
 A. They are generated when memory cycles are "stolen".
 B. They are used in place of data channels.
 C. They can indicate completion of an I/O operation.
 D. They cannot be generated by arithmetic operations.
Answer:


Question: Which of the following is true of interrupts?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following is true of interrupts?
 A. They are generated when memory cycles are "stolen".
 B. They are used in place of data channels.
 C. They can indicate completion of an I/O operation.
 D. They cannot be generated by arithmetic operations.
Answer:


Question: Which of the following is true of interrupts?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following is true of interrupts?
 A. They are generated when memory cycles are "stolen".
 B. They are used in place of data channels.
 C. They can indicate completion of an I/O operation.
 D. They cannot be generated by arithmetic operations.
Answer:


Question: Which of the following is true of interrupts?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following is true of interrupts?
 A. They are generated when memory cycles are "stolen".
 B. They are used in place of data channels.
 C. They can indicate completion of an I/O operation.
 D. They cannot be generated by arithmetic operations.
Answer: