Question:
Function signatures describe the types of the arguments to a function as well as the return value of the function. For instance, the addition function on reals has a signature of
add : real x real -> real
since it takes two real numbers and returns a real number. But, for a language that allows functions as return values, addition could be considered to have the signature
add : real -> (real -> real)
which means that add takes a single real (the first operand) and returns a new function that itself takes a single real (the second operand) and returns a real (the result). This process of reducing a function with multiple arguments to a function with fewer arguments is called currying. Which of the following is correct?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Function signatures describe the types of the arguments to a function as well as the return value of the function. For instance, the addition function on reals has a signature of
add : real x real -> real
since it takes two real numbers and returns a real number. But, for a language that allows functions as return values, addition could be considered to have the signature
add : real -> (real -> real)
which means that add takes a single real (the first operand) and returns a new function that itself takes a single real (the second operand) and returns a real (the result). This process of reducing a function with multiple arguments to a function with fewer arguments is called currying. Which of the following is correct?
 A. Currying can be applied to any function to the point where it has exactly one input argument.
 B. Currying cannot be applied to functions of more than two arguments.
 C. Currying cannot be applied to functions that return functions as arguments.
 D. Currying cannot be applied w functions that haw arguments that are functions.
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Function signatures describe the types of the arguments to a function as well as the return value of the function. For instance, the addition function on reals has a signature of
add : real x real -> real
since it takes two real numbers and returns a real number. But, for a language that allows functions as return values, addition could be considered to have the signature
add : real -> (real -> real)
which means that add takes a single real (the first operand) and returns a new function that itself takes a single real (the second operand) and returns a real (the result). This process of reducing a function with multiple arguments to a function with fewer arguments is called currying. Which of the following is correct?
 A. Currying can be applied to any function to the point where it has exactly one input argument.
 B. Currying cannot be applied to functions of more than two arguments.
 C. Currying cannot be applied to functions that return functions as arguments.
 D. Currying cannot be applied w functions that haw arguments that are functions.
Answer:


Question:
Function signatures describe the types of the arguments to a function as well as the return value of the function. For instance, the addition function on reals has a signature of
add : real x real -> real
since it takes two real numbers and returns a real number. But, for a language that allows functions as return values, addition could be considered to have the signature
add : real -> (real -> real)
which means that add takes a single real (the first operand) and returns a new function that itself takes a single real (the second operand) and returns a real (the result). This process of reducing a function with multiple arguments to a function with fewer arguments is called currying. Which of the following is correct?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Function signatures describe the types of the arguments to a function as well as the return value of the function. For instance, the addition function on reals has a signature of
add : real x real -> real
since it takes two real numbers and returns a real number. But, for a language that allows functions as return values, addition could be considered to have the signature
add : real -> (real -> real)
which means that add takes a single real (the first operand) and returns a new function that itself takes a single real (the second operand) and returns a real (the result). This process of reducing a function with multiple arguments to a function with fewer arguments is called currying. Which of the following is correct?
 A. Currying can be applied to any function to the point where it has exactly one input argument.
 B. Currying cannot be applied to functions of more than two arguments.
 C. Currying cannot be applied to functions that return functions as arguments.
 D. Currying cannot be applied w functions that haw arguments that are functions.
Answer:


Question:
Function signatures describe the types of the arguments to a function as well as the return value of the function. For instance, the addition function on reals has a signature of
add : real x real -> real
since it takes two real numbers and returns a real number. But, for a language that allows functions as return values, addition could be considered to have the signature
add : real -> (real -> real)
which means that add takes a single real (the first operand) and returns a new function that itself takes a single real (the second operand) and returns a real (the result). This process of reducing a function with multiple arguments to a function with fewer arguments is called currying. Which of the following is correct?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Function signatures describe the types of the arguments to a function as well as the return value of the function. For instance, the addition function on reals has a signature of
add : real x real -> real
since it takes two real numbers and returns a real number. But, for a language that allows functions as return values, addition could be considered to have the signature
add : real -> (real -> real)
which means that add takes a single real (the first operand) and returns a new function that itself takes a single real (the second operand) and returns a real (the result). This process of reducing a function with multiple arguments to a function with fewer arguments is called currying. Which of the following is correct?
 A. Currying can be applied to any function to the point where it has exactly one input argument.
 B. Currying cannot be applied to functions of more than two arguments.
 C. Currying cannot be applied to functions that return functions as arguments.
 D. Currying cannot be applied w functions that haw arguments that are functions.
Answer:


Question:
Function signatures describe the types of the arguments to a function as well as the return value of the function. For instance, the addition function on reals has a signature of
add : real x real -> real
since it takes two real numbers and returns a real number. But, for a language that allows functions as return values, addition could be considered to have the signature
add : real -> (real -> real)
which means that add takes a single real (the first operand) and returns a new function that itself takes a single real (the second operand) and returns a real (the result). This process of reducing a function with multiple arguments to a function with fewer arguments is called currying. Which of the following is correct?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Function signatures describe the types of the arguments to a function as well as the return value of the function. For instance, the addition function on reals has a signature of
add : real x real -> real
since it takes two real numbers and returns a real number. But, for a language that allows functions as return values, addition could be considered to have the signature
add : real -> (real -> real)
which means that add takes a single real (the first operand) and returns a new function that itself takes a single real (the second operand) and returns a real (the result). This process of reducing a function with multiple arguments to a function with fewer arguments is called currying. Which of the following is correct?
 A. Currying can be applied to any function to the point where it has exactly one input argument.
 B. Currying cannot be applied to functions of more than two arguments.
 C. Currying cannot be applied to functions that return functions as arguments.
 D. Currying cannot be applied w functions that haw arguments that are functions.
Answer:


Question:
Array A contains 256 elements of 4 bytes each. Its first element is stored at physical address 4,096.
Array B contains 512 elements of 4 bytes each. Its first element is stored at physical address 8,192.
Assume that only arrays A and B can be cached in an initially empty, physically addressed, physically tagged, direct-mapped, 2K-byte cache with an 8-byte block size. The following loop is then executed.
for (i = 0; i < 256; i++)
        A[i] = A[i] + B[2*i];
During the execution of the loop, how many bytes will be written to memory if the cache has a write-back policy?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Array A contains 256 elements of 4 bytes each. Its first element is stored at physical address 4,096.
Array B contains 512 elements of 4 bytes each. Its first element is stored at physical address 8,192.
Assume that only arrays A and B can be cached in an initially empty, physically addressed, physically tagged, direct-mapped, 2K-byte cache with an 8-byte block size. The following loop is then executed.
for (i = 0; i < 256; i++)
        A[i] = A[i] + B[2*i];
During the execution of the loop, how many bytes will be written to memory if the cache has a write-back policy?
 A. 0
 B. 256
 C. 1024
 D. 2000
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Array A contains 256 elements of 4 bytes each. Its first element is stored at physical address 4,096.
Array B contains 512 elements of 4 bytes each. Its first element is stored at physical address 8,192.
Assume that only arrays A and B can be cached in an initially empty, physically addressed, physically tagged, direct-mapped, 2K-byte cache with an 8-byte block size. The following loop is then executed.
for (i = 0; i < 256; i++)
        A[i] = A[i] + B[2*i];
During the execution of the loop, how many bytes will be written to memory if the cache has a write-back policy?
 A. 0
 B. 256
 C. 1024
 D. 2000
Answer:


Question:
Array A contains 256 elements of 4 bytes each. Its first element is stored at physical address 4,096.
Array B contains 512 elements of 4 bytes each. Its first element is stored at physical address 8,192.
Assume that only arrays A and B can be cached in an initially empty, physically addressed, physically tagged, direct-mapped, 2K-byte cache with an 8-byte block size. The following loop is then executed.
for (i = 0; i < 256; i++)
        A[i] = A[i] + B[2*i];
During the execution of the loop, how many bytes will be written to memory if the cache has a write-back policy?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Array A contains 256 elements of 4 bytes each. Its first element is stored at physical address 4,096.
Array B contains 512 elements of 4 bytes each. Its first element is stored at physical address 8,192.
Assume that only arrays A and B can be cached in an initially empty, physically addressed, physically tagged, direct-mapped, 2K-byte cache with an 8-byte block size. The following loop is then executed.
for (i = 0; i < 256; i++)
        A[i] = A[i] + B[2*i];
During the execution of the loop, how many bytes will be written to memory if the cache has a write-back policy?
 A. 0
 B. 256
 C. 1024
 D. 2000
Answer:


Question:
Array A contains 256 elements of 4 bytes each. Its first element is stored at physical address 4,096.
Array B contains 512 elements of 4 bytes each. Its first element is stored at physical address 8,192.
Assume that only arrays A and B can be cached in an initially empty, physically addressed, physically tagged, direct-mapped, 2K-byte cache with an 8-byte block size. The following loop is then executed.
for (i = 0; i < 256; i++)
        A[i] = A[i] + B[2*i];
During the execution of the loop, how many bytes will be written to memory if the cache has a write-back policy?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Array A contains 256 elements of 4 bytes each. Its first element is stored at physical address 4,096.
Array B contains 512 elements of 4 bytes each. Its first element is stored at physical address 8,192.
Assume that only arrays A and B can be cached in an initially empty, physically addressed, physically tagged, direct-mapped, 2K-byte cache with an 8-byte block size. The following loop is then executed.
for (i = 0; i < 256; i++)
        A[i] = A[i] + B[2*i];
During the execution of the loop, how many bytes will be written to memory if the cache has a write-back policy?
 A. 0
 B. 256
 C. 1024
 D. 2000
Answer:


Question:
Array A contains 256 elements of 4 bytes each. Its first element is stored at physical address 4,096.
Array B contains 512 elements of 4 bytes each. Its first element is stored at physical address 8,192.
Assume that only arrays A and B can be cached in an initially empty, physically addressed, physically tagged, direct-mapped, 2K-byte cache with an 8-byte block size. The following loop is then executed.
for (i = 0; i < 256; i++)
        A[i] = A[i] + B[2*i];
During the execution of the loop, how many bytes will be written to memory if the cache has a write-back policy?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Array A contains 256 elements of 4 bytes each. Its first element is stored at physical address 4,096.
Array B contains 512 elements of 4 bytes each. Its first element is stored at physical address 8,192.
Assume that only arrays A and B can be cached in an initially empty, physically addressed, physically tagged, direct-mapped, 2K-byte cache with an 8-byte block size. The following loop is then executed.
for (i = 0; i < 256; i++)
        A[i] = A[i] + B[2*i];
During the execution of the loop, how many bytes will be written to memory if the cache has a write-back policy?
 A. 0
 B. 256
 C. 1024
 D. 2000
Answer:


Question:
In which of the following representations of numbers by 8-bit words is the addition of the integers 109 and -42 within range?
I. One's complement
II. Two's complement
III. Sign and magnitude

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: In which of the following representations of numbers by 8-bit words is the addition of the integers 109 and -42 within range?
I. One's complement
II. Two's complement
III. Sign and magnitude
 A. I only
 B. II only
 C. I and II only
 D. I, II, and III
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: In which of the following representations of numbers by 8-bit words is the addition of the integers 109 and -42 within range?
I. One's complement
II. Two's complement
III. Sign and magnitude
 A. I only
 B. II only
 C. I and II only
 D. I, II, and III
Answer:


Question:
In which of the following representations of numbers by 8-bit words is the addition of the integers 109 and -42 within range?
I. One's complement
II. Two's complement
III. Sign and magnitude

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: In which of the following representations of numbers by 8-bit words is the addition of the integers 109 and -42 within range?
I. One's complement
II. Two's complement
III. Sign and magnitude
 A. I only
 B. II only
 C. I and II only
 D. I, II, and III
Answer:


Question:
In which of the following representations of numbers by 8-bit words is the addition of the integers 109 and -42 within range?
I. One's complement
II. Two's complement
III. Sign and magnitude

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: In which of the following representations of numbers by 8-bit words is the addition of the integers 109 and -42 within range?
I. One's complement
II. Two's complement
III. Sign and magnitude
 A. I only
 B. II only
 C. I and II only
 D. I, II, and III
Answer:


Question:
In which of the following representations of numbers by 8-bit words is the addition of the integers 109 and -42 within range?
I. One's complement
II. Two's complement
III. Sign and magnitude

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: In which of the following representations of numbers by 8-bit words is the addition of the integers 109 and -42 within range?
I. One's complement
II. Two's complement
III. Sign and magnitude
 A. I only
 B. II only
 C. I and II only
 D. I, II, and III
Answer:


Question: If a malicious process is granted temporary administrator-level access to a system

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: If a malicious process is granted temporary administrator-level access to a system
 A. the threat is over as soon as the process is killed
 B. the threat is over after the operating system is rebooted
 C. the thread is over after rebooting the machine and replacing files that show a virus infection
 D. the threat is often permanent until the entire disk is wiped clean
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: If a malicious process is granted temporary administrator-level access to a system
 A. the threat is over as soon as the process is killed
 B. the threat is over after the operating system is rebooted
 C. the thread is over after rebooting the machine and replacing files that show a virus infection
 D. the threat is often permanent until the entire disk is wiped clean
Answer:


Question: If a malicious process is granted temporary administrator-level access to a system

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: If a malicious process is granted temporary administrator-level access to a system
 A. the threat is over as soon as the process is killed
 B. the threat is over after the operating system is rebooted
 C. the thread is over after rebooting the machine and replacing files that show a virus infection
 D. the threat is often permanent until the entire disk is wiped clean
Answer:


Question: If a malicious process is granted temporary administrator-level access to a system

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: If a malicious process is granted temporary administrator-level access to a system
 A. the threat is over as soon as the process is killed
 B. the threat is over after the operating system is rebooted
 C. the thread is over after rebooting the machine and replacing files that show a virus infection
 D. the threat is often permanent until the entire disk is wiped clean
Answer:


Question: If a malicious process is granted temporary administrator-level access to a system

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: If a malicious process is granted temporary administrator-level access to a system
 A. the threat is over as soon as the process is killed
 B. the threat is over after the operating system is rebooted
 C. the thread is over after rebooting the machine and replacing files that show a virus infection
 D. the threat is often permanent until the entire disk is wiped clean
Answer:


Question:
Which of the following statements about horizontal versus vertical microarchitecture is (are) true?
I. Programs for horizontal architectures require more time steps than those for vertical architectures.
II. Horizontal microinstructions are unencoded.
III. Horizontal microinstructions usually have a single opcode and multiple operand specifiers.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following statements about horizontal versus vertical microarchitecture is (are) true?
I. Programs for horizontal architectures require more time steps than those for vertical architectures.
II. Horizontal microinstructions are unencoded.
III. Horizontal microinstructions usually have a single opcode and multiple operand specifiers.
 A. I only
 B. II only
 C. III only
 D. II and III only
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Which of the following statements about horizontal versus vertical microarchitecture is (are) true?
I. Programs for horizontal architectures require more time steps than those for vertical architectures.
II. Horizontal microinstructions are unencoded.
III. Horizontal microinstructions usually have a single opcode and multiple operand specifiers.
 A. I only
 B. II only
 C. III only
 D. II and III only
Answer:


Question:
Which of the following statements about horizontal versus vertical microarchitecture is (are) true?
I. Programs for horizontal architectures require more time steps than those for vertical architectures.
II. Horizontal microinstructions are unencoded.
III. Horizontal microinstructions usually have a single opcode and multiple operand specifiers.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following statements about horizontal versus vertical microarchitecture is (are) true?
I. Programs for horizontal architectures require more time steps than those for vertical architectures.
II. Horizontal microinstructions are unencoded.
III. Horizontal microinstructions usually have a single opcode and multiple operand specifiers.
 A. I only
 B. II only
 C. III only
 D. II and III only
Answer:


Question:
Which of the following statements about horizontal versus vertical microarchitecture is (are) true?
I. Programs for horizontal architectures require more time steps than those for vertical architectures.
II. Horizontal microinstructions are unencoded.
III. Horizontal microinstructions usually have a single opcode and multiple operand specifiers.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following statements about horizontal versus vertical microarchitecture is (are) true?
I. Programs for horizontal architectures require more time steps than those for vertical architectures.
II. Horizontal microinstructions are unencoded.
III. Horizontal microinstructions usually have a single opcode and multiple operand specifiers.
 A. I only
 B. II only
 C. III only
 D. II and III only
Answer:


Question:
Which of the following statements about horizontal versus vertical microarchitecture is (are) true?
I. Programs for horizontal architectures require more time steps than those for vertical architectures.
II. Horizontal microinstructions are unencoded.
III. Horizontal microinstructions usually have a single opcode and multiple operand specifiers.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following statements about horizontal versus vertical microarchitecture is (are) true?
I. Programs for horizontal architectures require more time steps than those for vertical architectures.
II. Horizontal microinstructions are unencoded.
III. Horizontal microinstructions usually have a single opcode and multiple operand specifiers.
 A. I only
 B. II only
 C. III only
 D. II and III only
Answer:


Question: A "strictly binary tree" is a binary tree in which every node that is not a leaf has two children. Suppose that for a class of strictly binary trees there exists c > 0 such that, for any tree in the class, the ratio of the lengths of any two root-to-leaf paths is bounded above by c. Which of the following best characterizes the height h of any tree in this class, where N is the number of nodes in the tree and N > 1 ?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: A "strictly binary tree" is a binary tree in which every node that is not a leaf has two children. Suppose that for a class of strictly binary trees there exists c > 0 such that, for any tree in the class, the ratio of the lengths of any two root-to-leaf paths is bounded above by c. Which of the following best characterizes the height h of any tree in this class, where N is the number of nodes in the tree and N > 1 ?
 A. h <= log2(N)
 B. h = 1/c * log2(N)
 C. h < c log2(N)
 D. h > c log2(N)
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: A "strictly binary tree" is a binary tree in which every node that is not a leaf has two children. Suppose that for a class of strictly binary trees there exists c > 0 such that, for any tree in the class, the ratio of the lengths of any two root-to-leaf paths is bounded above by c. Which of the following best characterizes the height h of any tree in this class, where N is the number of nodes in the tree and N > 1 ?
 A. h <= log2(N)
 B. h = 1/c * log2(N)
 C. h < c log2(N)
 D. h > c log2(N)
Answer:


Question: A "strictly binary tree" is a binary tree in which every node that is not a leaf has two children. Suppose that for a class of strictly binary trees there exists c > 0 such that, for any tree in the class, the ratio of the lengths of any two root-to-leaf paths is bounded above by c. Which of the following best characterizes the height h of any tree in this class, where N is the number of nodes in the tree and N > 1 ?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: A "strictly binary tree" is a binary tree in which every node that is not a leaf has two children. Suppose that for a class of strictly binary trees there exists c > 0 such that, for any tree in the class, the ratio of the lengths of any two root-to-leaf paths is bounded above by c. Which of the following best characterizes the height h of any tree in this class, where N is the number of nodes in the tree and N > 1 ?
 A. h <= log2(N)
 B. h = 1/c * log2(N)
 C. h < c log2(N)
 D. h > c log2(N)
Answer:


Question: A "strictly binary tree" is a binary tree in which every node that is not a leaf has two children. Suppose that for a class of strictly binary trees there exists c > 0 such that, for any tree in the class, the ratio of the lengths of any two root-to-leaf paths is bounded above by c. Which of the following best characterizes the height h of any tree in this class, where N is the number of nodes in the tree and N > 1 ?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: A "strictly binary tree" is a binary tree in which every node that is not a leaf has two children. Suppose that for a class of strictly binary trees there exists c > 0 such that, for any tree in the class, the ratio of the lengths of any two root-to-leaf paths is bounded above by c. Which of the following best characterizes the height h of any tree in this class, where N is the number of nodes in the tree and N > 1 ?
 A. h <= log2(N)
 B. h = 1/c * log2(N)
 C. h < c log2(N)
 D. h > c log2(N)
Answer:


Question: A "strictly binary tree" is a binary tree in which every node that is not a leaf has two children. Suppose that for a class of strictly binary trees there exists c > 0 such that, for any tree in the class, the ratio of the lengths of any two root-to-leaf paths is bounded above by c. Which of the following best characterizes the height h of any tree in this class, where N is the number of nodes in the tree and N > 1 ?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: A "strictly binary tree" is a binary tree in which every node that is not a leaf has two children. Suppose that for a class of strictly binary trees there exists c > 0 such that, for any tree in the class, the ratio of the lengths of any two root-to-leaf paths is bounded above by c. Which of the following best characterizes the height h of any tree in this class, where N is the number of nodes in the tree and N > 1 ?
 A. h <= log2(N)
 B. h = 1/c * log2(N)
 C. h < c log2(N)
 D. h > c log2(N)
Answer:


Question: Which of the following sorting algorithms has average-case and worst-case running times of O(n log n)?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following sorting algorithms has average-case and worst-case running times of O(n log n)?
 A. Bubble sort
 B. Insertion sort
 C. Merge sort
 D. Quicksort
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Which of the following sorting algorithms has average-case and worst-case running times of O(n log n)?
 A. Bubble sort
 B. Insertion sort
 C. Merge sort
 D. Quicksort
Answer:


Question: Which of the following sorting algorithms has average-case and worst-case running times of O(n log n)?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following sorting algorithms has average-case and worst-case running times of O(n log n)?
 A. Bubble sort
 B. Insertion sort
 C. Merge sort
 D. Quicksort
Answer:


Question: Which of the following sorting algorithms has average-case and worst-case running times of O(n log n)?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following sorting algorithms has average-case and worst-case running times of O(n log n)?
 A. Bubble sort
 B. Insertion sort
 C. Merge sort
 D. Quicksort
Answer:


Question: Which of the following sorting algorithms has average-case and worst-case running times of O(n log n)?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following sorting algorithms has average-case and worst-case running times of O(n log n)?
 A. Bubble sort
 B. Insertion sort
 C. Merge sort
 D. Quicksort
Answer:


Question: Consider the following equations concerning a stack module that has the operations Push, Pop, Top, and IsEmpty. Which of the equations does NOT represent the conventional semantics of a stack?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Consider the following equations concerning a stack module that has the operations Push, Pop, Top, and IsEmpty. Which of the equations does NOT represent the conventional semantics of a stack?
 A. IsEmpty(Push(Stack,Elem)) = true
 B. Pop(Push(Stack,Elem)) = Stack
 C. Top(Push(Stack,Elem)) = Elem
 D. IsEmpty(Push(Push(Stack,Elem1),Elem2)) = false
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Consider the following equations concerning a stack module that has the operations Push, Pop, Top, and IsEmpty. Which of the equations does NOT represent the conventional semantics of a stack?
 A. IsEmpty(Push(Stack,Elem)) = true
 B. Pop(Push(Stack,Elem)) = Stack
 C. Top(Push(Stack,Elem)) = Elem
 D. IsEmpty(Push(Push(Stack,Elem1),Elem2)) = false
Answer:


Question: Consider the following equations concerning a stack module that has the operations Push, Pop, Top, and IsEmpty. Which of the equations does NOT represent the conventional semantics of a stack?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Consider the following equations concerning a stack module that has the operations Push, Pop, Top, and IsEmpty. Which of the equations does NOT represent the conventional semantics of a stack?
 A. IsEmpty(Push(Stack,Elem)) = true
 B. Pop(Push(Stack,Elem)) = Stack
 C. Top(Push(Stack,Elem)) = Elem
 D. IsEmpty(Push(Push(Stack,Elem1),Elem2)) = false
Answer:


Question: Consider the following equations concerning a stack module that has the operations Push, Pop, Top, and IsEmpty. Which of the equations does NOT represent the conventional semantics of a stack?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Consider the following equations concerning a stack module that has the operations Push, Pop, Top, and IsEmpty. Which of the equations does NOT represent the conventional semantics of a stack?
 A. IsEmpty(Push(Stack,Elem)) = true
 B. Pop(Push(Stack,Elem)) = Stack
 C. Top(Push(Stack,Elem)) = Elem
 D. IsEmpty(Push(Push(Stack,Elem1),Elem2)) = false
Answer:


Question: Consider the following equations concerning a stack module that has the operations Push, Pop, Top, and IsEmpty. Which of the equations does NOT represent the conventional semantics of a stack?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Consider the following equations concerning a stack module that has the operations Push, Pop, Top, and IsEmpty. Which of the equations does NOT represent the conventional semantics of a stack?
 A. IsEmpty(Push(Stack,Elem)) = true
 B. Pop(Push(Stack,Elem)) = Stack
 C. Top(Push(Stack,Elem)) = Elem
 D. IsEmpty(Push(Push(Stack,Elem1),Elem2)) = false
Answer:


Question:
Assume that any assignment statement can be executed in unit time. If as many identical processors as needed are used, what is the minimum number of time units needed to execute the assignments
A := B + C
B := A - B
C := A * E
D := A/F
E := B - C
F := A + B
with the same result as if the assignments were executed in the order shown?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Assume that any assignment statement can be executed in unit time. If as many identical processors as needed are used, what is the minimum number of time units needed to execute the assignments
A := B + C
B := A - B
C := A * E
D := A/F
E := B - C
F := A + B
with the same result as if the assignments were executed in the order shown?
 A. 1
 B. 2
 C. 3
 D. 4
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Assume that any assignment statement can be executed in unit time. If as many identical processors as needed are used, what is the minimum number of time units needed to execute the assignments
A := B + C
B := A - B
C := A * E
D := A/F
E := B - C
F := A + B
with the same result as if the assignments were executed in the order shown?
 A. 1
 B. 2
 C. 3
 D. 4
Answer:


Question:
Assume that any assignment statement can be executed in unit time. If as many identical processors as needed are used, what is the minimum number of time units needed to execute the assignments
A := B + C
B := A - B
C := A * E
D := A/F
E := B - C
F := A + B
with the same result as if the assignments were executed in the order shown?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Assume that any assignment statement can be executed in unit time. If as many identical processors as needed are used, what is the minimum number of time units needed to execute the assignments
A := B + C
B := A - B
C := A * E
D := A/F
E := B - C
F := A + B
with the same result as if the assignments were executed in the order shown?
 A. 1
 B. 2
 C. 3
 D. 4
Answer:


Question:
Assume that any assignment statement can be executed in unit time. If as many identical processors as needed are used, what is the minimum number of time units needed to execute the assignments
A := B + C
B := A - B
C := A * E
D := A/F
E := B - C
F := A + B
with the same result as if the assignments were executed in the order shown?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Assume that any assignment statement can be executed in unit time. If as many identical processors as needed are used, what is the minimum number of time units needed to execute the assignments
A := B + C
B := A - B
C := A * E
D := A/F
E := B - C
F := A + B
with the same result as if the assignments were executed in the order shown?
 A. 1
 B. 2
 C. 3
 D. 4
Answer:


Question:
Assume that any assignment statement can be executed in unit time. If as many identical processors as needed are used, what is the minimum number of time units needed to execute the assignments
A := B + C
B := A - B
C := A * E
D := A/F
E := B - C
F := A + B
with the same result as if the assignments were executed in the order shown?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Assume that any assignment statement can be executed in unit time. If as many identical processors as needed are used, what is the minimum number of time units needed to execute the assignments
A := B + C
B := A - B
C := A * E
D := A/F
E := B - C
F := A + B
with the same result as if the assignments were executed in the order shown?
 A. 1
 B. 2
 C. 3
 D. 4
Answer:


Question:
Two expressions E and F are said to be unifiable if there are substitutions for the variables of E and F that make the expressions lexically identical. In the following three expressions, only w, x, y, and z are variables.
I. f(w,w)
II. f(x,1)
III. f(y,g(z))
Which pairs of these expressions is (are) pairs of unifiable expressions?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Two expressions E and F are said to be unifiable if there are substitutions for the variables of E and F that make the expressions lexically identical. In the following three expressions, only w, x, y, and z are variables.
I. f(w,w)
II. f(x,1)
III. f(y,g(z))
Which pairs of these expressions is (are) pairs of unifiable expressions?
 A. (I, II) only
 B. (I, III) only
 C. (II, III) only
 D. (I, II) and (I, III) only
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Two expressions E and F are said to be unifiable if there are substitutions for the variables of E and F that make the expressions lexically identical. In the following three expressions, only w, x, y, and z are variables.
I. f(w,w)
II. f(x,1)
III. f(y,g(z))
Which pairs of these expressions is (are) pairs of unifiable expressions?
 A. (I, II) only
 B. (I, III) only
 C. (II, III) only
 D. (I, II) and (I, III) only
Answer:


Question:
Two expressions E and F are said to be unifiable if there are substitutions for the variables of E and F that make the expressions lexically identical. In the following three expressions, only w, x, y, and z are variables.
I. f(w,w)
II. f(x,1)
III. f(y,g(z))
Which pairs of these expressions is (are) pairs of unifiable expressions?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Two expressions E and F are said to be unifiable if there are substitutions for the variables of E and F that make the expressions lexically identical. In the following three expressions, only w, x, y, and z are variables.
I. f(w,w)
II. f(x,1)
III. f(y,g(z))
Which pairs of these expressions is (are) pairs of unifiable expressions?
 A. (I, II) only
 B. (I, III) only
 C. (II, III) only
 D. (I, II) and (I, III) only
Answer:


Question:
Two expressions E and F are said to be unifiable if there are substitutions for the variables of E and F that make the expressions lexically identical. In the following three expressions, only w, x, y, and z are variables.
I. f(w,w)
II. f(x,1)
III. f(y,g(z))
Which pairs of these expressions is (are) pairs of unifiable expressions?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Two expressions E and F are said to be unifiable if there are substitutions for the variables of E and F that make the expressions lexically identical. In the following three expressions, only w, x, y, and z are variables.
I. f(w,w)
II. f(x,1)
III. f(y,g(z))
Which pairs of these expressions is (are) pairs of unifiable expressions?
 A. (I, II) only
 B. (I, III) only
 C. (II, III) only
 D. (I, II) and (I, III) only
Answer:


Question:
Two expressions E and F are said to be unifiable if there are substitutions for the variables of E and F that make the expressions lexically identical. In the following three expressions, only w, x, y, and z are variables.
I. f(w,w)
II. f(x,1)
III. f(y,g(z))
Which pairs of these expressions is (are) pairs of unifiable expressions?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Two expressions E and F are said to be unifiable if there are substitutions for the variables of E and F that make the expressions lexically identical. In the following three expressions, only w, x, y, and z are variables.
I. f(w,w)
II. f(x,1)
III. f(y,g(z))
Which pairs of these expressions is (are) pairs of unifiable expressions?
 A. (I, II) only
 B. (I, III) only
 C. (II, III) only
 D. (I, II) and (I, III) only
Answer:


Question: Which of the following instruction-set features is NOT generally considered an obstacle to aggressive pipelining of an integer unit?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following instruction-set features is NOT generally considered an obstacle to aggressive pipelining of an integer unit?
 A. Condition codes set by every instruction
 B. Variable-length encoding of instructions
 C. Instructions requiring widely varying numbers of cycles to execute
 D. Several different classes (sets) of registers
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Which of the following instruction-set features is NOT generally considered an obstacle to aggressive pipelining of an integer unit?
 A. Condition codes set by every instruction
 B. Variable-length encoding of instructions
 C. Instructions requiring widely varying numbers of cycles to execute
 D. Several different classes (sets) of registers
Answer:


Question: Which of the following instruction-set features is NOT generally considered an obstacle to aggressive pipelining of an integer unit?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following instruction-set features is NOT generally considered an obstacle to aggressive pipelining of an integer unit?
 A. Condition codes set by every instruction
 B. Variable-length encoding of instructions
 C. Instructions requiring widely varying numbers of cycles to execute
 D. Several different classes (sets) of registers
Answer:


Question: Which of the following instruction-set features is NOT generally considered an obstacle to aggressive pipelining of an integer unit?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following instruction-set features is NOT generally considered an obstacle to aggressive pipelining of an integer unit?
 A. Condition codes set by every instruction
 B. Variable-length encoding of instructions
 C. Instructions requiring widely varying numbers of cycles to execute
 D. Several different classes (sets) of registers
Answer:


Question: Which of the following instruction-set features is NOT generally considered an obstacle to aggressive pipelining of an integer unit?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following instruction-set features is NOT generally considered an obstacle to aggressive pipelining of an integer unit?
 A. Condition codes set by every instruction
 B. Variable-length encoding of instructions
 C. Instructions requiring widely varying numbers of cycles to execute
 D. Several different classes (sets) of registers
Answer:


Question: Let k >= 2. Let L be the set of strings in {0, 1}^* such that x \in L if and only if the number of 0's in x is divisible by k and the number of 1's in x is odd. The minimum number of states in a deterministic finite automaton (DFA) that recognizes L is

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let k >= 2. Let L be the set of strings in {0, 1}^* such that x \in L if and only if the number of 0's in x is divisible by k and the number of 1's in x is odd. The minimum number of states in a deterministic finite automaton (DFA) that recognizes L is
 A. k + 2
 B. 2k
 C. k log k
 D. k^2
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Let k >= 2. Let L be the set of strings in {0, 1}^* such that x \in L if and only if the number of 0's in x is divisible by k and the number of 1's in x is odd. The minimum number of states in a deterministic finite automaton (DFA) that recognizes L is
 A. k + 2
 B. 2k
 C. k log k
 D. k^2
Answer:


Question: Let k >= 2. Let L be the set of strings in {0, 1}^* such that x \in L if and only if the number of 0's in x is divisible by k and the number of 1's in x is odd. The minimum number of states in a deterministic finite automaton (DFA) that recognizes L is

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let k >= 2. Let L be the set of strings in {0, 1}^* such that x \in L if and only if the number of 0's in x is divisible by k and the number of 1's in x is odd. The minimum number of states in a deterministic finite automaton (DFA) that recognizes L is
 A. k + 2
 B. 2k
 C. k log k
 D. k^2
Answer:


Question: Let k >= 2. Let L be the set of strings in {0, 1}^* such that x \in L if and only if the number of 0's in x is divisible by k and the number of 1's in x is odd. The minimum number of states in a deterministic finite automaton (DFA) that recognizes L is

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let k >= 2. Let L be the set of strings in {0, 1}^* such that x \in L if and only if the number of 0's in x is divisible by k and the number of 1's in x is odd. The minimum number of states in a deterministic finite automaton (DFA) that recognizes L is
 A. k + 2
 B. 2k
 C. k log k
 D. k^2
Answer:


Question: Let k >= 2. Let L be the set of strings in {0, 1}^* such that x \in L if and only if the number of 0's in x is divisible by k and the number of 1's in x is odd. The minimum number of states in a deterministic finite automaton (DFA) that recognizes L is

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let k >= 2. Let L be the set of strings in {0, 1}^* such that x \in L if and only if the number of 0's in x is divisible by k and the number of 1's in x is odd. The minimum number of states in a deterministic finite automaton (DFA) that recognizes L is
 A. k + 2
 B. 2k
 C. k log k
 D. k^2
Answer:


Question:
Let G = (V, E) be a finite directed acyclic graph with |E| > 0. Which of the following must be true?
I. G has a vertex with no incoming edge.
II. G has a vertex with no outgoing edge.
III. G has an isolated vertex, that is, one with neither an incoming edge nor an outgoing edge.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let G = (V, E) be a finite directed acyclic graph with |E| > 0. Which of the following must be true?
I. G has a vertex with no incoming edge.
II. G has a vertex with no outgoing edge.
III. G has an isolated vertex, that is, one with neither an incoming edge nor an outgoing edge.
 A. I only
 B. II only
 C. III only
 D. I and II only
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Let G = (V, E) be a finite directed acyclic graph with |E| > 0. Which of the following must be true?
I. G has a vertex with no incoming edge.
II. G has a vertex with no outgoing edge.
III. G has an isolated vertex, that is, one with neither an incoming edge nor an outgoing edge.
 A. I only
 B. II only
 C. III only
 D. I and II only
Answer:


Question:
Let G = (V, E) be a finite directed acyclic graph with |E| > 0. Which of the following must be true?
I. G has a vertex with no incoming edge.
II. G has a vertex with no outgoing edge.
III. G has an isolated vertex, that is, one with neither an incoming edge nor an outgoing edge.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let G = (V, E) be a finite directed acyclic graph with |E| > 0. Which of the following must be true?
I. G has a vertex with no incoming edge.
II. G has a vertex with no outgoing edge.
III. G has an isolated vertex, that is, one with neither an incoming edge nor an outgoing edge.
 A. I only
 B. II only
 C. III only
 D. I and II only
Answer:


Question:
Let G = (V, E) be a finite directed acyclic graph with |E| > 0. Which of the following must be true?
I. G has a vertex with no incoming edge.
II. G has a vertex with no outgoing edge.
III. G has an isolated vertex, that is, one with neither an incoming edge nor an outgoing edge.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let G = (V, E) be a finite directed acyclic graph with |E| > 0. Which of the following must be true?
I. G has a vertex with no incoming edge.
II. G has a vertex with no outgoing edge.
III. G has an isolated vertex, that is, one with neither an incoming edge nor an outgoing edge.
 A. I only
 B. II only
 C. III only
 D. I and II only
Answer:


Question:
Let G = (V, E) be a finite directed acyclic graph with |E| > 0. Which of the following must be true?
I. G has a vertex with no incoming edge.
II. G has a vertex with no outgoing edge.
III. G has an isolated vertex, that is, one with neither an incoming edge nor an outgoing edge.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let G = (V, E) be a finite directed acyclic graph with |E| > 0. Which of the following must be true?
I. G has a vertex with no incoming edge.
II. G has a vertex with no outgoing edge.
III. G has an isolated vertex, that is, one with neither an incoming edge nor an outgoing edge.
 A. I only
 B. II only
 C. III only
 D. I and II only
Answer:


Question:
Let T be a depth-first search tree of a connected undirected graph G. For each vertex v of T, let pre(v) be the number of nodes visited up to and including v during a preorder traversal of T, and post(v) be the number of nodes visited up to and including v during a postorder traversal of T. The lowest common ancestor of vertices u and v in T is a vertex w of T such that w is an ancestor of both u and v, and no child of w is an ancestor of both u and v. Let (u, v) be an edge in G that is not in T, such that pre(u) < pre(v). Which of the following statements about u and v must be true?
I. post(u) < post(v)
II. u is an ancestor of v in T.
III. If w is the lowest common ancestor of u and v in T, then w = u.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let T be a depth-first search tree of a connected undirected graph G. For each vertex v of T, let pre(v) be the number of nodes visited up to and including v during a preorder traversal of T, and post(v) be the number of nodes visited up to and including v during a postorder traversal of T. The lowest common ancestor of vertices u and v in T is a vertex w of T such that w is an ancestor of both u and v, and no child of w is an ancestor of both u and v. Let (u, v) be an edge in G that is not in T, such that pre(u) < pre(v). Which of the following statements about u and v must be true?
I. post(u) < post(v)
II. u is an ancestor of v in T.
III. If w is the lowest common ancestor of u and v in T, then w = u.
 A. I only
 B. II only
 C. III only
 D. II and III
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Let T be a depth-first search tree of a connected undirected graph G. For each vertex v of T, let pre(v) be the number of nodes visited up to and including v during a preorder traversal of T, and post(v) be the number of nodes visited up to and including v during a postorder traversal of T. The lowest common ancestor of vertices u and v in T is a vertex w of T such that w is an ancestor of both u and v, and no child of w is an ancestor of both u and v. Let (u, v) be an edge in G that is not in T, such that pre(u) < pre(v). Which of the following statements about u and v must be true?
I. post(u) < post(v)
II. u is an ancestor of v in T.
III. If w is the lowest common ancestor of u and v in T, then w = u.
 A. I only
 B. II only
 C. III only
 D. II and III
Answer:


Question:
Let T be a depth-first search tree of a connected undirected graph G. For each vertex v of T, let pre(v) be the number of nodes visited up to and including v during a preorder traversal of T, and post(v) be the number of nodes visited up to and including v during a postorder traversal of T. The lowest common ancestor of vertices u and v in T is a vertex w of T such that w is an ancestor of both u and v, and no child of w is an ancestor of both u and v. Let (u, v) be an edge in G that is not in T, such that pre(u) < pre(v). Which of the following statements about u and v must be true?
I. post(u) < post(v)
II. u is an ancestor of v in T.
III. If w is the lowest common ancestor of u and v in T, then w = u.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let T be a depth-first search tree of a connected undirected graph G. For each vertex v of T, let pre(v) be the number of nodes visited up to and including v during a preorder traversal of T, and post(v) be the number of nodes visited up to and including v during a postorder traversal of T. The lowest common ancestor of vertices u and v in T is a vertex w of T such that w is an ancestor of both u and v, and no child of w is an ancestor of both u and v. Let (u, v) be an edge in G that is not in T, such that pre(u) < pre(v). Which of the following statements about u and v must be true?
I. post(u) < post(v)
II. u is an ancestor of v in T.
III. If w is the lowest common ancestor of u and v in T, then w = u.
 A. I only
 B. II only
 C. III only
 D. II and III
Answer:


Question:
Let T be a depth-first search tree of a connected undirected graph G. For each vertex v of T, let pre(v) be the number of nodes visited up to and including v during a preorder traversal of T, and post(v) be the number of nodes visited up to and including v during a postorder traversal of T. The lowest common ancestor of vertices u and v in T is a vertex w of T such that w is an ancestor of both u and v, and no child of w is an ancestor of both u and v. Let (u, v) be an edge in G that is not in T, such that pre(u) < pre(v). Which of the following statements about u and v must be true?
I. post(u) < post(v)
II. u is an ancestor of v in T.
III. If w is the lowest common ancestor of u and v in T, then w = u.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let T be a depth-first search tree of a connected undirected graph G. For each vertex v of T, let pre(v) be the number of nodes visited up to and including v during a preorder traversal of T, and post(v) be the number of nodes visited up to and including v during a postorder traversal of T. The lowest common ancestor of vertices u and v in T is a vertex w of T such that w is an ancestor of both u and v, and no child of w is an ancestor of both u and v. Let (u, v) be an edge in G that is not in T, such that pre(u) < pre(v). Which of the following statements about u and v must be true?
I. post(u) < post(v)
II. u is an ancestor of v in T.
III. If w is the lowest common ancestor of u and v in T, then w = u.
 A. I only
 B. II only
 C. III only
 D. II and III
Answer:


Question:
Let T be a depth-first search tree of a connected undirected graph G. For each vertex v of T, let pre(v) be the number of nodes visited up to and including v during a preorder traversal of T, and post(v) be the number of nodes visited up to and including v during a postorder traversal of T. The lowest common ancestor of vertices u and v in T is a vertex w of T such that w is an ancestor of both u and v, and no child of w is an ancestor of both u and v. Let (u, v) be an edge in G that is not in T, such that pre(u) < pre(v). Which of the following statements about u and v must be true?
I. post(u) < post(v)
II. u is an ancestor of v in T.
III. If w is the lowest common ancestor of u and v in T, then w = u.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let T be a depth-first search tree of a connected undirected graph G. For each vertex v of T, let pre(v) be the number of nodes visited up to and including v during a preorder traversal of T, and post(v) be the number of nodes visited up to and including v during a postorder traversal of T. The lowest common ancestor of vertices u and v in T is a vertex w of T such that w is an ancestor of both u and v, and no child of w is an ancestor of both u and v. Let (u, v) be an edge in G that is not in T, such that pre(u) < pre(v). Which of the following statements about u and v must be true?
I. post(u) < post(v)
II. u is an ancestor of v in T.
III. If w is the lowest common ancestor of u and v in T, then w = u.
 A. I only
 B. II only
 C. III only
 D. II and III
Answer: