Question:
In a height-balanced binary search tree, the heights of the left and right descendents of any node differ by at most 1. Which of the following are true of such a tree?
I. Worst-case search time is logarithmic in the number of nodes.
II. Average-case search time is logarithmic in the number of nodes.
III. Best-case search time is proportional to the height of the tree.
IV. The height of the tree is logarithmic in the number of nodes.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: In a height-balanced binary search tree, the heights of the left and right descendents of any node differ by at most 1. Which of the following are true of such a tree?
I. Worst-case search time is logarithmic in the number of nodes.
II. Average-case search time is logarithmic in the number of nodes.
III. Best-case search time is proportional to the height of the tree.
IV. The height of the tree is logarithmic in the number of nodes.
 A. I and III only
 B. II and III only
 C. II and IV only
 D. I, II, and IV
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: In a height-balanced binary search tree, the heights of the left and right descendents of any node differ by at most 1. Which of the following are true of such a tree?
I. Worst-case search time is logarithmic in the number of nodes.
II. Average-case search time is logarithmic in the number of nodes.
III. Best-case search time is proportional to the height of the tree.
IV. The height of the tree is logarithmic in the number of nodes.
 A. I and III only
 B. II and III only
 C. II and IV only
 D. I, II, and IV
Answer:


Question:
In a height-balanced binary search tree, the heights of the left and right descendents of any node differ by at most 1. Which of the following are true of such a tree?
I. Worst-case search time is logarithmic in the number of nodes.
II. Average-case search time is logarithmic in the number of nodes.
III. Best-case search time is proportional to the height of the tree.
IV. The height of the tree is logarithmic in the number of nodes.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: In a height-balanced binary search tree, the heights of the left and right descendents of any node differ by at most 1. Which of the following are true of such a tree?
I. Worst-case search time is logarithmic in the number of nodes.
II. Average-case search time is logarithmic in the number of nodes.
III. Best-case search time is proportional to the height of the tree.
IV. The height of the tree is logarithmic in the number of nodes.
 A. I and III only
 B. II and III only
 C. II and IV only
 D. I, II, and IV
Answer:


Question:
In a height-balanced binary search tree, the heights of the left and right descendents of any node differ by at most 1. Which of the following are true of such a tree?
I. Worst-case search time is logarithmic in the number of nodes.
II. Average-case search time is logarithmic in the number of nodes.
III. Best-case search time is proportional to the height of the tree.
IV. The height of the tree is logarithmic in the number of nodes.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: In a height-balanced binary search tree, the heights of the left and right descendents of any node differ by at most 1. Which of the following are true of such a tree?
I. Worst-case search time is logarithmic in the number of nodes.
II. Average-case search time is logarithmic in the number of nodes.
III. Best-case search time is proportional to the height of the tree.
IV. The height of the tree is logarithmic in the number of nodes.
 A. I and III only
 B. II and III only
 C. II and IV only
 D. I, II, and IV
Answer:


Question:
In a height-balanced binary search tree, the heights of the left and right descendents of any node differ by at most 1. Which of the following are true of such a tree?
I. Worst-case search time is logarithmic in the number of nodes.
II. Average-case search time is logarithmic in the number of nodes.
III. Best-case search time is proportional to the height of the tree.
IV. The height of the tree is logarithmic in the number of nodes.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: In a height-balanced binary search tree, the heights of the left and right descendents of any node differ by at most 1. Which of the following are true of such a tree?
I. Worst-case search time is logarithmic in the number of nodes.
II. Average-case search time is logarithmic in the number of nodes.
III. Best-case search time is proportional to the height of the tree.
IV. The height of the tree is logarithmic in the number of nodes.
 A. I and III only
 B. II and III only
 C. II and IV only
 D. I, II, and IV
Answer:


Question: Bob writes down a number between 1 and 1,000. Mary must identify that number by asking "yes/no" questions of Bob. Mary knows that Bob always tells the truth. If Mary uses an optimal strategy, then she will determine the answer at the end of exactly how many questions in the worst case?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Bob writes down a number between 1 and 1,000. Mary must identify that number by asking "yes/no" questions of Bob. Mary knows that Bob always tells the truth. If Mary uses an optimal strategy, then she will determine the answer at the end of exactly how many questions in the worst case?
 A. 1,000
 B. 999
 C. 500
 D. 10
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Bob writes down a number between 1 and 1,000. Mary must identify that number by asking "yes/no" questions of Bob. Mary knows that Bob always tells the truth. If Mary uses an optimal strategy, then she will determine the answer at the end of exactly how many questions in the worst case?
 A. 1,000
 B. 999
 C. 500
 D. 10
Answer:


Question: Bob writes down a number between 1 and 1,000. Mary must identify that number by asking "yes/no" questions of Bob. Mary knows that Bob always tells the truth. If Mary uses an optimal strategy, then she will determine the answer at the end of exactly how many questions in the worst case?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Bob writes down a number between 1 and 1,000. Mary must identify that number by asking "yes/no" questions of Bob. Mary knows that Bob always tells the truth. If Mary uses an optimal strategy, then she will determine the answer at the end of exactly how many questions in the worst case?
 A. 1,000
 B. 999
 C. 500
 D. 10
Answer:


Question: Bob writes down a number between 1 and 1,000. Mary must identify that number by asking "yes/no" questions of Bob. Mary knows that Bob always tells the truth. If Mary uses an optimal strategy, then she will determine the answer at the end of exactly how many questions in the worst case?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Bob writes down a number between 1 and 1,000. Mary must identify that number by asking "yes/no" questions of Bob. Mary knows that Bob always tells the truth. If Mary uses an optimal strategy, then she will determine the answer at the end of exactly how many questions in the worst case?
 A. 1,000
 B. 999
 C. 500
 D. 10
Answer:


Question: Bob writes down a number between 1 and 1,000. Mary must identify that number by asking "yes/no" questions of Bob. Mary knows that Bob always tells the truth. If Mary uses an optimal strategy, then she will determine the answer at the end of exactly how many questions in the worst case?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Bob writes down a number between 1 and 1,000. Mary must identify that number by asking "yes/no" questions of Bob. Mary knows that Bob always tells the truth. If Mary uses an optimal strategy, then she will determine the answer at the end of exactly how many questions in the worst case?
 A. 1,000
 B. 999
 C. 500
 D. 10
Answer:


Question:
Which of the following is (are) true about virtual memory systems that use pages?
I. The virtual address space can be larger than the amount of physical memory.
II. Programs must be resident in main memory throughout their execution.
III. Pages correspond to semantic characteristics of the program.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following is (are) true about virtual memory systems that use pages?
I. The virtual address space can be larger than the amount of physical memory.
II. Programs must be resident in main memory throughout their execution.
III. Pages correspond to semantic characteristics of the program.
 A. I only
 B. II only
 C. I and II
 D. I and III
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Which of the following is (are) true about virtual memory systems that use pages?
I. The virtual address space can be larger than the amount of physical memory.
II. Programs must be resident in main memory throughout their execution.
III. Pages correspond to semantic characteristics of the program.
 A. I only
 B. II only
 C. I and II
 D. I and III
Answer:


Question:
Which of the following is (are) true about virtual memory systems that use pages?
I. The virtual address space can be larger than the amount of physical memory.
II. Programs must be resident in main memory throughout their execution.
III. Pages correspond to semantic characteristics of the program.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following is (are) true about virtual memory systems that use pages?
I. The virtual address space can be larger than the amount of physical memory.
II. Programs must be resident in main memory throughout their execution.
III. Pages correspond to semantic characteristics of the program.
 A. I only
 B. II only
 C. I and II
 D. I and III
Answer:


Question:
Which of the following is (are) true about virtual memory systems that use pages?
I. The virtual address space can be larger than the amount of physical memory.
II. Programs must be resident in main memory throughout their execution.
III. Pages correspond to semantic characteristics of the program.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following is (are) true about virtual memory systems that use pages?
I. The virtual address space can be larger than the amount of physical memory.
II. Programs must be resident in main memory throughout their execution.
III. Pages correspond to semantic characteristics of the program.
 A. I only
 B. II only
 C. I and II
 D. I and III
Answer:


Question:
Which of the following is (are) true about virtual memory systems that use pages?
I. The virtual address space can be larger than the amount of physical memory.
II. Programs must be resident in main memory throughout their execution.
III. Pages correspond to semantic characteristics of the program.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following is (are) true about virtual memory systems that use pages?
I. The virtual address space can be larger than the amount of physical memory.
II. Programs must be resident in main memory throughout their execution.
III. Pages correspond to semantic characteristics of the program.
 A. I only
 B. II only
 C. I and II
 D. I and III
Answer:


Question: Which of the following is usually NOT represented in a subroutine's activation record frame for a stack-based programming language?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following is usually NOT represented in a subroutine's activation record frame for a stack-based programming language?
 A. Values of local variables
 B. A heap area
 C. The return address
 D. Stack pointer for the calling activation record
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Which of the following is usually NOT represented in a subroutine's activation record frame for a stack-based programming language?
 A. Values of local variables
 B. A heap area
 C. The return address
 D. Stack pointer for the calling activation record
Answer:


Question: Which of the following is usually NOT represented in a subroutine's activation record frame for a stack-based programming language?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following is usually NOT represented in a subroutine's activation record frame for a stack-based programming language?
 A. Values of local variables
 B. A heap area
 C. The return address
 D. Stack pointer for the calling activation record
Answer:


Question: Which of the following is usually NOT represented in a subroutine's activation record frame for a stack-based programming language?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following is usually NOT represented in a subroutine's activation record frame for a stack-based programming language?
 A. Values of local variables
 B. A heap area
 C. The return address
 D. Stack pointer for the calling activation record
Answer:


Question: Which of the following is usually NOT represented in a subroutine's activation record frame for a stack-based programming language?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following is usually NOT represented in a subroutine's activation record frame for a stack-based programming language?
 A. Values of local variables
 B. A heap area
 C. The return address
 D. Stack pointer for the calling activation record
Answer:


Question: Which of the following statements about a remote procedure call is true?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following statements about a remote procedure call is true?
 A. It is used to call procedures with addresses that are farther than 2^16 bytes away.
 B. It cannot return a value.
 C. It cannot pass parameters by reference.
 D. It cannot call procedures implemented in a different language.
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Which of the following statements about a remote procedure call is true?
 A. It is used to call procedures with addresses that are farther than 2^16 bytes away.
 B. It cannot return a value.
 C. It cannot pass parameters by reference.
 D. It cannot call procedures implemented in a different language.
Answer:


Question: Which of the following statements about a remote procedure call is true?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following statements about a remote procedure call is true?
 A. It is used to call procedures with addresses that are farther than 2^16 bytes away.
 B. It cannot return a value.
 C. It cannot pass parameters by reference.
 D. It cannot call procedures implemented in a different language.
Answer:


Question: Which of the following statements about a remote procedure call is true?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following statements about a remote procedure call is true?
 A. It is used to call procedures with addresses that are farther than 2^16 bytes away.
 B. It cannot return a value.
 C. It cannot pass parameters by reference.
 D. It cannot call procedures implemented in a different language.
Answer:


Question: Which of the following statements about a remote procedure call is true?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following statements about a remote procedure call is true?
 A. It is used to call procedures with addresses that are farther than 2^16 bytes away.
 B. It cannot return a value.
 C. It cannot pass parameters by reference.
 D. It cannot call procedures implemented in a different language.
Answer:


Question: Of the following sorting algorithms, which has a running time that is LEAST dependent on the initial ordering of the input?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Of the following sorting algorithms, which has a running time that is LEAST dependent on the initial ordering of the input?
 A. Insertion sort
 B. Quicksort
 C. Merge sort
 D. Selection sort
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Of the following sorting algorithms, which has a running time that is LEAST dependent on the initial ordering of the input?
 A. Insertion sort
 B. Quicksort
 C. Merge sort
 D. Selection sort
Answer:


Question: Of the following sorting algorithms, which has a running time that is LEAST dependent on the initial ordering of the input?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Of the following sorting algorithms, which has a running time that is LEAST dependent on the initial ordering of the input?
 A. Insertion sort
 B. Quicksort
 C. Merge sort
 D. Selection sort
Answer:


Question: Of the following sorting algorithms, which has a running time that is LEAST dependent on the initial ordering of the input?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Of the following sorting algorithms, which has a running time that is LEAST dependent on the initial ordering of the input?
 A. Insertion sort
 B. Quicksort
 C. Merge sort
 D. Selection sort
Answer:


Question: Of the following sorting algorithms, which has a running time that is LEAST dependent on the initial ordering of the input?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Of the following sorting algorithms, which has a running time that is LEAST dependent on the initial ordering of the input?
 A. Insertion sort
 B. Quicksort
 C. Merge sort
 D. Selection sort
Answer:


Question: A particular parallel program computation requires 100 seconds when executed on a single processor. If 40 percent of this computation is "inherently sequential" (i.e., will not benefit from additional processors), then the theoretically best possible elapsed times for this program running with 2 and 4 processors, respectively, are

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: A particular parallel program computation requires 100 seconds when executed on a single processor. If 40 percent of this computation is "inherently sequential" (i.e., will not benefit from additional processors), then the theoretically best possible elapsed times for this program running with 2 and 4 processors, respectively, are
 A. 20 and 10 seconds
 B. 30 and 15 seconds
 C. 50 and 25 seconds
 D. 70 and 55 seconds
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: A particular parallel program computation requires 100 seconds when executed on a single processor. If 40 percent of this computation is "inherently sequential" (i.e., will not benefit from additional processors), then the theoretically best possible elapsed times for this program running with 2 and 4 processors, respectively, are
 A. 20 and 10 seconds
 B. 30 and 15 seconds
 C. 50 and 25 seconds
 D. 70 and 55 seconds
Answer:


Question: A particular parallel program computation requires 100 seconds when executed on a single processor. If 40 percent of this computation is "inherently sequential" (i.e., will not benefit from additional processors), then the theoretically best possible elapsed times for this program running with 2 and 4 processors, respectively, are

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: A particular parallel program computation requires 100 seconds when executed on a single processor. If 40 percent of this computation is "inherently sequential" (i.e., will not benefit from additional processors), then the theoretically best possible elapsed times for this program running with 2 and 4 processors, respectively, are
 A. 20 and 10 seconds
 B. 30 and 15 seconds
 C. 50 and 25 seconds
 D. 70 and 55 seconds
Answer:


Question: A particular parallel program computation requires 100 seconds when executed on a single processor. If 40 percent of this computation is "inherently sequential" (i.e., will not benefit from additional processors), then the theoretically best possible elapsed times for this program running with 2 and 4 processors, respectively, are

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: A particular parallel program computation requires 100 seconds when executed on a single processor. If 40 percent of this computation is "inherently sequential" (i.e., will not benefit from additional processors), then the theoretically best possible elapsed times for this program running with 2 and 4 processors, respectively, are
 A. 20 and 10 seconds
 B. 30 and 15 seconds
 C. 50 and 25 seconds
 D. 70 and 55 seconds
Answer:


Question: A particular parallel program computation requires 100 seconds when executed on a single processor. If 40 percent of this computation is "inherently sequential" (i.e., will not benefit from additional processors), then the theoretically best possible elapsed times for this program running with 2 and 4 processors, respectively, are

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: A particular parallel program computation requires 100 seconds when executed on a single processor. If 40 percent of this computation is "inherently sequential" (i.e., will not benefit from additional processors), then the theoretically best possible elapsed times for this program running with 2 and 4 processors, respectively, are
 A. 20 and 10 seconds
 B. 30 and 15 seconds
 C. 50 and 25 seconds
 D. 70 and 55 seconds
Answer:


Question: Consider the representation of six-bit numbers by two's complement, one's complement, or by sign and magnitude. In which representation is there overflow from the addition of the integers 011000 and 011000?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Consider the representation of six-bit numbers by two's complement, one's complement, or by sign and magnitude. In which representation is there overflow from the addition of the integers 011000 and 011000?
 A. Two's complement only
 B. Sign and magnitude and one's complement only
 C. Two's complement and one's complement only
 D. All three representations
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Consider the representation of six-bit numbers by two's complement, one's complement, or by sign and magnitude. In which representation is there overflow from the addition of the integers 011000 and 011000?
 A. Two's complement only
 B. Sign and magnitude and one's complement only
 C. Two's complement and one's complement only
 D. All three representations
Answer:


Question: Consider the representation of six-bit numbers by two's complement, one's complement, or by sign and magnitude. In which representation is there overflow from the addition of the integers 011000 and 011000?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Consider the representation of six-bit numbers by two's complement, one's complement, or by sign and magnitude. In which representation is there overflow from the addition of the integers 011000 and 011000?
 A. Two's complement only
 B. Sign and magnitude and one's complement only
 C. Two's complement and one's complement only
 D. All three representations
Answer:


Question: Consider the representation of six-bit numbers by two's complement, one's complement, or by sign and magnitude. In which representation is there overflow from the addition of the integers 011000 and 011000?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Consider the representation of six-bit numbers by two's complement, one's complement, or by sign and magnitude. In which representation is there overflow from the addition of the integers 011000 and 011000?
 A. Two's complement only
 B. Sign and magnitude and one's complement only
 C. Two's complement and one's complement only
 D. All three representations
Answer:


Question: Consider the representation of six-bit numbers by two's complement, one's complement, or by sign and magnitude. In which representation is there overflow from the addition of the integers 011000 and 011000?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Consider the representation of six-bit numbers by two's complement, one's complement, or by sign and magnitude. In which representation is there overflow from the addition of the integers 011000 and 011000?
 A. Two's complement only
 B. Sign and magnitude and one's complement only
 C. Two's complement and one's complement only
 D. All three representations
Answer:


Question: Of the following, which best characterizes computers that use memory-mapped I/O?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Of the following, which best characterizes computers that use memory-mapped I/O?
 A. The computer provides special instructions for manipulating I/O ports.
 B. I/O ports are placed at addresses on the bus and are accessed just like other memory locations.
 C. To perform an I/O operation, it is sufficient to place the data in an address register and call the channel to perform the operation.
 D. Ports are referenced only by memory-mapped instructions of the computer and are located at hardwired memory locations.
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Of the following, which best characterizes computers that use memory-mapped I/O?
 A. The computer provides special instructions for manipulating I/O ports.
 B. I/O ports are placed at addresses on the bus and are accessed just like other memory locations.
 C. To perform an I/O operation, it is sufficient to place the data in an address register and call the channel to perform the operation.
 D. Ports are referenced only by memory-mapped instructions of the computer and are located at hardwired memory locations.
Answer:


Question: Of the following, which best characterizes computers that use memory-mapped I/O?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Of the following, which best characterizes computers that use memory-mapped I/O?
 A. The computer provides special instructions for manipulating I/O ports.
 B. I/O ports are placed at addresses on the bus and are accessed just like other memory locations.
 C. To perform an I/O operation, it is sufficient to place the data in an address register and call the channel to perform the operation.
 D. Ports are referenced only by memory-mapped instructions of the computer and are located at hardwired memory locations.
Answer:


Question: Of the following, which best characterizes computers that use memory-mapped I/O?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Of the following, which best characterizes computers that use memory-mapped I/O?
 A. The computer provides special instructions for manipulating I/O ports.
 B. I/O ports are placed at addresses on the bus and are accessed just like other memory locations.
 C. To perform an I/O operation, it is sufficient to place the data in an address register and call the channel to perform the operation.
 D. Ports are referenced only by memory-mapped instructions of the computer and are located at hardwired memory locations.
Answer:


Question: Of the following, which best characterizes computers that use memory-mapped I/O?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Of the following, which best characterizes computers that use memory-mapped I/O?
 A. The computer provides special instructions for manipulating I/O ports.
 B. I/O ports are placed at addresses on the bus and are accessed just like other memory locations.
 C. To perform an I/O operation, it is sufficient to place the data in an address register and call the channel to perform the operation.
 D. Ports are referenced only by memory-mapped instructions of the computer and are located at hardwired memory locations.
Answer:


Question: Many cryptographic protocols base their security on assumptions about the computational difficulty of integer factorization. Integer factorization serves this purpose because we believe that

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Many cryptographic protocols base their security on assumptions about the computational difficulty of integer factorization. Integer factorization serves this purpose because we believe that
 A. integer multiplication is a function whose inverse, factorization, remains difficult for a large class of inputs
 B. P = NP
 C. even if P = NP, integer factorization is still likely not to be polynomial-time computable
 D. testing primality is computationally intractable
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Many cryptographic protocols base their security on assumptions about the computational difficulty of integer factorization. Integer factorization serves this purpose because we believe that
 A. integer multiplication is a function whose inverse, factorization, remains difficult for a large class of inputs
 B. P = NP
 C. even if P = NP, integer factorization is still likely not to be polynomial-time computable
 D. testing primality is computationally intractable
Answer:


Question: Many cryptographic protocols base their security on assumptions about the computational difficulty of integer factorization. Integer factorization serves this purpose because we believe that

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Many cryptographic protocols base their security on assumptions about the computational difficulty of integer factorization. Integer factorization serves this purpose because we believe that
 A. integer multiplication is a function whose inverse, factorization, remains difficult for a large class of inputs
 B. P = NP
 C. even if P = NP, integer factorization is still likely not to be polynomial-time computable
 D. testing primality is computationally intractable
Answer:


Question: Many cryptographic protocols base their security on assumptions about the computational difficulty of integer factorization. Integer factorization serves this purpose because we believe that

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Many cryptographic protocols base their security on assumptions about the computational difficulty of integer factorization. Integer factorization serves this purpose because we believe that
 A. integer multiplication is a function whose inverse, factorization, remains difficult for a large class of inputs
 B. P = NP
 C. even if P = NP, integer factorization is still likely not to be polynomial-time computable
 D. testing primality is computationally intractable
Answer:


Question: Many cryptographic protocols base their security on assumptions about the computational difficulty of integer factorization. Integer factorization serves this purpose because we believe that

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Many cryptographic protocols base their security on assumptions about the computational difficulty of integer factorization. Integer factorization serves this purpose because we believe that
 A. integer multiplication is a function whose inverse, factorization, remains difficult for a large class of inputs
 B. P = NP
 C. even if P = NP, integer factorization is still likely not to be polynomial-time computable
 D. testing primality is computationally intractable
Answer:


Question: Which of the following sets of bit strings CANNOT be described with a regular expression?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following sets of bit strings CANNOT be described with a regular expression?
 A. All bit strings whose number of zeros is a multiple of five
 B. All bit strings starting with a zero and ending with a one
 C. All bit strings with an even number of zeros
 D. All bit strings with more ones than zeros
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Which of the following sets of bit strings CANNOT be described with a regular expression?
 A. All bit strings whose number of zeros is a multiple of five
 B. All bit strings starting with a zero and ending with a one
 C. All bit strings with an even number of zeros
 D. All bit strings with more ones than zeros
Answer:


Question: Which of the following sets of bit strings CANNOT be described with a regular expression?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following sets of bit strings CANNOT be described with a regular expression?
 A. All bit strings whose number of zeros is a multiple of five
 B. All bit strings starting with a zero and ending with a one
 C. All bit strings with an even number of zeros
 D. All bit strings with more ones than zeros
Answer:


Question: Which of the following sets of bit strings CANNOT be described with a regular expression?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following sets of bit strings CANNOT be described with a regular expression?
 A. All bit strings whose number of zeros is a multiple of five
 B. All bit strings starting with a zero and ending with a one
 C. All bit strings with an even number of zeros
 D. All bit strings with more ones than zeros
Answer:


Question: Which of the following sets of bit strings CANNOT be described with a regular expression?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following sets of bit strings CANNOT be described with a regular expression?
 A. All bit strings whose number of zeros is a multiple of five
 B. All bit strings starting with a zero and ending with a one
 C. All bit strings with an even number of zeros
 D. All bit strings with more ones than zeros
Answer:


Question:
Which of the following conditions can be expressed by a Boolean formula in the Boolean variables p_1, p_2, p_3, p_4 and the connectives ∧,∨ (without ¬)?
I. At least three of p_1, p_2, p_3, p_4 are true.
II. Exactly three of p_1, p_2, p_3, p_4 are true.
III. An even number of p_1, p_2, p_3, p_4 are true.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following conditions can be expressed by a Boolean formula in the Boolean variables p_1, p_2, p_3, p_4 and the connectives ∧,∨ (without ¬)?
I. At least three of p_1, p_2, p_3, p_4 are true.
II. Exactly three of p_1, p_2, p_3, p_4 are true.
III. An even number of p_1, p_2, p_3, p_4 are true.
 A. I only
 B. II only
 C. III only
 D. I and III
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Which of the following conditions can be expressed by a Boolean formula in the Boolean variables p_1, p_2, p_3, p_4 and the connectives ∧,∨ (without ¬)?
I. At least three of p_1, p_2, p_3, p_4 are true.
II. Exactly three of p_1, p_2, p_3, p_4 are true.
III. An even number of p_1, p_2, p_3, p_4 are true.
 A. I only
 B. II only
 C. III only
 D. I and III
Answer:


Question:
Which of the following conditions can be expressed by a Boolean formula in the Boolean variables p_1, p_2, p_3, p_4 and the connectives ∧,∨ (without ¬)?
I. At least three of p_1, p_2, p_3, p_4 are true.
II. Exactly three of p_1, p_2, p_3, p_4 are true.
III. An even number of p_1, p_2, p_3, p_4 are true.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following conditions can be expressed by a Boolean formula in the Boolean variables p_1, p_2, p_3, p_4 and the connectives ∧,∨ (without ¬)?
I. At least three of p_1, p_2, p_3, p_4 are true.
II. Exactly three of p_1, p_2, p_3, p_4 are true.
III. An even number of p_1, p_2, p_3, p_4 are true.
 A. I only
 B. II only
 C. III only
 D. I and III
Answer:


Question:
Which of the following conditions can be expressed by a Boolean formula in the Boolean variables p_1, p_2, p_3, p_4 and the connectives ∧,∨ (without ¬)?
I. At least three of p_1, p_2, p_3, p_4 are true.
II. Exactly three of p_1, p_2, p_3, p_4 are true.
III. An even number of p_1, p_2, p_3, p_4 are true.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following conditions can be expressed by a Boolean formula in the Boolean variables p_1, p_2, p_3, p_4 and the connectives ∧,∨ (without ¬)?
I. At least three of p_1, p_2, p_3, p_4 are true.
II. Exactly three of p_1, p_2, p_3, p_4 are true.
III. An even number of p_1, p_2, p_3, p_4 are true.
 A. I only
 B. II only
 C. III only
 D. I and III
Answer:


Question:
Which of the following conditions can be expressed by a Boolean formula in the Boolean variables p_1, p_2, p_3, p_4 and the connectives ∧,∨ (without ¬)?
I. At least three of p_1, p_2, p_3, p_4 are true.
II. Exactly three of p_1, p_2, p_3, p_4 are true.
III. An even number of p_1, p_2, p_3, p_4 are true.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following conditions can be expressed by a Boolean formula in the Boolean variables p_1, p_2, p_3, p_4 and the connectives ∧,∨ (without ¬)?
I. At least three of p_1, p_2, p_3, p_4 are true.
II. Exactly three of p_1, p_2, p_3, p_4 are true.
III. An even number of p_1, p_2, p_3, p_4 are true.
 A. I only
 B. II only
 C. III only
 D. I and III
Answer:


Question: Two alternatives for interconnecting a set of processors with bidirectional links are (1) the fully interconnected network, in which each processor is directly connected to every other processor, and (2) the ring network, in which each processor is connected to two other processors. The worst-case path length for a network is the maximum, over all pairs of nodes in the network, of the minimum length paths (measured in number of links) between the nodes. For each type of interconnection of n processors, a figure of merit can be formed as the product of the number of links required for the network times the worst-case path length connecting any two processors. The ratio of this figure of merit for the fully interconnected network compared to that of the ring network, for even n > 2, is

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Two alternatives for interconnecting a set of processors with bidirectional links are (1) the fully interconnected network, in which each processor is directly connected to every other processor, and (2) the ring network, in which each processor is connected to two other processors. The worst-case path length for a network is the maximum, over all pairs of nodes in the network, of the minimum length paths (measured in number of links) between the nodes. For each type of interconnection of n processors, a figure of merit can be formed as the product of the number of links required for the network times the worst-case path length connecting any two processors. The ratio of this figure of merit for the fully interconnected network compared to that of the ring network, for even n > 2, is
 A. 1/(n^2)
 B. 1/(n(n-1))
 C. 1/n
 D. (n-1)/n
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Two alternatives for interconnecting a set of processors with bidirectional links are (1) the fully interconnected network, in which each processor is directly connected to every other processor, and (2) the ring network, in which each processor is connected to two other processors. The worst-case path length for a network is the maximum, over all pairs of nodes in the network, of the minimum length paths (measured in number of links) between the nodes. For each type of interconnection of n processors, a figure of merit can be formed as the product of the number of links required for the network times the worst-case path length connecting any two processors. The ratio of this figure of merit for the fully interconnected network compared to that of the ring network, for even n > 2, is
 A. 1/(n^2)
 B. 1/(n(n-1))
 C. 1/n
 D. (n-1)/n
Answer:


Question: Two alternatives for interconnecting a set of processors with bidirectional links are (1) the fully interconnected network, in which each processor is directly connected to every other processor, and (2) the ring network, in which each processor is connected to two other processors. The worst-case path length for a network is the maximum, over all pairs of nodes in the network, of the minimum length paths (measured in number of links) between the nodes. For each type of interconnection of n processors, a figure of merit can be formed as the product of the number of links required for the network times the worst-case path length connecting any two processors. The ratio of this figure of merit for the fully interconnected network compared to that of the ring network, for even n > 2, is

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Two alternatives for interconnecting a set of processors with bidirectional links are (1) the fully interconnected network, in which each processor is directly connected to every other processor, and (2) the ring network, in which each processor is connected to two other processors. The worst-case path length for a network is the maximum, over all pairs of nodes in the network, of the minimum length paths (measured in number of links) between the nodes. For each type of interconnection of n processors, a figure of merit can be formed as the product of the number of links required for the network times the worst-case path length connecting any two processors. The ratio of this figure of merit for the fully interconnected network compared to that of the ring network, for even n > 2, is
 A. 1/(n^2)
 B. 1/(n(n-1))
 C. 1/n
 D. (n-1)/n
Answer:


Question: Two alternatives for interconnecting a set of processors with bidirectional links are (1) the fully interconnected network, in which each processor is directly connected to every other processor, and (2) the ring network, in which each processor is connected to two other processors. The worst-case path length for a network is the maximum, over all pairs of nodes in the network, of the minimum length paths (measured in number of links) between the nodes. For each type of interconnection of n processors, a figure of merit can be formed as the product of the number of links required for the network times the worst-case path length connecting any two processors. The ratio of this figure of merit for the fully interconnected network compared to that of the ring network, for even n > 2, is

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Two alternatives for interconnecting a set of processors with bidirectional links are (1) the fully interconnected network, in which each processor is directly connected to every other processor, and (2) the ring network, in which each processor is connected to two other processors. The worst-case path length for a network is the maximum, over all pairs of nodes in the network, of the minimum length paths (measured in number of links) between the nodes. For each type of interconnection of n processors, a figure of merit can be formed as the product of the number of links required for the network times the worst-case path length connecting any two processors. The ratio of this figure of merit for the fully interconnected network compared to that of the ring network, for even n > 2, is
 A. 1/(n^2)
 B. 1/(n(n-1))
 C. 1/n
 D. (n-1)/n
Answer:


Question: Two alternatives for interconnecting a set of processors with bidirectional links are (1) the fully interconnected network, in which each processor is directly connected to every other processor, and (2) the ring network, in which each processor is connected to two other processors. The worst-case path length for a network is the maximum, over all pairs of nodes in the network, of the minimum length paths (measured in number of links) between the nodes. For each type of interconnection of n processors, a figure of merit can be formed as the product of the number of links required for the network times the worst-case path length connecting any two processors. The ratio of this figure of merit for the fully interconnected network compared to that of the ring network, for even n > 2, is

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Two alternatives for interconnecting a set of processors with bidirectional links are (1) the fully interconnected network, in which each processor is directly connected to every other processor, and (2) the ring network, in which each processor is connected to two other processors. The worst-case path length for a network is the maximum, over all pairs of nodes in the network, of the minimum length paths (measured in number of links) between the nodes. For each type of interconnection of n processors, a figure of merit can be formed as the product of the number of links required for the network times the worst-case path length connecting any two processors. The ratio of this figure of merit for the fully interconnected network compared to that of the ring network, for even n > 2, is
 A. 1/(n^2)
 B. 1/(n(n-1))
 C. 1/n
 D. (n-1)/n
Answer:


Question:
For a connected, undirected graph G = (V, E), which of the following must be true?
I. Σ_{v∈V} degree(v) is even.
II. |E| ≥ |V| − 1
III. G has at least one vertex with degree 1.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: For a connected, undirected graph G = (V, E), which of the following must be true?
I. Σ_{v∈V} degree(v) is even.
II. |E| ≥ |V| − 1
III. G has at least one vertex with degree 1.
 A. I only
 B. II only
 C. III only
 D. I and II
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: For a connected, undirected graph G = (V, E), which of the following must be true?
I. Σ_{v∈V} degree(v) is even.
II. |E| ≥ |V| − 1
III. G has at least one vertex with degree 1.
 A. I only
 B. II only
 C. III only
 D. I and II
Answer:


Question:
For a connected, undirected graph G = (V, E), which of the following must be true?
I. Σ_{v∈V} degree(v) is even.
II. |E| ≥ |V| − 1
III. G has at least one vertex with degree 1.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: For a connected, undirected graph G = (V, E), which of the following must be true?
I. Σ_{v∈V} degree(v) is even.
II. |E| ≥ |V| − 1
III. G has at least one vertex with degree 1.
 A. I only
 B. II only
 C. III only
 D. I and II
Answer:


Question:
For a connected, undirected graph G = (V, E), which of the following must be true?
I. Σ_{v∈V} degree(v) is even.
II. |E| ≥ |V| − 1
III. G has at least one vertex with degree 1.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: For a connected, undirected graph G = (V, E), which of the following must be true?
I. Σ_{v∈V} degree(v) is even.
II. |E| ≥ |V| − 1
III. G has at least one vertex with degree 1.
 A. I only
 B. II only
 C. III only
 D. I and II
Answer:


Question:
For a connected, undirected graph G = (V, E), which of the following must be true?
I. Σ_{v∈V} degree(v) is even.
II. |E| ≥ |V| − 1
III. G has at least one vertex with degree 1.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: For a connected, undirected graph G = (V, E), which of the following must be true?
I. Σ_{v∈V} degree(v) is even.
II. |E| ≥ |V| − 1
III. G has at least one vertex with degree 1.
 A. I only
 B. II only
 C. III only
 D. I and II
Answer:


Question:
In multiprogrammed systems it is advantageous if some programs such as editors and compilers can be shared by several users. Which of the following must be true of multiprogrammed systems in order that a single copy of a program can be shared by several users?
I. The program is a macro.
II. The program is recursive.
III. The program is reentrant.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: In multiprogrammed systems it is advantageous if some programs such as editors and compilers can be shared by several users. Which of the following must be true of multiprogrammed systems in order that a single copy of a program can be shared by several users?
I. The program is a macro.
II. The program is recursive.
III. The program is reentrant.
 A. I only
 B. II only
 C. III only
 D. II and III only
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: In multiprogrammed systems it is advantageous if some programs such as editors and compilers can be shared by several users. Which of the following must be true of multiprogrammed systems in order that a single copy of a program can be shared by several users?
I. The program is a macro.
II. The program is recursive.
III. The program is reentrant.
 A. I only
 B. II only
 C. III only
 D. II and III only
Answer:


Question:
In multiprogrammed systems it is advantageous if some programs such as editors and compilers can be shared by several users. Which of the following must be true of multiprogrammed systems in order that a single copy of a program can be shared by several users?
I. The program is a macro.
II. The program is recursive.
III. The program is reentrant.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: In multiprogrammed systems it is advantageous if some programs such as editors and compilers can be shared by several users. Which of the following must be true of multiprogrammed systems in order that a single copy of a program can be shared by several users?
I. The program is a macro.
II. The program is recursive.
III. The program is reentrant.
 A. I only
 B. II only
 C. III only
 D. II and III only
Answer:


Question:
In multiprogrammed systems it is advantageous if some programs such as editors and compilers can be shared by several users. Which of the following must be true of multiprogrammed systems in order that a single copy of a program can be shared by several users?
I. The program is a macro.
II. The program is recursive.
III. The program is reentrant.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: In multiprogrammed systems it is advantageous if some programs such as editors and compilers can be shared by several users. Which of the following must be true of multiprogrammed systems in order that a single copy of a program can be shared by several users?
I. The program is a macro.
II. The program is recursive.
III. The program is reentrant.
 A. I only
 B. II only
 C. III only
 D. II and III only
Answer:


Question:
In multiprogrammed systems it is advantageous if some programs such as editors and compilers can be shared by several users. Which of the following must be true of multiprogrammed systems in order that a single copy of a program can be shared by several users?
I. The program is a macro.
II. The program is recursive.
III. The program is reentrant.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: In multiprogrammed systems it is advantageous if some programs such as editors and compilers can be shared by several users. Which of the following must be true of multiprogrammed systems in order that a single copy of a program can be shared by several users?
I. The program is a macro.
II. The program is recursive.
III. The program is reentrant.
 A. I only
 B. II only
 C. III only
 D. II and III only
Answer:


Question: Which of the following decimal numbers has an exact representation in binary notation?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following decimal numbers has an exact representation in binary notation?
 A. 0.1
 B. 0.2
 C. 0.3
 D. 0.5
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Which of the following decimal numbers has an exact representation in binary notation?
 A. 0.1
 B. 0.2
 C. 0.3
 D. 0.5
Answer:


Question: Which of the following decimal numbers has an exact representation in binary notation?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following decimal numbers has an exact representation in binary notation?
 A. 0.1
 B. 0.2
 C. 0.3
 D. 0.5
Answer:


Question: Which of the following decimal numbers has an exact representation in binary notation?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following decimal numbers has an exact representation in binary notation?
 A. 0.1
 B. 0.2
 C. 0.3
 D. 0.5
Answer:


Question: Which of the following decimal numbers has an exact representation in binary notation?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following decimal numbers has an exact representation in binary notation?
 A. 0.1
 B. 0.2
 C. 0.3
 D. 0.5
Answer: