Question:
Array A contains 256 elements of 4 bytes each. Its first element is stored at physical address 4,096.
Array B contains 512 elements of 4 bytes each. Its first element is stored at physical address 8,192.
Assume that only arrays A and B can be cached in an initially empty, physically addressed, physically tagged, direct-mapped, 2K-byte cache with an 8-byte block size. The following loop is then executed.
for (i = 0; i < 256; i++)
        A[i] = A[i] + B[2*i];
During the execution of the loop, how many bytes will be written to memory if the cache has a write-through policy?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Array A contains 256 elements of 4 bytes each. Its first element is stored at physical address 4,096.
Array B contains 512 elements of 4 bytes each. Its first element is stored at physical address 8,192.
Assume that only arrays A and B can be cached in an initially empty, physically addressed, physically tagged, direct-mapped, 2K-byte cache with an 8-byte block size. The following loop is then executed.
for (i = 0; i < 256; i++)
        A[i] = A[i] + B[2*i];
During the execution of the loop, how many bytes will be written to memory if the cache has a write-through policy?
 A. 0
 B. 256
 C. 1024
 D. 2048
Answer:


Question: At time 0, five jobs are available for execution on a single processor, with service times of 25, 15, 5, 3, and 2 time units. Which of the following is the minimum value of the average completion time of these jobs?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: At time 0, five jobs are available for execution on a single processor, with service times of 25, 15, 5, 3, and 2 time units. Which of the following is the minimum value of the average completion time of these jobs?
 A. 50
 B. 208/5
 C. 92/5
 D. 10
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: At time 0, five jobs are available for execution on a single processor, with service times of 25, 15, 5, 3, and 2 time units. Which of the following is the minimum value of the average completion time of these jobs?
 A. 50
 B. 208/5
 C. 92/5
 D. 10
Answer:


Question: At time 0, five jobs are available for execution on a single processor, with service times of 25, 15, 5, 3, and 2 time units. Which of the following is the minimum value of the average completion time of these jobs?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: At time 0, five jobs are available for execution on a single processor, with service times of 25, 15, 5, 3, and 2 time units. Which of the following is the minimum value of the average completion time of these jobs?
 A. 50
 B. 208/5
 C. 92/5
 D. 10
Answer:


Question: At time 0, five jobs are available for execution on a single processor, with service times of 25, 15, 5, 3, and 2 time units. Which of the following is the minimum value of the average completion time of these jobs?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: At time 0, five jobs are available for execution on a single processor, with service times of 25, 15, 5, 3, and 2 time units. Which of the following is the minimum value of the average completion time of these jobs?
 A. 50
 B. 208/5
 C. 92/5
 D. 10
Answer:


Question: At time 0, five jobs are available for execution on a single processor, with service times of 25, 15, 5, 3, and 2 time units. Which of the following is the minimum value of the average completion time of these jobs?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: At time 0, five jobs are available for execution on a single processor, with service times of 25, 15, 5, 3, and 2 time units. Which of the following is the minimum value of the average completion time of these jobs?
 A. 50
 B. 208/5
 C. 92/5
 D. 10
Answer:


Question: Let G = (V, E) be a connected, undirected graph, and let a and b be two distinct vertices in V. Let P_1 be the problem of finding a shortest simple path between a and b, and let P_2 be the problem of finding a longest simple path between a and b. Which of the following statements about P_1 and P_2 is true?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let G = (V, E) be a connected, undirected graph, and let a and b be two distinct vertices in V. Let P_1 be the problem of finding a shortest simple path between a and b, and let P_2 be the problem of finding a longest simple path between a and b. Which of the following statements about P_1 and P_2 is true?
 A. Both P_1 and P_2 can be solved in polynomial time.
 B. P_1 can be solved in polynomial time but P_2 is not known to be solvable in polynomial time.
 C. P_1 is not known to be solvable in polynomial time but P_2 can be solved in polynomial time.
 D. It is not known whether either P_1 or P_2 can be solved in polynomial time.
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Let G = (V, E) be a connected, undirected graph, and let a and b be two distinct vertices in V. Let P_1 be the problem of finding a shortest simple path between a and b, and let P_2 be the problem of finding a longest simple path between a and b. Which of the following statements about P_1 and P_2 is true?
 A. Both P_1 and P_2 can be solved in polynomial time.
 B. P_1 can be solved in polynomial time but P_2 is not known to be solvable in polynomial time.
 C. P_1 is not known to be solvable in polynomial time but P_2 can be solved in polynomial time.
 D. It is not known whether either P_1 or P_2 can be solved in polynomial time.
Answer:


Question: Let G = (V, E) be a connected, undirected graph, and let a and b be two distinct vertices in V. Let P_1 be the problem of finding a shortest simple path between a and b, and let P_2 be the problem of finding a longest simple path between a and b. Which of the following statements about P_1 and P_2 is true?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let G = (V, E) be a connected, undirected graph, and let a and b be two distinct vertices in V. Let P_1 be the problem of finding a shortest simple path between a and b, and let P_2 be the problem of finding a longest simple path between a and b. Which of the following statements about P_1 and P_2 is true?
 A. Both P_1 and P_2 can be solved in polynomial time.
 B. P_1 can be solved in polynomial time but P_2 is not known to be solvable in polynomial time.
 C. P_1 is not known to be solvable in polynomial time but P_2 can be solved in polynomial time.
 D. It is not known whether either P_1 or P_2 can be solved in polynomial time.
Answer:


Question: Let G = (V, E) be a connected, undirected graph, and let a and b be two distinct vertices in V. Let P_1 be the problem of finding a shortest simple path between a and b, and let P_2 be the problem of finding a longest simple path between a and b. Which of the following statements about P_1 and P_2 is true?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let G = (V, E) be a connected, undirected graph, and let a and b be two distinct vertices in V. Let P_1 be the problem of finding a shortest simple path between a and b, and let P_2 be the problem of finding a longest simple path between a and b. Which of the following statements about P_1 and P_2 is true?
 A. Both P_1 and P_2 can be solved in polynomial time.
 B. P_1 can be solved in polynomial time but P_2 is not known to be solvable in polynomial time.
 C. P_1 is not known to be solvable in polynomial time but P_2 can be solved in polynomial time.
 D. It is not known whether either P_1 or P_2 can be solved in polynomial time.
Answer:


Question: Let G = (V, E) be a connected, undirected graph, and let a and b be two distinct vertices in V. Let P_1 be the problem of finding a shortest simple path between a and b, and let P_2 be the problem of finding a longest simple path between a and b. Which of the following statements about P_1 and P_2 is true?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let G = (V, E) be a connected, undirected graph, and let a and b be two distinct vertices in V. Let P_1 be the problem of finding a shortest simple path between a and b, and let P_2 be the problem of finding a longest simple path between a and b. Which of the following statements about P_1 and P_2 is true?
 A. Both P_1 and P_2 can be solved in polynomial time.
 B. P_1 can be solved in polynomial time but P_2 is not known to be solvable in polynomial time.
 C. P_1 is not known to be solvable in polynomial time but P_2 can be solved in polynomial time.
 D. It is not known whether either P_1 or P_2 can be solved in polynomial time.
Answer:


Question: A major advantage of direct mapping of a cache is its simplicity. The main disadvantage of this organization is that

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: A major advantage of direct mapping of a cache is its simplicity. The main disadvantage of this organization is that
 A. it does not allow simultaneous access to the intended data and its tag
 B. it is more expensive than other types of cache organizations
 C. the cache hit ratio is degraded if two or more blocks used alternately map onto the same block frame in the cache
 D. its access time is greater than that of other cache organizations
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: A major advantage of direct mapping of a cache is its simplicity. The main disadvantage of this organization is that
 A. it does not allow simultaneous access to the intended data and its tag
 B. it is more expensive than other types of cache organizations
 C. the cache hit ratio is degraded if two or more blocks used alternately map onto the same block frame in the cache
 D. its access time is greater than that of other cache organizations
Answer:


Question: A major advantage of direct mapping of a cache is its simplicity. The main disadvantage of this organization is that

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: A major advantage of direct mapping of a cache is its simplicity. The main disadvantage of this organization is that
 A. it does not allow simultaneous access to the intended data and its tag
 B. it is more expensive than other types of cache organizations
 C. the cache hit ratio is degraded if two or more blocks used alternately map onto the same block frame in the cache
 D. its access time is greater than that of other cache organizations
Answer:


Question: A major advantage of direct mapping of a cache is its simplicity. The main disadvantage of this organization is that

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: A major advantage of direct mapping of a cache is its simplicity. The main disadvantage of this organization is that
 A. it does not allow simultaneous access to the intended data and its tag
 B. it is more expensive than other types of cache organizations
 C. the cache hit ratio is degraded if two or more blocks used alternately map onto the same block frame in the cache
 D. its access time is greater than that of other cache organizations
Answer:


Question: A major advantage of direct mapping of a cache is its simplicity. The main disadvantage of this organization is that

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: A major advantage of direct mapping of a cache is its simplicity. The main disadvantage of this organization is that
 A. it does not allow simultaneous access to the intended data and its tag
 B. it is more expensive than other types of cache organizations
 C. the cache hit ratio is degraded if two or more blocks used alternately map onto the same block frame in the cache
 D. its access time is greater than that of other cache organizations
Answer:


Question:
Let M be a single-tape, deterministic Turing machine with tape alphabet {blank,0,1}, and let C denote the (possibly infinite) computation of M starting with a blank tape. The input to each problem below is M, together with a positive integer n. Which of the following problems is (are) decidable?
I. The computation C lasts for at least n steps.
II. The computation C lasts for at least n steps, and M prints a 1 at some point after the nth step.
III. M scans at least n distinct tape squares during the computation C.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let M be a single-tape, deterministic Turing machine with tape alphabet {blank,0,1}, and let C denote the (possibly infinite) computation of M starting with a blank tape. The input to each problem below is M, together with a positive integer n. Which of the following problems is (are) decidable?
I. The computation C lasts for at least n steps.
II. The computation C lasts for at least n steps, and M prints a 1 at some point after the nth step.
III. M scans at least n distinct tape squares during the computation C.
 A. None
 B. III only
 C. I and II only
 D. I and III only
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Let M be a single-tape, deterministic Turing machine with tape alphabet {blank,0,1}, and let C denote the (possibly infinite) computation of M starting with a blank tape. The input to each problem below is M, together with a positive integer n. Which of the following problems is (are) decidable?
I. The computation C lasts for at least n steps.
II. The computation C lasts for at least n steps, and M prints a 1 at some point after the nth step.
III. M scans at least n distinct tape squares during the computation C.
 A. None
 B. III only
 C. I and II only
 D. I and III only
Answer:


Question:
Let M be a single-tape, deterministic Turing machine with tape alphabet {blank,0,1}, and let C denote the (possibly infinite) computation of M starting with a blank tape. The input to each problem below is M, together with a positive integer n. Which of the following problems is (are) decidable?
I. The computation C lasts for at least n steps.
II. The computation C lasts for at least n steps, and M prints a 1 at some point after the nth step.
III. M scans at least n distinct tape squares during the computation C.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let M be a single-tape, deterministic Turing machine with tape alphabet {blank,0,1}, and let C denote the (possibly infinite) computation of M starting with a blank tape. The input to each problem below is M, together with a positive integer n. Which of the following problems is (are) decidable?
I. The computation C lasts for at least n steps.
II. The computation C lasts for at least n steps, and M prints a 1 at some point after the nth step.
III. M scans at least n distinct tape squares during the computation C.
 A. None
 B. III only
 C. I and II only
 D. I and III only
Answer:


Question:
Let M be a single-tape, deterministic Turing machine with tape alphabet {blank,0,1}, and let C denote the (possibly infinite) computation of M starting with a blank tape. The input to each problem below is M, together with a positive integer n. Which of the following problems is (are) decidable?
I. The computation C lasts for at least n steps.
II. The computation C lasts for at least n steps, and M prints a 1 at some point after the nth step.
III. M scans at least n distinct tape squares during the computation C.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let M be a single-tape, deterministic Turing machine with tape alphabet {blank,0,1}, and let C denote the (possibly infinite) computation of M starting with a blank tape. The input to each problem below is M, together with a positive integer n. Which of the following problems is (are) decidable?
I. The computation C lasts for at least n steps.
II. The computation C lasts for at least n steps, and M prints a 1 at some point after the nth step.
III. M scans at least n distinct tape squares during the computation C.
 A. None
 B. III only
 C. I and II only
 D. I and III only
Answer:


Question:
Let M be a single-tape, deterministic Turing machine with tape alphabet {blank,0,1}, and let C denote the (possibly infinite) computation of M starting with a blank tape. The input to each problem below is M, together with a positive integer n. Which of the following problems is (are) decidable?
I. The computation C lasts for at least n steps.
II. The computation C lasts for at least n steps, and M prints a 1 at some point after the nth step.
III. M scans at least n distinct tape squares during the computation C.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let M be a single-tape, deterministic Turing machine with tape alphabet {blank,0,1}, and let C denote the (possibly infinite) computation of M starting with a blank tape. The input to each problem below is M, together with a positive integer n. Which of the following problems is (are) decidable?
I. The computation C lasts for at least n steps.
II. The computation C lasts for at least n steps, and M prints a 1 at some point after the nth step.
III. M scans at least n distinct tape squares during the computation C.
 A. None
 B. III only
 C. I and II only
 D. I and III only
Answer:


Question: A 3-way, set-associative cache is

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: A 3-way, set-associative cache is
 A. one in which each main memory word can be stored at any of 3 cache locations
 B. effective only if 3 or fewer processes are running alternately on the processor
 C. possible only with write-back
 D. faster to access than a direct-mapped cache
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: A 3-way, set-associative cache is
 A. one in which each main memory word can be stored at any of 3 cache locations
 B. effective only if 3 or fewer processes are running alternately on the processor
 C. possible only with write-back
 D. faster to access than a direct-mapped cache
Answer:


Question: A 3-way, set-associative cache is

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: A 3-way, set-associative cache is
 A. one in which each main memory word can be stored at any of 3 cache locations
 B. effective only if 3 or fewer processes are running alternately on the processor
 C. possible only with write-back
 D. faster to access than a direct-mapped cache
Answer:


Question: A 3-way, set-associative cache is

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: A 3-way, set-associative cache is
 A. one in which each main memory word can be stored at any of 3 cache locations
 B. effective only if 3 or fewer processes are running alternately on the processor
 C. possible only with write-back
 D. faster to access than a direct-mapped cache
Answer:


Question: A 3-way, set-associative cache is

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: A 3-way, set-associative cache is
 A. one in which each main memory word can be stored at any of 3 cache locations
 B. effective only if 3 or fewer processes are running alternately on the processor
 C. possible only with write-back
 D. faster to access than a direct-mapped cache
Answer:


Question: Consider an object-oriented language in which all entities are objects. Two relationships arise: (1) the instance relationship, between an object and the class of which that object is a member, and (2) the subclass relationship, between a class and the superclass from which that class inherits properties. In such a language, when a message is sent to an object requesting execution of one of its methods (procedures), the method is located by following

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Consider an object-oriented language in which all entities are objects. Two relationships arise: (1) the instance relationship, between an object and the class of which that object is a member, and (2) the subclass relationship, between a class and the superclass from which that class inherits properties. In such a language, when a message is sent to an object requesting execution of one of its methods (procedures), the method is located by following
 A. one instance link and then zero or more subclass links
 B. one or more instance links and then one or more subclass links
 C. one or more instance links
 D. one subclass link and then one or more instance links
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Consider an object-oriented language in which all entities are objects. Two relationships arise: (1) the instance relationship, between an object and the class of which that object is a member, and (2) the subclass relationship, between a class and the superclass from which that class inherits properties. In such a language, when a message is sent to an object requesting execution of one of its methods (procedures), the method is located by following
 A. one instance link and then zero or more subclass links
 B. one or more instance links and then one or more subclass links
 C. one or more instance links
 D. one subclass link and then one or more instance links
Answer:


Question: Consider an object-oriented language in which all entities are objects. Two relationships arise: (1) the instance relationship, between an object and the class of which that object is a member, and (2) the subclass relationship, between a class and the superclass from which that class inherits properties. In such a language, when a message is sent to an object requesting execution of one of its methods (procedures), the method is located by following

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Consider an object-oriented language in which all entities are objects. Two relationships arise: (1) the instance relationship, between an object and the class of which that object is a member, and (2) the subclass relationship, between a class and the superclass from which that class inherits properties. In such a language, when a message is sent to an object requesting execution of one of its methods (procedures), the method is located by following
 A. one instance link and then zero or more subclass links
 B. one or more instance links and then one or more subclass links
 C. one or more instance links
 D. one subclass link and then one or more instance links
Answer:


Question: Consider an object-oriented language in which all entities are objects. Two relationships arise: (1) the instance relationship, between an object and the class of which that object is a member, and (2) the subclass relationship, between a class and the superclass from which that class inherits properties. In such a language, when a message is sent to an object requesting execution of one of its methods (procedures), the method is located by following

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Consider an object-oriented language in which all entities are objects. Two relationships arise: (1) the instance relationship, between an object and the class of which that object is a member, and (2) the subclass relationship, between a class and the superclass from which that class inherits properties. In such a language, when a message is sent to an object requesting execution of one of its methods (procedures), the method is located by following
 A. one instance link and then zero or more subclass links
 B. one or more instance links and then one or more subclass links
 C. one or more instance links
 D. one subclass link and then one or more instance links
Answer:


Question: Consider an object-oriented language in which all entities are objects. Two relationships arise: (1) the instance relationship, between an object and the class of which that object is a member, and (2) the subclass relationship, between a class and the superclass from which that class inherits properties. In such a language, when a message is sent to an object requesting execution of one of its methods (procedures), the method is located by following

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Consider an object-oriented language in which all entities are objects. Two relationships arise: (1) the instance relationship, between an object and the class of which that object is a member, and (2) the subclass relationship, between a class and the superclass from which that class inherits properties. In such a language, when a message is sent to an object requesting execution of one of its methods (procedures), the method is located by following
 A. one instance link and then zero or more subclass links
 B. one or more instance links and then one or more subclass links
 C. one or more instance links
 D. one subclass link and then one or more instance links
Answer:


Question:
In a pipelined RISC computer where all arithmetic instructions have the same CPI (cycles per instruction), which of the following actions would improve the execution time of a typical program?
I. Increasing the clock cycle rate
II. Disallowing any forwarding in the pipeline
III. Doubling the sizes of the instruction cache and the data cache without changing the clock cycle time

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: In a pipelined RISC computer where all arithmetic instructions have the same CPI (cycles per instruction), which of the following actions would improve the execution time of a typical program?
I. Increasing the clock cycle rate
II. Disallowing any forwarding in the pipeline
III. Doubling the sizes of the instruction cache and the data cache without changing the clock cycle time
 A. I only
 B. II only
 C. III only
 D. I and III
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: In a pipelined RISC computer where all arithmetic instructions have the same CPI (cycles per instruction), which of the following actions would improve the execution time of a typical program?
I. Increasing the clock cycle rate
II. Disallowing any forwarding in the pipeline
III. Doubling the sizes of the instruction cache and the data cache without changing the clock cycle time
 A. I only
 B. II only
 C. III only
 D. I and III
Answer:


Question:
In a pipelined RISC computer where all arithmetic instructions have the same CPI (cycles per instruction), which of the following actions would improve the execution time of a typical program?
I. Increasing the clock cycle rate
II. Disallowing any forwarding in the pipeline
III. Doubling the sizes of the instruction cache and the data cache without changing the clock cycle time

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: In a pipelined RISC computer where all arithmetic instructions have the same CPI (cycles per instruction), which of the following actions would improve the execution time of a typical program?
I. Increasing the clock cycle rate
II. Disallowing any forwarding in the pipeline
III. Doubling the sizes of the instruction cache and the data cache without changing the clock cycle time
 A. I only
 B. II only
 C. III only
 D. I and III
Answer:


Question:
In a pipelined RISC computer where all arithmetic instructions have the same CPI (cycles per instruction), which of the following actions would improve the execution time of a typical program?
I. Increasing the clock cycle rate
II. Disallowing any forwarding in the pipeline
III. Doubling the sizes of the instruction cache and the data cache without changing the clock cycle time

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: In a pipelined RISC computer where all arithmetic instructions have the same CPI (cycles per instruction), which of the following actions would improve the execution time of a typical program?
I. Increasing the clock cycle rate
II. Disallowing any forwarding in the pipeline
III. Doubling the sizes of the instruction cache and the data cache without changing the clock cycle time
 A. I only
 B. II only
 C. III only
 D. I and III
Answer:


Question:
In a pipelined RISC computer where all arithmetic instructions have the same CPI (cycles per instruction), which of the following actions would improve the execution time of a typical program?
I. Increasing the clock cycle rate
II. Disallowing any forwarding in the pipeline
III. Doubling the sizes of the instruction cache and the data cache without changing the clock cycle time

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: In a pipelined RISC computer where all arithmetic instructions have the same CPI (cycles per instruction), which of the following actions would improve the execution time of a typical program?
I. Increasing the clock cycle rate
II. Disallowing any forwarding in the pipeline
III. Doubling the sizes of the instruction cache and the data cache without changing the clock cycle time
 A. I only
 B. II only
 C. III only
 D. I and III
Answer:


Question: A microcomputer used for data acquisition and control is required to digitize and process four analog input signals and to output their average continually; i.e., in real time. The time for an external analog-to-digital converter (which is triggered by a CPU instruction) to digitize one input is 12 microseconds, and only one digitization occurs at a time. Five CPU instructions, including the triggering instruction, must be executed for each signal digitized. Ten CPU instructions are executed in order to average each set of four samples and output this value. The time to convert the output from digital to analog form is to be ignored. If it is assumed that suitable data buffering is employed, then the maximum average instruction execution time that allows the microcomputer to keep up with the input-output data rates, is

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: A microcomputer used for data acquisition and control is required to digitize and process four analog input signals and to output their average continually; i.e., in real time. The time for an external analog-to-digital converter (which is triggered by a CPU instruction) to digitize one input is 12 microseconds, and only one digitization occurs at a time. Five CPU instructions, including the triggering instruction, must be executed for each signal digitized. Ten CPU instructions are executed in order to average each set of four samples and output this value. The time to convert the output from digital to analog form is to be ignored. If it is assumed that suitable data buffering is employed, then the maximum average instruction execution time that allows the microcomputer to keep up with the input-output data rates, is
 A. 0.8 microseconds
 B. 1.2 microseconds
 C. 1.6 microseconds
 D. 2.4 microseconds
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: A microcomputer used for data acquisition and control is required to digitize and process four analog input signals and to output their average continually; i.e., in real time. The time for an external analog-to-digital converter (which is triggered by a CPU instruction) to digitize one input is 12 microseconds, and only one digitization occurs at a time. Five CPU instructions, including the triggering instruction, must be executed for each signal digitized. Ten CPU instructions are executed in order to average each set of four samples and output this value. The time to convert the output from digital to analog form is to be ignored. If it is assumed that suitable data buffering is employed, then the maximum average instruction execution time that allows the microcomputer to keep up with the input-output data rates, is
 A. 0.8 microseconds
 B. 1.2 microseconds
 C. 1.6 microseconds
 D. 2.4 microseconds
Answer:


Question: A microcomputer used for data acquisition and control is required to digitize and process four analog input signals and to output their average continually; i.e., in real time. The time for an external analog-to-digital converter (which is triggered by a CPU instruction) to digitize one input is 12 microseconds, and only one digitization occurs at a time. Five CPU instructions, including the triggering instruction, must be executed for each signal digitized. Ten CPU instructions are executed in order to average each set of four samples and output this value. The time to convert the output from digital to analog form is to be ignored. If it is assumed that suitable data buffering is employed, then the maximum average instruction execution time that allows the microcomputer to keep up with the input-output data rates, is

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: A microcomputer used for data acquisition and control is required to digitize and process four analog input signals and to output their average continually; i.e., in real time. The time for an external analog-to-digital converter (which is triggered by a CPU instruction) to digitize one input is 12 microseconds, and only one digitization occurs at a time. Five CPU instructions, including the triggering instruction, must be executed for each signal digitized. Ten CPU instructions are executed in order to average each set of four samples and output this value. The time to convert the output from digital to analog form is to be ignored. If it is assumed that suitable data buffering is employed, then the maximum average instruction execution time that allows the microcomputer to keep up with the input-output data rates, is
 A. 0.8 microseconds
 B. 1.2 microseconds
 C. 1.6 microseconds
 D. 2.4 microseconds
Answer:


Question: A microcomputer used for data acquisition and control is required to digitize and process four analog input signals and to output their average continually; i.e., in real time. The time for an external analog-to-digital converter (which is triggered by a CPU instruction) to digitize one input is 12 microseconds, and only one digitization occurs at a time. Five CPU instructions, including the triggering instruction, must be executed for each signal digitized. Ten CPU instructions are executed in order to average each set of four samples and output this value. The time to convert the output from digital to analog form is to be ignored. If it is assumed that suitable data buffering is employed, then the maximum average instruction execution time that allows the microcomputer to keep up with the input-output data rates, is

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: A microcomputer used for data acquisition and control is required to digitize and process four analog input signals and to output their average continually; i.e., in real time. The time for an external analog-to-digital converter (which is triggered by a CPU instruction) to digitize one input is 12 microseconds, and only one digitization occurs at a time. Five CPU instructions, including the triggering instruction, must be executed for each signal digitized. Ten CPU instructions are executed in order to average each set of four samples and output this value. The time to convert the output from digital to analog form is to be ignored. If it is assumed that suitable data buffering is employed, then the maximum average instruction execution time that allows the microcomputer to keep up with the input-output data rates, is
 A. 0.8 microseconds
 B. 1.2 microseconds
 C. 1.6 microseconds
 D. 2.4 microseconds
Answer:


Question: A microcomputer used for data acquisition and control is required to digitize and process four analog input signals and to output their average continually; i.e., in real time. The time for an external analog-to-digital converter (which is triggered by a CPU instruction) to digitize one input is 12 microseconds, and only one digitization occurs at a time. Five CPU instructions, including the triggering instruction, must be executed for each signal digitized. Ten CPU instructions are executed in order to average each set of four samples and output this value. The time to convert the output from digital to analog form is to be ignored. If it is assumed that suitable data buffering is employed, then the maximum average instruction execution time that allows the microcomputer to keep up with the input-output data rates, is

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: A microcomputer used for data acquisition and control is required to digitize and process four analog input signals and to output their average continually; i.e., in real time. The time for an external analog-to-digital converter (which is triggered by a CPU instruction) to digitize one input is 12 microseconds, and only one digitization occurs at a time. Five CPU instructions, including the triggering instruction, must be executed for each signal digitized. Ten CPU instructions are executed in order to average each set of four samples and output this value. The time to convert the output from digital to analog form is to be ignored. If it is assumed that suitable data buffering is employed, then the maximum average instruction execution time that allows the microcomputer to keep up with the input-output data rates, is
 A. 0.8 microseconds
 B. 1.2 microseconds
 C. 1.6 microseconds
 D. 2.4 microseconds
Answer:


Question: Suppose that a certain software product has a mean time between failures of 10,000 hours and has a mean time to repair of 20 hours. If the product is used by 100 customers, what is its availability?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Suppose that a certain software product has a mean time between failures of 10,000 hours and has a mean time to repair of 20 hours. If the product is used by 100 customers, what is its availability?
 A. 80%
 B. 90%
 C. 98%
 D. 99.80%
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Suppose that a certain software product has a mean time between failures of 10,000 hours and has a mean time to repair of 20 hours. If the product is used by 100 customers, what is its availability?
 A. 80%
 B. 90%
 C. 98%
 D. 99.80%
Answer:


Question: Suppose that a certain software product has a mean time between failures of 10,000 hours and has a mean time to repair of 20 hours. If the product is used by 100 customers, what is its availability?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Suppose that a certain software product has a mean time between failures of 10,000 hours and has a mean time to repair of 20 hours. If the product is used by 100 customers, what is its availability?
 A. 80%
 B. 90%
 C. 98%
 D. 99.80%
Answer:


Question: Suppose that a certain software product has a mean time between failures of 10,000 hours and has a mean time to repair of 20 hours. If the product is used by 100 customers, what is its availability?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Suppose that a certain software product has a mean time between failures of 10,000 hours and has a mean time to repair of 20 hours. If the product is used by 100 customers, what is its availability?
 A. 80%
 B. 90%
 C. 98%
 D. 99.80%
Answer:


Question: Suppose that a certain software product has a mean time between failures of 10,000 hours and has a mean time to repair of 20 hours. If the product is used by 100 customers, what is its availability?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Suppose that a certain software product has a mean time between failures of 10,000 hours and has a mean time to repair of 20 hours. If the product is used by 100 customers, what is its availability?
 A. 80%
 B. 90%
 C. 98%
 D. 99.80%
Answer: