Question: In systems with support for automatic memory management, a garbage collector typically has the responsibility for reclaiming allocated memory objects whose contents cannot affect any future legal computation. Such objects are identified by determining that they cannot be reached from a root set. Which of the following is NOT part of the root set in a typical garbage collector?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: In systems with support for automatic memory management, a garbage collector typically has the responsibility for reclaiming allocated memory objects whose contents cannot affect any future legal computation. Such objects are identified by determining that they cannot be reached from a root set. Which of the following is NOT part of the root set in a typical garbage collector?
 A. Actual parameters of the active procedures
 B. Dynamically allocated objects on the heap
 C. Global variables of the program
 D. Local variables on the call stack
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: In systems with support for automatic memory management, a garbage collector typically has the responsibility for reclaiming allocated memory objects whose contents cannot affect any future legal computation. Such objects are identified by determining that they cannot be reached from a root set. Which of the following is NOT part of the root set in a typical garbage collector?
 A. Actual parameters of the active procedures
 B. Dynamically allocated objects on the heap
 C. Global variables of the program
 D. Local variables on the call stack
Answer:


Question: In systems with support for automatic memory management, a garbage collector typically has the responsibility for reclaiming allocated memory objects whose contents cannot affect any future legal computation. Such objects are identified by determining that they cannot be reached from a root set. Which of the following is NOT part of the root set in a typical garbage collector?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: In systems with support for automatic memory management, a garbage collector typically has the responsibility for reclaiming allocated memory objects whose contents cannot affect any future legal computation. Such objects are identified by determining that they cannot be reached from a root set. Which of the following is NOT part of the root set in a typical garbage collector?
 A. Actual parameters of the active procedures
 B. Dynamically allocated objects on the heap
 C. Global variables of the program
 D. Local variables on the call stack
Answer:


Question: In systems with support for automatic memory management, a garbage collector typically has the responsibility for reclaiming allocated memory objects whose contents cannot affect any future legal computation. Such objects are identified by determining that they cannot be reached from a root set. Which of the following is NOT part of the root set in a typical garbage collector?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: In systems with support for automatic memory management, a garbage collector typically has the responsibility for reclaiming allocated memory objects whose contents cannot affect any future legal computation. Such objects are identified by determining that they cannot be reached from a root set. Which of the following is NOT part of the root set in a typical garbage collector?
 A. Actual parameters of the active procedures
 B. Dynamically allocated objects on the heap
 C. Global variables of the program
 D. Local variables on the call stack
Answer:


Question: In systems with support for automatic memory management, a garbage collector typically has the responsibility for reclaiming allocated memory objects whose contents cannot affect any future legal computation. Such objects are identified by determining that they cannot be reached from a root set. Which of the following is NOT part of the root set in a typical garbage collector?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: In systems with support for automatic memory management, a garbage collector typically has the responsibility for reclaiming allocated memory objects whose contents cannot affect any future legal computation. Such objects are identified by determining that they cannot be reached from a root set. Which of the following is NOT part of the root set in a typical garbage collector?
 A. Actual parameters of the active procedures
 B. Dynamically allocated objects on the heap
 C. Global variables of the program
 D. Local variables on the call stack
Answer:


Question: In the Internet Protocol (IP) suite of protocols, which of the following best describes the purpose of the Address Resolution Protocol?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: In the Internet Protocol (IP) suite of protocols, which of the following best describes the purpose of the Address Resolution Protocol?
 A. To translate Web addresses to host names
 B. To determine the IP address of a given host name
 C. To determine the hardware address of a given host name
 D. To determine the hardware address of a given IP address
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: In the Internet Protocol (IP) suite of protocols, which of the following best describes the purpose of the Address Resolution Protocol?
 A. To translate Web addresses to host names
 B. To determine the IP address of a given host name
 C. To determine the hardware address of a given host name
 D. To determine the hardware address of a given IP address
Answer:


Question: In the Internet Protocol (IP) suite of protocols, which of the following best describes the purpose of the Address Resolution Protocol?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: In the Internet Protocol (IP) suite of protocols, which of the following best describes the purpose of the Address Resolution Protocol?
 A. To translate Web addresses to host names
 B. To determine the IP address of a given host name
 C. To determine the hardware address of a given host name
 D. To determine the hardware address of a given IP address
Answer:


Question: In the Internet Protocol (IP) suite of protocols, which of the following best describes the purpose of the Address Resolution Protocol?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: In the Internet Protocol (IP) suite of protocols, which of the following best describes the purpose of the Address Resolution Protocol?
 A. To translate Web addresses to host names
 B. To determine the IP address of a given host name
 C. To determine the hardware address of a given host name
 D. To determine the hardware address of a given IP address
Answer:


Question: In the Internet Protocol (IP) suite of protocols, which of the following best describes the purpose of the Address Resolution Protocol?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: In the Internet Protocol (IP) suite of protocols, which of the following best describes the purpose of the Address Resolution Protocol?
 A. To translate Web addresses to host names
 B. To determine the IP address of a given host name
 C. To determine the hardware address of a given host name
 D. To determine the hardware address of a given IP address
Answer:


Question: Which of the following language features requires that stack-based storage allocation be used rather than static allocation?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following language features requires that stack-based storage allocation be used rather than static allocation?
 A. Recursive procedures
 B. Arbitrary goto's
 C. Two-dimensional arrays
 D. Integer-valued functions
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Which of the following language features requires that stack-based storage allocation be used rather than static allocation?
 A. Recursive procedures
 B. Arbitrary goto's
 C. Two-dimensional arrays
 D. Integer-valued functions
Answer:


Question: Which of the following language features requires that stack-based storage allocation be used rather than static allocation?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following language features requires that stack-based storage allocation be used rather than static allocation?
 A. Recursive procedures
 B. Arbitrary goto's
 C. Two-dimensional arrays
 D. Integer-valued functions
Answer:


Question: Which of the following language features requires that stack-based storage allocation be used rather than static allocation?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following language features requires that stack-based storage allocation be used rather than static allocation?
 A. Recursive procedures
 B. Arbitrary goto's
 C. Two-dimensional arrays
 D. Integer-valued functions
Answer:


Question: Which of the following language features requires that stack-based storage allocation be used rather than static allocation?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following language features requires that stack-based storage allocation be used rather than static allocation?
 A. Recursive procedures
 B. Arbitrary goto's
 C. Two-dimensional arrays
 D. Integer-valued functions
Answer:


Question: Which of the following is not a sentence that is generated by the grammar A -> BC, B -> x|Bx, C -> B|D, D -> y|Ey, E -> z?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following is not a sentence that is generated by the grammar A -> BC, B -> x|Bx, C -> B|D, D -> y|Ey, E -> z?
 A. xyz
 B. xy
 C. xxzy
 D. xxxxy
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Which of the following is not a sentence that is generated by the grammar A -> BC, B -> x|Bx, C -> B|D, D -> y|Ey, E -> z?
 A. xyz
 B. xy
 C. xxzy
 D. xxxxy
Answer:


Question: Which of the following is not a sentence that is generated by the grammar A -> BC, B -> x|Bx, C -> B|D, D -> y|Ey, E -> z?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following is not a sentence that is generated by the grammar A -> BC, B -> x|Bx, C -> B|D, D -> y|Ey, E -> z?
 A. xyz
 B. xy
 C. xxzy
 D. xxxxy
Answer:


Question: Which of the following is not a sentence that is generated by the grammar A -> BC, B -> x|Bx, C -> B|D, D -> y|Ey, E -> z?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following is not a sentence that is generated by the grammar A -> BC, B -> x|Bx, C -> B|D, D -> y|Ey, E -> z?
 A. xyz
 B. xy
 C. xxzy
 D. xxxxy
Answer:


Question: Which of the following is not a sentence that is generated by the grammar A -> BC, B -> x|Bx, C -> B|D, D -> y|Ey, E -> z?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following is not a sentence that is generated by the grammar A -> BC, B -> x|Bx, C -> B|D, D -> y|Ey, E -> z?
 A. xyz
 B. xy
 C. xxzy
 D. xxxxy
Answer:


Question: Let T (n) be defined by T(1) = 7 and T(n + 1) = 3n + T(n) for all integers n ≥ 1. Which of the following represents the order of growth of T(n) as a function of n?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let T (n) be defined by T(1) = 7 and T(n + 1) = 3n + T(n) for all integers n ≥ 1. Which of the following represents the order of growth of T(n) as a function of n?
 A. Θ(n)
 B. Θ(n log n)
 C. Θ(n^2)
 D. Θ(n^2 log n)
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Let T (n) be defined by T(1) = 7 and T(n + 1) = 3n + T(n) for all integers n ≥ 1. Which of the following represents the order of growth of T(n) as a function of n?
 A. Θ(n)
 B. Θ(n log n)
 C. Θ(n^2)
 D. Θ(n^2 log n)
Answer:


Question: Let T (n) be defined by T(1) = 7 and T(n + 1) = 3n + T(n) for all integers n ≥ 1. Which of the following represents the order of growth of T(n) as a function of n?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let T (n) be defined by T(1) = 7 and T(n + 1) = 3n + T(n) for all integers n ≥ 1. Which of the following represents the order of growth of T(n) as a function of n?
 A. Θ(n)
 B. Θ(n log n)
 C. Θ(n^2)
 D. Θ(n^2 log n)
Answer:


Question: Let T (n) be defined by T(1) = 7 and T(n + 1) = 3n + T(n) for all integers n ≥ 1. Which of the following represents the order of growth of T(n) as a function of n?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let T (n) be defined by T(1) = 7 and T(n + 1) = 3n + T(n) for all integers n ≥ 1. Which of the following represents the order of growth of T(n) as a function of n?
 A. Θ(n)
 B. Θ(n log n)
 C. Θ(n^2)
 D. Θ(n^2 log n)
Answer:


Question: Let T (n) be defined by T(1) = 7 and T(n + 1) = 3n + T(n) for all integers n ≥ 1. Which of the following represents the order of growth of T(n) as a function of n?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Let T (n) be defined by T(1) = 7 and T(n + 1) = 3n + T(n) for all integers n ≥ 1. Which of the following represents the order of growth of T(n) as a function of n?
 A. Θ(n)
 B. Θ(n log n)
 C. Θ(n^2)
 D. Θ(n^2 log n)
Answer:


Question:
Which of the following problems is (are) decidable?
I. Given a (finite) string w, is w a prefix of the decimal expansion of π?
II. Given a program and an input, is the program’s output the decimal expansion of π?
III. Given a program that takes as input a prefix of the decimal expansion of π, is the program’s output always the same for every prefix?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following problems is (are) decidable?
I. Given a (finite) string w, is w a prefix of the decimal expansion of π?
II. Given a program and an input, is the program’s output the decimal expansion of π?
III. Given a program that takes as input a prefix of the decimal expansion of π, is the program’s output always the same for every prefix?
 A. I only
 B. II only
 C. III only
 D. I and II only
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Which of the following problems is (are) decidable?
I. Given a (finite) string w, is w a prefix of the decimal expansion of π?
II. Given a program and an input, is the program’s output the decimal expansion of π?
III. Given a program that takes as input a prefix of the decimal expansion of π, is the program’s output always the same for every prefix?
 A. I only
 B. II only
 C. III only
 D. I and II only
Answer:


Question:
Which of the following problems is (are) decidable?
I. Given a (finite) string w, is w a prefix of the decimal expansion of π?
II. Given a program and an input, is the program’s output the decimal expansion of π?
III. Given a program that takes as input a prefix of the decimal expansion of π, is the program’s output always the same for every prefix?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following problems is (are) decidable?
I. Given a (finite) string w, is w a prefix of the decimal expansion of π?
II. Given a program and an input, is the program’s output the decimal expansion of π?
III. Given a program that takes as input a prefix of the decimal expansion of π, is the program’s output always the same for every prefix?
 A. I only
 B. II only
 C. III only
 D. I and II only
Answer:


Question:
Which of the following problems is (are) decidable?
I. Given a (finite) string w, is w a prefix of the decimal expansion of π?
II. Given a program and an input, is the program’s output the decimal expansion of π?
III. Given a program that takes as input a prefix of the decimal expansion of π, is the program’s output always the same for every prefix?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following problems is (are) decidable?
I. Given a (finite) string w, is w a prefix of the decimal expansion of π?
II. Given a program and an input, is the program’s output the decimal expansion of π?
III. Given a program that takes as input a prefix of the decimal expansion of π, is the program’s output always the same for every prefix?
 A. I only
 B. II only
 C. III only
 D. I and II only
Answer:


Question:
Which of the following problems is (are) decidable?
I. Given a (finite) string w, is w a prefix of the decimal expansion of π?
II. Given a program and an input, is the program’s output the decimal expansion of π?
III. Given a program that takes as input a prefix of the decimal expansion of π, is the program’s output always the same for every prefix?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following problems is (are) decidable?
I. Given a (finite) string w, is w a prefix of the decimal expansion of π?
II. Given a program and an input, is the program’s output the decimal expansion of π?
III. Given a program that takes as input a prefix of the decimal expansion of π, is the program’s output always the same for every prefix?
 A. I only
 B. II only
 C. III only
 D. I and II only
Answer:


Question:
Which of the following statements about circuits is (are) true?
I. Combinational circuits may have feedback; sequential circuits do not.
II. Combinational circuits have a "memoryless" property; sequential circuits do not.
III. Both sequential and combinational circuits must be controlled by an external clock.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following statements about circuits is (are) true?
I. Combinational circuits may have feedback; sequential circuits do not.
II. Combinational circuits have a "memoryless" property; sequential circuits do not.
III. Both sequential and combinational circuits must be controlled by an external clock.
 A. I only
 B. II only
 C. I and II only
 D. II and III only
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Which of the following statements about circuits is (are) true?
I. Combinational circuits may have feedback; sequential circuits do not.
II. Combinational circuits have a "memoryless" property; sequential circuits do not.
III. Both sequential and combinational circuits must be controlled by an external clock.
 A. I only
 B. II only
 C. I and II only
 D. II and III only
Answer:


Question:
Which of the following statements about circuits is (are) true?
I. Combinational circuits may have feedback; sequential circuits do not.
II. Combinational circuits have a "memoryless" property; sequential circuits do not.
III. Both sequential and combinational circuits must be controlled by an external clock.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following statements about circuits is (are) true?
I. Combinational circuits may have feedback; sequential circuits do not.
II. Combinational circuits have a "memoryless" property; sequential circuits do not.
III. Both sequential and combinational circuits must be controlled by an external clock.
 A. I only
 B. II only
 C. I and II only
 D. II and III only
Answer:


Question:
Which of the following statements about circuits is (are) true?
I. Combinational circuits may have feedback; sequential circuits do not.
II. Combinational circuits have a "memoryless" property; sequential circuits do not.
III. Both sequential and combinational circuits must be controlled by an external clock.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following statements about circuits is (are) true?
I. Combinational circuits may have feedback; sequential circuits do not.
II. Combinational circuits have a "memoryless" property; sequential circuits do not.
III. Both sequential and combinational circuits must be controlled by an external clock.
 A. I only
 B. II only
 C. I and II only
 D. II and III only
Answer:


Question:
Which of the following statements about circuits is (are) true?
I. Combinational circuits may have feedback; sequential circuits do not.
II. Combinational circuits have a "memoryless" property; sequential circuits do not.
III. Both sequential and combinational circuits must be controlled by an external clock.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following statements about circuits is (are) true?
I. Combinational circuits may have feedback; sequential circuits do not.
II. Combinational circuits have a "memoryless" property; sequential circuits do not.
III. Both sequential and combinational circuits must be controlled by an external clock.
 A. I only
 B. II only
 C. I and II only
 D. II and III only
Answer:


Question: Two single-user workstations are attached to the same local area network. On one of these workstations, file pages are accessed over the network from a file server; the average access time per page is 0.1 second. On the other of these workstations, file pages are accessed from a local disk; the average access time per page is 0.05 second. A particular compilation requires 30 seconds of computation and 200 file page accesses. What is the ratio of the total time required by this compilation if run on the diskless (file server) workstation to the total time required if run on the workstation with the local disk, if it is assumed that computation is not overlapped with file access?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Two single-user workstations are attached to the same local area network. On one of these workstations, file pages are accessed over the network from a file server; the average access time per page is 0.1 second. On the other of these workstations, file pages are accessed from a local disk; the average access time per page is 0.05 second. A particular compilation requires 30 seconds of computation and 200 file page accesses. What is the ratio of the total time required by this compilation if run on the diskless (file server) workstation to the total time required if run on the workstation with the local disk, if it is assumed that computation is not overlapped with file access?
 A. 1/1
 B. 5/4
 C. 5/3
 D. 10/5
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Two single-user workstations are attached to the same local area network. On one of these workstations, file pages are accessed over the network from a file server; the average access time per page is 0.1 second. On the other of these workstations, file pages are accessed from a local disk; the average access time per page is 0.05 second. A particular compilation requires 30 seconds of computation and 200 file page accesses. What is the ratio of the total time required by this compilation if run on the diskless (file server) workstation to the total time required if run on the workstation with the local disk, if it is assumed that computation is not overlapped with file access?
 A. 1/1
 B. 5/4
 C. 5/3
 D. 10/5
Answer:


Question: Two single-user workstations are attached to the same local area network. On one of these workstations, file pages are accessed over the network from a file server; the average access time per page is 0.1 second. On the other of these workstations, file pages are accessed from a local disk; the average access time per page is 0.05 second. A particular compilation requires 30 seconds of computation and 200 file page accesses. What is the ratio of the total time required by this compilation if run on the diskless (file server) workstation to the total time required if run on the workstation with the local disk, if it is assumed that computation is not overlapped with file access?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Two single-user workstations are attached to the same local area network. On one of these workstations, file pages are accessed over the network from a file server; the average access time per page is 0.1 second. On the other of these workstations, file pages are accessed from a local disk; the average access time per page is 0.05 second. A particular compilation requires 30 seconds of computation and 200 file page accesses. What is the ratio of the total time required by this compilation if run on the diskless (file server) workstation to the total time required if run on the workstation with the local disk, if it is assumed that computation is not overlapped with file access?
 A. 1/1
 B. 5/4
 C. 5/3
 D. 10/5
Answer:


Question: Two single-user workstations are attached to the same local area network. On one of these workstations, file pages are accessed over the network from a file server; the average access time per page is 0.1 second. On the other of these workstations, file pages are accessed from a local disk; the average access time per page is 0.05 second. A particular compilation requires 30 seconds of computation and 200 file page accesses. What is the ratio of the total time required by this compilation if run on the diskless (file server) workstation to the total time required if run on the workstation with the local disk, if it is assumed that computation is not overlapped with file access?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Two single-user workstations are attached to the same local area network. On one of these workstations, file pages are accessed over the network from a file server; the average access time per page is 0.1 second. On the other of these workstations, file pages are accessed from a local disk; the average access time per page is 0.05 second. A particular compilation requires 30 seconds of computation and 200 file page accesses. What is the ratio of the total time required by this compilation if run on the diskless (file server) workstation to the total time required if run on the workstation with the local disk, if it is assumed that computation is not overlapped with file access?
 A. 1/1
 B. 5/4
 C. 5/3
 D. 10/5
Answer:


Question: Two single-user workstations are attached to the same local area network. On one of these workstations, file pages are accessed over the network from a file server; the average access time per page is 0.1 second. On the other of these workstations, file pages are accessed from a local disk; the average access time per page is 0.05 second. A particular compilation requires 30 seconds of computation and 200 file page accesses. What is the ratio of the total time required by this compilation if run on the diskless (file server) workstation to the total time required if run on the workstation with the local disk, if it is assumed that computation is not overlapped with file access?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Two single-user workstations are attached to the same local area network. On one of these workstations, file pages are accessed over the network from a file server; the average access time per page is 0.1 second. On the other of these workstations, file pages are accessed from a local disk; the average access time per page is 0.05 second. A particular compilation requires 30 seconds of computation and 200 file page accesses. What is the ratio of the total time required by this compilation if run on the diskless (file server) workstation to the total time required if run on the workstation with the local disk, if it is assumed that computation is not overlapped with file access?
 A. 1/1
 B. 5/4
 C. 5/3
 D. 10/5
Answer:


Question: Assume that a debugger places a breakpoint at a load instruction at virtual address 0x77E81234 (hexadecimal notation) in a debugged process P. If the text segment of P begins at 0x77E80000 in P’s virtual address space and if the debugger has mapped this same text segment at 0x01000000 in its virtual address space, which of the following is the virtual address used by the debugger in its WRITE operation, along with a description of how the debugger has mapped the virtual memory page containing this address?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Assume that a debugger places a breakpoint at a load instruction at virtual address 0x77E81234 (hexadecimal notation) in a debugged process P. If the text segment of P begins at 0x77E80000 in P’s virtual address space and if the debugger has mapped this same text segment at 0x01000000 in its virtual address space, which of the following is the virtual address used by the debugger in its WRITE operation, along with a description of how the debugger has mapped the virtual memory page containing this address?
 A. 0x01001234; page mapped with READ/WRITE access
 B. 0x01001234; page mapped with COPY-ON-WRITE access
 C. 0x76E81234; page mapped with READ/WRITE access
 D. 0x76E81234; page mapped with COPY-ON-WRITE access
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Assume that a debugger places a breakpoint at a load instruction at virtual address 0x77E81234 (hexadecimal notation) in a debugged process P. If the text segment of P begins at 0x77E80000 in P’s virtual address space and if the debugger has mapped this same text segment at 0x01000000 in its virtual address space, which of the following is the virtual address used by the debugger in its WRITE operation, along with a description of how the debugger has mapped the virtual memory page containing this address?
 A. 0x01001234; page mapped with READ/WRITE access
 B. 0x01001234; page mapped with COPY-ON-WRITE access
 C. 0x76E81234; page mapped with READ/WRITE access
 D. 0x76E81234; page mapped with COPY-ON-WRITE access
Answer:


Question: Assume that a debugger places a breakpoint at a load instruction at virtual address 0x77E81234 (hexadecimal notation) in a debugged process P. If the text segment of P begins at 0x77E80000 in P’s virtual address space and if the debugger has mapped this same text segment at 0x01000000 in its virtual address space, which of the following is the virtual address used by the debugger in its WRITE operation, along with a description of how the debugger has mapped the virtual memory page containing this address?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Assume that a debugger places a breakpoint at a load instruction at virtual address 0x77E81234 (hexadecimal notation) in a debugged process P. If the text segment of P begins at 0x77E80000 in P’s virtual address space and if the debugger has mapped this same text segment at 0x01000000 in its virtual address space, which of the following is the virtual address used by the debugger in its WRITE operation, along with a description of how the debugger has mapped the virtual memory page containing this address?
 A. 0x01001234; page mapped with READ/WRITE access
 B. 0x01001234; page mapped with COPY-ON-WRITE access
 C. 0x76E81234; page mapped with READ/WRITE access
 D. 0x76E81234; page mapped with COPY-ON-WRITE access
Answer:


Question: Assume that a debugger places a breakpoint at a load instruction at virtual address 0x77E81234 (hexadecimal notation) in a debugged process P. If the text segment of P begins at 0x77E80000 in P’s virtual address space and if the debugger has mapped this same text segment at 0x01000000 in its virtual address space, which of the following is the virtual address used by the debugger in its WRITE operation, along with a description of how the debugger has mapped the virtual memory page containing this address?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Assume that a debugger places a breakpoint at a load instruction at virtual address 0x77E81234 (hexadecimal notation) in a debugged process P. If the text segment of P begins at 0x77E80000 in P’s virtual address space and if the debugger has mapped this same text segment at 0x01000000 in its virtual address space, which of the following is the virtual address used by the debugger in its WRITE operation, along with a description of how the debugger has mapped the virtual memory page containing this address?
 A. 0x01001234; page mapped with READ/WRITE access
 B. 0x01001234; page mapped with COPY-ON-WRITE access
 C. 0x76E81234; page mapped with READ/WRITE access
 D. 0x76E81234; page mapped with COPY-ON-WRITE access
Answer:


Question: Assume that a debugger places a breakpoint at a load instruction at virtual address 0x77E81234 (hexadecimal notation) in a debugged process P. If the text segment of P begins at 0x77E80000 in P’s virtual address space and if the debugger has mapped this same text segment at 0x01000000 in its virtual address space, which of the following is the virtual address used by the debugger in its WRITE operation, along with a description of how the debugger has mapped the virtual memory page containing this address?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Assume that a debugger places a breakpoint at a load instruction at virtual address 0x77E81234 (hexadecimal notation) in a debugged process P. If the text segment of P begins at 0x77E80000 in P’s virtual address space and if the debugger has mapped this same text segment at 0x01000000 in its virtual address space, which of the following is the virtual address used by the debugger in its WRITE operation, along with a description of how the debugger has mapped the virtual memory page containing this address?
 A. 0x01001234; page mapped with READ/WRITE access
 B. 0x01001234; page mapped with COPY-ON-WRITE access
 C. 0x76E81234; page mapped with READ/WRITE access
 D. 0x76E81234; page mapped with COPY-ON-WRITE access
Answer:


Question:
Which of the following considerations applies (apply) to choosing the page size in a paging system?
I. An advantage of larger pages is that they lead to smaller page tables.
II. An advantage of smaller pages is that they lead to less waste due to internal fragmentation.
III. Normally, the dominant factor in disk access time is not dependent on page length, so longer pages can be used advantageously.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following considerations applies (apply) to choosing the page size in a paging system?
I. An advantage of larger pages is that they lead to smaller page tables.
II. An advantage of smaller pages is that they lead to less waste due to internal fragmentation.
III. Normally, the dominant factor in disk access time is not dependent on page length, so longer pages can be used advantageously.
 A. I only
 B. II only
 C. I and III only
 D. I, II, and III
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Which of the following considerations applies (apply) to choosing the page size in a paging system?
I. An advantage of larger pages is that they lead to smaller page tables.
II. An advantage of smaller pages is that they lead to less waste due to internal fragmentation.
III. Normally, the dominant factor in disk access time is not dependent on page length, so longer pages can be used advantageously.
 A. I only
 B. II only
 C. I and III only
 D. I, II, and III
Answer:


Question:
Which of the following considerations applies (apply) to choosing the page size in a paging system?
I. An advantage of larger pages is that they lead to smaller page tables.
II. An advantage of smaller pages is that they lead to less waste due to internal fragmentation.
III. Normally, the dominant factor in disk access time is not dependent on page length, so longer pages can be used advantageously.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following considerations applies (apply) to choosing the page size in a paging system?
I. An advantage of larger pages is that they lead to smaller page tables.
II. An advantage of smaller pages is that they lead to less waste due to internal fragmentation.
III. Normally, the dominant factor in disk access time is not dependent on page length, so longer pages can be used advantageously.
 A. I only
 B. II only
 C. I and III only
 D. I, II, and III
Answer:


Question:
Which of the following considerations applies (apply) to choosing the page size in a paging system?
I. An advantage of larger pages is that they lead to smaller page tables.
II. An advantage of smaller pages is that they lead to less waste due to internal fragmentation.
III. Normally, the dominant factor in disk access time is not dependent on page length, so longer pages can be used advantageously.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following considerations applies (apply) to choosing the page size in a paging system?
I. An advantage of larger pages is that they lead to smaller page tables.
II. An advantage of smaller pages is that they lead to less waste due to internal fragmentation.
III. Normally, the dominant factor in disk access time is not dependent on page length, so longer pages can be used advantageously.
 A. I only
 B. II only
 C. I and III only
 D. I, II, and III
Answer:


Question:
Which of the following considerations applies (apply) to choosing the page size in a paging system?
I. An advantage of larger pages is that they lead to smaller page tables.
II. An advantage of smaller pages is that they lead to less waste due to internal fragmentation.
III. Normally, the dominant factor in disk access time is not dependent on page length, so longer pages can be used advantageously.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following considerations applies (apply) to choosing the page size in a paging system?
I. An advantage of larger pages is that they lead to smaller page tables.
II. An advantage of smaller pages is that they lead to less waste due to internal fragmentation.
III. Normally, the dominant factor in disk access time is not dependent on page length, so longer pages can be used advantageously.
 A. I only
 B. II only
 C. I and III only
 D. I, II, and III
Answer:


Question:
Two processors, M-5 and M-7, implement the same instruction set. Processor M-5 uses a 5-stage pipeline and a clock cycle of 10 nanoseconds. Processor M-7 uses a 7-stage pipeline and a clock cycle of 7.5 nanoseconds. Which of the following is (are) true?
I. M-7’s pipeline has better maximum throughput than M-5’s pipeline.
II. The latency of a single instruction is shorter on M-7’s pipeline than on M-5’s pipeline.
III. Programs executing on M-7 will always run faster than programs executing on M-5.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Two processors, M-5 and M-7, implement the same instruction set. Processor M-5 uses a 5-stage pipeline and a clock cycle of 10 nanoseconds. Processor M-7 uses a 7-stage pipeline and a clock cycle of 7.5 nanoseconds. Which of the following is (are) true?
I. M-7’s pipeline has better maximum throughput than M-5’s pipeline.
II. The latency of a single instruction is shorter on M-7’s pipeline than on M-5’s pipeline.
III. Programs executing on M-7 will always run faster than programs executing on M-5.
 A. I only
 B. II only
 C. I and III
 D. II and III
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Two processors, M-5 and M-7, implement the same instruction set. Processor M-5 uses a 5-stage pipeline and a clock cycle of 10 nanoseconds. Processor M-7 uses a 7-stage pipeline and a clock cycle of 7.5 nanoseconds. Which of the following is (are) true?
I. M-7’s pipeline has better maximum throughput than M-5’s pipeline.
II. The latency of a single instruction is shorter on M-7’s pipeline than on M-5’s pipeline.
III. Programs executing on M-7 will always run faster than programs executing on M-5.
 A. I only
 B. II only
 C. I and III
 D. II and III
Answer:


Question:
Two processors, M-5 and M-7, implement the same instruction set. Processor M-5 uses a 5-stage pipeline and a clock cycle of 10 nanoseconds. Processor M-7 uses a 7-stage pipeline and a clock cycle of 7.5 nanoseconds. Which of the following is (are) true?
I. M-7’s pipeline has better maximum throughput than M-5’s pipeline.
II. The latency of a single instruction is shorter on M-7’s pipeline than on M-5’s pipeline.
III. Programs executing on M-7 will always run faster than programs executing on M-5.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Two processors, M-5 and M-7, implement the same instruction set. Processor M-5 uses a 5-stage pipeline and a clock cycle of 10 nanoseconds. Processor M-7 uses a 7-stage pipeline and a clock cycle of 7.5 nanoseconds. Which of the following is (are) true?
I. M-7’s pipeline has better maximum throughput than M-5’s pipeline.
II. The latency of a single instruction is shorter on M-7’s pipeline than on M-5’s pipeline.
III. Programs executing on M-7 will always run faster than programs executing on M-5.
 A. I only
 B. II only
 C. I and III
 D. II and III
Answer:


Question:
Two processors, M-5 and M-7, implement the same instruction set. Processor M-5 uses a 5-stage pipeline and a clock cycle of 10 nanoseconds. Processor M-7 uses a 7-stage pipeline and a clock cycle of 7.5 nanoseconds. Which of the following is (are) true?
I. M-7’s pipeline has better maximum throughput than M-5’s pipeline.
II. The latency of a single instruction is shorter on M-7’s pipeline than on M-5’s pipeline.
III. Programs executing on M-7 will always run faster than programs executing on M-5.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Two processors, M-5 and M-7, implement the same instruction set. Processor M-5 uses a 5-stage pipeline and a clock cycle of 10 nanoseconds. Processor M-7 uses a 7-stage pipeline and a clock cycle of 7.5 nanoseconds. Which of the following is (are) true?
I. M-7’s pipeline has better maximum throughput than M-5’s pipeline.
II. The latency of a single instruction is shorter on M-7’s pipeline than on M-5’s pipeline.
III. Programs executing on M-7 will always run faster than programs executing on M-5.
 A. I only
 B. II only
 C. I and III
 D. II and III
Answer:


Question:
Two processors, M-5 and M-7, implement the same instruction set. Processor M-5 uses a 5-stage pipeline and a clock cycle of 10 nanoseconds. Processor M-7 uses a 7-stage pipeline and a clock cycle of 7.5 nanoseconds. Which of the following is (are) true?
I. M-7’s pipeline has better maximum throughput than M-5’s pipeline.
II. The latency of a single instruction is shorter on M-7’s pipeline than on M-5’s pipeline.
III. Programs executing on M-7 will always run faster than programs executing on M-5.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Two processors, M-5 and M-7, implement the same instruction set. Processor M-5 uses a 5-stage pipeline and a clock cycle of 10 nanoseconds. Processor M-7 uses a 7-stage pipeline and a clock cycle of 7.5 nanoseconds. Which of the following is (are) true?
I. M-7’s pipeline has better maximum throughput than M-5’s pipeline.
II. The latency of a single instruction is shorter on M-7’s pipeline than on M-5’s pipeline.
III. Programs executing on M-7 will always run faster than programs executing on M-5.
 A. I only
 B. II only
 C. I and III
 D. II and III
Answer:


Question: Which of the following pairs of 8-bit, two's-complement numbers will result in overflow when the members of the pairs are added?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following pairs of 8-bit, two's-complement numbers will result in overflow when the members of the pairs are added?
 A. 11111111, 00000001
 B. 00000001, 10000000
 C. 11111111, 10000001
 D. 10000001, 10101010
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Which of the following pairs of 8-bit, two's-complement numbers will result in overflow when the members of the pairs are added?
 A. 11111111, 00000001
 B. 00000001, 10000000
 C. 11111111, 10000001
 D. 10000001, 10101010
Answer:


Question: Which of the following pairs of 8-bit, two's-complement numbers will result in overflow when the members of the pairs are added?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following pairs of 8-bit, two's-complement numbers will result in overflow when the members of the pairs are added?
 A. 11111111, 00000001
 B. 00000001, 10000000
 C. 11111111, 10000001
 D. 10000001, 10101010
Answer:


Question: Which of the following pairs of 8-bit, two's-complement numbers will result in overflow when the members of the pairs are added?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following pairs of 8-bit, two's-complement numbers will result in overflow when the members of the pairs are added?
 A. 11111111, 00000001
 B. 00000001, 10000000
 C. 11111111, 10000001
 D. 10000001, 10101010
Answer:


Question: Which of the following pairs of 8-bit, two's-complement numbers will result in overflow when the members of the pairs are added?

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Which of the following pairs of 8-bit, two's-complement numbers will result in overflow when the members of the pairs are added?
 A. 11111111, 00000001
 B. 00000001, 10000000
 C. 11111111, 10000001
 D. 10000001, 10101010
Answer:


Question: Two computers communicate with each other by sending data packets across a local area network. The size of these packets is 1,000 bytes. The network has the capacity to carry 1,000 packets per second. The CPU time required to execute the network protocol to send one packet is 10 milliseconds. The maximum rate at which one computer can send data to another is approximately

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Two computers communicate with each other by sending data packets across a local area network. The size of these packets is 1,000 bytes. The network has the capacity to carry 1,000 packets per second. The CPU time required to execute the network protocol to send one packet is 10 milliseconds. The maximum rate at which one computer can send data to another is approximately
 A. 10,000 bytes/second
 B. 25,000 bytes/ second
 C. 100,000 bytes/ second
 D. 500,000 bytes/ second
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Two computers communicate with each other by sending data packets across a local area network. The size of these packets is 1,000 bytes. The network has the capacity to carry 1,000 packets per second. The CPU time required to execute the network protocol to send one packet is 10 milliseconds. The maximum rate at which one computer can send data to another is approximately
 A. 10,000 bytes/second
 B. 25,000 bytes/ second
 C. 100,000 bytes/ second
 D. 500,000 bytes/ second
Answer:


Question: Two computers communicate with each other by sending data packets across a local area network. The size of these packets is 1,000 bytes. The network has the capacity to carry 1,000 packets per second. The CPU time required to execute the network protocol to send one packet is 10 milliseconds. The maximum rate at which one computer can send data to another is approximately

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Two computers communicate with each other by sending data packets across a local area network. The size of these packets is 1,000 bytes. The network has the capacity to carry 1,000 packets per second. The CPU time required to execute the network protocol to send one packet is 10 milliseconds. The maximum rate at which one computer can send data to another is approximately
 A. 10,000 bytes/second
 B. 25,000 bytes/ second
 C. 100,000 bytes/ second
 D. 500,000 bytes/ second
Answer:


Question: Two computers communicate with each other by sending data packets across a local area network. The size of these packets is 1,000 bytes. The network has the capacity to carry 1,000 packets per second. The CPU time required to execute the network protocol to send one packet is 10 milliseconds. The maximum rate at which one computer can send data to another is approximately

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Two computers communicate with each other by sending data packets across a local area network. The size of these packets is 1,000 bytes. The network has the capacity to carry 1,000 packets per second. The CPU time required to execute the network protocol to send one packet is 10 milliseconds. The maximum rate at which one computer can send data to another is approximately
 A. 10,000 bytes/second
 B. 25,000 bytes/ second
 C. 100,000 bytes/ second
 D. 500,000 bytes/ second
Answer:


Question: Two computers communicate with each other by sending data packets across a local area network. The size of these packets is 1,000 bytes. The network has the capacity to carry 1,000 packets per second. The CPU time required to execute the network protocol to send one packet is 10 milliseconds. The maximum rate at which one computer can send data to another is approximately

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Two computers communicate with each other by sending data packets across a local area network. The size of these packets is 1,000 bytes. The network has the capacity to carry 1,000 packets per second. The CPU time required to execute the network protocol to send one packet is 10 milliseconds. The maximum rate at which one computer can send data to another is approximately
 A. 10,000 bytes/second
 B. 25,000 bytes/ second
 C. 100,000 bytes/ second
 D. 500,000 bytes/ second
Answer:


Question:
Consider the following grammar.
S → ( S )
S → x
Which of the following statements is (are) true?
I. The grammar is ambiguous.
II. The grammar is suitable for top-down parsing.
III. The grammar is suitable for bottom-up parsing.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Consider the following grammar.
S → ( S )
S → x
Which of the following statements is (are) true?
I. The grammar is ambiguous.
II. The grammar is suitable for top-down parsing.
III. The grammar is suitable for bottom-up parsing.
 A. I only
 B. II only
 C. III only
 D. II and III only
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Consider the following grammar.
S → ( S )
S → x
Which of the following statements is (are) true?
I. The grammar is ambiguous.
II. The grammar is suitable for top-down parsing.
III. The grammar is suitable for bottom-up parsing.
 A. I only
 B. II only
 C. III only
 D. II and III only
Answer:


Question:
Consider the following grammar.
S → ( S )
S → x
Which of the following statements is (are) true?
I. The grammar is ambiguous.
II. The grammar is suitable for top-down parsing.
III. The grammar is suitable for bottom-up parsing.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Consider the following grammar.
S → ( S )
S → x
Which of the following statements is (are) true?
I. The grammar is ambiguous.
II. The grammar is suitable for top-down parsing.
III. The grammar is suitable for bottom-up parsing.
 A. I only
 B. II only
 C. III only
 D. II and III only
Answer:


Question:
Consider the following grammar.
S → ( S )
S → x
Which of the following statements is (are) true?
I. The grammar is ambiguous.
II. The grammar is suitable for top-down parsing.
III. The grammar is suitable for bottom-up parsing.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Consider the following grammar.
S → ( S )
S → x
Which of the following statements is (are) true?
I. The grammar is ambiguous.
II. The grammar is suitable for top-down parsing.
III. The grammar is suitable for bottom-up parsing.
 A. I only
 B. II only
 C. III only
 D. II and III only
Answer:


Question:
Consider the following grammar.
S → ( S )
S → x
Which of the following statements is (are) true?
I. The grammar is ambiguous.
II. The grammar is suitable for top-down parsing.
III. The grammar is suitable for bottom-up parsing.

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Consider the following grammar.
S → ( S )
S → x
Which of the following statements is (are) true?
I. The grammar is ambiguous.
II. The grammar is suitable for top-down parsing.
III. The grammar is suitable for bottom-up parsing.
 A. I only
 B. II only
 C. III only
 D. II and III only
Answer:


Question: Hash tables can contribute to an efficient average-case solution for all of the problems described below EXCEPT:

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Hash tables can contribute to an efficient average-case solution for all of the problems described below EXCEPT:
 A. Counting distinct values: Given a set of n keys, determine the number of distinct key values.
 B. Dynamic dictionary: Support the operations of insert, delete, and search in a dictionary.
 C. Range search: Given values a and b, find all the records whose key value is in the range a, b.
 D. Symbol table lookup: Given a program identifier, find its type and address.
Answer:

Context:
The following are multiple choice questions (with answers) about college computer science.

Question: Which of the following regular expressions is equivalent to (describes the same set of strings as) (a* + b)*(c + d)?
 A. a*(c + d)+ b(c + d)
 B. a*(c + d)* + b(c + d)*
 C. a*(c + d)+ b*(c + d)
 D. (a + b)*c +(a + b)*d
Answer: D

Question: A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations.
ADD Rs1, Rs2, Rd Add Rs1 to Rs2 and put the sum in Rd
MUL Rs1, Rs2, Rd Multiply Rs1 by Rs2 and put the product in Rd
An operation normally takes one cycle; however, an operation takes two cycles if it produces a result required by the immediately following operation in an operation sequence. Consider the expression AB + ABC + BC, where variables A, B, C are located in registers R0, R1, R2. If the contents of these three registers must not be modified, what is the minimum number of clock cycles required for an operation sequence that computes the value of AB + ABC + BC?
 A. 5
 B. 6
 C. 7
 D. 8
Answer: B

Question: The Singleton design pattern is used to guarantee that only a single instance of a class may be instantiated. Which of the following is (are) true of this design pattern?
I. The Singleton class has a static factory method to provide its instance.
II. The Singleton class can be a subclass of another class.
III. The Singleton class has a private constructor.
 A. I only
 B. II only
 C. III only
 D. I, II, and III
Answer: D

Question: A compiler generates code for the following assignment statement.
G := (A + B) * C - (D + E) * F
The target machine has a single accumulator and a single-address instruction set consisting of instructions load, store, add, subtract, and multiply. For the arithmetic operations, the left operand is taken from the accumulator and the result appears in the accumulator. The smallest possible number of instructions in the resulting code is
 A. 5
 B. 6
 C. 7
 D. 9
Answer: D

Question: Consider a computer design in which multiple processors, each with a private cache memory, share global memory using a single bus. This bus is the critical system resource. Each processor can execute one instruction every 500 nanoseconds as long as memory references are satisfied by its local cache. When a cache miss occurs, the processor is delayed for an additional 2,000 nanoseconds. During half of this additional delay, the bus is dedicated to serving the cache miss. During the other half, the processor cannot continue, but the bus is free to service requests from other processors. On average, each instruction requires 2 memory references. On average, cache misses occur on 1 percent of references. What proportion of the capacity of the bus would a single processor consume, ignoring delays due to competition from other processors?
 A. 1/50
 B. 1/27
 C. 1/25
 D. 2/27
Answer: B

Question: Hash tables can contribute to an efficient average-case solution for all of the problems described below EXCEPT:
 A. Counting distinct values: Given a set of n keys, determine the number of distinct key values.
 B. Dynamic dictionary: Support the operations of insert, delete, and search in a dictionary.
 C. Range search: Given values a and b, find all the records whose key value is in the range a, b.
 D. Symbol table lookup: Given a program identifier, find its type and address.
Answer:


Question: Hash tables can contribute to an efficient average-case solution for all of the problems described below EXCEPT:

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Hash tables can contribute to an efficient average-case solution for all of the problems described below EXCEPT:
 A. Counting distinct values: Given a set of n keys, determine the number of distinct key values.
 B. Dynamic dictionary: Support the operations of insert, delete, and search in a dictionary.
 C. Range search: Given values a and b, find all the records whose key value is in the range a, b.
 D. Symbol table lookup: Given a program identifier, find its type and address.
Answer:


Question: Hash tables can contribute to an efficient average-case solution for all of the problems described below EXCEPT:

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Hash tables can contribute to an efficient average-case solution for all of the problems described below EXCEPT:
 A. Counting distinct values: Given a set of n keys, determine the number of distinct key values.
 B. Dynamic dictionary: Support the operations of insert, delete, and search in a dictionary.
 C. Range search: Given values a and b, find all the records whose key value is in the range a, b.
 D. Symbol table lookup: Given a program identifier, find its type and address.
Answer:


Question: Hash tables can contribute to an efficient average-case solution for all of the problems described below EXCEPT:

college_computer_science

Choices:
- A
- B
- C
- D

Question:
Question: Hash tables can contribute to an efficient average-case solution for all of the problems described below EXCEPT:
 A. Counting distinct values: Given a set of n keys, determine the number of distinct key values.
 B. Dynamic dictionary: Support the operations of insert, delete, and search in a dictionary.
 C. Range search: Given values a and b, find all the records whose key value is in the range a, b.
 D. Symbol table lookup: Given a program identifier, find its type and address.
Answer: